Page 1
Smart Two Channel Highside Power Switch
Product Summary
Features
•
Overload protection
•
Current limitation
•
Short-circuit protection
•
Thermal shutdown
•
Overvoltage protection
(including load dump)
•
Fast demagnetization of inductive loads
•
Reverse battery protection
•
Undervoltage and overvoltage shutdown
with auto-restart and hysteresis
•
Open drain diagnostic output
•
Open load detection in ON-state
•
CMOS compatible input
•
Loss of ground and loss of V
•
Electrostatic discharge (ESD) protection
1
)
protection
bb
Application
•
µC compatible power switch with diagnostic feedback
for 12 V and 24 V DC grounded loads
•
All types of resistive, inductive and capacitive loads
•
Replaces electromechanical relays and discrete circuits
Overvoltage Protection
Operating voltage
active channels: one two parallel
On-state resistance
Nominal load current
Current limitation
R
ON
I
L(NOM)
I
L(SCr)
PROFET® BTS 726 L1
V
bb(AZ)
V
bb(on)
5.0 ... 34 V
60 30
4.0 6.0 A
16 16 A
43 V
m
Ω
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS technology. Fully protected by embedded protection
functions.
Pin Definitions and Functions
Pin Symbol Function
1,10,
11,12,
15,16,
19,20
3 IN1 Input 1,2, activates channel 1,2 in case of
7 IN2 logic high signal
17,18 OUT1 Output 1,2, protected high-side power output
13,14 OUT2 of channel 1,2. Design the wiring for the max.
4 ST1 Diagnostic feedback 1,2 of channel 1,2,
8 ST2 open drain, low on failure
2 GND1 Ground 1 of chip 1 (channel 1)
6 GND2 Ground 2 of chip 2 (channel 2)
5,9 N.C. Not Connected
V
bb
Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
short circuit current
Pin configuration
Vbb1
GND1 2 19 V
IN1 3 18 OUT1
ST1 4 17 OUT1
N.C. 5 16 V
GND2 6 15 V
IN2 7 14 OUT2
ST2 8 13 OUT2
N.C. 9 12 V
Vbb10 11 V
•
(top view)
20 V
bb
bb
bb
bb
bb
bb
)
1
With external current limit (e.g. resistor R
connection, reverse load current limited by connected load.
=150 Ω) in GND connection, resistor in series with ST
GND
Semiconductor Group 1 06.96
Page 2
Block diagram
Two Channels; Open Load detection in on state;
3
4
1
Signal GND
Chip 1
IN1
ST1
GND1
ESD
Voltage
source
V
Logic
Voltage
sensor
Logic
Overvoltage
protection
Charge pump
Level shifter
Rectifier
Chip 1
Current
limit
unclamped
ind. loads
Open load
detection
Gate
protection
Limit for
Temperature
sensor
R
O1
GND1
BTS 726 L1
+ V
bb
Leadframe
OUT1
17,18
Load GND
Load
7
8
6
Signal GND
Chip 2
Logic and protection circuit of chip 2
(equivalent to chip 1)
IN2
ST2
GND2
Chip 2
PROFET
Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20
R
O2
GND2
+ V
Leadframe
bb
OUT2
13,14
Load
Load GND
Maximum Ratings
at
= 25°C unless otherwise specified
j
T
Parameter Symbol Values Unit
Supply voltage (overvoltage protection see page 4)
Supply voltage for full short circuit protection
T
= -40 ...+150°C
j,start
V
V
bb
bb
43 V
34 V
Semiconductor Group 2
Page 3
BTS 726 L1
)
at
T
Maximum Ratings
Parameter Symbol Values Unit
= 25°C unless otherwise specified
j
Load current (Short-circuit current, see page 5)
)
Load dump protection
)
3
R
= 2 Ω,
I
t
= 200 ms; IN = low or high,
d
each channel loaded with
2
V
LoadDump
R
= 3.4 Ω,
L
=
U
+
V
,
U
s
= 13.5 V
A
A
Operating temperature range
Storage temperature range
Power dissipation (DC)
(all channels active)
5
T
= 25°C:
a
T
= 85°C:
a
Inductive load switch-off energy dissipation, single pulse
V
= 12V,
bb
I
= 4.0 A, Z
L
I
= 6.0 A, Z
L
see diagrams on page 9 and page 10
T
= 150°C5),
j,start
= 50 mH, 0 Ω one channel:
L
= 42 mH, 0 Ω two parallel channels:
L
Electrostatic discharge capability (ESD
(Human Body Model)
Input voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagram page 8
I
L
V
Load dump
T
j
T
stg
P
tot
E
AS
V
ESD
V
IN
I
IN
I
ST
self-limited A
)
4
-40 ...+150
60 V
°C
-55 ...+150
3.7
W
1.9
0.5
J
1.0
1.0 kV
-10 ... +16 V
±2.0
mA
±5.0
Thermal resistance
junction - soldering point
junction - ambient
5)
5),6)
each channel:
one channel active:
R
R
thjs
thja
all channels active:
)
2
Supply voltages higher than V
150 Ω resistor in the GND connection and a 15 kΩ resistor in series with the status pin. A resistor for input
protection is integrated.
3)
R
= internal resistance of the load dump test pulse generator
I
4)
V
Load dump
)
5
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
connection. PCB is vertical without blown air. See page 15
)
6
Soldering point: upper side of solder edge of device pin 15. See page 15
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
require an external current limit for the GND and status pins, e.g. with a
bb(AZ)
2
(one layer, 70µm thick) copper area for V
12 K/W
41
34
bb
Semiconductor Group 3
Page 4
Electrical Characteristics
BTS 726 L1
Parameter and Conditions,
at Tj = 25 °C,
V
= 12 V unless otherwise specified
bb
each of the two channels
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT)
IL = 2 A each channel,
two parallel channels,
T
= 25°C:
j
T
= 150°C:
j
T
= 25°C:
j
Nominal load current one channel active:
two parallel channels active:
Device on PCB5),
T
= 85°C,
a
T
≤ 150°C
j
Output current while GND disconnected or pulled
up; V
= 30 V,
bb
Turn-on time to 90%
Turn-off time to 10%
R
= 12 Ω
L
T
,
V
= 0, see diagram page 9
IN
=-40...+150°C
j
V
V
OUT
OUT
:
:
Slew rate on
10 to 30%
V
OUT
R
,
= 12 Ω
L
T
,
=-40...+150°C:
j
Slew rate off
70 to 40%
V
OUT
,
R
L
= 12 Ω
T
,
=-40...+150°C:
j
Symbol Values Unit
min typ max
R
ON
I
L(NOM)
I
L(GNDhigh)
t
on
t
off
dV/dt
on
-dV/dt
off
--
50
100
120
25
3.6
5.5
4.0
6.0
-- -- 10 mA
80
80
200
230
400
450
0.1 -- 1 V/µs
0.1 -- 1 V/µs
mΩ
60
30
-- A
µs
Operating Parameters
)
Operating voltage
7
Undervoltage shutdown
Undervoltage restart
T
=-40...+150°C:
j
T
=-40...+150°C:
j
T
Undervoltage restart of charge pump
see diagram page 14
T
=-40...+150°C:
j
Undervoltage hysteresis
V
∆
bb(under)
Overvoltage shutdown
Overvoltage restart
Overvoltage hysteresis
Overvoltage protection
I
= 40 mA
bb
=
V
bb(u rst)
-
V
bb(under)
)
8
T
=-40...+150°C:
j
T
=-40...+150°C:
j
T
=-40...+150°C: ∆
j
T
=-40...+150°C:
j
Standby current, all channels off
V
= 0
IN
7)
At supply voltage increase up to
8)
see also
V
ON(CL)
in circuit diagram on page 8.
V
= 5.6 V typ without charge pump,
bb
=-40...+25°C:
j
T
=+150°C:
j
T
=25°C
j
T
=150°C:
j
:
V
bb(on)
V
bb(under)
V
bb(u rst)
V
bb(ucp)
V
∆
bb(under)
V
bb(over)
V
bb(o rst)
V
bb(over)
V
bb(AZ)
I
bb(off)
V
5.0 --
3.5 --
-- -- 5.0
-- 5.6 7.0 V
-- 0.2 -- V
34 -33 -- -- V
-- 0.5 -- V
42 47 -- V
OUT
--
--
≈
V
bb
20
29
- 2 V
34 V
5.0 V
7.0
43 V
50
µA
56
V
Semiconductor Group 4
Page 5
BTS 726 L1
)
j
Parameter and Conditions,
at Tj = 25 °C,
V
= 12 V unless otherwise specified
bb
Leakage output current (included in
= 0
=
I
GND1
+
I
GND2
V
IN
,
IN
V
Operating current 9),
I
GND
each of the two channels
I
bb(off
= 5V,
=-40...+150°C
T
one channel on:
two channels on:
Protection Functions
Initial peak short circuit current limit,
diagrams, page 12)
each channel,
(see timing
two parallel channels
Repetitive short circuit current limit,
T
=
T
each channel
j
jt
two parallel channels
(see timing diagrams, page 12)
Initial short circuit shutdown time
T
T
(see page 11 and timing diagrams on page 12)
Output clamp (inductive load switch off)
at V
ON(CL)
= Vbb - V
OUT
Thermal overload trip temperature
Thermal hysteresis
)
=-40°C:
j
T
=25°C:
j
T
=+150°C:
j
T
=-40°C:
j,start
= 25°C:
j,start
10)
Symbol Values Unit
min typ max
I
L(off)
I
GND
I
L(SCp)
-- -- 12
--
--
21
15
11
1.8
3.6
32
25
17
µ
3.57mA
43
35
24
twice the current of one channel
I
L(SCr)
t
off(SC)
V
ON(CL)
T
jt
∆T
jt
--
--
--
--
16
16
--
--
5
----ms
4
-- 47 -- V
150 -- -- °C
-- 10 -- K
A
A
A
Reverse Battery
)
Reverse battery voltage
Drain-source diode voltage
= - 4.0 A,
L
I
)
9
Add
10
11
)
)
I
If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
V
ON(CL)
Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 3 and circuit page 8).
ST
, if
j
T
I
ST
= +150°C
> 0
11
(V
out
> Vbb)
-
V
bb
-
V
ON
-- -- 32 V
-- 610 -- mV
Semiconductor Group 5
Page 6
BTS 726 L1
Parameter and Conditions,
at Tj = 25 °C,
V
= 12 V unless otherwise specified
bb
each of the two channels
Diagnostic Characteristics
Open load detection current,
(on-condition)
each channel,
T
= -40°C:
j
T
= 25°C:
j
T
= 150°C:
j
two parallel channels
)
Open load detection voltage
12
T
=-40..+150°C:
j
Internal output pull down
T
(OUT to GND), V
OUT
= 5 V
Input and Status Feedback
13
=-40..+150°C:
j
)
Input resistance
(see circuit page 8)
T
=-40..+150°C:
j
Input turn-on threshold voltage
T
=-40..+150°C:
j
Input turn-off threshold voltage
T
=-40..+150°C:
j
Input threshold hysteresis
Off state input current
T
=-40..+150°C:
j
On state input current
T
=-40..+150°C:
j
V
= 0.4 V:
IN
V
IN
= 5 V:
Delay time for status with open load after switch
off
(see timing diagrams, page 13
),
T
=-40..+150°C:
j
Status invalid after positive input slope
(open load)
T
=-40..+150°C:
j
Status output (open drain)
Zener limit voltage
ST low voltage
T
=-40...+150°C,
j
T
=-40...+25°C,
j
T
= +150°C,
j
I
= +1.6 mA:
ST
I
= +1.6 mA:
ST
I
= +1.6 mA:
ST
Symbol Values Unit
min typ max
I
L (OL)
1
20
20
20
--
850
--
750
--
750
mA
twice the current of one channel
V
OUT(OL)
R
O
R
I
V
IN(T+)
V
IN(T-)
∆
V
IN(T)
I
IN(off)
I
IN(on)
t
d(ST OL4)
t
d(ST)
V
ST(high)
V
ST(low)
234V
41030k
2.5 3.5 6 k
1.7 -- 3.5 V
1.5 -- -- V
-- 0.5 -- V
1--50
20 50 90
µ
µ
100 520 1000
-- 250 600
5.4
--
--
6.1
--
--
--
0.4
0.6
Ω
Ω
A
A
µ
s
µ
s
V
12)
External pull up resistor required for open load detection in off state.
13)
If ground resistors R
are used, add the voltage drop across these resistors.
GND
Semiconductor Group 6
Page 7
Truth Table
Cannel 1 Input 1 Output 1 Status 1
Cannel 2 Input 2 Output 2 Status 2
BTS 726 L1
level level
Normal
operation
Open load L
Short circuit
to V
bb
Overtemperature
Undervoltage
Overvoltage L
L
H
L
H
Z
H
L
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
BTS 726L1
H
H
14
)
H (L
)
L
15
)
L
16
)
H (L
)
H
L
H
H
H
H
L = "Low" Level X = don't care Z = high impedance, potential depends on external circuit
H = "High" Level Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. The
status outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
I
bb
V
bb
I
IN1
IN1
3
I
ST1
ST1
V
4
ST1
R
V
IN1
PROFET
GND1
Leadframe
V
bb
Chip 1
GND1
2
I
GND1
OUT1
I
L1
17,18
V
V
OUT1
ON1
PROFET
GND2
Leadframe
V
bb
Chip 2
GND2
6
I
GND2
OUT2
I
L2
13,14
I
IN2
IN2
7
I
ST2
ST2
V
8
ST2
R
V
IN2
Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20
External R
optional; two resistors R
GND
GND1
, R
= 150 Ω or a single resistor R
GND2
= 75 Ω for reverse
GND
battery protection up to the max. operating voltage.
)
14
With external resistor between output and V
15)
An external short of output to Vbb in the off state causes an internal current from output to ground. If R
used, an offset voltage at the GND and ST pins will occur and the V
)
16
Low resistance to
V
may be detected by no-load-detection
bb
bb
signal may be errorious.
ST low
V
V
OUT2
ON2
GND
is
Semiconductor Group 7
Page 8
BTS 726 L1
I
I
IN1 or IN2
Input circuit (ESD protection),
R
IN
I
ESD-ZD
I
GND
ESD zener diodes are not to be used as voltage clamp at
DC conditions. Operation in this mode may result in a drift of
the zener voltage (increase of up to 1 V).
Status output,
ST1 or ST2
R
ST(ON)
GND
+5V
ST
ESDZD
Overvoltage protection of logic part
GND1 or GND2
V
Z2
PROFET
GND
R
GND
Signal GND
,
R
V
= 6.1 V typ., V
Z1
= 150
R
GND
R
I
IN
Logic
ST
ST
V
Z1
= 47 V typ., RI = 3.5 kΩ typ.
Z2
, R
Ω
= 15 kΩ nominal.
ST
Reverse battery protection
+ 5V
+ V
-
bb
V
bb
ESD-Zener diode: 6.1 V typ., max 5.0 mA; R
ST(ON)
< 380
Ω
at 1.6 mA, ESD zener diodes are not to be used as voltage
clamp at DC conditions. Operation in this mode may result in
a drift of
the zener voltage (increase of up to 1 V).
Inductive and overvoltage output clamp,
OUT1 or OUT2
+V
bb
V
Z
V
ON
OUT
PROFET
Power GND
clamped to
V
ON
V
ON(CL)
= 47 V typ.
R
ST
R
I
R
GND
= 150 Ω,
IN
ST
= 3.5 kΩ typ
R
I
Logic
GND
R
GND
Signal GND
,
Power
Inverse
Diode
Power GND
R
OUT
L
Temperature protection is not active during inverse current
operation.
Semiconductor Group 8
Page 9
BTS 726 L1
Open-load detection,
OUT1 or OUT2
ON-state diagnostic condition:
I
V
< R
ON
ON
Logic
unit
·
L(OL)
ON
; IN high
Open load
detection
OFF-state diagnostic condition:
V
> 3 V typ.; IN low
OUT
GND disconnect with GND pull up
V
PROFET
V
>
GND
IN
bb
V
-
GND
V
IN(T+)
OUT
device stays off
+ V
V
OUT
bb
ON
V
bb
Any kind of load. If V
Due to V
> 0, no VST = low signal available.
GND
IN
ST
V
V
ST
IN
GND
Vbb disconnect with energized inductive
load
R
EXT
high
IN
V
bb
OFF
Logic
unit
Open load
detection
GND disconnect
IN
ST
VbbV
IN
V
ST
Signal GND
V
bb
PROFET
GND
V
GND
OUT
PROFET
V
OUT
R
O
V
bb
ST
GND
For an inductive load current up to the limit defined by E
OUT
AS
(max. ratings see page 3 and diagram on page 10) each
switch is protected against loss of Vbb.
Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load the whole load
current flows through the GND connection.
Any kind of load. In case of IN = high is
Due to V
>
0, no VST = low signal available.
GND
V
OUT
V
V
≈
-
IN
IN(T+)
Semiconductor Group 9
.
Page 10
Inductive load switch-off energy
dissipation
E
bb
E
AS
V
IN
bb
E
BTS 726 L1
Load
PROFET
=
ST
GND
OUT
L
Z
L
{
R
L
Energy stored in load inductance:
/
2
·L·
2
I
L
1
E
=
L
While demagnetizing load inductance, the energy
dissipated in PROFET is
E
= Ebb + EL - ER= ∫ V
AS
with an approximate solution for R
·
I
L
L
=
(
V
+ |V
OUT(CL)
bb
·
R
2
L
|)
E
AS
ON(CL)
>
L
ln
(1+
0
·
iL(t) dt,
Ω
:
|V
OUT(CL)
·
I
R
L
L
|
Maximum allowable load inductance for
a single switch off
L = f (IL );
T
j,start
150°C, V
=
(one channel)
bb
5)
= 12 V, RL = 0
Ω
E
L
E
R
)
L [mH]
1000
100
10
1
23456789101112
I
[A]
L
Semiconductor Group 10
Page 11
BTS 726 L1
Typ. on-state resistance
RON = f (Vbb,Tj )
[mOhm]
R
ON
150
125
100
75
50
25
0
0 10203040
= 2 A, IN = high
; I
L
T
= 150°C
j
85°C
25°C
-40°
Typ. standby current
I
I
= f (Tj )
bb(off)
[µA]
bb(off)
40
35
30
25
20
15
10
5
0
-50 0 50 100 150 200
= 9...34 V, IN1,2 = low
; V
bb
Typ. open load detection current
I
L(OL)
I
L(OL)
500
450
400
350
300
250
200
150
100
50
= f (Vbb,Tj );
[mA]
V
< 6
bb
for V
no load detection not specified
IN
= high
-40°C
25°C
85°C
Tj = 150°C
Vbb [V]
Tj [°C]
Typ. initial short circuit shutdown time
t
t
off(SC)
off(SC)
6
5
4
3
2
1
= f (T
[msec]
j,start
)
; V
bb
=12 V
0
0102030
Vbb [V]
Semiconductor Group 11
0
-50 0 50 100 150 200
T
[°C]
j,start
Page 12
BTS 726 L1
Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and
channel 2
Figure 1a: V
turn on:
bb
IN1
IN2
V
bb
V
OUT1
V
OUT2
ST open drain
Figure 2a: Switching a lamp:
IN
Figure 2b: Switching an inductive load
IN
t
ST
V
OUT
I
L
I
L(OL)
d(ST)
*)
t
*) if the time constant of load is too large, open-load-status may
occur
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
IN1
other channel: normal operation
t
ST
V
OUT
I
L
t
The initial peak current should be limited by the lamp and not by
the initial short circuit current I
= 25 A typ. of the device.
L(SCp)
Semiconductor Group 12
I
L1
I
L(SCp)
I
L(SCr)
t
off(SC)
ST
t
Heating up of the chip may require several milliseconds, depending
on external conditions (t
off(SC)
vs. T
see page 11)
j,start
Page 13
BTS 726 L1
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
IN1/2
I + I
L1 L2
I
L(SCp)
I
L(SCr)
t
off(SC)
ST1/2
Figure 5a: Open load: detection in ON-state, turn
on/off to open load
IN
t
ST
d(ST)
V
OUT
I
L
open
t
t
d(ST OL4)
t
ST1 and ST2 have to be configured as a 'Wired OR' function
ST1/2 with a single pull-up resistor.
Figure 4a: Overtemperature:
T
Reset if
T
<
j
jt
IN
ST
V
OUT
T
J
The status delay time t
failure modes "open load in ON-state" and "overtemperature".
d(STOL4)
allows to distinguish between the
Figure 5b: Open load: detection in ON-state, open
load occurs in on-state
IN
ST
V
I
OUT
L
t
d(ST OL1)
normal
open
t
d(ST OL2)
normal
t
Semiconductor Group 13
t
d(ST OL1)
= 20 µs typ., t
d(ST OL2)
t
= 10 µs typ
Page 14
BTS 726 L1
V
V
V
V
Figure 5c: Open load: detection in ON- and OFF-state
(with R
), turn on/off to open load
EXT
IN
ST
V
OUT
t
d(ST)
I
L
open
t
Figure 6b: Undervoltage restart of charge pump
V
V
on
off-state
bb(u rst)
bb(u cp)
bb(under)
IN = high, normal load conditions.
Charge pump starts at V
bb(ucp)
= 5.6 V typ.
V
on-state
bb(o rst)
ON(CL)
bb(over)
off-state
V
bb
Figure 6a: Undervoltage:
IN
V
bb
V
OUT
ST
V
bb(under)
V
bb(u rst)
Figure 7a: Overvoltage:
IN
V
bb
V
OUT
ST
t
V
ON(CL)
V
bb(over)
V
bb(o rst)
t
Semiconductor Group 14
Page 15
Package and Ordering Code
BTS 726 L1
Standard P-DSO-20-9
BTS726L1 Q67060-S7003-A2
All dimensions in millimetres
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Definition of soldering point with temperature Ts:
upper side of solder edge of device pin 15.
Ordering Code
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer
70µm, 6cm
max. power dissipation P
I
L(NOM)
2
active heatsink area) as a reference for
, nominal load current
and thermal resistance R
tot
thja
Semiconductor Group 15
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