Datasheet BTS725L1 Datasheet (Siemens)

PROFET® Preliminary BTS 725 L1

Smart Two Channel Highside Power Switch

Product Summary

Features

•

Overload protection

•

Current limitation

•

Short-circuit protection

•

Thermal shutdown

•

Overvoltage protection

(including load dump)

•

Reverse battery protection

•

Undervoltage and overvoltage shutdown

with auto-restart and hysteresis

•

Open drain diagnostic output

•

Open load detection in ON-state

•

CMOS compatible input

•

Loss of ground and loss of V

•

Electrostatic discharge (ESD) protection

1

)

protection

bb

Application

•

µC compatible power switch with diagnostic feedback

for 12 V DC grounded loads

•

Most suitable for resistive and lamp loads

•

Replaces electromechanical relays and discrete circuits

Overvoltage Protection Operating voltage

active channels: one two parallel On-state resistance Nominal load current Current limitation

R

ON

I

L(NOM)

I

L(SCr)

V

bb(AZ)

V

bb(on)

5.0 ... 24 V

43 V

60 30

4.0 6.0 A 17 17 A

m

Ω

General Description

N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, monolithically integrated in Smart SIPMOS technology. Fully protected by embedded protection functions.

Pin Definitions and Functions

Pin Symbol Function

1,10, 11,12, 15,16, 19,20 3 IN1 Input 1,2, activates channel 1,2 in case of 7 IN2 logic high signal 17,18 OUT1 Output 1,2, protected high-side power output 13,14 OUT2 of channel 1,2. Design the wiring for the max.

4 ST1 Diagnostic feedback 1,2 of channel 1,2, 8 ST2 open drain, low on failure 2 GND1 Ground 1 of chip 1 (channel 1) 6 GND2 Ground 2 of chip 2 (channel 2) 5,9 N.C. Not Connected

V

bb

Positive power supply voltage. Design the

wiring for the simultaneous max. short circuit currents from channel 1 to 2 and also for low thermal resistance

short circuit current

Pin configuration

Vbb1

GND1 2 19 V

IN1 3 18 OUT1

ST1 4 17 OUT1

N.C. 5 16 V

GND2 6 15 V

IN2 7 14 OUT2

ST2 8 13 OUT2

N.C. 9 12 V

Vbb10 11 V

•

(top view)

20 V

bb bb

)

1

With external current limit (e.g. resistor R connection, reverse load current limited by connected load.

=150 Ω) in GND connection, resistor in series with ST

GND

Semiconductor Group 1 03.96

Block diagram

Two Channels; Open Load detection in on state;

Voltage

source

V

Logic

Voltage

Overvoltage

protection

Charge pump

Current

limit

Gate

protection

Preliminary BTS 725 L1

+ V

bb

Leadframe

OUT1

17,18

3

4

1

Signal GND

Chip 1

7

IN1

ST1

GND1

IN2

ESD

sensor

Logic

Level shifter

Rectifier

Open load

detection

Chip 1

Logic and protection circuit of chip 2

(equivalent to chip 1)

Temperature

sensor

R

O1

GND1

+ V

Leadframe

bb

OUT2

13,14

Load

Load GND

Load

ST2

8

R

O2

GND2

6

GND2

Load GND

Signal GND

Chip 2

PROFET



Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20

Maximum Ratings

at

= 25°C unless otherwise specified

j

T

Parameter Symbol Values Unit

Supply voltage (overvoltage protection see page 4) Supply voltage for full short circuit protection

T

= -40 ...+150°C

j,start

V V

bb bb

43 V 24 V

Semiconductor Group 2

Preliminary BTS 725 L1

)

at

T

Maximum Ratings Parameter Symbol Values Unit

= 25°C unless otherwise specified

j

Load current (Short-circuit current, see page 5)

)

Load dump protection

)

3

R

= 2 Ω,

I

t

= 200 ms; IN = low or high,

d

each channel loaded with

2

V

LoadDump

R

= 3.4 Ω,

L

=

U

+

V

,

A

U

s

Operating temperature range Storage temperature range Power dissipation (DC) (all channels active)

5

T T

Electrostatic discharge capability (ESD (Human Body Model)

Input voltage (DC) Current through input pin (DC) Current through status pin (DC)

see internal circuit diagram page 8

Thermal resistance junction - soldering point junction - ambient

5)

5),6)

each channel:

one channel active:

all channels active:

= 13.5 V

A

= 25°C:

a

= 85°C:

a

I

L

V

Load dump

T

j

T

stg

P

tot

V

ESD

V

IN

I

IN

I

ST

R

thjs

R

thja

self-limited A

)

4

-40 ...+150

60 V

°C

-55 ...+150

3.7

W

1.9

1.0 kV

-10 ... +16 V ±2.0

mA

±5.0

12 K/W 41 34

Electrical Characteristics

Parameter and Conditions,

at Tj = 25 °C,

V

= 12 V unless otherwise specified

bb

Load Switching Capabilities and Characteristics

On-state resistance (Vbb to OUT) IL = 2 A each channel,

two parallel channels,

)

2

Supply voltages higher than V 150 Ω resistor in the GND connection and a 15 kΩ resistor in series with the status pin. A resistor for input protection is integrated.

3)

R

= internal resistance of the load dump test pulse generator

I

4)

V

Load dump

)

5

Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm connection. PCB is vertical without blown air. See page 14

)

6

Soldering point: upper side of solder edge of device pin 15. See page 14

is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839

each of the two channels

Symbol Values Unit

min typ max

T

= 25°C:

j

T

= 150°C:

j

T

= 25°C:

j

require an external current limit for the GND and status pins, e.g. with a

bb(AZ)

R

ON

2

(one layer, 70µm thick) copper area for V

--

50

100

25

120

60

30

mΩ

bb

Semiconductor Group 3

Preliminary BTS 725 L1

)

j

Parameter and Conditions,

at Tj = 25 °C,

V

= 12 V unless otherwise specified

bb

each of the two channels

Nominal load current one channel active:

two parallel channels active:

Device on PCB5),

T

= 85°C,

a

T

≤ 150°C

j

Output current while GND disconnected or pulled

up; V

Turn-on time Turn-off time to 10%

R

= 12

L

= 30 V,

bb

Ω

,

V

= 0, see diagram page 9

IN

T

=-40...+150°C

j

to 90%

V V

OUT OUT

Slew rate on 10 to 30%

V

OUT

R

= 12

,

L

Ω

,

T

=-40...+150°C:

j

Slew rate off 70 to 40%

V

OUT

,

R

= 12

L

Ω

,

T

=-40...+150°C:

j

Operating Parameters

)

Operating voltage Undervoltage shutdown Undervoltage restart

7

T

=-40...+150°C:

j

T

=-40...+150°C:

j

T

=-40...+150°C:

j

Undervoltage restart of charge pump see diagram page 13

T

=-40...+150°C:

j

Undervoltage hysteresis

V

∆

bb(under)

Overvoltage shutdown Overvoltage restart Overvoltage hysteresis Overvoltage protection

I

= 40 mA

bb

Standby current, all channels off V

= 0

IN

Leakage output current (included in

IN

V

Operating current 9),

I

GND

= 0

=

I

GND1

=

V

+

bb(u rst)

I

GND2

-

V

,

V

8

IN

bb(under)

)

= 5V,

T

=-40...+150°C:

j

T

=-40...+150°C:

j

T

=-40...+150°C:

j

T

=-40...+150°C:

j

T

j

I

bb(off

=-40...+150°C

T

one channel on:

=25°C

j

=150°C:

)

two channels on:

Symbol Values Unit

min typ max

: :

:

I

t t

dV/dt

-dV/dt

V V V V

∆

V V

∆

V

I

L(NOM)

L(GNDhigh)

on off

on

off

bb(on) bb(under) bb(u rst) bb(ucp)

V

bb(under)

bb(over) bb(o rst)

V

bb(over)

bb(AZ)

bb(off)

L(off)

GND

3.6

5.5

4.0

6.0

-- -- 10 mA

80 80

200 230

400 450

0.1 -- 1 V/µs

5.0 --

3.5 --

24 V

5.0 V

-- -- 5.0 V

-- 5.6 7.0 V

-- 0.2 -- V

24 --

34 V

23 -- -- V

-- 0.5 -- V

42 47 -- V

--

20 29

50 56

-- -- 12

--

1.8

3.6

3.57mA

-- A

µ

s

A

7)

At supply voltage increase up to

8)

)

9

see also Add

V

I

, if

ST

in circuit diagram on page 8.

ON(CL)

I

> 0

ST

V

= 5.6 V typ without charge pump,

bb

Semiconductor Group 4

V

OUT

≈

V

- 2 V

bb

Preliminary BTS 725 L1

Parameter and Conditions,

at Tj = 25 °C,

V

= 12 V unless otherwise specified

bb

each of the two channels

Protection Functions

Initial peak short circuit current limit,

diagrams, page 11)

each channel,

(see timing

two parallel channels

Repetitive short circuit current limit,

T

=

T

each channel

j

jt

two parallel channels

(see timing diagrams, page 11)

Initial short circuit shutdown time

T T

(see page 10 and timing diagrams on page 11)

Thermal overload trip temperature Thermal hysteresis

=-40°C:

j

T

=25°C:

j

T

=+150°C:

j

T

=-40°C:

j,start

= 25°C:

j,start

Symbol Values Unit

min typ max

I

L(SCp)

27 20 12

37 30 18

47 40 25

twice the current of one channel

I

L(SCr)

t

off(SC)

T

jt

∆T

jt

--

17 17

--

5

----ms

4

150 -- -- °C

-- 10 -- K

A

Reverse Battery

)

Reverse battery voltage Drain-source diode voltage

= - 4.0 A,

L

I

j

= +150°C

T

10

(V

out

> Vbb)

-

V

bb

-

V

ON

-- -- 32 V

-- 610 -- mV

Diagnostic Characteristics

Open load detection current,

Open load detection voltage

(on-condition)

each channel,

T

two parallel channels

)

11

=-40..+150°C:

T

j

= -40°C:

T

j

= 25°C:

T

j

= +150°C:

j

I

L (OL)

V

OUT(OL)

4

10 10 10

--

800

--

600

--

600

twice the current of one channel

234V

Internal output pull down

(OUT to GND), V

)

10

Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature protection is not active during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and circuit page 8).

11)

External pull up resistor required for open load detection in off state.

OUT

= 5 V

=-40..+150°C:

T

j

R

O

41030k

mA

Ω

Semiconductor Group 5

Preliminary BTS 725 L1

Parameter and Conditions,

at Tj = 25 °C,

V

= 12 V unless otherwise specified

bb

Input and Status Feedback

each of the two channels

)

12

Input resistance

(see circuit page 8)

T

=-40..+150°C:

j

Input turn-on threshold voltage

T

=-40..+150°C:

j

Input turn-off threshold voltage

T

=-40..+150°C:

j

Input threshold hysteresis Off state input current

T

=-40..+150°C:

j

On state input current

T

=-40..+150°C:

j

V

= 0.4 V:

IN

V

IN

= 5 V:

Delay time for status with open load after switch off

(see timing diagrams, page 12

),

T

=-40..+150°C:

j

Status invalid after positive input slope (open load)

T

=-40..+150°C:

j

Status output (open drain)

Zener limit voltage ST low voltage

T

=-40...+150°C,

j

T

=-40...+25°C,

j

T

= +150°C,

j

I

= +1.6 mA:

ST

I

= +1.6 mA:

ST

I

= +1.6 mA:

ST

Symbol Values Unit

min typ max

R

I

V

IN(T+)

V

IN(T-)

∆

V

IN(T)

I

IN(off)

I

IN(on)

t

d(ST OL4)

t

d(ST)

V

ST(high)

V

ST(low)

2.5 3.5 6 k

1.7 -- 3.5 V

1.5 -- -- V

-- 0.5 -- V 1--50

20 50 90

µ µ

100 520 1000

-- 250 600

5.4

--

6.1

--

0.4

0.6

Ω

A A

µ

s

µ

s

V

12)

If ground resistors R

are used, add the voltage drop across these resistors.

GND

Semiconductor Group 6

Truth Table

Cannel 1 Input 1 Output 1 Status 1 Cannel 2 Input 2 Output 2 Status 2

Preliminary BTS 725 L1

level level

Normal operation Open load L

Short circuit to V

bb

Overtemperature Undervoltage Overvoltage L

L

H

L H Z

H

L

H

L

H

L

H

H H H L L L L L

H

L

BTS 725L1

H H

13

)

H (L

)

L

14

)

L

15

)

H (L

) H L H H H H

L = "Low" Level X = don't care Z = high impedance, potential depends on external circuit H = "High" Level Status signal valid after the time delay shown in the timing diagrams

Parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. The status outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor.

Terms

I

bb

V

bb

I

IN1

3

I

ST1

V

4

ST1

R

V

IN1

PROFET

GND1

Leadframe

V

bb

Chip 1

GND1

2

I

GND1

OUT1

I

L1

17,18

V

OUT1

ON1

PROFET

GND2

Leadframe

V

bb

Chip 2

GND2

6

I

GND2

OUT2

I

L2

13,14

I

IN2

7

I

ST2

V

8

ST2

R

V

IN2

Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20

Ω

External R

optional; two resistors R

GND

GND1

, R

GND2

= 150

or a single resistor R

= 75 Ω for reverse

GND

battery protection up to the max. operating voltage.

)

13

With external resistor between output and V

14)

An external short of output to Vbb in the off state causes an internal current from output to ground. If R used, an offset voltage at the GND and ST pins will occur and the V

)

15

Low resistance to

V

may be detected by no-load-detection

bb

signal may be errorious.

ST low

V

OUT2

ON2

GND

is

Semiconductor Group 7

Preliminary BTS 725 L1

I

IN1 or IN2

Input circuit (ESD protection),

R

IN

I

ESD-ZD

I

GND

ESD zener diodes are not to be used as voltage clamp at DC conditions. Operation in this mode may result in a drift of the zener voltage (increase of up to 1 V).

Status output,

ST1 or ST2

R

ST(ON)

GND

+5V

ST

ESDZD

Overvoltage protection of logic part

GND1 or GND2

V

Z2

PROFET

GND

R

GND

Signal GND

,

R

V

= 6.1 V typ., V

Z1

= 150

R

GND

R

I

IN

Logic

ST

V

Z1

= 47 V typ., RI = 3.5 kΩ typ.

Z2

, R

Ω

= 15 kΩ nominal.

ST

Reverse battery protection

+ 5V

+ V

-

bb

V

bb

ESD-Zener diode: 6.1 V typ., max 5.0 mA; R

ST(ON)

< 380

Ω

at 1.6 mA, ESD zener diodes are not to be used as voltage clamp at DC conditions. Operation in this mode may result in a drift of

overvoltage output clamp,

the zener voltage (increase of up to 1 V).

OUT1 or OUT2

+V

V

Z

bb

V

ON

OUT

PROFET

Power GND

clamped to

V

ON

V

ON(CL)

= 47 V typ.

R

ST

R

I

R

GND

= 150 Ω,

IN

ST

= 3.5 kΩ typ

R

I

Logic

GND

R

GND

Signal GND

,

Power Inverse Diode

Power GND

R

OUT

L

Temperature protection is not active during inverse current operation.

Semiconductor Group 8

Preliminary BTS 725 L1

Open-load detection,

OUT1 or OUT2

ON-state diagnostic condition:

I

V

< R

ON

Logic

unit

·

L(OL)

ON

; IN high

Open load

detection

OFF-state diagnostic condition:

V

> 3 V typ.; IN low

OUT

GND disconnect with GND pull up

V

bb

PROFET

GND

V

OUT

GND

V

-

IN

V

IN

ST

V

ST

device stays off

IN(T+)

+ V

bb

V

ON

OUT

R

EXT

V

bb

If V

GND

Due to V

V

>

IN

> 0, no VST = low signal available.

GND

OFF

Logic

unit

Open load

detection

GND disconnect

IN

ST

VbbV

IN

V

ST

Signal GND

V

bb

PROFET

GND

V

GND

OUT

V

OUT

R

O

In case of IN = high is no V

= low signal available.

ST

V

OUT

V

≈

-

IN

IN(T+)

. Due to V

GND

>

0,

Semiconductor Group 9

Preliminary BTS 725 L1

Typ. on-state resistance

RON = f (Vbb,Tj )

[mOhm]

R

ON

150

125

100

75

50

25

0

0102030

= 2 A, IN = high

; I

L

Tj = 150°C

85°C

25°C

-40°

Vbb [V]

Typ. standby current

I

= f (Tj )

bb(off)

[µA]

I

bb(off)

40

35

30

25

20

15

10

5

0

-50 0 50 100 150 200

= 9...24 V, IN1,2 = low

; V

bb

Tj [°C]

Typ. open load detection current

I

= f (Vbb,Tj );

L(OL)

[mA]

I

L(OL)

500

450

400

350 300

250

200

150

100

50

0

0 5 10 15 20 25

V 6 <

bb

for V

no load detection not specified

IN

= high

Typ. initial short circuit shutdown time

t

= f (T

off(SC)

t

[msec]

off(SC)

6

5

4

3

2

1

0

-50 0 50 100 150 200

j,start

)

; V

bb

=12 V

Vbb [V]

Semiconductor Group 10

T

j,start

[°C]

Preliminary BTS 725 L1

Timing diagrams

Both channels are symmetric and consequently the diagrams are valid for channel 1 and channel 2

Figure 1a: V

turn on:

bb

IN1

IN2

V

bb

V

OUT1

V

OUT2

ST open drain

Figure 2a: Switching a lamp:

Figure 3a: Turn on into short circuit:

shut down by overtemperature, restart by cooling

IN1

I

L1

other channel: normal operation

I

L(SCp)

I

L(SCr)

t

off(SC)

ST

t

Heating up of the chip may require several milliseconds, depending on external conditions (t

off(SC)

vs. T

see page 10)

j,start

t

IN

ST

V

OUT

I

L

t

The initial peak current should be limited by the lamp and not by the initial short circuit current I

= 28 A typ. of the device.

L(SCp)

Figure 3b: Turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2)

IN1/2

I + I

L1 L2

I

L(SCp)

I

L(SCr)

t

off(SC)

ST1/2

t

Semiconductor Group 11

ST1 and ST2 have to be configured as a 'Wired OR' function ST1/2 with a single pull-up resistor.

Figure 4a: Overtemperature:

T

Reset if

T

<

j

jt

Preliminary BTS 725 L1

Figure 5b: Open load: detection in ON-state, open

load occurs in on-state

IN

ST

V

OUT

T

J

Figure 5a: Open load: detection in ON-state, turn on/off to open load

IN

t

d(ST OL1)

ST

V

OUT

normal

I

L

open

normal

t

d(ST OL1)

= 20 µs typ., t

d(ST OL2)

= 10 µs typ

Figure 5c: Open load: detection in ON- and OFF-state (with R

), turn on/off to open load

EXT

t

d(ST OL2)

t

IN

ST

V

I

OUT

L

t

d(ST)

open

t

d(ST OL4)

IN

ST

V

OUT

t

d(ST)

I

L

open

t

Semiconductor Group 12

V

Figure 6a: Undervoltage:

Preliminary BTS 725 L1

Figure 7a: Overvoltage:

IN

V

bb

V

bb(u rst)

V

OUT

V

bb(under)

ST

Figure 6b: Undervoltage restart of charge pump

IN

V

bb

V

OUT

ON(CL)

V

bb(over)

V

bb(o rst)

ST

t

V

on

off-state

bb(u rst)

bb(u cp)

bb(under)

IN = high, normal load conditions. Charge pump starts at V

bb(ucp)

= 5.6 V typ.

V

on-state

bb(o rst)

bb(over)

V

ON(CL)

off-state

V

bb

Semiconductor Group 13

Package and Ordering Code

Preliminary BTS 725 L1

Standard P-DSO-20-9

BTS725L1 Q67060-S7006-A2

All dimensions in millimetres

1) Does not include plastic or metal protrusions of 0.15 max per side

2) Does not include dambar protrusion of 0.05 max per side

Definition of soldering point with temperature Ts: upper side of solder edge of device pin 15.

Ordering Code

Pin 15

Printed circuit board (FR4, 1.5mm thick, one layer 70µm, 6cm max. power dissipation P I

L(NOM)

2

active heatsink area) as a reference for

, nominal load current

and thermal resistance R

tot

thja

Semiconductor Group 14

Datasheet BTS725L1 Datasheet (Siemens)

Specifications and Main Features

Frequently Asked Questions

User Manual