Datasheet BF1202WR, BF1202R, BF1202 Datasheet (Philips)

DISCRETE SEMICONDUCTORS

DATA SHEET

BF1202; BF1202R; BF1202WR

N-channel dual-gate PoLo
MOS-FETs

Preliminary specification 1999 Nov 26

Philips Semiconductors Preliminary specification

N-channel dual-gate PoLo MOS-FETs

FEATURES

• Short channel transistor with high

forward transfer admittance to input
capacitance ratio

• Low noise gain controlled amplifier

• Partly internal self-biasing circuit to

ensure good cross-modulation
performance during AGC and good
DC stabilization.

APPLICATIONS

• VHF and UHF applications with

3 - 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.

DESCRIPTION

PINNING

PIN DESCRIPTION

1 source
2drain
3 gate 2
4 gate 1

handbook, 2 columns

BF1202; BF1202R;

BF1202WR

handbook, 2 columns

Top view MSB035

BF1202R marking code: LEp

Fig.2 Simplified outline

(SOT143R).

34

book, halfpage

43

12

43

Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source

12

Top view MSB014

21

Top view MSB842

protect against excessive input
voltage surges. The BF1202,

BF1202 marking code: LDp

BF1202WR marking code: LE

BF1202R and BF1202WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic

Fig.1 Simplified outline

(SOT143B).

Fig.3 Simplified outline

(SOT343R).

packages respectively.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DS

I

D

P

tot

y

 forward transfer admittance 25 30 40 mS

fs

C

ig1-ss

C

rss

drain-source voltage −−10 V
drain current −−30 mA
total power dissipation −−200 mW

input capacitance at gate 1 − 1.7 2.2 pF
reverse transfer capacitance f = 1 MHz − 15 30 fF

F noise figure f = 800 MHz − 1.0 1.8 dB
X

mod

cross-modulation input level for k = 1% at

100 105 − dBµV

40 dB AGC

T

j

operating junction temperature −−150 °C

CAUTION

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.

1999 Nov 26 2

Philips Semiconductors Preliminary specification

Fig.4 Power derating curve.

N-channel dual-gate PoLo MOS-FETs

BF1202; BF1202R;

BF1202WR

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

Note

1. T

s

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-s

drain-source voltage − 10 V
drain current − 30 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation Ts≤ 110 °C; note 1 − 200 mW
storage temperature −65 +150 °C
operating junction temperature − +150 °C

is the temperature of the soldering point of the source lead.

thermal resistance from junction to soldering point 200 K/W

250

P

tot

(mW)

200

150

100

50

0

0 50 100 150 200

T

(°C)

s

1999 Nov 26 3

Philips Semiconductors Preliminary specification

N-channel dual-gate PoLo MOS-FETs

BF1202; BF1202R;

BF1202WR

STATIC CHARACTERISTICS

T

=25°C unless otherwise specified.

j

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

(BR)DSS

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S (th)

V

G2-S (th)

I

DSX

I

G1-SS

I

G2-SS

Note

1. R

drain-source breakdown voltage V
gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
forward source-gate 1 voltage V
forward source-gate 2 voltage V
gate 1-source threshold voltage V
gate 2-source threshold voltage V
drain-source current V

gate 1 cut-off current V
gate 2 cut-off current V

connects G1 to VGG=5V

G1

G1-S=VG2-S

G2-S=VDS

G1-S=VDS

G2-S=VDS

G1-S=VDS

=4V; VDS=5V; ID=100µA0.31.0V

G2-S

=5V; VDS=5V; ID=100µA0.31.2V

G1-S

=4V; VDS=5V; RG1= 120 kΩ;

G2-S

=0; ID=10µA10− V
=0; I
=0; I
=0; I
=0; I

=10mA 6 − V

G1-S

=10mA 6 − V

G2-S

=10mA 0.5 1.5 V

S-G1

=10mA 0.5 1.5 V

S-G2

816mA

note 1

G2-S=VDS

G1-S=VDS

=0; V
=0; V

=5V − 50 nA

G1-S

=4V − 20 nA

G2-S

DYNAMIC CHARACTERISTICS

Common source; T

=25°C; V

amb

=4V; VDS=5V; ID= 12 mA; unless otherwise specified.

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

y

 forward transfer admittance pulsed; Tj=25°C 253040mS

fs

C

ig1-ss

C

ig2-ss

C

oss

C

rss

NF noise figure f = 400 MHz; Y

X

mod

input capacitance at gate 1 f = 1 MHz − 1.7 2.2 pF
input capacitance at gate 2 f = 1 MHz − 1 − pF
output capacitance f = 1 MHz − 0.85 − pF
reverse transfer capacitance f = 1 MHz − 15 30 fF

− 0.8 1.5 dB

− 11.8dB
90 −−dBµV

− 92 − dBµV

100 105 − dBµV

cross-modulation

S=YSopt

f = 800 MHz; Y

S=YSopt

input level for k = 1% at 0 dB AGC;

=50MHz; f

f

w

= 60 MHz; note 1

unw

input level for k = 1% at 10 dB AGC;
f

=50MHz; f

w

= 60 MHz; note 1

unw

input level for k = 1% at 40 dB AGC;

=50MHz; f

f

w

= 60 MHz; note 1

unw

Note

1. Measured in test circuit of Fig.5.

1999 Nov 26 4

Philips Semiconductors Preliminary specification

N-channel dual-gate PoLo MOS-FETs

V

GG

R1

10 kΩ

R

V

G1

AGC

handbook, full pagewidth

R

GEN
50 Ω

V

C2

4.7 nF

R2

50 Ω

I

C1

4.7 nF

DUT

V

DS

C3

4.7 nF

L1

≈2.2 µH

C4

4.7 nF

BF1202; BF1202R;

BF1202WR

R

L

50 Ω

MGS315

Fig.5 Cross-modulation test set-up.

1999 Nov 26 5

Philips Semiconductors Preliminary specification

N-channel dual-gate PoLo MOS-FETs

BF1202; BF1202R;

BF1202WR

PACKAGE OUTLINES

Plastic surface mounted package; 4 leads SOT143B

D

y

e

b

p

B

w M

E

v M

A

B

H

E

A

X

b

1

e

1

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

1.1

0.9

1

A

max

0.1

b

0.48

0.38

b

c

1

p

0.88

0.15

0.78

0.09

34

21

0 1 2 mm

scale

D

E

e

e

1

3.0

1.4

1.9

2.8

1.2

1.7

H

2.5

2.1

Q

A

A

1

c

L

p

detail X

L

E

p

0.45

0.55

0.15

0.45

ywvQ

0.1 0.10.2

OUTLINE

VERSION

SOT143B

REFERENCES

IEC JEDEC EIAJ

EUROPEAN

PROJECTION

ISSUE DATE

97-02-28

1999 Nov 26 6

Philips Semiconductors Preliminary specification

N-channel dual-gate PoLo MOS-FETs

BF1202; BF1202R;

BF1202WR

Plastic surface mounted package; reverse pinning; 4 leads SOT143R

D

y

e

b

p

B

v

M

A

w

M

B

E

H

E

A

X

e

1

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

1.1

0.9

1

A

max

0.1

b

0.48

0.38

b

c

1

p

0.88

0.15

0.78

0.09

43

12

b

1

0 1 2 mm

scale

D

E

e

e

1

3.0

1.4

1.9

2.8

1.2

1.7

H

2.5

2.1

Q

A

A

1

c

L

p

detail X

L

E

p

0.55

0.45

0.25

0.25

ywvQ

0.1 0.10.2

OUTLINE
VERSION

SOT143R SC-61B

IEC JEDEC EIAJ

REFERENCES

EUROPEAN

PROJECTION

ISSUE DATE

97-03-10
99-09-13

1999 Nov 26 7

Philips Semiconductors Preliminary specification

N-channel dual-gate PoLo MOS-FETs

BF1202; BF1202R;

BF1202WR

Plastic surface mounted package; reverse pinning; 4 leads SOT343R

D

y

e

43

E

H

E

AB

X

v M

A

21

b

B

w M

DIMENSIONS (mm are the original dimensions)

A

mm

1.1

0.8

A

max

0.1

UNIT

p

e

1

1

b

0.4

0.3

p

b

0.7

0.5

1

cD

0.25

0.10

b

1

0 1 2 mm

scale

e

E

2.2

1.35

1.15

1.3

1.8

Q

A

A

1

c

L

p

detail X

H

L

0.45

0.15

Qwv

p

0.23

0.13

0.2y0.10.21.15

e

E

1

2.2

2.0

OUTLINE

VERSION

SOT343R

REFERENCES

IEC JEDEC EIAJ

EUROPEAN

PROJECTION

ISSUE DATE

97-05-21

1999 Nov 26 8

Philips Semiconductors Preliminary specification

N-channel dual-gate PoLo MOS-FETs

BF1202; BF1202R;

BF1202WR

DEFINITIONS

Data Sheet Status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Nov 26 9

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1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands budgetnum/printrun/ed/pp10 Date of release: 1999 Nov 26 Document order number: 9397 750 06646