Datasheet BF1102 Datasheet (Philips)

DISCRETE SEMICONDUCTORS

MBD128

DATA SHEET

BF1102

Dual N-channel dual gate MOS-FET

Preliminary specification 1999 Jul 08

Philips Semiconductors Preliminary specification

Dual N-channel dual gate MOS-FET BF1102

FEATURES

• Two low noise gain controlled amplifiers in a single

package

• Specially designed for 5 V applications

• Superior cross-modulation performance during AGC

• High forward transfer admittance

• High forward transfer admittance to input capacitance

ratio.

APPLICATIONS

• Gain controlled low noise amplifier for VHF and UHF

applications such as television tuners and professional
communications equipment.

DESCRIPTION

The BF1102 is a combination of two equal dual gate
MOS-FETs with shared source and gate 2 leads.
The source and substrate are interconnected. An internal
bias circuit enables DC stabilization and a very good
cross-modulation performance at 5 V supply voltage.
Integrated diodes between the gates and source protect
against excessive input voltage surges. The transistor has
a SOT363 micro-miniature plastic package.

PINNING - SOT363

PIN DESCRIPTION

1 gate 1 (1)
2 gate 2 (1,2)
3drain(1)
4drain(2)
5 source (1,2)
6 gate 1 (2)

handbook, halfpage

56

4

132

Marking code: W1.

Fig.1 Simplified outline and symbol.

g2 (1, 2)

AMP2

s (1, 2)

AMP1 d (1)g1 (1)

d (2)g1 (2)

MBL029

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Per MOS-FET unless otherwise specified

V

DS

I

D

P

tot

y

 forward transfer admittance ID=15mA − 43 − mS

fs

C

ig1-s

C

rss

drain-source voltage −−7V
drain current (DC) −−40 mA
total power dissipation Ts≤ 102 °C; note 1 −−200 mW

input capacitance at gate 1 ID=15mA − 2.8 − pF
reverse transfer capacitance f = 1 MHz − 30 − fF

F noise figure f = 800 MHz −−2.8 dB
X

mod

T

j

cross-modulation input level for k = 1% at 40 dB AGC 100 −−dBµV
operating junction temperature −−150 °C

Note

is the temperature at the soldering point of the source lead.

1. T

s

CAUTION

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.

1999 Jul 08 2

Philips Semiconductors Preliminary specification

Fig.2 Power derating curve.

handbook, halfpage

0 50 100 200

250

0

200

MGS359

150

150

100

50

Ts (°C)

P

tot

(mW)

Dual N-channel dual gate MOS-FET BF1102

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per MOS-FET unless otherwise specified

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-s

drain-source voltage − 7V
drain current (DC) − 40 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation Ts≤ 102 °C − 200 mW
storage temperature −65 +150 °C
operating junction temperature − +150 °C

thermal resistance from junction to soldering point 240 K/W

1999 Jul 08 3

Philips Semiconductors Preliminary specification

Dual N-channel dual gate MOS-FET BF1102

STATIC CHARACTERISTICS

T

=25°C unless otherwise specified.

j

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per MOS-FET unless otherwise specified

V

(BR)DSS

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S(th)

V

G2-S(th)

I

DSX

I

G1-S

I

G2-S

drain-source breakdown voltage V

G1-S=VG2-S

=0; ID=10µA7− V
gate-source breakdown voltage VGS=VDS=0; I
gate-source breakdown voltage VGS=VDS=0; I
forward source-gate voltage V
forward source-gate voltage V

G2-S=VDS

G1-S=VDS

gate-source threshold voltage VDS=5V; V
gate-source threshold voltage VDS=5V; V
drain-source current V
gate cut-off current V
gate cut-off current V

G2-S

G1-S

G2-S

=0; I
=0; I

G2-S

G1-S

=4V; VDS=5V; RG= 120 kΩ; note 1 12 20 mA
=5V; V
=5V; V

G2-S=VDS

G1-S=VDS

=10mA 6 15 V

G1-S

=5mA 6 15 V

G2-S

= −10 mA 0.5 1.5 V

S-G1

= −10 mA 0.5 1.5 V

S-G2

=4V; ID=20µA0.31V
=4V; ID=20µA0.31.2V

=0 − 50 nA
=0 − 20 nA

Notes

1. R

connects gate 1 to VGG=5V.

G1

DYNAMIC CHARACTERISTICS

Common source; T

=25°C; V

amb

=4V; VDS=5V; ID= 15 mA; unless otherwise specified.

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Per MOS-FET unless otherwise specified (note 1)

y

 forward transfer admittance Tj=25°C 364350mS

fs

C

ig1-ss

C

ig2-ss

C

oss

C

rss

F noise figure f = 800 MHz; Y
X

mod

input capacitance at gate 1 f = 1 MHz 2 2.8 3.6 pF
input capacitance at gate 2 f = 1 MHz −−7pF
output capacitance f = 1 MHz − 1.6 2.5 pF
reverse transfer capacitance f = 1 MHz − 30 50 fF

S=YSopt

cross-modulation input level for k = 1% at 0 dB AGC;

=50MHz; f

f

w

=60MHz; (note2)

unw

input level for k = 1% at 40 dB AGC;
f

=50MHz; f

w

=60MHz; (note2)

unw

− 22.8dB
85 −−dBµV

100 −−dBµV

Notes

1. Not used MOS-FET: V

=0; VDS=0.

G1-S

2. Measured in test circuit of Fig.17.

1999 Jul 08 4

Philips Semiconductors Preliminary specification

Fig.3 Transfer characteristics; typical values.

VDS=5V.
T

j

=25°C.

handbook, halfpage

0

30

20

10

0

0.80.4 2.42.01.61.2

MGS360

V

G1-S

(V)

2.5 V

2 V

1.5 V

1 V

3.5 V

3 V

V

G2-S

= 4 V

I

D

(mA)

Fig.5 Gate 1 current as a function of gate 1

voltage; typical values.

VDS=5V.
T

j

=25°C.

handbook, halfpage

0

160

80

120

40

0

0.5 2.5

MGS362

1 1.5 2

I

G1

(µA)

V

G1-S

(V)

2.5 V

2 V

3.5 V

3 V

V

G2-S

= 4 V

Dual N-channel dual gate MOS-FET BF1102

ALL GRAPHS FOR ONE MOS-FET

30

handbook, halfpage

I

D

(mA)

20

10

0

010

V

=4V.

G2-S

T

=25°C.

j

2468

V

G1-S

= 1.5 V

1.4 V

1.3 V

1.2 V

1.1 V

1 V

Fig.4 Output characteristics; typical values.

MGS361

VDS (V)

1999 Jul 08 5

50

handbook, halfpage

|yfs|

(mS)

40

30

20

10

0

010 30

VDS=5V.
T

=25°C.

j

V

G2-S

= 4 V

20

Fig.6 Forward transfer admittance as a

function of drain current; typical values.

3.5 V

MGS363

3 V

2.5 V

2 V

ID (mA)

Philips Semiconductors Preliminary specification

Fig.7 Drain current as a function of gate 1 current;

typical values.

VDS=5V; V

G2-S

=4V; Tj=25°C.

handbook, halfpage

020 60

25

0

5

20

15

10

MGS364

40

I

D

(mA)

IG1 (µA)

Fig.9 Drain current as a function of gate 1 (= VGG)

and drain supply voltage; typical values.

V

G2-S

=4V; Tj=25°C.

R

G1

connected to VGG; see Fig.17.

handbook, halfpage

010

30

0

10

20

MGS366

2468

I

D

(mA)

VGG = VDS (V)

RG1 = 47 kΩ

68 kΩ

82 kΩ

100 kΩ

120 kΩ

150 kΩ
180 kΩ
220 kΩ

Dual N-channel dual gate MOS-FET BF1102

15

handbook, halfpage

I

D

(mA)

10

5

0

0

VDS=5V; V
R

=120kΩ (connected to VGG); see Fig.17.

G1

1

=4V; Tj=25°C.

G2-S

23 54

Fig.8 Drain current as a function of gate 1

supply voltage (= V

); typical values.

GG

MGS365

VGG (V)

1999 Jul 08 6

V

G1-S

V

G2-S

MGS367

= 5 V

4.5 V
4 V

3.5 V

3 V

(V)

20

handbook, halfpage

I

D

(mA)

16

12

8

4

0

02 6

VDS=5V; Tj=25°C.
R

=120kΩ (connected to VGG); see Fig.17.

G1

4

Fig.10 Drain current as a function of gate 2 voltage;

typical values.

Philips Semiconductors Preliminary specification

Fig.11 Gate 1 current as a function of gate 2

voltage; typical values.

VDS=5V; Tj=25°C.
R

G1

=120kΩ (connected to VGG); see Fig.17.

handbook, halfpage

0

40

20

30

10

0

MGS368

264

I

G1

(µA)

V

G2-S

(V)

4.5 V

4 V

3.5 V

3 V

V

G1-S

= 5 V

Dual N-channel dual gate MOS-FET BF1102

120

handbook, halfpage

V

unw

(dBµV)

110

100

90

80

020 60

VDS=5V; VGG=5V; fw=50MHz; f
R

=120kΩ (connected to VGG); see Fig.17.

G1

40

gain reduction (dB)

=60MHz; T

unw

MGS369

=25 °C;

amb

Fig.12 Unwanted voltage for 1% cross-modulation

as a function of gain reduction;
typical values.

1999 Jul 08 7

Philips Semiconductors Preliminary specification

Fig.13 Input admittance as a function of frequency;

typical values.

VDS=5V; VG2=4V.
I

D

=15mA; T

amb

=25°C.

handbook, halfpage

MGS370

10

2

10

1

10

−1

10 10

2

10

3

f (MHz)

y

is

(mS)

b

is

g

is

Fig.15 Forward transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V.
I

D

=15mA; T

amb

=25°C.

handbook, halfpage

MGS372

10

2

−ϕ

fs

(deg)

10

2

1

10

10

1

10 10

2

10

3

f (MHz)

|yfs|

(mS)

ϕ

fs

|yfs|

Dual N-channel dual gate MOS-FET BF1102

3

10

handbook, halfpage

MGS371

|yrs|
(µS)

ϕ

2

10

rs

|yrs|

10

11

10 10

2

f (MHz)

VDS=5V; VG2=4V.
I

=15mA; T

D

amb

=25 °C.

Fig.14 Reverse transfer admittance and phase as

a function of frequency; typical values.

3

10

−ϕ

rs

(deg)

2

10

10

3

10

1999 Jul 08 8

10

handbook, halfpage

y

os

MGS373

(mS)

b

os

1

g

os

−1

10

10 10

VDS=5V; VG2=4V.
I

=15mA; T

D

amb

=25°C.

2

f (MHz)

3

10

Fig.16 Output admittance as a function of

frequency; typical values.

Philips Semiconductors Preliminary specification

Dual N-channel dual gate MOS-FET BF1102

handbook, full pagewidth

V

AGC

R1

R

GEN
50 Ω

V

10 kΩ

C2

4.7 nF

R2

50 Ω

V

I

GG

C1

4.7 nF

DUT

R

G1

V

C3

4.7 nF

L1

≈2.2 µH

C4

4.7 nF

DS

Fig.17 Cross-modulation test set-up (for one MOS-FET).

MGS315

R

L

50 Ω

1999 Jul 08 9

Philips Semiconductors Preliminary specification

Dual N-channel dual gate MOS-FET BF1102

PACKAGE OUTLINE

Plastic surface mounted package; 6 leads SOT363

D

y

pin 1
index

132

e

1

e

E

H

E

56

b

p

4

A

A

1

wBM

detail X

AB

Q

L

p

X

v M

A

c

01 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

max

0.1

1

b

cD

p

0.30

0.25

0.20

0.10

IEC JEDEC EIAJ

2.2

1.8

E

1.35

1.15

REFERENCES

1.3

e

H

L

e

0.65

E

1

2.2

0.45

2.0

0.15

Qywv

p

0.25

0.15

0.2 0.10.2

EUROPEAN

PROJECTION

ISSUE DATE

97-02-28

UNIT

A

1.1

mm

0.8

OUTLINE
VERSION

SOT363 SC-88

1999 Jul 08 10

Philips Semiconductors Preliminary specification

Dual N-channel dual gate MOS-FET BF1102

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Jul 08 11

Philips Semiconductors – a worldwide company

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For all other countries apply to: Philips Semiconductors,
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© Philips Electronics N.V. SCA

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1999 66

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 125004/00/01/pp12 Date of release: 1999 Jul 08 Document orde r number: 9397 750 06 179