Datasheet BF1201WR, BF1201R, BF1201 Datasheet (Philips)

DISCRETE SEMICONDUCTORS

DATA SH EET

BF1201; BF1201R; BF1201WR

N-channel dual-gate PoLo
MOS-FETs

Product specification
Supersedes data of 1999 Dec 01

2000 Mar 29

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

FEATURES

• Short channel transistor with high
forwardtransferadmittancetoinput
capacitance ratio

• Low noise gain controlled amplifier

• Partly internal self-biasing circuit to

ensure good cross-modulation
performanceduring AGC andgood
DC stabilization.

APPLICATIONS

• VHF and UHF applications with
3 to 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.

DESCRIPTION

PINNING

PIN DESCRIPTION

1 source
2 drain
3 gate 2
4 gate 1

handbook, 2 columns

BF1201; BF1201R;

BF1201WR

handbook, 2 columns

Top view

BF1201R marking code: LBp

Fig.2 Simplified outline

(SOT143R).

34

page

43

12

MSB035

43

Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source

12

Top view

MSB014

21

Top view

MSB842

protect against excessive input
voltage surges. The BF1201,

BF1201 marking code: LAp.

BF1201WR marking code: LA

BF1201R and BF1201WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic

Fig.1 Simplified outline

(SOT143B).

Fig.3 Simplified outline

(SOT343R).

packages respectively.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DS

I

D

P

tot

y

 forward transfer admittance 23 28 35 mS

fs

C

ig1-ss

C

rss

drain-source voltage −−10 V
drain current −−30 mA
total power dissipation −−200 mW

input capacitance at gate 1 − 2.6 3.1 pF

reverse transfer capacitance f = 1 MHz − 15 30 fF
F noise figure f = 400 MHz − 1 1.8 dB
X

mod

cross-modulation input level for k = 1% at

105 −−dBµV

40 dB AGC

T

j

operating junction temperature −−150 °C

CAUTION

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.

2000 Mar 29 2

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

BF1201; BF1201R;

BF1201WR

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

Note

1. Tsis the temperature of the soldering point of the source lead.

THERMAL CHARACTERISTICS

drain-source voltage − 10 V
drain current (DC) − 30 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation

BF1201; BF1201R T
BF1201WR T

≤ 113 °C; note 1 − 200 mW

s

≤ 109 °C; note 1 − 200 mW

s

storage temperature −65 +150 °C
operating junction temperature − 150 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-s

thermal resistance from junction to soldering point

BF1201; BF1201R 185 K/W
BF1201WR 155 K/W

150

MCD934

Ts (°C)

250

handbook, halfpage

P

tot

(mW)

200

150

100

50

0

050

(1)

(2)

100 200

(1) BF1201WR.
(2) BF1201 and BF1201R.

Fig.4 Power derating curve.

2000 Mar 29 3

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

BF1201; BF1201R;

BF1201WR

STATIC CHARACTERISTICS

Tj=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

(BR)DSS

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S(th)

V

G2-S(th)

I

DSX

I

G1-SS

I

G2-SS

Note

1. R

connects G1to VGG=5V.

G1

drain-source breakdown voltage V
gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
forward source-gate 1 voltage V
forward source-gate 2 voltage V
gate 1-source threshold voltage V
gate 2-source threshold voltage V
drain-source current V

gate 1 cut-off current V
gate 2 cut-off current V

G1-S=VG2-S
G2-S=VDS
G1-S=VDS
G2-S=VDS
G1-S=VDS

=4V; VDS=5V; ID= 100 µA 0.3 1.0 V

G2-S
G1-S=VDS

=4V; VDS=5V; RG1=62kΩ;

G2-S

note 1

G2-S=VDS
G1-S=VDS

= 0; ID=10µA10−V
= 0; I
= 0; I
= 0; I
= 0; I

=10mA 6 − V

G1-S

=10mA 6 − V

G2-S

= 10 mA 0.5 1.5 V

S-G1

= 10 mA 0.5 1.5 V

S-G2

=5V; ID= 100 µA 0.3 1.2 V

11 19 mA

= 0; V
= 0; V

=5V − 50 nA

G1-S

=4V − 20 nA

G2-S

DYNAMIC CHARACTERISTICS

Common source; T

=25°C; V

amb

=4V; VDS=5V; ID= 15 mA; unless otherwise specified.

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

y

 forward transfer admittance pulsed; Tj=25°C 232835mS

fs

C

ig1-ss

C

ig2-ss

C

oss

C

rss

F noise figure f = 10.7 MHz; G

G

tr

X

mod

input capacitance at gate 1 f = 1 MHz − 2.6 3.1 pF
input capacitance at gate 2 f = 1 MHz − 1.1 − pF
output capacitance f = 1 MHz − 0.9 − pF
reverse transfer capacitance f = 1 MHz − 15 30 fF

= 20 mS; BS=0 − 57dB

S

f = 400 MHz; Y
f = 800 MHz; Y

S=YS opt
S=YS opt

power gain f = 200 MHz; GS= 2 mS; BS=B

GL= 0.5 mS; BL=B
f = 400 MHz; G

S

GL= 1 mS; BL=B
f = 800 MHz; G

S

GL= 1 mS; BL=B

;

L opt

= 2 mS; BS=B

;

L opt

= 3.3 mS; BS=B

;

L opt

S opt

S opt

S opt

− 1 1.8 dB

− 1.9 2.5 dB

;

− 33.5 − dB

;

− 29 − dB

;

− 24 − dB

cross-modulation input level for k = 1%; fw= 50 MHz;

f

= 60 MHz; note 1

unw

at 0 dB AGC 90 −−dBµV
at 10 dB AGC − 95 − dBµV
at 40 dB AGC 105 −−dBµV

Note

1. Measured in Fig.21 test circuit.

2000 Mar 29 4

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

V

MCD935

3.5 V
3 V

2.5 V

2 V

1.5 V

1 V

G1-S

(V)

25

handbook, halfpage

I

D

(mA)

20

15

10

5

0

0 2.5

V

= 4 V

G2-S

0.5 1 1.5 2

24

handbook, halfpage

I

D

(mA)

16

8

0

010

BF1201; BF1201R;

BF1201WR

MCD936

V

= 1.8 V

G1-S

1.7 V

1.6 V

1.5 V

1.4 V

1.3 V

1.2 V

2

648

VDS (V)

VDS=5V.
Tj=25°C.

Fig.5 Transfer characteristics; typical values.

100

handbook, halfpage

I

G1

(µA)

80

60

40

20

0

0 2.5

0.5 1 1.5 2

V

G2-S

= 4 V

3 V

2 V

V

MCD937

3.5 V

2.5 V

1.5 V

G1-S

(V)

V

=4V.

G2-S

Tj=25°C.

Fig.6 Output characteristics; typical values.

40

handbook, halfpage

y

fs

(mS)

30

20

10

2 V

0

0

525

10 15 20

V

G2-S

MCD938

= 4 V

3.5 V

3 V

2.5 V

ID (mA)

VDS=5V.
Tj=25°C.

Fig.7 Gate 1 current as a function of gate 1

voltage; typical values.

2000 Mar 29 5

VDS=5V.
Tj=25°C.

Fig.8 Forward transfer admittance as a function

of drain current; typical values.

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

16

handbook, halfpage

I

D

(mA)

12

8

4

0

0

VDS= 5 V; V
Tj=25°C.

10 50

=4V.

G2-S

20 30 40

MCD939

IG1 (µA)

BF1201; BF1201R;

20

handbook, halfpage

I

D

(mA)

16

12

8

4

0

05

VDS= 5 V; V
RG1=62kΩ (connected to VGG); see Fig.21.

1234

= 4 V; Tj=25°C.

G2-S

BF1201WR

MCD940

VGG (V)

Fig.9 Draincurrentas a function of gate 1current;

typical values.

25

handbook, halfpage

I

D

(mA)

20

15

10

5

0

010

V

= 4 V; Tj=25°C.

G2-S

RG1 connected to VGG; see Fig.21.

R

G1

56 kΩ

62 kΩ

2468

= 39 kΩ

47 kΩ

MCD941

68 kΩ

82 kΩ

100 kΩ

VGG = VDS (V)

Fig.10 Drain current as a function of gate 1 supply

voltage (= VGG); typical values.

20

handbook, halfpage

I

D

(mA)

16

12

8

4

0

0246

VDS= 5 V; Tj=25°C.
RG1=62kΩ (connected to VGG); see Fig.21.

MCD942

V

= 5 V

GG

4.5 V
4 V

3.5 V
3 V

V

(V)

G2-S

Fig.11 Drain currentasafunctionof gate 1 (= VGG)

and drain supply voltage; typical values.

2000 Mar 29 6

Fig.12 Drain current as a function of gate 2

voltage; typical values.

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

60

handbook, halfpage

I

G1

(µA)

40

20

0

0246

VDS= 5 V; Tj=25°C.
RG1=62kΩ (connected to VGG); see Fig.21.

V

GG

V

G2-S

MCD943

= 5 V

4.5 V

4 V

3.5 V
3 V

(V)

handbook, halfpage

0

gain

reduction

(dB)

−10

−20

−30

−40

−50

012 4

VDS= 5 V; VGG= 5 V; RG1=62kΩ;
f = 50 MHz; T

amb

=25°C.

BF1201; BF1201R;

BF1201WR

MCD944

3

V

(V)

AGC

Fig.13 Gate 1 current as a function of gate 2

voltage; typical values.

120

handbook, halfpage

V

unw

(dBµV)

110

100

90

80

0

10 50

VDS= 5 V; VGG= 5 V; RG1=62kΩ;f = 50 MHz;

= 60 MHz; T

f

unw

amb

20 30 40

=25°C.

gain reduction (dB)

MCD945

Fig.15 Unwanted voltage for1% cross-modulation

as a function of gain reduction; typical
values; see Fig.21.

Fig.14 Typical gain reduction as a function of the

AGC voltage; see Fig.21.

20

handbook, halfpage

I

D

(mA)

16

12

8

4

0

VDS= 5 V; VGG= 5 V; RG1=62kΩ;
f = 50 MHz; T

10 20 30 40

050

=25°C.

amb

gain reduction (dB)

MCD946

Fig.16 Drain current as a function of gain

reduction; typical values; see Fig.21.

2000 Mar 29 7

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

g

is

MCD947

3

10

2

10

handbook, halfpage

Y

is

(mS)

10

1

−1

10

10

VDS= 5 V; VG2=4V.
ID= 15 mA; T

amb

=25°C.

b

is

2

10

f (MHz)

3

10

handbook, halfpage

y

rs

(µS)

2

10

10

1

10

VDS= 5 V; VG2=4V.
ID= 15 mA; T

amb

=25°C.

BF1201; BF1201R;

BF1201WR

MCD948

ϕ

rs

y

rs

2

10

f (MHz)

3

−10

ϕ

rs

(deg)

2

−10

−10

−1

3

10

Fig.17 Input admittanceasa function offrequency;

typical values.

2

10

handbook, halfpage

y

fs

(mS)

10

1

10 10

VDS= 5 V; VG2=4V.
ID= 15 mA; T

amb

=25°C.

y

fs

ϕ

fs

2

MCD949

f (MHz)

Fig.18 Reverse transfer admittance and phase as

a function of frequency; typical values.

2

−10

ϕ

fs

(deg)

−10

−1

3

10

10

handbook, halfpage

Y

os

(mS)

1

−1

10

−2

10

10

VDS= 5 V; VG2=4V.
ID= 15 mA; T

amb

=25°C.

b

os

g

os

2

10

f (MHz)

MCD950

3

10

Fig.19 Forward transfer admittance and phase as

a function of frequency; typical values.

2000 Mar 29 8

Fig.20 Output admittance as a function of

frequency; typical values.

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

V

GG

R1

10 kΩ

R

V

G1

handbook, full pagewidth

R

GEN
50 Ω

V

C2

4.7 nF

R2

50 Ω

I

AGC

C1

4.7 nF

DUT

V

L1

≈2.2 µH

DS

C3

4.7 nF

C4

4.7 nF

BF1201; BF1201R;

BF1201WR

R

L

50 Ω

MGS315

Fig.21 Cross-modulation test set-up.

Table 1 Scattering parameters: VDS=5V; V

s

f

(MHz)

MAGNITUDE

(ratio)

11

ANGLE

(deg)

MAGNITUDE

(ratio)

=4V; ID= 15 mA; T

G2-S

s

21

ANGLE

(deg)

=25°C

amb

s

12

MAGNITUDE

(ratio)

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.987 −4.72 2.775 174.6 0.0006 88.8 0.997 −1.84
100 0.985 −9.39 2.774 169.5 0.0010 86.7 0.997 −3.37
200 0.978 −18.59 2.731 159.1 0.0019 79.7 0.996 −6.72
300 0.976 −27.74 2.671 148.8 0.0026 74.2 0.994 −10.02

400 0.949 −36.59 2.599 138.8 0.0032 69.9 0.992 −13.33
500 0.928 −45.08 2.501 129.1 0.0035 65.9 0.989 −16.55
600 0.905 −53.26 2.400 119.8 0.0035 64.6 0.986 −19.64
700 0.882 −61.07 2.297 110.9 0.0033 65.7 0.982 −22.63
800 0.860 −68.48 2.199 102.4 0.0029 69.1 0.979 −25.54
900 0.838 −75.55 2.096 94.2 0.0024 83.3 0.975 −28.44

1000 0.818 −82.23 1.997 86.3 0.0021 103.8 0.971 −31.42

Table 2 Noise data: V

=5V; V

DS

=4V; ID= 15 mA; T

G2-S

amb

=25°C

f

(MHz)

F

min

(dB)

400 1 0.825 38.93 50
800 1.9 0.753 70.65 38.75

2000 Mar 29 9

Γ

opt

(ratio) (deg)

R
(Ω)

n

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

BF1201; BF1201R;

BF1201WR

PACKAGE OUTLINES

Plastic surface mounted package; 4 leads SOT143B

D

y

e

b

p

B

w M

E

v M

A

B

H

E

A

X

b

1

e

1

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

1.1

0.9

1

A

max

0.1

b

0.48

0.38

b

c

1

p

0.88

0.15

0.78

0.09

34

21

0 1 2 mm

scale

D

E

e

e

1

3.0

1.4

1.9

2.8

1.2

1.7

H

2.5

2.1

Q

A

A

1

c

L

p

detail X

L

E

p

0.45

0.55

0.15

0.45

ywvQ

0.1 0.10.2

OUTLINE

VERSION

SOT143B

IEC JEDEC EIAJ

REFERENCES

2000 Mar 29 10

EUROPEAN

PROJECTION

ISSUE DATE

97-02-28

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

BF1201; BF1201R;

BF1201WR

Plastic surface mounted package; reverse pinning; 4 leads SOT143R

D

y

e

b

p

w M

B

v M

A

B

E

H

E

A

X

e

1

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

1.1

0.9

1

A

max

0.48

0.1

0.38

b

b

p

0.88

0.78

c

1

0.15

0.09

43

12

b

1

0 1 2 mm

scale

D

E

e

e

1

3.0

1.4

1.9

2.8

1.2

1.7

H

2.5

2.1

Q

A

A

1

c

L

p

detail X

L

E

p

0.55

0.25

0.45

0.25

0.1 0.10.2

ywvQ

OUTLINE
VERSION

SOT143R SC-61B

IEC JEDEC EIAJ

REFERENCES

2000 Mar 29 11

EUROPEAN

PROJECTION

ISSUE DATE

97-03-10
99-09-13

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

BF1201; BF1201R;

BF1201WR

Plastic surface mounted package; reverse pinning; 4 leads SOT343R

D

y

e

43

E

H

E

AB

X

v M

A

21

b

B

w M

DIMENSIONS (mm are the original dimensions)

A

mm

1.1

0.8

A

max

0.1

UNIT

p

e

1

1

0.4

0.3

b

p

b

1

0.7

0.5

cD

0.25

0.10

b

1

0 1 2 mm

scale

e

E

2.2

1.35

1.15

1.3

1.8

Q

A

A

1

c

L

p

detail X

H

L

e

E

1

2.2

0.45

2.0

0.15

Qwv

p

0.23

0.13

0.2y0.10.21.15

OUTLINE
VERSION

SOT343R

IEC JEDEC EIAJ

REFERENCES

2000 Mar 29 12

EUROPEAN

PROJECTION

ISSUE DATE

97-05-21

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs

BF1201; BF1201R;

BF1201WR

DATA SHEET STATUS

DATA SHEET STATUS

Objective specification Development This data sheet contains the design target or goal specifications for

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be

Product specification Production This data sheet contains final specifications. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese or at anyotherconditions above thosegivenin the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warranty that suchapplicationswillbe
suitable for the specified use without further testing or
modification.

PRODUCT

STATUS

DEFINITIONS

product development. Specification may change in any manner without
notice.

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expectedto result inpersonal injury.Philips
Semiconductorscustomersusing or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of theseproducts,conveys no licence ortitle
under any patent, copyright, or mask work right to these
products,and makes norepresentationsor warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

(1)

2000 Mar 29 13

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR

NOTES

2000 Mar 29 14

Philips Semiconductors Product specification

N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR

NOTES

2000 Mar 29 15

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Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation,Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

69

Printed in The Netherlands 603504/02/pp16 Date of release: 2000 Mar 29 Document order number: 9397 750 06901