Datasheet BF1109WR, BF1109R, BF1109 Datasheet (Philips)

Page 1
DISCRETE SEMICONDUCTORS
DATA SH EET
BF1109; BF1109R; BF1109WR
N-channel dual-gate MOS-FETs
Product specification Supersedes data of 1997 Sep 03 File under Discrete Semiconductors, SC07
1997 Dec 08
Page 2
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
FEATURES
Short channel transistor with high forward transfer admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz
Internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization.
APPLICATIONS
VHF and UHF applications with 9 V supply voltage, such as television tuners and professional communications equipment.
DESCRIPTION
Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1109, BF1109R and BF1109WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively.
PINNING
PIN DESCRIPTION
1 source 2 drain 3 gate 2 4 gate 1
12
Top view
BF1109 marking code: NFp.
Fig.1 Simplified outline
(SOT143B).
34
MSB014
handbook, 2 columns
Top view
BF1109R marking code: NBp.
Fig.2 Simplified outline
(SOT143R).
page
21
Top view
BF1109WR marking code: NB.
Fig.3 Simplified outline
(SOT343R).
43
12
MSB035
43
MSB842
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DS
I
D
P
tot
forward transfer admittance 30 mS
y
fs
C
ig1-ss
C
rss
drain-source voltage −−11 V drain current (DC) −−30 mA total power dissipation T
80 °C −−200 mW
amb
input capacitance at gate 1 2.2 2.7 pF
reverse transfer capacitance f = 1 MHz 25 40 fF F noise figure f = 800 MHz 1.5 2.5 dB X
mod
T
j
cross-modulation input level for k = 1% at 40 dB AGC 100 −−dBµV
operating junction temperature −−150 °C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
Page 3
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. Device mounted on a printed-circuit board.
drain-source voltage 11 V
drain current (DC) 30 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation T
80 °C; note 1 200 mW
amb
storage temperature 65 +150 °C
operating junction temperature +150 °C
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0 40 80 160
120
T
amb
Fig.4 Power derating curve.
MGM243
(°C)
Page 4
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
R
th j-s
Note
1. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
=25°C unless otherwise specified.
T
j
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
(BR)DSS
V
(BR)G1-SS
V
(BR)G2-SS
V
G2-S (th)
I
DSX
I
G1-SS
I
G2-SS
thermal resistance from junction to ambient in free air note 1 350 K/W
thermal resistance from junction to soldering point 200 K/W
drain-source breakdown voltage V
gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
gate 2-source threshold voltage V
self-biasing drain current V
gate 1 cut-off current V
gate 2 cut-off current V
G1-S=VG2-S
= 0; I
G2-S G1-S=VDS
=9V; VDS=9V; ID=20µA 0.3 1.2 V
G1-S
=4V; VDS= 9 V 8 16 mA
G2-S
=9V; V
G1-S G1-S=VDS
= 0; ID=10µA11V
=10µA; ID=0 11 V
G1-S
= 0; I
G2-S
= 0; V
=10µA11V
G2-S
= 0; ID=0 20 nA
=9V 20 nA
G2-S
DYNAMIC CHARACTERISTICS
Common source; T
=25°C; V
amb
= 4 V; VDS= 9 V; self-biasing current; unless otherwise specified.
G2-S
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
y
forward transfer admittance pulsed; Tj=25°C2430mS
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
F noise figure f = 800 MHz; Y G
p
X
mod
input capacitance at gate 1 f = 1 MHz 2.2 2.7 pF
input capacitance at gate 2 f = 1 MHz 1.5 pF
output capacitance f = 1 MHz 1.3 pF
reverse transfer capacitance f = 1 MHz 25 40 fF
S=YS opt
power gain GS= 2 mS; BS=B
BL=B G
S
BL=B
; f = 200 MHz; see Fig.16
L opt
= 3.3 mS; BS=B
; f = 800 MHz; see Fig.17
L opt
; GL= 0.5 mS;
S opt
; GL= 1 mS;
S opt
cross-modulation input level for k = 1% at 0 dB AGC;
fw= 50 MHz; f
= 60 MHz; see Fig.18
unw
input level for k = 1% at 40 dB AGC; f
= 50 MHz; f
w
= 60 MHz; see Fig.18
unw
1.5 2.5 dB
38 dB
20 dB
85 −−dBµV
100 −−dBµV
Page 5
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
25
handbook, halfpage
I
D
(mA)
20
15
10
5
0
010
V
=4V.
G2-S
Tj=25°C.
2468
Fig.5 Output characteristics; typical values.
V
G1
MDA613
= 1.6 V
1.5 V
1.4 V
1.3 V
1.2 V
1.1 V 1 V
VDS (V)
40
handbook, halfpage
I
D
(mA)
30
V
= 4 V
G2-S
20
10
0
0
0.5 2.5
VDS=9V. Tj=25°C.
1 1.5 2
Fig.6 Transfer characteristics; typical values.
MDA614
3.5 V 3 V
2.5 V
2 V
1.5 V
1 V
VG1 (V)
V
G2-S
2.5 V
= 4 V
I
D (mA)
MDA615
3.5 V
3 V
40
handbook, halfpage
y
fs
(mS)
30
20
10
0
0 102030
VDS=9V. Tj=25°C.
2 V
Fig.7 Forward transfer admittance as a function
of drain current; typical values.
16
handbook, halfpage
I
D
(mA)
12
(2)
(3)
(1)
8
(4)
4
0
0
(1) VDS=9V. (2) VDS=7V.
15
234
(3) VDS=5V. (4) VDS=3V.
Fig.8 Drain current as a function of gate 2
voltage; typical values.
V
MDA616
G2-S
(V)
Page 6
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
16
handbook, halfpage
I
D
(mA)
12
8
4
0
02 10
V
=4V.
G2-S
Tj=25°C.
46 8
MDA617
VDS (V)
Fig.9 Drain current as a function of drain-source
voltage; typical values.
2
MDA618
IG1 (µA)
16
handbook, halfpage
I
D
(mA)
12
8
4
0
8 6 40
VDS= 9 V; V
= 4 V; Tj=25°C.
G2-S
Fig.10 Drain current as a function of gate 1 current;
typical values.
120
handbook, halfpage
V
unw
(dBµV)
110
100
90
80
020
VDS= 9 V; V
= 60 MHz; T
f
unw
G2nom
= 4 V; I
amb
Dnom
=25°C.
40 60
gain reduction (dB)
= 12 mA; fw= 50 MHz;
MDA619
Fig.11 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values (see Fig.18).
Page 7
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
2
10
handbook, halfpage
y
is
MDA620
(mS)
10
b
is
1
g
1
10
2
10
10
VDS= 9 V; V ID= 12 mA; T
G2-S
amb
=4V.
=25°C.
is
2
10
f (MHz)
Fig.12 Input admittance as a function of frequency;
typical values.
3
10
handbook, halfpage
MDA621
|yrs|
(mS)
2
10
|yrs|
ϕ
rs
10
3
10
1
10
VDS= 9 V; V ID= 12 mA; T
G2-S
amb
=4V.
=25°C.
2
10
f (MHz)
3
10
ϕ
rs
(deg)
2
10
10
1
3
10
Fig.13 Reverse transfer admittance and phase as
a function of frequency; typical values.
2
10
handbook, halfpage
MDA622
|yfs|
(mS)
10
1
10 10
VDS= 9 V; V ID= 12 mA; T
G2-S
amb
=4V.
=25°C.
2
|yfs|
ϕ
fs
f (MHz)
Fig.14 Forward transfer admittance and phase as
a function of frequency; typical values.
10
ϕ
(deg)
2
fs
10
handbook, halfpage
y
os
(mS)
1
b
os
MDA623
10
1
10
g
os
1
3
10
2
10
10
VDS= 9 V; V ID= 12 mA; T
G2-S
amb
=4V.
=25°C.
2
10
f (MHz)
3
10
Fig.15 Output admittance as a function of
frequency; typical values.
Page 8
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
1 nF
1 nF
pF
V
AGC
47 k
G2
BF1109
BF1109R
G1
BF1109WR
15
BB405
330 k
1 nF
V
input
tun
handbook, full pagewidth
5.5 pF
input 50
VDS= 9 V, GS= 2 mS, GL= 0.5 mS, f = 200 MHz. L1 = 45 nH, 4 turns, internal diameter = 4 mm, 0.8 mm copper wire. L2 = 160 nH, 3 turns, internal diameter = 8 mm, 0.8 mm copper wire; tapped at approximately half a turn from the cold side, to set GL= 0.5 mS. C1 adjusted for GS= 2 mS.
C1
L1
1 nF
D
S
1 nF
1 nF
V
DS
2 µH
1 nF
output
L2
10 pF
BB405
50
330 k
1 nF
V
output
tun
MDA624
Fig.16 Gain test circuit.
handbook, full pagewidth
1 nF
input 50
2 to 18 pF
VDS= 9 V, GS= 3.3 mS, GL= 1 mS, f = 800 MHz. L1 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L2 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L3 = 11 turns 0.5 mm copper wire without spacing, internal diameter = 3 mm, L = approx. 200 nH.
V
AGC
1 nF
47 k
1 nF
G2
BF1109
L1
0.5 to 3.5 pF
G1
BF1109R
BF1109WR
D
S
Fig.17 Gain test circuit.
L2
0.5 to 3.5 pF
V
DS
1 nF
L3
1 nF
4 to 40 pF
output
50
MDA625
Page 9
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
handbook, full pagewidth
R
gen
50
V
i
50
4.7 nF
10 nF
V
G2
G2
G1
10 k
BF1109WR
BF1109
BF1109R
V
DS
4.7 nF
47 µH
10 nF
D
S
R1 = 50
MDA626
Fig.18 Cross-modulation test set-up.
Table 1 Scattering parameters: VDS= 9 V; V
S
f
(MHz)
MAGNITUDE
(ratio)
11
ANGLE
(deg)
MAGNITUDE
(ratio)
= 4 V; ID=12mA
G2-S
S
21
ANGLE
(deg)
S
MAGNITUDE
(ratio)
12
ANGLE
(deg)
S
MAGNITUDE
(ratio)
22
ANGLE
(deg)
50 0.995 3.71 3.013 175.0 0.000 88.2 0.998 1.8 100 0.992 7.29 3.002 170.2 0.001 83.7 0.997 3.5 200 0.984 14.3 2.967 160.7 0.002 86.2 0.995 7.0 300 0.973 21.2 2.922 151.3 0.002 83.2 0.992 10.5 400 0.961 27.9 2.869 142.0 0.003 84.1 0.990 13.9 500 0.944 34.4 2.793 132.9 0.003 85.7 0.987 17.2 600 0.926 40.8 2.730 124.1 0.003 88.4 0.985 20.5 700 0.906 46.9 2.660 1115.3 0.003 94.6 0.983 23.7 800 0.887 52.9 2.605 106.5 0.004 107.2 0.981 26.8 900 0.868 58.8 2.527 97.8 0.004 114.9 0.977 30.0
1000 0.852 64.3 2.457 89.6 0.004 129.7 0.9377 33.1
Table 2 Noise data: V
f
(MHz)
DS
= 9 V; V
= 4 V; ID=12mA
G2-S
F
min
(dB)
800 1.5 0.684 40.94 40.4
Γ
opt
(ratio) (deg)
R
()
n
Page 10
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
PACKAGE OUTLINES
Plastic surface mounted package; 4 leads SOT143B
D
y
e
b
p
B
w M
E
v M
A
B
H
E
A
X
34
Q
A
A
1
21
L
b
1
e
1
detail X
p
c
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
VERSION
1.1
0.9
OUTLINE
SOT143B
1
A
max
0.1
b
c
D
b
0.48
0.38
1
p
0.88
0.15
0.78
0.09
IEC JEDEC EIAJ
E
3.0
1.4
2.8
1.2
REFERENCES
e
1.9
1997 Dec 08 10
e
1.7
H
L
E
1
2.5
2.1
0.45
0.15
p
0.55
0.45
EUROPEAN
PROJECTION
ywvQ
0.1 0.10.2
ISSUE DATE
97-02-28
Page 11
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Plastic surface mounted package; reverse pinning; 4 leads SOT143R
D
y
e
b
p
B
w M
E
v M
A
B
H
E
A
X
43
Q
A
A
1
c
12
L
b
1
e
1
detail X
p
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
VERSION
1.1
0.9
OUTLINE
SOT143R
1
A
max
0.1
b
c
D
b
0.48
0.38
1
p
0.88
0.15
0.78
0.09
IEC JEDEC EIAJ
E
3.0
1.4
2.8
1.2
REFERENCES
e
1.9
1997 Dec 08 11
e
1.7
H
L
E
1
2.5
2.1
0.55
0.25
p
0.45
0.25
EUROPEAN
PROJECTION
ywvQ
0.1 0.10.2
ISSUE DATE
97-03-10
Page 12
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
Plastic surface mounted package; reverse pinning; 4 leads SOT343R
w M
D
y
e
43
21
b
B
p
e
b
1
1
E
H
E
A
A
1
detail X
AB
Q
L
p
X
v M
A
c
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
OUTLINE
VERSION
SOT343R
A
1.1
0.8
max
0.1
1
b
p
0.4
0.3
IEC JEDEC EIAJ
b
1
0.7
0.5
cD
0.25
2.2
0.10
1.8
REFERENCES
E
1.35
1.15
e
1.3
1997 Dec 08 12
H
L
e
E
1
2.2
0.45
2.0
0.15
Qwv
p
0.23
0.13
0.2y0.10.21.15
EUROPEAN
PROJECTION
ISSUE DATE
97-05-21
Page 13
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
DEFINITIONS
Data Sheet Status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Dec 08 13
Page 14
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
NOTES
1997 Dec 08 14
Page 15
Philips Semiconductors Product specification
N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR
NOTES
1997 Dec 08 15
Page 16
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Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997 SCA55 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 117067/00/02/pp16 Date of release: 1997 Dec 08 Document order number: 9397 750 02954
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