Datasheet A8906CLB Datasheet (Allegro)

BIDIRECTIONAL 3-PHASE BRUSHLESS DC MOTOR

CONTROLLER/DRIVER WITH BACK-EMF SENSING

LOAD

C

OUT

OUT

OUT

C

C

WD

C

RES

1

2

D2

3

4

ST

5

A

6

7

8

B

9

9

C

10

11

SUPPLY

GROUND

GROUND

CENTERTAP

BRAKE

ABSOLUTE MAXIMUM RATINGS

Load Supply Voltage, VBB. . . . . . . . . . 14 V

Output Current, I
Logic Supply Voltage, V
Logic Input Voltage Range,

VIN. . . . . . . . . . . -0.3 V to VDD + 0.3 V

Package Power Dissipation, P
Operating Temperature Range,

TA. . . . . . . . . . . . . . . . . . 0°C to +70°C

Junction Temperature, T
Storage Temperature Range,

TS. . . . . . . . . . . . . . . -55°C to +150°C

† Fault conditions that produce excessive junction
temperature will activate device thermal shutdown
circuitry. These conditions can be tolerated, but
should be avoided.

Output current rating may be restricted to a value
determined by system concerns and factors.
These include: system duty cycle and timing,
ambient temperature, and use of any heatsinking
and/or forced cooling. For reliable operation, the
specified maximum junction temperature should
not be exceeded.

V

BB

BOOST

CHARGE

at T

PUMP

OUT

COMMUTATION

DELAY

SERIAL PORT

MUX

FLL

= +25°C

A

V

DD

C

24

23

DATA IN

22

CLOCK

21

CHIP SELECT

20

RESET

19

18

GROUND

DATA OUT

17

16

LOGIC

15

SUPPLY
SECTOR

14

DATA

1312

FILTER

Dwg. PP-040B

. . . . . . . . . . . . ±1.25 A

. . . . . . . . . 6.0 V

DD

See Graph

D

. . . . . . . +150°C†

J

D1

GROUND

OSCILLATOR

8906

The A8906CLB is a bidirectional three-phase brushless dc motor
controller/driver. The three half-bridge outputs are low on-resistance n­channel DMOS devices capable of driving up to 1 A. The A8906CLB
provides complete, reliable, self-contained back-EMF sensing motor
startup and running algorithms. A programmable digital frequency­locked loop speed control circuit together with the linear current control
circuitry provides precise motor speed regulation.

A serial port allows the user to program various features and
modes of operation, such as the speed control parameters, rotational
direction, startup current limit, sleep mode, diagnostic modes, and
others.

The A8906CLB is fabricated in Allegro’s BCD (Bipolar CMOS
DMOS) process, an advanced mixed-signal technology that combines
bipolar, analog and digital CMOS, and DMOS power devices. The
A8906CLB is provided in a 24-lead wide-body SOIC batwing package.
It provides for the smallest possible construction in surface-mount
applications.

PRELIMINARY INFORMATION

FEATURES

■ DMOS Outputs

■ Low r

■ Startup Commutation Circuitry

■ Back-EMF Commutation Circuitry

■ Direction Control

■ Serial Port Interface

■ Frequency-Locked Loop Speed Control

■ Sector Data Tachometer Signal Input

■ Programmable Start-Up Current

■ Diagnostics Mode

■ Sleep Mode

■ Linear Current Control

■ Internal Current Sensing

■ Dynamic Braking Through Serial Port

■ Power-Down Dynamic Braking

■ System Diagnostics Data Out

■ Data Out Ported in Real Time

■ Internal Thermal Shutdown Circuitry

Always order by complete part number, e.g., A8906CLB .

DS(on)

(Subject to change without notice)

March 1, 1999

Data Sheet

26301.4

8906

BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER

FUNCTIONAL BLOCK DIAGRAM

LOGIC

SUPPLY

15

V

DD

CENTERTAP

10

OUT

OUT

OUT

A

B

C

FCOM

LOGIC

BLANK

COMMUTATION

C

D1

24

C

D2

2

COMMUTATION

DELAY

START-UP

C

OSC.

4

ST

BRAKE

11

BRAKE

SEQUENCE

LOGIC

C

RES

12

BOOST

CHARGE

PUMP

V

BB

1

5

8

9

LOAD
SUPPLY

OUT

A

OUT

B

OUT

C

2.5

2.0

1.5

1.0

C

WD

SECTOR

DATA

OSC

DATA IN

R = 55°C/W

θJA

3

14

16

23

FREQUENCY-

LOCKED LOOP

SERIAL PORT MUX

22

21

WATCHDOG

CHARGE

1720

TIMER

PUMP

TSD

13

CURRENT
CONTROL

R

S

6-7

GROUND

18-19

GROUND

FILTER

CHIP

SELECT

R = 6°C/W

θJT

CLOCK

RESET

OUT

DATA

Dwg. FP-034

0.5

0

25

ALLOWABLE PACKAGE POWER DISSIPATION in WATTS

50 75 100 125 150

TEMPERATURE in °C

Dwg. GP-019B

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Copyright © 1999 Allegro MicroSystems, Inc.

8906

BIDIRECTIONAL

3-PHASE BRUSHLESS DC

MOTOR CONTROLLER/DRIVER

ELECTRICAL CHARACTERISTICS at T

= +25°C, V

A

= 5.0 V

DD

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Units

Logic Supply Voltage V
Logic Supply Current I

DD

DD

Operating 4.5 5.0 5.5 V
Operating — 7.5 10 mA

Sleep Mode — 250 500 µA
Load Supply Voltage V
Thermal Shutdown T
Thermal Shutdown Hysteresis ∆T

BB

J

J

Operating 4.0 — 14 V

— 165 — °C
— 20 — °C

Output Drivers

Output Leakage Current I

Total Output ON Resistance r

DSX

DS(on)

VBB = 14 V, V

V

= 14 V, V

BB

I

= 600 mA — 1.0 1.4 Ω

OUT

= 14 V — 1.0 300 µA

OUT

= 0 V — -1.0 -300 µA

OUT

(Source + Sink + RS)
Output Sustaining Voltage V

DS(sus)

Clamp Diode Forward Voltage V

F

V

= 14 V, I

BB

OUT

= I

(MAX), L = 3 mH 14 ——V

OUT

IF = 1.0 A — 1.25 1.5 V

Control Logic

Logic Input Voltage V

Logic Input Current I

DATA Output Voltage V

C

Current I

ST

C

Threshold V

ST

Filter Current I

Filter Threshold V
CD Current I

IN(0)

V

IN(1)

IN(0)

I

IN(1)

OUT(0)

V

OUT(1)

CST

CSTH

V

CSTL

FILTER

FILTERTH

CD

(CD1 or CD2)
C

Current Matching — I

D

CD Threshold V

CDTH

SECTOR DATA, RESET, CLK, -0.3 — 1.5 V

CHIP SELECT, OSC 3.5 — 5.3 V

VIN = 0 V ——-0.5 µA

VIN = 5.0 V ——1.0 µA

I

= 500 µA ——1.5 V

OUT

I

= -500 µA 3.5 —— V

OUT

Charging -9.0 -10 -11 µA

Discharging — 500 — µA

2.25 2.5 2.75 V

0.85 1.0 1.15 V
Charging -9.0 -10 -11 µA
Discharging 9.0 10 11 µA
Leakage, V

= 2.5 V ——5.0 nA

FILTER

1.57 1.85 2.13 V
Charging -18 -20 -22 µA
Discharging 32 40 48 µA

CD(DISCHRG)/ICD(CHRG)

1.8 2.0 2.2 —

2.25 2.5 2.75 V

Continued next page …

8906

BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER

ELECTRICAL CHARACTERISTICS continued

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Units

C

Current I

WD

C

Threshold Voltage V

WD

Max. FLL Oscillator Frequency f
I

(MAX) — D3 = 0, D4 = 0 1.0 1.2 1.4 A

OUT

CWD

V

TH

OSC

TL

Charging -9.0 -10 -11 µA

0.22 0.25 0.28 V

2.25 2.5 2.75 V
VDD = 5.0 V, TA = 25°C12——MHz

D3 = 0, D4 = 1 0.9 1.0 1.1 A
D3 = 1, D4 = 0 0.5 0.6 0.7 A
D3 = 1, D4 = 1 — 250 — mA

BRAKE Threshold V
BRAKE Hysteresis Current I
Transconductance Gain g
Centertap Resistors R

BRK

BRKL

m

CT

Back-EMF Hysteresis — V

SERIAL PORT TIMING CONDITIONS

CHIP SELECT

E

CLOCK

DATA

1.5 1.75 2.0 V

V

= 750 mV — 20 — µA

BRK

0.42 0.50 0.58 A/V

5.0 10 13 kΩ

BEMF

- V

at 5.0 20 37 mV

CTAP

FCOM Transition -5.0 -20 -37 mV

A

C

D C D

B

Dwg. WP-019

A. Minimum CHIP SELECT setup time before CLOCK rising edge.......... 100 ns

B. Minimum CHIP SELECT hold time after CLOCK rising edge............... 150 ns

C. Minimum DATA setup time before CLOCK rising edge........................ 150 ns

D. Minimum DATA hold time after CLOCK rising edge............................. 150 ns

E. Minimum CLOCK low time before CHIP SELECT.................................. 50 ns

F. Maximum CLOCK frequency .............................................................. 3.3 MHz

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

8906

BIDIRECTIONAL

3-PHASE BRUSHLESS DC

MOTOR CONTROLLER/DRIVER

TERMINAL FUNCTIONS

Term. Terminal Name Function

1 LOAD SUPPLY VBB; the 5 V or 12 V motor supply.
2C

3C

4CSTStartup oscillator timing capacitor.
5 OUT

6-7 GROUND Power and logic ground and thermal heat sink.

8 OUT

9 OUT
10 CENTERTAP Motor centertap connection for back-EMF detection circuitry.
11 BRAKE Active low turns ON all three sink drivers shorting the motor windings to ground.

12 C

13 FILTER Analog voltage input to control motor current. Also, compensation node for

14 SECTOR DATA External tachometer input. Can use sector or index pulses from disk to provide

15 LOGIC SUPPLY VDD; the 5 V logic supply.
16 OSCILLATOR Clock input for the speed reference counter. Typical max. frequency is 10 MHz.
17 DATA OUT Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real

18-19 GROUND Power and logic ground and thermal heat sink.

20 RESET When pulled low forces the chip into sleep mode; clears all serial port bits.
21 CHIP SELECT Strobe input (active low) for data word.
22 CLOCK Clock input for serial port.
23 DATA IN Sequential data input for the serial port.
24 C

D2

WD

A

B

C

RES

D1

One of two capacitors used to generate the ideal commutation points from the
back-EMF zero crossing points.

Timing capacitor used by the watchdog circuit to disable the back-EMF compara­tors during commutation transients, and to detect incorrect motor position.

Power amplifier A output to motor.

Power amplifier B output to motor.
Power amplifier C output to motor.

External capacitor and resistor at BRAKE provide brake delay.
External reservoir capacitor used to hold charge to drive the source drivers’

gates. Also provides power for brake circuit.

internal speed control loop.

precise motor speed feedback to internal frequency-locked loop.

time, controlled by 2-bit multiplexer in serial port.

One of two capacitors used to generate the ideal commutation points from the
back-EMF zero crossing points.

8906

BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER

FUNCTIONAL DESCRIPTION

Power Outputs. The power outputs of
the A8906CLB are n-channel DMOS transis­tors with a total source plus sink r

DS(on)

of
typically 1 Ω. Internal charge pump boost
circuitry provides voltage above supply for
driving the high-side DMOS gates. Intrinsic
ground clamp and flyback diodes provide
protection when switching inductive loads and
may be used to rectify motor back-EMF in
power-down conditions. An external Schottky
power diode or pass FET is required in series
with the load supply to allow motor back-EMF
rectification in power down conditions.

Back-EMF Sensing Motor Startup and

Running Algorithm. The A8906CLB pro-

vides a complete self-contained back-EMF
sensing startup and running commutation
scheme. The three half-bridge outputs are
controlled by a state machine. There are six
possible combinations. In each state, one
output is high (sourcing current), one low
(sinking current), and one is OFF (high
impedance or ‘Z’). Motor back EMF is sensed
at the OFF output. The truth table for the
output drivers sequencing is:

Direction

Control OUT

High Low Z

Z Low High

Low Z High

D2 Low

D2 High

Low High Z

Z High Low

High Z Low

A

OUT

B

OUT

C

At startup, the outputs are enabled in one
of the sequencer states shown. The back
EMF is examined at the OFF output by
comparing the output voltage to the motor
centertap voltage at CENTERTAP. The
motor will then either step forward, step
backward, or remain stationary (if in a null­torque position). If the motor moves, the
back-EMF detection circuit waits for the
correct polarity back-EMF zero crossing

(output crossing through centertap). True back-EMF zero crossings are
used by the adaptive commutation delay circuit to advance the state
sequencer (commutate) at the proper time to synchronously run the
motor. Back-EMF zero crossings are indicated by FCOM, an internal
signal that toggles at every zero crossing. FCOM is available at the
DATA OUT terminal via the programmable data out multiplexer.

V

OUTA

V

OUTB

V

OUTC

FCOM

V

SOURCE ON

CTAP

BACK-EMF VOLTAGE

SINK ON

FCOM TOGGLES AT
BACK-EMF ZERO CROSSING

Dwg. WP-016-1

Direction Control. Serial port bit D2 controls the direction of
rotation (see sequencer state table). The motor should be at a com­plete stop before beginning a startup sequence that reverses the
direction of rotation.

Startup Oscillator. If the motor does not move at the initial startup
state, then it is in a null-torque position. In this case, the outputs are
commutated automatically by the startup oscillator after a period set by
the external capacitor at CST where

t

CST

=

4(V

I

ST(charge)

CSTH

- V
+ I

CSTL

) x C

ST(discharge)

ST

In the next state, the motor will move, back EMF will be detected,
and the motor will accelerate synchronously. Once normal synchro­nous back-EMF commutation occurs, the startup oscillator is defeated
by pulses of pulldown current at CST at each commutation, which
prevents CST from reaching its upper threshold and thus completing a
cycle and commutating.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

8906

BIDIRECTIONAL

3-PHASE BRUSHLESS DC

MOTOR CONTROLLER/DRIVER

Adaptive Commutation Delay. The
adaptive commutation delay circuit uses the
back-EMF zero-crossing indicator signal
(FCOM) to determine an optimal commuta­tion time for efficient synchronous operation.
This circuit commutates the outputs, delayed
from the last zero crossing, using two
external timing capacitors, CD1 and CD2,

t

FCOM

FCOM

V

CWD

t

CD1

V

CD1

t

CD2

V

CD2

Dwg. WP-016-2

Blanking and Watchdog Timing Functions. The blanking and

watchdog timing functions are derived from one timing capacitor, CWD.
where t

BLANK

and tWD =

=

VTH x C

VTL x C

I

I

CWD

WD

CWD

WD

The CWD capacitor begins charging at each commutation, initiating
the BLANK signal. BLANK is an internal signal that inhibits the back­EMF comparators during the commutation transients, preventing errors
due to inductive recovery and voltage settling transients.

The watchdog timing function allows time to detect correct motor
position by checking the back-EMF polarity after each commutation. If
the correct polarity is not observed between t

and tWD, then the

BLANK

watchdog timer commutates the outputs to the next state to synchro­nize the motor. This function is useful in preventing excessive reverse
rotation, and helps in resynchronizing (or starting) with a moving
spindle.

V

t

TL

BLANK

Dwg. WP-022

V

CWD

BLANK

to measure the time between crossings.

I

where tCD = t

FCOM

x

I

CD(charge)

CD(discharge)

CD1 charges up with a fixed current from
its 2.5 V reference while FCOM is high.
When FCOM goes low at the next zero
crossing, CD1 is discharged at approximately
twice the charging current. When CD

1

reaches the CD threshold, a commutation
occurs. CD2 operates similarly except on the
opposite phase of FCOM . Thus the com­mutations occur approximately halfway
between zero crossings. The actual delay is
slightly less than halfway to compensate for
electrical delays in the motor, which im­proves efficiency.

V

CWD

BLANK

NORMAL COMMUTATION

V

TL

t

BLANK

t

WD

WATCHDOG-TRIGGERED

COMMUTATION

V

TH

Dwg. WP-021

8906

BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER

Current Control. The A8906CLB provides linear current control
via the FILTER terminal, an analog voltage input. Maximum current
limit is also provided, and is controlled in four steps via the serial port.
Output current is sensed via an internal sense resistor (R

). The

S

voltage across the sense resistor is compared to one-tenth the voltage
at the FILTER terminal less the filter threshold voltage, or to the maxi­mum current limit reference, whichever is lower. This transcon­ductance function is I
nominally 0.2 Ω and V

POWER UP

ERROR FAST

FROM FLL

SPEED-CONTROL

V

DD

ERROR SLOW

C

R

FROM FLL

F1

F1

FILTER

C

I

c

I

d

F2

CHARGE

PUMP

OUT

FILTERTH

YANK

S Q
R

INITIALIZATION

+

x1

–

1.85 V

ERROR FAST
FROM FLL

= (V

FILTER

-V

FILTERTH

is approximately 1.85 V.

V

DD

MUX

–

+

I

V max

FROM
SERIAL PORT
REGISTER
D3 AND D4

MAX CURRENT LIMIT

) / 10RS, where RS is

SEQUENTIAL

LOGIC

C

RES

BOOST

CHARGE

PUMP

+

÷10

–

LINEAR
CURRENT CONTROL

V

BB

R

S

Dwg. EP-046

OUT

Speed Control. The A8906CLB includes a frequency-locked loop
speed control system. This system monitors motor speed via internal
or external digital tachometer signals, generates a precision speed
reference, determines the digital speed error, and corrects the motor
current via an internal charge pump and external filtering components
on the FILTER terminal.

A once per revolution TACH signal can be generated by counting
cycles of FCOM (the number of motor poles must be selected via the
serial port). TACH is then a jitter-free signal that toggles once per
motor revolution. The rising edge of TACH triggers REF, a precision
speed reference derived by a programmable counter. The duration of
REF is set by programming the counter to count the desired number of
OSC cycles

SECTOR

FCOM

OSC

COUNT

(3 x MOTOR POLES)

D20 &
D21

4-BIT

FIXED

COUNTER

ONCE-AROUND

PULSE

SERIAL PORT

REGISTER

D5–D18

14-BIT

PROGRAMMABLE

COUNTER

MUX

D19

REF

÷2

REF

TACH

ERROR

SLOW

REF
TACH
ERROR

FAST

TACH

Dwg. EP-045

60 x f

desired

total count

=

desired motor speed (rpm)

OSC

where the total count (number of oscillator
cycles) is equal to the sum of the selected
(programmed low) count numbers corre­sponding to bits D5 through D18.

The speed error is detected as the
difference in falling edges of TACH and
REF. The speed error signals control the
error-correcting charge pump on the FILTER
terminal, which drive the external loop com­pensation components to correct the motor
current.

Sector Mode. An external tachometer
signal, such as sector or index pulses, may
be used to create the TACH signal, rather
than the internally derived once around. To
use this mode, the signal is input to the
SECTOR terminal, and the sector mode must
be enabled via the serial port. When Switch­ing from the once-around mode to sector
mode, it is important to monitor the SYNC
signal on DATA OUT, and switch modes only
when SYNC is low. This ensures making the
transition without disturbing the speed control
loop. The speed reference counter should be
reprogrammed at the same time.

Speed Loop Initialization (YANK). To
improve the acquire time of the speed control
loop, there is an automatic feature controlled
by an internal YANK signal. The motor is
started at the maximized programmed current
by bypassing the FILTER terminal. The
FILTER terminal is clamped to an internal
reference (the filter threshold voltage),
initializing it near the closed loop operating
point. YANK is enabled at startup and stays
high until the desired speed is reached. Once
the first error-fast occurs, indicating the motor
crossed through the desired speed, YANK
goes low. This releases the clamp on the
FILTER terminal and current control is
returned to FILTER. This feature optimizes
speed acquire and minimizes settling. The
Current Control Block Diagram illustrates the
YANK signal and its effects.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

8906

BIDIRECTIONAL

3-PHASE BRUSHLESS DC

MOTOR CONTROLLER/DRIVER

Serial Port. The serial port functions to write various operational
and diagnostic modes to the A8906CLB. The serial port DATA IN is
enabled/disabled by the CHIP SELECT terminal. When CHIP SE­LECT is high the serial port is disabled and the chip is not affected by
changes in data at the DATA IN or CLOCK terminals.

To write data to the serial port, the CLOCK terminal should be low
prior to the CHIP SELECT terminal going low. Once CHIP SELECT
goes low, information on the DATA IN terminal is read into the shift
register on the positive-going transition of the CLOCK. There are 24
bits in the serial input port.

Data written into the serial port is latched and becomes active
upon the low-to-high transition of the CHIP SELECT terminal at the
end of the write cycle. D0 will be the last bit written to the serial port.

SERIAL PORT BIT DEFINITIONS

D0- Sleep/Run Mode; LOW = Sleep, HIGH = Run

This bit allows the device to be powered down when not in use.

D1- Step Mode; LOW = Normal Operation, HIGH = Step Only

When in the step-only mode the back-EMF commutation circuitry
is disabled and the power outputs are commutated by the start­up oscillator. This mode is intended for device and system
testing.

Bit Number Count Number

D5 16
D6 32
D7 64
D8 128

D9 256
D10 512
D11 1 024
D12 2 048
D13 4 096
D14 8 192
D15 16 384
D16 32 768
D17 65 536
D18 131 072

D19-Speed-control mode switch;

LOW = internal once-around speed signal,
HIGH = external sector data.

D20 and D21-These bits program the number

of motor poles for the once-around FCOM
counter:

D2- Direction; LOW = Forward, HIGH = Reverse.
D3 and D4 - These two bits set the output current limit:

D3 D4 Current Limit

0 0 1.2 A
0 1 1 A
1 0 600 mA
1 1 250 mA

D5 thru D18-This 14-bit word (active low) programs the REF time to set
desired motor speed.

D20 D21 Motor Poles

00 8

01 4

10 16

11 12

D22 and D23-Controls the multiplexer for

DATA OUT:

D22 D23 DATA OUT

0 0 TACH (once around or sector)
0 1 Thermal Shutdown
1 0 SYNC
1 1 FCOM

Reset. The RESET terminal when pulled
low clears all serial port bits, including the D0
latch, which puts the A8906CLB in the sleep
mode.

8906

BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER

V – V

FAULT

C

B

BRAKE

R

B

FAULT D

Braking. A dynamic braking feature of the A8906CLB shorts the
three motor windings to ground. This is accomplished by turning the
three source drivers OFF and the three sink drivers ON. Activation of
the brake can be implemented through the BRAKE input. The supply
voltage for the brake circuitry is the C

voltage, allowing the brake

RES

function to remain active after power failure. Power-down braking with
delay can be implemented by using an external RC and other compo­nents to control the brake terminal, as shown. Brake delay can be set
using the equation below. Once the brake is activated, due to the

BRAKE

ACTIVATED

V

t

BRK

BRK

Dwg. OP-004

inherent capacitive input, the three sink
drivers will remain active until the device is
reset.

V

t

= RBCB 1 – l

BRK

n

BRK

V

FAULT - VD

Centertap. The A8906CLB internally
simulates the centertap voltage of the motor.
To obtain reliable start-up performance from
motor to motor, the motor centertap should be
connected to this terminal.

External Component Selection. Appli­cations information regarding the selection of
external component values is available from
the factory for external component selection,
frequency-locked loop speed control, and
commutation delay capacitor selection.

V

RET

FAULT

BYPASS

R

B

TYPICAL APPLICATION

V

BB

COMMUTATION

V

BB

BOOST

CHARGE

PUMP

DELAY

SERIAL PORT

MUX

FLL

C

B

C

RES

0.22 µF

1

2

C

D2

3

C

WD

4

C

ST

5

6

7

8

9

9

10

11

24

23

22

21

20

19

18

17

16

V

15

DD

14

1312

DATA IN

CLOCK

CHIP SELECT

RESET

BYPASS

+5 V

SECTOR
DATA

C

D1

DATA OUT

OSC (REF)

R

F1

C

F2

Dwg. EP-036C

C

F1

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]

MOTOR CONTROLLER/DRIVER

°

°

Dimensions in Inches

(for reference only)

8906

BIDIRECTIONAL

3-PHASE BRUSHLESS DC

0.2992

0.2914

0.020

0.013

0.0926

0.1043

24 13

1 2

3

0.6141

0.5985

0.0040

MIN

.

Dimensions in Millimeters

(controlling dimensions)

24 13

0.050

BSC

NOTE 1
NOTE 3

0.0125

0.0091

0.491

0.394

0.050

0.016

0° TO 8

Dwg. MA-008-25 in

0.32

0.23

7.60

7.40

0.51

0.33

2.65

2.35

1 2

0.10 MIN

10.65

10.00

1.27

0.40

3

15.60

15.20

.

NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.

1.27

BSC

NOTE 1
NOTE 3

2. Lead spacing tolerance is non-cumulative.

3. Exact body and lead configuration at vendor’s option within limits shown.

0° TO 8

Dwg. MA-008-25A mm

8906

BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER

Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the design of its products.

The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibil­ity for its use; nor for any infringements of patents or other rights of third
parties which may result from its use.

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]