19.3Repairing soldered joints
20DEFINITIONS
21LIFE SUPPORT APPLICATIONS
22PURCHASE OF PHILIPS I2C COMPONENTS
1996 Nov 292
Page 3
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
1FEATURES
1.1PCF84CXXXA kernel
• 8-bit CPU, ROM, RAM, I/O in a single 42 leads shrink
DIL package
• Over 80 instructions all of 1 or 2 cycles
• 29 quasi-bidirectional standard I/O port lines
• Configuration of I/O lines individually selected by mask
• External interrupt
• 2 direct testable inputs T0 and T1
• 8-bit programmable timer/event counter
• 3 single level vectored interrupts (external,
timer/counter, I2C-bus)
• Power-on-reset and low voltage detector
• Single power supply
• 2 power reduction modes: Idle and Stop
• Operating temperature range: −20 to +70 °C
• Silicon gate CMOS fabrication process (SAC2).
1.2Derivative features PCA84C640
Although the PCA84C640 is specifically referred to
throughout this data sheet, the information applies to all
the devices. The small differences between the 84C640
and the other devices are specified in the text and also
highlighted in Chapter 6.
The PCA84C640 comprises:
• The PCF84CXXXA processor core
• 6 kbytes mask-programmable program ROM
• 128 bytes RAM
• Multi-master I
• AFC input for Voltage Synthesized Tuning
(VST; with 3-bit DAC and comparator)
• On Screen Display (OSD) facility for two rows of
16-characters
• On Screen Display character set of 64 types
INT/T0
2
C-bus interface
• Four programmable display dot sizes
• Half dot character rounding
• Seven colours for each character
• One 14-bit PWM output for VST
• Five 6-bit PWM outputs for analog controls
• Eight port lines with 10 mA LED drive capability
• 18 general purpose bidirectional I/O lines
plus 11 function-combined I/O lines
• 2 direct testable lines
• Programmable VSYNCN and HSYNCN input polarity
• RC oscillator for OSD function.
2GENERAL DESCRIPTION
The 84C44X; 84C64X; 84C84X denotes the types:
• PCA84C440; 84C441; 84C443; 84C444
• PCA84C640; 84C641; 84C643; 84C644
• PCA84C840; 84C841; 84C843; 84C844.
which are 8-bit microcontrollers with On Screen Display
(OSD) and Voltage Synthesized Tuning (VST) functions.
All are members of the 84CXXX microcontroller family.
There are two oscillator types for the OSD function in the
various types, i.e.,
This data sheet details the specific properties of the
PCA84C44X, PCA84C64X and PCA84C84X.
The shared characteristics of the PCA84CXXX family of
microcontrollers are described in the PCF84CXXXA
Family single-chip 8-bit Microcontroller of
IC14”
, which should be read in conjunction with this data
General purpose I/O lines 181718171817181718171817
Table 2 Differences between the types PCA84C44X, PCA84C64X and PCA84C84X
In this table: yes = available; no = not available.
1996 Nov 297
I
Latchyesnoyesnoyesnoyesnoyesnoyesno
Page 8
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
7RESET
The RESET pin (active LOW input) is used to initialize the
microcontroller to a defined state. The Reset configuration
is shown in Fig.5.
V
ndbook, halfpage
R ≤ 100 kΩ
RESET
C
MCD174
DD
V
SS
Fig.4 External components for RESET pin.
7.1Power-on-reset
The Power-on-reset circuit monitors the voltage level of
VDD. If VDD remains below the internal reference voltage
level V
When VDD rises above V
(typically 1.3 V), the oscillator is inhibited.
ref
, the oscillator is released and
ref
the internal reset is active for a period of td (typically
50 µs).
Considering the VDD rise time, the following measures for
a correct Power-on-reset can be taken:
• If the VDD rises above the minimum operation voltage
before time period t
is exceeded, no external
d
components are necessary (see Fig.6).
• If V
has a slow rise time, such that after the time
DD
period (t
Vref+td
) has elapsed the supply voltage is still
below the minimum operation voltage (V
min
),
external components are required (see Figs 4 and 7).
To guarantee a correct reset operation, ensure that the
time constant RC ≥ 8 × t
VDD
.
A definite Power-on-reset can be realized by applying an
(external)
RESET signal during power-on.
handbook, full pagewidth
V
ref
internal
reset
oscillator
inhibit
POWER-ON-RESET
Fig.5 Reset configuration.
MLA651
V
DD
RESET
V
SS
1996 Nov 298
Page 9
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
handbook, full pagewidth
V
RESET
OSCILLATOR
handbook, full pagewidth
V
DD
RESET
without
external
component
RESET
with
external
component
DD
V
DD
V
ref
V
SS
V
DD
V
SS
t
d
oscillator start up time
MCD240
Fig.6 Reset with fast rising VDD.
V
DD
V
min
V
ref
V
SS
t
VDD
V
DD
V
SS
t
Vref
V
DD
V
SS
t
d
RC ≥ 8 × t
VDD
OSCILLATOR
Fig.7 Reset with slow VDD.
1996 Nov 299
oscillator start up time
MCD241
Page 10
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
8ANALOG CONTROL
8.16-bit PWM DACs
Five PWM outputs are available for analog control
purposes e.g. volume, balance, brightness, saturation, etc.
The block diagram of a typical 6-bit PWM DAC is shown in
Fig.8. Each PWM output can generate pulses of
programmable length that have a repetition frequency of
1
⁄64× f
8.1.1P
, where f
PWM
IN SELECTION FOR PWM OUTPUTS
PWM
=1⁄3× f
XTAL
.
The PWM outputs PWM1 to PWM5, share the same pins
as the Derivative Port lines DP0.1 to DP0.5.
Setting the (relevant PWM enable) bit PWMnE to:
• Logic 1, selects the relevant PWMx output function
• Logic 0, selects the relevant DP0.x Port function.
8.1.2P
OLARITY OF THE PWM OUTPUTS
The polarity of all five PWM outputs is selected by the state
of the polarity control bit P6LVL.
Setting the control bit P6LVL to:
• Logic 0, sets the PWMx outputs to the default polarity
• Logic 1, inverts all the PWMx outputs.
8.1.3A
NALOG OUTPUT VOLTAGE
A DC voltage proportional to the PWM control setting may
be obtained by connecting an integrating network to each
of the PWM outputs (see Fig.9).
The analog value is calculated as follows:
t
HIGH
V
------------- t
r
×=
O
V
A
Where:
•
t
HIGHt0
t
•
•
t
r
0
=
t
------------- -
0
f
PWMDL×HIGH time of the PWM pulse==
64×repetition time of the PWM pulse==
3
XTAL
• PWMDL is the decimal value of the contents of the
PWM data latch.
Therefore, the analog output voltage is:
V
A
PWMDL
----------------------- 64
×=
V
O
handbook, full pagewidth
f
PWM
6-BIT PWM DATA LATCH
6-BIT DAC PWM
CONTROLLER
Q
Q
Fig.8 Block diagram of the 6-bit PWM DAC.
1996 Nov 2910
P6LVL
DP0.x data
I/O
PWMnE
polarity control bit
DP0.x/PWMx
MCD176
Page 11
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
t
handbook, full pagewidth
f
PWM
00
01
m
63
0
6413mm + 1m + 263641
2
decimal value PWM data latch
Fig.9 PWM output patterns (P6LVL = 0).
MCD175
1996 Nov 2911
Page 12
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
9VST CONTROL
9.114-bit PWM DAC
The PCA84C640 has one 14-bit PWM DAC output (TDAC)
with a resolution of 16384 levels for Voltage Synthesized
Tuning. The PWM DAC (see Fig.10) consists of:
• 14-bit counter
• Two 7-bit DAC interface data latches (VSTH and VSTL)
• One 14-bit DAC data latch (VSTREG)
• Pulse control.
The polarity of output TDAC is selected with bit P14LVL.
Setting the bit P14LVL to:
• Logic 1, sets the TDAC output to the default polarity
• Logic 0, inverts the TDAC output.
9.1.114-
BIT COUNTER
The counter is continuously running and is clocked by f0.
The period of the clock,
t
3
=
------------- -
0
f
XTAL
The repetition time for one complete cycle of the counter:
t
rt0
16384×=
The repetition time for one cycle of the lower 7-bits of the
counter is:
t
subt0
Therefore, the number of t
128×=
periods in a complete
sub
cycle tr is:
t
16384×
0
N
--------------------------t
0
9.1.2D
128×
ATA AND INTERFACE LATCHES
128==
In order to ensure correct operation, interface data latch
VSTH is loaded first and then interface data latch VSTL.
The contents of:
• VSTH are used for coarse adjustment
• VSTL are used for fine adjustment.
9.2Coarse adjustment
The coarse adjustment output (OUT1) is reset to LOW
(inactive) at the start of each t
It will remain LOW until the timehas
period.
sub
t0VSTH 1+()×[]
elapsed and then will go HIGH and remain so until the next
t
period starts.
sub
9.3Fine adjustment
Fine adjustment is achieved by generating additional
pulses at the start of particular sub-periods (t
subn
).
These additional pulses have a width of t0.
The sub-period in which a pulse is added is determined by
the contents of VSTL interface latch.
Table 3 gives the numbers of the t
, at the start of which
subn
an additional pulse is generated, depending on the bit in
VSTL being a logic 0. When more than one bit is a logic 0
a combination of additional pulses are generated.
For example, if VSTL = 1111010, which is a combination
of
• VSTL = 1111110: sub-period 64, and
• VSTL = 1111011: sub-periods 16, 48, 80 and 112,
then additional pulses will be given in sub-periods
16, 48, 64, 80 and 112; this is illustrated in Fig.12.
If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0,
then the TDAC output is as shown in Fig.13.
of VSTL, both data latches are loaded into data latch
VSTREG. After the contents of VSTH and VSTL are
latched into VSTREG, one t
period is needed to
sub
generate the appropriate pulse pattern.
To ensure correct DAC conversion, two (2) t
periods
sub
should be allowed before beginning the next sequence.
1996 Nov 2912
Page 13
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
handbook, full pagewidth
'MOV instruction'
DATA LOAD
TIMING PULSE
polarity
control bit
DATA LATCH VSTH
P14LVL
DATA LATCH VSTL
77
LOAD
DAC DATA LATCH VSTREG
77
COARSE PWMFINE
OUT2OUT1
ADD
Q
Q14 to Q8Q7 to Q1
14-BIT COUNTER
Q
'MOV instruction'
TDAC output
f
0
Fig.10 Block diagram of the 14-bit PWM DAC.
ndbook, full pagewidth
OUT 1
t
sub0
t0 × (VSTH + 1)
t
sub1
Fig.11 Coarse adjustment output (OUT1).
1996 Nov 2913
MCD177
t
r
t
subn
t
sub127
MCD313
Page 14
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
t
handbook, full pagewidth
r
111 1110
111 1101
111 1011
111 1010
VSTL
t
sub0
t
sub16
t
sub32
t
sub48
t
sub64
t
sub80
Fig.12 Fine adjustment output (OUT2).
t
sub96
t
sub112
t
sub127
MCD314
handbook, full pagewidth
OUT 1
OUT 2
TDAC
t
sub0
t
sub16
t
sub32
t
sub48
Fig.13 TDAC output.
1996 Nov 2914
t
t
sub64
r
t
sub80
t
sub96
t
sub112
t
sub127
MCD315
Page 15
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
10 AFC INPUT
The AFC input is used to measure the level of the
Automatic Frequency Control signal. This is achieved by
comparing the AFC input signal with the output of a 3-bit
DAC as shown in Fig.14. DAC analog switches select one
of 8 resistor taps connected between VDD and VSS.
Consequently, eight different voltages may be selected
(see Table 4). The compare signal AFCC, can be tested to
determine whether the AFC input is higher or lower than
the DAC level.
The AFC input shares the same pin as the Derivative Port
line DP1.7. Setting the enable bit AFCE to:
• Logic 1, selects the AFC function
• Logic 0, selects the Derivative Port DP1.7 function.
handbook, full pagewidth
DP1.7
Table 4 Selection of V
ref
AFC2 AFC1 AFC0V
000V
001V
010V
011V
100V
101V
110V
DD
DD
DD
DD
DD
DD
DD
111 V
internal bus
V
ref
(for VDD= 5.0 V)
ref
× 0.1250.625 V
× 0.2501.250 V
× 0.3751.875 V
× 0.5002.500 V
× 0.6253.125 V
× 0.7503.750 V
× 0.8754.375 V
DD
5.000 V
DP1.7/AFC
COMPARATOR
EN
3-BIT DACEN
AFC2AFC1AFC0AFCE
Fig.14 AFC circuit.
AFCC
inner latches
MCD178
1996 Nov 2915
Page 16
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
11 INPUT/OUTPUT (I/O)
Each parallel I/O port line may be individually configured
using one of three possible I/O mask options.
The three I/O mask options are specified below:
Option 1 Standard port with switched pull-up current
Table 5 specifies the possible port option list. When these
devices are used for emulation purposes, in order to match
the piggy back device provided it is recommended that the
port options listed in Table 6 are used.
V
DD
I/O PORT
LINE
IN/MOV
TR2
TR1
constant
current
TR3
V
SS
source
100 µA typ.
MLA696
handbook, full pagewidth
Fig.15 Standard output with switched pull-up current source (Option 1).
WRITE PULSE
OUTL/ORL/ANL
DATA BUS
D
MQ
MASTER
ORL/ANL
D
SLAVE
SQ
SQ
TR1
IN
V
DD
V
SS
MLA697
Fig.16 Open drain type I/O (Option 2).
I/O PORT
LINE
1996 Nov 2916
Page 17
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
handbook, full pagewidth
WRITE PULSE
OUTL/OR /ANL
DATA BUS
D
D
MQ
MASTER
ORL/ANL
SQ
SLAVE
SQ
IN
Fig.17 Push-pull type output (Option 3).
TR2
TR1
V
DD
constant
current
source
100 µA typ.
OUTPUT
LINE
V
SS
MGD864
1996 Nov 2917
Page 18
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
1. Each pin can be configured to a HIGH (S) or LOW (R)
state after power-on-reset. The required state of each
pin is therefore specified by R or S.
2. DP1.4 available only with the PCA84C440,
PCA84C443, PCA84C640, PCA84C643,
PCA84C840 and PCA84C843.
1996 Nov 2918
Page 19
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12 ON SCREEN DISPLAY
12.1Features
• Display format: 2 rows × 16 characters
• Software controlled vertical and horizontal display
position
• 64 different (mask programmable) characters in ROM
• Black box background
• Four programmable display character sizes
• Four programmable character dot matrix sizes:
–6×9 and 6 × 13
–8×9 and 8 × 13
• Half-dot rounding for the whole screen
• 4 from 7 colours possible on screen
• Clock generator for On Screen Display function with:
– RC oscillator
– LC oscillator,
for the various types of PCA84C44X; 84C64X; 84C84X.
12.2Horizontal display position control
The horizontal position counter is incremented every OSD
cycle after the programmed level of HSYNCN occurs at the
HSYNCN pin. The counter is reset when the opposite
polarity of the HSYNCN pulse is reached.
12.4Clock generator
There are two types of oscillators available for the various
types. The oscillator is triggered on the trailing edge of
HSYNCN when the OSD logic is enabled and stops on the
following leading edge of HSYNCN.
The OSD oscillator must be externally adjusted to the
desired frequency (decreasing the OSD frequency gives
broader characters). Before the oscillation frequency can
be adjusted HSYNCN must be HIGH (if HLVL = 1).
Oscillation stops by setting the HSYNCN pin LOW when
HLVL = 1.
12.4.1RC
The RC oscillator is available in the types:
The external LC network is connected between
pins 28 and 29 (see Fig.20).
OSCILLATOR
OSCILLATOR
12.3Vertical display position control
The vertical position counter is incremented every
HSYNCN cycle and is reset by the VSYNCN signal.
1996 Nov 2919
Page 20
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
handbook, full pagewidth
(1) See Figs 19 and 20 for connection of external components.
VSYNCN
HSYNCN
VERTICAL
DISPLAY
POSITION
CONTROL
HORIZONTAL
DISPLAY
POSITION
CONTROL
CLOCK
GENERATOR
(1)
DISPLAY
CONTROL
MEMORY
CONTROL
TIMING
GENERATOR
VOB
VOW1
VOW2
VOW3
Fig.18 OSD block diagram.
DISPLAY
CHARACTER
DATA
MEMORY
CHARACTER
ROM
DISPLAY
CONTROL
MCD179
V
MCD173
DD
V
SS
handbook, halfpage
R
DOSC1
C
Fig.19 RC oscillator.Fig.20 LC oscillator.
1996 Nov 2920
handbook, halfpage
C1
DOSC1
L1
C2
DOSC2
MCD247
Page 21
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12.5Display data registers
The display data registers consists of a group of 32 derivative registers located at addresses 20H to 3FH inclusive
(see Table 7). At power-up the contents of the display data registers are undefined.
The format of each display data register is shown in Table 8, and their functions described in Table 9.
20H to 2FHRow 0 = the first display row
30H to 3FHRow 1 = the second display row
Table 8 Display data register (address 20H to 3FH)
76543210
CC1CC0MD5MD4MD3MD2MD1MD0
Table 9 Description of display data register bits
CC1CC0MD5MD4MD3MD2MD1MD0
BITSYMBOLDESCRIPTION
7CC1Colour code. The state of these two bits enable individual characters to be displayed in
6CC0
5MD5Character code.
4MD4
3MD3
2MD2
1MD1
0MD0
12.6Display control registers
The display control registers consists of a group of 6 derivative registers located at addresses 40H to 45H inclusive
(see Table 10). Each register may be read from or written to. After a reset operation the contents of the display control
registers are zero.
The character set is stored in ROM and consists of 64 different characters.
The selection of each character is dependent on the state of the 6 bits, MD0 to MD5.
1996 Nov 2921
Page 22
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12.6.1DERIVATIVE REGISTER OSDCA
Table 11 Derivative register OSDCA (address 40H)
76543210
CC34CC24CC14RBLKROUNDSTBYVLVLHLVL
Table 12 Description of OSCDA bits
BIT SYMBOLDESCRIPTION
7CC34Character colour code bits.
6CC24
5CC14
4RBLKRaster blanking control (see Fig.24). When the RBLK bit is:
3ROUNDCharacter rounding control (see Figs 22 and 23). The rounding function generates half dots where
2STBYStand-by. This bit is used to enable or disable the OSD facility. When the STBY bit is:
1VLVLVertical synchronous signal level (see Fig.21).
0HLVLHorizontal synchronous signal level (see Fig.21).
These bits are used for colour selection purposes. See Table 24.
Logic 1, the VOB output is driven HIGH to display the OSD characters on a blank screen.
Logic 0, the VOB output returns to its normal output state on the trailing edge of VSYNCN.
the corners of two dots meet. The rounding function also works with multiple cell characters.
When the ROUND bit is:
Logic 1, the rounding function is enabled.
Logic 0, the rounding function is disabled.
Logic 1, the OSD oscillator is disabled.
Logic 0, the OSD oscillator is enabled and the OSD facility is available.
This bit selects the active level of the VSYNCN input signal. When the VLVL bit is:
Logic 1, VSYNCN is active HIGH.
Logic 0, VSYNCN is active LOW.
This bit selects the active level of the HSYNCN input signal. When the HLVL bit is:
Logic 1, HSYNCN is active HIGH.
Logic 0, HSYNCN is active LOW.
handbook, full pagewidth
HSYNCN
(VSYNCN)
HSYNCN
(VSYNCN)
characters can be displayed
Fig.21 VSYNCN and HSYNCN active level.
1996 Nov 2922
(HLVL = VLVL = 1)
(HLVL = VLVL = 0)
MCD180
Page 23
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
ROUND = 1ROUND = 0
H
H
handbook, halfpage
H
H
TTT
handbook, full pagewidth
VSYNCN
H
H
Fig.22 Rounding function.
RBLK
MCD181
TTT
MCD246
Fig.23 Rounding effect.
VOB
VOW1, 2, 3
= normal output
Fig.24 Raster blanking timing RLBK.
1996 Nov 2923
MCD316
Page 24
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12.6.2DERIVATIVE REGISTERS LINE 0A AND LINE 0B
REGISTERFUNCTION
LINE 0ADetermine the character size and vertical position of Row 0 (the first display row).
LINE 0BDetermine the horizontal position of Row 0 and the selection of background and blanking functions.
Table 13 Derivative register LINE 0A (address 41H)
76543210
SZ01SZ00VP05VP04VP03VP02VP01VP00
Table 14 Description of LINE 0A bits
BIT SYMBOLDESCRIPTION
7SZ01Character size. The state of these two bits enable one of four possible character sizes to be
6SZ00
5VP05Vertical position control.
4VP04
3VP03
2VP02
1VP01
0VP00
selected for Row 0. Character sizes include background. See Table 23.
The vertical position of Row 0 is selected by the state of the 6 bits, VP00 to VP05.
For details see Section 12.7.1 “Vertical position”.
Table 15 Derivative register LINE 0B (address 42H)
76543210
BLK0VB0HP05HP04HP03HP02HP01HP00
Table 16 Description of LINE 0B bits
BIT SYMBOLDESCRIPTION
7BLK0Blanking. This bit enables or disables the character display. When BLK0 is set to:
Logic 1, the outputs VOW1, VOW2, VOW3 and VOB are enabled; characters are displayed.
Logic 0, the outputs VOW1, VOW2, VOW3 and VOB are disabled; no characters are displayed.
6VB0Background. This bit determines whether the background display is selected or not.
The visual effect of background versus no background is shown in Fig.26. When VB0 is set to:
Logic 1, the characters in this row are displayed with background.
Logic 0, the background is disabled and only the characters are displayed.
5HP05Horizontal position control.
4HP04
3HP03
2HP02
1HP01
0HP00
These 6 bits determine the start position of Row 0.
The horizontal position control is only active during OSDC clock cycles.
For details Section 12.7.2 “Horizontal position” and Fig.25.
1996 Nov 2924
Page 25
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12.6.3DERIVATIVE REGISTERS LINE 1A AND LINE 1B
REGISTERFUNCTION
LINE 1ADetermine the character size and vertical position of Row 1 (the second display row).
LINE 1BDetermine the horizontal position of Row 1 and the selection of background and blanking functions.
Table 17 Derivative register LINE 1A (address 44H)
76543210
SZ11SZ10VP15VP14VP13VP12VP11VP10
Table 18 Description of LINE 1A bits
BIT SYMBOLDESCRIPTION
7SZ11Character size. The state of these two bits enable one of four possible character sizes to be
6SZ10
5VP15Vertical position control.
4VP14
3VP13
2VP12
1VP11
0VP10
selected for Row 1. Character sizes include background. See Table 23.
The vertical position of Row 1 is selected by the state of the 6 bits, VP10 to VP15.
For details see Section 12.7.1 “Vertical position”.
Table 19 Derivative register LINE 1B (address 45H)
76543210
BLK1VB1HP15HP14HP13HP12HP11HP10
Table 20 Description of LINE 1B bits
BIT SYMBOLDESCRIPTION
7BLK1Blanking. This bit enables or disables the character display. When BLK1 is:
Logic 0, the outputs VOW1, VOW2, VOW3 and VOB are disabled; no characters are displayed.
Logic 1, the outputs VOW1, VOW2, VOW3 and VOB are enabled; characters are displayed.
6VB1Background. This bit determines whether the background display is selected or not.
The visual effect of background versus no background is shown in Fig.26. When VB1 is set to:
Logic 1, the characters in this line are displayed with background.
Logic 0, the background is disabled and only the character is displayed.
5HP15Horizontal position control.
4HP14
3HP13
2HP12
1HP11
0HP10
These 6 bits determine the start position of Row 1.
The horizontal position control is only active during OSDC clock cycles.
For details Section 12.7.2 “Horizontal position” and Fig.25.
1996 Nov 2925
Page 26
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12.6.4DERIVATIVE REGISTER OSDCB
REGISTERFUNCTION
OSDCBDetermine the selection of:
• The size of the dot matrix grid
• Four colours from a possible seven for the display.
Table 21 Derivative register OSDCB (address 43H)
76543210
CDTWCDTHCC33CC23CC32CC12CC21CC11
Table 22 Description of OSDCB bits
BIT SYMBOLDESCRIPTION
7CDTWCharacter dot width control.The state of this bit determines the dot width of the character. When
the CDTW bit is set to:
Logic 1, the character width is 6 dots.
Logic 0, the character width is 8 dots.
6CDTHCharacter dot height control. The state of this bit determines the dot height of the character. When
the CDTH bit is set to:
Logic 1, the character height is 13 dots.
Logic 0, the character height is 9 dots.
5CC33Colour control bits.
4CC23
3CC32
2CC12
1CC21
0CC11
In every VSYNCN cycle one screen can select any 4 colours from 7 and in addition a blank or black
screen. Combinations of CC1X, CC2X and CC3X control the character outputs VOW1, VOW2 and
VOW3 as shown in Table 24.
1996 Nov 2926
Page 27
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12.7OSD display position
12.7.1V
ERTICAL POSITION
The line number of the vertical start position for:
• Row 0 is 4 × (VP00 → VP05)
• Row 1 is 4 × (VP10 → VP15).
Where:
• (VP00 → VP05) = the decimal value of VP00 → VP05
• (VP10 → VP15) = the decimal value of VP10 → VP15.
The character height in:
• Row 0 is H0 and is a function of the number of dots per
character and the state of the size control bits
SZ00 and SZ01
• Row 1 is H1 and is a function of the number of dots per
character and the state of the size control bits
SZ10 and SZ11.
Row 0 and Row 1 must not overlap each other and
therefore: VP1 ≥ (VP0 + H0); see Fig.25.
The four possible character heights are shown in Table 23.
12.7.2H
ORIZONTAL POSITION
The horizontal start position (HP) of,
• Row 0: HP0 = 4 × (HP00 → HP05) + 5 × t
• Row 1: HP1 = 4 × (HP10 → HP15) + 5 × t
OSCD
OSCD
Where:
• (HP00 → HP05) = the decimal value of HP00 → HP05
and (HP00 → HP05) > 10
• (HP10 → HP15) = the decimal value of HP10 → HP15
and (HP10 → HP15) > 10
• t
= one OSCD clock period.
OSCD
Therefore for both Row 0 and Row 1,
HP0, HP1 ≥ 45 × t
OSCD
.
HP0
VP0
handbook, halfpage
with backgroundwithout background
ROW 0 CHARACTERS
HP1
H0
ROW 1 CHARACTERS
VP1
MCD183
Fig.25 Display position.Fig.26 Background versus no background.
MCD182
1996 Nov 2927
Page 28
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12.8OSD character size and colour selection
12.8.1C
HARACTER SIZE
The character sizes are selected by bits SZn1 and SZn0,
which denotes:
• SZ01 and SZ00 for Row 0
The character sizes are determined by the bits:
• SZ11 and SZ10 for Row 1.
• CDTW, for the width
• CDTH, for the height.
Table 23 Character sizes selection
H denotes one horizontal line, T denotes one OSDC clock period and D denotes dots per character width/height.
12.8.2COLOUR SELECTION
Colour selection is achieved using bits in the,
• OSDCA register: CC34, CC24 and CC14
• OSDCB register: CC33, CC23, CC32, CC12,
In this way every combination of four colours can be made
(black and white can not be displayed at the same time).
The user may choose one colour out of each block.
Table 24 shows the selection of the output combinations.
Tables 25 and 26 show the possible colour combinations.
CC21, and CC11
• Display data registers: CC1 and CC0.
handbook, full pagewidth
CHARACTER ROM
DISPLAY DATA
MEMORY
DISPLAY CIRCUIT
CONTROL REGISTERS
MCD184
dot
CC1
CC0
CCxx
background control
Fig.27 Colour control.
1996 Nov 2928
OUTPUT
CONTROL
LOGIC
OR
VOW1
VOW2
VOW3
VOB
Page 29
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
12.9Character ROM
Character ROM contains the dot character fonts.
13 × 8 dots are reserved for each character, regardless of
the dot matrix size actually selected.
The dot matrix grid is shown in Fig.28.
Philips provides a software under MS DOS environment
(IBM/PC or compatible) to help customer to design the
character font on the screen and to generate the bit pattern
HEX decimal file automatically.
Contact your local Philips Sales Organization for details.
12345678
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
MCD185
13 EMULATION MODE
The emulation mode configuration is shown in Fig.29.
In the emulation mode configuration the PCA84C640’s
CPU is disabled and only its derivative logic is active.
The device is controlled by the PCF84C00 bond-out chip.
The PCA84C640's two derivative ports act as additional
ports for the PCF84C00. The interaction between the two
devices is as follows:
1. During the first machine cycle the PCF84C00 fetches
an instruction from EPROM and then decodes that
instruction.
2. During the second machine cycle the PCF84C00
executes the decoded instruction. If the instruction is
related to the derivative ports then DXALE, DXRDN
and/or DXWRN become active and the PCA84C640
operates as a peripheral of the PCF84C00.
3. Depending on the type of instruction executed during
the second machine cycle the following data transfer
happens:
a) During TS1 data from the EPROM is available on
P0.0 to P0.7 which is then available on IB0.0 of the
PCF84C00.
b) During TS4 data from the PCA84C640 can be
transferred to the PCF84C00.
c) During TS6 data from the PCF84C00 can be
transferred to the PCA84C640.
Fig.28 Character ROM.
1996 Nov 2930
Page 31
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
handbook, full pagewidth
P0.0 to P0.7
P1.0 to P1.7
P2.0 to P2.7
PCF84C00
XTAL1
RESET
XTAL2
XTAL1
RESET
PCA84C640
DP0.0 to DP0.7
DP1.0 to DP1.7
PSEN
A0 to A12
D0 to D7
STFF
DXALE
DXRD
DXWR
P1.0
P1.1
P1.2
P1.3
P0.0 to P0.7
TEST/EMU
address bus
CE
A0 to A12
data bus
D0 to D7
EPROM
MCD317
+5 V
Fig.29 Emulation mode configuration.
1996 Nov 2931
Page 32
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
14 REGISTER MAP
The number within parentheses denotes the initial state; ‘X’ denotes don’t care.
R = Read, W = Write, R/W = Read/Write.
1. These bits are not available in the PCA84C441, PCA84C444, PCA84C641, PCA84C644,
PCA84C841 and PCA84C844.
CC24
(0)
SZ00
(0)
VB0
(0)
CDTH
(0)
SZ10
(0)
VB1
(0)
CC14
(0)
VP05
(0)
HP05
(0)
CC33
(0)
VP15
(0)
HP15
(0)
RBLK
(0)
VP04
(0)
HP04
(0)
CC23
(0)
VP14
(0)
HP14
(0)
ROUND
(0)
VP03
(0)
HP03
(0)
CC32
(0)
VP13
(0)
HP13
(0)
STBY
(1)
VP02
(0)
HP02
(1)
CC12
(1)
VP12
(1)
HP12
(1)
VLVL
(0)
VP01
(0)
HP01
(0)
CC21
(0)
VP11
(0)
HP11
(0)
HLVL
(0)
VP00
(0)
HP00
(0)
CCV11
(0)
VP10
(0)
HP10
(0)
R/W
R/W
R/W
R/W
R/W
R/W
15 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOLPARAMETERMIN.MAX.UNIT
V
V
I
I
P
T
T
DD
I
OH
OL
tot
stg
amb
supply voltage−0.3+7.0V
input voltage (all inputs)−0.3VDD+ 0.3 V
maximum source current for all port lines−−10mA
maximum sink current for all port lines−−30mA
total power dissipation−900mW
storage temperature−55+125°C
operating ambient temperature (for all devices)−20+70°C
1996 Nov 2933
Page 34
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
max.
mm
5.080.514.0
OUTLINE
VERSION
SOT270-1
12
min.
max.
IEC JEDEC EIAJ
1.3
0.8
b
1
0.53
0.40
REFERENCES
0.32
0.23
cEeM
(1)(1)
D
38.9
38.4
1996 Nov 2938
14.0
13.7
21
(1)
Z
1
L
M
E
3.2
15.80
2.9
15.24
EUROPEAN
PROJECTION
17.15
15.90
e
w
H
0.181.77815.24
ISSUE DATE
90-02-13
95-02-04
max.
1.73
Page 39
Philips SemiconductorsProduct specification
8-bit microcontrollers with OSD and VST84C44X; 84C64X; 84C84X
19 SOLDERING
19.1Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
19.2Soldering by dipping or by wave
The maximum permissible temperature of the solder is
The total contact time of successive solder waves must not
exceed 5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
19.3Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds.
20 DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
21 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2
22 PURCHASE OF PHILIPS I
Purchase of Philips I
C COMPONENTS
2
C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 2939
Page 40
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands457021/1200/03/pp40 Date of release: 1996 Nov 29Document order number: 9397 750 01542
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