Page 1
INTEGRATED CIRCUITS
DATA SH EET
74AVC16373
16-bit D-type transparent latch;
3.6 V tolerant; 3-state
Product Specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC24
2000 Mar 09
Page 2
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
FEATURES
• Wide supply voltage range from 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• Dynamic Controlled Output (DCO) circuit dynamically
changes output impedance,resulting in noise reduction
without speed degradation
• Low inductance multiple VCCand GND pins to minimize
noise and ground bounce
• Supports Live Insertion.
DESCRIPTION
The 74AVC16373 is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch, and
3-state outputs for bus oriented applications. One Latch
Enable (LE) input and one Output Enable (OE) input are
provided per 8-bit section. The 74AVC16373 consist of
two sections of eight D-type transparent latches with
3-state true outputs.
The 74AVC16373 is designed to have an extremely fast
propagation delay and a minimum amount of power
consumption.
To ensure the high-impedance output state during
power-up or power-down, pin OEn should be tied to V
through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is
implemented to support termination line drive during
transient (see Figs 1 and 2).
74AVC16373
CC
handbook, halfpage
0
I
OH
(mA)
1.8 V
−100
2.5 V
−200
3.3 V
−300
012 4
Fig.1 Output voltage as a function of the
HIGH-level output current.
3
VOH (V)
MNA506
300
handbook, halfpage
I
OL
(mA)
200
100
0
012 4
1.8 V
3.3 V
2.5 V
Fig.2 Output voltage as a function of the
LOW-level output current.
3
MNA507
VOL (V)
2000 Mar 09 2
Page 3
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
QUICK REFERENCE DATA
GND = 0 V; T
t
PHL/tPLH
C
I
C
PD
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in Volts;
∑ (CL× V
2. The condition is VI= GND to VCC.
=25°C; tr=tf≤2.0 ns.
amb
SYMBOL PARAMETER CONDITIONS TYP. UNIT
propagation delay
nDnto nQ
n
input capacitance 5.0 pF
power dissipation
capacitance per buffer
2
× fi+ ∑ (CL× V
CC
2
× fo) = sum of outputs.
CC
2
× fo) where:
CC
74AVC16373
VCC= 1.2 V 3.6 ns
V
= 1.5 V 3.1 ns
CC
V
= 1.8 V 2.2 ns
CC
= 2.5 V 1.6 ns
V
CC
V
= 3.3 V 1.4 ns
CC
notes 1 and 2
outputs enabled 34 pF
outputs disabled 1 pF
FUNCTION TABLE
See note 1.
OPERATING MODES
n
Enable and read register
(transparent mode)
Latch and read register
(hold mode)
Latch register and disable outputs H
INPUTS
OE LE nA
L
L
L
L
H
H
L
L
L
H
L
n
L
H
l
h
l
h
INTERNAL
LATCHES
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high impedance OFF-state.
OUTPUTS
nY
n
L
H
L
H
L
H
L
H
L
H
Z
Z
2000 Mar 09 3
Page 4
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
74AVC16373
3-state
ORDERING AND PACKAGE INFORMATION
to 1Q
to 2Q
to 2D
to 1D
PACKAGE
data outputs
7
DC supply voltage
data outputs
7
data inputs
0
data inputs
0
TYPE NUMBER
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74AVC16373DGG −40 to +85 °C 48 TSSOP plastic SOT362-1
PINNING
PIN SYMBOL DESCRIPTION
11
2, 3, 5, 6, 8, 9, 11 and 12 1Q
OE output enable input (active LOW)
0
4, 10, 15, 21, 28, 34, 39 and 45 GND ground (0 V)
7, 18, 31 and 42 V
13, 14, 16, 17, 19, 20, 22 and 23 2Q
24 2
CC
0
OE output enable input (active LOW)
25 2LE latch enable input (active HIGH)
26, 27, 29, 30, 32, 33, 35 and 36 2D
37, 38, 40, 41, 43, 44, 46 and 47 1D
7
7
48 1LE latch enable input (active HIGH)
2000 Mar 09 4
Page 5
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
handbook, halfpage
1OE
1Q
1Q
GND
1Q
1Q
V
CC
1Q
1Q
GND
1Q
1Q
2Q
2Q
GND
2Q
2Q
V
CC
2Q
2Q
GND
2Q
2Q
2OE
1
2
0
3
1
4
5
2
6
3
7
8
4
9
5
10
11
6
12
7
0
1
2
3
4
5
6
7
16373
13
14
15
16
17
18
19
20
21
22
23
24
MNA541
1LE
48
1D
47
0
1D
46
1
GND
45
1D
44
2
1D
43
3
V
42
CC
1D
41
4
1D
40
5
GND
39
1D
38
6
1D
37
7
2D
36
0
2D
35
1
GND
34
2D
33
2
2D
32
3
V
31
CC
2D
30
4
2D
29
5
GND
28
2D
27
6
2D
26
7
2LE
25
handbook, halfpage
74AVC16373
1
24
1OE
2OE
47
1D
0
46
1D
1
1D
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
1D
3
1D
4
1D
5
1D
6
1D
7
2D
0
2D
1
2D
2
2D
3
2D
4
2D
5
2D
6
2D
7
1LE 2LE
48 25
1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
MNA547
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Fig.3 Pin configuration.
2000 Mar 09 5
Fig.4 Logic symbol.
Page 6
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
handbook, halfpage
1OE
1LE
2OE
2LE
1D
1D
1D
1D
1D
1D
1D
1D
2D
2D
2D
2D
2D
2D
2D
2D
1
1EN
48
C3
24
2EN
25
C4
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
3D 1
4D 2
MNA546
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
2
1Q
0
3
1Q
1
5
1Q
2
6
1Q
3
8
1Q
4
9
1Q
5
11
1Q
6
12
1Q
7
13
2Q
0
14
2Q
1
16
2Q
2
17
2Q
3
19
2Q
4
20
2Q
5
22
2Q
6
23
2Q
7
74AVC16373
Fig.5 IEEE/IEC logic symbol.
handbook, full pagewidth
1D
1LE
1OE
MNA545
D1Q
0
Q
LATCH
1
LE
to 7 other channels
0
2D
2LE
2OE
0
D2Q
Q
LATCH
9
LE
to 7 other channels
0
Fig.6 Logic diagram.
2000 Mar 09 6
Page 7
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
74AVC16373
3-state
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
V
T
t
r,tf
CC
I
O
amb
DC supply voltage according to JEDEC Low Voltage
Standards
for low-voltage applications 1.2 3.6 V
DC input voltage 0 3.6 V
DC output voltage output 3-state 0 3.6 V
output HIGH or LOW state 0 V
operating ambient temperature in free air −40 +85 °C
input rise and fall time ratios VCC= 1.4 to 1.6 V 0 40 ns/V
V
= 1.65 to 2.3 V 0 30 ns/V
CC
V
= 2.3 to 3.0 V 0 20 ns/V
CC
V
= 3.0 to 3.6 V 0 10 ns/V
CC
1.4 1.6 V
1.65 1.95 V
2.3 2.7 V
3.0 3.6 V
CC
V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
I
IK
V
I
I
OK
V
O
DC supply voltage −0.5 +4.6 V
DC input diode current VI<0 −−50 mA
DC input voltage for inputs; note 1 −0.5 +4.6 V
DC output clamping diode current VO<0 −−50 mA
DC output voltage output HIGH or LOW state; note 1 −0.5 VCC+ 0.5 V
output 3-state; note 1 −0.5 +4.6 V
I
O
I
CC,IGND
T
stg
P
D
DC output sink current VO= 0 to V
CC
− 50 mA
DC VCCor GND current −±100 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range:
− 500 mW
−40 to +85 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 60 °C the value of PD derates linearly with 5.5 mW/K.
2000 Mar 09 7
Page 8
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
V
OH
HIGH-level output
voltage
V
OL
LOW-level output
voltage
I
I
input leakage
current per pin
I
off
power-off leakage
current
I
IHZ/IILZ
input current for
common I/O pins
I
OZ
3-state output
OFF−state current
I
CC
quiescent supply
current
TEST CONDITIONS T
OTHER VCC(V) MIN. TYP.
1.2 V
CC
1.4 to 1.6 0.65 × V
1.65 to 1.95 0.65 × V
2.3 to 2.7 1.7 1.2 − V
3.0 to 3.6 2.0 1.5 − V
1.2 −−GND V
1.4 to 1.6 − 0.9 0.35 × V
1.65 to 1.95 − 0.9 0.35 × V
2.3 to 2.7 − 1.2 0.7 V
3.0 to 3.6 − 1.5 0.8 V
VI=VIHor V
IL
IO= −100 µA 1.65 to 3.6 VCC− 0.20 V
I
= −3 mA 1.4 VCC− 0.35 VCC− 0.23 − V
O
= −4 mA 1.65 VCC− 0.45 VCC− 0.25 − V
I
O
I
= −8 mA 2.3 VCC− 0.55 VCC− 0.38 − V
O
I
= −12 mA 3.0 VCC− 0.70 VCC− 0.48 − V
O
VI=VIHor V
IL
IO= 100 µA 1.65 to 3.6 − GND 0.20 V
I
=3mA 1.4 − 0.18 0.35 V
O
= 4 mA 1.65 − 0.22 0.45 V
I
O
I
=8mA 2.3 − 0.37 0.55 V
O
I
=2mA 3.0 − 0.51 0.70 V
O
VI=VCCor GND 1.4 to 3.6 − 0.1 2.5 µA
VIor VO= 3.6 V 0 − 0.1 ±10 µA
VI=VCCor GND 1.4 to 3.6 − 0.1 12.5 µA
VI=VIHor VIL;
VO=VCC or GND
VI=VCCor GND;
IO=0
1.4 to 2.7 − 0.1 5 µA
3.0 to 3.6 − 0.1 10 µA
1.4 to 2.7 − 0.1 20 µA
3.0 to 3.6 − 0.2 40 µA
= −40 to +85 °C
amb
−−V
0.9 − V
CC
0.9 − V
CC
CC
74AVC16373
(1)
MAX.
− V
CC
CC
UNIT
V
V
Note
1. All typical values are measured at T
amb
=25°C.
2000 Mar 09 8
Page 9
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
AC CHARACTERISTICS
GND = 0 V; tr=tf≤2.0 ns.
SYMBOL PARAMETER
t
PHL/tPLH
propagation delay nDnto nQ
propagation delay nLE to nQ
t
PZH/tPZL
t
PHZ/tPLZ
t
W
t
su
t
h
3-state output enable time
nOE to nQ
n
3-state output disable time
nOE to nQ
n
nLE pulse width HIGH see Figs 8 and 11 1.2 − 2.4 − ns
set-up time nDnto nLE see Figs 10 and 11 1.2 − 0.4 − ns
hold time nDnto nLE see Figs 10 and 11 1.2 −−0.2 − ns
see Figs 7 and 11 1.2 − 3.6 − ns
n
see Figs 8 and 11 1.2 − 3.6 − ns
n
see Figs 9 and 11 1.2 − 5.9 − ns
see Figs 9 and 11 1.2 − 5.8 − ns
TEST CONDITIONS T
WAVEFORMS V
74AVC16373
= −40 to +85 °C
amb
(V) MIN. TYP.
CC
1.40 to 1.60 1.2 3.1 6.8 ns
1.65 to 1.95 1.0 2.2 5.7 ns
2.3 to 2.7 0.7 1.6 3.3 ns
3.0 to 3.6 0.7 1.4 2.8 ns
1.40 to 1.60 2.5 3.1 9.4 ns
1.65 to 1.95 2.3 2.2 7.8 ns
2.3 to 2.7 1.3 1.6 4.2 ns
3.0 to 3.6 0.7 1.4 3.9 ns
1.40 to 1.60 1.6 4.2 8.8 ns
1.65 to 1.95 1.6 3.5 6.7 ns
2.3 to 2.7 1.4 2.4 4.3 ns
3.0 to 3.6 0.7 2.0 3.4 ns
1.40 to 1.60 2.5 4.6 9.4 ns
1.65 to 1.95 2.3 3.6 7.8 ns
2.3 to 2.7 1.3 1.9 4.2 ns
3.0 to 3.6 1.2 2.1 3.9 ns
1.40 to 1.60 − 1.9 − ns
1.65 to 1.95 2.2 1.7 − ns
2.3 to 2.7 2.0 1.6 − ns
3.0 to 3.6 1.8 1.4 − ns
1.40 to 1.60 1.2 0.2 − ns
1.65 to 1.95 1.1 0.1 − ns
2.3 to 2.7 +0.9 −0.1 − ns
3.0 to 3.6 +0.8 −0.1 − ns
1.40 to 1.60 +1.1 −0.1 − ns
1.65 to 1.95 1.1 0.0 − ns
2.3 to 2.7 1.1 0.1 − ns
3.0 to 3.6 1.0 0.2 − ns
(1)
MAX.
UNIT
Note
1. All typical values are measured at T
=25°C and at VCC respectively 1.2, 1.5, 1.8, 2.5 and 3.3 V.
amb
2000 Mar 09 9
Page 10
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
AC WAVEFORMS
GND
V
OH
V
OL
V
V
V
V
CC
CC
I
V
M
t
PHL
V
M
I
handbook, full pagewidth
V
CC
≤2.3 to 2.7 V 0.5 × V
3.0 to 3.6 V 0.5 × V
V
nDn input
nQn output
M
CC
CC
t
PLH
MNA544
74AVC16373
VOLand VOH are typical output voltage drop that occur with the output load.
Fig.7 The input (nDn) to output (nQn) propagation delay.
GND
V
OH
V
OL
V
I
V
M
t
W
t
PHL
V
I
V
CC
V
CC
handbook, full pagewidth
V
CC
≤2.3 to 2.7 V 0.5 × V
3.0 to 3.6 V 0.5 × V
nLE input
nQn output
V
M
CC
CC
V
M
t
PLH
V
M
MNA543
VOLand VOH are typical output voltage drop that occur with the output load.
Fig.8 The latch enable input (nLE) pulse width to output (nQn) propagation delays.
2000 Mar 09 10
Page 11
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
handbook, full pagewidth
V
CC
≤2.3 to 2.7 V 0.5 × V
3.0 to 3.6 V 0.5 × V
nOE input
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
V
M
CC
CC
V
I
V
M
GND
t
PLZ
V
CC
V
V
OL
V
OH
GND
t
PHZ
outputs
enabled
V
X
X
V
Y
V
Y
VOL+ 0.15 V VOH− 0.15 V V
VOL+ 0.3 V VOH− 0.3 V V
outputs
disabled
V
CC
CC
I
t
PZL
t
PZH
74AVC16373
V
M
V
M
outputs
enabled
MNA478
VOLand VOH are typical output voltage drop that occur with the output load.
Fig.9 3-state enable and disable times.
V
GND
GND
I
V
M
t
V
I
V
V
V
su
I
CC
CC
handbook, full pagewidth
V
CC
≤2.3 to 2.7 V 0.5 × V
3.0 to 3.6 V 0.5 × V
nDn input
nLE input
V
M
CC
CC
t
h
V
M
t
t
h
su
MNA542
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.10 Data set-up and hold times for nDninput to nLE input.
2000 Mar 09 11
Page 12
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
handbook, full pagewidth
V
CC
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
open
2 × V
GND
CC
PULSE
GENERATOR
VCC (V) V
1.2 V
1.4 to 1.6 V
1.65 to 1.95 V
2.3 to 2.7 V
3.0 to 3.6 V
V
I
D.U.T.
R
T
I
2000 Ω 15 pF
CC
2000 Ω 15 pF
CC
1000 Ω 30 pF
CC
500 Ω 30 pF
CC
500 Ω 30 pF
CC
V
O
R
load
C
74AVC16373
S1
2 × V
CC
open
R
load
C
L
R
L
load
GND
MNA505
Fig.11 Load circuitry for switching times.
2000 Mar 09 12
Page 13
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
PACKAGE OUTLINE
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
D
c
y
Z
48 25
H
74AVC16373
SOT362-1
E
E
A
X
v M
A
A
2
A
1
pin 1 index
L
p
L
0.50
0.35
detail X
0.08
124
w M
b
e
DIMENSIONS (mm are the original dimensions).
mm
A
max.
1.2
0.15
0.05
1
A2A
1.05
0.85
0.25
b
0.28
0.17
p
cD
0.2
0.2
0.1
0.1
3
UNIT A
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
p
0
(1)E(2)
12.6
12.4
2.5
scale
eHELLpQZywvθ
6.2
0.5 1 0.25
6.0
8.3
7.9
5 mm
0.8
0.4
Q
(A )
3
A
θ
0.1
0.8
0.4
o
8
o
0
OUTLINE
VERSION
SOT362-1
IEC JEDEC EIAJ
REFERENCES
MO-153
2000 Mar 09 13
EUROPEAN
PROJECTION
ISSUE DATE
95-02-10
99-12-27
Page 14
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
SOLDERING
Introduction to soldering surface mount packages
Thistext gives a very briefinsightto a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages.Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
– smaller than 1.27 mm, the footprint longitudinal axis
The footprint must incorporate solder thieves at the
downstream end.
• Forpackageswith leads on foursides,thefootprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
74AVC16373
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
must be parallel to the transport direction of the
printed-circuit board.
2000 Mar 09 14
Page 15
Philips Semiconductors Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
74AVC16373
3-state
Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable
(3)
PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable for SSOP and TSSOP packageswith a pitch (e) equal to or larger than 0.65 mm; it is
, SO, SOJ suitable suitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
SOLDERING METHOD
WAVE REFLOW
(2)
(3)(4)
(5)
suitable
suitable
suitable
(1)
.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting valuesgiven are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Mar 09 15
Page 16
Philips Semiconductors – a w orldwide compan y
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For all other countries apply to: Philips Semiconductors,
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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
2000
Internet: http://www.semiconductors.philips.com
69
Printed in The Netherlands 613507/02/pp16 Date of release: 2000 Mar 09 Document order number: 9397750 06897
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