Datasheet 74ABT240CSJX, 74ABT240CSJ, 74ABT240CSCX, 74ABT240CSC, 74ABT240CMTCX Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS011664 www.fairchildsemi.com

March 1994
Revised November 1999

74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs

74ABT240
Octal Buffer/Line Driv e r wit h 3- S TATE Outputs

General Description

The ABT240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus or iented tra nsmitter or receive r which
provides improved PC board density.

Features

■ Output sink capability of 64 mA, source capability of
32 mA

■ Guarante ed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Nondestructive hot insertion capability

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram Pin Descriptions

Tru th Tables

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

Order Number Package Number Package Description

74ABT240CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT240CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT240CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT240CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

OE

1

, OE

2

3-STATE Output
Enable Inputs

I

0–I7

Inputs

O

0–O7

Outputs

Inputs Outputs

(Pins 12, 14, 16, 18)

OE

1

I

n

LL H
LH L
HX Z

Inputs Outputs

(Pins 3, 5, 7, 9)

OE

2

I

n

LL H
LH L
HX Z

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74ABT240

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.

Note 2: Either voltage lim it or c urrent limit is sufficient to prot ect inputs.

DC Electrical Characteristics

Note 3: Guaranteed, but not tested.
Note 4: For 8 bits toggling, I

CCD

< 0.8 mA/MHz.

Storage Temperature −65°C to +150°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disabled or
Power-Off State −0.5V to 5.5V
in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

DC Latchup Source Current

(Across Comm Operating Range) −150 mA

Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

V

OH

Output HIGH Voltage 2.5 V Min IOH = −3 mA

2.0 V Min IOH = −32 mA

V

OL

Output LOW Voltage 0.55 V Min IOL = 64 mA

I

IH

Input HIGH Current 1

µAMax

VIN = 2.7V (Note 3)

1V

IN

= V

CC

I

BVI

Input HIGH Current Breakdown Test 7 µAMaxVIN = 7.0V

I

IL

Input LOW Current −1

µAMax

VIN = 0.5V (Note 3)

−1V

IN

= 0.0V

V

ID

Input Leakage Test 4.75 V 0.0 IID = 1.9 µA

All Other Pins Grounded

I

OZH

Output Leakage Current 10 µA0 − 5.5V

V

OUT

= 2.7V; OEn = 2.0V

I

OZL

Output Leakage Current −10 µA0 − 5.5V

V

OUT

= 0.5V; OEn = 2.0V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

= 0.0V

I

CEX

Output HIGH Leakage Current 50 µAMaxV

OUT

= V

CC

I

ZZ

Bus Drainage Test 100 µA0.0V

OUT

= 5.5V; All Others GND

I

CCH

Power Supply Current 50 µA Max All Outputs HIGH

I

CCL

Power Supply Current 30 mA Max All Outputs LOW

I

CCZ

Power Supply Current

50 µAMax

OEn = VCC;
All Others at VCC or Ground

I

CCT

Additional ICC/Input Outputs Enabled 1.5 mA

Max

VI = VCC − 2.1V
Outputs 3-STATE 1.5 mA Enable Input VI = VCC − 2.1V
Outputs 3-STATE 50 µA Data Input VI = VCC − 2.1V

All Others at VCC or Ground

I

CCD

Dynamic I

CC

No Load mA/

Max

Outputs Open

(Note 3) 0.1

MHz

OEn = GND, (Note 4)

One Bit Toggling, 50% Duty Cycle

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74ABT240

AC Electrical Characteristics

Capacitance

Note 5: C

OUT

is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.

TA = +25°CT

A

= −55°C to +125°CTA = −40°C to +85°C

V

CC

= +5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V

Symbol Parameter

C

L

= 50 pF CL = 50 pF CL = 50 pF

Units

Min Typ Max Min Max Min Max

t

PLH

Propagation Delay 1.0 4.8 0.8 5.5 1.0 4.8

ns

t

PHL

Data to Outputs 1.6 4.8 1.0 5.5 1.6 4.8

t

PZH

Output Enable 1.1 6.2 0.8 7.5 1.1 6.2

ns

t

PZL

Time 1.1 6.2 0.8 7.7 1.1 6.2

t

PHZ

Output Disable 1.8 6.4 1.0 7.5 1.8 6.4

ns

t

PLZ

Time 1.6 5.8 1.0 7.2 1.6 5.8

Symbol Parameter Typ Units

Conditions

T

A

= 25°C

C

IN

Input Capacitance 5.0 pF VCC = 0V

C

OUT

(Note 5) Output Capacitance 9.0 pF VCC = 5.0V

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74ABT240

AC Loading

*Includes jig and pr obe capacitance

Standard AC Test Load

Test Input Signal Lev els

Test Input Signal Requirements

AC Waveforms

Propagation Delay,

Pulse Width Waveforms

3-STAT E Output HIGH

and LOW Enable and Disable Times

Propagati o n Delay Waveforms for

Inverting and Non-Inverting Functions

Setup Time, Hold Time

and Recovery Time Waveforms

Amplitude Rep. Rate t

W

t

r

t

f

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

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74ABT240

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74ABT240

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74ABT240

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Num b er MSA20

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74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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SEMICONDUCTOR CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component in any compon ent of a lif e supp ort
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