Datasheet 74ABT16952CSSC, 74ABT16952CMTDX, 74ABT16952CMTD Datasheet (Fairchild Semiconductor)

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November 1993 Revised January 1999

74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs

General Description

The ABT16952 is a 16-bi t registere d transceiver. Two 8-bit back to back registers store data fl owing in both direct ions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to source 32 mA and to sink 64 mA.

Features

■ Separate clock, clock enable and 3-STATE output enable provided for each register

■ A and B output sink capability of 64 mA source capability of 32 mA

■ Guaranteed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Nondestructive hot insertion capability

Ordering Code:

Order Number Package Number Package Description

74ABT16952CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16952CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to t he ordering code.

Pin Descriptions

Pin Names Description

0–A15

0–B15

CPAB CEA OEAB

, CPBA

, CEB

, OEBA

Data Register A Inputs/ B-Register 3-STATE Outputs Data Register B Inputs/ A-Register 3-STATE Outputs Clock Pulse Inputs

Clock Enable

Output Enable Inputs

Connection Diagram

Pin Assignment for SSOP

Output Control

Internal QOutput Function

H X Z Disable Outputs L L L Enable Outputs LH H

(Applies to A or B Register)

H = HIGH Voltage Level Z = HIGH Impedance L = LOW Voltage Level

X = Immaterial NC = No Change

Inputs Internal

X X H NC Hold Data

 

L L Load Data L H



= LOW-to-HIGH Transition

FunctionDCPCE

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Block Diagram

74ABT16952

n for either byte 1 or byte 2

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Absolute Maximum Ratings(Note 1)

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C

Pin Potential to

Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Any Output

in the Disable or Power-Off State −0.5V to +5.5V

in the HIGH State −0.5V to V Current Applied to Output

in LOW State (Max) twice the rated I

DC Latchup Source Current −500 mA Over Voltage Latchup (I/O) 10V

Recommended Operating Conditions

Free Air Ambient Temperature −40°C to +85°C Supply Voltage +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns Enable Input 20 mV/ns Clock Input 100 mV/ns

Note 1: Absolute maximum ratin gs are values beyond which the device may be damaged or have its useful life impaired. Functional operation

(mA)

under these condit ions is not implied.

Note 2: Either voltage limit or current limi t is s uf f ic ient to protect inputs.

DC Electrical Characteristics

Symbol Parameter Min Typ Max Units

V V V V

V V

BVI

BVIT

IIH + I

IIL + I

CEX

CCH

CCL

CCZ

CCT

CCD

Note 3: For 8-bit toggling, I Note 4: Guaranteed, but not tested.

Input HIGH Voltage 2.0 V Recognized HIGH Signal

Input LOW Voltage 0.8 V Recognized LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)

Output HIGH Voltage 2.5 IOH = −3 mA (An, Bn)

Output LOW Voltage 0.55 IOL = 64 mA (An, Bn)

Input Leakage Test 4.75 V 0.0 IID = 1.9 µA (Non-I/O Pins)

Input HIGH Current 1 µA MaxVIN = 2.7V (Non-I/O Pins) (Note 4)

Input HIGH Current 7 µA MaxVIN = 7.0V (Non-I/O Pins) Breakdown Test Input HIGH Current 100 µA MaxVIN = 5.5V (An, Bn) Breakdown Test (I/O) Input LOW Current −1 µA MaxVIN = 0.5V (Non-I/O Pins) (Note 4)

Output Leakage Current 10 µA 0V–5.5V V

OZH

Output Leakage Current −10 µA 0V–5.5VV

OZL

Output Short-Circuit Current −100 −275 mA Max V Output HIGH Leakage Current 50 µA MaxV Bus Drainage Test 100 µA 0.0V V

Power Supply Current 1.0 mA Max All Outputs HIGH Power Supply Current 60 mA Max All Outputs LOW Power Supply Current 1.0 mA Max Outputs 3-STATE;

Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V; All Others

Dynamic I (Note 4)

CCD

<1.4 mA/MHz.

No Load Outputs Open

2.0 IOH = −32 mA (An, Bn)

−1V

0.18 mA/MHz Max

All Other Pins Grounded

= VCC (Non-I/O Pins)

= 0.0V (Non-I/O Pins)

= 2.7V (An, Bn);

OUT

OEA or OEB = 2.0V

= 0.5V (An, Bn);

OUT

OEA or OEB = 2.0V

= 0V (An, Bn)

OUT

= VCC (An, Bn)

OUT

= 5.5V (An, Bn);

OUT

All Others GND

at VCC or GND

OEA or OEB = GND, Non-I/O = GND or V One Bit toggling, 50% duty cycle (Note 3)

74ABT16952

Conditions

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AC Electrical Charac teristics

(SSOP Package)

Symbol Parameter

74ABT16952

max

PLH

PHL

PZH

PZL

PHZ

PLZ

Max Clock 200 200 MHz Frequency Propagation Delay 1.5 5.3 1.5 5.3 ns CPABn or CPBAn to 1.5 5.3 1.5 5.3 An or B

Output Enable Time 1.5 5.5 1.5 5.5 ns OEABn or OEBAn to

An or B

Output Disable Time 1.5 6.0 1.5 6.0 ns OEABn or OEBAn to

An or B

TA = +25°CT

= −40°C to +85°C

VCC = +5.0V VCC = 4.5V to 5.5V

CL = 50 pF CL = 50 pF

Min Max Min Max

1.5 5.5 1.5 5.5

1.5 6.0 1.5 6.0

AC Operating Requirements

TA = +25°CT

Symbol Parameter

VCC = +5.0V VCC = 4.5V to 5.5V

CL = 50 pF CL = 50 pF

Min Max Min Max

tS(H) Setup Time, HIGH 2.5 2.5 ns tS(L) or LOW An or B

to CPABn or CPBA

2.5 2.5

tH(H) Hold Time, HIGH 1.5 1.5 ns tH(L) or LOW An or B

to CPABn or CPBA

1.5 1.5

tS(H) Setup Time, HIGH 2.5 2.5 ns tS(L)

or LOW CEAn or CEB to CPABn or CPBA

2.5 2.5

tH(H) Hold Time, HIGH 1.5 1.5 ns tH(L)

or LOW CEAn or CEB to CPABn or CPBA

1.5 1.5

tW(H) Pulse Width, 3.0 3.0 tW(L) HIGH or LOW 3.0 3.0

to CPABn or CPBA

Capacitance

Symbol Parameter Typ Units

(Note 5) Output Capacitance 11 pF VCC = 5.0V (An, Bn)

I/O

Note 5: C

Input Capacitance 5 pF VCC = 0V (Non I/O Pins)

is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.

I/O

= −40°C to +85°C

Conditions

TA = 25°C

Units

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AC Loading

74ABT16952

*Includes jig and prob e c apacitance

FIGURE 1. Standard AC Test Load

Amplitude Rep. Rate t

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

AC Waveforms

FIGURE 4. Propagation Delay Waveforms for

Inverting and Non-Inverting Functions

FIGURE 2. Test Input Signal Levels

FIGURE 3. Input Signal Requirements

FIGURE 6. 3-STATE Output HIGH

and LOW Enable and Disable Times

FIGURE 5. Propagation Delay,

Pulse Width Waveforms

FIGURE 7. Setup Time, Hold Time

and Recovery Time Waveforms

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Physical Dimensions in ches (millimeters) unless otherwise noted

74ABT16952

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

Package Number MS56A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the user.

Package Number MTD56

2. A critical component in any com ponent of a li fe support device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness.

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Fairchild does not assume any responsibility for use of any circuitry descri bed, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitr y and specifications.