Page 1
查询74ABT16823供应商
INTEGRATED CIRCUITS
74ABT16823A
74ABTH16823A
18-bit bus interface D-type flip-flop
with reset and enable (3-State)
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
Page 2
Philips Semiconductors Product specification
Quiescent su ly current
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
FEA TURES
•Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
•Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
•Live insertion/extraction permitted
•Power-up 3-State
•74ABTH16823A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
•Power-up Reset
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
I
CCL
IN
Propagation delay
nCP to nQx
Input capacitance VI = 0V or V
Output capacitance VO = 0V or VCC; 3-State 6 pF
pp
74ABT16823A
74ABTH16823A
DESCRIPTION
The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE
interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
Two options are available, 74ABT16823A which does not have the
bus-hold feature and 74ABTH16823A which incorporates the
bus-hold feature.
T
amb
CL = 50pF; VCC = 5V
Outputs disabled; VCC = 5.5V 500 µA
Outputs low; VCC = 5.5V 9 mA
) and Master Reset (nMR) which are ideal for parity bus
CONDITIONS
= 25°C; GND = 0V
CC
TYPICAL UNIT
2.3
1.9
4 pF
ns
ORDERING INFORMATION
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16823A DL BT16823A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16823A DGG BT16823A DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16823A DL BH16823A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16823A DGG BH16823A DGG SOT364-1
PIN DESCRIPTION
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
1998 Feb 27 853-1791 19025
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
PIN NUMBER SYMBOL FUNCTION
2, 27 1OE, 2OE Output enable input (active-Low)
1D0-1D8
2D0-2D8
1Q0-1Q8
2Q0-2Q8
56, 29 1CP, 2CP Clock pulse input (active rising edge)
55, 30 1CE, 2CE Clock enable input (active-Low)
1, 28 1MR, 2MR Master reset input (active-Low)
7, 22, 35, 50 V
CC
2
Data inputs
Data outputs
Positive supply voltage
Page 3
Philips Semiconductors Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
PIN CONFIGURATION
1
2
1OE
3
1Q0
4
GND
5
1Q1
6
1Q2
7
V
CC
8
1Q3
9
1Q4
10
1Q5
GND
11
1Q6
12
1Q7
13
1Q8
14
2Q0
15
2Q1
16
2Q2
17
GND
18
2Q3
19
2Q4
20
2Q5
21
V
22
CC
23
2Q6
24
2Q7
25
GND
26
2Q8
27
2OE
28 29
2MR
561MR
1CP
55
1CE
54
1D0
GND
53
1D1
52
1D2
51
V
50
CC
1D3
49
1D4
48
1D5
47
GND
46
1D6
45
1D7
44
1D8
43
2D0
42
2D1
41
2D2
40
GND
39
2D3
38
2D4
37
2D5
36
V
35
CC
34
2D6
33
2D7
32
GND
31
2D8
30
2CE
2CP
LOGIC SYMBOL (IEEE/IEC)
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2
1
55
56
27
28
30
29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
EN1
R2
G3
3C4
EN5
R6
G7
7C8
4D
8D
74ABT16823A
74ABTH16823A
1, 2 ∇
5, 6 ∇
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
25
SH00015
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1998 Feb 27
SH00014
3
Page 4
Philips Semiconductors Product specification
OPERATING MODE
Load and read data
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
LOGIC DIAGRAM
nCE
nD0
nCP
nMR
nOE
n = 1 or 2
nD1
CP CP CP CP CP CP CP CP CP
nD
R
nD
R
Q
nQ0
nD2
Q Q Q Q Q Q Q Q
nQ1
74ABT16823A
74ABTH16823A
nD3
nD
R
nD
R
nQ2
nQ3
nD4
nD5
nD
R
nD
R
nQ4
nQ5
nD6
nD7
nD
R
nQ6
nD8
nD
R
nQ7
nD
R
nQ8
SH00016
FUNCTION TABLE
INPUTS OUTPUTS
nOE nMR nCE nCP nDx nQ0 – nQ8
L L X X X L Clear
L H L ↑ h H
L H L ↑ l L
L H H ↑ X NC Hold
H X X X X Z High impedance
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low to High clock transition
= Not a Low-to-High clock transition
↑
1998 Feb 27
4
Page 5
Philips Semiconductors Product specification
I
DC output current
mA
SYMBOL
PARAMETER
UNIT
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
I
V
I
OK
V
OUT
OUT
T
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC supply voltage –0.5 to +7.0 V
CC
DC input diode current VI < 0 –18 mA
IK
DC input voltage
I
DC output diode current VO < 0 –50 mA
DC output voltage
p
Storage temperature range –65 to 150 °C
stg
PARAMETER CONDITIONS RATING UNIT
3
3
1, 2
output in Off or High state –0.5 to +5.5 V
output in Low state 128
output in High state –64
74ABT16823A
74ABTH16823A
–1.2 to +7.0 V
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
amb
DC supply voltage 4.5 5.5 V
CC
Input voltage 0 V
I
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
High-level output current –32 mA
Low-level output current 64 mA
Operating free-air temperature range –40 +85 °C
CC
V
1998 Feb 27
5
Page 6
Philips Semiconductors Product specification
µ
IIIn ut leakage curent
V
CC
5.5V V
I
V
CC
GND
±0.01±1±1
µA
In ut leakage current
Data pins
5
74ABTH16823A
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER TEST CONDITIONS T
V
V
V
V
RST
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
IK
VCC = 4.5V; IOH = –3mA; VI = VIL or V
High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V
OH
VCC = 4.5V; IOH = –32mA; VI = VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
OL
Power-up output low
3
voltage
I
Input leakage curent V
VCC = 5.5V; IOL = 1mA; VI = GND or V
= 5.5V; V
= V
VCC = 5.5V; VI = VCC or GND
I
I
p
74ABTH16823A
VCC = 5.5V; VI = V
CC
VCC = 5.5V; VI = 0
or GND ±0.01 ±1 ±1
or
IH
IH
IH
IH
CC
Control
pins
p
VCC = 4.5V; VI = 0.8V 35 35
I
HOLD
Bus Hold current inputs
74ABTH16823A
VCC = 4.5V; VI = 2.0V –75 –75 µA
VCC = 5.5V; VI = 0 to 5.5V ±800
I
OFF
I
PU/PD
I
OZH
I
OZL
I
CEX
I
I
CCH
I
CCL
I
CCZ
∆I
Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State
output current
4
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output High leakage
current
O
Output current
1
VCC = 2.1V; VO = 0.5V; VI = GND or VCC,
VOE = Don’t care
IH
IH
VCC = 5.5V; VO = 5.5V; VI = GND or V
CC
VCC = 5.5V; VO = 2.5V –50 –80 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or
V
CC
Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V
CC
VCC = 5.5V; Outputs 3–State;
Additional supply current
CC
per input pin
VI = GND or V
2
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
transition time of up to 100µsec is permitted.
between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
CC
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
= +25°C
amb
MIN TYP MAX MIN MAX
2.5 2.9 2.5 V
3.0 3.4 3.0 V
2.0 2.4 2.0 V
0.42 0.55 0.55 V
0.13 0.55 0.55 V
±0.01 ±1 ±1 µA
0.01 1 1 µA
–2 –3 –5 µA
±5.0 ±50 ±50 µA
1.0 10 10 µA
–1.0 –10 –10 µA
50 50 50 µA
0.5 1 1 mA
9.0 19 19 mA
0.5 1 1 mA
0.2 1 1 mA
74ABTH16823A
LIMITS
74ABT16823A
T
= –40°C
amb
to +85°C
UNIT
A
1998 Feb 27
6
Page 7
Philips Semiconductors Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ABT16823A
74ABTH16823A
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
T
= –40°C
SYMBOL PARAMETER WAVEFORM
f
MAX
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency 1 140 190 140 MHz
Propagation delay
nCP to nQx
Propagation delay
nMR to nQx
Output enable time
to High and Low level
Output disable time
from High and Low level
1
2 2.0 3.3 4.3 2.0 5.0 ns
4
5
4
5
T
= +25°C
amb
VCC = +5.0V
MIN TYP MAX MIN MAX
1.4
1.2
1.3
1.2
1.7
1.6
2.3
1.9
2.4
2.1
2.9
2.3
3.2
2.6
3.2
2.9
4.0
3.2
amb
to +85°C
V
= +5.0V ±0.5V
CC
1.4
1.2
1.3
1.2
1.7
1.6
3.7
2.9
3.9
3.4
4.7
3.4
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
T
= +25°C
SYMBOL PARAMETER WAVEFORM
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
ts(H)
ts(L)
th(H)
th(L)
tw(L) nMR pulse width, Low 2 3.0 1.7 3.0 ns
t
rec
Setup time, High or Low
nDx to nCP
Hold time, High or Low
nDx to nCP
nCP pulse width
High or Low
Setup time, High or Low
nCE to nCP
Hold time, High or Low
nCE to nCP
Recovery time
nMR to nCP
3
3
1
3
3
2 2.5 1.0 2.5 ns
amb
VCC = +5.0V
MIN TYP MIN
2.0
1.5
1.5
1.5
3.3
3.3
1.5
2.0
1.5
1.5
1.3
0.9
–0.9
–1.2
1.7
1.7
0.9
0.9
–0.8
–0.9
T
= –40 to +85°C
amb
VCC = +5.0V ±0.5V
2.0
1.5
1.5
1.5
3.3
3.3
1.5
2.0
1.5
1.5
UNIT
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
1998 Feb 27
7
Page 8
Philips Semiconductors Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
nCP
nQx
V
M
tw(H)
t
PHL
V
M
t
tw(L)
V
M
PLH
V
M
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
nMR
nCP
nQx
V
M
t
PHL
tw(L)
V
M
t
REC
V
M
V
M
Waveform 2. Master Reset Pulse WIdth, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
3.0V or V
whichever
is less
0V
V
OH
0V
SH00017
3.0V or V
whichever
is less
0V
3.0V or V
whichever
is less
0V
V
OH
0V
SH00018
CC
CC
CC
nOE
V
M
t
nQx
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
V
nOE
nQx
M
t
PZL
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
PZH
74ABT16823A
74ABTH16823A
V
M
t
PHZ
V
M
V
M
t
PLZ
V
M
V
OH
VOH–0.3V
VOL +0.3V
V
OL
3.0V or VCC
whichever
is less
0V
0V
SH00020
3.0V or VCC
whichever
is less
0V
3.0V or V
CC
whichever
is less
SH00021
nDx,
nCE
nCP
1998 Feb 27
V
V
M
M
th(H)ts(H)
V
M
V
V
M
M
th(L)ts(L)
V
M
Waveform 3. Data Setup and Hold Times
3.0V or V
whichever
is less
0V
3.0V or V
whichever
is less
0V
SH00019
CC
CC
8
Page 9
Philips Semiconductors Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
TEST CIRCUIT AND WAVEFORM
V
CC
R
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
DEFINITIONS:
R
= Load resistor; see AC CHARACTERISTICS for value.
L
C
= Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
= Termination resistance should be equal to Z
R
T
pulse generators.
L
R
C
L
L
OUT
of
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
90%
10%
FAMILY
74ABT16
t
W
V
M
10%
t
V
90%
M
THL (tf
t
TLH (tr
)
)
t
TLH (tr
t
THL (tf
t
W
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
Amplitude
3.0V
Rep. Rate
1MHz 500ns
74ABT16823A
74ABTH16823A
AMP (V)
90%
V
M
10%
)
)
90%
V
M
t
w
2.5ns 2.5ns
10%
t
0V
AMP (V)
0V
t
R
F
SH00022
1998 Feb 27
9
Page 10
Philips Semiconductors Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1
74ABT16823A
74ABTH16823A
1998 Feb 27
10
Page 11
Philips Semiconductors Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1
74ABT16823A
74ABTH16823A
1998 Feb 27
11
Page 12
Philips Semiconductors Product specification
18-bit bus-interface D-type flip-flop with reset
and enable (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74ABT16823A
74ABTH16823A
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-03502
yyyy mmm dd
12
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