Datasheet 74ABT16646CSSCX, 74ABT16646CSSC, 74ABT16646CMTDX, 74ABT16646CMTD Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS011644 www.fairchildsemi.com

October 1993
Revised November 1999

74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs

74ABT16646
16-Bit Transceivers and Registers with 3-STATE Outputs

General Description

The ABT16646 consists o f bus transceiver circ uits with 3­STATE, D-type flip-flo ps, and c ontrol circui try arranged for
multiplexed transmission of da ta directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE

and direction pins are pr o­vided to control the tr ansceiver function. In the tran sceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE

is Active

LOW. In the isolation mode (control OE

HIGH), A data may
be stored in the B register a nd/or B data may be stored in
the A regis ter.

Features

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data

■ A and B output sink capability of 64 mA, source

capability of 32 mA

■ Guarante ed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Nondestructive hot insertion capability

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagram

Order Number Package Number Package Description

74ABT16646CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names Description

A

0–A15

Data Register A Inputs/
3-STATE Outputs

B

0–B15

Data Register B Inputs/
3-STATE Outputs

CPAB

n

, CPBAn Clock Pulse Inputs

SAB

n

, SBA

n

Select Inputs

OE

n

Output Enable Input

DIR Direction Control Input

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74ABT16646

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial



= LOW-to-HIGH Transition

Note 1: The data output functions may be enabled or disabled by various s ignals at the OE

and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15)
and #2 control pins.

Real Time Transfer

A-Bus to B-Bus

FIGURE 1.

Real Time Transfer

B-Bus to A-Bus

FIGURE 2.

Storage from

Bus to Register

FIGURE 3.

Transfer from

Register to Bus

FIGURE 4.

Inputs Data I/O (Note 1) Output Operation Mode

OE

1

DIR1CPAB1CPBA1SAB1SBA1A

0–7

B

0–7

H X H or L H or L X X Isolatio n
H X



X X X Input Input Clock An Data into A Register

H X X



X X Clock Bn Data Into B Register
L H X X L X An to Bn—Real Time (Transparent Mode)
L H



X L X Input Output Clock An Data to A Register
L H H or L X H X A Register to Bn (Stored Mode)
L H



X H X Clock An Data into A Register and Output to Bn
L L X X X L Bn to An—Real Time (Transparent Mode)
L L X



X L Output Input Clock Bn Data into B Register
L L X H or L X H B Register to An (Stored Mode)
L L X



X H Clock Bn into B Register and Output to An

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74ABT16646

Logic Diagram

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74ABT16646

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.

Note 3: Either voltage lim it or c urrent limit is sufficient to prot ect inputs.

DC Electrical Characteristics

Note 4: For 8-bit toggling, I

CCD

< 1.4 mA/MHz.

Note 5: Guaranteed but not tested.

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 3) −0.5V to +7.0V
Input Current (Note 3) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disable or
Power-Off State −0.5V to +5.5V
in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the r ated I

OL

(mA)
DC Latchup Source Current −500 mA
Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Inpu t 20 mV/ns
Clock Input 100 mV/ns

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins)

V

OH

Output HIGH Voltage 2.5 IOH = −3 mA, (An, Bn)

2.0 IOH = −32 mA, (An, Bn)

V

OL

Output LOW Voltage 0.55 V Min IOL = 64 mA, (An, Bn)

V

ID

Input Leakage Test 4.75 V 0.0 IID = 1.9 µA, (Non-I/O Pins)

All Other Pins Grounded

I

IH

Input HIGH Current 1

µA Max

VIN = 2.7V (Non-I/O Pins) (Note 5)

1 V

IN

= VCC (Non-I/O Pins)

I

BVI

Input HIGH Current Breakdown Test 7 µA Max VIN = 7.0V (Non-I/O Pins)

I

BVIT

Input HIGH Current Breakdown T est (I/O) 100 µA Max VIN = 5.5V (An, Bn)

I

IL

Input LOW Current −1

µA Max

VIN = 0.5V (Non-I/O Pins) (Note 5)

−1 V

IN

= 0.0V (Non-I/O Pins)

IIH + I

OZH

Output Leakage Current 10 µA 0V–5.5V

V

OUT

= 2.7V (An, Bn); OE = 2.0V

IIL + I

OZL

Output Leakage Current −10 µA 0V–5.5V

V

OUT

= 0.5V (An, Bn); OE = 2.0V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

= 0V (An, Bn)

I

CEX

Output HIGH Leakage Current 50 µA Max V

OUT

= VCC (An, Bn)

I

ZZ

Bus Drainage Test 100 µA 0.0V V

OUT

= 5.5V (An, Bn);

All Others GND

I

CCH

Power Supply Current 1.0 mA Max All Outputs HIGH

I

CCL

Power Supply Current 60 mA Max All Outputs LOW

I

CCZ

Power Supply Current 1.0 mA Max Outputs 3-STATE; All Others GND

I

CCT

Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V

All Other Outputs at VCC or GND

I

CCD

Dynamic I

CC

No Load mA/ Max Outputs OPEN

(Note 5)

0.23 MHz

OE, DIR, and SEL = GND,
Non-I/O = GND or VCC(Note 4)
One Bit toggling, 50% duty cycle

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74ABT16646

DC Electrical Characteristics

(SSOP Package)

Note 6: Max number of outputs defined as (n). n − 1 data input s are driven 0V to 3V. One output at LOW. Guaran te ed, but not tested.
Note 7: Max number of outputs defined as (n). n − 1 data input s are driven 0V to 3V. One output HIGH. Guaranteed, but not te s t ed.
Note 8: Max number of data inputs (n) s witc hing. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V

ILD

), 0V to threshold (V

IHD

).

Guaranteed, but not tested.

AC Electrical Characteristics

(SSOP Package)

AC Operating Requirements

Symbol Par ameter Min Typ Max Units

V

CC

Conditions

CL = 50 pF, RL = 500Ω

V

OLP

Quiet Output Maximum Dynamic V

OL

0.7 1.2 V 5.0 TA = 25°C (Note 6)

V

OLV

Quiet Output Minimum Dynamic V

OL

−1.4 −1.0 V 5.0 TA = 25°C (Note 6)

V

OHV

Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25° (Note 7)

V

IHD

Minimum HIGH Level Dynamic Input Voltage 2.2 1.6 V 5.0 TA = 25°C (Note 8)

V

ILD

Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 TA = 25°C (Note 8)

Symbol Parameter

TA = +25°CT

A

= −40°C to +85°C

Units

V

CC

= +5.0V VCC = 4.5V–5.5V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

f

MAX

Maximum Clock Frequency 200 MHz

t

PLH

Propagation Delay 1.5 3.0 4.9 1.5 4.9

ns

t

PHL

Clock to Bus 1.5 3.4 4.9 1.5 4.9

t

PLH

Propagation Delay 1.5 2.6 4.5 1.5 4.5

ns

t

PHL

Bus to Bus 1.5 3.0 4.5 1.5 4.5

t

PLH

Propagation Delay 1.5 2.9 5.0 1.5 5.0

ns

t

PHL

SBAn or SABn to An to B

n

1.5 3.2 5.0 1.5 5.0

t

PZH

Enable Time 1.5 2.8 5.5 1.5 5.5

ns

t

PZL

OEn to An or B

n

1.5 3.0 5.5 1.5 5.5

t

PHZ

Disable Time 1.5 3.9 6.0 1.5 6.0

ns

t

PLZ

OEn to An or B

n

1.5 3.2 6.0 1.5 6.0

t

PZH

Enable Time 1.5 3.5 5.5 1.5 5.5

ns

t

PZL

DIRn to An or B

n

1.5 3.2 5.5 1.5 5.5

t

PHZ

Disable Time 1.5 3.8 6.5 1.5 6.5

ns

t

PLZ

DIRn to An or B

n

1.5 3.2 6.5 1.5 6.5

Symbol Parameter

TA = +25°CT

A

= −40°C to +85°C

Units

V

CC

= +5.0V VCC = 4.5V–5.5V

CL = 50 pF CL = 50 pF

Min Max Min Max

tS(H) Setup Time, HIGH

2.0 2.0 ns

tS(L) or LOW Bus to Clock
tH(H) Hold Time, HIGH

1.0 1.0 ns

tH(L) or LOW Bus to Clock
tW(H) Pulse Width,

3.0 3.0 ns

tW(L) HIGH or LOW

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74ABT16646

Extended AC Electrical Characteristics

(SSOP Package)

Note 9: This specification is gu aranteed but not tested. The limits apply to propagation delays for all paths described s w it ch ing in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 10: This specification is guaranteed but no t tested. The limits represent propagation delay with 250 pF lo ad capacitors in place of the 50 pF load capac­itors in the standard AC load. This specification pertains to single output switching only.

Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.

Note 12: The 3-STATE delays are dominated by the RC n et work (500Ω, 250 pF) on the output and has been excluded from the datasheet.

Symbol Parameter

TA = −40°C to +85°CTA = −40°C to +85°CTA = −40°C to +85°C

Units

VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V

CL = 50 pF CL = 250 pF CL = 250 pF

8 Outputs Switching 1 Output Switching 8 Outputs Switching

(Note 9) (Note 10) (Note 11)

Min Max Min Max Min Max

t

PLH

Propagation Delay 1.5 5.8 2.0 7.5 2.5 10.0

ns

t

PHL

Clock to Bus 1.5 5.8 2.0 7.5 2.5 10.0

t

PLH

Propagation Delay 1.5 6.5 2.0 7.0 2.5 9.5

ns

t

PHL

Bus to Bus 1.5 6.5 2.0 7.0 2.5 9.5

t

PLH

Progagation Delay

1.5 6.0 2.0 7.5 2.5 10.0
ns

t

PHL

SBAn or SABn to An or B

n

1.5 6.0 2.0 7.5 2.5 10.0

t

PZH

Output Enable Time 1.5 6.0 2.0 8.0 2.5 10.5

ns

t

PZL

OEn to An or B

n

1.5 6.0 2.0 8.0 2.5 10.5

t

PHZ

Output Disable Time 1.5 6.0

(Note 12) (Note 12) ns

t

PLZ

OEn to An or B

n

1.5 6.0

t

PZH

Output Enable Time 1.5 6.5 2.0 8.0 2.5 10.5

ns

t

PZL

DIR to An or B

n

1.5 6.5 2.0 8.0 2.5 10.5

t

PHZ

Output Disable Time 1.5 6.5

(Note 12) (Note 12) ns

t

PLZ

DIR to An or B

n

1.5 6.5

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74ABT16646

Skew

(SOIC Package)

Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 14: This spec ification is guara nteed but no t tested. The lim its represen t propagation de lays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.

Note 15: Skew is def ined as the absolu te valu e of the differ ence be tween the actu al propag ation de lays f or any tw o separ ate outpu ts of the sam e devi ce.
The specification a pplies to any outputs s w it c hing HIGH to LOW (t

OSHL

), LOW to HIGH (t

OSLH

), or any combination switching LOW to HIGH and/or HIGH to

LOW (t

OST

). This specification is guaranteed but not tested.

Note 16: This describ es th e d ifferenc e b etw een t he del ay o f t he LO W-to -HIGH an d the HIGH -to -LOW tra nsitio n on t he s ame p in. It is mea sure d across all
the outputs (drivers) on t he same chip, the worst (largest delta) numb er is the guaranteed specification. This specification is guaranteed but not tested.

Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and V

CC

) from device to device. This specification is guaranteed but not

tested.

Capacitance

Note 18: C

I/O

is measured at frequency, f = 1 MHz, per MIL-STD-883, M et hod 3012.

Symbol Parameter

TA = −40°C to +85°CT

A

= −40°C to +85°C

Units

VCC = 4.5V–5.5V VCC = 4.5V–5.5V

CL = 50 pF CL = 250 pF

16 Outputs Switching 16 Outputs Switching

(Note 13) (Note 14)

Max Max

t

OSHL

Pin to Pin Skew

2.0 2.5 ns

(Note 15) HL Transitions
t

OSLH

Pin to Pin Skew

2.0 2.5 ns

(Note 15) LH Transitions
t

PS

Duty Cycle

2.0 2.5

(Note 16) LH–HL Skew
t

OST

Pin to Pin Skew

2.8 3.0 ns

(Note 15) LH/HL Transitions
t

PV

Device to Device Skew

3.5 4.0 ns

(Note 17) LH/HL Transitions

Symbol Parameter Typ Units

Conditions

TA = 25°C

C

IN

Input Capacitance 5 pF VCC = 0V (non I/O pins)

C

I/O

(Note 18) Output Capacitance 11 pF VCC = 5.0V (An, Bn)

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74ABT16646

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

Package Number MS56A

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74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 6.1mm Wide

Package Number MTD56

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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user.

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