Page 1
74ABT16543
74ABTH16543
16-bit latched transceivers with
dual enable (3-State)
Product specification
Supersedes data of 1995 Aug 17
IC23 Data Handbook
1998 Feb 27
INTEGRATED CIRCUITS
Page 2
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
2
1998 Feb 27 853-1739 19026
FEA TURES
•Two 8-bit octal transceivers with D-type latch
•Live insertion/extraction permitted
•Power-up 3-State
•Power-up reset
•Multiple V
CC
and GND pins minimize switching noise
•Back-to-back registers for storage
•Separate controls for data flow in each direction
•74ABTH16543 incorporates bus-hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
•See 74ABT161543 for same function with Master Reset control
pins
DESCRIPTION
The 74ABT16543 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16543 16-bit registered transceiver contains two sets of
D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (nLEAB
, nLEBA) and Output
Enable (nOEAB
, nOEBA) inputs are provided for each register to
permit independent control of data transfer in either direction. The
outputs are guaranteed to sink 64mA.
Two options are available, 74ABT16543 which does not have the
bus-hold feature and 74ABTH16543 which incorporates the
bus-hold feature.
QUICK REFERENCE DA TA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
nAx to nBx
CL = 50pF; VCC = 5V
2.5
2.2
ns
C
IN
Input capacitance VI = 0V or V
CC
3 pF
C
I/O
I/O capacitance VO = 0V or V
CC;
3-State 7 pF
I
CCZ
pp
Outputs disabled; VCC = 5.5V 550 µA
I
CCL
Quiescent su ly current
Outputs low; VCC = 5.5V 9 mA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16543 DL BT16543 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16543 DGG BT16543 DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16543 DL BH16543 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16543 DGG BH16543 DGG SOT364-1
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
1A0 – 1A7,
2A0 – 2A7
Data inputs/outputs
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40,38, 37, 36, 34, 33
1B0 – 1B7,
2B0 – 2B7
Data inputs/outputs
1, 56
28, 29
1OEAB, 1OEBA,
2OEAB, 2OEBA
A to B / B to A Output Enable inputs (active-Low)
3, 54
26, 31
1EAB, 1EBA,
2EAB, 2EBA
A to B / B to A Enable inputs (active-Low)
2, 55
27, 30
1LEAB, 1LEBA,
2LEAB, 2LEBA
A to B / B to A Latch Enable inputs (active-Low)
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
7, 22, 35, 50 V
CC
Positive supply voltage
Page 3
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
3
LOGIC SYMBOL (IEEE/IEC)
SH00036
5
6
8
9
10
12
13
14
16
17
19
20
21
23
24
56
1EN3
∇3
5D
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
15
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
6D 4 ∇
∇911D
12D
10 ∇
54
55
1
3
2
29
31
30
28
26
27
1OEBA
1EBA
1LEBA
1OEAB
1EAB
1LEAB
2OEBA
2EBA
2LEBA
2OEAB
2EAB
2LEAB
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
PIN CONFIGURA TION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
27
28
30
29
1OEAB
1LEAB
1EAB
GND
1A0
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
2A0
2A2
GND
2A3
V
CC
2A1
2A4
2A5
2A6
2A7
2EAB
V
CC
GND
2LEAB
2OEAB
1OEBA
1LEBA
1EBA
GND
1B0
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
2B0
2B2
GND
2B3
V
CC
2B1
2B4
2B5
2B6
2B7
2EBA
V
CC
GND
2LEBA
2OEBA
SH00037
Page 4
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
4
LOGIC SYMBOL
3
54
1EAB
1EBA
2 1LEAB
55 1LEBA
11OEAB
561OEBA
26
31
2EAB
2EBA
27 2LEAB
30 2LEBA
282OEAB
292OEBA
5 6 10 12 13 1489
52 51 47 45 44 4349 48
15 16 20 21 23 2417 19
42 41 37 36 34 3340 38
SH00038
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
FUNCTIONAL DESCRIPTION
The 74ABT16543 contains two sets of eight D-type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (nEAB
) input and the A-to-B Latch
Enable (nLEAB
) input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the nLEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB
and nOEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the nEBA
,
nLEBA
, and nOEBA inputs.
FUNCTION TABLE
INPUTS OUTPUTS
nOEXX nEXX nLEXX nAx or nBx nBx or nAx
STATUS
H X X X Z Disabled
X H X X Z Disabled
L
L
↑
↑
L
L
h
l
Z
Z
Disabled + Latch
L
L
L
L
↑
↑
h
l
H
L
Latch + Display
L
L
L
L
L
L
H
L
H
L
Transparent
L L H X NC Hold
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High transition of nLEXX
or nEXX (XX = AB or BA)
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High transition of nLEXX
or nEXX (XX = AB or BA)
X = Don’t care
↑ = Low-to-High transition of nLEXX
or nEXX (XX = AB or BA)
NC= No change
Z = High impedance or “off” state
Page 5
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
5
LOGIC DIAGRAM
D
LE
Q
D
LE
Q
DETAIL A
nB0
nB1nA1
nB2nA2
nB3nA3
nB4nA4
nB5nA5
nB6nA6
nB7nA7
DETAIL A X 7
nOEAB
nEAB
nLEAB
nOEBA
nEBA
nLEBA
nA0
SH00039
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER CONDITIONS RATING UNIT
V
CC
DC supply voltage –0.5 to +7.0 V
I
IK
DC input diode current VI < 0 –18 mA
V
I
DC input voltage
3
–1.2 to +7.0 V
I
OK
DC output diode current VO < 0 –50 mA
V
OUT
DC output voltage
3
output in Off or High state –0.5 to +5.5 V
p
output in Low state 128 mA
I
OUT
DC output current
output in High state –64 mA
T
stg
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Page 6
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
6
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
Min Max
UNIT
V
CC
DC supply voltage 4.5 5.5 V
V
I
Input voltage 0 V
CC
V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level Input voltage 0.8 V
I
OH
High-level output current –32 mA
I
OL
Low-level output current 64 mA
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
T
amb
= +25°C
T
amb
= –40°C
to +85°C
UNIT
MIN TYP MAX MIN MAX
V
IK
Input clamp voltage VCC = 4.5V; IIK = –18mA –1.2 –1.2 V
VCC = 4.5V; IOH = –3mA; VI = VIL or V
IH
2.5 2.9 2.5 V
V
OH
High-level output voltage
VCC = 5.0V; IOH = –3mA; VI = VIL or V
IH
3.0 3.4 3.0 V
VCC = 4.5V; IOH = –32mA; VI = VIL or V
IH
2.0 2.4 2.0 V
V
OL
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
IH
0.36 0.55 0.55 V
V
RST
Power-up output voltage
3
VCC = 5.5V; IO = 1mA; VI = GND or V
CC
0.13 0.55 0.55 V
Input leakage
;
Control
I
I
g
current
V
CC
= 5.5V
V
I
=
GND or 5.5V
pins
0.01
±1.0
±1.0
µA
VCC = 4.5V; VI = 0.8V 35 35
I
HOLD
B
us Hold current A or
B
5
VCC = 4.5V; VI = 2.0V –75 –75
µA
Ports 74ABTH16543
VCC = 5.5V; VI = 0 to 5.5V ±800
I
OFF
Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V 2.0 ±100 ±100 µA
I
PU/PD
Power-up/down 3-State
output current
4
VCC = 2.1V; VO = 0.0V or VCC;
VI = GND or VCC; VOE = Don’t care
1.0 ±50 ±50 µA
IIH + I
OZH
3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or V
IH
1.0 10 10 µA
IIL + I
OZL
3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or V
IH
–1.0 –10 –10 µA
I
CEX
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
CC
1.0 50 50 µA
I
O
Output current
1
VCC = 5.5V; VO = 2.5V –50 –100 –200 –50 –200 mA
I
CCH
VCC = 5.5V; Outputs High, VI = GND or V
CC
0.55 2 2 mA
I
CCL
pp
VCC = 5.5V; Outputs Low , VI = GND or V
CC
9 19 19 mA
I
CCZ
Quiescent su ly current
VCC = 5.5V; Outputs 3–State;
VI = GND or V
CC
0.55 2 2 mA
∆I
CC
Additional supply current
per input pin
2
74ABT16543
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
5.0 50 50 µA
∆I
CC
Additional supply current
per input pin
2
74ABTH16543
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
200 500 500 µA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V .
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V , with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transition time of up to 100µsec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
Page 7
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
7
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25oC
VCC = +5.0V
T
amb
= –40 to +85oC
VCC = +5.0V ±0.5V
UNIT
MIN TYP MAX MIN MAX
t
PLH
t
PHL
Propagation delay
nAx to nBx, nBx to nAx
2
1.0
1.0
2.5
2.2
3.3
4.4
1.0
1.0
3.8
5.1
ns
t
PLH
t
PHL
Propagation delay
LEBA
to nAx, LEAB to nBx
1, 2
1.0
1.2
3.1
3.0
4.3
4.8
1.0
1.2
5.2
5.6
ns
t
PZH
t
PZL
Output enable time
OEBA to nAx, OEAB to nBx
4
5
1.0
1.1
3.3
3.3
4.3
5.9
1.0
1.1
5.2
7.0
ns
t
PHZ
t
PLZ
Output disable time
OEBA to nAx, OEAB to nBx
4
5
1.9
1.6
3.5
2.6
5.0
4.2
1.9
1.6
5.7
4.6
ns
t
PZH
t
PZL
Output enable time
EBA to nAx, EAB to nBx
4
5
1.0
1.2
3.4
3.4
4.9
6.5
1.0
1.2
6.2
7.8
ns
t
PHZ
t
PLZ
Output disable time
EBA to nAx, EAB to nBx
4
5
2.0
1.7
3.4
2.6
5.6
5.1
2.0
1.7
6.6
5.4
ns
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25oC
VCC = +5.0V
T
amb
= –40 to +85oC
VCC = +5.0V ±0.5V
UNIT
MIN TYP MIN
ts(H)
ts(L)
Setup time
nAx to LEAB, nBx to LEBA
3
1.5
3.5
0.4
–0.1
1.5
3.5
ns
th(H)
th(L)
Hold time
nAx to LEAB, nBx to LEBA
3
1.5
2.0
0.2
–0.3
1.5
2.0
ns
ts(H)
ts(L)
Setup time
nAx to EAB, nBx to EBA
3
1.5
3.5
0.2
–0.3
1.5
3.5
ns
th(H)
t
h
(L)
Hold time
nAx to EAB
, nBx to EBA
3
1.5
2.0
0.3
–0.2
1.5
2.0
ns
tw(L) Latch enable pulse width, Low 3 4.0 3.1 4.0 ns
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
V
IN
V
M
t
PHL
t
PLH
V
M
V
M
V
M
V
OUT
SH00040
Waveform 1. Propagation Delay For Inverting Output
V
M
t
PLH
t
PHL
V
M
V
M
V
M
V
IN
V
OUT
SH00041
Waveform 2. Propagation Delay For Non-Inverting Output
Page 8
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
8
AC WAVEFORMS (Continued)
VM = 1.5V, VIN = GND to 3.0V
V
M
nAx, nBx
V
M
V
M
V
M
V
MVM
nLEAB, nLEBA,
nEAB
, nEBA
ts(H)
t
h
(H)
t
s
(L)
t
h
(L)
tw(L)
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SH00042
Waveform 3. Data Setup and Hold Times and Latch Enable
Pulse Width
nOEAB, nOEBA,
nEAB, nEBA
V
M
t
PZH
t
PHZ
0V
V
OH
–0.3V
V
M
V
M
nAx, nBx
V
OH
SH00043
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
t
PZL
t
PLZ
VOL +0.3V
V
M
V
M
V
M
nOEAB, nOEBA,
nEAB, nEBA
nAx, nBx
V
OL
SH00044
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORMS
PULSE
GENERATOR
R
T
V
IN
D.U.T.
V
OUT
R
L
V
CC
R
L
7.0V
Test Circuit for 3-State Outputs
V
M
V
M
t
W
AMP (V)
NEGATIVE
PULSE
10% 10%
90%
90%
0V
V
M
V
M
t
W
AMP (V)
POSITIVE
PULSE
90% 90%
10%
10%
0V
t
THL
(tF)
t
TLH
(tR)t
THL
(tF)
t
TLH
(tR)
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate t
W
t
R
t
F
74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns
SWITCH POSITION
TEST SWITCH
t
PLZ
closed
t
PZL
closed
All other open
SA00018
C
L
Page 9
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
9
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1
Page 10
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
10
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1
Page 11
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
1998 Feb 27
11
NOTES
Page 12
Philips Semiconductors Product specification
74ABT16543
74ABTH16543
16-bit latched transceivers with dual enable
(3-State)
yyyy mmm dd
12
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-03496
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
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