Datasheet 5962-8968201LA, 5962-89682013A, 5962-8968201KA, 54AC646SDMQB-RH, 54AC646MDA Datasheet (NSC)

54AC646
Octal Transceiver/Register with TRI-STATE

®

Outputs

General Description

The ’AC646 consist of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on theAor B bus
will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in

Figures 1, 2, 3, 4

.

Features

n Independent registers for A and B buses

n Multiplexed real-time and stored data transfers
n TRI-STATE outputs
n 300 mil slim dual-in-line package
n Outputs source/sink 24 mA
n ’ACT646 has TTL compatible inputs
n Standard Microcircuit Drawing (SMD)

—’AC646: 5962-89682

Logic Symbols

Pin Names Description

A

0–A7

Data Register A Inputs
Data Register A Outputs

B

0–B7

Data Register B Inputs

Data Register B Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Transmit/Receive Inputs
G

Output Enable Input
DIR Direction Control Input

TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT

®

is a registered trademark of Fairchild Semiconductor Corporation.

DS100231-1

IEEE/IEC

DS100231-2

August 1998

54AC646 Octal Transceiver/Register with TRI-STATE Outputs

© 1998 National Semiconductor Corporation DS100231 www.national.com

Connection Diagrams

Pin Assignment

for DIP and Flatpak

DS100231-3

Pin Assignment

for LCC

DS100231-4

Real Time Transfer

A-Bus to B-Bus

DS100231-7

FIGURE 1.

Real Time Transfer

B-Bus to A-Bus

DS100231-8

FIGURE 2.

Storage from

Bus to Register

DS100231-9

FIGURE 3.

Transfer from

Register to Bus

DS100231-10

FIGURE 4.

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Function Table

Inputs Data I/O (Note 1) Function

G

DIR CPAB CPBA SAB SBA A0–A7B0–B

7

H X H or L H or L X X Isolation
HX

N

X X X Input Input Clock AnData into A Register

HX X

N

X X Clock BnData into B Register

LH X X L X A

n

to Bn—Real Time (Transparent Mode)

LH

N

X L X Input Output Clock AnData into A Register

L H H or L X H X A Register to B

n

(Stored Mode)

LH

N

X H X Clock AnData into A Register and Output to B

n

LL X X X L Bnto An—Real Time (Transparent Mode)
LL X

N

X L Output Input Clock BnData into B Register

L L X H or L X H B Register to A

n

(Stored Mode)

LL X

N

X H Clock BnData into B Register and Output to A

n

H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial

N

=

LOW-to-HIGH Transition

Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the
bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.

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Logic Diagram

DS100231-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

CC

) −0.5V to +7.0V

DC Input Diode Current (I

IK

)

V

I

=

−0.5V −20 mA

V

I

=

V

CC

+ 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC+ 0.5V

DC Output Diode Current (I

OK

)

V

O

=

−0.5V −20 mA

V

O

=

V

CC

+ 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC+ 0.5V

DC Output Source

or Sink Current (I

O

)

±

50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

)

±

50 mA

Storage Temperature (T

STG

) −65˚C to +150˚C

Junction Temperature (T

J

)

CDIP 175˚C

Recommended Operating
Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V

Input Voltage (V

I

) 0VtoV

CC

Output Voltage (VO) 0VtoV

CC

Operating Temperature (TA)

54AC −55˚C to +125˚C

Minimum Input Edge Rate (∆V/∆t)

’AC Devices
V

IN

from 30%to 70%of V

CC

V

CC

@

3.3V, 4.5V, 5.5V 125 mV/ns

Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom­mend operation of FACT

®

circuits outside databook specifications.

DC Characteristics for ’AC Family Devices

54AC

Symbol Parameter V

CC

T

A

=

Units Conditions

(V) −55˚C to +125˚C

Guaranteed

Limits

V

IH

Minimum High Level 3.0 2.1 V

OUT

=

0.1V

Input Voltage 4.5 3.15 V or V

CC

− 0.1V

5.5 3.85

V

IL

Maximum Low Level 3.0 0.9 V

OUT

=

0.1V

Input Voltage 4.5 1.35 V or V

CC

− 0.1V

5.5 1.65

V

OH

Minimum High Level 3.0 2.9 I

OUT

=

−50 µA

Output Voltage 4.5 4.4 V

5.5 5.4
(Note 3)

V

IN

=

V

IL

or V

IH

3.0 2.4 IOH= −12 mA

4.5 3.7 V I

OH

= −24 mA

5.5 4.7 I

OH

= −24 mA

V

OL

Maximum Low Level 3.0 0.1 I

OUT

=

50 µA

Output Voltage 4.5 0.1 V

5.5 0.1
(Note 3)

V

IN

=

V

IL

or V

IH

3.0 0.50 IOH=12mA

4.5 0.50 V I

OL

=24mA

5.5 0.50 I

OH

=24mA

I

IN

Maximum Input 5.5

±

1.0 µA V

I

=

V

CC

, GND

Leakage Current

I

OLD

Minimum Dynamic
Output Current
(Note 4)

5.5 50 mA V

OLD

=

1.65V Max

I

OHD

5.5 −50 mA V

OHD

=

3.85V Min

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DC Characteristics for ’AC Family Devices (Continued)

54AC

Symbol Parameter V

CC

T

A

=

Units Conditions

(V) −55˚C to +125˚C

Guaranteed

Limits

I

CC

Maximum Quiescent 5.5 160.0 µA V

IN

=

V

CC

Supply Current or GND

I

OZT

Maximum I/O VI(OE)=VIL,V

IH

Leakage Current 5.5

±

10.0 µA V

I

=

V

CC

, GND

V

O

=

V

CC

, GND

Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I

IN

and I

CC

@

3.0V are guaranteed to be less than or equal to the respective limit@5.5V VCC.

I

CC

for 54AC@25˚C is identical to 74AC@25˚C.

AC Electrical Characteristics

54AC

V

CC

T

A

=

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 6) C

L

=

50 pF

Min Max

t

PLH

Propagation Delay 3.3 1.0 20.0 ns
Clock to Bus 5.0 1.5 14.0

t

PHL

Propagation Delay 3.3 1.0 17.5 ns
Clock to Bus 5.0 1.5 12.0

t

PLH

Propagation Delay 3.3 1.0 15.0 ns
Bus to Bus 5.0 1.5 10.0

t

PHL

Propagation Delay 3.3 1.0 14.5 ns
Bus to Bus 5.0 1.5 9.5

t

PLH

Propagation Delay 3.3 1.0 17.0
SBA or SAB to A

n

or B

n

5.0 1.5 12.0 ns

(w/ A

n

or BnHIGH or LOW)

t

PHL

Propagation Delay 3.3 1.0 17.0
SBA or SAB to A

n

or B

n

5.0 1.5 12.0 ns

(w/ A

n

or BnHIGH or LOW)

t

PZH

Enable Time 3.3 1.0 13.0 ns
GtoA

n

or B

n

5.0 1.5 9.5

t

PZL

Enable Time 3.3 1.0 15.5 ns
GtoA

n

or B

n

5.0 1.5 11.0

t

PHZ

Disable Time 3.3 1.0 14.0 ns
GtoA

n

or B

n

5.0 1.5 11.0

t

PLZ

Disable Time 3.3 1.0 13.5 ns
GtoA

n

or B

n

5.0 1.5 11.0

t

PZH

Enable Time 3.3 1.0 14.5 ns
DIR to A

n

or B

n

5.0 1.5 10.5

t

PZL

Enable Time 3.3 1.0 16.0 ns
DIR to A

n

or B

n

5.0 1.5 12.5

t

PHZ

Disable Time 3.3 1.0 14.5 ns
DIR to A

n

or B

n

5.0 1.5 12.0

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AC Electrical Characteristics (Continued)

54AC

V

CC

T

A

=

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 6) C

L

=

50 pF

Min Max

t

PLZ

Disable Time 3.3 1.0 16.5 ns
DIR to A

n

or B

n

5.0 1.5 12.0

Note 6: Voltage Range 3.3 is 3.3V±0.3V
Voltage Range 5.0 is 5.0V

±

0.5V

AC Operating Requirements

54AC

V

CC

T

A

=

−55˚C Fig.

Symbol Parameter (V) to +125˚C Units No.

(Note 7) C

L

=

50 pF

Guaranteed

Minimum

t

s

Setup Time, HIGH or LOW 3.3 6.0 ns
Bus to Clock 5.0 4.5

t

h

Hold Time, HIGH or LOW 3.3 1.5 ns
Bus to Clock 5.0 2.0

t

w

Clock Pulse Width 3.3 5.0 ns
HIGH or LOW 5.0 5.0

Note 7: Voltage Range 3.3 is 3.3V±0.3V
Voltage Range 5.0 is 5.0V

±

0.5V

Capacitance

Symbol Parameter Typ Units Conditions

C

IN

Input Capacitance 4.5 pF V

CC

=

OPEN

C

I/O

Input/Output Capacitance 15.0 pF V

CC

=

5.0V

C

PD

Power Dissipation 60.0 pF V

CC

=

5.0V

Capacitance

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8

Physical Dimensions inches (millimeters) unless otherwise noted

28-Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E28A

24-Lead Slim (0.300" Wide) Ceramic Dual-In-Line Package (SD)

NS Package Number J24F

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE­VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI­CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys­tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail­ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

2. A critical component in any component of a life support
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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Corporation

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24-Lead Ceramic Flatpak (F)

NS Package Number W24C

54AC646 Octal Transceiver/Register with TRI-STATE Outputs

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.