Datasheet AD844SQ-883B, AD844SQ, AD844SCHIPS, AD844JR-16-REEL7, AD844JR-16-REEL Datasheet (Analog Devices)

60 MHz, 2000 V/s

a

FEATURES
Wide Bandwidth: 60 MHz at Gain of –1
Wide Bandwidth: 33 MHz at Gain of –10
Very High Output Slew Rate: Up to 2000 V/s
20 MHz Full Power Bandwidth, 20 V p-p, R
Fast Settling: 100 ns to 0.1% (10 V Step)
Differential Gain Error: 0.03% at 4.4 MHz
Differential Phase Error: 0.158 at 4.4 MHz
High Output Drive: 650 mA into 50  Load
Low Offset Voltage: 150 mV Max (B Grade)
Low Quiescent Current: 6.5 mA
Available in Tape and Reel in Accordance with
EIA-481A Standard

APPLICATIONS
Flash ADC Input Amplifiers
High-Speed Current DAC Interfaces
Video Buffers and Cable Drivers
Pulse Amplifiers

PRODUCT DESCRIPTION

The AD844 is a high-speed monolithic operational amplifier
fabricated using Analog Devices’ junction isolated complemen­tary bipolar (CB) process. It combines high bandwidth and very
fast large signal response with excellent dc performance. Although
optimized for use in current to voltage applications and as an
inverting mode amplifier, it is also suitable for use in many
noninverting applications.

The AD844 can be used in place of traditional op amps, but its
current feedback architecture results in much better ac perfor­mance, high linearity and an exceptionally clean pulse response.

This type of op amp provides a closed-loop bandwidth which is
determined primarily by the feedback resistor and is almost inde­pendent of the closed-loop gain. The AD844 is free from the slew
rate limitations inherent in traditional op amps and other
current-feedback op amps. Peak output rate of change can be over
2000 V/µs for a full 20 V output step. Settling time is typically
100 ns to 0.1%, and essentially independent of gain. The AD844
can drive 50 Ω loads to ±2.5 V with low distortion and is short
circuit protected to 80 mA.

The AD844 is available in four performance grades and three
package options. In the 16-lead SOIC (R) package, the AD844J is
specified for the commercial temperature range of 0°C to 70°C.
The AD844A and AD844B are specified for the industrial tem­perature range of –40°C to +85°C and are available in the cerdip (Q)

= 500 

L

Monolithic Op Amp

AD844

CONNECTION DIAGRAMS

8-Lead Plastic (N),

and Cerdip (Q) Packages

NULL

–IN

+IN

–V

1

2

3

4

S

(Not to Scale)

AD844

TOP VIEW

8

NULL

7

+V

6

OUTPUT

5

TZ

S

OFFSETNULL

package. The AD844A is also available in an 8-lead plastic
mini-DIP (N). The AD844S is specified over the military tempera­ture range of –55°C to +125°C. It is available in the 8-lead
cerdip (Q) package. “A” and “S” grade chips and devices processed
to MIL-STD-883B, REV. C are also available.

PRODUCT HIGHLIGHTS

1. The AD844 is a versatile, low cost component providing an
excellent combination of ac and dc performance.

2. It is essentially free from slew rate limitations. Rise and fall
times are essentially independent of output level.

3. The AD844 can be operated from ±4.5 V to ±18 V power
supplies and is capable of driving loads down to 50 Ω, as well
as driving very large capacitive loads using an external network.

4. The offset voltage and input bias currents of the AD844 are
laser trimmed to minimize dc errors; V
1 µV/°C and bias current drift is typically 9 nA/°C.

5. The AD844 exhibits excellent differential gain and differen­tial phase characteristics, making it suitable for a variety of
video applications with bandwidths up to 60 MHz.

6. The AD844 combines low distortion, low noise and low drift
with wide bandwidth, making it outstanding as an input
amplifier for flash A/D converters.

16-Lead SOIC

(R) Package

1

NC

AD844

2

3

–IN

4

NC

5

+IN

6

NC

7

V–

TOP VIEW

8

NC

(Not to Scale)

NC = NO CONNECT

drift is typically

OS

16

NC

15

OFFSETNULL

14

V+

13

NC

12

OUTPUT

11

TZ

10

NC

9

NC

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD844–SPECIFICATIONS

(@ TA = 25C and VS = 15 V dc, unless otherwise noted)

Model Conditions Min Typ Max Min Typ Max Min Typ Max Unit

AD844J/A AD844B AD844S

INPUT OFFSET VOLTAGE

T

MIN–TMAX

1

50 300 50 150 50 300 µV
75 500 75 200 125 500 µV

vs. Temperature 1 1 5 1 5 µV/°C
vs. Supply 5 V–18 V

Initial 4 20 4 10 4 20 µV/V
T

MIN–TMAX

vs. Common Mode V

= ±10 V

CM

4410420µV/V

Initial 10 35 10 20 10 35 µV/V
T

MIN–TMAX

INPUT BIAS CURRENT

–Input Bias Current
T

MIN–TMAX

1

10 10 20 10 35 µV/V

200 450 150 250 200 450 nA
800 1500 750 1100 1900 2500 nA

vs. Temperature 9 9 15 20 30 nA/°C
vs. Supply 5 V–18 V

Initial 175 250 175 200 175 250 nA/V
T

MIN–TMAX

vs. Common Mode V

= ±10 V

CM

220 220 240 220 300 nA/V

Initial 90 160 90 110 90 160 nA/V
T

MIN–TMAX

+Input Bias Current
T

MIN–TMAX

1

110 110 150 120 200 nA/V
150 400 100 200 100 400 nA
350 700 300 500 800 1300 nA

vs. Temperature 3 3 7 7 15 nA/°C
vs. Supply 5 V–18 V

Initial 80 150 80 100 80 150 nA/V
T

MIN–TMAX

vs. Common Mode V

= ±10 V

CM

100 100 120 120 200 nA/V

Initial 90 150 90 120 90 150 nA/V
T

MIN–TMAX

130 130 190 140 200 nA/V

INPUT CHARACTERISTICS

Input Resistance

–Input 50 65 50 65 50 65 Ω
+Input 7 10 7 10 7 10 MΩ

Input Capacitance

–Input 2 2 2 pF
+Input 2 2 2 pF

Input Voltage Range
Common Mode ±10 ±10 ±10 V

INPUT VOLTAGE NOISE f ≥ 1 kHz 2 2 2 nV/√Hz

INPUT CURRENT NOISE

–Input f ≥ 1 kHz 10 10 10 pA/√Hz
+Input f ≥ 1 kHz 12 12 12 pA/√Hz

OPEN LOOP TRANSRESISTANCE V

T

MIN–TMAX

= ±10 V

OUT

= 500 Ω 2.2 3.0 2.8 3.0 2.2 3.0 MΩ

R

LOAD

1.3 2.0 1.6 2.0 1.3 1.6 MΩ

Transcapacitance 4.5 4.5 4.5 pF

DIFFERENTIAL GAIN ERROR

2

f = 4.4 MHz 0.03 0.03 0.03 %

DIFFERENTIAL PHASE ERROR2f = 4.4 MHz 0.15 0.15 0.15 Degree

FREQUENCY RESPONSE

Small Signal Bandwidth

Gain = –1
Gain = –10

TOTAL HARMOMIC DISTORTION f = 100 kHz,

3

4

5

2 V rms

60 60 60 MHz
33 33 33 MHz

0.005 0.005 0.005 %

SETTLING TIME

10 V Output Step ±15 V Supplies

Gain = –1, to 0.1%
Gain = –10, to 0.1%

2 V Output Step ± 5 V Supplies

Gain = –1, to 0.1%
Gain = –10, to 0.1%

5

6

5

6

100 100 100 ns
100 100 100 ns

110 110 110 ns
100 100 100 ns

–2–

REV. D

AD844

Model Conditions Min Typ Max Min Typ Max Min Typ Max Unit

AD844J/A AD844B AD844S

OUTPUT SLEW RATE Overdriven

Input 1200 2000 1200 2000 1200 2000 V/µs

FULL POWER BANDWIDTH

= 20 V p-p

V

OUT

= 2 V p-p

V

OUT

5

5

VS = ±15 V 20 20 20 MHz
VS = ±5 V 20 20 20 MHz
THD = 3%

OUTPUT CHARACTERISTICS

Voltage R

= 500 Ω 10 11 10 11 10 11 ± V

LOAD

Short Circuit Current 80 80 80 mA
T

MIN–TMAX

60 60 60 mA

Output Resistance Open Loop 15 15 15 Ω

POWER SUPPLY

Operating Range ±4.5 ± 18 ± 4.5 ±18 +4.5 ±18 V
Quiescent Current 6.5 7.5 6.5 7.5 6.5 7.5 mA
T

MIN–TMAX

NOTES

1

Rated performance after a 5 minute warmup at TA = 25°C.

2

Input signal 285 mV p-p carrier (40 IRE) riding on 0 mV to 642 mV (90 IRE) ramp. RL= 100 Ω; R1, R2 = 300 Ω.

3

Input signal 0 dBm, CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 500 Ω in Figure 2.

4

Input signal 0 dBm, CL =10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 50 Ω in Figure 2.

5

CL = 10 pF, RL = 500 Ω, R1 = 1 kΩ, R2 = 1 kΩ in Figure 2.

6

CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 50 Ω in Figure 2.

Specifications subject to change without notice. All min and max specifications are guaranteed.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Power Dissipation

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W

1

Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite

Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . ± V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Inverting Input Current

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA

7.5 8.5 7.5 8.5 8.5 9.5 mA

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability.

S

2

8-Lead Plastic Package: θ

8-Lead Cerdip Package: θJA = 110°C/W
16-Lead SOIC Package: θJA = 100°C/W

= 90°C/W

JA

Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C

Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V

METALIZATION PHOTOGRAPH

Contact factory for latest dimensions.

Dimension shown in inches and (mm).

ORDERING GUIDE

Temperature Package

Model Range Option

*

AD844AN –40°C to +85°C N-8
AD844ACHIPS –40°C to +85°CDie
AD844AQ –40°C to +85°C Q-8
AD844BQ –40°C to +85°C Q-8
AD844JR-16 0°C to 70°C R-16
AD844JR-16-REEL 0°C to 70°C 13" Tape

and Reel

AD844JR-16-REEL7 0°C to 70°C 7" Tape

and Reel

AD844SCHIPS –55°C to +125°CDie
AD844SQ –55°C to +125°C Q-8
AD844SQ/883B –55°C to +125°C Q-8

5962-8964401PA –55°C to +125°C Q-8

*

N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).

REV. D

–3–

AD844–Typical Characteristics

(TA = 25C and VS = 15 V, unless otherwise noted)

70

60

50

40

–3dB BANDWIDTH – MHz

30

05 20

10 15

SUPPLY VOLTAGE – V

TPC 1. –3 dB Bandwidth vs.
Supply Voltage R1 = R2 = 500

20

TA = 25C

15

10

5

Ω

–60

–70

HARMONIC DISTORTION – dB

–80

–90

–100

–110

–120

–130

1V rms

2ND HARMONIC

3RD HARMONIC

100 1k 100k

INPUT FREQUENCY – Hz

10k

TPC 2. Harmonic Distortion vs.
Frequency, R1 = R2 = 1 k

20

RL = 500
T

= 25C

A

15

10

5

5

4

3

2

TRANSRESISTANCE – M

1

0

–50 150

0 50 100

TEMPERATURE – C

R

=

L

RL = 500

RL = 50

TPC 3. Transresistance vs.

Ω

Temperature

10

9

8

7

VS = 15V

6

SUPPLY CURRENT – mA

5

V

S

= 5V

MAGNITUDE OF THE OUTPUT VOLTAGE – V

0

05 20

10 15

SUPPLY VOLTAGE – V

TPC 4. Noninverting Input Voltage
Swing vs. Supply Voltage

2

1

I

0

–1

INPUT BIAS CURRENT – A

–2

–50 150

0 50 100

TEMPERATURE – C

BP

I

BN

TPC 7. Inverting Input Bias Cur­rent (I
Bias Current (I

) and Noninverting Input

BN

) vs. Temperature

BP

MAGNITUDE OF THE OUTPUT VOLTAGE – V

0

05 20

10 15

SUPPLY VOLTAGE – V

TPC 5. Output Voltage Swing
vs. Supply Voltage

100

10

5V SUPPLIES

1

0.1

OUTPUT IMPEDANCE – 

0.01
10k 100k 100M

1M 10M

FREQUENCY – Hz

TPC 8. Output Impedance vs.
Frequency, Gain = –1, R1 = R2 = 1 k

4
–60

0

–40 –20 40 60 80 100 120 140

20

TEMPERATURE – C

TPC 6. Quiescent Supply
Current vs. Temperature and
Supply Voltage

40

35

30

25

20

–3dB BANDWIDTH – MHz

15

10

–40 –20 40 60 80 100 120 140

–60

020

TEMPERATURE – C

VS = 15V

V

= 5V

S

TPC 9. –3 dB Bandwidth vs.

Ω

Temperature, Gain = –1,
R1 = R2 = 1 k

Ω

–4–

REV. 0

Inverting Gain-of-1 AC Characteristics

AD844

+V

S

–

AD844

+

0.22F

–V

4.7

R1

R

L

4.7

S

0.22F

R2

V

IN

TPC 10. Inverting Amplifier,
Gain of –1 (R1 = R2)

6

0

–6

V

OUT

C

L

GAIN – dB

–12

–18

–24

100k 1M 100M10M

FREQUENCY – Hz

R1 = R2 = 500

R1 = R2 = 1k

TPC 11. Gain vs. Frequency for
Gain = –1, R

= 500 Ω, CL = 0 pF

L

–180

–210

–240

–270

PHASE – Degrees

–300

–330

050

R1 = R2 = 1k

FREQUENCY – MHz

R1 = R2 = 500

25

TPC 12. Phase vs. Frequency
Gain = –1, R

= 500 Ω, CL = 0 pF

L

TPC 13. Large Signal Pulse
Response, Gain = –1, R1 = R2 = 1 k

Ω

Inverting Gain-of-10 AC Characteristics

26

+V

S

0.22F

50

V

IN

4.7

500

–

AD844

+

R

L

0.22F

4.7

–V

S

TPC 15. Gain of –10 Amplifier

V

OUT

C

L

20

14

GAIN – dB

8

2

–4

100k 1M 100M10M

FREQUENCY – Hz

TPC 16. Gain vs. Frequency,
Gain = –10

RL = 500

RL = 50

TPC 14. Small Signal Pulse
Response, Gain = –1, R1 = R2 = 1 k

–180

–210

–240

–270

PHASE – Degrees

–300

–330

050

R

= 50

L

FREQUENCY – MHz

TPC 17. Phase vs. Frequency,
Gain = –10

Ω

RL = 500

25

REV. D

–5–

AD844

Inverting Gain-of-10 Pulse Response

TPC 18. Large Signal Pulse
Response, Gain = –10, R

= 500

L

Ω

Noninverting Gain-of-10 AC Characteristics

26

+V

50

V

S

IN

–V

S

4.7

–

AD844

+

4.7

0.22F

450

0.22F
R

L

TPC 20. Noninverting Gain of
+10 Amplifier

V

OUT

20

14

GAIN – dB

8

C

2

L

–4

100k 1M 100M10M

FREQUENCY – Hz

TPC 21. Gain vs. Frequency,
Gain = +10

RL = 50

TPC 19. Small Signal Pulse
Response, Gain = –10, R

–180

R

= 500

L

–210

–240

–270

PHASE – Degrees

–300

–330

= 500

L

RL = 50k

050

FREQUENCY – MHz

Ω

R

= 500

L

25

TPC 22. Phase vs. Frequency,
Gain = +10

TPC 23. Noninverting Amplifier Large
Signal Pulse Response, Gain = +10,
RL = 500

Ω

–6–

TPC 24. Small Signal Pulse
Response, Gain = +10, R

= 500

L

Ω

REV. D

AD844

UNDERSTANDING THE AD844

The AD844 can be used in ways similar to a conventional op
amp while providing performance advantages in wideband
applications. However, there are important differences in the
internal structure which need to be understood in order to
optimize the performance of the AD844 op amp.

Open Loop Behavior

Figure 1 shows a current feedback amplifier reduced to essen­tials. Sources of fixed dc errors such as the inverting node bias
current and the offset voltage are excluded from this model and
are discussed later. The most important parameter limiting the
dc gain is the transresistance, Rt, which is ideally infinite. A finite
value of R

is analogous to the finite open loop voltage gain in a

t

conventional op amp.

The current applied to the inverting input node is replicated by
the current conveyor so as to flow in resistor R
developed across R
Voltage gain is the ratio R
and R

= 50 Ω, the voltage gain is about 60,000. The open

IN

is buffered by the unity gain voltage follower.

t

/ RIN. With typical values of Rt = 3 MΩ

t

. The voltage

t

loop current gain is another measure of gain and is determined
by the beta product of the transistors in the voltage follower
stage (see Figure 4); it is typically 40,000.

+1

I

IN

R

IN

I

IN

R

t

C

t

+1

Figure 1. Equivalent Schematic

The important parameters defining ac behavior are the trans­capacitance, C

, and the external feedback resistor (not shown).

t

The time constant formed by these components is analogous to
the dominant pole of a conventional op amp, and thus cannot
be reduced below a critical value if the closed loop system is to
be stable. In practice, C

is held to as low a value as possible

t

(typically 4.5 pF) so that the feedback resistor can be maximized
while maintaining a fast response. The finite R

also affects the

IN

closed loop response in some applications as will be shown.

The open loop ac gain is also best understood in terms of the
transimpedance rather than as an open loop voltage gain. The
open loop pole is formed by R

in parallel with Ct. Since Ct is

t

typically 4.5 pF, the open loop corner frequency occurs at
about 12 kHz. However, this parameter is of little value in
determining the closed loop response.

Response as an Inverting Amplifier

Figure 2 shows the connections for an inverting amplifier.
Unlike a conventional amplifier the transient response and the
small signal bandwidth are determined primarily by the value of
the external feedback resistor, R1, rather than by the ratio of
R1/R2 as is customarily the case in an op amp application. This
is a direct result of the low impedance at the inverting input. As
with conventional op amps, the closed loop gain is –R1/R2.

The closed loop transresistance is simply the parallel sum of R1
and R

. Since R1 will generally be in the range 500 Ω to 2 kΩ

t

is about 3 MΩ the closed loop transresistance will be

and R

t

only 0.02% to 0.07% lower than R1. This small error will often
be less than the resistor tolerance.

When R1 is fairly large (above 5 kΩ) but still much less than R

,

t

the closed loop HF response is dominated by the time constant

. Under such conditions the AD844 is over-damped and

R1C

t

will provide only a fraction of its bandwidth potential. Because
of the absence of slew rate limitations under these conditions,
the circuit will exhibit a simple single pole response even under
large signal conditions.

In Figure 2, R3 is used to properly terminate the input if desired.
R3 in parallel with R2 gives the terminated resistance. As R1 is
lowered, the signal bandwidth increases, but the time constant
R1C

becomes comparable to higher order poles in the closed

t

loop response. Therefore, the closed loop response becomes
complex, and the pulse response shows overshoot. When R2 is
much larger than the input resistance, R

, at Pin 2, most of the

IN

feedback current in R1 is delivered to this input; but as R2
becomes comparable to R

, less of the feedback is absorbed at

IN

Pin 2, resulting in a more heavily damped response. Conse­quently, for low values of R2 it is possible to lower R1 without
causing instability in the closed loop response. Table I lists
combinations of R1 and R2 and the resulting frequency response
for the circuit of Figure 2. TPC 13 shows the very clean and fast
±10 V pulse response of the AD844.

R1

V

IN

OPTIONAL

R2

R3

AD844

V

OUT

R

L

C

L

Figure 2. Inverting Amplifier

REV. D

–7–

AD844

Table I.

Gain R1 R2 BW (MHz) GBW (MHz)

–1 1 kΩ 1 kΩ 35 35
–1 500 Ω 500 Ω 60 60
–2 2 kΩ 1 kΩ 15 30
–2 1 kΩ 500 Ω 30 60
–5 5 kΩ 1 kΩ 5.2 26
–5 500 Ω 100 Ω 49 245
–10 1 kΩ 100 Ω 23 230
–10 500 Ω 50 Ω 33 330
–20 1 kΩ 50 Ω 21 420
–100 5 kΩ 50 Ω 3.2 320
+100 5 kΩ 50 Ω 9 900

Response as an I-V Converter

The AD844 works well as the active element in an operational
current to voltage converter, used in conjunction with an exter­nal scaling resistor, R1, in Figure 3. This analysis includes the
stray capacitance, C

, of the current source, which might be a

S

high speed DAC. Using a conventional op amp, this capacitance
forms a “nuisance pole” with R1 which destabilizes the closed
loop response of the system. Most op amps are internally com­pensated for the fastest response at unity gain, so the pole due
to R1 and C
system. For example, if R1 were 2.5 kΩ a C

reduces the already narrow phase margin of the

S

of 15 pF would

S

place this pole at a frequency of about 4 MHz, well within the
response range of even a medium speed operational amplifier.
In a current feedback amp this nuisance pole is no longer deter­mined by R1 but by the input resistance, R

. Since this is about

IN

50 Ω for the AD844, the same 15 pF forms a pole 212 MHz
and causes little trouble. It can be shown that theresponse of
this system is:

V

= – Isig

OUT

KR1

(1 + sTd )(1 + sTn )

where K is a factor very close to unity and represents the finite
dc gain of the amplifier, Td is the dominant pole and Tn is the
nuisance pole:

I

SIG

C

S

R1

AD844

V

OUT

R

L

C

L

Figure 3. Current-to-Voltage Converter

Circuit Description of the AD844

A simplified schematic is shown in Figure 4. The AD844 differs
from a conventional op amp in that the signal inputs have
radically different impedance. The noninverting input (Pin 3)
presents the usual high impedance. The voltage on this input is
transferred to the inverting input (Pin 2) with a low offset
voltage, ensured by the close matching of like polarity transis­tors operating under essentially identical bias conditions. Laser
trimming nulls the residual offset voltage, down to a few
tens of microvolts. The inverting input is the common emitter
node of a complementary pair of grounded base stages and
behaves as a current summing node. In an ideal current feed­back op amp the input resistance would be zero. In the AD844
it is about 50 Ω.

A current applied to the inverting input is transferred to a
complementary pair of unity-gain current mirrors which deliver
the same current to an internal node (Pin 5) at which the full
output voltage is generated. The unity-gain complementary
voltage follower then buffers this voltage and provides the load
driving power. This buffer is designed to drive low impedance
loads such as terminated cables, and can deliver ±50 mA into a
50 Ω load while maintaining low distortion, even when operat­ing at supply voltages of only ±6 V. Current limiting (not
shown) ensures safe operation under short circuited conditions.

+V

7

S

I

B

R

=

RR

+ 1

t

t

t

K

Td = KR1C

Tn = RINCS (assuming RIN << R1)

Using typical values of R1 = 1 kΩ and R

= 3 MΩ, K is 0.9997;

t

in other words, the “gain error” is only 0.03%. This is much less
than the scaling error of virtually all DACs and can be absorbed,
if necessary, by the trim needed in a precise system.

In the AD844, R

is fairly stable with temperature and supply

t

voltages, and consequently the effect of finite “gain” is negli­gible unless high value feedback resistors are used. Since that
would result in slower response times than are possible, the
relatively low value of R

in the AD844 will rarely be a signifi-

t

cant source of error.

–8–

325 6

+IN OUT

I

B

–IN

TZ

–V

4

S

Figure 4. Simplified Schematic

REV. D

AD844

It is important to understand that the low input impedance at
the inverting input is locally generated, and does not depend on
feedback. This is very different from the “virtual ground” of a
conventional operational amplifier used in the current summing
mode which is essentially an open circuit until the loop settles.
In the AD844, transient current at the input does not cause
voltage spikes at the summing node while the amplifier is settling.
Furthermore, all of the transient current is delivered to the
slewing (TZ) node (Pin 5) via a short signal path (the grounded
base stages and the wideband current mirrors).

The current available to charge the capacitance (about 4.5 pF)
at TZ node, is always proportional to the input error current, and
the slew rate limitations associated with the large signal response
of op amps do not occur. For this reason, the rise and fall times
are almost independent of signal level. In practice, the input
current will eventually cause the mirrors to saturate. When using
±15 V supplies, this occurs at about 10 mA (or ±2200 V/µs).
Since signal currents are rarely this large, classical “slew rate”
limitations are absent.

This inherent advantage would be lost if the voltage follower
used to buffer the output were to have slew rate limitations. The
AD844 has been designed to avoid this problem, and as a result
the output buffer exhibits a clean large signal transient response,
free from anomalous effects arising from internal saturation.

Response as a Noninverting Amplifier

Since current feedback amplifiers are asymmetrical with regard
to their two inputs, performance will differ markedly in nonin­verting and inverting modes. In noninverting modes, the large
signal high speed behavior of the AD844 deteriorates at low
gains because the biasing circuitry for the input system (not
shown in Figure 4) is not designed to provide high input voltage
slew rates.

However, good results can be obtained with some care. The
noninverting input will not tolerate a large transient input; it
must be kept below ±1

V for best results. Consequently this mode

is better suited to high gain applications (greater than ×10).
TPC 20 shows a noninverting amplifier with a gain of 10 and a
bandwidth of 30 MHz. The transient response is shown in
TPCs 23 and 24. To increase the bandwidth at higher gains, a
capacitor can be added across R2 whose value is approximately
the ratio of R1 and R2 times C

.

t

Noninverting Gain of 100

The AD844 provides very clean pulse response at high nonin­verting gains. Figure 5 shows a typical configuration providing a
gain of 100 with high input resistance. The feedback resistor is
kept as low as practicable to maximize bandwidth, and a peak­ing capacitor (C

) can optionally be added to further extend

PK

the bandwidth. Figure 6 shows the small signal response with

= 3 nF, RL = 500 Ω, and supply voltages of either ±5 V or

C

PK

±15 V. Gain bandwidth products of up to 900 MHz can be achieved
in this way.

The offset voltage of the AD844 is laser trimmed to the 50 µV
level and exhibits very low drift. In practice, there is an addi­tional offset term due to the bias current at the inverting input
(I

) which flows in the feedback resistor (R1). This can option-

BN

ally be nulled by the trimming potentiometer shown in Figure 5.

+V

S

4.7

R1

499 

0.22F

0.22F

R

L

8

S

C

PK

4.99

V

OFFSET

TRIM

3nF

R2

IN

20

–

AD844

+

4.7

–V

Figure 5. Noninverting Amplifier Gain = 100, Optional
Offset Trim Is Shown

46

40

34

GAIN – dB

28

22

16

100k 1M

FREQUENCY – Hz

VS = 15V

V

S

= 5V

10M

20M

Figure 6. AC Response for Gain = 100, Configuration
Shown in Figure 5

USING THE AD844
Board Layout

As with all high frequency circuits considerable care must be
used in the layout of the components surrounding the AD844.
A ground plane, to which the power supply decoupling capaci­tors are connected by the shortest possible leads, is essential
to achieving clean pulse response. Even a continuous ground
plane will exhibit finite voltage drops between points on the
plane, and this must be kept in mind in selecting the grounding
points. Generally speaking, decoupling capacitors should be
taken to a point close to the load (or output connector) since
the load currents flow in these capacitors at high frequencies.
The +IN and –IN circuits (for example, a termination resistor
and Pin 3) must be taken to a common point on the ground
plane close to the amplifier package.

Use low impedance capacitors (AVX SR305C224KAA or
equivalent) of 0.22 µF wherever ac coupling is required. Include
either ferrite beads and/or a small series resistance (approxi­mately 4.7 Ω) in each supply line.

REV. D

–9–

AD844

Input Impedance

At low frequencies, negative feedback keeps the resistance at the
inverting input close to zero. As the frequency increases, the
impedance looking into this input will increase from near zero to
the open loop input resistance, due to bandwidth limitations,
making the input seem inductive. If it is desired to keep the
input impedance flatter, a series RC network can be inserted
across the input. The resistor is chosen so that the parallel sum
of it and R2 equals the desired termination resistance. The
capacitance is set so that the pole determined by this RC network
is about half the bandwidth of the op amp. This network is not
important if the input resistor is much larger than the termina­tion used, or if frequencies are relatively low. In some cases, the
small peaking that occurs without the network can be of use in
extending the –3 dB bandwidth.

Driving Large Capacitive Loads

Capacitive drive capability is 100 pF without an external net­work. With the addition of the network shown in Figure 7, the
capacitive drive can be extended to over 10,000 pF, limited by
internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current
limit. Since this is roughly ±100 mA, under these conditions,
the maximum slew rate into a 1000 pF load is ±100 V/µs.
Figure 8 shows the transient response of an inverting amplifier
(R1 = R2 = 1 kΩ) using the feed forward network shown in
Figure 7, driving a load of 1000 pF.

AD844

750

22pF

V

OUT

C

L

Figure 7. Feed Forward Network for Large Capacitive
Loads

Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ,

= 500 Ω. For the gain of –10, R5 = 50 Ω, R6 = 500 Ω

and R

L

and R

was not used since the summing network loads the

L

output with approximately 275 Ω. Using this network in a
unity-gain configuration, settling time is 100 ns to 0.1% for a
–5 V to +5 V step with C

R5

D1 D2

V

IN

R3

D1, D2 IN6263 OR EQUIV. SCHOTTKY DIODE

= 10 pF.

L

TO SCOPE
(TEK 7A11 FET PROBE)

R2

R6

AD844

R1

V

OUT

R

L

C

L

Figure 9. Settling Time Test Fixture

DC Error Calculation

Figure 10 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, I
feedback resistor. I
in the resistance at Pin 3 (R

, the noninverting input bias current, flows

BP

), and the resulting voltage (plus

P

, flows in the

BN

any offset voltage) will appear at the inverting input. The total
error, V

, at the output is:

O

VO= (IBPRP+VOS+ IBNRIN)1+






R1

R2



+ I

BN

R1




Since IBN and IBP are unrelated both in sign and magnitude,
inserting a resistor in series with the noninverting input will not
necessarily reduce dc error and may actually increase it.

Figure 8. Driving 1000 pF CL with Feed Forward Network
of Figure 7

Settling Time

Settling time is measured with the circuit of Figure 9. This
circuit employs a false summing node, clamped by the two

–10–

R1

V

R2

N

+

~

I

NN

I

NP

R

P

R

IN

I

BN

I

BP

AD844

V

OS

Figure 10. Offset Voltage and Noise Model for the AD844

REV. D

Noise

V

OUT

– IRE

DIFFERENTIAL PHASE – Degree

0.3

0.2

–0.3

018 90

36 54 72

0.1

0

–0.1

–0.2

IRE = 7.14mV

V

OUT

– IRE

DIFFERENTIAL PHASE – Degree

0.06

0.04

–0.06

0

18

90

36

54

72

0.02

0

–0.02

–0.04

IRE = 7.14mV

Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are I
induced noise at the output, V

VON= (( Inp RP)2+Vn2)1+

, INP, VN, and the amplifier

NN

, is:

ON

R1

R2

2



+( Inn R1)









2

Overall noise can be reduced by keeping all resistor values to a
minimum. With typical numbers, R1 = R2 = 1 kΩ, R

Vn = 2 nV/√Hz, Inp = 10 pA/√Hz, Inn = 12 pA/√Hz , V

= 0,

P

ON

calculates to 12 nV/√Hz. The current noise is dominant in
this case, as it will be in most low gain applications.

Video Cable Driver Using 5 Volt Supplies

The AD844 can be used to drive low impedance cables. Using
±5 V supplies, a 100 Ω load can be driven to ±2.5 V with low
distortion. Figure 11a shows an illustrative application which
provides a noninverting gain of 2, allowing the cable to be
reverse-terminated while delivering an overall gain of +1 to the
load. The –3 dB bandwidth of this circuit is typically 30 MHz.
Figure 11b shows a differential gain and phase test setup. In
video applications, differential-phase and differential-gain
characteristics are often important. Figure 11c shows the varia­tion in phase as the load voltage varies. Figure 11d shows the
gain variation.

Applications–

AD844

Figure 11c. Differential Phase for the Circuit of Figure 11a

+5V

2.2F

V

IN

50

3

7

6

2

4

2.2F

–5V

50

300

300

ZO = 50

R

50

V

OUT

L

Figure 11a. The AD844 as a Cable Driver

HP8753A
NETWORK
ANALYZER

EXT
TRIG

SYNC OUT

HP3314A

STAIRCASE

GENERATOR

R

OUT

INRF OUT

HP11850C
SPLITTER

OUT

(TERMINATOR)

50

OUT

OUT

V

IN

V

470

IN

CIRCUIT

UNDER

TEST

V

OUT

Figure 11b. Differential Gain/Phase Test Setup Figure

Figure 11d. Differential Gain for the Circuit of Figure 11a

High Speed DAC Buffer

The AD844 performs very well in applications requiring
current-to-voltage conversion. Figure 12 shows connections for
use with the AD568 current output DAC. In this application the
bipolar offset is used so that the full-scale current is ±5.12 mA,
which generates an output of ±5.12 V usingdecoupling and
grounding techniques to achieve the full 12-bit accuracy and
realize the fast settling capabilities of the system. The unmarked
capacitors in this figure are 0.1 µF ceramic (for the 1 kΩ appli-
cation resistor on the AD568. Figure 13 shows the full-scale
transient response. Care is needed in power supply example,
AVX Type SR305C104KAA), and the ferrite inductors should
be about 2.5 µH (for example, Fair-Rite Type 2743002122).
The AD568 data sheet should be consulted for more complete
details about its use.

REV. D

–11–

AD844

DIGITAL
INPUTS

MSB

+15V

–15V

I

BPD

I

OUT

ACOM

LCOM

SPAN

SPAN

THCOM

V

24

*

23

*

22

21

20

19

R

L

18

17

16

15

14

100pF

13

TH

AD844

*0.22F
POWER SUPPLY
BYPASS CAPACITORS

1

2

3

4

5

6

AD568

7

8

9

10

11

12

LSB

TOP VIEW

(Not to Scale)

REFCOM

Figure 12. High Speed DAC Amplifier

INPUTS

0 TO 3V

2V FS

GND

V

V

3nF

I/P

+15V

*

*

–15V

V

OUT

R

I

ANALOG
SUPPLY
GROUND

GROUND

10

0.22F

X

Y

DIGITAL
SUPPLY

–5V

1

(Not to Scale)

16

TOP VIEW

AD539

89

10

0.22F

AD844

0.22F

+V

TYP+6V

@15A

V

10

S

OUTPUT

V

W

–V

=

W

XVY

2V

Figure 13. DAC Amplifier Full-Scale Transient Response

20 MHz Variable Gain Amplifier

The AD844 is an excellent choice as an output amplifier for the
AD539 multiplier, in all of its connection modes. (See AD539
data sheet for full details.) Figure 14 shows a simple multiplier
providing the output:

VW= –

V

XVY

2 V

where VX is the “gain control” input, a positive voltage of from
0 V to 3.2 V (max) and V

is the “signal voltage,” nominally

Y

±2 V FS but capable of operation up to ±4.2 V. The peak out­put in this configuration is thus ±6.7 V. Using all four of the
internal application resistors provided on the AD539 in parallel
results in a feedback resistance of 1.5 kΩ, at which value the
bandwidth of the AD844 is about 22 MHz, and is essentially
independent of V

. The gain at VX = 3.16 V is +4 dB.

X

0.22F

*VX AND VY INPUTS MAY OPTIONALLY

BE TERMINATED – TYPICALLY BY USING
A 50 OR 75 RESISTOR TO GROUND.

10

–V

TYP+6V

@15A

S

Figure 14. 20 MHz VGA Using the AD539

Figure 15 shows the small signal response for a 50 dB gain
control range (V

= 10 mV to 3.16 V). At small values of VX,

X

capacitive feedthrough on the PC board becomes troublesome,
and very careful layout techniques are needed to minimize this
problem. A ground strip between the pins of the AD539 will be
helpful in this regard. Figure 16 shows the response to a 2 V
pulse on V

for VX = 1 V, 2 V, and 3 V. For these results, a load

Y

resistor of 500 Ω was used and the supplies were ±9 V. The
multiplier will operate from supplies between ±4.5 V and ± 16.5 V.

Disconnecting Pins 9 and 16 on the AD539 alters the denomi­nator in the above expression to 1 V, and the bandwidth will be
approximately 10 MHz, with a maximum gain of 10 dB. Using
only Pin 9 or Pin 16 results in a denominator of 0.5 V, a band­width of 5 MHz and a maximum gain of 16 dB.

–12–

REV. D

GAIN – dB

–16

–26

–36

–46

AD844

+4

VX = 3.15V

–6

V

= 1.0V

X

= 0.316V

V

X

V

= 0.10V

X

= 0.032V

V

X

–56

100k 1M 60M

FREQUENCY – Hz

10M

Figure 15. VGA AC Response Figure 16. VGA Transient Response with VX = 1 V, 2 V, and 3 V

REV. D

–13–

AD844

PIN 1

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Mini-DIP (N) Package

(N-8)

0.430 (10.92)

0.348 (8.84)

8

0.100 (2.54)

1

BSC

5

0.280 (7.11)

0.240 (6.10)

4

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

Cerdip (Q) Package

(Q-8)

0.195 (4.95)

0.115 (2.93)

PIN 1

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.4133 (10.50)

0.3977 (10.00)

16

1

0.005 (0.13)
MIN

0.405 (10.29) MAX

0.023 (0.58)

0.014 (0.36)

0.055 (1.4)
MAX

85

1

0.100 (2.54) BSC

4

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

16-Lead SOIC (R) Package

(R-16)

9

0.2992 (7.60)

0.2914 (7.40)

8

0.4193 (10.65)

0.3937 (10.00)

0.320 (8.13)

0.290 (7.37)

15

0

0.015 (0.38)

0.008 (0.20)

PIN 1

0.0118 (0.30)

0.0040 (0.10)

0.050 (1.27)
BSC

0.0192 (0.49)

0.0138 (0.35)

0.1043 (2.65)

0.0926 (2.35)

SEATING
PLANE

–14–

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

8
0

 45

0.0500 (1.27)

0.0157 (0.40)

REV. D

AD844

Revision History

Location Page

Data Sheet changed from REV. B to REV. C.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

REV. D

–15–

C00897–0–11/01(D)

–16–

PRINTED IN U.S.A.