Datasheet 2N7002LT1 Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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N–Channel Enhancement

1
GATE

MAXIMUM RATINGS

Rating Symbol Value Unit

Drain–Source Voltage V
Drain–Gate Voltage (RGS = 1.0 MΩ) V
Drain Current — Continuous TC = 25°C

Drain Current — Continuous TC = 100°C
Drain Current — Pulsed

Gate–Source Voltage

— Continuous
— Non–repetitive (tp ≤ 50 µs)

(2)

(1)

(1)

I

V

V

DSS

DGR

I

D

I

D

DM

GS

GSM

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation FR–5 Board,

Derate above 25°C
Thermal Resistance, Junction to Ambient R
Total Device Dissipation

Alumina Substrate,

Derate above 25°C
Thermal Resistance, Junction to Ambient R
Junction and Storage Temperature TJ, T

(4)

TA = 25°C

(3)

TA = 25°C

DEVICE MARKING

2N7002L T1 = 702

60 Vdc
60 Vdc

±115

±75

±800

±20
±40

3 DRAIN

2 SOURCE

mAdc

Vdc
Vpk

P

D

θJA

P

D

θJA

stg



Motorola Preferred Device

3

1

2

CASE 318–08, STYLE 21

SOT–23 (TO–236AB)

225

1.8
556 °C/W
300

2.4
417 °C/W

–55 to +150 °C

mW

mW/°C

mW

mW/°C

ELECTRICAL CHARACTERISTICS (T

Characteristic

= 25°C unless otherwise noted)

A

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

(VGS = 0, ID = 10 µAdc)

Zero Gate Voltage Drain Current TJ = 25°C

(VGS = 0, VDS = 60 Vdc) TJ = 125°C

Gate–Body Leakage Current, Forward

(VGS = 20 Vdc)

Gate–Body Leakage Current, Reverse

(VGS = –20 Vdc)

1. The Power Dissipation of the package may result in a lower continuous drain current.

2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.

3. FR–5 = 1.0 x 0.75 x 0.062 in.

4. Alumina = 0.4 x 0.3 x 0.025 in 99.5% alumina.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola Small–Signal Transistors, FETs and Diodes Device Data

 Motorola, Inc. 1997

V

(BR)DSS

I

DSS

I

GSSF

I

GSSR

60 — — Vdc

—
—

— — 100 nAdc

— — –100 nAdc

—
—

1.0

500

µAdc

1

2N7002LT1

(

DD

,

D

,

(T

ELECTRICAL CHARACTERISTICS

Characteristic

ON CHARACTERISTICS

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)

On–State Drain Current

(VDS ≥ 2.0 V

Static Drain–Source On–State Voltage

(VGS = 10 Vdc, ID = 500 mAdc)
(VGS = 5.0 Vdc, ID = 50 mAdc)

Static Drain–Source On–State Resistance

(VGS = 10 V, ID = 500 mAdc) TC = 25°C

(VGS = 5.0 Vdc, ID = 50 mAdc) TC = 25°C

Forward Transconductance

(VDS ≥ 2.0 V

DS(on)

DS(on)

(2)

, VGS = 10 Vdc)

, ID = 200 mAdc)

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)

Output Capacitance

(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)

Reverse Transfer Capacitance

(VDS = 25 Vdc, VGS = 0, f = 1.0 MHz)

SWITCHING CHARACTERISTICS

Turn–On Delay Time
Turn–Off Delay Time

(VDD = 25 Vdc, ID ^ 500 mAdc,
RG = 25 Ω, RL = 50 Ω)

BODY–DRAIN DIODE RATINGS

Diode Forward On–Voltage

(IS = 11.5 mAdc, VGS = 0 V)

Source Current Continuous

(Body Diode)

Source Current Pulsed I

2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.

= 25°C unless otherwise noted) (Continued)

A

TC = 125°C

TC = 125°C

(2)

Symbol Min Typ Max Unit

V

GS(th)

I

D(on)

V

DS(on)

r

DS(on)

g

C

C

C

t

d(on)

t

d(off)

V

I

SM

FS

iss

oss

rss

SD

S

1.0 — 2.5 Vdc

500 — — mA

—
—

—
—
—
—

80 — — mmhos

— — 50 pF

— — 25 pF

— — 5.0 pF

— — 30 ns
— — 40 ns

— — –1.5 Vdc

— — –115 mAdc

— — –800 mAdc

—
—

—
—
—
—

3.75

0.375

7.5

13.5

7.5

13.5

Vdc

Ohms

2

Motorola Small–Signal Transistors, FETs and Diodes Device Data

2N7002LT1

2.0

1.8

TA = 25°C

1.6

1.4

1.2

1.0

0.8

0.6

, DRAIN CURRENT (AMPS)

D

I

0.4

0.2
0

VDS, DRAN SOURCE VOLTAGE (VOLTS)

VGS = 10 V

9 V
8 V
7 V

6 V
5 V
4 V

3 V

100 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0

Figure 1. Ohmic Region

2.4

2.2
VGS = 10 V

2.0
ID = 200 mA

1.8

1.6

1.4

1.2

(NORMALIZED)

1.0

0.8

, STA TIC DRAIN–SOURCE ON–RESISTANCE

0.6

0.4

DS(on)

r

–60 –20 + 20 +60 +100 +140 –60 – 20 +20 +60 +100 +140

°

T, TEMPERA TURE (

C)

1.0
VDS = 10 V

0.8

0.6

0.4

, DRAIN CURRENT (AMPS)

D

I

0.2

1.2

1.05

1.1

1.10

1.0

0.95

0.9

0.85

0.8

, THRESHOLD VOLTAGE (NORMALIZED)

0.75

GS(th)

V

0.7

–55°C

125°C

VGS, GATE SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

VDS = V
ID = 1.0 mA

T, TEMPERA TURE (°C)

25°C

100 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0

GS

Figure 3. T emperature versus Static

Drain–Source On–Resistance

Figure 4. T emperature versus Gate

Threshold V oltage

Motorola Small–Signal Transistors, FETs and Diodes Device Data

3

2N7002LT1

INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection

0.037

0.95

0.035

0.9

SOT–23 POWER DISSIP ATION

The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by T
die, R
ambient, and the operating temperature, TA. Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:

The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.

The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.

, the maximum rated junction temperature of the

J(max)

, the thermal resistance from the device junction to

θJA

PD =

T

PD =

150°C – 25°C

556°C/W

J(max)

R

θJA

– T

A

= 225 milliwatts

0.031

0.8

SOT–23

interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.

0.037

0.95

0.079

2.0

inches

mm

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.

4

Motorola Small–Signal Transistors, FETs and Diodes Device Data

2N7002LT1

P ACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

A

L

3

1

S

B

2

GV

C

D

H

K

J

CASE 318–08

3. MAXIUMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.

INCHES

DIMAMIN MAX MIN MAX

0.1102 0.1197 2.80 3.04

B 0.0472 0.0551 1.20 1.40
C 0.0350 0.0440 0.89 1.11
D 0.0150 0.0200 0.37 0.50
G 0.0701 0.0807 1.78 2.04
H 0.0005 0.0040 0.013 0.100
J 0.0034 0.0070 0.085 0.177
K 0.0140 0.0285 0.35 0.69
L 0.0350 0.0401 0.89 1.02
S 0.0830 0.1039 2.10 2.64
V 0.0177 0.0236 0.45 0.60

STYLE 21:

PIN 1. GATE

2. SOURCE

3. DRAIN

MILLIMETERS

ISSUE AF

SOT–23 (TO–236AB)

Motorola Small–Signal Transistors, FETs and Diodes Device Data

5

2N7002LT1

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

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Motorola Small–Signal Transistors, FETs and Diodes Device Data

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2N7002LT1/D