: In this Manual, some parts can be changed for improving. their
performance without notice in the parts list. So, if you need the
latest parts information, please refer to PPL(Parts Price List)in
Service Information Center.
Service Manual
COLOR Television
CHASSIS :
Model :
CP-520V
DTX-21G2/21B4/21U7
P/N:TCP520VEF0
Dec. 2006
Page 2
CP-520V Service Manual
1
CONTENTS
DOCUMENT HISTORY3
1 MAIN FEATURES4
1.1 SPECIFICATIONS 4
1.1.1 GENERAL4
1.1.2 EURO-SCART 1 (21 Pin)4
1.1.3 EURO-SCART 2 (21 Pin)5
1.2 CHANNEL/FREQUENCY TABLE6
2 SAFETY INSTRUCTION9
3 ALIGNMENT INSTRUCTIONS10
3.1 MICROCONTROLLER CONFIGURATION : SERVICE MODE10
3.2 SERVICE MODE NAVIGATION10
3.3 MICROCONTROLLER CONFIGURATION : OPTION BITS10
3.4 OPTION 111
3.5 OPTION 211
3.6 NVM DEFAULT SETTING12
3.7 TV SET ALIGNMENT14
3.7.1 G2 ALIGNMENT14
3.7.2 WHITE BALANCE14
3.7.3 FOCUS14
3.7.4 VERTICAL GEOMETRY14
3.7.5 HORIZONTAL PICTURE CENTRING14
3.7.6 AGC14
4 IC DESCRIPTION15
4.1 UOC III SERIES15
4.1.1 IC MARKING AND VERSION15
4.1.2 BLOCK DIAGRAM16
4.1.3 PINNING17
4.1.4 FEATURES20
4.2 LA42032 STEREO AUDIO AMPLI FIER23
4.2.1 FEATURES24
4.3 LA78040 VERTICAL AMPLIFIER26
4.3.1 FEATURES26
4.4 24WC16 - 16 KB EEPROM28
4.5 STR - W675429
4.5.1 GENERAL DESCRIPTION29
4.5.2 FEATURES29
4.5.3 BLOCK DIAGRAM29
4.5.4 PIN DESCRIPTION30
4.5.5 CONTROL PART - ELECTRICAL CHARACTERISTICS30
Page 3
CP-520V Service Manual
2
5 CIRCUIT DESCRIPTION32
5.1 BLOCK DIAGRAM32
5.2 FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR33
5.2.1 Vision IF amplifier33
5.2.2 QSS sound circuit33
5.2.3 FM demodulator33
5.2.4 Audio input selector and volume contro34
5.2.4.1 STEREO AND AV STEREO VERSIONS34
5.2.4.2 MONO VERSIONS34
5.2.5 CVBS and Y/C input signal selection34
5.2.5.1 ALL VERSIONS34
5.2.6 Synchronisation circuit35
5.2.7 Horizontal and vertical drive36
5.2.8 Chroma, luminance and feature processing36
5.2.9 Colour decoder37
5.2.10 RGB output circuit38
5.2.11 I2C-BUS USER INTERFACE DESCRIPTION40
5.3 GENERAL DESCRIPTION OF THE TV SOUND OF SOUND PROCESSOR40
5.3.1 Supported standards41
5.4 FUNCTIONAL DESCRIPTION SOUND PROCESSOR42
5.4.1 The UOC III TV Sound Concept42
5.4.2 Functional Overview Of the digital controller sound part43
5.4.3 Demodulator and decoder44
6 SERVICE PARTS LIST47
6.1 DTX-21G2FZP-SB47
7 EXPLODED VIEW52
7.1 DTX-21G252
7.2 DTX-21B453
7.3 DTX-21U754
8 PRINTED CIRCUIT BOARD55
8.1 4859813693(OLD PCB)55
8.2 4859816393(NEW PCB)56
9 SCHEMATIC DIAGRAM57
9.1 CP-520V57
Page 4
CP-520V Service Manual
DOCUMENT HISTORY
VERSION DATE COMMENTS
V1.4607/07/06 Creation of document (Author JS KIM) for project CP520 50Hz TV.
3
Page 5
1 MAIN FEATURES
1.1 SPECIFICATIONS
1.1.1 GENERAL
TV standard PAL - SECAM B/G D/K, PAL I/I, SECAM L/L’
Sound system NICAM B/G, I, D/K, L,
Power
consumption
CP-520V Service Manual
Tuner PAL, SECAM Colour system
AV PAL, SECAM, PAL 60, NTSC M, NTSC 4.43
FM 2Carrier B/G, D/K
59W
Sound Output
Power
Speaker 12W 8 ohm x2
Teletext system 10 pages memory FASTEXT (FLOF or TOP)
Aerial input 75 ohm unbalanced
Channel coverage Off-air channels, S-cable channels and hyperband
Tuning system frequency synthesiser tuning system
Visual screen size 51cm
Channel indication On Screen Display
Program Selection 100 programmes
Aux. terminal EURO-SCART 1 : Audio / Video In and Out, R/G/B
Remote Control
Unit
4.5W x 2 (at 60% mod, 10% THD)
In, Slow and Fast switching.
EURO-SCART 2 : Audio / Video In and Out, SVHS
In.
AV3 : Audio-Video Jack on front of cabinet.
Headphone jack (3.5 mm) on front of cabinet
SVHS3 (option) : Jack on front of cabinet – sound
input common with AV3.
R-49C10
1.1.2 EURO-SCART 1 (21 Pin)
Pin Signal Description Matching value
1 Audio Output Right
2 Audio Input Right
3 Audio Output Left
4 Audio Earth
5 Blue Earth
6 Audio Input Left
7 Blue Input
0.5 Vrms, Impedance < 1 kΩ, ( RF 54% Mod )
0.5 Vrms, Impedance > 10 kΩ
0.5 Vrms, Impedance < 1 kΩ, ( RF 54% Mod )
0.5 Vrms, Impedance > 10 kΩ
0.7 Vpp ±0.1V, Impedance 75Ω
4
Page 6
CP-520V Service Manual
8 Slow Switching TV : 0 to 2V, AV 16/9 : 4.5 to 7V, AV 4/3 : 9.5 to 12V , Impedance
> 10 kΩ
9 Green Earth
10 N.C.
11 Green Input
12 N.C.
13 Red Earth
14 Blanking Earth
15 Red Input
16 Fast Switching
17 Video Out Earth
18 Video In Earth
19 Video Output
20 Video Input
21 Common Earth
1.1.3 EURO-SCART 2 (21 Pin)
Pin Signal Description Matching value
1 Audio Output Right
2 Audio Input Right
3 Audio Output Left
4 Audio Earth
5 Earth
6 Audio Input Left
7 N.C.
8 N.C.
9 N.C.
10 N.C.
11 N.C.
12 N.C.
13 Earth
14 Earth
15 Chroma Input
16 N.C.
17 Earth
18 Video In Earth
19 Video Output
20 Video Input, Y In.
21 Common Earth
0.7 Vpp ± 0.1V, Impedance 75Ω
0.7 Vpp ± 0.1V, Impedance 75Ω
0 to 0.4V : Logic “0”, 1 to 3V : Logic “1”, Impedance 75Ω
2 SAFETY INSTRUCTION
WARNING: Only competent service personnel may carry out work involving the testing or repair
of this equipment.
X-RAY RADIATION PRECAUTION
1. Excessive high voltage can produce potentially hazardous X-RAY RADIATION. To avoid
such hazards, the high voltage must not exceed the specified limit. The nominal value of the high
voltage of this receiver is 25KV at max beam current.
The high voltage must not, under any circumstances, exceed 29KV.
Each time a receiver requires servicing, the high voltage should be checked. It is important to
use an accurate and reliable high voltage meter.
2. The only source of X-RAY Radiation in this TV receiver is the picture tube. For continued
X-RAY RADIATION protection, the replacement tube must be exactly the same type tube as
specified in the parts list.
SAFETY PRECAUTION
Potentials of high voltage are present when this receiver is operating. Operation of the receiver
outside the cabinet or with the back board removed involves a shock hazard from the receiver.
Servicing should not be attempted by anyone who is not thoroughly familiar with the precautions
necessary when working on high voltage equipment.
Discharge the high potential of the picture tube before handling the tube. The picture tube is
highly evacuated and if broken, glass fragments will be violently expelled.
If any Fuse in this TV receiver is blown, replace it with the FUSE specified in the Replacement
Parts List.
When replacing a high wattage resistor (metal oxide film resistor) in the circuit board, keep the
resistor 10 mm away from circuit board.
Keep wires away from high voltage or high temperature components.
This receiver must operate under AC 230 volts, 50 Hz. NEVER connect to a DC supply or any
other voltage or frequency.
PRODUCT SAFETY NOTICE
Many electrical and mechanical parts in this equipment have special safety-related
characteristics. These characteristics are often passed unnoticed by a visual inspection and the
X-RAY RADIATION protection afforded by them cannot necessarily be obtained by using
replacement components rated for higher voltage, wattage, etc. Replacement parts which have
these special safety characteristics are identified in this manual and its supplements, electrical
components having such features are identified by designated symbol on the parts list. Before
replacing any of these components, read the parts list in this manual carefully. The use of
substitutes replacement parts which do not have the same safety characteristics as specified in
the parts list may create X-RAY Radiation.
9
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CP-520V Service Manual
10
3 ALIGNMENT INSTRUCTIONS
3.1 MICROCONTROLLER CONFIGURATION : SERVICE MODE
To switch the TV set into service mode please see instruction below.
1 - Select PR. number 91
2 - Adjust sharpness to minimum and exit all menus.
3 – Within 2 seconds press the key sequence : RED - GREEN - menu
The software version is displayed beside the word Service, e.g. “SERVICE VER 1.46”.
To exit SERVICE menu press menu key or Std By key.
3.2 SERVICE MODE NAVIGATION
Pr Up/Down remote keys : cycle through the service items available.
Vol -/+ remote keys : Dec./Increment the values within range – Cycle trough option bits.
OK key : Toggle bits in option byte
Order Item Default setting
1 HOR CEN
2 RED GAIN
3 GRN GAIN
4 BLUE GAIN
5 RED BIAS
6 GRN BIAS
7 AGC LEVEL
8 G2 – SCREEN
9 OPTION1
10 OPTION2
11 AVL
12 PARABOLA
13 HOR WIDTH
14 CORNER T
15 CORNER B
16 HOR. PARAL
17 V. LINEAR
18 V. SLOPE
19 EW TRAPEZ
20 S CORRECT
21 VERT CENT
22 VERT SIZE
3.3 MICROCONTROLLER CONFIGURATION : OPTION BITS
There are two option bytes available (16 bits in all). These option bits are available from Service
mode. First find the OPTION1 or OPTION2 control, and then use the Volume PLUS/MINUS
buttons on the remote control keypad to locate the bits, and OK key to toggle them. The table
below shows the two option bytes available;
Page 12
11
3.4OPTION 1
OPTION
B7B6B5B4B3B2B1B0
TOP
1
Teletext
OFF
TOP
0
Teletext
ON
3.5OPTION 2
B7B6B5B4B3B2B1B0
1
Fixed to
‘ 0’
0
FASTEXT
(FLOF)
OFF
FASTEXT
(FLOF) ON
JVC
remote
control
Daewoo
Remote
control
TUBE
4:3
TUBE
16:9
AVL
control
OFF
AVL
control
ON
VAI bit set
to 1 in
SECAM L
VAI bit set
to 0 in
SECAM L
PICTURE
TILT ON
PICTURE
TILT OFF
Dolby
Virtual
OFF
Dolby
Virtual
ON
5 keys
local
keyboard
7 keys
lacal
keyboard
SVHS3
disable
SVHS3
enable
Full
ATSS
Basic
ATSS
CP-520V Service Manual
TUNER OPTIONS
00 = Philips
01 = Not used
10 = Alps, LG
11 = Parstnic, SS
Double
Window
Enabled
Double
Window
Disabled
n.u.
Must
be set
to 1 for
future
compa
tibility
CHASSISMODEL
CP-520V
OPTION
BIT[b7…b0]
I001111103EDTX-21G2/B4/U7
II000011110F
DW[hex]REMARKS
OPTION1 “ b1,b0” depends on Tuner
Page 13
CP-520V Service Manual
12
3.6 NVM default setting
The purpose of this message, when you change a virgin EEPROM, is to allow to modify
the NVM DATA to desired values.
1 - Introduction :
The NVM default valus are fixed for the user, but for flexibility in service, these data are stored in
NVM and can be changed when the TV set is in a special mode call "NVM EDITOR". This mode
can only be access from "FACTORY" mode.
2 - Entering into "FACTORY" mode.
To switch the TV set into FACTORY mode, use the factory remote control, and press on “SVC”
key. The factory menu will appear on the screen, showing “FACTORY” , plus other relevant
information like software version and date.
WARNING : When in "FACTORY" mode you should not press any key other than the keys
described in the procedure below. Unwanted key stroke could misadjust the TV set.
3 - Entering into "NVM EDITOR" mode.
To switch the TV set into NVM EDITOR mode, use the user remote control, and press on
“PICTURE/OK” key. The NVM EDITOR window will appear on the screen. This mode allow you
to access all data stored in NVM. The current NVM address is given in column "ADDR." in both
DECimal and HEXadecimal format. The column DATA gives the value contained at selected
address in both DECimal and HEXadecimal format.
4 - Navigation in "NVM EDITOR" mode.
Use Program Up/Dwn keys to select the desired address. Use Volume Up/Dwn keys to change
the data at selected address. You must press "PICTURE/OK" key to store value after
modification.
The data can be adjusted between 0 and 63.
5 - Exit "NVM EDITOR" mode.
To switch the TV set back into FACTORY mode, use the user remote control, and press on
“MENU” key.
The factory menu will appear on the screen, showing “FACTORY”.
6 - Exit "FACTORY" mode.
To exit "FACTORY" mode, use the factory remote control, and press on “SVC” key.
The factory menu will disappear from the screen.
Page 14
CP-520V Service Manual
13
NVM DATA CHANGE LIST
No Register NameAddressDefault
1OCP_THRESHOLD0x58F0x91
2DCXO0x5900x4E
3AGC_PHILIPS0x5C10xAB
4AGC_NC0x5C20xAB
5AGC_ALPS, LG0x5C30xB6
6AGC_PARTSNIC0x5C40xB6
7AGC_PHILIPS_START0x5C50x16O x OF
8AGC_NC_START0x5C60x16
9AGC_ALPS, LG_START0x5C70x16
10AGC_PARTSNIC_START0x5C80x16
11AVLLEV0x6210x5
12Nor1_Bright0x64A0x23
13Nor1_contrast0x64B0x2E
14Nor1_Colour0x64C0x1C
15Nor1_Sharpness0x64D0x23
16Nor1_Tint0x64E0x20
17Nor1_JVC_Bri0x64F0x2D
18Nor1_JVC_Cont0x6500x2A
19Nor1_JVC_Colour0x6510x1B
20Nor1_JVC_Sharp0x6520x23
21Nor2_Bright0x6530x28
22Nor2_Contrast0x6540x13
23Nor2_Colour0x6550x19
24Nor2_Sharpness0x6560x1B
25Nor2_Tint0x6570x20
26PresetGainRGB0x6730x2A
27PresetGainRGB0x6740x2A
28PresetGainRGB0x6750x2A
29Cathode_Drive0x67B0x1
30Y_delay_PAL_BG0x6860x5
31Y_delay_SECAM_BG0x6870x8
32Y_delay_PAL_DK0x6880x5
33Y_delay_SCM_DK0x6890x5
34Y_delay_PAL_I0x68A0x7
35Y_delay_SECAM0x68B0x5
36Y_delay_SECAM-L0x68C0x8
37Y_delay_AV0x68D0xA
38G2_Bright0x68E0x1A
39G2_Contrast0x68F0x42
(hex)CP-520V
21G2/B4/U7
<
<
<
<
<
<
O x OF
O x OF
O x OF
<
<
<
<
<
<
<
<
<
<
<
<
<
<
O x 10
O x 10
O x 10
<
O x 02
O x 0B
O x 0
O x 08
O x 0B
O x 07
O x 07
O x 05
0x28
-
-
-
-
-
-
-<
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<
Page 15
CP-520V Service Manual
14
3.7 TV SET ALIGNMENT
3.7.1 G2 ALIGNMENT
- Tune a colour bar pattern.
- Find the “G2 – SCREEN” item in service mode.
- Adjust screen volume (on FBT) to bring the cursor to central position(Green).
3.7.2 WHITE BALANCE
- Select a dark picture and adjust RED BIAS and GRN BIAS to the desired colour temperature.
- Select a bright picture and adjust RED, GRN and BLUE GAIN to the desired colour temperature.
3.7.3 FOCUS
Adjust the Focus volume (on FBT) to have the best resolution on screen.
3.7.4 VERTICAL GEOMETRY
Adjust V. LINEAR (linearity), S CORRECT (S. Correction), VERT SIZE (Vertical amplitude),
VERT CENT (vertical centring) to compensate for vertical distortion.
3.7.5 HORIZONTAL PICTURE CENTRING
Adjust HOR CEN (Horizontal centre) to have the picture in the centre of the screen.
3.7.6 AGC
- Make sure option bits are correct for the tuner fitted on the chassis (See above how to change
option bits).
- Adjust the antenna signal level at 62 dBµV
- Tune a colour bar pattern.
- Find the “AGC” item in service mode.
- Press the key “OK” on the remote keypad and wait until AGC level stabilise to the optimum
value.
- Alternatively, use “Vol Up/Dwn” keys to adjust manually to the desired Tuner Take Over Point
(TOP).
Page 16
15
4 IC DESCRIPTION
CP-520V Service Manual
4.1 UOC
III
Series
The UOC
III
series combines the functions of a Video Signal Processor (VSP) together with a
FLASH embedded TEXT/Control/Graphics µ-Controller (TCG µ-Controller) and US Closed
Caption decoder. In addition the following functions can be added:
• Adaptive digital (4H/2H) PAL/NTSC combfilter
• Teletext decoder with 10 page text memory
• Multi-standard stereo decoder
• BTSC stereo decoder
• Digital sound processing circuit
• Digital video processing circuit
4.1.1 IC MARKING AND VERSION
Chassis IC marking OSD languages ATSS countries Text
1 P1.5/TX Port 1.5 or UART bus
2 P1.4/RX port 1.4 or UART bus
3 P1.2/INT2 port 1.2 or external interrupt 2
4 VSSC3 Ground
5 VDDC3 digital supply to core (1.8V)
6 P2.5/PWM4 port 2.5 or PWM4 output
7 P2.4/PWM3 port 2.4 or PWM3 output
8 VSSC/P digital ground for m-Controller core and periphery
9 P3.3/ADC3 port 3.3 or ADC3 input
10 P3.2/ADC2 port 3.2 or ADC2 input
11 DECV1V8 decoupling 1.8 V supply
12 VDDC1 digital supply to core (+1.8 V)
13 P3.1/ADC1 port 3.1 or ADC1 input
14 P3.0/ADC0 port 3.0 or ADC0 input
15 P2.3/PWM2 port 2.3 or PWM2 output
16 P2.2/PWM1 port 2.2 or PWM1 output
17 P2.1/PWM0 port 2.1 or PWM0 output
18 P2.0/TPWM port 2.0 or Tuning PWM output
19 VDDP(3.3V)
20 P1.7/SDA port 1.7 or I2C-bus data line
21 P1.6/SCL port 1.6 or I2C-bus clock line
22 P1.3/T1 port 1.3 or Counter/Timer 1 input
23 P0.0/I2SDI1/O port 0.0 or I2S digital input 1 or I2S digital output
24 P0.1/I2SDO1 port 0.1 or I2S digital output 1
25 P0.2/I2SDO2 port 0.2 or I2S digital output 2
26 P0.3/I2SCLK port 0.3 or I2S clock
27 P0.4/I2SWS port 0.4 or I2S word select
28 VSSC2 Ground
29 VDDC2 digital supply to core (1.8 V)
30 P1.1/T0 port 1.1 or Counter/Timer 0 input
31 P1.0/INT1 port 1.0 or external interrupt 1
32 INT0/P0.5
33 VDDadc(1.8) supply voltage video ADC
34 VSSadc ground for on-chip temperature sensor
35 VDDA2(3.3) supply voltage SDAC (3.3 V)
36 VDDA(1.8) analogue supply for audio ADCs (1.8 V)
37 GNDA Ground
38 VREFAD reference voltage for audio ADCs (3.3/2 V)
39 VREFAD_POS positive reference voltage (3.3 V)
40 VREFAD_NEG negative reference voltage (0 V)
41 VDDA1
42 BO Blue output
supply to periphery and on-chip voltage regulator (3.3
V)
external interrupt 0 or port 0.5 (4 mA current sinking
capability for direct drive of LEDs)
analog supply for TCG m-Controller and digital supply
for
TV-processor (+3.3 V)
Page 19
CP-520V Service Manual
18
43 GO Green output
44 RO Red output
45 BLKIN black current input
46 BCLIN beam current limiter input
47 VP3 3rd supply for TV processor
48 GND3 ground 3 for TV-processor
49 B/PBIN3 3rd B input / PB input
50 G/YIN3 3rd G input / Y input
51 R/PRIN3 3rd R input / PR input
52 INSSW3 3rd RGB / YPBPR insertion input
Automatic Volume Levelling / switch output / sound IF
input /
subcarrier reference output / external reference signal
input for I
signal mixer for DVB operation
V-guard input / I/O switch (e.g. 4 mA current sinking
capability for
direct drive of LEDs)
CP-520V Service Manual
Page 21
CP-520V Service Manual
20
4.1.4 FEATURES
Analogue Video Processing (all versions)
· Multi-standard vision IF circuit with alignment-free PLL demodulator
· Internal (switchable) time-constant for the IF-AGC circuit
· Switchable group delay correction and sound trap (with switchable centre frequency) for the
demodulated CVBS signal
· DVB/VSB IF circuit for preprocessing of digital TV signals.
· Video switch with 3 external CVBS inputs and a CVBS output. All CVBS inputs can be used as
Y-input for Y/C signals. However, only 2 Y/C sources can be selected because the circuit has 2
chroma inputs. It is possible to add an additional CVBS(Y)/C input (CVBS/YX and CX) when the
YUV interface and the RGB/YPRPB input are not needed.
· Automatic Y/C signal detector
· Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the
chrominance signal.
· Integrated luminance delay line with adjustable delay time
· Picture improvement features with peaking (with switchable centre frequency, depeaking,
variable positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring),
dynamic skin tone control, gamma control and blue- and black stretching. All features are
available for CVBS, Y/C and RGB/YPBPR signals.
· Switchable DC transfer ratio for the luminance signal
· Only one reference (24.576 MHz) crystal required for the TCG m-Controller, digital sound
processor, Teletext and the colour decoder
· Multi-standard colour decoder with automatic search system and various “forced mode”
possibilities
· Internal base-band delay line
· Indication of the Signal-to-Noise ratio of the incoming CVBS signal
· Linear RGB/YPBPR input with fast insertion.
· YUV interface. When this feature is not required some pins can be used as additional
RGB/YPBPR input. It is also possible to use these pins for additional CVBS (or Y/C) input
(CVBS/YX and CX).
· Tint control for external RGB/YPBPR signals
· Scan Velocity Modulation output. The SVM circuit is active for all the incoming CVBS, Y/C and
RGB/YPBPR signals. The SVM function can also be used during the display of teletext pages.
· RGB control circuit with ‘Continuous Cathode Calibration’, white point and black level off-set
adjustment so that the colour temperature of the dark and the light parts of the screen can be
chosen independently.
· Contrast reduction possibility during mixed-mode of OSD and Text signals
· Adjustable ‘wide blanking’ of the RGB outputs
· Horizontal synchronization with two control loops and alignment-free horizontal oscillator
· Vertical count-down circuit
· Vertical driver optimized for DC-coupled vertical output stages
· Horizontal and vertical geometry processing with horizontal parallelogram and bow correction
and horizontal and vertical zoom
· Low-power start-up of the horizontal drive circuit
Analogue video processing (stereo versions)
· The low-pass filtered ‘mixed down’ I signal is available via a single ended or balanced output
stage.
Analogue video processing (mono versions)
· The low-pass filtered ‘mixed down’ I signal is available via a single ended output stage
Digital Video Processing (some versions)
· Double Window mode applications. It is possible to display a video and a text window or 2 text
Page 22
CP-520V Service Manual
21
windows in parallel.
· Linear and non-linear horizontal scaling of the video signal to be displayed.
Sound Demodulation (all versions)
· Separate SIF (Sound IF) input for single reference QSS (Quasi Split Sound) demodulation.
· AM demodulator without extra reference circuit
· The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched
to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such
that the external band-pass filters can be omitted. In the stereo versions of UOCIII the use of this
demodulator is optional for special applications. Normally the FM demodulators of the stereo
demodulator/decoder part are used (see below).
· The FM-PLL demodulator can be set to centre frequencies of 4.72/5.74 MHz so that a second
sound channel can be demodulated. In such an application it is necessary that an external
bandpass filter is inserted.
· The vision IF and mono intercarrier sound circuit can be used for the demodulation of FM radio
signals. With an external FM tuner also signals with an IF frequency of 10.7 MHz can be
demodulated.
· Switch to select between 2nd SIF from QSS demodulation or external FM (SSIF)
Audio Interfaces and switching (stereo versions with Audio DSP)
· Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH, 1 stereo output for
HEADPHONE. The headphone channel has an analogue volume control circuit for the L and R
channel. Finally 1 stereo SPEAKER output with digital controls.
· AVL (Automatic Volume Levelling) circuit for the headphone channel.
· Digital input crossbar switch for all digital signal sources and destinations
· Digital output crossbar for exchange of channel processing functionality
· Digital audio input interface (stereo I2S input interface)
· Digital audio output interface (stereo I2S output interface)
Audio interfaces and switching (AV stereo versions without Audio DSP)
· Audio switch circuit with 4 stereo inputs, a stereo output for SCART/CINCH and a stereo
SPEAKER output with analogue volume control.
· Analogue mono AVL circuit at left audio channel
Audio interfaces and switching (mono versions)
· Audio switch circuit with 4 external audio (mono) inputs and a volume controlled output
· AVL circuit
Stereo Demodulator and Decoder (full stereo versions)
· Demodulator and Decoder Easy Programming (DDEP)
· Auto standard detection (ASD)
· Static Standard Selection (SSS)
· DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation
· NICAM decoding (B/G, I, D/K and L standard)
· Two-carrier multistandard FM demodulation (B/G, D/K and M standard)
· Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound
· Adaptive de-emphasis for satellite FM
· Optional AM demodulation for system L, simultaneously with NICAM
· Identification A2 systems (B/G, D/K and M standard) with different identification time constants
· FM pilot carrier present detector
· Monitor selection for FM/AM DC values and signals, with peak and quasi peak detection option
· BTSC MPX decoder
· SAP decoder
· dbx® noise reduction (4)
· Japan (EIAJ) decoder
· FM radio decoder
· Soft-mute for DEMDEC outputs DEC, MONO and SAP
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22
· FM overmodulation adaptation option to avoid clipping and distortion
Audio Multi Channel Decoder (stereo versions with Audio DSP)
· Dolby® Pro Logic® (DPL) (1)
· Five channel processing for Main Left and Right, Subwoofer, Centre and Surround. To exploit
this feature an external DAC is required.
Volume and tone control for loudspeakers (stereo versions with Audio DSP)
· Automatic Volume Level (AVL) control
· Smooth volume control
· Master volume control
· Soft-mute
· Loudness
· Bass, Treble
· Dynamic Bass Boost (DBB) (2)
· Dynamic Virtual Bass (DVB) (3)
· BBE® Sound processing (4)
· Graphic equalizer
· Processed or non processed subwoofer
· Programmable beeper
Reflection and delay for loudspeaker channels (stereo versions with Audio DSP)
· Dolby® Pro Logic® Delay (1)
· Pseudo hall/matrix function
Psycho acoustic spatial algorithms, downmix and split in loudspeaker channels (stereo
versions with Audio DSP)
· Extended Pseudo Stereo (EPS) (5)
· Extended Spatial Stereo (ESS) (6)
· Virtual Dolby® Surround (VDS 422,423) (1)
· SRS 3D and SRS TruSurround® (4)
RDS/RBDS
· Demodulation of the European Radio Data system (RDS) or the USA Radio Broadcast Data
System (RBDS) signal
· RDS and RBDS block detection
· Error detection and correction
· Fast block synchronisation
· Synchronisation control (flywheel)
· Mode control for RDS/RBDS processing
· Different RDS/RBDS block information output modes
m-Controller
· 80C51 m-controller core standard instruction set and timing
· 0.4883 ms machine cycle
· maximum of 256k x 8-bit flash programmable ROM
· maximum of 8k x 8-bit Auxiliary RAM
· 12-level Interrupt controller for individual enable/disable with two level priority
· Two 16-bit Timer/Counter registers
· One 24-bit Timer (16-bit timer with 8-bit Pre-scaler)
· WatchDog timer
· Auxiliary RAM page pointer
· 16-bit Data pointer
· Stand-by, Idle and Power Down modes
· 24 general I/O
· 14 bits PWM for Voltage Synthesis Tuning
· 8-bit A/D converter with 4 multiplexed inputs
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23
· 5 PWM (6-bits) outputs for analogue control functions
· 4 WST Character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic)
· G1 Mosaic graphics, Limited G3 Line drawing characters
· WST Character sets and Closed Caption Character set in single device
· SVM for Text
4.2 LA42032 STEREO AUDIO AMPLIFIER
The LA42032 is a dual-channel audio power amplifier with an output power of 2 x 5 W at an 8
Ω load and a 9 V supply.
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24
4.2.1 FEATURES
LA42032
CP-520V Service Manual
5W x 2 Channel(Vcc=9V, R
Standby function
•
Mute function
•
Thermal protection circuit
•
L=8Ω)•
Pin description
PinSymbolDescription
1R.F.
2 Right input
3 Ground
4Left Input
5Standby
6Mute
7 Supply Voltage
8Positive Left output
9 Negative Left Output
10 Ground
11 Negative Right Output
12
13
Rin
GND
Lin
STB
Mute
Vcc
Lo(+)
Lo(-)
GND
Ro(-)
Ro(+)
N.C.
Ripple Filter
Positive Right Output
Not Connected
R.F.
Rin
GND
Lin
STB
Mute
Vcc
Lo(+)
Lo(-)
GND
Ro(-)
Ro(+)
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
MBK932
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25
Block diagram LA42032
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CP-520V Service Manual
4.3 LA78040 VERTICAL AMPLIFIER
The LA78040 are power circuit for use in 90° and 110° colour deflection systems for field
frequencies of 25 to 200Hz field frequencies, and for 4:3 and 16/9 picture tubes. The IC contains
a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge
output circuit allows DC coupling of the deflection coil in combination with single positive supply
voltages.
4.3.1 FEATURES
§ Built-in pump-up circuti for low power dissipation
§ Vertical output circuit
§ Thermal protection circuit
1
Vin(-)
2
Vcc
-14V
Vout
Vcc
Vin(+)
3
4
5
6
7
LA78040
MGL867
Pump Up Out
26
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27
Pinning
Pin Symbol Description
1 Vin(-) Inverting Input
2 VccSupply voltage
3 Pump Up Out Pump Up Out
4 -14V -14V
5 Vout Ver. Output
6 Vcc Output Stage Vcc
7 Vin(+) Non Inv. Input
CP-520V Service Manual
Block diagram LA78040
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28
4.4 24WC16 - 16 KB EEPROM
Features :
§ 16 Kbit serial I2C bus EEPROM
§ 400KHz I2C Bus Compatible
§ supply voltage : 1.8 V to 6.0 V
§ Low Power CMOS Technology
§ 1 Million Erase/Write cycles (minimum)
§ 100 year data retention (minimum)
Pin description
Pin No.Name Description
1, 2, 3 A0, A1, A2 Device address – not used
5 SDA Serial Data/Address Input/Output
6 SCL Serial clock
7 WP Write control
8 Vcc Supply voltage
4 Vss Ground
The memory device is compatible with the I2C memory standard. This is a two wire serial
interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4-bit
unique device type identifier code (1010) in accordance with the I2C bus definition.
Serial Clock (SCL)
The SCL input is used to strobe all data in and out of the memory.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to transfer data in or out of the memory.
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The STR-W6754 is a quasi-resonant regulator specifically designed
to satisfy the requirements for increased integration and reliability in
switch-mode power supplies. It incorporates a primary control and drive
circuit with an avalanche-rated power MOSFET.
• Auto-Bias Function Stable Burst Operation Without Generating Interference
• Internal Off-Timer Circuit
• Built-In Constant-Voltage Drive
• Multiple Protections: Pulse-by-Pulse Overcurrent Protection
Overload Protection with Auto Recovery
Latching Overvoltage Protection
Undervoltage Lockout with Hysteresis
• RoHS Compliant
4.5 STR - W6754
4.5.1 GENERAL DESCRIPTION
CP-520V Service Manual
4.5.2 FEATURES
4.5.3 BLOCK DIAGRAM
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30
4.5.4 PIN DESCRIPTION
PINNAMESYMBOLDESCRIPTION
1DrainDMOSFET drain
3Source/GroundS/GNDGround
4SupplyVccPower Supply
5Overload ProtectionSS/OLP Overload Protection and Soft Start Operation Time set up
6FeedbackFB
7Overcurrent ProtectionOCP/BD
Constant Voltage Control Signal Input,
Burst mode Oscillation Control
Overcurrent Protection Signal Input/
Bottom Detection Signal Input
4.5.5 CONTROL PART - ELECTRICAL CHARACTERISTICS
Limits
CharacteristicSymbolTest ConditionsMin.Typ.Max. Units
Start-Up Operation
Operation Start VoltageV
Soft-Start Operation Stop VoltageV
Soft-Start Oper. Charging CurrentI
Operation Stop VoltageV
Circuit Current in Non-OperationI
Normal Operation
Drain-Source Breakdown VoltageV
Drain Leakage CurrentI
On-State Resistancer
ItnerruC tiucriC
Oscillation Frequencyf
Bottom-Skip Oper. Threshold Volt.V
Quasi-Resonant Oper. ThresholdV
OCPBD(BS1)
V
OCPBD(BS2)
OCPBD(TH1)
V
OCPBD(TH2)
Feedback-Pin Threshold VoltageV
Feedback-Pin CurrentI
Standby Operation
CC(ON)
SS/OLP
SS/OLP
CC(OFF)
CC(OFF)
(BR)DSS
DSS
DS(on)
temiT gnihctiwS
f
CC(ON)
osc
FB(OFF)
FB(ON)
Turn-on, VCC = 019.9 V16.318.219.9V
1.11.21.4V
-390-550-710µA
Turn-off, VCC = 19.98.8 V8.89.710.6V
V
CC
I
D
V
DS
ID = 1.9 A, TJ = +25°C––0.96Ω
––400ns
––6.0mA
192225kHz
-605-665-720mV
-385-435-485mV
280400520mV
670800930mV
1.321.451.58V
60010001400µA
Aµ001––V 51 =
V––056Aµ 003 =
Aµ003––V 056 =
Standby Operation Start VoltageV
Standby Oper. Start Volt. IntervalV
Standby Non-Operation CurrentI
Feedback-Pin CurrentI
FB(ON)
Feedback-Pin Threshold VoltageV
Minimum ON Timet
on(min)
CC(S)
CC
CC(S)
FB(S)
VCC = 012.2 V10.311.112.1V
1.101.351.65V
V
CC
V
CC
VCC = 12.2 V0.551.101.50V
0.50.81.2µs
Aµ6502–V 2.01 =
Aµ410.4–V 2.01 =
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31
Limits
CharacteristicSymbolTest ConditionsMin.Typ.Max. Units
Protection Operation
OVP Operation VoltageV
Maximum ON Timet
OLP Operation VoltageV
OLP Operation CurrentI
Overcurrent Detect. Threshold Volt.V
OCPBD(LIM)
OCP/BD-Pin CurrentI
Latch Holding CurrentI
Latch Release VoltageV
Other
Thermal ResistanceR
CC(OVP)
on(max)
SSOLP
SSOLP
OCPBD
CC(H)
CC(L)
θJF
Turn-off, VCC = 029.9 V25.527.729.9V
27.532.539.0µs
4.04.95.8V
-6.0-11-16µA
-0.895 -0.940 -0.995V
-40-100-250µA
VCC = 29.9V
– 0.3 V–45140mA
CC(OF F)
VCC = 29.96 V6.07.28.5V
Output junction-to-frame––1.6°C/W
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5 CIRCUIT DESCRIPTION
5.1 BLOCK DIAGRAM
CP-520V Service Manual
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33
5.2 FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR
5.2.1 Vision IF amplifier
The vision IF amplifier can demodulate signals with positive and megative modulation. The PLL
demodulator is completely alignment-free.
The VCO of the PLL circuit is internal and the grequency is fixed to the required value by using
the clock ftequency of the TCG u-Controller as a reference. The setting of the various
frequencies (e.g. 38, 38.9, 45.75 and 58.75MHz) can be made via the control bits IFA-IFC in
subaddress 2FH. Because of the internal VCO the IF circuit has a high immunity to EMC
interferences.
The output of the AFC detector can be read from output byte o4H and has a resolution of
7bit(25kHz per step). By means of this information a fast tuning algorithm can be designed.
The IC contains a group delay correction circuit which can be switched between the BG and a
uncompensated group delay response characteristic. This hasthe advantage that in multistandard receivers no compromise has to be made for the choice of the SAW filter. This group
delay corection is realised for the demodulated CVBS output signal. The IC contains in addition a
sound trap circuit with a switchable centre frequency.
5.2.2 QSS sound circuit
The sound IF amplifier is similar to the vision IF amplifier and has an external AGC decoupling
capacitor.
ThesinglereferenceQSSmixerisrealisedbyamultiplier. In this multiplier the SIF signal is converted
to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The
mixer output signal is suppliedtotheoutputviaahigh-passfilterforattenuation of the residual video
signals. With this system a high performance hi-fi stereo sound processing can be achieved.
TheAMsounddemodulatorisrealisedbyamultiplier.The modulated sound IF signal is multiplied in
phase with the limited SIF signal. The demodulator output signal is supplied to the output via a
low-pass filter for attenuation of the carrier harmonics.
SwitchingbetweentheQSSoutputandAMoutputismade by means of the AM bit in subaddress 33H.
5.2.3 FM demodulator
TheFMdemodulatorisrealisedasnarrow-bandPLL with internal loop filter, which provides the
necessary selectivity without using an external band-pass filter. To obtain a good selectivity a
linear phase detector and a constant input signal amplitude are required. For this reason the
intercarrier signal is internally supplied to the demodulator via a gain controlled amplifier and
AGC circuit. To improve the selectivity an internal bandpass filter is connected in front of the PLL
circuit.
The nominal frequency of the demodulator is tuned to the required frequency (4.5/5.5/6.0/6.5
MHz) by means of a calibration circuit which uses the clock frequency of the TCG(1)-Controller
as a reference. It is also possible to frequencies of 4.72 and 5.74Mhz so that a second sound
channel can be demodulated. In the latter application an external bandpass filter has to be
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34
applied to obtain sufficient selectivity (the sound input can be activated by means of the setting of
CMB2-CMB0 bits in subaddress 4AH). The setting to the wanted frequency is realised by means
of the control bits FMA, FMB and FMC in the control bit 33H.
From the output status bytes it can be read whether the PL Lfrequency is inside or outside the
window and whether thePLL is in lock or not. With this information it is possible to make an
automatic search system for the incoming sound frequency. This can be realised by means of a
software loop which switches the demodulator to the various frequencies and then select the
frequency on which a lock condition has been found.
The amplitude deemphasis output signal changed with 6dB by means of the AGN bit. In this way
output signal differences between the 4.5 MHz standard (frequency deviation25 kHz) and the
other standards (frequency deviation50 kHz) can be compensated.
5.2.4 Audio input selector and volume control
5.2.4.1 STEREO AND AV STEREO VERSIONS
The audio input selector circuit has 4 external stereo inputs, a stereo output for SCART/CINCH
and stereo outputs for headphone and audio power amplifiers. The selection is made with the
bits SAS2/0, SO2/0 and HPO2/0. AV stereo versions without Audio DSP have no headphone
output. The input signal selection for the volumecontrolledaudiooutputsisrealisedbytheHPO2/0
bits.
The gain from an external audio input to each of the (non-controlled) analog output is 0 or
+6dB(controlled by the DSG bit). A supply voltage of 5V allows input and output amplitude of
1VRMS full scale, as required to comply with the SCART specification, the audio supply voltage
must be 8V. In that case the gain of the audio amplifier must be doubled. This can be realised
with the DSG bit in subaddress 32H.
The circuit contains an analogue stereo volume control circuit with a control range of about 70dB.
This volume control circuit is used for the headphone channel (stereo versions with Audio DSP)
or for the main channel (AV stereo versions without Audio DSP). The analogue control circuit
also contains an Automatic Volume Levelling(AVL) function. When this function is activated it
stabilises the audio output signal to a certainl evel so that big fluctuations of the output power are
prevented.
5.2.4.2 MONO VERSIONS
The audio input selector circuit has 4 inputs for mono signals. The selection is made with the
HPO2/0 bits.
The circuit contains an analogue volume control circuit with a control range of about 70dB and an
AVL circuit.
5.2.5 CVBS and Y/C input signal selection
5.2.5.1 ALL VERSIONS
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The Ics have 3 inputs for external CVBS signals. All CVBS inputs can be used as Y input for the
insertion of Y/C signals.However, the CVBS(Y)2 input has to be combined with the C3 input. It is
possible to add and extra CVBS(Y/C) input via the pins which are intended to be used for YUV
interface (or RGB/YPrPb input). The selection of this additional CVBS(Y/C) input is made via the
YC bit.
The function of the IFVO/SVO/CVBSI pin is determined by the SVO1/SVO0 bits. When used as
output a selection can be made between the IF video output signal or the selected CVBS signal
(monitor out). This pin can also be used as additional CVBS input. This signal is inserted in front
of the group delay / sound trap circuit. It is also possible to use the group delay and sound trap
circuit for the CVBS2 signal (via the CV2 bit).
For the CVBS(Y/C) inputs the circuit can detect whether a CVBS or Y/C signal is present on the
input. The result can be read from the status register (YCD bit in subaddress 03H) and this
information can be used to put the input switch in the right position (by means of the INA-IND bits
in subaddress 38H). The Y/C detector is only active for the CVBS(Y)3/C3, CVBS(Y)4/C4 and
CVBS(Y)x/Cx inputs. It is not active for the CVBS(Y)2/C3 input.
The video ident circuit can be connected to all video input signals. This ident circuit is
independent of the synchronisation and can be used to switch the synchronisation and can be
used to switch the presence of a video signal (via the VID bit). In this way a very stable OSD can
be realised. The result of the video ident circuit can be read from the output bit SID (subaddress
00).
5.2.6 Synchronisation circuit
The IC contains separator circuits for the horizontal and vertical sync pulses. To obtain an
accurate timing of the displayed picture the input signal of the sync separator is not derived from
the various CVBS/Y or RGB/YPrPb inputs but from the YOUT pin. For this reason the YOUT pin
must be capacitively coupled to the YSYNC pin. The delay between the various inputs and the
YOUT signal can have rather large differences (e.g. comb filter active or not). By choosing the
YOUT signal as input signal for the sync separator these delays have no effect on the picture
position. Only for RGB signals without sync on green the input of the sync separator has to be
connected to one of the CVBS inputs. This selection is made by means of the SYS bit.
The horizontal drive signal is obtained from an internal VCO which is running at a frequency of
25 MHz. This oscillator is stabilised to this frequency by using the clock signal coming from the
reference oscillator of the TCG -Controller.
To obtain a stable On-Screen-Display (OSD) under all conditions it is important that the first
control loop is switched off or set to low gain when no signal is available at the input. The input
signal condition is detected by the video identification circuit. The video identification circuit can
automatically switch first control loop to a low gain when no input signal is available. This mode is
obtained when the VID bit is set to “0”. When the VID bit is “1” the mode of the first control loop
can be switched by means of the FOA/FOB or POC bits.
For a good performance during normal TV reception (display of the front-end signal) various
connections are active between the vision IF amplifier and the synchronisation circuit (e.g. gating
pulses for the AGC detector and noise gating of the sync separator). These connections are not
allowed when external video signals are displayed. The switching of these connections can be
coupled to the input signal selection bits (INA-IND). This mode is obtained when the VDXEN bit
is “0”. Due to the input signal selector configuration it is possible that the internal CVBS signal is
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36
available on one of the other CVBS inputs.In this condition the connections between the vision IF
amplifier and the synchronisation circuit can be switched on and off by means of the VDX bit.
The VDXEN bit must be set to “1” for this mode.
The vertical synchronisation is realised by means of a divider circuit.
5.2.7 Horizontal and vertical drive
The horizontal drive is switched on and off via the soft start/stop procedure. The soft start
function is realised by means of variation of the TON of the horizontal drive pulses. During the
soft-stop period the horizontal output frequency is doubled resulting in a reduction of the EHT so
that the picture tube capacitance can easily be discharged. In addition the horizontal drive circuit
has a ‘low-power start-up’ function.
The vertical ramp generator needs an external resistor and capacitor. For the vertical drive a
differential output current is available. The outputs must be DC coupled to the vertical output
stage.
The IC has the following geometry control functions:
n Vertical amplitude
n Vertical slope
n S-correction
n Vertical shift
n Vertical zoom
n Vertical scroll
n Vertical linearity correction. When required the linearity setting for the upper and lower part
of the screen can have a different setting.
n Horizontal shift
n EW width
n EW parabola width
n EW upper and lower corner parabola correction
n EW trapezium correction
n Horizontal parallelogram and bow correction.
When the East-West geometry function is not required (e.g. for 90 picture tubes) the EW output
pin can be used for the connection of the AVL capacitor. This function is chosen by means of the
AVLE bit.
5.2.8 Chroma, luminance and feature processing
Someversionscontaina4H/2H(2D)adaptivePAL/NTSC comb filter. The comb filter is
automatically activated when standard CVBS signals are received.A signal is considered as
“standard signal” when a PAL or NTSC signal is identified and when the vertical divider is in the
modes ‘standard narrow window’ or ‘standard TV norm’.For non-standard signals and for
SECAM signals the comb filter is bypassed and the signal is filtered by means of bandpass and
trap filters.
The chroma band-pass and trap circuits (including the SECAM cloche filter) are realised by
means of internal filters and are tuned to the right frequency by comparing the tuning frequency
with the reference frequency of the colour decoder.
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The circuit contains the following picture improvement features:
n Peaking control circuit. The peaking function can be activated for all incoming CVBS, Y/C
and RGB/YPrPb signals. Various parameters of the peaking circuit can be adapted by means
of the I2C-bus. The main parameters are:
- Peaking centre frequency (via the PF1/PF0 bits in subaddress 19H).
- Ratio of positive and negative peaks (via the RPO1/RPO0 bits in subaddress 47H). The
peaks in the direction “white” are the positive peaks.
- Ratio of pre- and aftershoots (via the RPA1/RPA0 bits in subaddress 47H).
n Video dependent coring in the peaking circuit. The coring can be activated only in the low-
light parts of the screen. This effectively reduces noise while having maximum peaking in the
bright parts of the picture.
n Black stretch. This function corrects the black level for incoming signals which have a
difference between the black level and the blanking level. The amount of stretching (A-A in
Fig. 72) and the minimum required back ground to activate the stretching can be set by
means of the I2C-bus (BSD/AAS in subaddress 45H).
n Gamma control. When this function is active the transfer characteristic of the luminance
amplifier is made non-linear.Thecontrolcurvecanbeadaptedbymeans of I2C-bus settings (see
Fig. 74). It is possible to make the gamma control function dependent on the picture content
(Average Picture Level, APL). The effect is illustrated in Fig. 75. Previously this function was
mentioned under the name “white stretch function”.
n Blue-stretch. This circuit is intended to shift colour near ‘white’ with sufficient contrast values
towards more blue to obtain a brighter impression of the picture.
n Dynamic skin tone (flesh) control. This function is realised in the YUV domain by detecting
the colours near to the skin tone.
n Scan-Velocity modulation output. Also the SVM function can be activated for all incoming
CVBS, Y/C and RGB/YPrPb signals. The delay between the RGB output signals and the
SVM output signal can be adjusted (by means of the SVM2-SVM0 bits in subaddress 48H)
so that an optimum picture performance can be obtained. Furthermore a coring function can
be activated. It is possible to generate Scan Velocity Modulation drive signals during the
display of ‘full screen’ teletext (not in mixed mode). Another feature is that the SVM output
signal can be made dependent on the horizontal position on the screen (parabola on the
SVM output).
5.2.9 Colour decoder
The ICs decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder does not need
external reference crystals but has an internal clock generator which is stabilised to the required
frequency by using the clock signal from the reference oscillator of the TCG u -Controller.
Under bad-signal conditions (e.g. VCR-playback n feature mode), it may occur that the colour
killer is activated although the colour PLL is still in lock. When this killing action is not wanted it is
possible to overrule the colour killer by forcing the colour decoder to the required standard and to
activate the FCO-bit (Forced Colour On) in subaddress3CH. The sensitivity of the colour decoder
for PAL and NTSC can be increased by means of the setting of the CHSE1/CHSE0 bits in
subaddress 3CH.
The Automatic Colour Limiting (ACL) circuit (switchable via the ACL bit in subaddress 3BH)
prevents that oversaturation occurs when signals with a high chroma-to-burst ratio are received.
The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal.
This has the advantage that the colour sensitivity is not affected by this function.
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The SECAM decoder contains an auto-calibrating PLL demodulator which has two references,
viz: the divided reference frequency (obtained from the-Controller) which is used to tune the PLL
to the desired free-running frequency and the bandgap reference to obtain the correct absolute
value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period,
when the IC is in search or SECAM mode. The frequency offset of the B-Y demodulator can be
reduced by means of the SBO1/SBO0 bits in subaddress 3CH.
The base-band delay line is integrated. In devices without CVBS comb filter this delay line is also
active during NTSC to obtain a good suppression of cross colour effects. The demodulated
colour difference signals are internally supplied to the delay line. The baseband comb filter can
be switched off by means of the BPS bit (subaddress 3CH).
The subcarrier output is combined with a 3-level output switch (0 V, 2.1 V and 4.5 V). The output
level and the availability of the subcarrier signal is controlled by the CMB2-CMB0 bits.
5.2.10 RGB output circuit
In the RGB control circuit the signal is controlled on contrast, brightness and saturation. The IC
has a YUV interface so that additional picture improvement ICs can be applied. To compensate
signal delays in the external YUV path the clamp pulse in the control circuit can be shifted by
means of the CLD bit in subaddress 44H. When the YUV interface is not required some of the
pins can be used for the insertion of RGB/YPrPb signals or as additional CVBS(Y)/C input. When
the YUV interface is not used one of the pins (VOUT) is transferred to general purpose output
switch (SWO1). The IC has also a YUV interface to th edigita ldie. Via this loop digital features
like “double window” are added.
A tint control is available for the base-band U/V signals. For this reason this tint control can be
activated for all colour standards. The signals for OSD and text are internally supplied to the
control circuit. The output signal has an amplitude of about 1.2V black-to-white at nominal input
signals and nominal settings of the various controls.
To obtain an accurate biasing of the picture tube the ‘Continuous Cathode Calibration’ system
has been included in these ICs. The system is slightly adapted compared with the previous
circuits. In the new configuration the cut-off level of the picture tube is controlled with a
continuous loop whereas the correction of the amplitude of the output signals is realised by
means of a digital loop. As a consequence the current measurement can be controlled from theProcessor. The value of the “highcurrent”intheCCCloopcanbechosenviatheSLG0 and SLG1 bits
(subaddresses 42H and 46H). The gain control in the 3 RGB channels is realised by means of 7bit DACs. The total gain control range is6 dB. The change in amplitude at the cathodes of the
picture tube for one LSB is about 1.1 Vp-p. The setting of the control DAC is determined by the
following registers:
n The white point setting of the R, G and B channel in subaddress 20H to 22H. This register
has a resolution of 6 bits and the control range in output signal amplitude is +/-3 dB.
n The cathode drive setting (CL3-CL0 in subaddress 42H). This setting is valid for all channels,
there solution is 4 bits and the control range is +/-3 dB.
n The gain setting of the R, G and B channel. During switch on this register is loaded with the
preset gain setting of subaddress 23H to 25H and when necessary it will be adapted by the
CCC control loop. These registers have a resolution of 7 bits. The control of the gain setting
is illustrated in table below.
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39
WPR(GB) ‘0’ B5 B4 B3 B2 B1 B0 Max 64
CL ‘0’ B3 B2 B1 B0 ‘0’ ‘0’ Max 60
CCC-gain B6 B5 B4 B3 B2 B1 B0 Max 126
R(GB)-gain B6 B5 B4 B3 B2 B1 B0 Max 126
The setting of the gain registers of the 3 channels can be stored during switch off and can be
loaded again during switch-on so that the drive conditions are maintained.
When required the operation of the CCC system can be changed into a one-point black current
system. The switching between the 2 possibilities is realised by means of the EGL bit (EGL = 0)
in subaddress 42H. When used asone-point control loop the system will control the black level of
the RGB output signals to the ‘low’ reference current and not on the cut off point of the cathode.
In this way spreads in the picture tube characteristics will not be taken into account. In this
condition the settings of the “white point control registers”(subaddress 20H-22H) and the
“cathode drive level bits” (CL3 - CL0 in subaddress 42H) are added to the settings of the RGB
preset gain registers (subaddress 23H - 25H).
A black level off-set can be made with respect to the level which is generated by the black
current stabilization system. In this way different colour temperatures can be
obtainedforthebrightandthedarkpartofthepicture.The black level control is active on the Red and
the Green output signal. It is also possible to control the black level of the Blue and the Green
output signal (OFB bit = 1).
In the Vg2 adjustment mode (AVG=1) the black current stabilization system checks the output
level of the 3 channels and indicates whether the black level of the highest output is in a certain
window(WBC-bit) or below or above this window (HBC-bit). This indication can be read from the
status byte 01 and can be used for automatic adjustment of the Vg2 voltage during the
production of the TV receiver. During this test the vertical scan remains active so that the
indication of the 2 bits can be made visible on the TV screen.
The control circuit contains a beam current limiting circuit and a peak white limiting circuit. The
control is realised by means of a reduction of the contrast and brightness control settings. The
way of control (first contrast and then brightness or contrast and brightness in parallel) can be
chosen by means of the CBS bit (subaddress 44H). The peak white level is adjustable via the
I2C-bus.
To prevent that the peak white limiting circuit reacts on the high frequency content of the video
signal a low-passfilter is inserted in front of the peak detector. The circuit also contains a softclipper which prevents that the high frequency peaks in the output signal become too high. The
difference between the peak white limiting level and the soft clipping level is adjustable via the
I2C-bus in a few steps.
During switch-off of the TV receiver a fixed beam current is generated by the black current
control circuit. This current ensures that the picture tube capacitance is discharged. During the
switch-off period the vertical deflection can be placed in an overscan position so that the
discharge is not visible on the screen.
A wide blanking pulse can be activated in the RGB outputs by means of the HBL bit in
subaddress 43H. The timing of this blanking can be adjusted by means of the bits WBF/R bits in
subaddress 26H.
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40
5.2.11 I2C-BUS USER INTERFACE DESCRIPTION
The UOC III series is fully controlled via the I2C-bus. Control is exercised by writing data to one
or more internal registers. Status information can be read from a set of info registers to enable
the controlling microcontroller determine whether any action is required. The device has an I2Cbus slave transceiver, in accordance with the fast-mode specification, with a maximum speed of
400 kbits/s. Information concerning the I2C-bus can be found in brochure “I2C-bus and how to
use it” (order number 939839340011). To avoid conflicts in a real application with other ICs
providing similar or complementary functions, there are two possible slave addresses available
which can be selected by the SVM pin(pin 65).
Possible slave address
SVM PIN SLAVE ADDRESS A6 TO A0
Scavem application 1 0 0 0 1 0 1
Tied 5 volts 1 0 0 0 1 1 1
The device will not respond to a ‘generalcall’ on the I2C-bus, i.e. when a slave address of
0000000 is sent by a master.
Write registers
Each address of the address space (see below) can only be written.
Correct operation is not guaranteed if registers in the range $FB to $FF will be addressed!
Read registers
The output registers of the TV processor are only available via auto-increment mode, no address
can be used and all registers must be read.
5.3 GENERAL DESCRIPTION OF THE TV SOUND OF SOUND PROCESSOR
The TV Sound Processor is a digital TV sound processor for analog multi-channel sound
systems in TV sets. It is based on a 24 bit DSP and designed to support several applications.
A new easy-to-use control concept was implemented for easiest configuration programming of
the very complex functionality of the TV Sound Processor. Pre-defined setups are available for
all implemented sound processing modes. Aloud speaker switching concept allows it to adapt the
pre-defined setups to the specific loudspeaker application.The built-in intelligence for pre-defined
standards and Auto Standard Detection (ASD) allows an easy setup of the demodulator and
decoder part.
The control concept for the audio processor is based on the following new features:
n Pre-defined setups for the sound processing modes like Dolby® Pro Logic® and Virtual
Dolby® Surround (422, 423)
n Flexible configuration of audio outputs to the loudspeaker configuration with an additional
output crossbar
n Master volume function
The control concept for the demodulator and decoder (DEMDEC) is based on the following new
features:
n Easy demodulator setup for all implemented standards with Demodulator and Decoder Easy
Programming (DDEP) for a pre-selected standard or combined with Auto Standard Detection
(ASD) for automatic detection of a transmitted standard
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41
n Automatic decoder configuration and signal routing depending on the selected or detected
standard
n FM overmodulation adaptation option to avoid clipping and distortion
5.3.1 Supported standards
The multistandard capability of the TV Sound Processor covers all terrestrial TV sound standards,
FM Radio and satellite FM.
The AM sound of L/L' standard is normally demodulated in the 1st sound IF. The resulting AF
signal has to been tered into the mono audio input of the TV Sound Processor. A second
possibility is to use the AMdemodulator in the DEMDEC part, however this may result in limited
performance.
Korea has a stereo sound system similar to Europe. It is supported by the TV Sound Processor.
Differences include deviation, modulation contents and identification. It is based on M standard.
Other features of the DEMDEC are:
n M/BTSC and N standards supported
n M/Japan (EIAJ) supported
n FM Radio stereo decoding
n Alignment-free, fully digital system
n For BTSC full dbx® performance
n SAP demodulation (without dbx®) simultaneously with stereo decoding, or mono plus SAP
with dbx®
n Line/pilot frequency selectable from 15.734 kHz and 15.625 kHz (or automatic detection /
auto search)
n High selectivity for pilot detection, high robustness against high-frequent audio components
n Pilot lock indicator
n SAP detector
n Separate noise detectors for stereo and SAP with adjustable threshold levels, hysteresis, and
automute function
An overview of the supported standards and sound systems and their key parameters is given in
the following tables.
The analog multi-channel sound systems (A2, A2+ and A2*) are sometimes also named 2CS (2
carrier systems).
ANALOG 2-CARRIER SYSTEMS
[Table] Frequency modulation
STANDARD
M Mono 4.5 15/25/50 Mono - 15/75
M A2+ 4.5/4.724 15/25/50 1/2(L+R) 1/2(L+R) 15/75(Korea)
B/G A2 5.5/5.742 27/50/80 1/2(L+R) R 15/50
I Mono 6.0 27/50/80 mono - 15/50
D/K(1) A2* 6.5/6.258 27/50/80 1/2(L+R) R 15/50
D/K(2) A2* 6.5/6.742 27/50/80 1/2(L+R) R 15/50
D/K(3) A2* 6.5/5.742 27/50/80 1/2(L+R) R 15/50
SOUND
SYSTEM
CARRIER
FREQUENCY
(MHz)
FM DEVIATION(kHz)
NOM./MAX./OVER
MODULATION
SC1 SC2
BANDWIDTH/
DE-EMPHASIS
(kHz/us)
[Table] Identification for A2 systems
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42
PARAMETER A2/A2* A2+ (KOREA)
Pilot frequency 54.6875kHz = 3.5 x line freq. 55.0699 kHz = 3.5 x line freq.
Stereo identification frequency 117.5 Hz = line freq / 133 149.9 Hz = line freq / 105
Dual indetification frequency 274.1 Hz = line freq / 57 276.0 Hz = line freq / 57
AM modulation depth 50% 50%
2-CARRIERSYSTEMSWITHNICAM
[Table] NICAM standards
SC1
MODULATION
STANDARD
B/G 5.5 FM - 27/50/80 5.85 J17 40 Note1
I 6.0 FM - 27/50/80 6.552 J17 100 Note1
D/K 6.5 FM - 27/50/80 5.85 J17 40 Note1
L 6.5 AM 54/100 - 5.85 J17 40 Note1
FREQUENCY
(MHz)
TYPE
INDEX(%)
NOM./MAX.
DEVIATION
(kHz)
NAM./MAX.
/OVER
SC2
(MHz)
NICA
M
DE-
EMPAHSIS
ROLL-
OFF (%)
NICAM
CODING
Note 1. See ‘EBU specification’ or equivalent specification.
5.4 FUNCTIONAL DESCRIPTION SOUND PROCESSOR
5.4.1 The UOC III TV Sound Concept
The UOCIII sound concept is implemented over the video processor and TCG-microcontroller.
Only relevant blocks, functions and signal flows for sound are given.
The tuner receives a RF signal and converts it to IF. Via appropriate SAW filters the SIF signal is
delivered to the QSS stage of the video processor and if channels according to standard L/L’ are
received also to the AM demodulator. The Quasi Split Sound demodulation generates the SSIF
or intercarrier signal. By the SSIF switch it is possible to choose between the internally derived
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43
intercarrier and an external second SIF(2NDSIFEXT), e.g. an intercarrier coming from a PIP
frontend. In other applications a 10.7MHz radio IF or satellite FM may be connected to this input.
The selected SSIF passes some anti alias filtering, is amplified in an AGC amplifier (SSIF AGC)
and is then converted from analogue to digital (SSIF ADC).
The audio signal out of the AM demodulator is connected to the analogue crossbar at the video
processor. All other inputs to this multiplexer/audio switch come from external, either from a PIP
frontend or SCART/CINCH(AUDINx) or the DAC output signals from the digital controller. The
audio AD converters are digitising the audio signals foreseen for further digital processing. One
stereo output (AUDOUTS) is available for connections to SCART/CINCH sockets.
The sound part on the digital controller consists of the demodulator/decoder(DEMDEC), a digital
input crossbar, the digital audio processing for the loudspeaker and DAC channels, the I2S
processing and interfacing, a digital output crossbar as well as the DA conversion.
An auxiliary audio control (volume control, AUX audio contr.) is available on the video processor.
Here it is applied to the headphone channel.
The part of the concept located in the digital controller will be described in the next chapters.
5.4.2 Functional Overview Of the digital controller sound part
The digital controller sound part consists of the SSIFADC, audio ADCs, DEMDEC HW, the sound
DSP core, audio DACs and I2S interface hardware as shown in fig below. The DEMDEC part of
the Sound DSP is used for the decoder and partly demodulator tasks. The AUDIO part provides
the sound features, from the level adjust unit up to the output crossbar. Audio DACs and I2S
hardware are converting the processed signals to analogue or digital audio.
The SSIF signal is applied to the SSIF ADC for conversion and is then fed to the DEMDEC
hardware processing mainly for demodulation but also some decoding tasks. Remaining
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44
decoding is done in the DEMDEC block of the Sound DSP. The DEMDEC processing will be
described in the next chapter.
The audio signals (AUD ADC IN) from the analogue crossbar pass the audio ADC and are fed
directly into the AUDIO part of the Sound DSP like the I2S signals, which is coming from I2S
processing hardware. After level adjust all signals from the DEMDEC and the I2S input are
available at the digital input crossbar. A special input is provided for the Noise/Silence Generator
needed for olby® Pro Logic® processing.
In standard TV applications the main channel signal(L,R) will be connected to the DAC2 for
reproduction at the speakers. With multichannel signals centre, surround or subwoofer channels
may be passed to the I2S outputs where external DACs may be applied. By this it is possible to
build Dolby Normal/Wide, Dolby Phantom Centre or Dolby 3 Stereo set-ups and also a VDS423
application.
5.4.3 Demodulator and decoder
INTRODUCTION
The TV sound processor provides an easy-to-use programming interface and built-in intelligence
for the demodulator and decoder part.
The sound demodulator is able to search for sound carriers and react to transmission mode
changes autonomously, without interaction of the micro controller software.
It is possible for a typical terrestrial TV application to setup the entire demodulator with
transmission of few control words.
The control interface still allows access to every detail, called demodulator expert mode, for
special applications such as satellite TV, more elaborated search algorithms etc.
The new TV Sound ProcessorDemodulator and
DecoderEasyProgramming(DDEP)interfaceprovides three possible approaches to setup the
demodulator and decoder parts:
n Auto Standard Detection (ASD)
n Static Standard Selection (SSS)
n Demodulator and Decoder Expert Mode (DDXM)
MIXER
The digitized 2nd SIF input signal is fed to the mixers, which mix one or both input sound carriers
down to zero IF. The mixer frequency is derived by the standard setting (Easy Programming) or
in the Demodulator and Decoder Expert Mode (DDXM) by a 24-bit control word for each carrier.
For NICAM demodulation, a feedback signal is added to the control word of the second carrier
mixer to establish a carrier-frequency loop.
FMANDAMDEMODULATION
An FM or AM input signal is fed via a band-limiting filter to a one of two demodulators that can be
used for either FM or AM demodulation. Four filters with different bandwidth are available. The
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45
output signal of the first demodulator can be used for further demodulation of multiplex signals
used in the BTSC, EIAJ and FM Radio standards.
FMIDENTIFICATION
The identification of the FM sound mode is performed by AM synchronous demodulation of the
pilot signal and narrow-band detection of the identification frequencies. The result is available via
the control bus interface. A selection can be made for three different modes that represent
different trade-offs between speed and reliability of identification. The mode is set by DDEP (for
FM two-carrier standards) or via expert mode. DDEP also performs automatic FM de-matrix
control in dependence on the identification.
FM/AMDECODING
A high-pass filter suppresses DC offsets from the FM/AM demodulators due to carrier frequency
offsets and supplies the monitor/peak function with DC values and an un-filtered signal, e.g. for
the purpose of carrier detection.
The audio bandwidth is approx. 15 kHz.
The de-emphasis function offers fixed settings for the supported standards (50s, 60s, 75s and
J17).
A matrix performs the de-matrixing of the A2 stereo, dual and mono signals to obtain the left (L)
and right (R) or language A and B signals.
FMPILOTCARRIERPRESENTDETECTOR
The TV Sound Processor provides FM A2 standard pilot carrier detection.
NICAMDEMODULATION
The NICAM signal is transmitted via DQPSK modulation at a bit rate of 728kBit/s. The NICAM
demodulator performs DQPSK demodulation and feeds the resulting bit stream and clock signal
to the NICAM decoder.
A timing loop controls the sample rate conversion circuitry to lock the sampling rate to the symbol
timing of the NICAM data.
NICAM DECODER
The NICAM decoder performs all decoding functions in accordance with theEBU NICAM 728
specification. After locking to the frame alignment word, the data is de scrambled by applying the
defined pseudo-random binary sequence; the NICAM decoder will then synchronize to the
periodic frame flag bitC0.
The status of the NICAM decoder can be read out from the NICAM status register by the user
(see the control-bus register description). The OSB bit indicates that the decoder has locked to
the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM data and that
the data is valid sound data. The C4 bit indicates that the sound conveyed by the FM mono
channel is identical to the sound conveyed by the NICAM channel. The error byte contains the
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46
number of sound sample errors, resulting from parity checking, that occurred in the past 128ms
period. The Bit Error Rate (BER) can be calculated using the following equation;
During NICAM mode a switchable J17 de-emphasis is supplied.
NICAM AUTO-MUTE
If the Auto Standard Detection (ASD) or the Static Standard Detection (SSS) feature is activated
the following auto mute function is in effect.
If NICAM B/G, I, D/K is received, the auto-mute is enabled and the signal quality becomes poor,
the built-in control automatically switches the output signal (DEC output) to FM channel 1. The
automatic switching depends on the NICAM bit error rate. The auto-mute function can be
disabled via the control bus.
This function is enabled by setting bit NIC_AMUTE to 0. Upper and lower error limits may be
defined by writing appropriate values to the corresponding control bits (NICLOERRLIM and
NICUPERRLIM). When the number of errors in a 128 ms period exceeds the upper error limit the
auto-mute function will switch the output sound from
NICAMtowhateversoundisonthefirstsoundcarrier(FM or AM). When the error count is smaller than
the lower error limit the NICAM sound is restored.
The auto-mute function can be disabled by setting bit NIC_AMUTE to 1. In this condition clicks
become audible when the error count increases; the user will hear a signal of degrading quality.
For NICAM L applications, it is recommended to demodulate AM sound in the first sound IF. The
demodulated AM is provided by the internal IF processor. For applications with external IF
processing the external demodulated AM signal can be connected to the SCART/Mono input of
the TV Sound Processor. By setting the EXTAM bit, the auto-mute function will switch to the
audio ADC input signal named EXTAM instead of switching to the first sound carrier. The ADC
source selector should be set to internal AM mono signal or to the external SCART/mono input,
where the AM sound signal should be connected.
Page 48
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CP-520V Service Manual
6. SERVICE PARTS LIST
6.1 DTX-21G2FZP-SB
z_locz_parts_codeparts_nameparts_descrremark
z_locz_parts_codeparts_nameparts_descrremark
ZZ100PTACPWE519ACCESSORY ASDTX-21G2FZS-SB
1200048B5849C1001TRANSMITTER REMOCONR-49C10
130004850Q00910BATTERYAAA R03 SUPERGARD/ROCKET
140004858213801BAG INSTRUCTIONL. D. P. E. T0. 05X250X400
ZZ120PTBCSHE519COVER BACK ASDTX-21G2FZS-SB
M2114852172311GCOVER BACK21G2 HIPS GY8301A
M5414855415800S/PLATE150ART P/E FILM (C/TV)
M5424855800022P1LABEL SERIALART 90 55X34
ZZ130PTCACAE524CABINET ASDTX-21G2FZP-SB
202193110002SOLDER WIRESN-3.0AG-0.5CU (DHB-RMA3)
404856812001TIE CABLENYLON66 DA100
M1914851954300DOOR AS21G2 GY340A+SV128BP/PC
M201A4856017703SCREW CRT FIX5X30 L80 BK 3CR
M201B4856215402WASHER RUBBER20’’
M201C4856017710SCREW CRT FIX5X30 L190 BK 3CR
M211A7172401652SCREW TAPPTITETT2 TRS 4X16 MFZN BK 3CR
M211B7178301052SCREW TAPPTITETT2 WAS 3X10 MFZN BK 3CR
M231A7172401252SCREW TAPPTITETT2 TRS 4X12 MFZN BK 3CR
M4814854869711BUTTON POWER21G2 ABS GY340A+SV128BP
M481A4856715600SPRING14A5 SWPA
M501485506202001DECO CTRL21G2 PC T0.25
M56148556192SD02MARK BRAND“DAEWOO 68MM (20””21””)”
M7814857817610CLOTH BLACK“300 MM 20”””
M7914857923300DOOR LOCKLA701 (KIFCO)
PWC14859903110CORD POWERW/F 6-LO (LOMAX)
SP01A7172401252SCREW TAPPTITETT2 TRS 4X12 MFZN BK 3CR
SP02A7172401252SCREW TAPPTITETT2 TRS 4X12 MFZN BK 3CR
V9014859640060“CRT (THOMSON 21””)”A51ELD032X001
ZZ13158G0000177COIL DEGAUSSINGDC-21SF AL
ZZ13248519A7610CRT GROUND AS2103S-1015-1P
ZZ200PTFMSJY21G2SMASK FRONT ASDTY-21G2 SV128BP
M2314852330711PANEL FRONT21G2 HIPS BK+GY8204BP
M8014852090511SMASK FRONT21G2 GY340A
ZZ210PTSPPWE519SPEAKER ASDTX-21G2FZS-SB
P601A4850704S28CONN ASYH025-04+35089+ULW=600
SP014858317410SPEAKERSP-58126FC
SP024858317410SPEAKERSP-58126FC
ZZ290PTMPMSE524PCB MAIN MANUAL ASDTX-21G2FZP-SB
102193110001SOLDER WIRESN-3.0AG (NP303T) 3.0
202193110002SOLDER WIRESN-3.0AG-0.5CU (DHB-RMA3)
302291050617PFLUX SOLDERCF-329D
402291050314FLUX SOLVENTIM-1000
C403CMYH3C662HC MYLAR1.6KV BUP 6600PF H
C407CMXF2E224JC MYLAR250V MPU 0.22MF J
C408CEXF2E100VC ELECTRO250V RSS 10MF (10X20) TP
C626CEXF1C102VC ELECTRO16V RSS 1000MF (10X20) TP
C801CL1UC3474MC LINE ACROSS0.47MF 1J(UCVSNDF/SV
C804CEYD2G181DC ELECTRO400V FHS 180MF
C805CCXR3D681KC CERA2KV R 680PF K 125C
C811CH1BFE222MC CERA ACU/C/V AC400V 2200PF
C812CCXB3D471KC CERA2KV B 470PF K (TAPPING)
C813CEXF2C101VC ELECTRO160V RSS 100MF (16X25) TP
C814CEXF2C470VC ELECTRO160V RSS 47MF (13X25) TP
C816CEXF1C102VC ELECTRO16V RSS 1000MF (10X20) TP
C818CEXF1C222VC ELECTRO16V RSS 2200MF(13X25)TP
C827CCXB3D471KC CERA2KV B 470PF K (TAPPING)
D707DLH3PRG03-LED BLOCKLH-3P-RG-03
F8015FSCB4022RFUSE CERASEMKO F4AH 4A 250V MF51
HP014859102130JACK EARPHONEYSC-1537
I3011LA78040—IC VERTICALLA78040
I301A4857027100HEAT SINKSPCC T1.0+SN
I301B7174300851SCREW TAPPTITETT2 RND 3X8 MFZN 3CR
I502124LC16B1BIC MEMORY24LC16B1B
I6011LA42032E-IC AUDIO AMPLA42032-E
I601A4857024401HEAT SINKAL EX (NO ANODIZING)
I601B7174300851SCREW TAPPTITETT2 RND 3X8 MFZN 3CR
I8011STRW6754-IC POWERSTR-W6754
I801A4857024600HEAT SINKAL EX B/K
I801B7174300851SCREW TAPPTITETT2 RND 3X8 MFZN 3CR
I8021LTV817C—IC PHOTO COUPLERLTV-817C
I8041LE33CZ—-IC REGULATORLE33CZ
IF011441VF6—-IC PREAMP441VF6
JPA014859200401SOCKET RGBSR-21A1 (ANGLE TYPE)
JPA024859200401SOCKET RGBSR-21A1 (ANGLE TYPE)
JPA034859108450JACK PIN BOARDYSC03P-4120-14A
L40158H0000020COIL H-LINEARITYL-76(76.5UH)
LF8015PLF24A1—FILTER LINELF-24A1
P4014850705N14CONNECTORBIC-05T-25T+ULW=500
P4024859242420CONN WAFERYFW800-04
P5014850705N14CONNECTORBIC-05T-25T+ULW=500
P6014859231720CONN WAFERYW025-04
P7014859231720CONN WAFERYW025-04
P8014859242220CONN WAFERYFW800-02
P8024859242220CONN WAFERYFW800-02
Q402TST1803DFHTR HORIST1803DFH
Q402A4857027201HEAT SINKAL T1.0
Q402B7174301051SCREW TAPPTITETT2 RND 3X10 MFZN 3CR
R311RS02Y229JSR M-OXIDE FILM2W 2.2 OHM J SMALL
R406RS02Y103JSR M-OXIDE FILM2W 10K OHM J SMALL
R407RS02Y102JSR M-OXIDE FILM2W 1K OHM J SMALL
R411RS02Y109JSR M-OXIDE FILM2W 1 OHM J SMALL
R800RX07B229JPR CEMENT7W 2.2 OHM J BEN 15MM 4P
R801DTC7R0M270POSISTORPDC7R0MP6B7Z81C
R805RS02Y228JSR M-OXIDE FILM2W 0.22 OHM J SMALL
SCT014859304130SOCKET CRTISHG93S
SW8015S40101143SW PUSHPS3-22SP (P.C.B)
T40150D10A3—-TRANS DRIVETD-10A3
T40250H0000310FBTLTC-565
T80150M3541C4-TRANS SMPSTSM-3541C4
U1004859730330TUNER VARACTORTAEM-G010D
X5015XJ24R576ECRYSTAL QUARTZHC-49/S 24.576MHZ 30PPM
Z1015PK3953M—FILTER SAWK3953M
Z1025PK9650M—FILTER SAWK9650M
ZZ200PTMPJBE520PCB MAIN EYE LET ASDTX-21U7FZS
E014856310600EYE LETBSR 2.3(R2.3) BIG
E024856310600EYE LETBSR 2.3(R2.3) BIG
E034856310600EYE LETBSR 2.3(R2.3) BIG
E054856310600EYE LETBSR 2.3(R2.3) BIG
E064856310300EYE LETBSR T0.2 (R1.6) SMALL
E084856310300EYE LETBSR T0.2 (R1.6) SMALL
E094856310300EYE LETBSR T0.2 (R1.6) SMALL
E104856310300EYE LETBSR T0.2 (R1.6) SMALL
E114856310300EYE LETBSR T0.2 (R1.6) SMALL
E124856310300EYE LETBSR T0.2 (R1.6) SMALL
E134856310300EYE LETBSR T0.2 (R1.6) SMALL
E144856310300EYE LETBSR T0.2 (R1.6) SMALL
E154856310300EYE LETBSR T0.2 (R1.6) SMALL
E164856310300EYE LETBSR T0.2 (R1.6) SMALL
E174856310300EYE LETBSR T0.2 (R1.6) SMALL
E184856310300EYE LETBSR T0.2 (R1.6) SMALL
E194856310300EYE LETBSR T0.2 (R1.6) SMALL
E204856310300EYE LETBSR T0.2 (R1.6) SMALL
E214856310600EYE LETBSR 2.3(R2.3) BIG
E224856310600EYE LETBSR 2.3(R2.3) BIG
E234856310600EYE LETBSR 2.3(R2.3) BIG
E244856310600EYE LETBSR 2.3(R2.3) BIG
E254856310600EYE LETBSR 2.3(R2.3) BIG
ZZ200PTMPJ2E520PCB CHIP MOUNT B ASDTX-21U7FZS
I5011TDA20HF01IC MICOM FLASHTDA12020H1/N1/F01
ZZ200PTMPJRE520PCB MAIN RADIAL ASDTX-21U7FZS
C101CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C102CEXF1C101VC ELECTRO16V RSS 100MF (6.3X11) TP
C105CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C106CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C302CEXF1H101VC ELECTRO50V RSS 100MF (8*11.5) TP
C305CEXF1C331VC ELECTRO16V RSS 330MF (8X11.5) TP
C306CEXF1C331VC ELECTRO16V RSS 330MF (8X11.5) TP
C307CMXM2A104JC MYLAR100V 0.1MF J TP
C401CMXM2A104JC MYLAR100V 0.1MF J TP
C402CCXB2H102KC CERA500V B 1000PF K (TAPPING)
Caution : In this Service Manual, some parts can be changed for improving, their performance
without notice in the parts list. So, if you need the latest parts information, please refer to PPL(Parts
Price List) in Service Information Center(http://svc.dwe.co.kr)
Page 49
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CP-520V Service Manual
z_locz_parts_codeparts_nameparts_descrremark
z_locz_parts_codeparts_nameparts_descrremark
C405CCXB2H561KC CERA500V B 560PF K (TAPPING)
C406CEXF2C109VC ELECTRO160V RSS 1MF (6.3*11) TP
C409CXSL2H470JC CERA500V SL 47PF J (TAPPING)
C410CMXM2A104JC MYLAR100V 0.1MF J TP
C501CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C502CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C505CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C507CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C508CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C509CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C510CEXF1E101VC ELECTRO25V RSS 100MF (6.3X11) TP
C511CCXB1H102KC CERA50V B 1000PF K (TAPPING)
C513CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C514CCXB1H102KC CERA50V B 1000PF K (TAPPING)
C515CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C516CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C517CEXF1C101VC ELECTRO16V RSS 100MF (6.3X11) TP
C518CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C519CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C520CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C521CMXM2A222JC MYLAR100V 2200PF J TP
C522CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C524CMXM2A682JC MYLAR100V 6800PF J TP
C525CEXF1H109VC ELECTRO50V RSS 1MF (5X11) TP
C526CMXL1J224JC MYLAR63V MEU 0.22MF J TP
C527CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C528CCXF1H223ZC CERA50V F 0.022MF Z (TAPPING)
C529CMXL1J154JC MYLAR63V MEU 0.15MF J
C534CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C535CMXL1J474JC MYLAR63V 0.47MF MKT
C536CMXL1J474JC MYLAR63V 0.47MF MKT
C537CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C538CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C539CMXM2A332JC MYLAR100V 3300PF J TP
C540CMXM2A473JC MYLAR100V 0.047MF J TP
C542CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C543CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C545CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C547CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C548CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C549CMXL1J474JC MYLAR63V 0.47MF MKT
C552CMXL1J474JC MYLAR63V 0.47MF MKT
C553CMXL1J474JC MYLAR63V 0.47MF MKT
C554CMXL1J474JC MYLAR63V 0.47MF MKT
C556CCXB1H102KC CERA50V B 1000PF K (TAPPING)
C558CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C560CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C561CEXF1H229VC ELECTRO50V RSS 2.2MF (5X11) TP
C562CMXM2A104JC MYLAR100V 0.1MF J TP
C563CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C567CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C568CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C569CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C574CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C576CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C577CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C579CCXB1H102KC CERA50V B 1000PF K (TAPPING)
C581CBXF1H104ZC CERA SEMI50V F 0.1MF Z (TAPPING)
C601CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C602CEXF1H479VC ELECTRO50V RSS 4.7MF (5*11) TP
C603CEXF1H479VC ELECTRO50V RSS 4.7MF (5*11) TP
C609CEXF1E470VC ELECTRO25V RSS 47MF (5X11) TP
C610CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C611CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C625CEXF1H479VC ELECTRO50V RSS 4.7MF (5*11) TP
C802CCXF3A472ZC CERA1KV F 4700PF Z (T)
C803CCXF3A472ZC CERA1KV F 4700PF Z (T)
C806CEXF1H100VC ELECTRO50V RSS 10MF (5X11) TP
C807CEXF1H109VC ELECTRO50V RSS 1MF (5X11) TP
C815CEXF2A100VC ELECTRO100V RSS 10MF (6.3X11) TP
C817CEXF1A471VC ELECTRO10V RSS 470MF(TAPPING)
C819CEXF2C109VC ELECTRO160V RSS 1MF (6.3*11) TP
C820CMXM2A104JC MYLAR100V 0.1MF J TP
C821CEXF1C101VC ELECTRO16V RSS 100MF (6.3X11) TP
C824CEXF1A471VC ELECTRO10V RSS 470MF(TAPPING)
C833CEXF1C101VC ELECTRO16V RSS 100MF (6.3X11) TP
C834CEXF1C101VC ELECTRO16V RSS 100MF (6.3X11) TP
C835CEXF1C471VC ELECTRO16V RSS 470MF (10X12.5)TP
C904CCXB3A271KC CERA1KV B 270PF K (TAPPING)
CA10CCXB1H102KC CERA50V B 1000PF K (TAPPING)
F801A4857415001CLIP FUSEPFC5000-0702
F801B4857415001CLIP FUSEPFC5000-0702
I8031K1A431B—IC REGULATOR(SHUNT)KIA431B 2.495V 0.5% TO-92
I8051K1A431B—IC REGULATOR(SHUNT)KIA431B 2.495V 0.5% TO-92
L5175CPX479K—COIL PEAKING4.7UH K RADIAL
L5185CPX479K—COIL PEAKING4.7UH K RADIAL
L5195CPX479K—COIL PEAKING4.7UH K RADIAL
L80258CX430599COIL CHOKEAZ-9004Y 940K TP
Q101T2SC5343Y-TR2SC5343Y
Q401TKTC3207—TRKTC3207
Q501T2SC5343Y-TR2SC5343Y
Q502T2SA1980Y-TR2SA1980Y
Q503T2SC5343Y-TR2SC5343Y
Q504T2SA1980Y-TR2SA1980Y
Q506T2SC5343Y-TR2SC5343Y
Q507T2SA1980Y-TR2SA1980Y
Q508T2SC5343Y-TR2SC5343Y
Q513T2SA1980Y-TR2SA1980Y
Q514TH2N7000—TRH2N7000
Q515TH2N7000—TRH2N7000
Q601T2SA1980Y-TR2SA1980Y
Q602T2SC5343Y-TR2SC5343Y
Q801T2SC5343Y-TR2SC5343Y
Q802T2SC5343Y-TR2SC5343Y
Q803T2SC5343Y-TR2SC5343Y
Q804TKTA1270Y-TRKTA1270Y
Q805TKTA1270Y-TRKTA1270Y
Q806T2SC5343Y-TR2SC5343Y
Q807TKTA1270Y-TRKTA1270Y
Q808T2SC5343Y-TR2SC5343Y
Q809TKTC3202Y-TRKTC3202Y
Q901TKTC3207—TRKTC3207
Q902TKTC3207—TRKTC3207
Q903TKTC3207—TRKTC3207
Q904TBF420——TRBF420
Q905TBF420——TRBF420
Q906TBF420——TRBF420
Q907TBF421——TRBF421
Q908TBF421——TRBF421
Q909TBF421——TRBF421
R823RN02B390JSR METAL FILM2W 39 OHM J SMALL
R836RN02B390JSR METAL FILM2W 39 OHM J SMALL
R837RN02B100JSR METAL FILM2W 10 OHM J SMALL
R838RN02B240JSR METAL FILM2W 24 OHM J SMALL
R904RN02B123JSR METAL FILM2W 12K OHM J SMALL
R905RN02B123JSR METAL FILM2W 12K OHM J SMALL
R906RN02B123JSR METAL FILM2W 12K OHM J SMALL
R910RN01B680JSR METAL FILM1W 68 OHM J SMALL
SW7005S50101090SW TACTSKHV17910A
SW7015S50101090SW TACTSKHV17910A
SW7025S50101090SW TACTSKHV17910A
SW7035S50101090SW TACTSKHV17910A
SW7045S50101090SW TACTSKHV17910A
Z6035PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6045PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6055PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6065PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6075PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6085PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6095PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6105PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6115PXF1B471MFILTER EMICFI 06 B 1H 470PF
Z6125PXF1B471MFILTER EMICFI 06 B 1H 470PF
ZZ200PTMPJAE520PCB MAIN AXIAL ASDTX-21U7FZS
102TM14006LBTAPE MASKING3M #232 6.0X2000M (WITH GLUE)
202TM10006LBTAPE MASKING3M #232-MAP-C 6.2X2000M (W/O GLUE)
A0014859813693PCB MAINCP-520V (DTX) 330X246(1X1)T1.6
C107CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C123CCZL1H472KC CERA50V B 4700PF K AXL (1608)
C301CCZJ1H103ZC CERA50V F 0.01MF Z AXL (1608)
C310CCZJ1H473ZC CERA50V F 0.047MF Z AXL (1608)
C412CCZJ1H473ZC CERA50V F 0.047MF Z AXL (1608)
C503CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C504CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C512CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C523CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C530CCZB1H101KC CERA50V B 100PF K (AXIAL)
C531CCZJ1H103ZC CERA50V F 0.01MF Z AXL (1608)
C532CCZJ1H103ZC CERA50V F 0.01MF Z AXL (1608)
C533CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C541CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C544CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
Page 50
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CP-520V Service Manual
z_locz_parts_codeparts_nameparts_descrremark
z_locz_parts_codeparts_nameparts_descrremark
C546CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C550CCZJ1H103ZC CERA50V F 0.01MF Z AXL (1608)
C551CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C555CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C557CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C564CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C565CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C566CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C575CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C578CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C589CCZL1H472KC CERA50V B 4700PF K AXL (1608)
C590CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C591CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C592CCZJ1H103ZC CERA50V F 0.01MF Z AXL (1608)
C605CBZR1C472MC CERAY5R 16V 4700PF M AXIAL
C606CBZR1C472MC CERAY5R 16V 4700PF M AXIAL
C612CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C613CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C614CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C615CCZJ1H104ZC CERA50V F 0.1MF Z AXL (1608)
C616CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C617CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C618CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C619CCZB1H102KC CERA50V B 1000PF K (AXIAL)
C701CCZJ1H103ZC CERA50V F 0.01MF Z AXL (1608)
C808CCZB1H471KC CERA50V B 470PF K (AXIAL)
C809CCZJ1H473ZC CERA50V F 0.047MF Z AXL (1608)
C810CCZB1H821KC CERA50V B 820PF K (AXIAL)
C828CCZB1H561KC CERA50V B 560PF K (AXIAL)
C901CCZB1H331KC CERA50V B 330PF K (AXIAL)
C902CCZB1H331KC CERA50V B 330PF K (AXIAL)
C903CCZB1H331KC CERA50V B 330PF K (AXIAL)
CA01CCZB1H101KC CERA50V B 100PF K (AXIAL)
CA02CCZB1H101KC CERA50V B 100PF K (AXIAL)
CA03CCZB1H101KC CERA50V B 100PF K (AXIAL)
CA04CCZB1H101KC CERA50V B 100PF K (AXIAL)
CA05CCZB1H101KC CERA50V B 100PF K (AXIAL)
CA06CCZB1H101KC CERA50V B 100PF K (AXIAL)
CA28CCZB1H102KC CERA50V B 1000PF K (AXIAL)
D101DUZ33B——DIODE ZENERUZ-33B
D102DBA282——DIODEBA282
D103D1N4148—-DIODE1N4148 (TAPPING)
D104DTZX3V9B—DIODE ZENERTZX3V9B (TAPPING)
D301D1N4004S—DIODE1N4004S
D302D1N4937G—DIODE1N4937G
D303D1N4937G—DIODE1N4937G
D401D1N4937G—DIODE1N4937G
D402D1N4148—-DIODE1N4148 (TAPPING)
D403D1N4148—-DIODE1N4148 (TAPPING)
D404D1N4937G—DIODE1N4937G
D501D1N4148—-DIODE1N4148 (TAPPING)
D502DTZX3V9B—DIODE ZENERTZX3V9B (TAPPING)
D503DTZX3V9B—DIODE ZENERTZX3V9B (TAPPING)
D522DTZX3V9B—DIODE ZENERTZX3V9B (TAPPING)
D523DTZX3V9B—DIODE ZENERTZX3V9B (TAPPING)
D524DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
D525DTZX6V2—-DIODE ZENERTZX6V2B (TAPPING)
D526DTZX6V2—-DIODE ZENERTZX6V2B (TAPPING)
D527DTZX6V2—-DIODE ZENERTZX6V2B (TAPPING)
D601D1N4148—-DIODE1N4148 (TAPPING)
D602D1N4148—-DIODE1N4148 (TAPPING)
D801DLT2A05G—DIODELT2A05G
D802DLT2A05G—DIODELT2A05G
D803DLT2A05G—DIODELT2A05G
D804DLT2A05G—DIODELT2A05G
D805D1N4937G—DIODE1N4937G
D806D1N4937G—DIODE1N4937G
D807D1N4148—-DIODE1N4148 (TAPPING)
D808DTZX6V2—-DIODE ZENERTZX6V2B (TAPPING)
D809DRGP15J—-DIODERGP15J
D811D1N4937G—DIODE1N4937G
D812DRGP15J—-DIODERGP15J
D817DRGP15J—-DIODERGP15J
D817BDRGP15J—-DIODERGP15J
D818DTZX4V3B—DIODE ZENERTZX4V3B (TAPPING)
D819DRGP15J—-DIODERGP15J
D820DTZX2V4A—DIODE ZENERTZX2V4A (TAPPING)
D821DTZX2V4A—DIODE ZENERTZX2V4A (TAPPING)
D902D1N4148—-DIODE1N4148 (TAPPING)
DA0185801060GYWIRE COPPER1/0.6 TIN COATING
DA02DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA0385801060GYWIRE COPPER1/0.6 TIN COATING
DA04DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA06DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA08DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA09DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA10DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA11DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA13DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA14DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA15DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA16DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA20DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA21DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DA22DTZX5V6B—DIODE ZENERTZX5V6B (TAPPING)
DF01DTZX3V9B—DIODE ZENERTZX3V9B (TAPPING)
J00185801060GYWIRE COPPER1/0.6 TIN COATING
J00285801060GYWIRE COPPER1/0.6 TIN COATING
J00385801060GYWIRE COPPER1/0.6 TIN COATING
J00485801060GYWIRE COPPER1/0.6 TIN COATING
J00585801060GYWIRE COPPER1/0.6 TIN COATING
J00685801060GYWIRE COPPER1/0.6 TIN COATING
J00785801060GYWIRE COPPER1/0.6 TIN COATING
J00885801060GYWIRE COPPER1/0.6 TIN COATING
J00985801060GYWIRE COPPER1/0.6 TIN COATING
J01085801060GYWIRE COPPER1/0.6 TIN COATING
J01185801060GYWIRE COPPER1/0.6 TIN COATING
J01285801060GYWIRE COPPER1/0.6 TIN COATING
J01385801060GYWIRE COPPER1/0.6 TIN COATING
J01485801060GYWIRE COPPER1/0.6 TIN COATING
J01585801060GYWIRE COPPER1/0.6 TIN COATING
J01685801060GYWIRE COPPER1/0.6 TIN COATING
J01785801060GYWIRE COPPER1/0.6 TIN COATING
J01885801060GYWIRE COPPER1/0.6 TIN COATING
J01985801060GYWIRE COPPER1/0.6 TIN COATING
J02085801060GYWIRE COPPER1/0.6 TIN COATING
J02185801060GYWIRE COPPER1/0.6 TIN COATING
J02285801060GYWIRE COPPER1/0.6 TIN COATING
J02385801060GYWIRE COPPER1/0.6 TIN COATING
J02485801060GYWIRE COPPER1/0.6 TIN COATING
J02585801060GYWIRE COPPER1/0.6 TIN COATING
J02685801060GYWIRE COPPER1/0.6 TIN COATING
J02785801060GYWIRE COPPER1/0.6 TIN COATING
J02885801060GYWIRE COPPER1/0.6 TIN COATING
J02985801060GYWIRE COPPER1/0.6 TIN COATING
J03085801060GYWIRE COPPER1/0.6 TIN COATING
J03185801060GYWIRE COPPER1/0.6 TIN COATING
J03285801060GYWIRE COPPER1/0.6 TIN COATING
J03485801060GYWIRE COPPER1/0.6 TIN COATING
J03585801060GYWIRE COPPER1/0.6 TIN COATING
J03785801060GYWIRE COPPER1/0.6 TIN COATING
J03885801060GYWIRE COPPER1/0.6 TIN COATING
J03985801060GYWIRE COPPER1/0.6 TIN COATING
J04085801060GYWIRE COPPER1/0.6 TIN COATING
J04185801060GYWIRE COPPER1/0.6 TIN COATING
J04385801060GYWIRE COPPER1/0.6 TIN COATING
J04485801060GYWIRE COPPER1/0.6 TIN COATING
J04585801060GYWIRE COPPER1/0.6 TIN COATING
J04685801060GYWIRE COPPER1/0.6 TIN COATING
J04785801060GYWIRE COPPER1/0.6 TIN COATING
J04885801060GYWIRE COPPER1/0.6 TIN COATING
J04985801060GYWIRE COPPER1/0.6 TIN COATING
J05085801060GYWIRE COPPER1/0.6 TIN COATING
J05185801060GYWIRE COPPER1/0.6 TIN COATING
J05285801060GYWIRE COPPER1/0.6 TIN COATING
J05385801060GYWIRE COPPER1/0.6 TIN COATING
J05485801060GYWIRE COPPER1/0.6 TIN COATING
J05585801060GYWIRE COPPER1/0.6 TIN COATING
J05685801060GYWIRE COPPER1/0.6 TIN COATING
J05785801060GYWIRE COPPER1/0.6 TIN COATING
J05885801060GYWIRE COPPER1/0.6 TIN COATING
J05985801060GYWIRE COPPER1/0.6 TIN COATING
J06185801060GYWIRE COPPER1/0.6 TIN COATING
J06285801060GYWIRE COPPER1/0.6 TIN COATING
J06385801060GYWIRE COPPER1/0.6 TIN COATING
J06585801060GYWIRE COPPER1/0.6 TIN COATING
J06685801060GYWIRE COPPER1/0.6 TIN COATING
J06785801060GYWIRE COPPER1/0.6 TIN COATING
J06885801060GYWIRE COPPER1/0.6 TIN COATING
J06985801060GYWIRE COPPER1/0.6 TIN COATING
J07085801060GYWIRE COPPER1/0.6 TIN COATING
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CP-520V Service Manual
z_locz_parts_codeparts_nameparts_descrremark
z_locz_parts_codeparts_nameparts_descrremark
J07185801060GYWIRE COPPER1/0.6 TIN COATING
J07285801060GYWIRE COPPER1/0.6 TIN COATING
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