SystemTF : PAL - B/G for West Europe, NTSC-3.58 / 4.43 (Play back)
TA : PAL - B/G, SECAM-L/L’ for France, NTSC-3.58 / 4.43 (Play back)
TU : PAL- I for U.K, NTSC-3.58 / 4.43 (Play back)
TK : PAL/SECAM - B/G, D/K, NTSC-3.58/4.43(play back) for East Europe & CIS
Main Voltage230V AC, 50Hz
Power ConsumptionStand-by mode : 10 Watts
Normal operating mode : 25” = 75 Watts
28” = 75 Watts
Sound output5 + 5 Watts, 10 % THD at RF 60 % mod. (1 )
Speaker12W 4 ohm x 2 EA
Antenna75 ohm unbalanced input
Impedance
Tuning systemVS( voltage synthesis ) tuning
Tuner3303KHC (TF, TA, TK, TI Model)
BAND I : CH2 - CH4
BAND III : CH5 - CH12
CABLE BAND : S1’ - S3’ , S1 - S20
HYPER BAND : S21 - S41
BAND IV, V : CH21 - CH69
DT2-IV17D (TU Model )
BAND IV, V : CH21 - CH69
Number of 70 programs
program
Aux. Terminal21 pin EURO-SCART jack ( AV input, TV output, RGB input )
21 pin EURO-SCART jack ( AV input, S-VHS input )
RCA type AV input jack
Headphone jack (3.5 mm )
Remote controllerR-28B03 or R-35D05 with 2 “AA” type batteries
Teletext8 pages memory TOP & FLOF
- West option :English, German/Dutch/Flemish, French, Italian,
Spanish/Portuguese, Swedish/Finnish/Danish, Czech/Slovak
- East option : Polish, Czech/Slovak, Rumanian, Hungarian, Servo-croat,
German/Dutch/Flemish, French, Italian
- Cyrillic option: Russian, Lettish/Lithuanian, Estonian, Ukranian,
Czech/Slovak, Servo-croat, English
OSD language-East,West,Turkish Version : English,French,German,Italian,Spanish
-Cyrillic Version : Russian, English, German
1
Page 3
21 PIN EURO-SCART
PINSignal DesignationMatching Value
1Audio Out(linked with 3)0.5Vrms,lmp<1(RF 60% MOD)
2Audio In(linked with 6)0.5Vrms,lmp>10
3Audio Out(linked with 1)0.5Vrms,lmp<1(RF 60% MOD)
4Audio Earth
5Blue Earth
6Audio in (linked with 2)0.5Vrms,lmp>10
7Blue in0.7Vpp 3 ,lmp75
8Slow(Function) SwitchingTV:0-2V,PERI:9.5-12V,lmp>10
9Green Earth
10NC
11Green In0.7Vpp 3 ,lmp75
12NC
13Red Earth
14NC
15Red In, C In0.7Vpp 3 ,lmp75
16Rapid(Blanking) switchingLogic 0:0-0.4V,Logic 1:1-3V,Imp 75
17Video Earth
18Rapid Blanking Earth
19Video Out1Vpp 3 ,lmp75
20Video In, Y In1Vpp 3 ,lmp75
21Common Earth
2018161412108642
21191715131197531
2
Page 4
Safety Instruction
WARNING: Only competent service personnel may carry out work involving the testing or repair of
this equipment.
X-RAY RADIATION PRECAUTION
1. Excessive high voltage can produce potentially
hazardous X-RAY RADIATION.To avoid such
hazards, the high voltage must not exceed the
specified limit. The nominal value of the high
voltage of this receiver is 26at max beam
current. The high voltage must not, under any
circumstances, exceed 29.5(25"), 30(28").
Each time a receiver requires servicing, the high
voltage should be checked. It is important to use
an accurate and reliable high voltage meter.
SAFETY PRECAUTION
1. Potentials of high voltage are present when this
receiver is operating. Operation of the receiver
outside the cabinet or with the back board
removed involves a shock hazard from the
receiver.
1) Servicing should not be attempted by anyone
who is not thoroughly familiar with the
precautions necessary when working on highvoltage equipment.
2) Discharge the high potential of the picture tube
before handling the tube. The picture tube is
highly evacuated and if broken, glass
fragments will be violently expelled.
2. The only source of X-RAY Radiation in this TV
receiver is the picture tube.For continued X-RAY
RADIATION protection,the replacement tube
must be exactly the same type tube as specified
in the parts list.
2. If any Fuse in this TV receiver is blown, replace it
with the FUSE specified in the Replacement
Parts List.
3. When replacing a high wattage resistor(oxide
metal film resistor)in circuit board, keep the
resistor 10mm away from circuit board.
4. Keep wires away from high voltage or high
temperature components.
5. This receiver must operate under AC230 volts,
50Hz. NEVER connect to DC supply or any other
power or frequency.
PRODUCT SAFETY NOTICE
Many electrical and mechanical parts in this have
special safety-related characteristics. These
characteristics are often passed unnoticed by a
visual inspection and the X-RAY RADIATION
protection afforded by them cannot necessarily be
obtained by using replacement components rated
for higher voltage,wattage,etc. Replacement parts
which have these special safety characteristics are
identified in this manual and its supplements,
electrical components having such features are
identified by designated symbol on the parts list.
Before replacing any of these components, read the
parts list in this manual carefully. The use of
substitute replacement parts which do not have the
same safety characteristics as specified in the parts
list may create X-RAY Radiation.
3
Page 5
Alignment Instructions
1. AFT
1.1 Standard B/G,D/K,I and L
1) Set a Signal Generator with
- RF FREQUENCY = 38.9 MHz,
- RF OUTPUT LEVEL = 80 5 dBuV
- System = PAL / SECAM - B/G, D/K, I
2) Connect the Signal Generator RF Output to P101 (Tuner IF Output).
There must be no signal input to the tuner.
3) Press the “AFT” KEY and wait until the TV screen display “AFT OK”.
1.2 Standard SECAM-L’ (France VHF-Low)
Above mentioned “1.1” adjustment has to be done in advance.
1) Set a Signal Generator with
- RF FREQUENCY = 34.5 MHz,
- RF OUTPUT LEVEL = 80 5 dBuV
- System = SECAM - L’
2) Connect the Signal Generator RF Output to P101 (Tuner IF Output).
There must be no signal input to the tuner.
3) Press the “L’ AFT” KEY and wait until the TV screen display “L AFT OK”.
2. AGC
1) Set a Pattern Generator with RF LEVEL 63 2 dBuV .
2) Connect a OSCILLOSCOPE PROBE to P101 (TUNER AGC INPUT).
3) Adjust AGC UP/DOWN KEY the voltage drop 1V dc over below its maximum voltage.
Alternative Method
1) Set a Pattern Generator with
- RF LEVEL 80 5 dBuV
- PAL CROSSHATCH
( without SOUND CARRIER )
2) Connect a OSCILLOSCOPE
( Bandwidth 100MHz ) PROBE
to P101 (TUNER IF OUTPUT).
3) Use AGC UP/DOWN KEY to obtain
an envelop amplitude 200 + 50 mVp-p.
3. SCREEN
1) Apply a COLOR BAR pattern signal.
2) Set the CONTRAST, BRIGHTNESS Black level
to MAX, COLOR to MIN.
3) Set the R,G,B LEVEL to CENTER (31/63) 140 5Vdc
with R,G,B UP/DOWN KEY.
4) Connect a OSCILLOSCOPE PROBE
to P906 ( CRT CATHOD R, G, B ).
5) Adjust the SCREEN VOLUME on FBT
such that the highest black level voltage GND
140 5Vdc.
5
Page 6
4. WHITE BALANCE
1) Set the TV to NOR I mode.
2) Set the R,G,B LEVEL to CENTER with R,G,B UP/DOWN KEY .
3) Adjust the R,G,B UP/DOWN KEY of the other color which did not appear
on the screen to obtain WHITE.
5. FOCUS
1) Apply a RETMA PATTERN signal.
2) Adjust the FOCUS VOLUME on FBT to obtain optimal resolution.
6. GEOMETRY
6.1 VERTICAL CENTER
1) Set the TV to NOR I mode.
2) Pressing the V-SIZE UP/DOWN KEY, the
lower half of the screen is blanked.
3) Adjust the border line of blanked picture
coincident with the mechanical center marks
of the CRT using the V-SIZE UP/DOWN KEY.
6.2 VERTICAL SIZE
The VERTICAL CENTER adjustment
has to be done in advance.
1) Apply a RETMA PATTERN signal.
2) Set the TV to NOR I mode.
3) Adjust the upper part of the picture
with the V-SIZE UP/DOWN keys.
6.3 VERTICAL SLOPE
The VERTICAL SIZE adjustment
has to be done in advance.
1) Apply a RETMA PATTERN signal.
2) Adjust the lower part of the picture
with the V-SLOPE UP/DOWN keys.
6.4 VERTICAL S-CORRECTION
1) Apply a CROSSHATCH PATTERN signal.
2) Adjust the S-COR UP/DOWN KEY to obtain
the same distance between horizontal lines.
6.5 HORIZONTAL CENTER
1) Apply a RETMA PATTERN signal.
2) Adjust picture centering with CENTER
LEFT/RIGHT keys.
6
Page 7
7. EW
7.1 WIDTH
1) Apply a RETMA PATTERN signal.
2) Pressing the EW KEY, the WIDTH OSD appear in the screen.
3) Adjust the over to make a perfect circle with VOL-UP/DOWN KEY.
7.2 PARA
1) Apply a CROSSHATCH PATTERN signal.
2) Pressing the EW KEY, the PARA OSD appear in the screen.
3) Adjust the vertical line to straight with VOL-UP/DOWN KEY.
7.3 CORNER
1) Apply a CROSSHATCH PATTERN signal.
2) Pressing the EW KEY, the CORNER OSD appear in the screen.
3) Adjust the vertical line to straight with VOL-UP/DOWN KEY.
7.4 TRAPI
1) Apply a CROSSHATCH PATTERN signal.
2) Pressing the EW KEY, the TRAPI OSD appear in the screen.
3) Adjust the vertical line to straight with VOL-UP/DOWN KEY.
7
Page 8
If EEPROM (I702) has been changed ;
- Option data has to be changed and
- all alignment function has to be readjusted .
The initial state of adjustment are as follows;Service Remocon
The TDA5255 contains a slicer for VPS and TTX, an accelerating acquisition hardware module, a display
generator for “LEVEL 1” TTX data and a 8 bit u-controller running at 333 nsec cycle time.
The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX
acquisition , transfers data to/from the external memory interface and receives/transmits data via I2C and
UART user interfaces.
The Slicer combined with dedicated hardware stores TTX data in a VBI 1Kbyte buffer.
The u-controller firmware does the total acquisition task ( hamming- and parity -checks,
page search and evaluation of header control bits) once per field.
(2) Feature
•
Acquisition:
- feature selection via special function register
- simultaneous reception of TTX and VPS
- fixed framing code for VPS and TTX
- programmable framing code window for TTX
- Acquisition during VBI
- direct access to VBI RAM buffer
- Acquisition of packets x/26, x/27, 8/30 (firmware)
- assistance of all relevant checks (firmware)
- 1-bit framing-code error tolerance (switchable)
•
. Display:
- features selectable via special function register
- 50/60 Hz display
- level 1 serial attribute display pages
- blanking and contrast reduction output
- 8 direct addressable display pages
- 12 x 10 character matrix
- 96 character ROM (standard G0 character set)
- 143 national option characters for 11 languages
- 288 characters for X/26 display
- 64 block mosaic graphic characters
- 32 free addressable characters for OSD in expanded character ROM + 32 inside OSD box
- double height (TOP/BOTTOM)
- conceal/reveal
- transparent foreground/background -inside/outside of a box
- cursor (colour changes from foreground to background colour)
- flash (flash rate 1s)
- programmable horizontal und vertical sync delay
- hardware assisted fast display page erase
- full screen background colour in outer screen
•
Synchronization:
display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with startstop-oscillator or
display synchronization to sandcastle or Horizontal Sync and Vertical Sync with external clock
independent clock systems for acquisition, display and controller
•
Controller:
- 8 bit configuration
- 18 MHz internal clock
- 0.33 us instruction cycle
- eight 16-bit data pointer registers (DPTR)
10
Page 11
- two 16-bit timers
- watchdog timer
- serial interface (UART)
- 256 bytes on-chip RAM
- 1 Kbyte on-chip extended RAM (access via MOVX)
- 8 Kbyte on-chip ACQ-buffer-RAM (access via MOVX)
- 6 channel 8-bit pulse width modulation unit
- 2 channel 14-bit pulse width modulation unit
- 4 multiplexed ADC inputs with 8-bit resolution
- one 8-bit I/O port with open drain output and optional I2C emulation
- two 8-bit multifunctional I/O ports
- one 4-bit port working as digital or analog inputs
- one 2-bit I/O port with optional address latch enable function
•
P-SDIP 52 package
•
5 V supply voltage
(3) Block Diagram
11
Page 12
PinNameSymbolDescription
1P3.1SYSSECAM-L’ OUT for switching SAW filter L9461
- SECAM-L’ : H
- SECAM- L : L
2P0.7/Open DrainBUSSTOPI2C BUS STOP IN for Computer controlled
alignment in Factory ( Active Low )
3P0.6/Open DrainSDASerial data IN/OUT for I2C
4P0.5/Open DrainSCLSerial clock IN/OUT for I2C
5P0.4/Open DrainOPTION#5 #6 Teletext
6P0.3/Open DrainOPTIONH H West Teletext
L H East Teletext
H L Turkish Teletext
7P0.2/Open DrainOPTION#7 #8 #17 Tuning / Sound System
8P0.1/Open DrainOPTIONL H H B/G (2-G, NICAM)
H H H B/G, D/K (2-C, NICAM)
L L H I/I (NICAM)
H L H I (UHF only, NICAM)
H H L L/L’ B/G (2-C, NICAM)
L H L B/G L/L’ (2-C, NICAM)
9P0.0/Open DrainLEDLED drive OUT
- Stand-by mode : H
- Operating mode : L
( IR reception : pulse )
10VSSVSSground
11VCCVCCPower Supply
12XTAL1OSCINInput to inverting osc. Amplifier
13XTAL2OSCOUTOutput of inverting osc. Amplifier
14P4.0/ALENot Used
15RESETRSTRESET IN (ACTIVE LOW)
16P1.7/14BIT PWMVTTUNING VOLTAGE OUT
17P1.6/14BIT PWMOPTIONTUNING SYSTEM
18P1.5/14BIT PWMF/SWF/SW IDENT IN for stopping OSD
display in RGB mode
- H : TV /AV mode
- L : RGB mode
19P1.4/14BIT PWMOPTIONATS OPTION H : ON
L : OFF
20P1.3/14BIT PWMMUTEAUDIO MUTE OUT
21P1.2/14BIT PWMGNDGND
22P1.1/8BIT PWMNot Used
23P1.0/8BIT PWMNot Used
12
Page 13
PinNameSymbolDescription
24VSSAVSSAAnalog GND for Slicer
25FIL3FIL3PLL Loop Filter I/O for Phase Shifting
26FIL2FIL2PLL Loop Filter I/O for TTX Slicing
27FIL1FIL1PLL Loop Filter I/O for VPS Slicing
28VCCAVCCAAnalog Supply for Slicer
29IREFIREFReference Current for Slicer PLLs
30CVBS CVBS CVBS IN
31P2.3/8 bit ADCNot Used
32P2.2/8 bit ADCAGCIF AGC INPUT for Auto Tuning System
33P2.1/8 bit ADCKSLocal KEY SCAN IN
34P2.0/8 bit ADCS/SWS/SW IDENT IN for Automatic
switching between TV/AV mode
- H : AV / RGB mode
- L : TV mode
35VSS VSS-OSDVSSGround
36P3.3/INT1IRREMOTE IR IN
37VDD VCC-OSDVDDPower Supply
38LCIN OSCIN-OSDLCINCLOCK IN for OSD
39LCOUTLCOUTCLOCK OUT for OSD
40P3.7/TXT I/OBLBAND VHF-L OUT ( Active High )
41P3.6/RXDBHBAND VHF-H OUT ( Active High )
42P3.5/T1BUBAND UHF OUT ( Active High )
43P3.4/T0POWERPOWER CONTROL OUT
44P3.2/INT0Not Used
45HS/SCHSYNCHOR. SYNC. IN (Active High)
46P4.7/VSVSYNCVERT. SYNC. IN (Active High)
47RRRED OUT
48GGGREEN OUT
49BBBLUE OUT
50BLANKBLBLANK OUT
51CORCORNot Used
(CONTRAST REDUCTION OUT)
52P3.0 T1C2/PWM1EVEN/ODDEVEN/ODD OUT for non-interlacing
in TTX mode
13
Page 14
CAT24C08P (E2PROM)
(1) Typical Features
•
IC Bus compatible
•
Low power CMOS Technology
•
16 Byte page write Buffer
•
Self-Timed Write cycle with Auto-Clear
•
100,000 program/Erase cycles
•
100 Year Data Retention
•
Optional High Endurance Device Available
(2) Description
The CAT24C08P is a 8K bit serial CMOS E2PROM internally organized as 1024x8bits.
The CAT 24C08P features a 16 byte page write
buffer.
(3) Block Diagram
EXTERNAL
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
Vcc
Vgg
D OUT
AKC
WORD ADDRESS
BUFFERS
SDA
TEST
SEL
A0
A1
A2
(4) Pin Description
PINSYMBOLDESCRIPTION
1-3A0, A1, A2Device Address lnputs
4VssGround
5SDASerial Data/Address
6SCLSerial Clock
7TESTConnect to Vss
8Vcc+5V Power supply
START/STOP
LOGIC
CONTROL
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
XDEC
64
2
DATE IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
14
Page 15
TDA8375A (Single chip TV Processor for Negative modulation IF )
(1) General Description
The TDA8375A is I2C-bus controlled single chip TV processors which are intended to be applied in PAL/NTSC
television receiver.
The IC is mounted in a S-DIL 56 envelope.
(2) Feature
•
IF
- Vision IF amplifier with high sensitivity and good figures for differential phase and gain
- PLL demodulator with high linearity offering the possibility for (single standard) intercarrier stereo audio application .
- Alignment PLL via I2C
- [TDA8375A] Multistandard IF with negative and positive modulation, switchable via I2C
•
Video
- Integrated luminance delay line
- Integrated chroma trap and bandpass filters (auto calibrated)
- Asymmetrical peaking circuit in the luminance channel
- Black stretching of non standard CVBS or luminance signals
•
Colour
- SECAM interface for application with SECAM add-on TDA8395.
•
RGB
- RGB control (brightness, contrast, saturation)
- Black current stabilization and white point adjustment
•
Input / Output
- Flexible video source select with CVBS input for the internal signal and two external video inputs(one switchable for
CVBS or Y/C).
- The output signal of the video source select is externally available ( also as CVBS when Y/C input is used).
- External audio input.
- Linear RGB input with fast blanking.
•
Synchronization and Deflection
- Horizontal synchronization with two control loops and alignment free horizontal oscillator.
- Slow start and slow stop of the horizontal drive output to enable low stress start-up and switch-off from the line circuit
at nominal line supply voltage.
- Vertical count-down circuit for stable behavior with provisions for non-standard signals.
- Vertical geometry control.
- Vertical drive optimized for DC coupled vertical output stages.
•
Control
- Full I2C bus control, as well for customer controls as for factory alignment.
- All automatic controls have an option for forced mode.
•
Power consumption
- Low power consumption (900 mW at 8.0 Volts).
•
Packaging
- SDIL-56 (Shrinked Dual In Line, 56 pins).
15
Page 16
(3) Block Diagram
16
Page 17
NoNameDescription
1SOUND IF INPUTnot used.
2EXT AUDIO INPUTnot used.
3VCO REF FILTERThe IF VCO tuned circuit is applied to these pin.
4Its resonance frequency must be two times the IF-frequency and in between a
range of 64-120MHz.
This range is suitable for the IF standards as 33.4, 38.9, 45.75 and 58.75MHz.
The VCO frequency can be adjusted by I2C bus so a fixed coil can be used.
5PLL LOOP FILTERThe PLL loopfilter is a first order filter with R=390 ohm and C = 100nF in
series to ground.
The loopfilter bandwidth is 60kHz and is optimal for both fast catching and
sufficient video suppression for optimal sound performance.
Sound performance can theoretically be improved by adding a small
capacitor (approx.0- 4.7nF) between pin 5 and ground.
This however must be evaluated further because the normal video signal
response should not be effected.
6IF VIDEO OUTPUTAlthough the video output impedance is low it is recommended to avoid
high frequency current in the output due to for instance sound trap filters.
This can be achieved by means of an emitter follower at the video output with
a 1resistor in series with the base.
7BUS INPUT : SCLSerial clock line
8BUS INPUT : SDASerial data line
9BANDGAP The bandgap circuit provides a very stable and temperature independent
DECOUPLINGreference voltage.
This reference voltage (6.7V) ensures optimal performance of the TDA8375
and is used in almost all functional circuit blocks.
10CHROMA INPUTThe supplied C S-VHS input burst amplitude should be nominally 300mVpp
(assumed is a colour bar signal with 75% saturation and with chroma/burst
ratio of 2.2/1 ). The C S-VHS input is internally clamped to 4V via 50 .
The external AC coupling capacitor with 50forms a high pass filter.
A recommended coupling capacitor is 1 nF; the high pass filter cut off
frequency is then approximately 3KHz.
11Y/CVBS INPUTThe Y S-VHS signal of 1Vpp ( inclusive sync amplitude) is AC coupled to pin11.
12MAINThe TDA8375 has a main supply pin 12 and a horizontal supply pin 37. Both
37POSITIVE SUPPLYpins have to be supplied simultaneously.
Notice that the IC has not been designed to use this pin 37 as start pin.
(pin 37 supplies the horizontal oscillator, PHI-1 and PHl-2)
(pin 12 supplies the rest of the circuits in the IC)
The nominal supply voltage is 8V. With min/max values of 7.2-8.8V.
Also in stand-by condition the IC must be supplied with 8V.
A voltage detection circuit is connected to both pins.
- pin12 if V12 <6.8V than a power on reset, POR, is generated. The Hout
output is disabled immediate.
- pin37 if V37 <5.8V than the horizontal output is disabled immediate.
17
Page 18
NoNameDescription
13INT CVBS INPUTIt is recommended that the CVBS1 int and CVBS2 ext input amplitudes are
17EXT CVBS INPUT1 Vpp (inclusive sync amplitude).
This, because the noise detector switches the 1 loop to slow mode
(i.e. auto 1mode when FOA, FOB = 0,0) when noise level exceeds
100mVrms (i.e. at S/N of 20dB).
14GROUNDAll internal circuits are connected to this ground pin 14.
15AUDIO OUTPUTnot used.
16DECOUPLING Voltage variations at pin 16, which can be due to external leakage current or
FILTER TUNINGcrosstalk from interference sources, should be less than 50mV to ensure that
tuning of filters/delay cells remains correct.
18BLACK CURRENT For correct operation of the loop CURRENT information is supplied to the
INPUTblack current input pin.
19BLUE OUTPUT The RGB outputs are supplied to the video output stages from pins 21, 20
20GREEN OUTPUTand 19 respectively.
21RED OUTPUTFor nominal signals (i.e. CVBS/S-VHS, -(R-Y)/- (R-Y), TXT inputs) and for
nominal control settings, then the RGB output Signal amplitudes is
typically 2VBLACK_WHITE.
22V-GUARD INPUT/Vertical Guard
BEAM CURRENT With this function, the correct working of the vertical deflection can be
LIMITERmonitored. If the vertical deflection fails, the RGB outputs are blanked to
prevent damage to the picture tube.
Beam current limitinq
The beam current limiting function is realised by reducing the contrast (and
finally the brightness) when the beam current reaches s too high level. The
circuit falls apart in two functions:
- Average beam current limiting (ABL): reacting on the average content of
the picture
- Peak white limiting (PWL): reacting on high local peaks in the RGB signal.
23RED INPUTThe Rin, Gin, Bin input signals (nominal signal amplitude of 700mV) are
24GREEN INPUTAC coupled to pin 23, 24 and 25 respectively.
25BLUE INPUTClamping action occurs during burstkey period.
26RGB INSERTIONThe table below a survey is given of the three modes which can be selected
SWITCH INPUTwith a voltage on RGB insertion switch input pin ;
Vpin26 I2C function Selected RGB signal
0.9V-3V IE1=0 RGB(internal)
IE1=1 Rin,Gin,Bin
(fast insertion on pin23,24,25)
> 4V IE1=X OSD can be inserted at the RGBout pins
27LUMINANCE INPUTAn nominal input signal amplitude of 1 Vblack-white MUST be DC coupled
to the luminance input pin 27.
The pin is internally AC coupled to the luminance clamp via a capacitor of
50pF; clamping action occurs during burstkey period.
28LUMINANCE The luminance output signal is approximately l V black-white with typical
OUTPUToutput impedance of 25O ohm.
18
Page 19
NoNameDescription
29B-Y OUTPUTThe maximum output impedance of pins 29 and 30 is 500when PAL/NTSC
30R-Y OUTPUTsignals are identified. When SECAM is identified by the SECAM add-on and
no PAL/NTSC is already identified by the ASM, then the ASM sets the
-(B-Y)/-(R-Y) output switch open (via DEMSW).
This enables the -(B-Y)/-(R-Y) outputs of the TDA8395 to be directly connected
to pins 29 and 3O respectively.
31B-Y INPUTThe -(B-Y),-(R-Y) output signals (supplied from baseband delay line) are AC
32R-Y INPUTcoupled, via a coupling capacitor of 10nF or greater, to the -(B-Y)/-(R-Y) inputs;
both inputs are clamped during burstkey period.
33SECAM REFThe SECAM reference output is directly connected to pin l of the TDA8395 for
OUTPUTSECAM decoding ; it also can be used as a reference for comb filter applications.
- sync calibration internal circuits,
it is only allowed to have 3.6MHz Xtals on pin34: both 4.4MHz,3.6MHz Xtals
are allowed on pin 35.
If pin 35 is not used: then it is left open in application (also XA,XB=O,1 ).
36LOOP FILTER One of the important aspects of the PLL is the 1oop filter connected to pin 36;
BURST PHASEit influences the dynamic performance of the loop.
DETECTOR
38CVBS OUTPUTThe output amplitude is 1Vpp (transfer gain ratio between CVBS1int or
CVBS2ext or CVBS3ext/Ys-vhs and CVBSout is 1).
The maximum output impedance is 250 ohm.
39BLACK PEAKFor the correct working of the black stretcher an external time constant should
HOLD CAPACITORbe added at the black peak hold capacitor input.
40HOR OUTPUTThis open collector output is meant to drive the horizontal output stage.
The output is active low, i.e. the line transistor should conduct during the low
period of the output.
41SANDCASTLE Pin 41 is a combined input/output pin.
OUTPUT/The pin provides a three level sandcastle pulse.
FLYBACK INPUTBoth burstkey pulse and vertical blanking pulse are always available, the line
blanking pulse is only present when the external flyback pulse is fed to this pin.
The line flyback pulse, fed to this pin is used for two functions:
- input signal for the PHI-2 1oop and
- RGB line blanking. (without flyback pulse blanking occurs only during the
burstkey pulse)
To ensure correct working of the delay line and SECAM add-on, the output
should not be loaded with more than:
- Sandcastle input delay line TDA 4665
- Sandcastle input SECAM add-on TDA 8395
42PHI-2 FILTER /The loopfilter is a first order filter.
FLASH PROTECTThis pin requires a capacitor (C) only.
A flash protection becomes active when this pin is forced >6V. The horizontal
drive is switched-off immediately.
Once the voltage is <6V the horizontal drive is switched-on again via the slow
start procedure.
19
Page 20
NoNameDescription
43PHI-1 FILTERThe loopfilter connected to pin 43 is suitable for various signal conditions as
strong/weak and VCR signal.
This is achieved by switching of the loopfilter time constant by changing the
PHI-1 output current.
Via I2C bus FOA/B, different time constants can be chosen, including an
automatic mode which gives optimal performance under varying conditions.
44GROUNDTo this pin are connected the IC-substrate and horizontal output.
45EAST-WEST DRIVEThe EW drive is a current output.
The output is single-ended and is fed directly to the EW-input terminal
46VERT DRIVE +The vertical drive has a current output. The output is balanced which ensures
47VERT DRIVE -a good common mode behavior with temperature and makes the output signal
less sensitive for disturbances.
48IF INPUTThe PLL frequency range is 32-60MHz with corresponding VCO frequency
4964-120MHz.
The IF input impedances is 2in parallel with 3pF and matches the required
load for commonly used SAW filters.
A DC coupling is allowed, so no series capacitors between SAW filter and IF
input are necessary.
50EHT/OVERVOLTAGEThe input range for EHT tracking is 1.2 ~ 2.8V, for a compensation of +/- 5%
PROTECT INPUTon vertical and/or EW.
The tracking on EW can be switched on/off by HCO.
The overvoltage protection is activated when the voltage on pin 50 exceeds
3.9V typical.
51VERTThis pin requires a capacitor to ground of l00nF +/- 5%.
SAWTOOTH The optimal sawtooth amplitude is 3.5V and is determined by the external
CAPACITORcapacitor and charge current.
The sawtooth bottom-level is 2V.
52REFERENCEThis pin requires a resistor to ground.
CURRENT INPUTThe optimal reference current is 100 . which is determined by this resistor.
53AGC The AGC capacitor value is 2.2and has been defined for an optimal
DECOUPLINGcompromise between AGC speed and tilt for all AGC modes
CAPACITOR(negative/positive modulation).
54TUNER AGCThis output is used to control (reduce) the tuner gain for strong RF signals.
OUTPUTThe tuner AGC is an open collector output which is acting as a variable
current source to ground.
55AUDIO not used.
DEEMPHASSIS
56DECOUPLINGThis pin requires a capacitor of 10connected to ground.
SOUND The pin acts as a low pass filter needed for the DC feedback loop.
DEMODULATOR
20
Page 21
TDA4665(Base Band Delay Line)
(1) Features
• Two comb filters, using the switched-capacitor technique,for one line delay time (64µs)
• Adjustment free application
• No crosstalk between SECAM colour carriers
• Handles negative or positive colour-difference input signals
• Clamping of AC-coupled input signals(±(R-Y)and±(B-Y))
• VCO without external components
• 3MHz internal clock signal derived from a 6MHz VCO, line-locked by the sandcastle pulse (64µs line)
• Sample-and -hold circuits and low-pass filters to suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference signals to suppress cross-colour
(2) General Description
The TDA4661 is an integrated baseband delay line circuit with one line delay. It is suitable for decoders
with colour-difference signal outputs±(R-Y)and±(B-Y).
(3)Block Diagram
(4) Pin Description
SYMBOL PINDESCRIPTION
Vp21+5V supply voltage for digital part
n.c.2not connected
GND23ground for digital part (0V)
i.c.4internally connected
SAND5sandcastle pulse input
n.c.6not connected
i.c.7internally connected
i.c.8internally connected
SYMBOL PINDESCRIPTION
Vp19+5V supply voltage for analog part
GND110ground for analog part (0V)
V0 (R-Y)11± (R-Y) output signal
V0 (B-Y)12± (B-Y) output signal
n.c.13not connected
V1 (B-Y)14± (B-Y) input signal
n.c.15not connected
1 (R-Y)16± (R-Y) input signal
V
21
Page 22
TDA8395 (Secam Decoder)
(1) Features
Fully integrated filters
Alignment free
For use with baseband delay
(2) Description
The TDA8395 is a self-calibrating,fully integrated SECAM decoder. The IC should preferably be used
in conjunction with the PAL/NTSC decoder TDA8362 and with the switch capacitor baseband delay
circuit TDA4665. The IC incorporates HF and LF filters, a demodulator and an identification circuit
(Iuminance is not processed in this IC).
A highly stable reference frequency is required for calibration and a two-level sandcastle pulse for
blanking and burst gating.
(3) Block Diagram
refPLLrefGND
CLOCHE
100 nF
78362
220 nF
TEST
p
V
BANDGAPTUNINGTUNING
CVBS
16
ACC
INTERFACE
115
f
ref/IDENT
CLOCHE
FILTER
CONTROL
SAND
PLL
IDENT-
IFICATION
(4) Pin Description
SYMBOLPINDESCRIPTION
fp1/IDENT1reference frequency input/identification input
TEST2test output
Vp3positive supply voltage
n.c.4not connected
n.c.5not connected
GND6ground
CLOCHEref7Cloche reference filter
PLL ref8PLL reference
The TDA6106Q is a monolithic video output amplifier (5MHz bandwidth) in a SIL 9 MPpackage, using high-voltage
DMOS technology, and is intended to drive the cathode of CRT directly .
To obtain maximum performance, the amplifier should be used with black-current control.
(2) Feature
•
Black - current measurement output for automatic black current stabilization (ABS)
•
Single supply voltage of 200V
•
Internal protection against positive appearing CRT flash-over discharge
The TDA8351 is power circuit for use in 90 and 110 color deflection systems for field frequencies of 50 to 120 Hz.
The circuit provides a DC driven vertical deflection output circuit, operating as a high efficient class G system.
(2) Feature
•
High efficient fully DC-coupled vertical output bridge circuit
•
Vertical fly-back switch
•
Guard circuit
•
Protection against : - short circuit of the output pins (7 and 4)
- short circuit of the output pins to Vp
•
Temperature (thermal) protection
•
High EMC immunity because of common mode inputs
•
A guard signal in zoom mode.
(3) Block Diagram
(4) Pin Description
PINSYMBOLDESCRIPTION
1I drive (pos)input power stage (positive); include Ii(sb) signal bias
2I drive (neg)input power stage (negative); include Ii(sb) signal bias
3V poperating supply voltage
4V o(b)output voltage B
5GNDground
6V fbinput fly-back supply voltage
7V o(a)output voltage A
8V o(guard)guard output voltage (Not used)
9V I(fb)input feedback voltage
24
Page 25
STR-S5707 (Hybrid IC for a Switching Regulator)
(1) General Description
The STR-S5707 is a Hybrid IC with a built in power transistor and a separate excitation control IC,
designed for converter type switching mode power supply applications.
The IC is capable of quasi-resonant mode and requires small number of external component.
(2) Feature
•
Small SIP isolated package : Resin sealed type (transfer mold)
•
Lower power dissipation at a lighter load
•
Many protection function : - Pulse-by-pulse over current protection
- Over-voltage protection with a latch
- Thermal protection with a latch
•
These protection functions are incorporated and can be latched with an external signal.
(3) Block Diagram
(4) Pin Description
PINNAMESYMBOLDESCRIPTION
1CollectorCCollector of power Tr
2GroundGNDground (Emitter of power Tr)
3BaseBBase of power Tr
4SinkSINKBase current (IS) input
5Over-current OCPover-current sensing signal input
protection
6InhibitINHinput for synchronizing OFF time
Latchand latch circuit operation
7SensingSENSconstant voltage control signal input
8DriveDRIVEBase drive current (ID) output
9VinVINsupply voltage for control circuit
25
Page 26
Electrical Characteristics of Control Part (Ta=25 )
DescriptionTerminalSymbolRatingUnit
MINTYPMAX
On-state Voltage9-2V
Off-state Voltage9-2V
Operating Circuit Current9-2I
Stand-by Circuit Current9-2I
On TimeT
Off TimeT
OCP terminal Threshold Voltage6-2V
INH terminal Threshold Voltage 18-2V
INH terminal Threshold Voltage 2 8-2V
INH terminal Threshold Voltage 38-2V
OVP Operating Voltage9-2V
Latch Circuit Sustaining Current9-2I
Latch Circuit Cancellation Voltage9-2V
MIC Thermal ShutdownTj
IN(ON)
IN(OFF)
IN(ON)
IN(OFF)
ON
OFF
OCP
INH-1
INH-2
Latch
IN(OVP)
H
IN(La.OFF)
(TSD)
7.6 88.4V
4.64.95.2V
1528mA
200A
3341
4555
-1.12-1-0.88V
0.650.750.85V
1.42..0V
3.25.15.8V
9.210.7V
500A
2.53.1V
125150
Starting Temp
Fixed Reference Voltage7-2V
S
32.0V
Temperature Coefficient of7-2+2.5mV/
Reference Voltage
Electrical Characteristics of Power Transistor Part(Trl) (Ta=25 )
DescriptionTerminalSymbolRatingUnit
MINTYPMAX
Collector Saturation Voltage1-2V
Collector Cutoff Current1-2I
Base-Emitter saturation voltage3-2V
DC Current Gainh
TDA8138 (5.1V+12V regulator with Disable and Reset)
(1) General Description
The TDA8138 is a monolithic dual positive voltage regulator designed to provide fixed precision output voltages of
5.1V and 12V at currents up to 1A.
A internal reset cuicuit generates a reset pulse when the output 1 decrease below the regulated voltage value.
Output 2 can be disabled by TTL input.
Shot circuit and themal protections are included.
(2) Feature
•
output currents up to 1A
•
ixed precision Output 1 voltage 5.1V 2%
•
fixed precision Output 2 voltage 12V 2%
•
output 1 with Reset facility
•
output 2 with Disable by TTL input
•
short circuit protection at both outputs
•
thermal protection
•
low drop output voltage
(3) Block Diagram (4) Pin Description
PINSYMBOLDESCRIPTION
1V in 1input 1
2V in 2input 2
3C eDelay capacitor
4V disdisable
5GNDground
6RSTreset
7n.c
8V out 2output 2 (12V)
9V out 1output 1 (5.1V)
27
Page 28
TDA1519B (BTL or STEREO audio amplifier)
(1) Features
Requires very few external
components for Bridge Tied Load
(BTL)
Stereo or BTL application
High output power
Low offset voltage at output (important for BTL)
Fixed gain
Good ripple rejection
Mute/stand-by switch
Load dump protection
SC and DC short-circuit-safe to ground and VP
(2) General Description
The TDA1519B is an integrated class-B dual output amplifier in a 9-lead single in-line (SIL) plastic medium
power package. The device is primarily developed for car radio applications.
(3) Block Diagram(4) Pin Description
1
60k
mute switch
C
m
Thermally protected
Reverse polarity safe
Capability to handle high energy on outputs (VP
= 0 V)
No switch-on/switch-off plop
Protected against electrostatic discharge
Identical inputs (inverting and non-inverting)
Compatible with TDA1519A (except output
power)
PIN NAMEDESCRIPTION
1NINVnon-inverting input
2GND1 ground (signal)
3RRsupply voltage ripple
rejection
4OUT1output 1
183
VA
18.1 k
4
power stage
5GND2ground (substrate)
Vp
mute
switch
8
6
mute
reference
voltage
C
m
Vp
+
+
–
+
–
TDA1519B
power stage
stand–by
reference
voltage
power
ground
(substrate)
stand–by
switch
VA
15k
3
183
9
60k
input
reference
voltage
x1
15k
18.1 k
VA
+
mute switch
signal
ground
275
6OUT2output 2
7Vppositive supply voltage
8M/SSmute/stand-by switch
9INVinverting input
28
Page 29
MSP3410 (Multistandard Sound processor for NICAM & 2-Carrier
(1) Features
•
Asingle-chip Multistandard Sound Pressor for applications in analog and digital TV sets
•
TWO selectable analog inputs
•
Automatic Gain control for analog input
•
All demoudlation and filtering is performed on chip and is individually programmable
•
Adjustment of volume, balance, loudness, treble, bass, base width enlargement, pseudo stereo
•
Independent input selection for speaker-out and scart-out
(2) Block Diagram
29
Page 30
(3) Description
• Analog Sound IF - Input Section
The input pins ANA_IN1+, ANA_IN2+ and ANN_IN-offer the possibility to connect two different sound IF sources to
the MSP 3410. By means of bit [8] of AD_CV either terrestrial or satellite sound IF signals can be selected. The analogto-digital conversion of the preselected sound IF signal is done by a flash-converter, whose output can be used to control an analog automatic gain circuit (AGC), providing optimum level for a wide range of input levels. It is possible to
switch between automatic gain control and a fixed (setable) input gain. In the optimum case, the input range of the AD
converter is completely covered by the sound if source. Some combinations of SAW filters and sound IF mixer IC’s
however show large picture components on their outputs. In this case filtering is recommended. It was found, that the
high pass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ are sufficient in most cases.
• Quadrature Mixers
The digital input coming from the integrated A/D converter may contain audio information at a frequency
range of theoretically 0 to 9 MHz corresponding to the selected standards. By means of two
programmable quadrature mixers two different audio sources, for example NICAM and FM-mono, may be
shifted into baseband position. In the following the two main channels are provided to process either:
- NICAM (channel 1) and FM mono (channel 2) simultaneously or alternatively
- FM2 (channel 1) and FM1 (channel2).
Two independent digital oscillators are provided to generate two pairs of sin/cos-functions. Two
programmable increments, to be divided up into Low- and High part, determine frequency of the oscillator,
which corresponds to the frequency of the desired audio carrier.
•
Lowpass Filtering Block for Mixed Sound IF Signals
By means of decimation filters the sampling rate is reduced. Then, data shaping and/or FM bandwidth limitation is
performed by a linear phase Finite Impulse Response (FIR-filter). Just like the oscillators’ increments the filter
coefficients are programmable and are written into the IC by the CCU via the control bus. Thus, for example, different
NICAM versions can easily be implemented. Two not necessarily different sets of coefficients are required, one for
channel 1 (NICAM or FM2) and one for channel 2 (FM1=FM-mono).
Since both MSP channels are designed to process the German FM Stereo System with the same FIR coefficient set
(despite 7 dB power level difference of the two sound carriers), the MSP channel 1 has an internal overall gain of 6
dB. To process two carriers of identical power level these 6 dBs have to be taken into account by decreasing the
values of the channel 1 coefficient set.
•
CORDIC Block
The filtered sound IF signals are demodulated by transforming the incoming signals from Cartesian into polar format
by means of a CORDIC processor block. On the output, the phase and amplitude is available for further processing.
AM signals are derived from the amplitude information whereas the phase information serves for FM and NICAM
(DQPSK) demodulation.
•
Differentiators
FM demodulation is completed by differentiation the phase information output of the CORDIC block.
• Lowpass Filer Block for Demodulated Signals
The demodulated FM and AM signals are further lowpass filtered and decimated to a final sampling
frequency of 32 kHz. The usable bandwidth of the final baseband signals is about 15 kHz.
30
Page 31
• DQPSK-Decoder
In case of NICAM-mode the phase samples are decoded according the DQPSK-Coding scheme. The
output of this block contains the original NICAM-bitstream, which is available at the N-Bus interface.
• NICAM-Decoder
Before any NICAM decoding can start, the MSP must lock to the NICAM frame structure by searching and
synchronizing to the so-called Frame Alignment Words (FAW).
To reconstruct the original digital sound samples the NICAM-bitstream has to be descrambled,
deinterleaved and rescaled. Also bit error detection and correction (concealment) is performed in this
NICAM specific block.
To facilitate the Central Control Unit CCU to switch the TV-set to the actual sound mode, control
information on the NICAM mode and bit error rate are supplied by the the NICAM-Decoder, It can be read
out via the I2C-Bus.
• Analog Section and SCART Switches
The analog input and output sections offer a wide range of switching facilities, which are shown in Fig.
To realize a TV-set with 3 pairs of SCART-inputs and two pairs of SCART-outputs no external switching
hardware is required.
The switches are controlled by the ACB bits defined in the audio processing interface (see chapter
“programming the audio processing part”).
If the MSP 3410 is switched off by first pulling STANDBYQ low and then disconnecting the 5V but keeping
the 8V power supply (‘Standby’-mode), the switches S1, S2 and S3 maintain their position and function.
This facilitates the copy from selected SCART-inputs to SCART-outputs in the TV-sets standby mode.
Fig. SCART-Switching Facilities Bold lines determine the default configuration
31
Page 32
In case of power-on start or starting from standby, the IC switches automatically to the default
configuration, shown in the figure above. This action takes place after the first I2C transmission into the
DFP part. By transmitting the ACB register first, the default setting mode can be changed.
• MSP 3410 Audio Baseband Processing
By means of the DFP processor all audio baseband functions are performed by digital signal processing
(DSP). The DSP functions are grouped into three processing parts: Input preprocessing, channel selection
and channel postprocessing.
The input preprocessing is intended to prepare the various signals of all input sources in order to form a
standardized signal at the input to the channel selector. The signals can be adjusted in volume, are
processed with the appropriate deemphasis and are dematrixed if necessary.
Having prepared the signals that way, the channel selector makes it possible to distribute all possible
source signals to the desired output channels.
Of special importance is the ability to route in an external coprocessor for special effects like graphic
equalizer, surround processing and sound field processing. Routing can be done with each input source
and output channel via the I2S inputs and outputs.
All input and output signals can be processed simultaneously with the exception that FM2 cannot be
processed at the same time as NICAM. Note that the NICAM input signals are only available in the MSP
3410 version. While processing the adaptive deemphasis, no dual carrier stereo (German or Korean) or
NICAM processing is possible. Identification values are not valid either.
• Dual Carrier FM Stereo/Bilingual Detection
In the German and Korean TV standard, audio information can be transmitted in three modes: Mono,
stereo or bilingual. To obtain information about the current audio operation mode, the MSP 3410 detects
the so-called identification signal. Information is supplied via the Stereo Detection Register to an external
CCU.
32
Page 33
(4) Pin Description
PINPIN NAMEDESCRIPTION
1AUD_CL_OUTAudio clock output
2CW_CLPay-TV control clock
3CW_DAPay-TV control data
4D_CTR_OUT1Digital control output 1
5D_CRT_OUT0Digital control output 0
6ADR_SELControl bus address select
7STANDBYQStandby (low-active)
8D_CTR_IN 0For future use
9I
2
C_CLI2C clock
10I2C_DAI2C clock
11I2S_CLI2S clock
12I2S_WSI2S wordstrobe
13I2S_DA_OUTI2S data output
14I2S_DA_INI2S data input
15S_DA_INSBUS data input
16S_IDSBUS ident
17S_CLSBUS clock
18DVSUPDigital power supply +5V
19DVSSDigital ground
20S_DA_OUTSBUS data output (FM/NICAM-test)
21FRAMENBUS frame
22N_CLNBUS clock
23N_DANBUS data
24RESETQPower-on-reset
25DACA_RAnalog output AUX, right
26DACA_LAnalog output AUX, left
27VREF2Reference ground2 high voltage part
28DACM_RAnalog output MAIN, right
29DACM_LAnalog output MAIN, left
30TESTIO2Test pin 2
31C_DACS_RSCART output capacitor to ground
32C_DACS_LSCART output capacitor to ground
33SC2_OUT_RSCART output2, right
34SC2_OUT_LSCART output2, left
35VREF1Reference ground1 high voltage part
36SC1_OUT_RSCART output, right
37SC1_OUT_LSCART output, left
38CAPL_AVolume capacitor AUX
39AHVSUPAnalog power supply 8V
40CAPL_MVolume capacitor MAIN
33
Page 34
PINPIN NAMEDESCRIPTION
41AHVSSAnalog ground
42AGNDCAnalog reference voltage high voltage part
43PDMC1Capacitor to BAGNDI
44PDMC2Capacitor to BAGNDI
45BAGNDIBuffered AGNDC
46SC3_IN_LScart input3 in, left
47SC2_IN_RScart input3 in, right
48ASG2Analog Shield Ground2
49SC2_IN_LScart input2 in, left
50SC2_IN_RScart input2 in, right
51ASG1Analog Shield Ground1
52SC1_IN_LScart input1 in, left
53SC1_IN_RScart input1 in, right
54VREFTOPReference voltage IF A/D converter
55MONO_INMono input
56AVSSAnalog ground
57AVSUPAnalog power supply +5V
58ANA_IN1+IF input1
59ANA_IN1-IF common
60ANA_IN2+IF input (if ANA_IN1+is used only, connect to
AVSS with 50pF Capacitor
61TESTIO1Test pin1
62XTAL_INCrystal oscillator
63XTAL_OUTCrystal oscillator
64DMA_SYNCDMAC-sync: signal
34
Page 35
TDA4445B (Quasi Parallel Sound Processor)
(1) Features
• Very high input sensitivity
• Excellent signal to noise ratio
• Fast averaged AGC
• IF amplifier can be switched off for VTR mode
• Output signal stabilized against supply voltage variations
• Very few external components
• Targeting bistandard applications
• Low AM distortion
(2) General Description
The TDA4445B is quasi parallel sound processor with quadrature intercarrier demodulator.
(3)Block Diagram
(4)Pin Description
PINDESCRIPTION
1, 16IF input
3IF AGC time constant
8, 9Tuned circuit
11Supply voltage
12Sound-IF-output
13Ground
2,4,7,10
14,15
5Average capacitor
6AF output
not be connected
35
Page 36
GMS301 12-R098 (4-bit Single Chip Microcomputer for Remote control)
(1) General Description
The GMS30112-R098 is 4-bit single chip CMOS microcomputer.
(2) Feature
•
program memory : 1024 bytes
•
data memory : 32 x 4 bits
•
43 types of instruction set
•
3 levels of subroutine nesting
•
1 bit output port for a large current (REMOUT signal)
•
operating frequency : 300kHz - 1 MHz
•
instruction cycle : 12.5 usec @ 480kHz
•
CMOS process ( single 3.0 V power supply )
•
stop mode (through internal instruction)
•
released stop mode by key input (masked option)
•
built in capacitor for ceramic oscillation circuit (masked option)
•
built in a watch dog timer(WDT)
•
low operating voltage (2.0 V to 4.0 V)
(3) Block Diagram
36
Page 37
(4) Pin Description
PINSYMBOLDESCRIPTION
1,2,3,4K0,K1,K2,K34 bit input port with built in pull up resistor
5,6,7,8,9,10D0,D1,D2,D3,D4,D510 bit output port which can be set or reset pin
by pin independently.
The output structure is N-channel open drain.
11REMOUTremote control signal output port which has
high current driving capability
12OSC 2oscillator output
13OSC 1oscillator input
14Vdd2-4V power supply
15RESETreset signal input which is a low active
16GNDground
17,18,19,20R0,R1,R2,R34 bit programmable I/O port
37
Page 38
IC DC Voltage charts
Input signal PAL/CH5-Video : 8 step colour bar (87% AM)
Audio : 1 KHz sinewave (60% FM)
User’s control condition Contrast, Brightness, Colour, Volume Controls-max.
Line voltage AC 230V, 50Hz
All the voltage in each point are measured with Multimeter
1. TDA 8375A (I501)
Pin No.
V(DC)
Pin No.
V(DC)
Pin No.
V(DC)
Pin No.
V(DC)
Pin No.
V(DC)
Pin No.
1
0
11
3.5
21
4
31
4
41
0.5
51
2
0
12
8
22
1.9
32
4
42
4.5
52
3
3.6
13
4
23
3.5
33
1.6
43
4
53
4
3.6
14
0
24
3.5
34
2.6
44
0
54
5
2.7
15
3.4
25
3.5
35
2.6
45
0.5
55
6
3.3
16
3.6
26
0.3
36
4.9
46
2.2
56
7
3.7
17
3.5
27
2.8
37
8
47
2.2
8
3.4
18
5.1
28
2.8
38
8
48
4
9
6.6
19
3.8
29
1.8
39
4
49
4
10
4
20
3.9
30
1.8
40
1.5
50
1.7
V(DC)
2. DW 5255S(I701)
Pin No.
V(DC)
Pin No.
V(DC)
Pin No.
V(DC)
3.8
1
0
11
5
21
5
3.9
2
5
12
2.6
22
5
3
3
3.4
13
2.6
23
5
3
4
3.6
14
5
24
0
3.5
5
5
15
5
25
2.6
38
3.8
6
5
16
4.1
26
2.6
7
5
17
0
27
2.6
18
28
8
5
5
5
9
0
19
5
29
1.5
10
0
20
0
30
1.5
Page 39
Pin No.
31
32
33
34
35
36
37
38
39
40
V(DC)
Pin No.
V(DC)
Pin No.
V(DC)
3. TDA 4665 (I503)
Pin No.
V(DC)
Pin No.
V(DC)
0.5
41
0
51
0
1
5
11
2.9
2.5
42
0
52
0
2
0
12
2.9
5
43
4.7
3
0
13
0
0
44
5
4
0
14
1.3
0
45
0.4
5
0.6
15
0
5
46
1.3
6
0
16
1.3
5
47
0
7
0.3
2.7
48
0
8
0
2.8
49
0
9
5
3.2
50
0
10
0
4. TDA 4445B (I603)
Pin No.
V(DC)
Pin No.
V(DC)
5. TDA 4445B (I602)
Pin No.
V(DC)
Pin No.
V(DC)
1
4.5
11
12
1
4.5
11
12
2
0
12
5.3
2
0
12
3.7
3
2.5
13
0
3
2.6
13
0
4
0
14
0
4
0
14
0
5
4
15
0
5
4
15
0
39
6
4
16
4.5
6
4
16
4.5
7
0
7
0
8
4.7
8
4.8
9
4.7
9
4.8
10
0
10
0
Page 40
6. TDA 8395 (I502)
Pin No.
V(DC)
Pin No.
V(DC)
7. TDA 8138 (I802)
Pin No.
V(DC)
8. TDA 8351 (I301)
Pin No.
V(DC)
1
1.6
11
0
1
12
1
2.3
2
1.2
12
0
2
4.5
2
2.3
3
8
13
3
3
3
16
4
0
14
0
0
4
4.5
4
8.3
5
0
15
0.5
5
0
5
0
6
0
16
3.4
6
5
6
4.6
7
3.3
7
0
7
8.3
8
4.3
8
12
8
0.6
9
1.7
9
5
9
7.1
10
1.7
9. TDA 1519B (I601)
Pin No.
V(DC)
10. MSP 3410 (I602)
Pin No.
V(DC)
Pin No.
V(DC)
Pin No.
V(DC)
Pin No.
1
1.9
1
0
11
2.5
21
0
31
2
0
2
0
12
2.5
22
2.5
32
3
6.4
3
0
13
2.5
23
0.5
33
4
6.4
4
0
14
2.5
24
5
34
5
0
5
0
15
2.5
25
0.1
35
6
6.5
6
0
16
4.9
26
0.1
36
7
13.3
7
4.9
17
3.8
27
0
37
8
12.7
8
0
18
4.9
28
1.5
38
9
1.9
9
3.6
19
0
29
1.7
39
10
3.4
20
3.8
30
0
40
V(DC)
3.8
3.8
3.8
3.8
0
40
3.8
3.8
7.1
8
6.2
Page 41
Pin No.
41
42
43
44
45
46
47
48
49
50
V(DC)
Pin No.
V(DC)
Pin No.
V(DC)
0
51
0
61
0
3.7
52
3.8
62
2.5
3.8
53
3.8
63
2.5
3.8
54
2.7
64
0.1
3.8
55
4
3.8
56
0
3.8
57
5
0
58
1.5
3.8
59
1.5
3.8
60
0.1
41
Page 42
Circuit Description
Vision IF amplifier, AFC, video demodulator
The IF signal from the tuner is fed through a SAW filter to the differential IF input (pin 48 and 49).
The first IF stage consists of 3 AC-coupled amplifiers with a total gain control range of over 66 dB.
The reference carrier for the video demodulator is obtained by a PLL carrier regenerator
(eliminating notch filter compromises, as in reference tuned circuits for passive carrier regeneration).
Only an oscillator coil is needed( pin 3 and 4) that can be aligned via l2C-bus to the double IF frequency.
The AFC information is derived from the VCO control voltage of the IF-PLL
and can be read via I2C-bus.
Bit AFB toggles when the picture carrier is exactly at the desired IF frequency (= half the aligned IF-PLL frequency).
AFA is active in a window around this point.
For fast search-tuning applications this window can be increased by a factor 3 (AFW bit).
Tuner A.G.C.
The automatic gain control (A.G.C.) circuit operates on top sync level at negative modulated signals
or on peak white level at positive modulation, selected by MOD bit.
The tuner A.G.C. is controlled via pin 54.
The tuner A.G.C. take over point (T.O.P.) can be set over a wide range: 0.8 mVrms .. 80 mVrms
IF input signal amplitude.
The tuner AGC output may have to operate above Vcc of TDA8375A.
Therefore pin 54 is an open collector output, that can operate from 0.3 up to Vcc+ 1 Volt
(at > 2 mA sink current)
Source select switch
TDA8375A input switch can select one of the following sources ;
pin 13 front-end : CVBS l int
pin17 : CVBS 2 ext
pin 11.pinlO : Y (S-VHS), C (S-VHS)
Selected signal is available at the CVBS output pin 38, in case of Y/C input Y+C are added.
It drive teletext and the TDA8395 SECAM add-on.
For S-VHS applications, the Y,C input can be selected, independent of the CVBS source switch.
TDA8375A Y,C inputs are selected, while the source switch outputs CVBS l int or CVBS 2 ext on CVBS out.
Horizontal synchronization and protection
The synchronization separator adapts its slicing level in the middle between top-sync and black level of the CVBS signal.
The separated synchronization pulses are fed to the first phase detector and to the coincidence detector.
The -1 loop gain is determined by the components at pin 43 (C+RC).
The coincidence detector detects whether the horizontal line oscillator is synchronized to the incoming video.
The line oscillator is a VCO-type, running at twice the line frequency.
It is calibrated with the X-tal oscillator frequency of the colour decoder and has a maximum deviation of 2% of the
nominal frequency, so no alignment is-needed.
Calibration is done at start up( the TDA8375A must first know what colour X-tals are connected, bits XA and XB) and
after synchronization loss ( -1 coincidence detector “Sync Locked” bit SL).
The second phase detector -2 locks the phase of the horizontal driver pulses at output pin 40 to the horizontal
flyback pulse at input pin 41 .
This compensates for the storage time of the horizontal deflection transistor.
The - 2 loop filter (C) is externally connected to pin 42.
The horizontal phase can be given a static off set via I2C-but (HSH “horizontal shift”)
A dynamic correction is possible by current feedback into the - 2 loop filter capacitor.
To protect the horizontal deflection transistor, the ho rizontal drive is switched off immediately when a power
42
Page 43
failure ( “ Power-On Reset “ bit POR ) is detected.
The power failure may have corrupted the contents of the internal data registers, so the TDA8375A should be
started up again.
The TDA8375A has a separate supply input (pin 37) that only used as a clean supply voltage for thehorizontal
oscillator circuits.
V ertical synchronization
The vertical sawtooth generator drives the vertical output.
It uses an external capacitor at pin 51 and a current reference resistor at pin 52.
The TDA8375A vertical drive has differential current outputs for DC-coupled vertical output stage, like the TDA8351 .
At TDA8351 input pins l and 2 this current is converted into a drive voltage via a resistor.
Geometry processing
With the TDA8375A is possible to implement automatic geometry alignment, because all parameters are adjusted
via the I2C bus.
The deflection processor of the TDA8375A offers the following five controls;
- Horizontal shift
- Vertical slope.
- Vertical amplitude
- Vertical S-correction
- vertical shift
Colour decoder
The colour decoder contains an alignment-free X-tal oscillator, a dual killer circuit and colour difference demodulators.
Together with the TDA8395 SECAM add-on a multi standard PAL/SECAM/NTSC decoder can be built with
automatic recognition.
Which standard can be decoded depends on the external Xtals used.
Two Xtal pins (34and 36) are present so normally no external switching is required.
The I.C. must be told which X-tals are connected (bits XA and XB).
This is important, because the X-tal frequency of the colour decoder is also used to calibrate many internal circuit.
The burst phase detector locks the Xtal oscillator with the chroma burst signal.
The phase detector operates during the burst key period only, to prevent disturbance of the PLL by the chroma signal.
Two gain modes provide:
- Good catching range when the PLL is not Locked.
- Low ripple voltage and good noise immunity once the PLL has locked
The killer circuit switches-off the R-Y and B-Y demodulators at very low input signal conditions (chroma burst amplitude).
A hysteresis prevents on/off switching at low, noisy signals.
Color standardpin34pin35XAXB
PAL4.43/SECAM + NTSC-4.43none4.4310
PAL4.43/SECAM + NTSC-M3.584.4311
Integrated video filters
The TDA8375A has alignment-free internal luminance delay, chroma bandpass and chroma trap.
They are implemented as gyrator circuits tuned by tracking to the frequency of the chroma Xtal oscillator.
The chroma trap in the Y signal path is by-passed when Y/C input is selected (S-VHS ).
For SECAM an extra luminance delay is build-in, for correct delay of the luminance signal.
43
Page 44
RGB output and black current stabilization
The colour difference signals (R-Y, B-Y) are matrixed with the luminance signal (Y) to obtain the RGBout output
signals (pins 19, 20, 21).
In the TDA8375A the matrix type automatically adapts to the decoded standard (NTSC,PAL) .
Linear amplifiers are used to interface external RGB in signals (pins 23,24,25) from the SCART connector.
These signals overrule the internal RGB signals when the data insertion pin 26 (FBI) is switched to a level between
1.0V and 3.0V.
The contrast and brightness control and the peak white limiter operate on both internal and external RGB signals
R,G and B each have their own, independent gain control to compensate for the difference in phosphor efficiencies
of the picture tube: so called “white point” adjustment.
The nominal amplitude is about 2V black to white, at nominal input signals and control settings.
TDA8375A has a black current stabilization loop, that automatically adjust the black level to the cut-off voltage of the
picture tubes three gun cathodes.
Since no current is flowing when the voltage the cathode is equal to the cut-off voltage of the tube, the loop stabilizes
at a very small gun current.
This “black current” of the three guns is measured internally and compared with a reference current, to adjust the
black level of RGBout.
The black level loop is active during 4 lines at the end of the vertical blanking.
In the first line the leakage current is measured (max. acceptable 100 A).
In the next three lines the black levels of the three guns are adjusted.
The nominal value of the ‘black current’ is 10 A.
The ratio of the ‘black currents’ for the 3 guns tracks automatically with the white point adjustment, so the
back-ground colour is the same as the adjusted white point.
At switch-on of the TV receiver the black current stabilization circuit is not yet active and RGBout are blanked.
Before the first measurement pulses appear, 0.5 sec delay ensures that the vertical deflection is active, so the pulses
will not be visible on the screen.
During the measuring lines RGBout will supply 4V pulses to the video output stages.
The TDA8375A waits until the black current feedback input (pin 18) exceeds 200 A, which indicates that the picture tube
is warm-up.
Then the black current stabilization circuit is active.
After a waiting time of about 1.0 sec, the blanking of RGBout is released.
Tuning
The AFC information of the TDA8375A is not available as an analogue voltage.
Automatic following (=frequency tracking, AFC) can be done via the I2C-bus by software.
The TDA8375A AFC window is typically 80 kHz wide.
This value is made higher than the 62.5 kHz tuning step, to prevent an automatic following loop from continuously
adapting the tuning frequency..
With this AFC window ( 40 kHz) the maximum tuning error is less than 62.5 kHz.
For high speed search-tuning-algorithms, the AFC window can be widened to 240 kHz via bit AFW.
TDA8395 SECAM decoder
The TDA8395 is an alignment-free SECAM colour decoder, including a Cloche filter, demodulator and line
identification circuit.
The Cloche filter is a gyrator-capacitor type.
Its frequency is calibrated in the vertical retrace period.
The calibration reference( pin 1 ) is obtained from the TDA8375A color X-tal oscillator (pin 33).
Pin 7 is a decoupling for the Cloche reference.
44
Page 45
The voltage change at this pin due to leakage currents should be lower than 10 mV, during field scan, resulting in a
capacitor of minimal 100 nF.
Pin 8 is the reference capacitor for the PLL.
The voltage variation during field scan at this pin should be lower than 2 mV , resulting in a capacitor of 220 nF.
The sandcastle input (pin 15) is connected to TDA8375A pin 41 and is used for generation of the blanking periods and
provides clock information for the identification circuit.
The CVBS source select output (TDA8375A pin 38) supplies SECAM chroma to pin 16 of the TDA8395.
This is demodulated by a PLL demodulator, that uses the reference frequency at pin l and a bandgap reference to
obtain the desired demodulation characteristic.
If the digital line identification in theTDA8395 detects SECAM, pin 1 will sink a current of 150 (A out of TDA8375A
SECAMref pin 33.
When the TDA8375A has not detected PAL or NTSC, it will respond by increasing the voltage at pin 33 from 1.5V to 5V.
Now the TDA8375A color difference outputs pin 30 and 29 are made high-ohmic and the TDA8395 output pin 9 and 10
are switched on.
These outputs will be disconnected and high-ohmic when no SECAM is detected for two frame periods, the decoder
will be initialized before trying again.
SECAM-L and -L ’ application
For SECAM-L and L’ the TDA8375A has to be switched to positive modulation via I2C-bus bit MOD.
SECAM-L’ signals only occur in VHF band l and have their picture and sound carrier interchanged, compared to
SECAM-L/PAL channels.
For SECAM-L’ the IF picture carrier is situated at 34.5 MHz and the AM-sound carrier at 41MHz.
Therefore the IF-PLL reference has to be tuned away from 38.9 to 34.5 MHz.
This can be done via I2C-bus sub-address 15hex (IF-PLL).
The AM sound output is inserted at TDA8375A external audio input pin via the SCART plug.
When bit MOD selects positive modulation for SECAM-L/L’, the TDA8375A automatically switches to external audio.
Base band delay line TDA4665
TDA4665 is an integrated double baseband delay line of 64 S.
It couples to the TDA8375A and TDA8395 without any switches or alignments.
The TDA4665 consist of two main blocks:
- Two delay lines of 64 sec in switched capacitor technique
- Internal clock generation of 3 MHz, line locked to the sandcastle pulse
The TDA4665 operates according to the mode demanded by the colour transmission standard:
- For PAL it operates as geometric adder to satisfy the PAL demodulation requirements
- In NTSC mode it reduces cross-colour interference (comb-filtering)
- For SECAM it repeats the colour difference signal on consecutive horizontal scan lines.
A sandcastle pulse is connected to pin 5.
The top pulse voltage (should not exceed 5 V) can be directly coupled to the 5 V sandcastle output of the TDA8375A.
The R-Y and B-Y colour difference signals (from TDA8375A pins 30 and 29) are AC-coupled and clamped by the
input stages at pins 16 and 14.
An internal 6 MHz Current controlled oscillator is line locked via a PLL to the sandcastle pulse at pin 5.
This clock drives the delay lines to obtain the required 64 sec.
Sample and hold low pass filters supress the clock signal.
The original and the delayed signals are added, buffered and fed to the output pins 11 and 12.
These are AC-coupled to the R-Y and B-Y colour difference input pin 32 and 31 of TDA8375A.
45
Page 46
The TDA4665 needs a 5 V supply voltage on pin 1 for the digital part and on pin 9 for the analog part.
TDA8351 vertical deflection.
The TDA8351 is a vertical deflection circuit.
It can be used in 90 deflection systems with frame frequencies from 50 up to 120 Hz
With its bridge configuration the deflection output can be DC coupled with few external components.
Only a supply voltage for the scan and a second supply for the flyback are needed.
The TDA8351 can drive max.2A.
The vertical drive currents of TDA8375A pins 47 and 46 are connected to input pins 1 and 2 of the TDA8351.
The currents are converted into a voltage by a resistor between pins 1 and 2.
Pin2 is on a fixed DC level (internal bias voltage) and on pin l the drive voltage can be measured (typical 1.8 Vpp).
The drive voltage is amplified by ‘A’ and fed to two amplifiers ‘B’ and ‘C’, one is inverting and the other is a non
inverting amplifier.
The outputs (pins 4 and 7) are connected to the series connection of the vertical deflection coil and feedback resistor .
The voltage across feed back resistor is fed via pin 9 to correction amplifier ‘D’, to obtain a deflection current which is
proportional to the drive voltage.
The supply voltage for the TDA8351 is 16V at pin 3.
The flyback generator has a separate supply voltage of 45V on pin 6.
Horizontal deflection
The circuit contains horizontal drive, line output transformer.
The horizontal driver pulses from the TDA8375A are amplified in the horizontal drive circuit, to get sufficient base-drive
current for the high voltage switching transistor Q401.
During the horizontal scan period( =52 s) Q401 will conduct, and a sawtooth current flows from +132V through the
primary winding of the FBT to ground.
After this time Q401 is switched off and the energy stored in the FBT during the scan period will be transformed to the
flyback capacitor CT.
This energy transfer will take place in a cosine shape because the primary of the FBT and CT from a resonant circuit.
The time the energy is transferred from FBT to CT. and back to the FBT, is called the flyback time and will take place
in about 12 s.
The flyback peak voltage is about 9 times the scan voltage.
In series with the horizontal deflection coil there is a (damped) linearity corrector coil.
During the scan there is some loss in the resistance of the deflection coil.
In the first part of a line the linearity corrector stores some energy in a permanent magnet until it is saturated.
This improves the linearity of the horizontal scan speed.
The required S correction for the picture tube can be adjusted with the value of C408.
The beam current limiting information (BeamCurr) is derived from the foot of the H.V winding of the FBT.
This is connected via resistor to +8V.
As the beam current increase, the voltage on line BeamCurr decreases.
BeamCurr is damped by a integration filter before it is fed back to TDA8375A pin 22.
The TDA8375A will decrease the contrast (and eventually the brightness) to limit the average beam current.
EW drive
The DC voltage on pin 45 is determined by the East-West driver stage input and may range from 1 to 8 volts.
To prevent distortion, the voltage must always be >1volt.
Because the DC voltage on pin 45 is equal to the minimal output voltage of the East-West driver stage (reached for iew =
0), it is recommended to choose this level close to 1 volt for maximum range.
46
Page 47
Video amplifiers
Three TDA6106Q integrated video amplifiers drive cathode of the picture tube directly.
They are protected against CRT flashover discharges and ESD (electro static discharge).
The three video amplifiers, have a beam current output I black, used by the TDA8375A black current loop to control
the black level on the cathodes.
The outputs can be connected together because the black current 100p sequentially controls the black level for each
cathode.
The amplification of the TDA6106Q is set by the resistors between pin 3 and 9 and between pin 3 (negative-input) and
the TDA8375A output.
There are no alignment any more on the CPT panel, because of the automatic black current stabilization and because
the white point adjustment can be done in the TDA8375A via I2C bus.
Power Supply STR-S5707
(1) VIN terminal, start-up circuit
A start-up circuit is to start and stop a operation of a control IC by detecting a voltage appearing at a VIN terminal
(pin-9).
At start up of a power supply, when a voltage at the VIN terminal reaches to 8V (typical) by charging up C812 by
the function of a start-up resistor, R802, a control circuit starts operating by the function of the start-up circuit.
After the control circuit starts its operation, power source is obtained by smoothing voltage appearing at winding of
pin6-7 of T802.
(2) Oscillator, F/B terminal voltage (Pin 7)
A oscillator generates pulse signals which turns a power transistor on and off by making use of charge and discharge
of C1 and C2 incorporated in the Hybrid IC.
Constant voltage control of a switch-mode power supply is performed by changing both ON-time and OFF-time except
when the load is light (ex. remote control stand-by mode of TVs).
The ON-time is controlled by changing a current charged by C1, which is as the result of that the detection winding of
pin5-7 of T802, which detects a change of voltage in a secondary side, connected to the sensing terminal (Pin 7) has the
current in accordance with an output signal from an output voltage detection circuit (an error amplifier) built in.
As an AC input voltage to the power supply gets the higher and a load current the smaller, the current flowing to the
SENS terminal gets the larger, and the ON-time gets the shorter.
(3) Function of INH terminal (Pin 6), control of OFF-time
Signal to the INH terminal is used as inputs to COMP.1 and COMP.2 inside of the control IC.
A threshold voltage of COMP.1, VTH1 is set at 0.75V (Ta=25°) and an input signal to a drive circuit becomes almost
0V (the power transistor is in OFF mode) when a voltage at the INH terminal reaches the VTH1.
A threshold voltage of COMP.2, VTH2, is set at 1.5V (Ta=25°).
When the INH terminal voltage reaches VTH2, an output from COMP.2 reverses (the power transistor is in on mode).
Quasi-resonant operation
By inputting the voltage of winding of pin6-7 of T802 which is synchronized with the energy discharge time of a
secondary winding, pin14(or 15)-16 of T802, to the INH terminal through D805 and RC803, quasi-resonant operation
can be achieved.
When the power transistor turns off and a voltage higher than VTH2 is applied to the INH terminal, C3 immediately
discharges and then starts charging again.
Even after the discharge of energy of a secondary winding is completed, VINH does not immediately increases.
When it gets lower than VTH1, the transistor turns on.
47
Page 48
Stand-By Mode
While being in remote control stand-by mode, the output voltage is kept on providing to the secondary side and
the power transistor operates at A class mode.
(4) Drive circuit
The STR-S5707 applies the proportional drive system in order to minimize turn-on and saturation loss, and storage time.
(5) OCP (over-current protection) function
Over-current protection is performed pulse by pulse by directly detecting collector current of the power transistor.
Detecting voltage is set to -1V below a reference point of GND (ground).
(6) Latch circuit
It is a circuit which sustains an output from the oscillator low and stops operation of the power supply when over-voltage
protection (OVP) circuit and thermal shutdown (TSD) circuit are in operation.
As the sustaining current of the latch circuit is 500 A maximum when VIN terminal voltage is 4V, the power supply
circuit sustains the off state as long as current of 500 A minimum flows to VIN terminal from a start-up resistor.
In order to prevent a malfunction to be caused by a noise and so on, delay time is provided by C1 incorporated in the
IC and, therefore, the latch circuit operates when the OVP or TSD circuit is in operation, or an external signal input is
provided for about 10 sec or longer.
In addition, even after the latch circuit start operating, the constant voltage regulator (Reg) circuit is in operation and the
circuit current is at high level.
As a result, VIN terminal voltage rapidly decreases.
When VIN terminal voltage becomes lower than the shutdown voltage, VIN(OFF) (4.9V typical), it starts increasing as the
circuit current is below 500 A.
When it reaches the ON-state voltage, VIN (ON) (8V typical), VIN terminal voltage starts decreasing because the circuit
current increases again.
When the latch circuit is on, VIN terminal voltage increases and decreases within the range from 4.9V typical to
8V typical and is prevented from abnormally rising.
Cancellation of the latch is done by decreasing VIN terminal voltage below 3.3V.
The power supply can be restarted after disconnecting an AC input to the power supply once.
(7) Thermal shutdown circuit
It is a circuit to trigger the latch circuit when the frame temperature of the IC exceeds 150 (typical).
Although the temperature is actually sensed at the control chip, it works against overheating of the power transistor
as the power transistor and the control IC are mounted on the same lead frame.
(8) Over-voltage protection circuit
It is a circuit to trigger the latch circuit when VIN terminal voltage exceeds 11V (typical).
Although it basically functions as protection of VIN terminal against over-voltage, since VIN terminal is usually supplied
from the drive winding of the transformer and the voltage is proportional to the output voltage, it also functions against
the over-voltage of secondary output which causes when the control circuit opens or in some other events.
48
Page 49
THE DIFFERENT PARTS FOR CRT (CP-775)
No LOC. NAME28” (V/COLOR28”(PHILIPS) 25”(PHILIPS) 25”(ORION) 29”(ORION)