DADD 3D7501Z, 3D7501M, 3D7501H, 3D7501G, 3D7501 Datasheet
3D7501
MONOLITHIC MANCHESTER
data
3
ENCODER
(SERIES 3D7501)
FEATURES
• All-silicon, low-power CMOS
technology
• TTL/CMOS compatible inputs and
outputs
• Vapor phase, IR and wave
solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Maximum data rate: 50 MBaud
CLK
RESB
DAT
GND
3D7501M DIP (.300)
3D7501H Gull Wing (.300)
3D7501Z SOIC (.150)
8
1
7
2
6
3
5
4
FUNCTIONAL DESCRIPTION
The 3D7501 is a monolithic CMOS Manchester Encoder. The clock
and data, present at the unit input, are combined into a single biphase-level signal. In this encoding mode, a logic one is represented
by a high-to-low transition within the bit cell, while a logic zero is
represented by a low-to-high transition. The unit operating baud rate (in
Mbaud) is equal to the input clock frequency (in MHZ) . All pins
marked N/C must be left unconnected.
PACKAGES
VDD
N/C
TXB
TX
delay
devices, inc.
14
CLK
N/C
N/C
RESB
DAT
N/C
GND
3D7501 DIP (.300)
3D7501G Gull Wing (.300)
3D7501D SOIC (.150)
PIN DESCRIPTIONS
DAT Data Input
CLK Clock Input
RESB Reset
TX Signal Output
TXB Inverted Signal Output
VCC +5 Volts
GND Ground
1
2
3
4
5
6
7
13
12
11
10
VDD
N/C
N/C
N/C
N/C
9
TXB
8
TX
The all-CMOS 3D7501 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL Manchester Encoder. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is
offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14pin SOICs.
Doc #96010 DATA DELAY DEVICES, INC. 1
5/19/97 3 Mt. Prospect Ave. Clifton, NJ 07013
3D7501
APPLICATION NOTES
The 3D7501 Manchester Encoder samples the
data input at the rising edge of the input clock.
The sampled data is used in conjunction with the
clock rising and falling edges to generate the byphase level Manchester code.
INPUT SIGNAL CHARACTERISTICS
The 3D7501 Manchester Encoder inputs are
TTL compatible. The user should assure
himself that the 1.5 volt TTL threshold is used
when referring to all timing, especially to the
input clock duty cycle.
CLOCK DUTY CYCLE ERRORS
The 3D7501 Manchester Encoder employs the
timing of the clock rising and falling edges (duty
cycle) to implement the required coding scheme.
To reduce the difference between the output data
high time and low time, it is essential that the
deviation of the input clock duty cycle from 50/50
be minimized.
OUTPUT SIGNAL CHARACTERISTICS
The 3D7501 presents at its outputs the true and
the complimented encoded data.
The High-to-Low time skew of the selected data
output should be budgeted by the user, as it
relates to his application, to satisfactorily
estimate the distortion of the transmitted data
stream.
Such estimate is very useful in determining the
functionality and margins of the data link, if a
3D7502 Manchester Decoder is used to decode
the received data.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D7501 Manchester encoder utilizes
novel and innovative compensation circuitry to
minimize timing variations induced by
fluctuations in power supply and/or temperature.
RESET
(RESB)
CLOCK
(CIN)
DATA
(DIN)
TRANSMIT
(TXB)
TRANSMIT
(TX)
Power-on reset (Left high for normal operation)
1/f
C
1 0 1 1 0 0 1 0
t
DS
t
DH
T
2H
T
2L
T
1H
T
1L
1 0 1 1 0 0 1 0
Figure 1: Timing Diagram
Doc #96010 DATA DELAY DEVICES, INC. 2
5/19/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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