Cypress Semiconductor CY7C4841-25AC, CY7C4841-15AC, CY7C4841-10AC, CY7C4831-25AC, CY7C4831-15AC Datasheet

256/512/1K/2K/4K/8K x9 x2

Double S

y

nc FIFOs

fax id: 5414

CY7C4801/4811/4821

CY7C4831/4841/4851

Cypress Semiconductor Corporation • 3901North First Street • San Jose • CA 95134 • 408-943- 2600

October 1996 - Revised January 15, 1997

1Double CY7C483 1/4
841/4851

Features

• Double high speed, low power, first-in first-out (FIFO)

memories

• Double 256 x 9 (CY7C4801)

• Double 512 x 9 (CY7C4811)

• Double 1K x 9 (CY7C4821)

• Double 2K x 9 (CY7C4831)

• Double 4K x 9 (CY7C4841)

• Double 8K x 9 (CY7C4851)

• Functionally equivalent to two CY7C4201/4211/4221/
4231/4241/4251 FIFOs in a single package

• 0.65 micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10 ns read/write cycle
times)

• Offers optimal combination of large capacity, high
speed, design flexibility, and small footprint

• Fully asynchronous and simultaneous read and write
operation

• Four status flags per device: Empty, Full, and program­mable Almost Empty/Almost Full

• Low power — I

CC1

= 60mA

• Output Enable (OEA

/OEB) pins

• Depth Expansion Capabilty

• Width Expansion Capabilty

• Space-saving 64-pin TQFP

• Pin compatible and functionally equivalent to IDT72801,
72811, 72821, 72831, 72841,72851

Functional Description

The CY7C48X1 are Double high-speed, low-power, first-in
first-out (FIFO) memories with clocked read a nd write in terfac­es. All are 9 bits wide and operate as two separate FIFOs. The
CY7C48X1 are pin-compatible to IDT728X1. Programmable
features include Almost Full/Almost Empty flags. These FIF Os
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor interfac­es, and communications buffering.

These FIFOs have two independent sets of 9-bit input and
output ports that are controlled by separate clock and enable
signals. The input port is contr olled by a free-running clock
(WCLKA,WCLKB) and two write-enable pins (WENA1

,

WENA2/LDA

, WENB1, WENB2/LDB).

When (WENA1

,WENB1) is LOW and (WENA2/LDA,

WENB2/LDB

) is HIGH, data is writ ten into the FIFO on the

rising edge of the (WCLKA,WCLKB) signal. While (WENA1

,

WENA2/LDA

, WENB1, WENB2/LDB) is held active, data is
continually written into the FIFO on each WCLKA, WCLKB
cycle. The output port is controlled in a similar manner by a
free-running read clock (RCLKA, RCLKB) and two read-en­able pins ((RENA1

,RENB1), (RENA2,RENB2)). In addition,

the CY7C48X1 has output enable pins (OEA

, OEB) for each
FIFO. The read (RCLKA, RCLKB) and write (WCLKA,
WCLKB) clocks may be tied together for single-clock o peration
or the two clocks may be run independently for asynchronous
read/write appli cations. Clock frequencies up to 100 MHz are
achievable.

Depth expansion is possible using one e nable input for system
control, while the other enable is controlled by expan sion logic
to direct the flow of data.

The CY7C48X1 provides two sets of four different status pins: Empty,
Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags
are programmable to single word granularity. The programmable
flags default to Empty+7 and Full–7.

The flags are synchronous, i.e., th ey change state relative to
either the read clock (RCLKA,RCLKB) or the write clock
(WCLKA,WCLKB). When entering or exiting the Empt y and
Almost Empty states, the flags are updated exclusively by the
(RCLKA,RCLKB). The flags denoting Almost Full, and Full
states are updated exclusively by (WCLKA,WCLKB) The syn­chronous flag architecture guarantees that the flags maintain
their status for at least one cycle

All configurations are fabricated using an advanced 0.65µ
N-Well CMOS technology. Input ESD protection is greater than
2001V , and latch-up is prevented by the use of guard rings.

CY7C4801/4811/4821

CY7C4831/4841/4851

2

Logic

Block Diagram

48X1–1

THREE–STATE

OUTPUT

REGISTER

READ

CONTROL B

FLAG

LOGIC

WRITE

CONTROL

WRITE

POINTER B

READ

POINT ER B

RESET

LOGIC

FLAG
PROGRAM
REGISTER

DB

0-8

RCLKB

EFA
PAEA

PAFA

QB

0-8

RSA

OEB

RAM

ARRAY A

256

x9

.

.

8k x

9

RENB1

RENB2

FFA

WRITE

CONTROL

WRITE

POINTER A

WENA1

WCLKA

WENA2/LDA

RSB

WENB1

WCLKB

WENB2/LDB

RAM

ARRAY B

.
.

8k x 9

READ

CONTROL A

READ

POINTER A

RCLKA

RENA1

RENA2

INPUT

REGISTER

DA

0-8

QA

0-8

LDA
LDB

EFB
PAEB
PAFB
FFB

OEA

INPUT

REGISTER

THREE–STATE

OUTPUT REGISTER

256

x9

TQFP

Top View

48X1–1

QA

2

QA

3

QA

4

QA

5

QA

6

QA

7

QA

8

V

cc

WENA2/LDA

WCLKA
WENA1

RSA

DA

8

DA

7

DA

6

QA

1

QB

0

FFB
EFB
OEB
RENB2
RCLKB
RENB1
GND
V

cc

PAEB
PAFB
DB

0

DB

1

DB

2

DB

3

DB

4

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

CY7C4801
CY7C4811
CY7C4821
CY7C4831
CY7C4841
CY7C4851

Pin Configuratio n

CY7C4801/4811/4821

CY7C4831/4841/4851

3

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .......................................−65

°C to +150°C

Ambient Temperature with

Power Applied.................................................... −55

°C to +125°C

Supply Voltage to Ground Potential.... .............−0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State.....................................................−0.5V to +7.0V

DC Input Voltage.................................................−0.5V to +7.0V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage ...........................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current .....................................................>200 mA

Selectio n Guide

7C48X1-10 7C48X1-15 7C48X1-25 7C48X1-35

Maximum Frequency (MHz) 100 66.7 40 28.6
Maximum Access Time (ns) 8 10 15 20
Minimum Cycle Time (ns) 10 15 25 35
Minimum Data or Enable Set-Up (ns) 3 4 6 7
Minimum Data or Enable Hold (ns) 0.5 1 1 2
Maximum Flag Delay (ns) 8 10 15 20
Active Power Supply

Current (I

CC1

) (mA)

Commercial 60 60 60 60
Industrial 70 70 70 70

CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851

Density Double 256 x 9 Double 512 x 9 Double 1K x 9 Double 2K x 9 Double 4K x 9 Double 8K x 9
Package 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP

Operating Range

Range

Ambient

Temperatur e

V

CC

Commercial 0°C to +70 °C 5V ± 10%
Industrial

[1]

−40°C to +85°C 5V ± 10%

Notes:

1. T

A

is the “instant on” c ase tempe rature.

CY7C4801/4811/4821

CY7C4831/4841/4851

4

Pin Definitions

Signal Name Description I/O Description

DA

0 − 8

Data Inputs I Data Inputs for 9-bit bus

DB

0 − 8

Data Inputs I Data Inputs for 9-bit bus

QA

0 − 8

Data Outputs O Data Outputs for 9-bit bus

QB

0 − 8

Data Outputs O Data Outputs for 9-bit bus

WENA1
WENB1

Write Enable 1 I WENA1 and WENB1become the only write enables when the device is configured to

have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when
(WENA1

,WENB1) is LOW and (FFA,FFB) is HIGH. If the FIFO is configured to have two write

enables, data is written on a LOW-to-HIGH transition of WCLK when (WENA1

,WENB1) i s

LO W a n d ( WENA2 /LD A

,WENB2/LDB ) and (FFA,FFB) are HIGH.

WENA2/LDA
WENB2/LDB
Dual Mode Pin

Write Enable 2 I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin

operates as a control to write or read the programmable flag offsets. (WENA1

,WENB1)

mu s t b e LOW and (WENA2/LDA

,WENB2/LDB ) must be HIGH to write data into the FIFO.

Data will not be written into the FIFO if the (FFA

,FFB) is LOW. If the FIFO is configured to have

programmable flags, (WENA2/LDA

,WENB2/LDB) is held LOW to write or read the program-

mable flag offsets.

Load I

RENA1
RENA2
RENB1
RENB2

Read Enable
Inputs

I Enables the device for Read operation.

WCLKA
WCKLB

Write Clock I The rising edge clocks data into the FIFO when (WENA1,WENB1) is LOW and

(WENA2/LDA

,WENB2/LDB) is HIGH and the FIFO is not Full. When

(WENA2/LDA

,WENB2/LDB) is asserted, WCLK writes data into the programmable flag-offset

register.

RCLKA
RCLKB

Read Clock I The rising edge clock s data out of the FIFO when (RE NA 1 ,RENB1) and (RENA2,RENB2)

are LOW and the FIFO is not Empty. When (WENA2/LDA,

WENB2/LDB) is LOW,

(RCLKA,RCLKB) reads data out of the programmable flag-offset register.
EFA,EFB Empty Flag O When (EFA,EFB) is LOW, the FIFO is empty. (EFA,EFB) is synchronized to (RCLKA,RCLKB).
FFA,FFB Full Flag O When (FFA,FFB) is LOW, t h e FIFO is full. ( FF A,FFB) is synchronized to (WCLKA,WCLKB).
P AEA

P AEB

Programmable
Almost Empty

O When (PAEA,PAEB) is LOW , the FIFO is almost empty based on the almost empty offset value

programmed into the FIFO. PAE is synchronized to RCLK.
PAFA

PAFB

Programmable
Almost Full

O When (PAFA,PAFB) is LOW, the FIFO is almost full based on the almost full offset value pro-

grammed into the FIFO. PAF is synchronized to WCLK.
RSA

RSB

Reset I Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.
OEA

OEB

Output Enable I When (OEA,OEB) is LOW , the FIFO’s data outputs drive the bus to which they are connected.

If (OEA

,OEB) is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

CY7C4801/4811/4821

CY7C4831/4841/4851

5

Electrical Characteristics Over the Operating Range

[2]

7C48X1-10 7C48X1-15 7C48X1-25 7C48X1-35

Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

V

OH

Output HIGH Voltage VCC = Min.,

I

OH

= −2.0 mA

2.4 2.4 2.4 2.4 V

V

OL

Output LOW Voltage VCC = Min.,

I

OL

= 8.0 mA

0.4 0.4 0.4 0.4 V

V

IH

Input HIGH Voltage 2.0 V

CC

2.0 V

CC

2.0 V

CC

2.0 V

CC

V

V

IL

Input LOW Voltage −0.5 0.8 −0.5 0.8 −0.5 0.8 −0.5 0.8 V

I

IX

Input Leakage
Current

V

CC

= Max. −10 +10 −10 +10 −10 +10 −10 +10 µA

I

OS

[3]

Output Short
Circuit Current

VCC = Max.,
V

OUT

= GND

−90 −90 −90 −90 mA

I

OZL

I

OZH

Output OFF,
High Z Current

OE > VIH,
V

SS

< VO < V

CC

−10 +10 −10 +10 −10 +10 −10 +10 µA

I

CC1

[4]

Active Power Supply
Current

Com’l 60 60 60 60 mA
Ind 70 70 70 70 mA

Capacitance

[5]

Par amete r Description Test Conditions Max. Unit

C

IN

Input Capacitance TA = 25°C, f = 1 MHz,

V

CC

= 5.0V

10 pF

C

OUT

Output Capacitance 10 pF

AC Test Loads and Waveforms

[6, 7]

Notes:

2. See the last page of this specification for Group A subgroup testing information.

3. Test no more than one output at a time for not more than one second.

4. Outputs open. Tested at Frequency = 20 MHz.

5. Tested initially and after any design or process changes that may affect these parameters.

6. C

L

= 30 pF for all AC par amet ers except for t

OHZ

.

7. CL = 5 pF for t

OHZ

.

3.0V

5V

OUTPUT

R1 1.1K

Ω

R2
680Ω

C

L

INCLUDING

JIGAND

SCOPE

GND

90%

10%

90%

10%

≤ 3ns ≤ 3

ns

OUTPUT 1.91V

Equivalentto: THÉ VENIN EQUIVALENT

48X1–4

420Ω

ALL INPUT PULSES

48X1–5

CY7C4801/4811/4821

CY7C4831/4841/4851

6

Switching Characteristics Over the Operating Range

7C48X1-10 7C48X1-15 7C48X1-25 7C48X1-35

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Uni t

f

S

Clock Cycle Frequency 100 66.7 40 28.6 MHz

t

A

Data Access Time 2 8 2 10 2 15 2 20 ns

t

CLK

Clock Cycle Time 10 15 25 35 ns

t

CLKH

Clock HIGH Time 4.5 6 10 14 ns

t

CLKL

Clock LOW Time 4.5 6 10 14 ns

t

DS

Data Set-Up Time 3.5 4 6 7 ns

t

DH

Data Hold Time 0.5 1 1 2 ns

t

ENS

Enable Set-Up Time 3.5 4 6 7 ns

t

ENH

Enable Hold Time 0. 5 1 1 2 ns

t

RS

Reset Pulse Width

[8.]

10 15 25 35 ns

t

RSS

Reset Set-Up Time 8 10 15 20 ns

t

RSR

Reset Recovery Time 8 10 15 20 ns

t

RSF

Reset to Flag and Output Time 10 15 25 35 ns

t

OLZ

Output Enable to Output in Low Z

[9]

0 0 0 0 ns

t

OE

Output Enable to Output Valid 3 7 3 8 3 12 3 15 ns

t

OHZ

Output Enable to Output in High Z

[9]

3 7 3 8 3 12 3 15 ns

t

WFF

Write Clock to Full Flag 8 10 15 20 ns

t

REF

Read Clock to Empty Flag 8 10 15 20 ns

t

PAF

Clock to Programmable Almost-Full Flag 8 10 15 20 ns

t

PAE

Clock to Programmable Almost-Full Flag 8 10 15 20 ns

t

SKEW1

Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag

5 6 10 12 ns

t

SKEW2

Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and Almost-Full
Flag

15 15 18 20 ns

Notes:

8. Pulse widths less than minimum values are not allowed.

9. Va lues guaranteed by design, not currently tested.

CY7C4801/4811/4821

CY7C4831/4841/4851

7

Switching Waveforms

Notes:

10. t

SKEW1

is the minimum time between a r ising (RCLKA,RC LKB) edge and a r ising (WCLKA, WCLKB) edge to guarantee that (FF A,FFB) will go HIGH during the current clock

cycle. If the time between the rising e dge of (R CLKA,RC LKB) an d the rising edg e of ( WCLKA,WCL KB) i s les s than t

SKEW1

, then (FF A,F FB) may not change sta te unt il the

next (WCLKA,WCLKB) rising edge .

11. t

SKEW1

is the minimum time between a rising ( WCLKA,WCLKB) edge and a risi ng (RCLKA,RCLKB) edge to guarantee that (EF A,EFB) will go HIGH during the current clock

cycle. It the time between the rising e dge of (WCLKA, WCLKB) a nd the rising edg e of R CLK is l ess than t

SKEW1

, then (EF A,EFB) may not change s tat e until t he next

(RCLKA,RCLKB) rising edge.

Write Cycle Timing

t

CLKH

t

CLKL

NO OPERATION

t

DS

t

SKEW1

t

ENS

WENA1

t

CLK

t

DH

t

WFF

t

WFF

t

ENH

WCLKA (WCLKB)

DA

0

−DA

8

FFA (FFB)

RENA1

,RENB2

RCLKA (RCLKB)

48X1–6

NO OPERATION

WENA2(WENB2)
(if applicable )

(WENB1

)

(RENB1

, RENB2)

(DB

0

−DB8)

[10]

Read Cycle Timing

t

CLKH

t

CLKL

NO OPERATION

t

SKEW1

t

CLK

t

OHZ

t

REF

t

REF

t

OE

t

ENS

t

OLZ

t

A

t

ENH

VALID DATA

48X1–7

EFA(EFB)

WCLKA,WCLKB

OEA

(OEB)

WENA2(WENB2)

QA

0

−QA

8

(QB0−QB8)

[11]

(RENB1,RENB2)

RENA1

,RENA2

WENA1(WENB1)

RCLKA (RCLKB)