CTLST CAT28C257T13I-90T, CAT28C257T13I-15T, CAT28C257T13I-12T, CAT28C257T13A-90T, CAT28C257T13A-15T Datasheet

Advanced

CAT28C257

256K-Bit CMOS PARALLEL E2PROM

FEATURES

■ Fast Read Access Times: 90/120/150 ns

■ Low Power CMOS Dissipation:

–Active: 25 mA Max.
–Standby: 150 µA Max.

■ Simple Write Operation:

–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear

■ Fast Write Cycle Time:

–5ms Max

■ CMOS and TTL Compatible I/O

DESCRIPTION

The CAT28C257 is a fast, low power, 5V-only CMOS
Parallel E2PROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto­clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the self­timed write cycle. Additionally, the CAT28C257 features
hardware and software write protection.

■ Automatic Page Write Operation:

–1 to 128 Bytes in 5ms
–Page Load Timer

■ End of Write Detection:

–Toggle Bit

DATADATA

–

DATA Polling

DATADATA

■ Hardware and Software Write Protection

■ 100,000 Program/Erase Cycles

■ 100 Year Data Retention

■ Commercial, Industrial and Automotive

Temperature Ranges

The CAT28C257 is manufactured using Catalyst’s ad­vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.

BLOCK DIAGRAM

A7–A

14

V

CC

CE
OE

WE

A0–A

6

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

ADDR. BUFFER

INADVERTENT

ADDR. BUFFER

& LATCHES

WRITE

PROTECTION

CONTROL

LOGIC

TIMER

& LATCHES

ROW

DECODER

HIGH VOL TAGE

GENERAT OR

DATA POLLING

AND

TOGGLE BIT

COLUMN

DECODER

1

32,768 x 8

E2PROM

ARRAY

128 BYTE PAGE

REGISTER

I/O BUFFERS

I/O0–I/O

7

5096 FHD F02

Doc. No. 25073-00 2/98

CAT28C257

Advanced

PIN CONFIGURATION

PLCC Package (N)DIP Package (P)

A
A

I/O
I/O
I/O

V

14
12

A
A
A
A
A
A
A
A

SS

1

28

2

27
3
4
5
6
7
8
9
10
11
12
13
14

26

25

24

23

22

21

20

19

18

17

16

15

7
6
5
4
3
2
1
0
0
1
2

V

CC

WE
A

13

A

8

A

9

A

11

OE
A

10

CE
I/O
I/O
I/O
I/O
I/O

A7A12A14NC

4321323130

A
A
A
A
A
A
A

7

NC

6

I/O

5
4
3

5

6

6

5

7

4

8

3

9

2

10

1

11

0

12
13

0

14 15 16 17 18 19 20

2

SS

I/O1I/O

NC

V

13

VCCWE

A

29
28
27
26
25
24
23
22
21

5

I/O3I/O4I/O

A

8

A

9

A

11

NC
OE
A

10

CE
I/O

7

I/O

6

5096 FHD F01

TSOP Package (8mm X 13.4mm) (T13)

V

A

A

A
WE

A

OE

11

A
A

13

CC

14

12
A

A
A
A
A

1
2
3

9

4

8

5
6
7
8
9
10

7

11

6

12

5

13

4

14

3

PIN FUNCTIONS

Pin Name Function

A0–A

14

I/O0–I/O

7

Address Inputs
Data Inputs/Outputs

CE Chip Enable
OE Output Enable

Pin Name Function

WE Write Enable
V
V

CC
SS

5V Supply
Ground

NC No Connect

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A

10

CE

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

GND
I/O

2

I/O

1

I/O

0

A

0

A

1

A

2

28C257 F03

Doc. No. 25073-00 2/98

2

Advanced CAT28C257

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

VCC with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

(2)

........... –2.0V to +VCC + 2.0V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica­tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor­mance and reliability.

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(3)

........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Test Method

N
T
V
I

LTH

END

DR

ZAP

(1)

(1)

(1)

(1)(4)

Endurance 104 or 10
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17

5

Cycles/Byte MIL-STD-883, Test Method 1033

D.C. OPERATING CHARACTERISTICS

VCC = 5V ±10%, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC

VCC Current (Operating, TTL) 30 mA CE = OE = VIL, f=6MH

z

All I/O’s Open

(5)

I

CCC

VCC Current (Operating, CMOS) 25 mA CE = OE = V

, f=6MH

ILC

z

All I/O’s Open

I

SB

I

SBC

(6)

VCC Current (Standby, TTL) 1 mA CE = VIH, All I/O’s Open
VCC Current (Standby, CMOS) 150 µA CE = V

IHC

,

All I/O’s Open

I

LI

I

LO

(6)

V

IH

(5)

V

IL

V

OH

V

OL

V

WI

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(5) V
(6) V

= –0.3V to +0.3V.

ILC

= VCC –0.3V to VCC +0.3V.

IHC

Input Leakage Current –10 10 µAVIN = GND to V
Output Leakage Current –10 10 µAV

= GND to VCC,

OUT

CE = V

IH

High Level Input Voltage 2 VCC +0.3 V
Low Level Input Voltage –0.3 0.8 V
High Level Output Voltage 2.4 V IOH = –400µA
Low Level Output Voltage 0.4 V IOL = 2.1mA
Write Inhibit Voltage 3.5 V

CC

3

Doc. No. 25073-00 2/98