CTLST CAT24WC65J-TE13, CAT24WC65J-1.8TE13, CAT24WC65KI-TE13, CAT24WC65KI-1.8TE13, CAT24WC65KA-TE13 Datasheet

Preliminary

CAT24WC33/65

32K/64K-Bit I2C Serial CMOS E2PROM

FEATURES

■ 400 KHz I

■ 1.8 to 6 Volt Read and Write Operation

■ Cascadable for up to Eight Devices

■ 32-Byte Page Write Buffer

■ Self-Timed Write Cycle with Auto-Clear

■ 8-Pin DIP or 8-Pin SOIC

■ Schmitt Trigger Inputs for Noise Protection

DESCRIPTION

2

C Bus Compatible*

■ Zero Standby Current

■ Commercial, Industrial and Automotive Tem-

perature Ranges

■ Write Protection

–Bottom 1/4 Array Protected When WP at V

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

IH

The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-

CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.

stantially reduces device power requirements. The

PIN CONFIGURATION BLOCK DIAGRAM

DIP Package (P)

1

A

0

A

1

A

2

V

SS

8

2

7

3

6

4

5

SOIC Package (J,K)

1

A

0

A

1

A

2

V

SS

8

2

7

3

6

4

5

V

CC

WP
SCL
SDA

V

CC

WP
SCL
SDA

24WC33/65 F01

EXTERNAL LOAD

V

CC

V

SS

SDA

WP

D

OUT

ACK

WORD ADDRESS

BUFFERS

STAR T/STOP

LOGIC

CONTROL

LOGIC

PIN FUNCTIONS

Pin Name Function

A0, A1, A2 Device Address Inputs

XDEC

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

128/256

E2PROM

128/256 X 256

DATA IN STORAGE

256

SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
V

CC

V

SS

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

+1.8V to +6V Power Supply
Ground

SCL

A
A1
A2

1

STATE COUNTERS

0

SLAVE
ADDRESS
COMPARATORS

HIGH VOL TAGE/

TIMING CONTROL

24WC33/65 F02

Doc. No. 25064-00 2/98 S-1

PreliminaryCAT24WC33/65

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

VCC with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

(1)

........... –2.0V to +V

CC

+ 2.0V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(2)

........................ 100mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

(3)

N
T
V
I

LTH

END
DR
ZAP

(3)

(3)

(3)(4)

Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I
I
I
I
V
V
V
V

CC
SB
LI
LO

IL
IH
OL1
OL2

(5)

Power Supply Current 3 mA f

= 100 KHz

SCL

Standby Current (VCC = 5V) 0 µAVIN = GND or V
Input Leakage Current 10 µAVIN = GND to V
Output Leakage Current 10 µAV

= GND to V

OUT

Input Low Voltage –1 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage (VCC = +3.0V) 0.4 V IOL = 3.0 mA
Output Low Voltage (VCC = +1.8V) 0.5 V IOL = 1.5 mA

CC
CC

CC

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Max. Units Conditions

(3)

C

I/O

(3)

C

IN

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby current (ISB ) = 0 µA (<900 nA).

Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (A0, A1, A2, SCL, WP) 6 pF V

I/O

IN

= 0V

= 0V

Doc. No. 25064-00 2/98 S-1

2

Preliminary CAT24WC33/65

A.C. CHARACTERISTICS

VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol Parameter 1.8V, 2.5V 4.5V-5.5V

Min. Max. Min. Max. Units

F

SCL

(1)

T

I

t

AA

t

BUF

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

t

HD:DAT

t

SU:DAT

(1)

t

R

(1)

t

F

t

SU:STO

t

DH

(1)

Clock Frequency 100 400 kHz
Noise Suppression Time 200 200 ns

Constant at SCL, SDA Inputs
SCL Low to SDA Data Out 3.5 1 µs

and ACK Out
Time the Bus Must be Free Before 4.7 1.2 µs

a New Transmission Can Start
Start Condition Hold Time 4 0.6 µs
Clock Low Period 4.7 1.2 µs
Clock High Period 4 0.6 µs
Start Condition Setup Time 4.7 0.6 µs

(for a Repeated Start Condition)
Data In Hold Time 0 0 ns
Data In Setup Time 50 50 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4 0.6 µs
Data Out Hold Time 100 100 ns

Power-Up Timing

(1)(2)

Symbol Parameter Max. Units

t

PUR

t

PUW

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

Power-Up to Read Operation 1 ms
Power-Up to Write Operation 1 ms

are the delays required from the time VCC is stable until the specified operation can be initiated.

PUW

Write Cycle Limits

Symbol Parameter Min. Typ. Max Units

t

WR

The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus

Write Cycle Time 10 ms

interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.

3

Doc. No. 25064-00 2/98 S-1

PreliminaryCAT24WC33/65

FUNCTIONAL DESCRIPTION

The CAT24WC33/65 supports the I2C Bus data trans­mission protocol. This Inter-Integrated Circuit Bus proto­col defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC33/65
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re­ceiver, but the Master device controls which mode is
activated.

PIN DESCRIPTIONS

SCL: Serial Clock

The serial clock input clocks all data transferred into or
out of the device.

SDA: Serial Data/Address
The bidirectional serial data/address pin is used to

Figure 1. Bus Timing

t

F

t

LOW

t

HIGH

transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.

A0, A1, A2: Device Address Inputs
These pins are hardwired or left unconnected (for hard­ware compatibility with CAT24WC16). When hardwired,
up to eight CAT24WC33/65s may be addressed on a
single bus system (refer to Device Addressing ). When
the pins are left unconnected, the default values are
zeros.

WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC33/65 when this pin
is tied to Vcc, the bottom 1/4 array of memory (locations
000H to 7FFH for the 24WC65 and locations 000H to
3FFH for 24WC33) is write protected . When left floating,
memory is unprotected.

t

R

t

LOW

SCL

t

SU:STA

SDA IN

SDA OUT

Figure 2. Write Cycle Timing

SCL

SDA

BYTE n

Figure 3. Start/Stop Timing

t

HD:STA

ACK8TH BIT

t

AA

t

HD:DAT

STOP
CONDITION

t

DH

t

WR

t

SU:DAT

START
CONDITION

t

SU:STO

t

BUF

ADDRESS

5020 FHD F03

5020 FHD F04

Doc. No. 25064-00 2/98 S-1

SDA

SCL

START BIT

STOP BIT

5020 FHD F05

4

Preliminary CAT24WC33/65

I2C BUS PROTOCOL

The features of the I2C bus protocol are defined as
follows:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.

START Condition

The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC33/65 monitors
the SDA and SCL lines and will not respond until this
condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three bits (A2, A1, A0) are the
device address bits; up to eight 32K/64K devices may
to be connected to the same bus. These bits must

compare to the hardwired input pins, A2, A1 and A0. The
last bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.

After the Master sends a START condition and the slave
address byte, the CAT24WC33/65 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC33/65 then performs a Read or Write opera­tion depending on the state of the R/W bit.

Acknowledge

After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg­ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.

The CAT24WC33/65 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiv­ing each 8-bit byte.

When the CAT24WC33/65 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC33/65 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT24WC33/65 to the standby
power mode and place the device in a known state.

Figure 4. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 5. Slave Address Bits

1

START

1 0 1 0 A2 A1 A0 R/W

5

89

ACKNOWLEDGE

5020 FHD F06

5027 FHD F07

Doc. No. 25064-00 2/98 S-1

PreliminaryCAT24WC33/65

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC33/65. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC33/65 acknowledges
once more and the Master generates the STOP condi­tion. At this time, the device begins an internal program­ming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.

Page Write

The CAT24WC33/65 writes up to 32 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31 additional bytes. After each byte has
been transmitted, CAT24WC33/65 will respond with an
acknowledge, and internally increment the five low order
address bits by one. The high order bits remain un­changed.

If the Master transmits more than 32 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.

When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24WC33/65 in a single write cycle.

Acknowledge Polling

Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC33/65 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu­ing the start condition followed by the slave address for
a write operation. If CAT24WC33/65 is still busy with the
write operation, no ACK will be returned. If
CAT24WC33/65 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the bottom 1/4 of the memory
array (locations 000H to 7FFH for the 24WC65 and

Figure 6. Byte Write Timing

BUS ACTIVITY :

MASTER

SDA LINE

Figure 7. Page Write Timing

S
T
A

BUS ACTIVITY :

MASTER

SDA LINE

R

T

S

SLAVE

ADDRESS

S
T
A
R
T

S

A
C
K

SLAVE

ADDRESS

BYTE ADDRESS

A15–A

8

XXX

*

S

BYTE ADDRESS

A15–A

8

XXX

*

A

C

K

A7–A

0

A
C
K

A
C
K

A7–A

0

A
C
K

A
C
K

A
C
K

DATA n

DATA

A
C
K

T
O
P

P

A
C
K

DATA n+31DATA

A
C
K

24WC33/65 F08

S
T
O
P

P

A
C
K

* = Don't care bit for 24WC33
X= Don't care bit

Doc. No. 25064-00 2/98 S-1

24WC33/65 F09

6

Preliminary CAT24WC33/65

locations 000H to 3FFH for 24WC33) is protected and
becomes read only. The CAT24WC33/65 will accept
both slave and byte addresses, but the memory location
accessed is protected from programming by the device’s
failure to send an acknowledge after the first byte of data
is received.

READ OPERATIONS

The READ operation for the CAT24WC33/65 is initiated
in the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current Ad­dress READ, Selective/Random READ and Sequential
READ.

Immediate/Current Address Read

The CAT24WC33/65’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=4095
for 24WC33 and E=8191 for 24WC65), then the counter
will ‘wrap around’ to address 0 and continue to clock out
data. After the CAT24WC33/65 receives its slave ad­dress information (with the R/W bit set to one), it issues
an acknowledge, then transmits the 8 bit byte requested.
The master device does not send an acknowledge, but
will generate a STOP condition.

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi­tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC33/65 acknowledges,
the Master device sends the START condition and the
slave address again, this time with the R/W bit set to one.
The CAT24WC33/65 then responds with its acknowl­edge and sends the 8-bit byte requested. The master
device does not send an acknowledge but will generate
a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC33/65 sends the initial 8­bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC33/65 will continue to output an 8­bit byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.

The data being transmitted from CAT24WC33/65 is
outputted sequentially with data from address N fol­lowed by data from address N+1. The READ operation
address counter increments all of the CAT24WC33/65
address bits so that the entire memory array can be read
during one operation. If more than E (where E=4095 for
24WC33 and E=8191 for 24WC65) bytes are read out,
the counter will ‘wrap around’ and continue to clock out
data bytes.

Figure 8. Immediate Address Read Timing

BUS ACTIVITY :

MASTER

SDA LINE

SCL

SDA 8TH BIT

S

T

A

SLAVE

R

ADDRESS

T

S

89

7

DATA

A
C
K

S
T

O

P

P

N
O
A
C
K

STOPNO ACKDATA OUT

24WC33/65 F10

Doc. No. 25064-00 2/98 S-1

Figure 9. Selective Read Timing

PreliminaryCAT24WC33/65

S
T
A

BUS ACTIVITY :

MASTER

SDA LINE

R
T

S

SLAVE

ADDRESS

A
C
K

* = Don't care for 24WC33
X= Don't care bit

Figure 10. Sequential Read Timing

BUS ACTIVITY:

MASTER

SDA LINE

SLAVE

ADDRESS

A
C
K

A15–A

XXX*

S
T

A
C
K

A
R
T

S

A
C
K

DATA n+2

ADDRESS

BYTE ADDRESS SLA VE

8

A

C

K

A
C
K

DATA n+1

A7–A

0

S
T

DATA

A
C
K

DATA n+xDATA n

A
C
K

O
P

P

N
O
A
C
K

S
T
O
P

P

N
O

A
C
K

24WC33/65 F11

5020 FHD F12

ORDERING INFORMATION

Prefix Device # Suffix

CAT

Optional
Company ID

24WC33

Product
Number

24WC33: 32K
24WC65: 64K

K

Temperature Range

Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*

Package

P: PDIP
K: SOIC (EIAJ)

I

Operating Voltage

Blank: 2.5V - 6.0V

1.8: 1.8V - 6.0V

-1.8

J: SOIC (JEDEC)

Notes:
(1) The device used in the above example is a 24WC33KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating

* -40˚ to +125˚C is available upon request

Voltage, Tape & Reel)

TE13

Tape & Reel

TE13: 2000/Reel

Doc. No. 25064-00 2/98 S-1

8