Rx ASIC RF25A
101110A Conexant – Preliminary 3
August 4, 2000 Proprietary Information
Technical Description
Low Noise Amplifier (LNA). The LNA is designed with a high
gain, low noise figure,and high 3
rd
order input intercept (IIP3)
performance. These parameters canbe optimized with the
mixer gain, noise figure, and IIP3 to achieve the cascade NF
and IIP3 system requirements.RF25A pin 2 isLNA decoupled,
requiring a RF bypasscapacitor to ground with minimal trace
length. Input and outputmatching networks are externalto the
Rx ASIC.
Mixers. The active doublebalanced mixer is designed for high
gain, a low noise figure, and high IIP3performance. The mixer
can also be optimizedfor RF performance to complement the
LNA RF performance, andsatisfy overall Rx NFand IIP3 system
requirements. The LO portoperates with a typicalLO drive level
of -10 dBm. Themixer has a balanced output to drive the IF
SAW filter in CDMA mode, and single-ended output to drive the
IF SAW filter in the AMPS mode.
Variable Gain Amplifier (VGA). Thehigh dynamic range
required by a CDMAhandset is achieved bythe VGA, which has
a minimum dynamic rangeof 90 dB anda control voltage range
from 0.5 to 2.5V. The VGA is common in both modes (CDMA
and AMPS) by switching its internal input buffers.
I/Q Demodulator. The I/Q Demodulator is designed for mobile
handset application. It hasan on-chip generated VHFLO with a
typical operating range of100 to 600 MHz and a typical I/Q
output operating range of 0 to 5 MHz. The I/Q Demodulator is
internally connected to theVGA output, and is fully differential to
reduce common mode noise.DC offsets between differentialI/Q
outputs, and between Iand Q channels, are extremely low to
facilitate compatibility with basebandinterfaces. The
I/Q Demodulator is alsodesigned to have very low amplitude
and phase imbalance.
VHF Oscillator. With external tankcircuits, the VCO p rovides
the LO signal to drive the demodulator, andthe prescaler of an
external Phase Locked Loop (PLL). The oscillator can operate
at two or four times at twice the IF frequency. Usinga selectable
divide ratio, the LOfor the I/Q demodulator is derived. The logic
signal to select thedivider ratio (2 or 4) is available on Pin 13
(DIV2/DIV4).
Mode Control. The operation of the chip is controlled by signals
at Pin 7 (FM/CDMA), Pin 20 (SLEEP), and Pin 13 (DIV2/DIV4).
All the switching is done internally. The supplyvoltage should be
present at all the VCC pins for normal operation. The modes
selected are shown inTable 4.
Electrical and Mechanical Specifications
Included in this documentare Tables 1 through 5 and Figures 1
through 4, which defineand illustrate the electrical and
mechanical specifications of the RF25A.
Table 1: RF25A Pin Assignments and Signal
Descriptions
Table 2: Absolute Maximum Ratings
Table 3: Recommended Operating Conditions
Table 4: Mode Control Select SignalSwitching
Table 5: RF25A RX ASIC Electrical Specifications
Figure 1: RF25A Rx ASIC Pin-out - 40-Pin LGA
6x6mmPackage
Figure 2: RF25A Rx ASIC Block Diagram
Figure 3 – 19: Typical Functional Block Performance
Figure 20: RF25A Schematic Diagram
Figure 21: RF25A Package Dimensions – 40-PinLGA
6x6mmPackage
Figure 22: 40-Pin LGA Tape and Reel Dimensions
ESD Sensitivity
The RF25A is a Class 1 device. The following extreme
Electrostatic Discharge (ESD) precautions arerequired
according to the HumanBody Model (HBM):
• Protective outer garments.
• Handle device in ESD safeguarded work area.
• Transport device in ESD shielded containers.
• Monitor and test all ESDprotection equipment.
The HBM ESD withstand threshold value, with respect to
ground, is ±1.5 kV.The HBM ESD withstand threshold value,
with respect to VDD(the positive power supplyterminal) is also
±1.5 kV.