Conexant CX25800 Data Sheet

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Page 1

CX25800 PCI Video Decoder with Mono

Audio Input

Data Sheet

DSH-201233A July 2007

Page 2

Ordering Information

Model Number Description Package

CX25800 176-pin LQFP

Revision History

Revision Date Description

A July 2, 2007 Initial Release

Operating

Temperature

0 to +70

Minimum

Order

Quantities

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2 Conexant DSH-201233A

Conexant Proprietary and Confidential 7/3/07

Page 3

Preliminary Information

This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices.

CX25800

PCI Video Decoder with Mono Audio Input

The CX25800 is a highly flexible single chip solution that enables video and audio capture over a PCI bus. Designed for surveillance applications, the CX25800 accepts analog NTSC and PAL video from cameras, as well as line-level mono audio inputs from microphones. The CX25800 enables audio/video capture and playback on PCbased Digital Video Recorders (DVRs). The CX25800 also supports a variety of peripheral connectivity options via its GPIO pins, BT.656, I

S, MPEG port, and host

port interfaces.

Functional Block Diagram

From

Video

Format

Converter

Serial

Bus

Video

Decompressor

656/VIP 2.0

Pixel Input

Scaler

Pixel

Engine

Audio FIFO

DMA

FIFO

GPIO

Video FIFO

DMA

FIFO

Host Port

DMA

FIFO

ViP 2.0

Host Port

PCI Interface

PCI Bus

Composite 1

Composite 2

Composite 3

Video

Composite

Composite 4

Audio

Stereo Right

Broadband/

Audio In

S Out

Stereo Left

Serial or

Parallel

Data

MPEG

Compressor

656 Pixel

Output

10-Bit

ADC

Decode

10-Bit

ADC

S In

ADAC

JTAG

Decode

Data FIFO

Video

Audio

Clocks

and PLL

Scaler

and SRC

DMA

Distinguishing Features

Video Subsystem

 10-bit video ADCs  NTSC and PAL Composite video

formats

 Capture resolution up to 720x576

(Square Pixel PAL)

 NTSC and PAL adaptive comb filter

for 2-D Y/C luminance and chrominance separation

 AGC video circuit  Multiple YCrCb and RGB pixel

formats and YUV planar formats support on output

 Selectable pixel density: 16 and 24

bits per pixel

 Complex clipping of video source

and VGA video overlay

 Allowance for different program

control and color space/scaling for even and odd fields

 Support of Windows “Scatter/

Gather” DMA

 High-quality multitap horizontal and

vertical image scaler for decoded video or 4:2:2 sources

 ITU-R BT.656 8-bit or 10-bit 4:2:2

output port

 ITU-R BT.656/VIP 2.0 pixel input

port

 Flexible VBI data capture for closed

captioning, teletext, and other analog data types

 Hue, brightness, contrast,

saturation control for video decoder

(Continued on the next page)

DSH-201233A Conexant 3 7/3/07 Conexant Proprietary and Confidential

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Distinguishing Features (continued)

Audio Subsystem

 10-bit A/D for mono analog audio

input

 Decoded 48 kHz audio stream to

PCI bus for real time encoding to MP3

 Integrated 90 dB SNR stereo

audio DACs to drive sound card or headphones

 I

S input port for external source connectivity to on-board stereo DACs

 I

S output port to drive coaxial/ optical digital audio interface

 Flexible audio sample rate

converter

Multipurpose I/O Subsystem

 Bidirectional 33 MBps VIP 2.0

Host port

 Bidirectional 10 MBps Intel/

Motorola-compatible General Purpose Host port

 Unidirectional 10 MBps parallel/

serial MPEG Transport/Data Stream port- compatible with all Conexant digital television channel demodulator ICs.

 MPEG Packet Synchronization  User-defined General Purpose

Input/Output pins

PCI Subsystem

 5 independent functions each with

Target/Master and Local register space (Video, Audio, MPEG Port, VIP 2.0 Host Port, GP Host Port)

 All RISC/Control programs

executed on-chip

 On-chip SRAM for PCI data

buffering Up/Down

 Vital product data  DMA byte alignment  PCI revision 2.3-compliant

Miscellaneous

 ACPI and power-down support  Only one crystal for all video and

audio decoding required

 400 kHz serial bus master  JTAG boundary scan interface  Compact 176-pin LQFP

Applications

 Surveillance camera systems

DSH-201233A Conexant 4 7/3/07 Conexant Proprietary and Confidential

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Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15

1.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.2 Detailed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.2.1 Analog Video Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.2.1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.2.1.2 Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.2.1.3 Image Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.2.1.4 Reduced Instruction Set Computer Engine . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.2.1.5 UltraLock™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.2.1.6 Vertical Blanking Interval (VBI) Data Capture. . . . . . . . . . . . . . . . . . . . . . . . 17

1.2.2 Analog Audio Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.2.3 ITU-R 656 4:2:2 Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.2.4 ITU-R 656/VIP 2.0 Pixel Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.2.5 MPEG Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.2.6 General Purpose Host Interface Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.2.7 GPIO Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2.8 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2.9 PCI Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27

2.1 Audio Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.1.2 Analog Input ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.1.3 Audio PLL Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.1.4 Input Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.1.5 Audio Control and Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.1.5.1 Audio Demodulator Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . 29

2.1.5.2 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.1.5.3 Balance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.1.6 I

DSH-201233A Conexant 5 7/3/07 Conexant Proprietary and Confidential

S Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.1.6.1 I

2.1.6.2 I

S Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

S Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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CX25800 Data Sheet

2.1.7 I2S Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.1.7.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.1.7.2 OSR DAC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.1.7.3 OSR ADC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.1.7.4 Passthrough Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.1.7.5 Full Functionality Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.1.8 Audio DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2 General Purpose Host Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.2 Host Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.3 General Purpose Host Port Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.2.4 General Purpose Host Port Interface Register Access . . . . . . . . . . . . . . . . . . . . . . . 46

2.2.5 General Purpose Host Interface External DMA Transfers. . . . . . . . . . . . . . . . . . . . . 46

2.2.6 General Purpose Host Interface Signaling—Nonmultiplexed Mode . . . . . . . . . . . . . 47

2.2.7 General Purpose Host Interface Signaling—Multiplexed Mode. . . . . . . . . . . . . . . . . 49

2.3 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.3.1 GPIO Pin Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.3.2 GPIO Modes in CX25800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.3.3 GPIO Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2.3.4 MPEG Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.3.5 8-Bit Parallel VIP Host Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.3.6 4-Bit Parallel VIP Host Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.3.7 Video Synchronous Pixel (SPI) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

2.3.8 10-Bit ITU-R. BT656 Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

2.3.9 8-Bit ITU-R. BT656/VIP 2.0 Pixel Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.3.10 Host Port Chip Select Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.4 Peripheral Component Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.4.1 PCI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.4.2 PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.4.3 PCI Subsystem IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.4.4 Accessing VPD on the CX25800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.4.5 PCI Specification Regarding VPD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.4.6 Using VPD Data with Multiple Functions on One Card . . . . . . . . . . . . . . . . . . . . . . . 64

2.4.7 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.4.8 Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

2.4.9 PCI Data Streaming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

2.4.10 SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2.4.11 FIFO Size Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.4.12 Programmable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.4.13 RISC Instruction Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

2.4.14 Channel Management Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.4.15 RISC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2.4.16 RISC Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2.4.17 Data Stream Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2.4.18 Data Stream User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2.4.19 PCI Master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

2.5 MPEG Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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CX25800 Data Sheet

2.5.1 Video Compressors/Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

2.5.2 Serial vs. Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

2.5.3 MPEG ES (Elementary Stream). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

2.6 Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.6.1 Video Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.6.2 10-bit Video Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.6.3 Video Signal Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.6.3.1 UltraLock Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

2.6.4 Video Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.6.4.1 Flexible Video Timing Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.6.5 Composite Video Input Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

2.6.6 Y/C Separation and Chroma Demodulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

2.6.6.1 The Y/C Separation Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

2.6.6.2 Conexant Adaptive Comb Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

2.6.7 Y/C Separation and Chroma Demodulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

2.6.8 Video Scaling, Cropping, and Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . 101

2.6.8.1 Down-Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

2.6.8.2 Vertical Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

2.6.8.3 Chrominance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

2.6.8.4 Video Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

2.6.8.5 The Horizontal Scaling Ratio (HSCALE) Register . . . . . . . . . . . . . . . . . . . 108

2.6.8.6 The Vertical Scaling Ratio Register (VSCALE) . . . . . . . . . . . . . . . . . . . . . 109

2.6.9 Image Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

2.6.10 Cropping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

2.6.10.1 Horizontal Delay Register (HDELAY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

2.6.10.2 Horizontal Active Register (HACTIVE). . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

2.6.10.3 The Vertical Delay Register (VDELAY). . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2.6.10.4 The Vertical Active Register (VACTIVE). . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2.6.11 Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2.6.12 Video Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2.6.12.1 The Hue Adjust Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2.6.12.2 The Contrast Adjust Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2.6.12.3 The Saturation Adjust Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2.6.12.4 The Brightness Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2.6.12.5 Automatic Chrominance Gain Control (ACGC) . . . . . . . . . . . . . . . . . . . . . 114

2.6.13 Low Color Detection and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2.6.14 Coring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2.6.15 VBI Data Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

2.6.16 VBI Line Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

2.6.17 ITU-R656 Output Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

2.6.18 ITU-R656/VIP 2.0 8-bit Pixel Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

2.7 VIP 2.0 Host Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

2.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

2.7.2 VIP 2.0 Host Master Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

2.7.3 VIP 2.0 Host Master System Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

2.7.3.1 Downstream DMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

2.7.3.2 Upstream DMA Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

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2.7.3.3 VIP External Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

2.7.3.4 VIP Local Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

2.7.4 VIP Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

2.7.5 VIP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

3 Electrical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 131

3.1 Input Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.1.1 Analog Signal Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.1.2 Multiplexer Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.1.2.1 ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.1.3 Power-Up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3.1.4 Crystal Inputs and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

3.1.5 Audio Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

3.2 Serial Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

3.2.1 Serial Bus Serial EEPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

3.2.2 EEPROM Upload at PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

3.2.3 Register Load from BIOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

3.3 Vital Product Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

3.3.1 Required VPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

3.3.2 VPD Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

3.3.3 VPD Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

3.3.4 VPD Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

3.3.5 VPD Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

3.4 Power Management Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

3.4.1 PME#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

3.4.2 D3 Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

3.5 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

3.5.1 Need for Functional Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

3.5.2 JTAG Approach to Testability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

3.5.3 Optional Device ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

3.5.4 Verification with the TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

4 PC Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 147

4.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

4.1.1 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

4.1.2 Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.1 PCI Configuration Registers: Function 0: Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.2 PCI Configuration Registers: Function 1: Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.3 PCI Configuration Registers: Function 2: MPEG TS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

5.4 PCI Configuration Registers: Function 3: VIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

5.5 PCI Configuration Registers: Function 4: Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

5.6 Memory Mapped Registers: Miscellaneous Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

5.7 Memory Mapped Registers: Function 0: Video. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

5.8 Memory Mapped Registers: Function 1: Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

5.9 Memory Mapped Registers: Function 2: MPEG TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

5.10 Memory Mapped Registers: Function 3: VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

5.11 Memory Mapped Registers: Function 4: Host. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

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6 Electrical and Mechanical

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

6.1 DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

6.2 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

6.3 Package Mechanical Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

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Figures

Figure 1. CX25800 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. CX25800 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 3. Simplified Block Diagram of CX25800 Audio Subsystem . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 4. Normal Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 5. OSR DAC Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 6. OSR ADC Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7. Passthrough Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8. Full Functionality Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 9. Host Interface Write Operation—Intel Style (Accessing an External Device) . . . . . . . . . 47

Figure 10. Host Interface Write Operation—Motorola Style (Accessing an External Device) . . . . . 47

Figure 11. Host Interface Read Operation—Intel Style (Accessing an External Device) . . . . . . . . . 48

Figure 12. Host Interface Read Operation—Motorola Style (Accessing an External Device) . . . . . 48

Figure 13. Host Interface Read Operation—Intel Style Multiplexed Address/Data Bus (Accessing an

External Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 14. Host Interface Read Operation—Motorola S tyle Multiplexed Address/Da ta Bus (Accessing

an External Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 15. Host Interface Write Operation—Intel Style Multiplexed Address/Data Bus (Accessing an

External Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 16. Host Interface Write Operation—Motorola S tyle Multiplexed Address/Dat a Bus (Accessing

an External Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 17. GPIO Pin Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 18. MPEG Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 19. 8-bit Parallel VIP Host Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 20. Video Synchronous Pixel (SPI) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 21. 10-bit ITU-R. BT656 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 22. 8-bit ITU-R. BT656/VIP 2.0 Pixel Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 23. Host Port Chip Select Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 24. SRAM Resource Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 25. Channel Management Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 26. SYNC Downstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 27. WRITE Downstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 28. WRITEC Downstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 29. READ Upstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 30. READC Upstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 31. SKIP RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 32. Jump RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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Figure 33. WRITERM RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 34. WRITECM RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 35. WRITECR RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 36. MPEG Port Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 37. UltraLock Behavior for NTSC Square Pixel Output using 4x Fsc Sampling Rate . . . . . 88

Figure 38. UltraLock and Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 39. Y/C Separation and Chroma Demodulation Circuit for Composite NTSC/PAL Video . . 93 Figure 40. Luma Notch Filter Frequency Responses for NTSC and PAL @ 4x Fsc Decoding Frequen-

cies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 41. Luma Notch Filter Frequency Responses for NTSC and P AL @ Square Pixel Decoding Fre-

quencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 42. Luma Notch Filter Frequency Responses for NTSC and PAL @ 13.5-MHz Decoding Fre-

quency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 43. Chroma Band Pass Filter Frequency Responses for NTSC and PAL @ 4x Fsc Decoding

Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 44. Chroma Band Pass Filter Frequency Responses for NTSC and PAL @ Square Pixel De-

coding Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 45. Chroma Band Pass Filter Frequency Responses for NTSC and P AL @ 1 3.5-MHz Decoding

Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 46. Optional Horizontal Luma Low-Pass Filter Responses for NTSC . . . . . . . . . . . . . . . . 102

Figure 47. Optional Horizontal Luma Low-Pass Filter Responses for PAL. . . . . . . . . . . . . . . . . . . 103

Figure 48. Combined Luma Notch 2x Oversampling and Optio nal Low-Pass Filter Response for NTSC

104 Figure 49. Combined Luma Notch 2x Oversampling and Optiona l Lo w- Pass Filter Re spon se for PAL/

SECA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 50. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters . . . . . . . 106

Figure 51. NTSC Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 52. PAL Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 53. Effect of the Delay and Active Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 54. Regions of the Video Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 55. Coring Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 56. Regions of the NTSC Video Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 57. Regions of the PAL Video Frame (Fields 1, 2, 5, and 6) . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 58. VBI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 59. Video ITU-R 656 Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 60. MPEG 2 Decoder to CX25800 ITU-R656 Connection, Example 1 . . . . . . . . . . . . . . . . 119

Figure 61. MPEG 2 Decoder to CX25800 ITU-R656 Connection, Example 2 . . . . . . . . . . . . . . . . 119

Figure 62. Data Transfer fro m VIP 2.0 Slave to Host through CX25800 . . . . . . . . . . . . . . . . . . . . 127

Figure 63. Data Transfer from Host to VIP Slave through CX25800 . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 64. VIP External Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 65. Resistor-Divider Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 66. Fundamental Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 67. 3rd Overtone Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 68. Crystal Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 69. Audio Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 70. The Relationship Between SIC and SID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 71. Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 72. JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 73. 176-pin TQFP Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

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Tables

Table 1. Pin Descriptions Grouped by Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 2. CX25800 Applications Enabled by Host Port Peripherals. . . . . . . . . . . . . . . . . . . . . . . . 38

Table 3. GPHP Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 4. GPHP Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 5. GPIO Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 6. GPIO Mode Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 7. GPIO Mode versus Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 8. PCI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 9. CX25800 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 10. MA Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 11. Channel Management Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 12. SOL/EOL Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 13. WRITERM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 14. Video Decoding Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 15. Sample Rate Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 16. Video Input Formats Supported by the CX25800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 17. Register Values for Square Pixel Video Input Formats. . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 18. Scaling Ratios for Popular Formats Using Frequency Values. . . . . . . . . . . . . . . . . . . . 110

Table 19. 4x Fsc Pixel Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 20. VIP Host Master Interface Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 21. Memory VIP Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 22. EEPROM Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 23. VPD Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 24. VPD Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 25. VPD Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 26. Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 27. Register Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 28. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 29. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Table 30. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Table 31. Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table 32. Power Supply Current Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table 33. JTAG Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

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CX25800 Data Sheet

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Product Overview

1.1 Functional Overview

The CX25800 is implemented as a multifunction PCI bus master and fabricated in an advanced CMOS process operating from +3.3 V I/P and 1.8 V (digital core) power supplies. PCI inputs are +5 V and 3.3 V tolerant.

The CX25800 is designed to enable high-functionality broadcast- centric PC cards that require high speed Input/Output (I/O) capability. This capability is necessary to support simultaneous compressed and uncompressed digital video/audio data flows in conjunction with hardware MPEG II/MPEG IV encoders and decoders.

Figure 1 illustrates a block diagram of the CX25800.

Figure 1. CX25800 Detailed Block Diagram

MPEG TS/

PS/LES,

Broadband Data

Broadband,

MPEG Port

Baseband

Audio

Output

Digital

Audio/ SPDIF Output

Sout I2Sin

Digital Audio/ SPDIF

Input

Audio

Input

Composite

Video

Video MUX

User

Configurable

1–24 GPI/O

Available

9 MBps

Bidirectional

General

Purpose

Host Port

JTAG

Clocks

and PLL

Serial

Bus

GPI/O

16-Bit

Intel/ Motorola Host Port

DMA

16-Bit Audio DAC

PCI Bus Interface Bridge

FIFO

DMA

PCI Bus

10-Bit

ADC

Audio

Control

and

Format

Conversion

FIFO FIFO FIFOFIFO

DMA DMA DMA

10-Bit

ADC

NTSC/PAL

Decoder, Adaptive

Comb Filter and

Scaler

Pixel

Engine

AGC

Scaler

VIP 2.0

Host Port

Interface

8-Bit or 10-Bit CCIR 656 Output

8-Bit CCIR 656 8-Bit VIP 2.0 Pixel Port

33 MBps Bidirectional Interface

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Product Overview CX25800 Data Sheet

1.2 Detailed Features

1.2.1 Analog Video Capture

1.2.1.1 Overview

The CX25800 integrates a 10-bit NTSC/PAL composite video decoder, image resizer/ scaler, Direct Memory Access (DMA) controller, and Peripheral Component Interface (PCI) Bus master on a single device. The CX25800 can place video data directly into host memory for video capture applications and into a target video display frame buffer for video overlay applications. As a PCI initiator, the CX25800 can take control of the PCI bus as soon as it is available, thereby avoiding the need for onboard frame buffers. The CX25800 contains a pixel data First In, First Out (FIFO) to decouple the high-speed PCI bus from the continuous video data stream. The video data input can be scaled, color-translated, and burst-transferred to a target location on a field basis.

1.2.1.2 Input Interface

Analog video signals are input to the CX25800 through a four-input multiplexer. An Automatic Gain Control (AGC) circuit enables the CX25800 to compensate for nonstandard amplitudes in the analog signal input.

1.2.1.3 Image Scaler

The CX25800 can reduce the video image size in both horizontal and vertical directions independently, using arbitrarily selected scaling ratios. The X and Y dimensions can be scaled down to one-sixteenth of the full resolution. Horizontal scaling is implemented with a six-tap interpolation filter, while up to five-tap interpolation is used for vertical scaling with a line store. The video image can be arbitrarily cropped by reducing the number of active scan lines and active horizontal pixels per line. The CX25800 supports a temporal decimation feature that reduces video bandwidth. This is accomplished by allowing frames or fields to be dropped from a video sequence at fixed but arbitrarily selected intervals.

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CX25800 Data Sheet Product Overview

1.2.1.4 Reduced Instruction Set Computer Engine

The CX25800 enables separate destinations for the odd and even video fields, each controlled by a pixel Reduced Instruction Set Computer (RISC) instruction list. This instruction list is created by the CX25800 device driver and can be run in the onboard memory or host memory. The instructions control the transfer of pixels to target memory locations on a byte resolution basis. Complex clipping can be accomplished by the instruction list, blocking the generation of PCI bus cycles for pixels that are not to be seen on the display.

The DMA channels can be programmed on a field basis to deliver the video data in packed or planar format. In packed mode, YCrCb data is stored in a single continuous block of memory. In planar mode, the YCrCb data is separated into three streams which are burst to different target memory blocks. Having the video data in planar format is useful for applications where the data compression is accomplished through software and the CPU.

1.2.1.5 UltraLock™

The CX25800 employs a proprietary technique known as UltraLock to lock to the incoming analog video signal. It always generates the required number of pixels per line from an analog source in which line length can vary by as much as a few microseconds. UltraLock's digital locking circuitry enables the CX25800 to lock onto video signals quickly and accurately, regardless of their source. Because the technique is completely digital, UltraLock can recognize unstable signals caused by VCR head switches or any other deviation and adapt the locking mechanism to accommodate the source. UltraLock uses nonlinear techniques that are difficult, if not impossible, to implement in genlock systems. And, unlike linear techniques, it adapts the locking mechanism automatically.

1.2.1.6 Vertical Blanking Interval (VBI) Data Capture

The CX25800 provides a flexible solution for capturing and decoding disparate VBI data types such as closed caption data, teletext, Vertical Internal Time and Control (VITC) codes, HTML data, or multicast data. The CX25800 can operate in a VBI Line Output mode, in which the VBI data is only captured during selected lines. This mode of operation enables concurrent capture of VBI lines containing ancillary data and normal video image data. In addition, the CX25800 supports a VBI Frame Output mode in which every line in the video frame is treated as if it were a VBI line. This mode of operation is designed for use with still-frame capture and processing applications where sophisticated image decoding can be performed in the software domain.

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Product Overview CX25800 Data Sheet

1.2.2 Analog Audio Capture

The CX25800 captures mono analog audio. The decoded audio is sample-rate converted to a 48-kHz Pulse Code Modulation (PCM) signal to simplify processing and interfacing. This 48-kHz stream can be routed to the built-in +85 dB Signal-to-Noise Ratio (SNR) stereo audio Digital-to-Analog Converters (DACs) for connection to the PC's sound card or headphones, to an external digital-audio interface, or to the PCI bus and host for direct capture by a software audio codec.

If capture of line-level stereo audio signals is required, an inexpensive audio Analogto-Digital Converter (ADC) can be directly connected to the CX25800's I and controlled through the serial bus master.

S input port

1.2.3 ITU-R 656 4:2:2 Data Output

The CX25800 provides a 27-MHz, 8- or 10-bit ITU-R 656 decoded video output interface to allow connection of a third-party MPEG II encoder or other type of video codec. This is useful when the host CPU is not powerful enough to perform such tasks in software, or when high-quality encoding must be achieved.

1.2.4 ITU-R 656/VIP 2.0 Pixel Data Input

The CX25800 provides a 27-MHz, 8-bit ITU-R 656 decoded video input interface. This allows a third-party MPEG II decoder or codec to send 4:2:2 data over the PCI bus to a target video display frame buffer for video overlay.

1.2.5 MPEG Data Port

Channel demodulators used for digital television or broadband data applications over terrestrial, satellite, or cable networks can be directly connected to the CX25800's MPEG data port. As a result, transport streams can be delivered to the host for subsequent storage to disk or software decode. Either parallel, common-interface Digital Video Broadcasting (DVB) or serial data paths from the channel demodulator can be supported at data transfer rates of up to 80 Mbps. If the serial interface mode is used, the remaining unused pins on this port can be allocated as General Purpose Input/Output (GPIO).

1.2.6 General Purpose Host Interface Port

The General Purpose Host interface allows connection of moderate-to-relatively slowspeed, third party peripherals such as infrared remote control processors, codec host ports, smart card controllers (etc.). This port allows simultaneous connection to two peripherals gluelessly, or to as many as four peripherals with the use of external glue logic to provide the additional chip selects. This interface can have one upstream and one downstream DMA channel active to or from the external peripherals at any given time. Data bursting is not supported.

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CX25800 Data Sheet Product Overview

1.2.7 GPIO Port

The CX25800 provides up to 24 GPIO pins. These GPIO pins are shared with the following pins/ports groups so that the user can determine exactly which pins can be dedicated to specific functions versus general purpose I/O functions.

1. MPEG Parallel Data Port

2. ITU–R 656 4:2:2 Data Output

3. ITU–R 656 4:2:2 Data Input

4. Extended VIP Host Port

5. Extended General Purpose Host Port (GPHP)

1.2.8 Serial Bus Interface

The CX25800's serial bus interface supports both 99.2-kHz timing transactions and

396.8-kHz, repeated start, multibyte sequential transactions. As a serial bus master, the CX25800 can program other devices on the video card, such as MUXs, as long as the device address is known. The CX25800 supports multibyte sequential reads (more than one transaction) and multibyte write transactions (greater than three transactions), which enable communication to devices that support auto-incremental internal addressing.

1.2.9 PCI Bus Interface

The CX25800 is designed to efficiently utilize the available 132 MBps PCI bus. The 32-bit dwords are output on the PCI bus with the appropriate image data under the control of the DMA channels. The video stream consumes bus bandwidth with average data rates varying from 44 MBps for full-size 768 576 PAL RGB32, to 4.6 MBps for NTSC CIF 320 240 RGB16, to 0.14 MBps for NTSC ICON 80 60 8-bit mode.

The pixel instruction stream for the DMA channels consumes a minimum of 0.1 MBps. The CX25800 provides the means for mitigating bandwidth bottlenecks caused by slow targets and long bus access latencies that can occur in some system configurations. To overcome these system bottlenecks, the CX25800 gracefully degrades and recovers from FIFO overruns to the nearest pixel in real time.

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Product Overview CX25800 Data Sheet

1.3 Pin Descriptions

Figure 2 displays the CX25800 pinout diagram. Table 1 provides a description of pin

functions grouped by common function.

Figure 2. CX25800 Pinout Diagram

SVAL/ERR

SDAT

PIO

G G

PIO

GPIO

PIO

G G

PIO PIO

PIO

HAD

V V

HAD

AD[31] A A A A A A A

AD[23] A A A AD[19] A

SCLK

SSOP

DDIO

[23] [22] [21] [20] [19] [18] [17] [16]

HCTL

IRQ#

IPCLK

NTA

R GNT

DDIO

[30]

[29]

D[28] D

[27]

[26]

[25]

[24] [3]#

DSEL

[22]

[21]

[20]

[18]

RSTO

174

173

172

171

170

TCKT

169

168

167

SCKO

LRCKOADATOASCKIALRCKIADATI

175

176

1 2 3

[0]

4 5

7 8 9 10 11 12 13 14 15 16

[1] [0]

17 18 19 20 21

# #

23 24

26 27

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

GNDAGDA

164

165

166

ACSO

163

REF

162

REF

161

ASCO

ADA

159

160

REFX

158

157

156

REFP

155

REFN

BGOUT

154

153

AUDIO_IN

151

152

RESERVED

150

GND

149

GASH

148

AASH

147

SUB

146

MUX

145

MUX

144

MUX

143

MUX

142

141

REFN

140

REFP

139

138

137

GXTL

136

135

134

AXTL

133

132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89

S S

PIO

GPIO G

PIO

PIO PIO

G G

PIO PCLKI

G V

DDIO

PIO

PIO PIO

G G

PIO PIO

G G

PIO PIO

G G

PCLKO

AD AD

H H

PP1 GND

DDIO

H H

AD AD

H H

AD AD

H HRD/

[0] [1] [2] [3] [4] [5] [6] [7]

[8] [9] [10] [11] [12] [13] [14] [15]

[0] [1] [2] [3] [4]

[5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] #

HDS

[17]

[16]

[2]#

RDY

RAME

DDIO

RDY

TOP

EVSEL

ERR

[15]

[14]

[13]

DDIO

[9]

[8]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[12]

[11]

[10]

[0]#

[1]#

DDIO

EXFB

ALE

RDY

HRW

VDD: 1.8 V digit al core suppl y Vpp,Pgnd: 1.8 V PLLs supply, ret urn Vddio: 3.3 V di git al I/ O supp ly Gnd: Digital core, I/O return supply VIO: PCI 5 V d i od e cl amp su pp ly

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CX25800 Data Sheet Product Overview

Table 1. Pin Descriptions Grouped by Pin Function (1 of 6)

Pin Number Pin Name Dir Type Signal Description

PCI Interface (50 Pins)

63 CLK I — Clock All PCI signals except RST# and INTA# are

sampled on the rising edge of this 33.3333 MHz clock.

22 RST# I — Reset Bus reset causes all PCI outputs to

asynchronously three-state. 23 REQ# O t/s Request Agent requests bus. 24 GNT# I — Grant Agent grants bus. 37 IDSEL I — Initialization Device

Select

[28–35, 38–43,

AD[31:0] I/O t/s Address/Data Address phase when FRAME# is 1st 48, 49, 60–62, 68–72, 74–81]

[36, 50, 59, 73] CBE[3:0]# I/O t/s Bus Command/

Byte Enables

Selects device during configuration read and write transactions.

asserted, and data transfer when IRDY# and TRDY# are both asserted.

Bus transaction-type command during address phase, and byte enables during entire data phase.

58 PAR I/O t/s Parity Even parity across {AD, C/BE#}, lags

address/data phase

51 FRAME# I/O s/t/s Cycle Frame Asserted to begin bus transaction.

Deasserted when transaction in final data phase.

52 IRDY# I/O s/t/s Initiator Ready Indicates the initiator is ready to accept read

data or has placed valid write data on the AD.

53 TRDY# I/O s/t/s Target Ready Indicates the target is rea dy to accept write

data or has presented valid data on AD during a read.

54 DEVSEL# I/O s/t/s Device Select Indicates the driving device has decoded

the address as the target of the current access.

55 STOP# I/O s/t/s Stop Target requesting master to stop current

transaction. 56 PERR# I/O s/t/s Parity Error Report data parity error. 57 SERR# O t/s System Error Report address parity or system error. 21 INTA# O t/s Interrupt A Request an interrupt.

JTAG Signals (4 Pins)

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Product Overview CX25800 Data Sheet

Table 1. Pin Descriptions Grouped by Pin Function (2 of 6)

Pin Number Pin Name Dir Type Signal Description

169 TCK I — Test Clock Used to synchronize all JTAG test

structures. Tie low when not using JTAG. 168 TMS I r Test Mode Select Transitions drive JTAG state machine

sequence. Tie high or leave floating when

not using JTAG. A fixed sequence on this

pin initializes the JTAG tap controller. 167 TDI I r Test Data In Load input instructions and/or test vector

data for boundary scan and internal scan.

Tie high or leave floating when not using

JTAG. 158 IREFX—TDO O Test Data Out Output for verifying JTAG serial operations.

The output is three-stated when not using

JTAG port.

VIP 2.0 Host Master Signals (5 or 11 Pins)

16, 17 8–15

VHAD[1:0] GPIO[23:16]

I/O — VIP Host Address/

Data

VIP Address and Data bus, defaults to

VIP1.1 interface with 2 addr/data pins. Can

(1)

be configured as VIP 2.0 with 8 address/

data pins (GPIO). 18 VHCTL I/O — VIP Host Control VIP System Host control 19 VIRQ# I/O od VIP Interrupt

VIP Interrupt Request (open drain)

Request

20 VIPCLK O — VIP Clock VIP master output clock. This clock is

buffered. PCI CLK = 33.3333 MHz.

Transport Stream Signals (4 or 11 Pins)

4TSDAT[0]

3 TSSOP I — Transport Stream

(2)

I — Transport Stream

Data

Start of Packet

Transport Stream Input data bus. TSDAT[0]

is used in serial mode.

Transport Stream Start-of-Packet indicator.

Indicates first byte in serial or parallel

transport packet. 2 TSVAL/ERR I — Transport Stream

Transport Stream Error or Valid indicator

Error/Valid

1 TSCLK I — Transport Stream

Clock

Transport Stream input clock. All other

transport stream inputs are sampled on the

rising (falling) edge of TSCLK.

Host Master Signals (22 Pins)

[91–101, 106– 110]

HAD[15:0] I/O — General Purpose

Host Address/Data

Bidirectional address/data access bus

90 HCS# O — General Purpose

External chip select

Host Chip Select

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CX25800 Data Sheet Product Overview

Table 1. Pin Descriptions Grouped by Pin Function (3 of 6)

Pin Number Pin Name Dir Type Signal Description

89 HRD#/

HDS#

O — General Purpose

Host Read/Data Strobe

88 HALE# O — General Purpose

Host Address Latch Enable

87 HWR/

HRW#

O — General Purpose

Host Write/Read, not Write

86 HRDY# I r General Purpose

Host Ready

85 HEXFB I r General Purpose

Host External Status

GPIO/Serial Bus/Reset (29 Pins)

[8–15, 112–119,

GPIO[23:0] I/O I/O GPIO See GPIO Cross-Reference Table.

123–130] 122 GPCLKI I I General Purpose

Input Clock

111 GPCLKO O O General Purpose

Output Clock

Either the active-low read signal or the

programmable polarity data strobe signal

Address Latch Enable signal, used only in

multiplexed 16-bit address/data mode

Either the active-low write signal or the

read/write bar

External data transfer acknowledge signal

Handshaking signal for use in DMA mode to

indicate the status of the external source or

destination FIFO.

Digital Video Input Reference clock

Digital Video Output Reference clock

132 SID I/O od Serial Data Bit data or acknowledge 131 SIC I/O od Serial Clock Bit clock 170 SYS_RSTO# O t/s System Reset Out Logical PCI reset, soft reset, or power-on

reset output. This is used to reset

CX25800’s peripheral under software

control or with hard reset.

Digital Audio (6 Pins)

171 ADATI I r Audio Data In Bit Serial Input data 172 ALRCKI I r Audio Left/Right

Left/Right Framing Input clock

Clock In

173 ASCKI I r Audio Serial Clock

Bit Serial Input clock

Input 174 ADATO O r Audio Data Out Bit Serial Output data 175 ALRCKO O r Audio Left/Right

Left/Right Framing Output clock

Clock Out

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Product Overview CX25800 Data Sheet

Table 1. Pin Descriptions Grouped by Pin Function (4 of 6)

Pin Number Pin Name Dir Type Signal Description

176 ASCKO O r Audio Serial Clock

Bit Serial Output clock

Output

Crystal Interface Signals (4 Pins)

134 XT2 O — XT2 Crystal oscillator pin 135 XT1 I — XT1 Crystal oscillator or clock oscillator input pin

can be connected to XT1.

133 VAXTL — — PSUP_XTAL XTAL and Sample and Hold digital power/

ground. Nominal VA = 3.3 V.

136 AGXTL — — NSPU_XTAL

ADC Interface (23 Pins)

[145:142] VMUX[1:4] I A Video Mux {1:4} Analog composite video inputs to the on-

chip 4:1 analog multiplexer. Leave unused inputs No Connect. Grounding unused

inputs may draw excessive power. 150 Reserved Leave this pin No Connect 151 AUDIO IN I A Audio IN Analog audio input. Leave unused input No

Connect or connected to ground via a

decoupling capacitor. Grounding this input

may draw excessive power. 138

156 140

154 139

155

VCM1 VCM2

VREFN1 VREFN2

VREFP1 VREFP2

O A VCM_ADC{1:2} Common mode voltage reference

O A VREFN{1:2} Input Negative reference (1.0 V)—one for

each Y and C/Aud ADCs, cap to AGA.

O A VREFP{1:2} Input Positive reference (1.8 V)—one for

each Y and C/Aud ADCs, cap to AGA. 153 VBGOUT O A VBGOUT Voltage reference 1.21 V nominal, cap to

AGA. 137, 157 VAA{1:2}CR — A VAA{1:2}CR A/D core power/ground. Nominal

VA = 3.3 V 141, 152 AGA{1:2}CR — A AGA{1:2}CR

146 ASUB — — ASUB A/D core substrate (ground) 147 VAASH — — PSUPA_SHA_ADC A/D Sample and Hold Analog power/

ground. Nominal VA = 3.3 V. 148 AGASH — — NSUPA_SHA_ADC

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CX25800 Data Sheet Product Overview

Table 1. Pin Descriptions Grouped by Pin Function (5 of 6)

Pin Number Pin Name Dir Type Signal Description

149 VGND I A/D Virtual Ground Single-end-to-differential converter input for

common-mode noise rejection. Connect to

analog ground through 3.3 μF series

capacitor. 105, 165 VPP1/VPP2 — — VPP1, VPP2 PLL power supply. VD = 1.8 V. 104, 166 PGND — — PGND PLL return supply 158 IREFX_TDO I/O A/D IREF_EXT/TDO Shared analog current ref pin JTAG TDO

Audio Output DAC Signals (6 Pins)

159 VADA — — VADA DAC analog core power and ground.

VA = 3.3 V 164 AGDA — — AGDA

163 LASCO O A LASCO DAC Pulse Width Modulator (PWM), left

stereo audio output channel 160 RASCO O A RASCO DAC PWM, right stereo audio output

channel 161 PWM_REF2 O A PWM_REF2 Audio DAC reference, right 162 PWM_REF1 O A PWM_REF1 Audio DAC reference, left

I/O and Core Power and Ground (23 Pins)

6, 26, 45, 65, 83, 103

7, 27, 44, 64, 82,

VDD — — VDD Digital core power supply. Nominal

VDD = 1.8 V.

GND — — GND Ground for digital core (GND)

120 5, 25, 46, 66, 84,

102, 121

VDDIO — — VDDI and VDDO Digital inputs/outputs power supply.

VD = 3.3 V. 47, 67 VIO — — VIO +5 V reference for 5 V-tolerant PCI input

buffers

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Product Overview CX25800 Data Sheet

Table 1. Pin Descriptions Grouped by Pin Function (6 of 6)

Pin Number Pin Name Dir Type Signal Description

FOOTNOTES:

(1)

VHAD[1:0] is the default for the 5-pin VIP Host Port setting.

(2)

TSDAT[0] is the default for the 4-pin serial MPEG Data Port setting. The 11-pin setting shares GPIO pins.

GENERAL NOTES:

1. Type:ractive resistive pull-up

od: open-drain t/s: three-state s/t/s: sustained three-state [x:y]: Bus {u:v:}Array of signal ports—expand to number without braces.

2. All signal I/O are LVTTL compatible (3.3 V operation with 3.9 V tolerance), except for the PCI signals which are all 5.5 V tolerant.

3. All inputs are Schmitt unless otherwise noted. The PCI inputs do not have hysteresis.

4. All outputs have drive capability I

= 4 mA unless otherwise noted.

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Functional Description

2.1 Audio Input

This section describes the functionality of the analog audio input. The following paragraphs define the logical sequence, from the audio input at the analog front end, to the output of digital audio samples, to the PCI bus or on-board DACs.

2.1.1 Overview

Analog audio input can be output directly to the on-board DACs for connection to the PC's sound card, to I host for software-based playback or encoding.

The major functional blocks of the audio subsystem are illustrated in Simplified Block Diagram of CX25800 Audio Subsystem and are broken down into the following sections:

 Audio-ADC  Audio PLL initialization  Input source select  Dematrix control  Audio control and Sample Rate Converter

 I

S input and output

 Audio DACs

S for high-fidelity digital coaxial and optical interfaces, or to the

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Functional Description CX25800 Data Sheet

Figure 3. Simplified Block Diagram of CX25800 Audio Subsystem

Audio

ADC

S I n

S Ou t

Lef t

DAC

Ri g h t

DAC

2.1.2 Analog Input ADC

The CX2500's Audio input (pin 151) is used for sampling line level audio signals from an amplified microphone.

2.1.3 Audio PLL Initialization

The audio PLL is automatically configured for 28.636363-MHz crystal frequency with the AUD_INIT_LD register. If using a crystal of frequency other than 28.636363 MHz, please contact Conexant Applications Engineering. If using the I PLL must be programmed to exactly 221.184 MHz in fractional mode.

Audio

Co n t r o l

Audio

FI FO

DMA

S output mode, the

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CX25800 Data Sheet Functional Description

2.1.4 Input Source Select

The 12 LSBs [11:0] of the AUD_CTL register (location 24'h32058C) determine the desired operation of the audio decoder.

24'h32058C—AUD_CTL Register

Bits Type Default Name Description

[5:0] RW 6'h00 Reserved Reserved [6] RW 1'b0 Reserved Reserved [8:7] RW 2'h0 Reserved Reserved [9] RW Reserved Reserved Reserved [10] RW 1'b0 Reserved Reserved [11] RW 1'b0 Reserved Reserved [12] RW 1'b0 DAC_ENABLE DAC enable bit

[13] RW 1'b0 I

SOUT_ENABLE I2S output enable bit [14] RW 1'b0 I2S_STR2DAC I2S input straight to DAC enable bit [15] RW 1'b0 I2SIN_ENABLE I2S input enable bit

2.1.5 Audio Control and Sample Rate Converter

2.1.5.1 Audio Demodulator Sample Rate Converter

Audio formats supported by the CX25800 are upconverted from their native sampled format to 48 kHz. This simplifies internal filtering and interfacing to external hardware peripherals through I

2.1.5.2 Volume

The volume control provides gain to both the left and right audio channel in 1 dB increments. The volume range is –63 to 0 dB and is controlled by the VOL_CTL register.

In addition, flexible control over muting is possible by the ability to control the muting of the selected source from the audio demodulator, the I During initialization, from reset to the end of the AUD_START_TIMER count, all three of these mutes are enabled automatically to avoid pops or clicks on any of the output s.

S, the internal audio DACs, or to software codecs.

S output, and the audio DAC.

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Functional Description CX25800 Data Sheet

24'h320594—VOL_CTL Register

Bits Type Default Name Description

[5:0] RW 8'h00 VOLUME Volume control in dB steps, 0 to –63 dB [6] RW 1'b0 SRC_MUTE_EN Source mute enable [7] RW 1'b0 I2S_MUTE_EN I2S mute enable [8] RW 1'b0 DAC_MUTE_EN DAC mute enable [15:9] RW 7'h00 — Reserved

2.1.5.3 Balance

The DAC output level can be adjusted. Digital balance control is used to alter the relative gain between the left and right channel outputs. Balance is controlled by providing an attenuation to one channel while maintaining 0 dB gain to the other channel. Attenuation of either channel is in the range of -63 to 0 dB in 1 dB steps. Balance attenuation is performed prior to the volume control. Stereo is only available

S input. The analog audio input is monophonic.

via I

24'h320598—BAL_CTL Register

Bits Type Default Name Description

[5:0] RW 8'h00 BAL_LEVEL Attenuation to be provided to the selected channel in dB. Range

is 0 to –63 dB.

[6] RW 1'b0 BAL_RIGHT Select right channel for balance control if 1, select left channel if

[15:7] RO 7'h00 — Reserved

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CX25800 Data Sheet Functional Description

2.1.6 I2S Input and Output

2.1.6.1 I2S Input

The CX8500 supports I2S input and output interfaces to a wide variety of external audio components. The three pins that make up the I (Audio Data In, pin 171), ALRCKI (Audio Left/Right Clock In, pin 172), ASCKI (Audio Serial Clock In, pin 173).

S input to the CX25800 can be used by an external audio or video processor to

The I take advantage of the CX25800 on-board audio DACs.

The CX25800 supports multiple I to external devices. The bit width of the input samples can range from 16-32 bits, and the input sample rate can be 48, 96, 144, or 192 kHz. Sony or Philips-style formats are supported. If the input samples are larger than 16 bits, the LSBs beyond 16 bits are truncated. Because the data rate to the audio subsystem is 48 kHz, if incoming input samples are received at rates in excess of 48 kHz, the extra samples are dropped. For instance, if the input format is 24 bits at 96 kHz, the eight lowest LSBs are truncated, and every other sample are dropped.

The CX25800 can be configured as either an I generates the clock and word select. As a slave it receives the clock and word select from the external I

An autobaud feature determines the baud rate of the incoming I The detected baud can be read in the I

S source.

S formats for maximum flexibility when connecting

S Input Status register, bits 5:0.

S input interface are ADATAI

S master or a slave. As a master it

S serial data stream.

24'h320120—I2SINPUT Register

Bits Type Default Name Description

[0] RW 1'b0 NSlaveMaster 0 = CX25800 is slave

1 = CX25800 is master

[1] RW 1'b0 NPhilipsSony 0 = Conform to Philips specification

1 = Conform to Sony specification

[2] RW 1'b0 DisableAutoBaud 0 = Autobaud

1 = Disable autobaud

[15:3] RO 13'h0000 — Reserved

24'h320124—I

Bits Type Default Name Description

[5:0] RO 6'h000 Status 0 = 0 kHz

SINPUTSTATUS Register

1 = 48 kHz 2 = 96 kHz 3 = 144 kHz 4 = 192 kHz 5 = 240 kHz (not supported) 6 = 288 kHz (not supported) > 6 => 288 kHz (not supported)

[15:6] RO 9'h000 — Reserved

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Functional Description CX25800 Data Sheet

2.1.6.2 I2S Output

The CX25800 supports I2S output to allow the user to bypass the built-in audio DACs and drive a Sony/Philips/Digital Interconnect Format (S/PDIF) driver for connection to a sound card, external surround processor, or digital recorder using an all-digital interface. In addition, this feature is useful when interfacing the CX25800 to a hardware MPEG II video and audio encoder for compression and synchronization between video and audio streams generated by the CX25800.

S output mode, the CX25800 is always the master device. It generates the clock

In I and word select.

Output muting is possible by asserting the Mute bit in the I

SOUTPUT register.

24'h320128—I2SOUTPUT Register

Bits Type Default Name Description

[0] RW 1'b0 NPhilipsSony 0 = Conform to Philips specification

1 = Conform to Sony specification [1] RW 1'b0 Mute Holds SCK, WS, and SD outputs [15:2] RW 14'h0000 — Reserved

2.1.7 I

S Control

The CX25800 can be used in a wide variety of audio applications. To support as many

S interface combinations as possible, the I2SCTL register provides several methods

I of multiplexing pins and signal information according to application. In addition to supporting timing master and slave modes on the I clock output is provided for interfacing to external audio ADCs or DACs. The oversample clock runs at 256 x the sample rate, which for 48 kHz audio is 12.288 MHz.

S input interface, an over-sample

24'h3205EC- I2SCTL

Bits Type Default Name Description

[0] RW* 1’b0 OSCLK2SCKOUT Send oversample clock out to the I2S Out sck (serial clock) pin

[1] RW* 1’b0 OSCLK2SCKIN Send oversample clock out to the I

Forces output enables for I

[2] RW* 1’b0 I

[3] RW* 1’b0 I

[15:4] RW* 12’h0000 Reserved

The I2SCTL register supports five modes for audio interfacing to external audio ADCs, DACs and compression ICs.

SOUT2IN Use I2S Out serial clock and word clock to drive I2S In block

internally.

SDIN2DOUT Connects the I2S In serial data input directly to the I2S Out serial

data output.

S In sck (serial clock) pin.

S In pins to be high (output mode)

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CX25800 Data Sheet Functional Description

2.1.7.1 Normal Mode

Normal mode operation supports transfer of audio samples to an MPEG Encoder/ CODEC or to a nyquist-rate audio ADCs and DACs. No oversample clock is provided, and each I illustrated in Normal Mode Operation. Normal mode is the default configuration. It can also be programmed by writing 0x0 to the I

Figure 4. Normal Mode Operation

S interface has its own dedicated three signals: SCK, LRCK, SDAT. This is

SCTL register.

Out

GENERAL NOTE:

S In enabled.

1. I

S Out enabled.

2. I

3. No oversample clock provided.

2.1.7.2 OSR DAC Mode

OSR DAC Mode is available to drive an external high quality stereo audio DAC which requires an oversampled clock. The I input serial clock pin is used to output the oversampled clock. The I still available.

OSR DAC mode is programmed by writing 0x2 to the I

SIN_ENABLE bit in the AUDCTL register must be disabled, and the

SOUT_ENABLE bit should be enabled. OSRDAC mode is illustrated in Figure 5.

sck

Irclk

sd o

sck

Irclk

sd i

Cod e c

I2S

Out

S output pins are

SCTL register. Additionally, the

sck

Irclk

sd i

sck

Irclk

sd o

sck

Irclk

sck

Irclk

S input is not available in this mode. The I2S

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Functional Description CX25800 Data Sheet

Figure 5. OSR DAC Mode Operation

Out

GENERAL NOTE:

I2S In disabled. I2S Out enabled.

3. Oversample clock provided for DAC.

2.1.7.3 OSR ADC Mode

OSR ADC mode is available as an input for baseband stereo audio through an external audio ADC which requires an oversample clock. The I available in this mode. The I oversampled clock. The I

OSR ADC mode is programmed by writing 0x1 to the I

SIN_ENABLE bit in the AUDCTL register should be enabled, and the

SOUT_ENABLE bit should be disabled. OSR ADC mode is illustrated in Figure 6.

Figure 6. OSR ADC Mode Operation

sck

Irclk

sd i

sck

Irclk

sd o

osck

OSR DAC

msck

sck

Irclk

S input pins are still available for use.

sck

Irclk

sd i

I2S

S output serial clock pin is used to output the

SCTL register. Additionally, the

St e r e o Audio Out

S output is not

I2S

Out

sck

Irclk

sd i

sck

Irclk

sd o

sck

Irclk

osck

Irclk

msck

sck

sd o

OSR ADC

Out

St e r e o Audio In

GENERAL NOTE:

I2S In enabled.

I2S Out disabled.

3. Oversample clock provided for ADC.

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CX25800 Data Sheet Functional Description

2.1.7.4 Passthrough Mode

Passthrough mode is provided as a method of making the CX25800 act as a multiplexer between its own digital output from the analog audio input and the digital output from an I oversample clock. In this mode, the oversample clock is sent to the I clock pin. Both the external I and word clock. The I output serial data output pin. Both of the external I mode operation. This is illustrated in Figure 7.

Passthrough mode is programmed by writing 0x8 to the I

SIN_ENABLE bit in the AUDCTL register should be disabled, and the

the I

SOUT_ENABLE bit should be enabled.

Figure 7. Passthrough Mode Operation

sck

Irclk

sd i

S input when either the I2S input or output (or both) require an

S devices are connected to the I2S output serial clock

S input serial data pin is internally connected directly to the I2S

OSR ADC

sck

Irclk

sd o

msck

S devices must support slave-

SCTL register. Additionally,

Out

S input serial

St e r e o Audio In

osck

sck

Out

GENERAL NOTE:

1. I

S In disabled.

2. I

S Out enabled.

3. External ADC and CODEC (or DAC) slaved to I

4. I

S In serial data passed directly to I2S Out serial data.

Irclk

sd o

sck

Irclk

5. Oversample clock provided for ADC and/or DAC.

S Out.

En co d er or COD EC

msck

sck

Irclk

sd i

I2S

Com p resse d Audio Out

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Functional Description CX25800 Data Sheet

2.1.7.5 Full Functionality Mode

Full functionality mode is available as a method for providing an oversampled clock to external I mode, the I the external devices are both connected to the I the oversample clock is provided on the I data in to the I separate. In this mode, it is possible to send data from the I encoder or codec, while simultaneously streaming baseband audio in the I over the PCI, enabling DVCR record-one, play-another functionality with composite source. Like the Passthrough mode, both I operation. This mode is illustrated in Figure 8.

Full functionality mode is enabled by programming 0x6 to the I enables the oversample clock output on the I

S input off the I2S output serial clock and word clock internally. Additionally, the

SIN_ENABLE bit, and the I2SOUT_ENABLE bit in the AUDCTL register should be

I enabled. Finally , the NSLA VEMASTER bit in the I to put the I

Figure 8. Full Functionality Mode

S devices, while still maintaining separate I2S streams in and out. In this

S input is internally slaved to the I2S output serial clock and word clock,

S Input block and serial data out from the I2S Output block are kept

S Input into slave mode.

S output serial clock and word clock,

S output serial clock pin, and only the serial

S output to a MPEG

S devices must support slave mode

S input serial clock pin, and slaves the

SINPUT register should be disabled

SCTL register, which

S input

Out

GENERAL NOTE:

1. I

S In enabled.

2. I

S Out enabled.

3. External ADC and DAC slaved from I

4. I

S In serial clock and word clock slaved from I2S Out.

sd i

sck

Irclk

sd o

S Out.

osck

sck

Irclk

5. Oversample clock provided for ADC and/or DAC.

sck

Irclk

sd o

msck

sck

Irclk

sd i

OSR ADC

OSR DAC

Out

St e r e o Audio In

St e r e o Audio Out

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CX25800 Data Sheet Functional Description

2.1.8 Audio DACs

The CX25800 provides an analog stereo audio output that can drive a PC audio card or a stereo preamplifier input. Two integrated audio DACs provide approximately 85 dB SNR when used with an external active filter circuit, or approximately 75 dB SNR when used with a simple RC external construction filter. See Chapter 3 for external component example circuits.

The input to the audio DACs is based on two bits present in the AUD_CTL register: DAC_ENABLE and I enables are passed to the DAC. If DAC_ENABLE is enabled, then either the I

S_STR2DAC is enabled) or the upstream DMA channel (if I2S_STR2DAC is

(if I disabled) is passed to the DAC.

S_STR2DAC. If DAC_ENABLE is disabled, then no signals or

S input

24'h32058C—AUD_CTL Register, Bits [12], [14]

Bits Type Default Name Description

[12] RW 1'b0 DAC_ENABLE DAC enable bit [14] RW 1'b0 I2S_STR2DAC I2S input straight to DAC enable bit

The DAC output sample rate is a fixed divide off the PLL clock. The sample rate is calculated as the PLL frequency divided by 18 (the DAC pulse width modulated output rate) and divided by 128 (the DAC oversampling ratio). Whichever sample rate converter is used to drive the input to the DAC (through a FIFO) must be programmed to this sample rate, not the 48 kHz sample rate that is normally used. For instance, if the demodulator is used as the source to the DAC, the demodulator sample rate converter DDS frequency must be programmed to provide output samples at the calculated sample rate of the DAC instead of 48 kHz.

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Functional Description CX25800 Data Sheet

2.2 General Purpose Host Port

2.2.1 Introduction

The CX25800 features a general purpose bidirectional host processor interface. This enables board vendors to add additional components to a basic CX25800 design.

Table 2 gives some examples of peripherals that can be added.

Table 2. CX25800 Applications Enabled by Host Port Peripherals

Application

Digital VCR Conexant MPEG Encoder IC Cable Modem PC/TV Conexant Cable Modem IC PC/TV with IR remote control IR Controller Video Editor DV Codec

2.2.2 Host Port Overview

The GPHP supports peripherals that conform to either Motorola or Intel-style bus interface signaling protocols, with appropriate big endian vs. little endian byte ordering. The GPHP supports either discrete or multiplexed address/data buses as follows:

 8-bit data path and 8-bit address on a nonmultiplexed bus  16-bit data path and 16-bit address on a multiplexed bus

The GPHP allows simultaneous connection to two peripheral ICs with no external interface logic, or four peripheral ICs with external glue logic. The function of the glue logic is to decode the chip select information encoded onto the two chip select pins when in encoded chip select mode. The GPHP can then be used to gain access to the memory map of these external devices for register reads and writes.

The GPHP interface is configurable through the host interface registers. These registers allow for the selection of the bus size, handshaking mode, signal polarity , and control signal timing adjustment.

ICs that connect to the

CX25800 General Purpose Host Port

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CX25800 Data Sheet Functional Description

The GPHP pin interface is defined in Table 19.

Table 3. GPHP Pin Definition

Pin Number Pin Name Dir Full Name Description: GPHP Signals

91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 106, 107, 108, 109, 110

90 HCS# O General Purpose Host Chip

89 HRD/HDS# O General Purpose Host Read/

87 HWR/HRW# O General Purpose Host Write/

88 HALE# O General Purpose Host

86 HRDY# I General Purpose Host Ready External data transfer acknowledge signal 85 HEXFB I General Purpose Host

HAD[15:0] I/O General Purpose Host

Address/Data

Select

Data Strobe

Read NOT Write

Address Latch Enable

External Status

Bidirectional address/data access bus. The width is selectable between an 8-bit address and 8-bit data bus, or a multiplexed 16-bit address/data bus.

External Chip select

Either the active low read signal (Intel mode) or the programmable polarity data strobe signal (Motorola mode).

Either the active low write signal (Intel mode) or the read/ not write (Motorola mode).

Address Latch Enable signal. Used only in multiplexed 16-bit address/data mode.

Handshaking signal for use in DMA mode to indicate the status of the external source or destination FIFO.

Host Wait-State Control

24'h380054—HST_WSC Register

Bits Type Default Name Description

[31:28] RW 4’h1 HST_W3W Wait state control for external write cycles to chip select:

HCS[3]#. Length of write cycle = (register value * bclk period). [27:24] RW 4’h1 HST_W2W HCS[2] write cycle [23:20] RW 4’h1 HST_W1W HCS[1] write cycle [19:16] RW 4’h1 HST_W0W HCS[0] write cycle [15:12] RW 4’h1 HST_W3R Wait state control for external read cycles to chip select:

HCS[3]#. Length of write cycle = (register value * bclk period). [11:8] RW 4’h1 HST_W2R HCS[2] read cycle [7:4] RW 4’h1 HST_W1R HCS[1] read cycle [3:0] RW 4’h1 HST_W0R HCS[0] read cycle

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Functional Description CX25800 Data Sheet

Host Transfer Control

24'h380058—HST_XFER_CNTL Register

Bits Type Default Name Description

[15] RW 1’b0 Hcs3_cs_hold HCS[3] chip select hold time (15 ns) relative to read or write

enable (1 = On, 0 = Off) [14] RW 1’b0 Hcs2_cs_hold HCS[2] chip select hold time [13] RW 1’b0 Hcs1_cs_hold HCS[1] chip select hold time [12] RW 1’b0 Hcs0_cs_hold HCS[0] chip select hold time [11] RW 1’b0 Hcs3_ds_polarity External Data Strobe polarity for HCS[3](1 = positive,

0 = negative) Motorola mode only. [10] RW 1’b0 Hcs2_ds_polarity External Data Strobe polarity for HCS[2] [9] RW 1’b0 Hcs1_ds_polarity External Data Strobe polarity for HCS[1] [8] RW 1’b0 Hcs0_ds_polarity External Data Strobe polarity for HCS[0] [7] RW 1’b0 Hcs3_xfer_mode External Transfer mode for HCS[3](we# & re# or R/W# & ds#)

(intel(0) or Motorola(1) [6] RW 1’b0 Hcs2_xfer_mode External Transfer mode for HCS[2] [5] RW 1’b0 Hcs1_xfer_mode External Transfer mode for HCS[1] [4] RW 1’b0 Hcs0_xfer_mode External Transfer mode for HCS[0] [3] RW 1’b0 Hcs2_sh_extend External data setup and hold time extend for HCS[3]

(0 = 1x bclk period 1 = 2x bclk period) [2] RW 1’b0 Hcs2_sh_extend External setup and hold extend for HCS[2] [1] RW 1’b0 Hcs1_sh_extend External setup and hold extend for HCS[1] [0] RW 1’b0 Hcs0_sh_extend External setup and hold extend for HCS[0]

Host Interface Width

24'h38005C—EXT_INTF_WIDTH Register

Bits Type Default Name Description

[3] RW 1’b0 Ext_intf_width[3] HCS3: (0): 16-bit (multiplexed), (1): 8-bit [2] RW 1’b0 Ext_intf_width[2] HCS2: (0): 16-bit (multiplexed), (1): 8-bit [1] RW 1’b0 Ext_intf_width[1] HCS1: (0): 16-bit (multiplexed), (1): 8-bit [0] RW 1’b0 Ext_intf_width[0] HCS0: (0): 16-bit (multiplexed), (1): 8-bit

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CX25800 Data Sheet Functional Description

Host Peripheral Handshake

24'h380060—HRDY_HANDSHAKE Register

Bits Type Default Name Description

[3] RW 1’b0 Mstr_handshake[3] HCS3 HRDY handshake enable bit [2] RW 1’b0 Mstr_handshake[2] HCS2 HRDY handshake enable bit [1] RW 1’b0 Mstr_handshake[1] HCS1 HRDY handshake enable bit [0] RW 1’b0 Mstr_handshake[0] HCS0 HRDY handshake enable bit

Host Multiplexed 16-bit Transfer Parameters

24'h380064—MUX16_PARAM Register

Bits Type Default Name Description

[31:28] RW 4’b0001 HCS3_ale_timing HCS3 HRDY handshake enable bit [27:24] RW 4’b0001 HCS2_ale_timing HCS2 HRDY handshake enable bit [23:20] RW 4’b0001 HCS1_ale_timing HCS1 HRDY handshake enable bit [19:16] RW 4’b0001 HCS0_ale_timing HCS0 HRDY handshake enable bit [15:12] RW 4’b0010 HCS3_addr_cyc HCS3 Address cycle width (register value * bclk period) setup

time not included [11:8] RW 4’b0010 HCS2_addr_cyc HCS2 Address cycle width [7:4] RW 4’b0010 HCS1_addr_cyc HCS1 Address cycle width [3:0] RW 4’b0010 HCS0_addr_cyc HCS0 Address cycle width

Host Chip Select Mode

24'h380068—HCS_MODE_SEL Register

Bits Type Default Name Description

[0] RW 1’b0 HCS_mode_sel This bit selects between the two possible chip select modes:

0: 2-bit dedicated chip selects. For times when two or fewer

devices are connected to the host port.

1: 2-bit encoded chip selects. For times when more than two

devices are connected to the host port.

Host Software Reset

24'h38C06C—HOST_SOFT_RST Register

Bits Type Default Name Description

[0] WO 1’b0 HOST_SOFT_RST Host Software Reset. Writing a 1 to this register triggers a reset

of the host logic.

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Host Interrupt Mask

24'h200090—HST_INT_MSK Register

Bits Type Default Name Description

[19:0] RW 20’b0 HST_INT_MASK A value of 1 enables the corresponding interrupt bit location in

the HST_INT_STAT register. Unmasking a bit may generate an

interrupt immediately due to a previously pending condition. The

interrupt remains asserted until the device driver clears or

masks the pending request.

Host Interrupt Status

24'h200094—HST_INT_STAT Register

Bits Type Default Name Description

[19] RR 1’b0 PCI_ABORT Set when the PCI master does a master-abort, or a target

responds with a target-abort. [18] RR 1’b0 RIP_ERR Set when a data parity error is detected (parity error response

must be set while the master is reading RISC instructions. [17] RR 1’b0 PAR_ERR Set when a parity error is detected on the PCI bus for any of the

transactions, R/W, address/data phases, master/target,

regardless of the parity error response bit. [16] RR 1’b0 OPC_ERR Set when the RISC controller detects a reserved/unused opcode

in the instruction sequence. [13] RR 1’b0 UP_SYNC Set when number of lines or bytes do not match the upstream

host RISC program expectations. [12] RR 1’b0 DN_SYNC Set when number of lines or bytes do not match the downstream

host RISC program expectations. [9] RR 1’b0 UPF_UF Set when upstream host FIFO underflow condition is being

handled. [8] RR 1’b0 DNF_OF Set when downstream host FIFO overflow condition is being

handled. [5] RR 1’b0 UP_RISCI2 Set when the IRQ2 bit in a upstream host RISC instruction is set. [4] RR 1’b0 DN_RISCI2 Set when the IRQ2 bit in a downstream host RISC instruction is

set. [1] RR 1’b0 UP_RISCI1 Set when the IRQ1 bit in a upstream host RISC instruction is set. [0] RR 1’b0 DN_RISCI1 Set when the IRQ1 bit in a downstream host RISC instruction is

set.

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Host Interrupt Masked Status

24'h200098—HST_INT_MSTA T Register

Bits Type Default Name Description

[19:0] RO 20’b0 HST_INT_MSTAT These bits are the logical AND of the corresponding bits in the

status and mask registers.

Host Interrupt Set Status

24'h20009C—HST_INT_SSTAT Register

Bits Type Default Name Description

[16:0] WO 17’b0 HST_INT_SSTAT Writing a 1 to these bits sets the corresponding bits in the status

The GPHP can support one upstream DMA (transfer from host to peripheral through the CX25800) and one downstream (transfer from peripheral to host through the CX25800) DMA channel active at any time. These DMA channels are configured by the EPHP DMA registers and are detailed in the following pages.

IPB DMAC Current Buffer Pointer

24'h3000A8—DMA31_PTR1 Register 24'h3000AC—DMA32_PTR1 Register

Bits Type Default Name Description

[23:2] RO 22’hxxxxxx DMA{x}_PTR1 Current DMA qword address pointer. Points to next qword

transfer location within source or destination buffer. Always

dword-aligned. [1:0] RO 2’b00 Reserved

IPB DMAC Current Table Pointer

24'h3000E8—DMA31_PTR2 Register 24'h3000EC—DMA32_PTR2 Register

Bits Type Default Name Description

[23:2] RW* 22’hxxxxxx DMA{x}_PTR2 Current DMA CDT address pointer. Points to current CDT entry.

Always dword-aligned. [1:0] RO 2’b00 Reserved

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IPB DMAC Buffer Limit

24'h300128—DMA31_CNT1 Register 24'h30012C—DMA32_CNT1 Register

Bits Type Default Name Description

[10:0] RW* 11’hxxx DMA{x}_CNT1 Initialize to DMA buffer size in number of qwords. Increments

during DMA data transfers and reloads when next CDT pointer

is fetched.

IPB DMAC Table Size

24'h300168—DMA31_CNT2 Register 24'h30016C—DMA32_CNT2 Register

Bits Type Default Name Description

[10:0] RW* 11’hxxx DMA{x}_CNT2 Initialize to DMA CDT size in number of qwords.

General Purpose Counter (Immediate access)

24'h38C020—HSTD_GP_CNT Register 24'h38C024—HSTU_GP_CNT Register

Bits Type Default Name Description

[15:0] RO 16’b0 {x}_GP_CNT General purpose counter used by RISC program.

General Purpose Counter Control (Immediate access)

24'h38C030—HSTD_GP_CNT_CNTRL Register 24'h38C034—HSTU_GP_CNT_CNTRL Register

Bits Type Default Name Description

[1:0] WO 2’b00 {x}_GP_CNT_CNTRL General purpose counter control used by RISC program:

00 = no change

01 = increment

10 = reserved

11 = reset to 0

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Host Interface Streaming Enable (Immediate Access)

24'h38C040—HST_STREAM_EN Register

Bits Type Default Name Description

[5] RW 1’b0 HSTU_RISC_EN RISC Controller enable for the host interface upstream DMA

channel. [4] RW 1’b0 HSTD_RISC_EN RISC Controller enable for the host interface downstream DMA

channel [1] RW 1’b0 HSTU_FIFO_EN Enable for pulling data out of the host upstream DMA FIFO or

CDT. [0] RW 1’b0 HSTD_FIFO_EN Enable for fetching downstream data from the external source.

Host Upstream DMA Control Register #1

24'h380048—HSTU_DMA_CTRL1 Register

Bits Type Default Name Description

[25] RW 1’b0 UP_FIFO_HK_EN Host upstream FIFO handshake enable. This enables the

CX25800 to monitor the External_fifo_busy bit and act

accordingly. [24] RW 1’b0 HSTU_AINC_EN Host upstream address auto-increment enable. Used to DMA

data to sequential addresses within the slave device. Not to be

used when the destination is a FIFO. [23:0] RW 24’hxxxxxx HSTU_DST_ADDR HST upstream IPB DMA Destination address. If auto-increment

is enabled then the value loaded into this register should be the

starting address.

Host Downstream DMA Control Register #1

24'h38004C—HSTD_DMA_CTRL1 Register

Bits Type Default Name Description

[25] RW 1’b0 DN_FIFO_HK_EN Host downstream FIFO handshake enable. This enables

CX25800 to monitor the External_fifo_busy bit and act

accordingly. [24] RW 1’b0 HSTD_AINC_EN Host downstream address auto-increment enable. Used to DMA

data to sequential addresses within the slave device. Not to be

used when the destination is a FIFO. [23:0] RW 24’hxxxxxx HSTD_SRC_ADDR HOST downstream IPB DMA source address. If auto increment

is enabled then the value loaded into this register should be the

starting address.

Host Downstream DMA Control Register #2

24'h380050—HSTD_DMA_CTRL2 Register

Bits Type Default Name Description

[11:0] RW 12’b0 HST_LNGTH HST downstream transfer count in bytes.

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2.2.3 General Purpose Host Port Memory Space

The memory space associated with the GPHP is divided into two categories, internal registers and the external peripheral address space. Table 20 provides descriptions of each address range in the GPHP memory space.

Table 4. GPHP Memory Space

ADDRESS RANGE SIZE DESCRIPTION

380000–38FFFF 64 kB HOST local registers, specific to the CX25800 390000–39FFFF 64 kB Peripheral 1 address space 3A0000–3AFFFF 64 kB Peripheral 2 address space 3B0000–3BFFFF 64 kB Peripheral 3 address space 3C0000–3CFFFF 64 kB Peripheral 4 address space

2.2.4 General Purpose Host Port Interface Register Access

There are 64 KB of address space available within the GPHP address space for each of the four possible peripherals and all of the registers pertaining to the GPHP configuration. For the peripherals that are connected to the CX25800 through the 8-bit data interface, only the lower 256 bytes of this space are accessible. This register mapping allows the peripherals to have their registers directly mapped into the CX25800 memory map.

2.2.5 General Purpose Host Interface External DMA Transfers

Streaming of data upstream and downstream is achieved through the DMA mechanism resident in the GPHP. There are two dedicated DMA channels that are available One channel is dedicated to upstream DMA while the other is dedicated to downstream DMA.

Once the DMAC is set up for the transfer, the GPHP must be configured. This configuration consists of the programming of the GPHP DMA Setup registers. For upstream transfers, the GPHP must be programmed with the external destination address, auto-increment enable/disable, and end-of-transfer interrupt enable. For downstream transfers, the GPHP must be programmed with the external source address, byte count, auto-increment enable/disable, and end-of-transfer interrupt enable. These reads and writes are then forwarded by the GPHP to the appropriate external source or destination address.

Upon completion of a packet of data, the GPHP generates the appropriate DMA interrupt.

The GPHP uses its external FIFO status pin to interface with an external streaming FIFO. When enabled, this pin is used to indicate when the external destination can safely accept more data in the upstream case, and when the external source has data to transfer in the downstream case. Because there are two DMA channels and only one FIFO status pin, one of the two DMA channels must use the register polling approach to obtain the FIFO status in the case where both channels are being used simultaneously.

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2.2.6 General Purpose Host Interface Signaling—Nonmultiplexed Mode

Figure 9. Host Interface Write Operation—Intel Style (Accessing an External Device)

HAD[15:8]

HAD[7:0]

HCS[X]#

HRD#

HWR#

HRDY#

Address

Data

GENERAL NOTES:

1. The HRDY# signal only used for handshaking when it is enabled via one of the host registers.

2. HRDY# has programmable polarity. HRDY# is shown here in its default setting, active low.

Figure 10. Host Interface Write Operation—Motorola Style (Accessing an External Device)

HAD[15:8]

HAD[7:0]

HCS[X]#

HR/W#

Address

Data

HDS#

HRDY#

GENERAL NOTES:

1. The HRDY# signal only used for handshaking when it is enabled via one of the host registers.

2. HRDY# and HDS# each have programmable polarity. Both are shown here in their default settings, active low.

Description Min Max

A Addr/Data setup time relative to write pulse and chip

1x PCLK Period 2x PCLK Period

select and HDS pulse B Write pulse width, HDS pulse width 1x PCLK Period 15x PCLK Period C Chip select hold time relative to write pulse and HDS

0 1x PCLK Period

pulse D Addr/Data hold time relative to chip select 1x PCLK Period 2x PCLK Period

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Figure 11. Host Interface Read Operation—Intel Style (Accessing an External Device)

HAD[15:8]

HAD[7:0]

HCS[X]#

HR/W#

HDS#

HRDY#

Address

Data

GENERAL NOTES:

1. The HRDY# signal only used for handshaking when it is enabled via one of the host registers.

2. HRDY# has programmable polarity. HRDY# is shown here in its default setting, active low.

Figure 12. Host Interface Read Operation—Motorola Style (Accessing an External Device)

HAD[15:8]

HAD[7:0]

HCS[X]#

HR/ W#

HDS#

Address

Data

HRDY#

GENERAL NOTES:

1. The HRDY# signal only used for handshaking when it is enabled via one of the host registers.

2. HRDY# and HDS# each have programmable polarity. Both are shown here in their default settings, active low.

Description Min Max

A Addr/Data setup time relative to write pulse and chip select and HDS pulse 1x PCLK Period 2x PCLK Period B Write pulse width, HDS pulse width 1x PCLK Period 15x PCLK Period C Chip select hold time relative to write pulse and HDS pulse 0 1x PCLK Period

D Addr hold time relative to chip select 1x PCLK Period 2x PCLK Period

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2.2.7 General Purpose Host Interface Signaling—Multiplexed Mode

Figure 13. Host Interface Read Operation—Intel Style Multiplexed Address/Data Bus (Accessing an External Device)

HAD[15:0]

HALE

HCS[X]#

HRD#

HWR#

HRDY#

Address Data

GENERAL NOTES:

1. The HRDY# signal only used for handshaking when it is enabled via one of the host registers.

2. HRDY# has programmable polarity. HRDY# is shown here in its default setting, active low.

Figure 14. Host Interface Read Operation—Motorola Style Multiplexed Address/Data Bus (Accessing an External Device)

HAD[15:0]

HALE

HCS[X]#

HR/W#

Address Data

HDS#

HRDY#

GENERAL NOTES:

1. The HRDY# signal only used for handshaking when it is enabled via one of the host registers.

2. HRDY# and HDS# each have programmable polarity. Both are shown here in their default settings, active low.

Description Min Max

A Addr/Data setup time to chip select 1x PCLK Period 2x PCLK Period B Addr setup time relative to HALE 2x PCLK Period 3x PCLK Period C Chip select hold time relative to address latch enable 1x PCLK Period 1x PCLK Period D Read pulse width, HDS pulse width 1x PCLK Period 15x PCLK Period E Chip select hold time relative to read pulse and HDS

0 1x PCLK Period

pulse

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Figure 15. Host Interface Write Operation—Intel Style Multiplexed Address/Data Bus (Accessing an External Device)

HAD[15:0]

HALE

HCS[X]#

HRD#

HWR#

HRDY#

Address Data

GENERAL NOTES:

1. The HRDY# signal only used for handshaking when it is enabled via one of the host registers.

2. HRDY# has programmable polarity. HRDY# is shown here in its default setting, active low.

Figure 16. Host Interface Write Operation—Motorola Style Multiplexed Address/Data Bus (Accessing an External Device)

HAD[15:0]

HALE

HCS[X]#

HR/W#

Address Data

HDS#

HRDY#

GENERAL NOTES:

1. The HRDY# signal only used for handshaking when it is enabled via one of the host registers.

2. HRDY# and HDS# each have programmable polarity. Both are shown here in their default settings, active low.

Description Min Max

A Addr setup time relative to chip select 1x PCLK Period 2x PCLK Period B Addr setup time relative to address latch enable (hale)

2x PCLK Period 3x PCLK Period

and HR/W# C Addr hold time relative to address latch enable (hale) 1x PCLK Period 1x PCLK Period D Data setup relative to (Intel) write pulse or (Moto) HDS

1x PCLK Period 1x PCLK Period

pulse E (Intel) Write pulse width (Moto) HDS pulse width 1x PCLK Period 15x PCLK Period F Chip select hold time relative to write pulse and HDS

0 1x PCLK Period

pulse G Data hold time relative to the chip select 1x PCLK Period 2x PCLK Period

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2.3 GPIO

2.3.1 GPIO Pin Architecture

Each GPIO pin is set up as a basic I/O buffer, with each bit of the General Purpose Output Enable (GPOE) register used to enable an individual pin’s output driver (see

Figure 17).

Figure 17. GPIO Pin Architecture

L o c a

e g

t e r

GPDATA Input/

Read Buffer/Register

GPDATA Output/

Write Holding Register

GP_OE[x]

GPIO[x]

Three-State

Buffer

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2.3.2 GPIO Modes in CX25800

Twenty-four pins are provided for GPIO. They are mapped onto the pin numbers listed in Table 21.

Table 5. GPIO Pin Numbers

Pin Numbers GPIO Number

8–15 [23–16]

112–119 [15–8]

123–130 [7–0]

The GPIO port is highly flexible and can be assigned to the following functions with the CX25800. See Table 1.

 GPIO functions  MPEG input parallel port (DVB common interface-compatible)  VIP parallel host port expansion  Digital video output from the video decoder as either 8-bit or 10-bit, 4:2:2 samples

with 601-like external synchronization signals

 Digital video output from the video decoder as 8-bit, ITU-R656, 27 MHz, 4:2:2

samples

 Digital video input to the CX25800 image scaler (and subsequent DMA to VGA

overlay surface) from an external MPEG decoder outputting ITU-R656, 27 MHz, 4:2:2 interlaced samples or 54 MHz, noninterlaced video samples

 General purpose host port external chip select function

The PINMUX_IO register is used to configure the entire GPIO port as desired. On power-up or PCI reset, all GPIO pins are undedicated. The 8 bits of the PINMUX_IO register [7:0] can be used to select any of 9 different basic functional usage configurations. Combinations of modes are possible, provided I/O pins do not overlap. The priority with respect to pin allocation to a desired function is from bit 7 down to bit

0. Therefore, if multiple GPIO modes are selected, the modes with the higher index are dominant and overwrite the functional meaning of pins selected by the lower index modes. In other words, MPEG_PAR_EN takes priority over VIP_MODE.

24'35C044—PINMUX_IO

Bits Mode Default Program Mode Name Description

[7] 1 0 1 MPEG_PAR_EN MPEG parallel port [6:5] 2/3 00 xx VIP_MODE VIP host port width [4] 4 0 1 VID_SYNC_EN 601 Video external output syncs [3] 5 0 1 VID8_OUT_EN 656 Video 8-bit output port [2] 6 0 1 VID10_OUT_EN 656 Video 10-bit output port [1] 7 0 1 VID_IN_EN 656 Video input port [0] 8 0 1 HCS1_EN Host port chip select

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Table 6 illustrates which modes can be used with other modes and which are mutually

exclusive. Table 7 illustrates the GPIO mode versus pin usage.

NOTE:

MPEG_PAR_EN, VIP4_MODE, VIP8_MODE, and HCS1_EN are extensions of the existing serial MPEG port, 2-bit VIP Host Master port, and GPHP, which are available at all times, irrespective of GPIO configuration.

Table 6. GPIO Mode Allocation

GPIO Pins

Mode Name

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

MPEG_PAR_EN XXXXXXX VIP4_MODE XX VIP8_MODE XXXXXX VID_SYNC_EN XXXXXXX VID8_OUT_EN XXXXXXXX VID10_OUT_EN XXXXXXXX XX VID_IN_EN XXXXXXXX HCS1_EN X

GENERAL NOTES:

1. X = Used in that mode; blank is unused and the pin is available for normal GPIO.

Table 7. GPIO Mode versus Pin Usage (1 of 2)

Default Power-Up

Reset State

PINMUX_IO PINMUX_IO PINMUX_IO PINMUX_IO

MPEG_PAR_EN=1 VIP_MODE=01 VIP_MODE=10 HCS1_EN=1

Pin Dir

Signal Dir Signal Dir Signal Dir Signal Dir

GPIO[23] I/O Tsdat[1] I HCS[1]# O GPIO[22] I/O Tsdat[2] I GPIO[21] I/O Tsdat[3] I VHAD[7] I/O GPIO[20] I/O Tsdat[4] I VHAD[6] I/O GPIO[19] I/O Tsdat[5] I VHAD[5] I/O GPIO[18] I/O Tsdat[6] I VHAD[4] I/O GPIO[17] I/O Tsdat[7] I VHAD[3] I/O VHAD[3] I/O GPIO[16] I/O VHAD[2] I/O VHAD[2] I/O

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Table 7. GPIO Mode versus Pin Usage (2 of 2)

Default Power-Up

Reset State

PINMUX_IO PINMUX_IO PINMUX_IO PINMUX_IO

MPEG_PAR_EN=1 VIP_MODE=01 VIP_MODE=10 HCS1_EN=1

Pin Dir

Signal Dir Signal Dir Signal Dir Signal Dir

GPIO[23] I/O VDO[1] O GPIO[22] I/O VDO[0] O GPIO[21] I/O GPIO[20] I/O GPIO[19] I/O GPIO[18] I/O GPIO[17] I/O GPIO[16] I/O GPIO[15] I/O VDO[9] O VDO[9] O GPIO[14] I/O VDO[8] O VDO[8] O GPIO[13] I/O VDO[7] O VDO[7] O GPIO[12] I/O VDO[6] O VDO[6] O GPIO[11] I/O VDO[5] O VDO[5] O GPIO[10] I/O VDO[4] O VDO[4] O GPIO[9] I/O VDO[3] O VDO[3] O GPIO[8] I/O VDO[2] O VDO[2] O GPIO[7] I/O VDI[7] I GPIO[6] I/O V_NVRESET O VDI[6] I GPIO[5] I/O V_NHRESET O VDI[5] I GPIO[4] I/O V_HACTIVE O VDI[4] I GPIO[3] I/O V_VACTIVE O VDI[3] I GPIO[2] I/O V_CBFLAG O VDI[2] I GPIO[1] I/O V_FIELD O VDI[1] I GPIO[0] I/O V_VALID O VDI[0] I

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2.3.3 GPIO Normal Mode

The GPIO Port Normal mode can be used to input or output general board-level signals to or from the CX25800. The PINMUX_IO bits are in the default state of 32’h0000 during Normal mode. When in Normal mode, these pins are not designed to support a high speed interface for video or broadband data. For such applications, the other modes must be used.

24’h350010—GP0_IO Register 24’h350014—GP1_IO Register 24’h350018—GP2_IO Register 24’h35001C—GP3_IO Register

Bits Type Default Name Description

[31:26] RO 6’h00 Reserved [25] RW 1’b0 GP3_MODE A value of 0 enables the GPIO register interface in default mode

where each set of 8 pins are controlled by a GP{x}_IO register. A value of 1 enables all 24 GPIO and/or GPOE bits to be read/

written simultaneously. [24] RO 1’b0 Reserved [23:16] Wd GP{x}_BWE If this field is equal to 8’h00, then the whole GPIO byte register

operates in normal R/W mode. If any bit is set, then the

corresponding GP_OE and GP_IO bit locations are enabled for

writing. If the bit write enable is not set, the corresponding GPIO

bits are unaffected. [15:8] RW 8’h00 GP{x}_OE A value of 1 enables corresponding GP_IO bit to be output on

the GPIO pin. [7:0] RW* 8’h00 GP{x}_IO Writing provides data for GPIO output pin drivers. Reading

accesses data directly from input pin buffers.

Note that the GP3_* control bits are only available in register GP3_IO. If GP3_MODE is set to 24-bit access mode, the GPIO register interface loses bit resolution field control capability.

24'h350010—GPIO

Bits Type Default Name Description

[23:0] RW* 24’h000000 GP_IO Writing provides data for GPIO output pin drivers. Reading

accesses data directly from input pin buffers.

24’h350014—GPOE

Bits Type Default Name Description

[23:0] RW* 24’h000000 GP_OE A value of 1 enables corresponding GP_IO bit to be output

on the GPIO pin.

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In addition to capturing or generating simple input/output signals, some GPIO pins can service externally generated interrupts. GPIO [23:22] (pins 8 and 9) have input interrupt capability. The GPIO_ISM register allows control of input signal polarity and level or edge sensitivity.

24’h350028—GPIO_ISM

Bits Type Default Name Description

[3:2] WO 2’b00 GP_ISM_SNS Sensitivity mode for interrupt inputs GPIO[23:22].

0 = level-sensitive 1 = edge-sensitive

[1:0] WO 2’b00 GP_ISM_POL Polarity control for interrupt inputs GPIO[23:22].

1 = active-hi or posedge 0 = active-lo or negedge

2.3.4 MPEG Parallel Port

Table 7 indicates that setting the PINMUX_IO register to 8’h80 enables the

MPEG_PAR_EN mode. This means that the existing serial MPEG port is augmented by GPIO [17:23] to enable a full parallel MPEG input port for connection of DVB channel demodulators (which typically use an 8-bit data interface conforming to ETSI document EN 50221). Alternatively , MPEG encoders outputting compressed data over an 8-bit path should use this mode. GPIO [0:16] become available for other functions such as 4:2:2 video input, output, or GPIO. This is illustrated in Figure 18.

Figure 18. MPEG Parallel Port

CX25800

11 12 13 14

1 2 3 4 8 9

TSCLK TSVAL/ERR TSSOP TSDAT[0] TSDAT[1] TSDAT[2] TSDAT[3] TSDAT[4] TSDAT[5] TSDAT[6] TSDAT[7]

GPIO[0:16]

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2.3.5 8-Bit Parallel VIP Host Master

Table 7 indicates that setting the PINMUX_IO register to 8’h40 enables the 8-bit VIP

Host Port mode. This means that the existing 2-bit VIP Host Port mode is augmented by GPIO [16:21] to enable a full 8-bit parallel VIP Host Master interface for connection of high performance digital video or graphics peripherals. GPIO [0:15,22:23] become available for other functions such as 4:2:2 video input, output, or GPIO. As seen from

Table 7, this mode is mutually exclusive from MPEG_PAR_EN. This mode is not

available on the CX25800. See Figure 19.

Figure 19. 8-bit Parallel VIP Host Master

20 19 18 17 16

CX25800

15 14 13 12

2.3.6 4-Bit Parallel VIP Host Master

Table 7 indicates that setting PINMUX_IO register to 8’h20 enables the 4-bit VIP Host

Port mode. This means that the existing 2-bit VIP Host Port mode is augmented by GPIO [16:17] to enable a 4-bit parallel VIP Host Master interface for connection of medium performance digital video or graphics peripherals. GPIO [0:15, 18:23] become available for other functions such as 4:2:2 video input, output, or GPIO. As seen from

Table 7, this mode is mutually exclusive from MPEG_PAR_EN.

VIPCLK VIRQ# VHCTL VHAD[0] VHAD[1] VHAD[2] VHAD[3] VHAD[4] VHAD[5] VHAD[6] VHAD[7]

GPIO[0:15, 22:23]

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2.3.7 Video Synchronous Pixel (SPI) Mode

This mode enables 8- or 10-bit 4:2:2 data to be output from the CX25800 to an external compressor or hardware deinterlacing integrated circuit, etc., which may not implement embedded video synchronization codes as used in ITU-R. BT656 or VIP

1.1 standards. If discrete video synchronization signals are required, this mode, invoked by setting PINMUX_IO register to 8’h08, should be used. As seen in Table 7, the GPIO [0:6] pins provide external synchronization signals, GPIO [8:15] pins are used for 8-bit 4:2:2 output samples, and GPIO [7, 16:23] pins are available for other functions. See Figure 20.

Figure 20. Video Synchronous Pixel (SPI) Mode

CX25800

111 112 113 114 115 116 117 118 119

124 125 126 127 128 129 130

GPCLKO VDO[9] VDO[8] VDO[7] VDO[6] VDO[5] VDO[4] VDO[3] VDO[2] V_NVRESET V_NHRESET V_HACTIVE V_VACTIVE V_CBFLAG V_FIELD V_VALID

GPIO[7,16:23]

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2.3.8 10-Bit ITU-R. BT656 Output Mode

This mode enables 10-bit 4:2:2 data to be output from the CX25800 to an external compressor or hardware deinterlacing integrated circuit etc. which implements embedded video synchronization codes as used in ITU-R. BT656 or VIP 1.1 standards. This mode is invoked by setting PINMUX_IO register to 8’h04. Table 7 indicates that the GPIO [8:15, 22:23] pins are used for 10-bit 4:2:2 output samples, and the GPIO [0:7, 16:21] pins are available for other functions. See Figure 21.

Figure 21. 10-bit ITU-R. BT656 Output Mode

CX25800

111 112 113 114 115 116 117 118 119

GPCLKO VDO[9] VDO[8] VDO[7] VDO[6] VDO[5] VDO[4] VDO[3]

VDO[2] 8 9

VDO[1]

VDO[0]

GPIO[0:7, 17:21]

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2.3.9 8-Bit ITU-R. BT656/VIP 2.0 Pixel Input Mode

This mode enables 8-bit 4:2:2 data to be input to the CX25800 from an external video de-compressor for scaling and DMA transfer to a VGA overlay surface for display. The incoming video data must adhere to 27 MHz ITU-R. BT656/VIP 1.1 or 8-bit VIP 2.0 pixel data at a maximum data rate of 54 MHz. This mode is configured by setting PINMUX_IO register to 8’h02. Table 7 indicates that the GPIO [0:7] pins are used for 8-bit 4:2:2 input samples, and the GPIO [8:23] pins are available for other functions. See Figure 22.

Figure 22. 8-bit ITU-R. BT656/VIP 2.0 Pixel Input Mode

CX25800

122 123 124 125 126 127 128 129 130

GPCLKI VDI[7] VDI[6] VDI[5] VDI[4] VDI[3] VDI[2] VDI[1] VDI[0]

GPIO[8:23]

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2.3.10 Host Port Chip Select Enable Mode

This mode enables four external peripheral devices to be connected to the CX25800 GPHP with simple glue decode logic. In conjunction with Pin 90 (HCS), GPIO[23] becomes a second chip select pin, thus enabling selection of up to four external peripherals. This mode is configured by setting PINMUX_IO register to 8’h01. Table7 indicates that GPIO [23] is used as the HCS[1] pin and the GPIO[0:22) pins are available for other functions. See Figure 23.

Figure 23. Host Port Chip Select Enable Mode

CX25800

110:106

101:91

90 89 87 88 86 85

HCS[1]#

HAD[0:4]

HAD[5:15]

HCS HREAD#/HDS# HWRITE/HRW# HALE# HRDY# HEXFB#

GPIO[0:22]

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2.4 Peripheral Component Interface

The Peripheral Component Interface (PCI) subsystem contains the interfaces, data buffers, and control registers to allow the high integrity, high bandwidth transfer of data between the CX25800 and the host. The subsystem is very flexible to allow being tailored to fit the many possible applications. Many features have been incorporated to enable the handling of PCI bus latencies with minimal data loss. Data is buffered internally using a programmable SRAM based architecture, and transferred using a unique RISC and DMA controller architecture. The PCI subsystem also allows the host to access all internal memory , internal registers and external peripheral registers. The interface is implemented as a 32-bit wide, 33-MHz data path that conforms to the PCI Local Bus Specification revision 2.3.

2.4.1 PCI Functions

The five peripherals of the CX25800 are assigned to the PCI functions detailed in

Table 8.

Table 8. PCI Functions

Function Peripheral

0Video 1Audio 2 Transport Stream 3 VIP Host Port 4GPHP

The CX25800 is configurable to have from one to five PCI functions depending on a particular application. For example, if an application only uses video, audio, and transport stream, the VIP Host Port and GPHP functions can be disabled. This is useful to eliminate the need for software drivers for unnecessary functions. Any combination of functions can be enabled or disabled, with the exception that function 0 cannot be disabled as required by the PCI specification.

Functions one through five are enabled using bits [1:4] of two-wire serial interface address 15’h5000, respectively, in the two-wire serial interface EEPROM which are automatically loaded into the CX25800 at reset. While the functions are automatically being configured after reset, any PCI accesses to the CX25800 are retried, to ensure that the PCI configuration space is established before the PCI system BIOS begins to access it. If no two-wire serial interface EEPROM is connected to the CX25800 through the two-wire serial interface, all functions are disabled except for function 0. The EEPROM can be programmed before being placed on the printed circuit board (PCB), or it can be written using the CX25800 two-wire serial interface control registers or the Vital Product Data (VPD) mechanism.

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2.4.2 PCI Configuration Space

Each enabled function has its own PCI configuration space. To allow independent control, there are separate registers for each of the following functions:

 Device ID  Command  Status  Master Latency Timer  Maximum Latency  Minimum Grant  Interrupt Line  Base Address  Power Management

A few registers, which contain information common to all functions, are shared although they appear in the configuration spaces of all functions (e.g., Vendor ID, Subsystem Vendor, Subsystem ID, and Vital Product Data). The CX25800 does not respond to an attempted configuration space access to a disabled function, and therefore the access terminates with a Master Abort, as required by the PCI specification.

2.4.3 PCI Subsystem IDs

The Subsystem ID and Subsystem Vendor ID registers are automatically loaded at reset with the data located in the two-wire serial interface EEPROM at two-wire serial interface address 15’h5004 through 15’h5007. While the registers are being loaded after reset, any PCI accesses to the CX25800 are retried, to ensure that the Subsystem ID and Subsystem Vendor ID are est ablished before the PCI system BIOS begins to access them. If no two-wire serial interface EEPROM is connected to the CX25800 through the two-wire serial interface, the Subsystem ID and Subsystem Vendor ID registers are loaded with 0. The EEPROM can be programmed before being placed on the printed circuit board (PCB), or it can be written using the CX25800 two-wire serial interface control registers or the Vital Product Data (VPD) mechanism. The Subsystem ID and Subsystem Vendor ID registers can also be written directly by software. To enable this, the SVIDS_EN bit in the Device Control #1 register must be first written to a 1.

2.4.4 Accessing VPD on the CX25800

To access the I²C EEPROM on the CX25800, the software application must add 15'h5008 to the address.

A typical example is when the application program needs to access memory address 15'h0020 in the I²C EEPROM. The application program must add 15'h5008 to the 15'h0020 address. The sum 15'h5028 is then written in the VPD_ADRS register.

The application program must add 15'h5008 to the address because there is no remapping of the I²C EEPROM in the CX25800. VPD starts at the physical address of 16'h5008. The 15-bit physical address maps directly to the EEPROM physical storage space. Addresses 11'h000-11'h007 are reserved in the EEPROM for function enables and Subsystem Vendor ID. Therefore, the first available VPD address is 15'h5008.

The two-wire serial interface EEPROM can be read any time by using the two-wire serial interface hardware, software, or direct mode.

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2.4.5 PCI Specification Regarding VPD Implementation

Section 6.4 (Vital Product Data) in PCI Specification revision 2.3 states that implementation of VPD is optional. In addition, operating systems such as Microsoft Windows and system BIOS do not access VPD data during the PCI configuration cycle of the system.

2.4.6 Using VPD Data with Multiple Functions on One Card

Function 0 for video is the only function that uses VPD. This is permitted as indicated by the fourth paragraph preceding Figure I-2 in Appendix-I of PCI Specification

revision 2.3.

2.4.7 PCI Power Management

The CX25800 implements the power management mechanism according to the PCI Bus Power Management Interface Specification Revision 1.1. Power states D0 (on), D3cold (off), and D3hot are supported. When the power state of all enabled functions is D3hot, the CX25800 goes into a low-power consumption mode.

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2.4.8 Memory Space

The CX25800 registers and 32 kB SRAM are mapped into the 16 MB address space defined by each PCI function Base Address register. This means that the registers and SRAM can be accessed in the memory space of any function. The memory map in

Table 9 indicates the 24-bit offset from the base address of the functions.

Table 9. CX25800 Memory Space

Beginning Address Resource

24’h000000 unused 24’h180000 SRAM (32 kB) 24’h188000 unused 24’h200000 DMAC 24’h310000 Video 24’h320000 Audio

2.4.9 PCI Data Streaming

The CX25800 uses the resources in the PCI Subsystem to stream data between its peripherals and the host processor, across the PCI bus. A total of 12 streams of data are supported, and can be active simultaneously, although the typical application scenario uses a subset of the streams. The streams are independent from each other and are controlled on an individual basis. There are two types of data stream channels: downstream and upstream. A downstream channel transfers data from a peripheral to the host memory using the PCI bus. An upstream channel transfers data from the host memory to a peripheral using the PCI bus. High performance internal data paths and programmable depth FIFOs are used to optimize the throughput of data across the PCI bus. The programmable depth FIFOs, which are implemented using the internal SRAM, decouple the constant rate flow of peripheral data from the bursts and latencies of the PCI bus. The channels have been assigned an arbitrary number that is used for identification. Table 10 lists the channel information.

24’h330000 Transport Stream 24’h340000 VIP 24’h350000 Miscellaneous 24’h360000 Two-Wire Serial Interface 24’h370000 unused 24’h380000 General Purpose Host 24’h3D0000 unused

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Table 10. MA Channel Assignment

Channel Number

21 Video packed or planar Y (luminance) down 48 22 Video planar U (chrominance) down 6 23 Video planar V (chrominance) down 6 24 Video VBI (vertical blanking interval data) down 36 25 Audio down 0.2 26 Audio (to digital-analog converters) up 0.2 28 Transport Stream (MPEG) down 9 29 VIP Host (from Video Interface Port peripheral) down 6.5 30 VIP Host (to Video Interface Port peripheral) up 6.5 31 GP Host (from General Purpose Host

peripheral)

32 GP Host (to General Purpose Host peripheral) up 6.5

Purpose Type BW

down 6.5

max

(MHz)

2.4.10 SRAM

The CX25800 contains an internal 32 kB SRAM that is used to store data and control information for the active streams. The use of the SRAM is programmable to accommodate a wide range of application scenarios. For example, an application can implement larger FIFOs on high bandwidth streams and smaller FIFOs on low bandwidth streams to handle the transfer latencies that may be encountered on the PCI bus. A multiple stream application may have some streams that are more tolerant to occasional data loss than others. The more critical streams can use deeper FIFOs, while the more tolerant streams can use smaller FIFOs. In addition to the FIFOs, the SRAM is used for control information, namely, RISC instruction queues, Channel Management Data Structures (CMDS), and optionally RISC programs. For each application, the FIFO depth for each stream is programmable, with the obvious restriction that the SRAM space used for the FIFOs plus the control information for all the active streams, cannot exceed 32 kB.

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2.4.11 FIFO Size Calculation

FIFOs are used to decouple the constant data rate stream and the burst transfer nature of the PCI bus. Although the PCI bus has sufficient average bandwidth to accommodate the demands of the peripherals, latencies can exist that are significant and can cause loss of peripheral data if no buffering is provided. The amount of FIFO buffering required depends on the average bandwidth of the peripheral data and the duration of PCI latencies to be tolerated. Latencies encountered on PC systems are usually in the 10–20 microsecond range, with occasionally longer latencies of 100– 200 ms. By sizing the FIFO buffers properly, most applications are able to protect its streams from the PCI latencies that are commonly encountered. The amount of buffering is the multiplication product of the average bandwidth of the data stream and the PCI latency duration.

The following is an example calculation of the FIFO buffer required for a video PAL, 768 pixel x 576 lines, RGB16 stream to tolerate a 200 microsecond PCI latency. The data stream bandwidth would be 24 MBps (25 frames per second * 625 total lines per frame * 768 pixels per line * 2 bytes per pixel = 24 MBps). The amount of FIFO buffering required would be 4800 bytes (24 MBps * 200 ms = 4800 bytes). Since the FIFO buffer must be a multiple number of lines and be two or greater, the FIFO buffer would actually be 6144 bytes (4800 bytes / 2 bytes per pixel / 768 pixels per line =

3.125 lines, rounded up to 4 lines * 768 pixels per line * 2 bytes per pixel = 6144 bytes). The actual latency protection would be 256 ms (6144 bytes / 24 MBps = 256 ms). Rounding down to 3 lines would require only 4608 bytes (3 lines * 768 pixels per line * 2 bytes per pixel = 4608 bytes), which would provide latency protection of 192 ms (4608 / 24 MBps = 192 ms).

The following is an example calculation of the FIFO buffer required for an ATSC MPEG transport stream (2.5 MBps) to tolerate a 200 microsecond PCI latency. The artificial line length is arbitrary, and the value chosen affects the size of the FIFO as it must be a multiple number of lines. This example is done using an artificial line length of 4 MPEG packets, which is 752 bytes (4 packets * 188 bytes per packet). The amount of FIFO buffering required would be 500 bytes (2.5 MBps * 200 ms = 500 bytes). Since the FIFO buffer must be a multiple number of lines and must two or greater, the FIFO buffer would actually be 1504 bytes (752 bytes per line * 2 lines = 1504 bytes). The actual latency protection would be 601.6 ms (1504 bytes / 2.5 MBp s = 601.6 ms).

2.4.12 Programmable FIFO

A programmable FIFO is implemented in the SRAM using a number of equal sized buffers, known as Cluster Buffers, and a table of pointers to the buffers, known as a Cluster Descriptor Table (CDT). The CDT table must be initialized before the APB DMAC CNT2 register is initialized, and before the FIFO_EN bit is set to 1. In addition, PTR2 and CNT1 must be initialized before the FIFO_EN bit is set to 1. The number of buffers and the size of the buffers are programmable, and are chosen based on the depth of the FIFO needed. For example, if a 1 kB FIFO is needed for a stream, it could be implemented using 4, 256 byte buffers. A different stream could have a 1 kB FIFO implemented using 8, 128 byte buffers.

Although the number and size of the buffers are programmable, there are a few restrictions. The number of buffers must be two or greater. This allows the peripheral to be streaming data to or from a buffer , while the PCI DMA controller bursts dat a to or from a different buffer. Each buffer must large enough to accommodate one and only one line of peripheral data, and be an integer number of qwords (8 bytes). For video streams, the line size is dependent on the video format. For example, a 768 pixel x

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576 line, RGB32 format would have 3 kB lines. The other downstream peripherals are not inherently line based and therefore use an artificial line length chosen by the application. For example, an MPEG Transport Stream may chose a line length equal to four packets, which would be 752 bytes (4x 188 bytes).

To specify the buffer size, use the DMAx_CNT1 register, where x is the number of the stream from Table 2-6. The register is written with the number of qwords minus one. For example, to specify 3 kB as the size of the buffers for the packed video stream, write 11’h17F to the DMA21_CNT1 register. To specify the buffer locations, use the CDT as described in the following paragraphs.

The set of buffers that make up a FIFO are supported by a CDT, which is also located in the SRAM. The table contains a four-dword descriptor for each buffer; therefore, the size of the CDT is directly related to the number of buffers that make up the FIFO. For example, a FIFO that was made up of three buffers would have a three entry table which would be a total of 48 bytes. The first dword of each entry is the address of the beginning of the buffer . The a ddress is a 24-bit SRAM address (24’h18xxxx) and must be dword aligned. The other three dwords of each descriptor are reserved for use by the internal hardware.

To specify the CDT size, use the DMAx_CNT2 register, where x is the number of the stream from Table 2-6. The register is written with the number of qwords. For example, to specify 48 bytes as the size of the CDT for the packed video stream, write 11’h006 to the DMA21_CNT2 register. This value must also be written to the CDT Size field in the Channel Management Data Structure (CMDS).

To specify the SRAM location of the CDT , use the DMAx_P TR2 register , where x is the number of the stream from Table 2-6. The register is written with the 24-bit SRAM address (24’h18xxxx) and must be dword aligned. For example, to specify 15’h1000 as the CDT location for the packed video stream, write 24’h181000 to the DMA21_PTR2 register. This value must also be written to the CDT Base field in the Channel Management Data Structure (CMDS).

To specify the SRAM locations of the buffers, use the first dword of each descriptor in the CDT. The register is written with the 24-bit SRAM address (24’h18xxxx) and must be dword aligned. For example, to specify the SRAM locations for the start of three, 3 kB buffers to be 15’h2000, 15’h2C00, and 15’h3800, using a CDT that is located at 15’h1000, write 24’h182000 to 24’h181000, 24’h182C00 to 24’h181010, and 24’h183800 to 24’h181020.

The CDT and buffers can be located anywhere in the SRAM with the exception of the address range 15’h0000 to 15’h033F, which is reserved for the Channel Management Data Structures.

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2.4.13 RISC Instruction Queue

The CX25800 DMA architecture includes a RISC controller, which is programmed using a simple set of RISC instructions. A series of RISC instructions form a program that specifies the PCI target addresses and the amount of data to be read or written by the CX25800 DMA controller. The RISC programs are generated by the software driver on the host and are stored either in host memory or in CX25800 SRAM. A valid RISC program must be in place before the corresponding RISC_EN bit is set to 1. Each active stream implements a RISC instruction queue in the SRAM to maximize the flow of instructions from the program memory to the RISC controller. When the RISC controller has no other higher priority task to attend to, such as transferring stream data, it attempts to keep the instruction queue full. This increases the system performance as the RISC controller virtually always has the next instruction available in SRAM when it needs it, and does not have to wait until it can fetch it from the host memory. The instruction queues are programmable in size and location in the SRAM. The minimum size is 8 dwords, the maximum size is 255 dwords, and the typical size is 16 dwords. Use the Instruction Queue Base and Instruction Queue Size fields in the Channel Management Data Structure (CMDS) to specify the location and size. The address must be dword aligned, and the size is in dwords. For example, to specify the packed video instruction queue to be 16 dwords in size and begin at address 15’h0400 in the SRAM, write 24’h180400 to address 24’h18004C, and write 8’h10 to address 24’h180050. See Figure 24 for an example.

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Figure 24. SRAM Resource Example

Registers

DMA21_PTR2

24'h18100024'h3000C0

DMA21_CNT2

11'h00624'h300140

DMA21_CNT1

11'h17F24'h300100

CMDS

Instruction

Queue

CDT

24'h180000 24'h18003F 24'h180040 24'h180044 24'h180048

24'h18004C

24'h180050

24'h18033F

24'h180400

24'h18403F

24'h181000 24'h181004 24'h181008

24'h18100C

24'h181010 24'h181014 24'h181018

24'h18101C

24'h181020 24'h181024 24'h181028

24'h18102C

SRAM

Reserved

24'h181000

11'h006

24'h180400

8'h10

Unused

24'h182000

Reserved

24'h182C00

Reserved

24'h183800

Reserved

Unused

24'h182000

Buffer 1

24'h182BFF

24'h182C00

Buffer 2

24'h1837FF

24'h183800

Buffer 3

24'h1843FF

Unused

24'h187FFF

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2.4.14 Channel Management Data Structure

The CX25800 uses the SRAM to store information to manage each stream channel. This information is called the Channel Management Data Structure (CMDS) and is fixed in the SRAM from address 15’h0040 to 15’h033F. The CMDS for each channel is located in the SRAM as shown in Table 11.

Table 11. Channel Management Data Structure

Number Purpose CMDS Base

21 Video packed or planar Y (luminance) 15’h0040 22 Video planar U (chrominance) 15’h0080 23 Video planar V (chrominance) 15’h00C0 24 Video VBI (vertical blanking interval data) 15’h0100 25 Audio 15’h0140 26 Audio (to digital to analog converters) 15’h0180 28 Transport Stream (MPEG) 15’h0200 29 VIP Host (from Video Interface Port peripheral) 15’h0240 30 VIP Host (to Video Interface Port peripheral) 15’h0280 31 GP Host (from General Purpose Host peripheral) 15’h02C0 32 GP Host (to General Purpose Host peripheral) 15’h0300

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The CMDS is composed of 16 dwords. The first five dwords (shown in gray in

Figure 25) are information that is supplied by the host software to control and set up

the RISC controller. The next ten dwords (shown in white in Figure 25) are used by the RISC controller to manage the stream channel. These fields are not to be written by the host software, although they can be read to monitor the channel information. The last dword (shown in black) is reserved and not used at this time, as are the rest of the fields shown in black in Figure 25. This figure also shows the layout of the CMDS. The fields of the CMDS are described in the next paragraph.

Figure 25. Channel Management Data Structure

Offset

6'h00

6'h04

6'h08

6'h0C

6'h10

6'h14

6'h18

6'h1C

6'h20

6'h24

6'h28

6'h2C

6'h30

6'h34

Channel Management Data Structure

24 16 8 0

Initial RISC Program Counter

CDT Base

Instruction Q Base

ISRP SRP

Line Count Current Byte Count Current

RISC Instruction DWORD 0 Current

RISC Instruction DWORD 1 Current

RISC Instruction DWORD 2 Current

RISC Program Counter

Instruction Q Write Pointer

Instruction Q Read Pointer

CDT Current

PCI Target Address Current

CDT Size

Instruction Q Size

6'h38

6'h3C

RISC Instruction DWORD 3 Current

Initial RISC Program Counter[31:0]

Location of the first RISC instruction. In SRAM Resident Program mode (SRP =1), this location is an SRAM address, and only bits [23:0] are relevant. In PCI Memory Resident Program mode (SRP = 0), it is a PCI target address of the host memory . The SRP bit is located at bit [31] in the dword at offset 6’h10.

CDT Base[23:0]

Location of beginning of the CDT in the SRAM. This address must match the address written to the DMAx_PTR2 register, where x is the number of the stream from

Table 2-6. See the description of the CDT in the Programmable FIFOs section.

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CDT Size[10:0]

The size in qwords of the CDT. This value must match the size written to the DMAx_CNT2 register, where x is the number of the stream from Table 2-6. See the description of the CDT in the Programmable FIFOs section.

Instruction Q Base[23:0]

Location of the beginning of the RISC instruction queue.

Instruction Q Size[7:0]

The size in dwords of the RISC instruction queue.

ISRP[31] (Initial SRAM Resident Program)

Used to specify whether the address in the Initial RISC Program Counter field is an SRAM address (ISRP =1), or a PCI target address (ISRP = 0).

RISC Program Counter[31:0]

The RISC controller uses this as temporary storage for the address of the current RISC instruction it is processing.

SRP[31] (SRAM Resident Program)

Used by the RISC controller to determine whether the program counter contains an SRAM address (SRP =1), or a PCI target address (SRP = 0).

Instruction Q Write Pointer[13:0]

Used by the RISC controller to maintain the location of the next dword to be written. This is a dword address, not a byte address.

Instruction Q Read Pointer[13:0]

Used by the RISC controller to maintain the location of the next dword to be read. This is a dword address, not a byte address.

CDT Current[15:0]

The RISC controller uses this as temporary storage for the current entry in the CDT that is being processed.

PCI Target Address Current[31:0]

The RISC controller uses this as temporary storage for the current PCI target address.

Byte Count Current[11:0]

The RISC controller uses this as temporary storage for the number of bytes of the current line that have been processed.

Line Count Current[25:16]

The RISC controller uses this as temporary storage for the current line it is processing.

RISC Instruction DWORD 0-3 Current[31:0]

The RISC controller uses this as temporary storage for the current instruction being processed.

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2.4.15 RISC Controller

The CX25800 DMA architecture includes a RISC controller, which coordinates the transfer of data over the 12 stream channels. Although each channel has independent control and data buffering, they are all handled by the single RISC controller. The RISC controller is put into a reset state whenever the CX25800 is reset. To allow the RISC controller to operate the RUN_RISC bit[5] in the Device Control #2 register must be set to 1. The RISC controller can be returned to the reset state at any time by clearing the RUN_RISC bit to 0.

2.4.16 RISC Instructions

The RISC controller processes a program made up of a series of RISC instructions. The purpose of the RISC program is to specify the PCI target addresses and the amount of data to be read or written by the CX25800 DMA controller. The RISC programs are generated by the software driver on the host and are stored either in host memory or in CX25800 SRAM. The address of the beginning of the program must be written to the Initial RISC Program Counter field in the CMDS. When the channel is turned on, the RISC controller loads the initial program counter into the program counter and begin processing the instructions. Programs that are stored in the host memory are called PCI Memory Resident Programs, while programs that are stored in the CX25800 SRAM are called SRAM Resident Programs. To indicate whether the address in the Initial RISC Program Counter is a PCI memory address or a CX25800 SRAM address, the Initial SRAM Resident Program (ISRP) bit must be written. The ISRP bit is bit [31] at offset 6’h10 in the CMDS. A PCI Memory Resident Program is specified by writing the ISRP bit to 0, an SRAM Resident Program is specified by writing the ISRP bit to 1. See Figure 2-11, Channel Management Data Structure.

The RISC instruction set is composed of 10 instructions that can be categorized as downstream, upstream, and common to both directions. The downstream instructions are SYNC, WRITE, and WRITEC. The upstream instructions are READ and READC. The instructions that can be used in both downstream and upstream programs are JUMP, SKIP, WRITERM, WRITECM, and WRITECR. See Figure 26 through 2-21 for RISC instruction specifics.

Figure 26. SYNC Downstream RISC Instruction

3 1

SYNC

OPCODE

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IRQ2

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LINE COUNT

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Figure 27. WRITE Downstream RISC Instruction

262

IRQ1

IRQ2

EOL

SOL

WRITE

3 1

000 1

OPCODE

3 1

2 8

Figure 28. WRITEC Downstream RISC Instruction

262

IRQ1

IRQ2

EOL

WRITEC

3 1

0011

OPCODE

2 8

PCI TARGET ADDRESS

CNT_CTL

1 1

BYTE COUNT

Figure 29. READ Upstream RISC Instruction

262

IRQ1

IRQ2

EOL

SOL

READ

3 1

1001

OPCODE

3 1

2 8

PCI TARGET ADDRESS

CNT_CTL

1 1

BYTE COUNT

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Figure 30. READC Upstream RISC Instruction

262

READC

3 1

1 010

OPCODE

Figure 31. SKIP RISC Instruction

262

2 8

SKIP

3 1

0010

OPCODE

Figure 32. Jump RISC Instruction

2 8

JUMP

3 1

0111

OPCODE

IRQ1

IRQ2

EOL

IRQ1

IRQ2

EOL

SOL

IRQ1

IRQ2

CNT_CTL

1 1

BYTE COUNT

1 1

BYTE COUNT

SRP

3 1

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Figure 33. WRITERM RISC Instruction

2 5

WRITERM

3 1

1011

OPCODE

3 1

2 8

Figure 34. WRITECM RISC Instruction

2 5

WRITECM

3 1

1100

OPCODE

2 8

2 4

IRQ1

IRQ2

PCI TARGET ADDRESS

2 4

IRQ1

IRQ2

CNT_CTL

IMM

3 1

PCI TARGET ADDRESS

3 1

CONSTANT

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Figure 35. WRITECR RISC Instruction

WRITECR

3 1

1101

OPCODE

3 1

2 8

IRQ1

IRQ2

CONSTANT

MASK

CNT_CTL

IMM

All instructions contain two interrupt bits, IRQ1 and IRQ2, that can be used to set the RISCI1 and RISCI2 bits respectively, in the interrupt status register of the corresponding function. This allows a PCI interrupt to be generated when the instruction is executed by the RISC controller. All instructions have control bits for the general purpose counter associated with each channel. This allows the software driver to count RISC program events. The two bit CNT_CTL field is coded for the following action: 2’b00 = no change, 2’b01 = increment, 2’b10 = reserved, 2’b11 = reset to 0.

SYNC is a one-dword instruction as shown above. It is used only in downstream channels to specify which line to synchronize to. This is especially important for the video streams, which are by nature line based. The lines of the odd video field are numbered starting at 10’h000, while the lines of the even video field are numbered starting at 10’h200. The other downstream channels are not naturally line based, and therefore use artificial lines. Each downstream channel has a line length register to program the number of bytes in each line. Typically, the streams that have artificial lines use a SYNC to line 10’h000 instruction.

The RISC controller discards the data of all lines until it encounters the line specified in the SYNC instruction. The SYNC instruction is then complete, and the next instruction is processed. If the RESYNC bit is 0, the x_SYNC bit in the interrupt status register of the corresponding function is set, where x is the associated channel. If the RESYNC bit is 1, the interrupt bit is not set.

WRITE is a two-dword instruction, as shown above. It is used only in downstream channels to specify the number of bytes of the current line to transfer, and the PCI target address to which the data must be written. The WRITE instruction is used to write an entire line or a portion of a line. It cannot be used to write multiple lines. The SOL (start of line) and EOL (end of line) bits are used to specify the portion of the current line to be processed by the instruction. The SOL bit must be set when the instruction applies to the beginning of the line (i.e., no portion of the line has been transferred or discarded by the previous instruction). The EOL bit must be set when the instruction applies to the end of the line (i.e., all data of the line has been transferred). See Table 12 for the possible combinations. If these bits do not match the

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expectations of the RISC controller, the x_SYNC bit in the interrupt status register of the corresponding function is set, where x is the associated channel.

Table 12. SOL/EOL Combinations

SOL EOL Usage

1 0 A beginning portion of the line. 0 0 A middle portion of the line. 0 1 An ending portion of the line. 1 1 The entire line.

WRITEC is a one-dword instruction, as shown above. It is used only in downstream channels to continue the processing of a line that has been started by a previous WRITE or SKIP. The data is written to the PCI target address that immediately follows the last address accessed by the previous WRITE or SKIP. The WRITEC instruction can also follow other WRITEC or SKIP instructions. There is no SOL bit, as WRITEC cannot be used to transfer the beginning of a line. The EOL bit must be set when the instruction applies to the end of the line (i.e., all data of the line has been transferred). See Table 2-8 for the possible combinations. If this bit does not match the expectations of the RISC controller, the x_SYNC bit in the interrupt status register of the corresponding function is set, where x is the associated channel.

READ is a two-dword instruction as shown above. It is used only in upstream channels to specify the number of bytes of the current line to transfer, and the PCI target address to which the data must be read. The READ instruction is used to read an entire line or a portion of a line. It cannot be used to read multiple lines. The SOL (start of line) and EOL (end of line) bits are used to specify the portion of the current line to be processed by the instruction. The SOL bit must be set when the instruction applies to the beginning of the line (i.e., no portion of the line has been transferred or discarded by the previous instruction). The EOL bit must be set when the instruction applies to the end of the line (i.e., all data of the line has been transferred). See

Table 2-8 for the possible combinations. If these bits do not match the expectations of

the RISC controller, the x_SYNC bit in the interrupt status register of the corresponding function is set, where x is the associated channel.

READC is a one-dword instruction, as shown above. It is used only in upstream channels to continue the processing of a line that has been started by a previous READ or SKIP. The data is read from the PCI target address that immediately follows the last address accessed by the previous READ or SKIP. The READC instruction can also follow other READC or SKIP instructions. There is no SOL bit, as READC cannot be used to transfer the beginning of a line. The EOL bit must be set when the instruction applies to the end of the line (i.e., all data of the line has been transferred). See Table 2-8 for the possible combinations. If this bit does not match the expectations of the RISC controller, the x_SYNC bit in the interrupt status register of the corresponding function is set, where x is the associated channel.

SKIP is a one-dword instruction, as shown above. It is used both in downstream and upstream channels to specify the number of bytes of the current line to discard. The data is discarded beginning at the PCI target address that immediately follows the last address accessed by the previous instruction. The PCI target address is advanced by the number of bytes in the instruction. The SKIP instruction is used to discard an entire line or a portion of a line. It cannot be used to discard multiple lines. The SOL (start of line) and EOL (end of line) bits are used to specify the portion of the current line to be

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processed by the instruction. The SOL bit must be set when the instruction applies to the beginning of the line (i.e., no portion of the line has been transferred or discarded by the previous instruction). The EOL bit must be set when the instruction applies to the end of the line (i.e., all data of the line has been transferred). See Table 2-8 for the possible combinations. If these bits do not match the expectations of the RISC controller, the x_SYNC bit in the interrupt st atus register of the corresponding function is set, where x is the associated channel.

JUMP is a two-dword instruction, as shown above. It is used both in downstream and upstream channels to load the current program counter with the specified address. The jump address can be either an SRAM address (SRP = 1) in which case only address bits [23:0] are relevant, or a PCI target address (SRP = 0) in which case all 32 address bits are used.

WRITERM is a three-dword instruction, as shown above. It is used both in downstream and upstream channels to write the value of a CX25800 register specified by the address field to the PCI target address. This instruction is typically used as a debug tool, but may be found to useful in some special situations. The only registers that can be used with WRITERM are the ones referred to as immediate, which are shown in Table 13. The IMM bit must always be set to 1.

Table 13. WRITERM Registers

Address Range Resource

24’h18xxxx SRAM 24’h20xxxx Miscellaneous registers 24’h30xxxx Miscellaneous registers 24’h31Cxxx Video registers 24’h32Cxxx Audio registers 24’h33Cxxx Transport Stream registers 24’h34Cxxx Video Interface Port Host registers 24’h35xxxx Miscellaneous registers 24’h38Cxxx General Purpose Host registers

WRITECM is a three-dword instruction, as shown in Figure 2-20. It is used both in downstream and upstream channels to write a 32-bit constant value to the PCI target address. This instruction is typically used as a debug tool, but may be found to useful in some special situations.

WRITECR is a four-dword instruction, as shown above. It is used both in downstream and upstream channels to write a 32-bit constant value to a CX25800 register specified by the address field according to the specified mask. A 1 in any bit position of the mask field causes the corresponding bit in the constant field to be written to the specified register. A 0 in any bit position of the mask field causes the corresponding bit in the register to be left unchanged. This instruction is typically used as a debug tool, but may be found to useful in some special situations. It is often used to turn on the FIFO enable bit of an upstream channel after the FIFO has been filled by previous READ instructions. The only registers that can be used with WRITECR are the ones referred to as immediate, which are shown in Table 2-9. The IMM bit must always be set to 1.

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2.4.17 Data Stream Control

Each of the 12 stream channels has a RISC_EN bit to control whether the RISC controller is actively processing the stream of data. The RISC_EN bit is located in the Streaming Enable register of the VIP and general purpose host functions, and in the DMA Control register of the video, audio, and transport stream functions. This bit is used to turn on the streaming of a channel after it has been configured (i.e., FIFO, RISC instruction queue, CMDS, RISC program, peripheral specific setup). This bit is used to turn off the streaming of a channel at any time by clearing it to 0.

Each of the 12 stream channels has a FIFO_EN bit to control whether the peripheral is actively storing data to the FIFO (in the case of a downstream channel) or taking data from the FIFO (in the case of an upstream channel). The FIFO_EN bit is located in the Streaming Enable register of the VIP and general purpose host functions, and in the DMA Control register of the video, audio, and transport stream functions.

In the downstream channels, the FIFO_EN bit is typically turned on at the same time as the RISC_EN bit, as they are in the same register. A valid RISC program must be in place before the corresponding RISC_EN bit is set to 1. In the upstream channels, the RISC_EN bit is typically turned on by the software driver writing the register, and the FIFO_EN bit is turned on by the upstream RISC program with a WRITECR instruction. This allows the RISC controller to fill the FIFO with data before the peripheral begins taking data from it.

2.4.18 Data Stream User Guide

The following is a description of the steps that must be taken to stream data using the CX25800. These steps are described in the following sections, and must be executed in the sequence listed below.

1. Initialize the CDT in SRAM.

2. Initialize the APB DMAC to use the CDT.

3. Build the RISC program in PCI memory or SRAM.

4. Initialize the Channel Management Data Structure in SRAM.

5. Enable the RISC controller.

6. Configure the peripheral.

7. Enable the peripheral.

Step 1: FIFO Buffer Size

Based on the bandwidth of the data stream and the PCI latency to tolerate, determine the amount of FIFO data buffering needed. Then based on the line size of the data stream, determine the number of cluster buffers are needed to provide the total data buffer requirement. This determines the number of entries needed in the CDT.

Step 2: CDT

Choose the locations for the cluster buffers in the SRAM and program the pointer to each using the first dword of each descriptor of the CDT. The remaining three dwords of each descriptor do not need to be initialized by the software, as the RISC controller initializes them upon being enabled. This table does not need to be reinitialized by the software when the data stream is disabled. The only time it must be changed is when the cluster buffers need to move, or additional entries are desired in the table.

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Step 3: Cluster Buffer Size

Based on the line size of the data stream (from video format or artificial) specify the cluster buffer size in qwords using the DMAx_CNT1 register, wh ere x is the number of the stream from Table 2-6. This register does not need to be reinitialized by the software when the data stream is disabled. The only time it needs to change is when the cluster buffers size needs to change.

Step 4: CDT Location and Size

Specify the SRAM location of the CDT using the DMAx_PTR2 register, where x is the number of the stream from Table 2-6. Based on the number of entries in the CDT, specify its size in qwords using the DMAx_CNT2 register, where x is the number of the stream from Table 2-6. These registers must be reinitialized by the software before the data stream is enabled.

NOTE:

Writing DMA{x}_CNT2 registers (location 24’h300140_14C) causes the hardware to begin using the CDT information. It is imperative to perform this step only after initialization of the Cluster Description Table, Cluster Buffer Size, and CDT location.

Step 5: RISC Program

Place the RISC program into PCI memory or SRAM depending on where it is to reside. The RISC program can reside in noncontiguous blocks of memory, with the JUMP instruction used to load the program counter with the address of the beginning of the next block.

Step 6: Channel Management Data Structure (CMDS)

Write the address of the beginning of the RISC program in the Initial RISC Program Counter field. Depending on whether the program resides in PCI memory or SRAM, write the ISRP bit.

Write the CDT Base and Size with the same values written to the DMAx_PTR2 and DMAx_CNT2 registers, respectively.

Decide the size and location in the SRAM of the RISC instruction queue. Write the Instruction Q Base and Size with the respective values. The size value is expressed in dwords. A size of 16 dwords is typical.

These fields do not need to be reinitialized by the software when the data stream is disabled.

Step 7: Configure Peripheral

Program any downstream line length register. Program any other configuration registers specific to the operation of the peripheral. Clear the interrupt status register and set the interrupt mask register of the function

(video, audio, MPEG transport stream, VIP, general purpose host). Set the mask of the PCI interrupt register.

Step 8: Enable RISC Controller

The RISC controller is held in a reset state by default after the CX25800 has been reset. Enable it to run by setting the RUN_RISC bit[5] in the Device Control #2 register to 1. The RISC controller does not begin to execute instructions and process data stream until the RISC enable bit for the data stream is set to 1.

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Step 9: Enable Peripheral Data Stream

Enable the RISC controller to begin executing instructions and processing the data stream by setting the RISC_EN bit to 1. The RISC_EN bit is located in the Streaming Enable register of the VIP and general purpose host functions, and in the DMA Control register of the video, audio, and transport stream functions.

Enable the downstream peripheral to begin storing data to the FIFO. This is done by setting the FIFO_EN bit to 1. This is typically done at the same time as the RISC_EN bit is done, as they are in the same register.

Upstream peripherals are typically enabled using a WRITECR RISC instruction to set the FIFO_EN bit to a 1. This allows the RISC controller to fill the FIFO with data, providing PCI latency protection, before the peripheral begins taking data from it.

2.4.19 PCI Master

The PCI master uses the cache line commands, Memory Write and Invalidate, Memory Read Line, and Memory Read Multiple, when appropriate, if enabled by the Memory Write and Invalidate Enable bit in the PCI Configuration Space Command register.

The PCI master arbitrates between writing the downstream data and reading the upstream or RISC instruction data. The transfer in either direction continues until completion, and then switches to transfer in the other direction. An exception to this is if the target terminates with RETRY consecutively and reaches the retry limit value programmed into the DMA_RTRY_LMT field in the Device Control #1 register. When this occurs, the master switches to transfer in the other direction.

A small percentage of PCI core logic chip sets may start a bus transaction during the same cycle that GNT# is deasserted. This is not PCI 2.3 compliant. To ensure compatibility when using PCs with these PCI core logic chip sets, the EN_VSFX bit in the Device Control #1 register is provided. When in this mode, the GNT# is not passed to the CX25800 master unless its REQ# is asserted. This prevents a bus transaction from starting the same cycle as GNT# is deasserted. This also has the side effect of not being able to take advantage of bus parking, this lowering arbitration performance. The CX25800 software driver must query for these noncompliant chip sets, and set the EN_VSFX bit only if required.

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2.5 MPEG Data Port

The CX25800 has a dedicated high-speed port to receive MPEG transport, elementary or program streams from digital television channel demodulators or video compressors/codecs. Using DMA, these streams are sent to the host for softwarebased decompression or storage.

2.5.1 Video Compressors/Codecs

Alternatively, this port can be used to transfer compressed MPEG II or MPEG IV streams from video compressors/codecs that support compressed data output over a non-CPU-based bus, where data is continuously output and is synchronized either to an output clock or a data valid signal. The MPEG data port can absorb data rates up to 80 Mbps without throttling.

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2.5.2 Serial vs. Parallel Interface

The MPEG data port can be configured for either a serial or parallel mode connection according to the functionality of the chosen channel demodulator or the video compressor/codec. Figure 36 illustrates the MPEG port serial interface.

If the channel demodulator or video compressor/codec supports both a serial and a parallel mode capability, the serial mode connection allows pins to be freed up and assigned as GPIO if desired.

NOTE:

Figure 36. MPEG Port Serial Interface

DTV Channel Demodulator

Vi deo Com p re sso r/ Co d e c

For very high-speed data applications (>40 Mbps), the parallel interface mode eases board layout concerns.

CX25800

Cl o c k

St ar t o f Pa ck et

Error/Valid

Se r i al D a t a

TSCLK

TSSO P

TSE RR/ T SV A L

TSDATA [0 ]

2.5.3 MPEG ES (Elementary Stream)

Use Register IPB_AUTO_SOP in punctured clock mode to internally generate a start of packet for applications that have a continuous stream with no start of packet signal such as a MPEG elementary stream. This mode must be used with IPB_SOP_SEL set to 2'h3. Also, use IPB_CAP_ALL when doing elementary stream. IPB_CAP_ALL when set to 0, the SOP (first start of packet) is ignored to allow the logic to get reliably synchronized to the data stream. While discarding a packet of MPEG transport stream is not a problem, losing the beginning of an MPEG elementary stream can be a serious problem.

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HW SOP Control (Immediate Access)

Bits Type Default Name Description

[23:16] RW 8’d47 IPB_STRT_BYTE Byte start pattern that is searched for in the MPEG transport

stream that signals start of transport stream. This is issued

every mpeg packet. [15:4] RW 12’d188 IPB_PKT_LNGTH Used to sync/mark detect SOP [3] RW 1’b0 IPB_ CAP_ALL A value of 1 allows all data of a punctured clock stream to be

captured. A value of 0 will result in the first two packets to be

lost. This bit must only be set to 1 when in punctured clock

mode. [2] RW 1’b0 IPB_ AUTO_SOP A value of 1 eliminates the need for an external start of packet

in punctured clock mode. It must only be used with

IPB_SOP_SEL = 00. A value of 0 allows all other start of

packet modes to be used. [1:0] RW 2’b00 IPB_STRT_FLTR_CNT Defines the number of IPB_strt_bytes that need to be detected

before the mpeg fec interface is declared as being in sync.

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2.6 Video Decoder

This section describes the functionality of the analog video decoder in sequence from the video input at the analog front end to the output of digital video pixels from the pixel engine to the internal peripheral bus. For details of the analog front-end interfacing circuit to baseband video signals, see Chapter 3.

2.6.1 Video Input Multiplexer

The CX25800 has a 4:1 multiplexer that can be used to switch between four composite video sources. This multiplexer is controlled by the YADC_SEL bits 14 and 15 of the Input Format register.

Input Format Register Register 24’h310104

Bits Type Default Name Description

[15:14] RW 2’b00 YADC_SEL Video input source selection.

00 = MUX1 01 = MUX2 10 = MUX3 11 = MU X4

2.6.2 10-bit Video Analog-to-Digital Converter

The CX25800 has a 10-bit, on-chip Analog-to-Digital Converter (ADC) to digitize incoming video baseband signals.

The ADC is used for digitizing composite video from video sources such as cameras with analog outputs.

2.6.3 Video Signal Locking

The line length (the interval between the midpoints of the falling edges of succeeding horizontal sync pulses) of analog video sources is not constant. For a stable source such as a studio quality source, test signal generator, or DVD player, this variation is very small (±2 ns). However, for an unstable source such as a VCR, the line length variation is as much as a few microseconds.

Digital display systems require a fixed number of pixels per line despite these variations. The CX25800 uses a technique known as UltraLock to lock to the horizontal sync and subcarrier of the desired analog video signal and generate the required number of pixels per line.

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2.6.3.1 UltraLock Overview

UltraLock is based on video signal oversampling using a fixed-frequency, stable clock. Because the video line length varies, the number of samples generated using a fixedfrequency sample clock also varies from line to line. If the number of generated samples per line is always greater than the number of samples per line required by the particular video format, the number of acquired samples can be reduced to fit the required number of pixels per line.

UltraLock accommodates line length variations from nominal in the incoming video by always acquiring more samples than are required by the particular video format and outputting the correct number of pixels per line. UltraLock then interpolates the required number of pixels in a way that maintains the stability of the original image despite variation in the line length of the incoming analog waveform.

Figure 37 illustrates an example using 4 × Fsc sampling of three successive lines of

video being decoded for square-pixel NTSC output. The first line is shorter than the nominal NTSC line time interval of 63.5 μs. On this line, a line time of 63.2 μs sampled at 4 × Fsc (14.31831 MHz) generates only 905 pixels. The second line matches the nominal line time of 63.5 μs and provides the expected 910 pixels. Finally, the third line is too long at 63.8 µs within which 913 pixels are generated. In all three cases, UltraLock outputs only 780 pixels.

Figure 37. UltraLock Behavior for NTSC Square Pixel Output using 4x Fsc Sampling Rate

Analog

Wav efo rm

Line

Len gt h

Pi x el s

Per Li ne

Pi x el s

Se n t t o

t he FI FO

Ult raLock ™

63.2 ns 63.5 ns 63.8 ns

905 pixels 910 p ixels 913 p ixels

780 pixels 780 p ixels 780 p ixels

UltraLock can be used to extract any programmable number of pixels from the original video stream as long as the sum of the nominal pixel line length (910 for NTSC and 1,135 for PAL) and the worst case line length validation from nominal in the active region is greater than or equal to the required number of output pixels per line:

where: P

Nom

+ P

Var

≥

Desired

= Nominal number of pixels per line at 4 × Fsc sample rate

(910 for NTSC, 1,135 for PAL) *

Var

= Variation of pixel count from nominal at 4 × Fsc (can be a

positive or negative number)

Desired

= Desired number of output pixels per line

NOTE:

Total number of pixels includes the active video region plus blanking and front porch.

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2.6.4 Video Sample Rate Converter

2.6.4.1 Flexible Video Timing Formats

In the CX25800, the UltraLock circuit has been enhanced by a video sample rate converter. This capability is required for applications such as video editing/authoring and time shifting that require decoded video to be sent out of the CX25800 for compression and simultaneous direct connection to a digital video encoder.

In combination with UltraLock implemented in the video decoder, the sample rate converter allows a choice of video sampling rates and video decoding rates. This flexibility means that video can be captured at the highest possible sampling rate, using UltraLock, to acquire the maximum number of samples at the 10-bit ADCs).

If decoded video is required on the CX25800’s output pixel port for connection of hardware MPEG compressors, TV encoders, or hardware video deinterlacers, the sample rate converter can be enabled to provide digital video with the following attributes:

 Provides a valid video data sample with each output clock  Produces the same number of output clocks per line  Generates consistent sample point locations from line-to-line

These attributes are mandatory for interfacing to the aforementioned devices.

Figure 38 provides a top level overview of the sample rate converter and video

decoder.

Figure 38. UltraLock and Sample Rate Converter

Co m p o si t e

Vi de o

10-Bit

ADC

Co n t r o l

Mult istandard

Vi d eo Deco de r and

Sc a l e r

XTAL

Sa m p l e

Ra t e

Co n v er t e r

PLL

Y/ Co m p os it e

Figure 38 indicates that there is a clock domain for the analog to digital converters and

another domain for the multistandard video decoder and scaler. Typically, an 8x Fsc (video subcarrier frequency) crystal is used to provide a sampling clock for the video ADCs to obtain more samples per line than is required (see UltraLock Overview) for square pixel or 4:3 aspect ratio decoding.

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If no external video processing is required, the sample rate converter can be bypassed and the video decoder clocked at the same frequency as the ADCs. The decoded video samples are DMAd to the PCI bus and the graphics overlay surface in the same fashion as our previous video decoders.

If external video processing is required, the Sample Rate Conversion register should be programmed for the desired frequency of video decode. This is typically 27 MHz for ITU-R. BT656 decoding, although other formats such as square pixel NTSC (24.5454/

12.2727 MHz) or PAL (29.5/14.75 MHz) may be supported. See Table 14.

Table 14. Video Decoding Formats

Video Standard Parameter 601/656 Square Pixel

NTSC Horizontal Pixels 720 640

Vertical Lines 480 480 Clock Rate 27 MHz 24.5454 MHz

PAL Horizontal Pixels 720 768

Vertical Lines 576 576 Clock Rate 27 MHz 29.5 MHz

To use the Sample Rate Converter, the ratio between the ADC sampling frequency (typically 8x Fsc) and the desired Video decoder core frequency (typically 24.54, 27.0, or 29.5 MHz) must be derived, multiplied by 2

, and converted to binary or

hexadecimal.

Sample Rate Conversion Register Register 24’h310170

Bits Type Default Name Description

[18] RW 19’h21F07 SRC_REG_V AL 19-bit SRC programmable value. This is a ra tio of the ADC

clock rate to video clock rate. (ADC sampling frequency / Video decoder core

frequency) * 2

Some examples of ADC sampling frequency versus desired video decoder frequency and the SRC value to be programmed are illustrated in Table 15.

Table 15. Sample Rate Conversion

XTAL Frequency (MHz)

28.636363 24.545454 Square Pixel NTSC 16'h23DF3

Desired Video Decoding

Frequency (MHz)

Application SRC_REG_VAL (HEX)

28.636363 27.000000 “601/656” NTSC/PAL 16'h21F07

28.636363 28.636363 8x Fsc NTSC 16'h20000

28.636363 29.500000 Square Pixel PAL 16'h1F102

28.636363 35.440000 8x Fsc PAL 16'h19D5F

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2.6.5 Composite Video Input Formats

The CX25800 supports most video formats in use worldwide. Table 16 lists the video input formats supported by the CX25800 and some of the countries in which each format is used.

Table 16. Video Input Formats Supported by the CX25800

Format Lines Fields Fsc (MHz) Country

NTSC-M 525 60 3.58 U.S., many others NTSC-Japan PAL-B, G, H 625 50 4.43 Western/Central Europe, others PAL-D 625 50 4.43 China PAL-I 625 50 4.43 U.K., Ireland, South Africa PAL-M 525 60 3.58 Brazil PAL-NC 625 50 3.58 Argentina PAL-N 625 50 3.58 Paraguay, Uruguay

FOOTNOTES:

(1)

NTSC—Japan has 0 IRE setup.

(1)

525 60 3.58 Japan

The video decoder must be programmed appropriately for each of the composite video input formats. Table 17 lists the register values that must be programmed for each input format.

Table 17. Register Values for Square Pixel Video Input Formats

Input Format (24'h310104)

FMT[3:0] 0001 0010 0011 0100 0101 0110 0111 1000

PAL-B, D,

G, H, I

PAL-M PAL-N PAL-NC PAL-60

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2.6.6 Y/C Separation and Chroma Demodulation

2.6.6.1 The Y/C Separation Problem

Many video decoders employ a luminance notch filter, a chrominance band-pass filter, and a chrominance comb filter. The luminance signal is derived by filtering out the color information (chrominance) from a composite video signal with a notch filter. This works because the NTSC color information is in a frequency band centered at about

3.58 MHz that extends approximately. + rejects frequencies in that range. Although this effectively filters most of the chrominance signal out of the luminance signal, it also removes the higher frequency luminance signal components. This loss of bandwidth reduces the horizontal resolution of the luminance signal, and fine detail in the picture is lost. The chrominance signal is derived by band-pass filtering the composite video signal to extract the frequency band centered at 3.58 MHz that contains the color information. A chrominance comb filter removes any residual luminance (Y) signal that overlaps the chrominance (C) signal in this frequency range.

Other video decoders employ a line comb filter. These line comb filters operate by delaying the previous composite video horizontal scan line and comparing it to the current horizontal scan line. Adding the two lines together cancels the C signal and provides the Y signal. Subtracting the current line from the delayed line provides the C signal. This process creates two filters which have a frequency response that look like teeth in a comb. This type of filter is usually known as a 1-H comb filter, since it uses a 1-horizontal scan line delay to process the signals. More complex 2-H comb filters can be built using 2-horizontal scan line delays. While these filters show improvement with a multiburst test pattern compared to a notch filter and demonstrate a horizontal flat frequency response, the multiburst pattern does not show that 50 percent of the vertical resolution is lost due to the averaging of two lines. These filters still suffer the hanging dot problem noticeable on test patterns such as the SMPTE color bar test pattern.

1.3 MHz (i.e., from 2.3 to 4.9 MHz). The Y filter

2.6.6.2 Conexant Adaptive Comb Filter

To overcome this hanging dot problem and the loss of vertical resolution, a sophisticated 3-line, adaptive comb filter has been implemented in the CX25800 to separate the Y/C components in composite NTSC/PAL video signals. As stated previously, simple 1-H comb filters cannot eliminate hanging dots on a vertical color transition. Comb filtering two successive scan lines with different color values at the same horizontal positions along the lines cause the problem. The line comb filter cannot separate the Y/C signals correctly in this situation. The color signal crosses over into the luminance signal, creating a cross-luminance artifact. In a 3-line adaptive Y/C separation filter, adaptive logic continuously evaluates the video image and then selects the most efficient processing algorithm available in the filter . This is sometimes called a 2-D filter, because both the horizontal scan lines and vertical transitions are processed. This eliminates the hanging dot problem by detecting vertical transitions in the image.

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The adaptation logic examines three successive horizontal scan lines simultaneously. If a vertical transition occurs between the first and third lines, notch filtered luminance and band-pass filtered chrominance are used directly, without comb filtering. Hence, two lines with different colors are not input to the comb filter at a transition boundary. Therefore, the Y/C signals are fully separated and the hanging dots eliminated. The CX25800 accomplishes this adaptive processing on a pixel-by-pixel basis, compared to other decoders which can only comb filter on a line by line basis. Figure 39 illustrates a high-level diagram of the NTSC/PAL adaptive comb filter.

Figure 39. Y/C Separation and Chroma Demodulation Circuit for Composite NTSC/PAL Video

Composite

Video

Notch Filter

Luma Comb

Video Delay

Band-Pass Filter

Luma Switch

Adaptive Logic

and Vertical

Transition Detector

Low-Pass Filter

sin

Low-Pass Filter

cos

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2.6.7 Y/C Separation and Chroma Demodulation

The luma notch filter responses for NTSC and PAL video, using 4x Fsc decoding (Y comb filter disabled) is illustrated in Figure 40.

Figure 40. Luma Notch Filter Frequency Responses for NTSC and PAL @ 4x Fsc Decoding Frequencies

NTSC

Amplitude in dB [20*log10[ampl]]

012345678

Fr eq u en cy i n MH z

PAL

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The luma notch filter response for NTSC and PAL video using square pixel decoding (Y comb filter disabled) is illustrated in Figure 41.

Figure 41. Luma Notch Filter Frequency Responses for NTSC and PAL @ Square Pixel Decoding Frequencies

NTSC

Amplitude in dB [20*log10[ampl]]

012345678

Fr eq u en cy i n MH z

PAL

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The luma notch filter response for NTSC and PAL video using 13.5-MHz decoding (Y comb filter disabled) is illustrated in Figure 42.

Figure 42. Luma Notch Filter Frequency Responses for NTSC and PAL @ 13.5-MHz Decoding Frequency

NTSC

Amplitude in dB [20*log10[ampl]]

012345678

Fr eq u en cy i n MH z

PAL

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The chroma band-pass filter response for NTSC and P AL video using 4x Fsc decoding is illustrated in Figure 43.

Figure 43. Chroma Band Pass Filter Frequency Responses for NTSC and PAL @ 4x Fsc Decoding Frequencies

Amplitude in dB [20*log10[ampl]]

012345678

NTSC

PAL

Fr eq u en cy i n MH z

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The chroma band-pass filter response for NTSC and PAL video using square pixel decoding is illustrated in Figure 44.

Figure 44. Chroma Band Pass Filter Frequency Responses for NTSC and PAL @ Square Pixel Decoding Frequencies

Amplitude in dB [20*log10[ampl]]

01234567

NTSC

PAL

Fr eq u en cy i n MH z

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The chroma band-pass filter response for NTSC and PAL using 13.5-MHz decoding is illustrated in Figure 45.

Figure 45. Chroma Band Pass Filter Frequency Responses for NTSC and PAL @ 13.5-MHz Decoding Frequency

Amplitude in dB [20*log10[ampl]]

0123456

NTSC

PAL

Fr eq u en cy i n MH z

When the adaptive comb filter determines that luma comb decoding is required, the luminance data that is combed out of the chroma data by the band-pass/chroma-comb filter is added back to the notched luma response, thereby restoring the full horizontal luminance content and ensuring a flat frequency response in the luma channel.

When using the video decoder with composite video sources, it is important not to disable the luma notch filter (bit 13 of even and odd field registers Horizontal/Vertical Filters Control). In addition, it is important to ensure that the comb filter bits (bits 5 and 6 of register Horizontal/Vertical Filters Control) remains at the default of 00 when capture sizes of 640x480 through 768x576 are required. For capture sizes below 640x480, the comb filter bits should be set to chroma-comb only (01) because the reduced luminance information is typically below the subcarrier frequency, thus rendering luma comb decoding irrelevant. In this case, bit 27 of the Output Format and 2D Comb Control register (24’h310164) must be disabled by writing a logical 0.

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Horizontal/Vertical Filters Control Register Register 24’h31015C—Even Field Register 24’h310160—Odd Field

Bits Type Default Name Description

[13] RW 1’b0 LNOTCH 0 = Enable notch filter

1 = Disable (recommended for monochrome input— enables full luma bandwidth)

[6:5] RW 2’b00 COMB Selects comb filter.

00 = Full Comb 01 = Chroma comb only 10 = Reserved 11 = No ne

The Output Format and 2H Comb Control register (24’h310164) has additional bit fields related to comb filtering with the defaults configured for optimal quality for the majority of applications. These defaults should not require user intervention unless adaptive comb filtering is required to be switched off, such as when decoding at small capture sizes. However, for PAL video sources, if full luma and chroma Y/C separation is required at resolutions greater than 640x480, bit 26 (PAL_INV_PHASE) must be asserted and a logical 1 written.

Output Format and 2H Comb Control Register Register 24’h310164

Bits Type Default Name Description

[31:29] RO 3’h0 Reserved [28] RW 1’b1 PREVREMOD Enable previous line remodulation; must be used in

conjunction with COMBALT = 1

[27] RW 1’b1 COMBALT 3 Line/2 Line adaptive comb filter

0 = Disable 1 = Enable

[26] RW 1’b0 PAL_INV_PHASE Used in PAL 2D comb filter mode.

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Functional Block Diagram

Distinguishing Features

Audio Subsystem

Multipurpose I/O Subsystem

PCI Subsystem

Miscellaneous

Applications

Contents

Figures

Tables

Product Overview

1.1 Functional Overview

1.2 Detailed Features

1.2.1 Analog Video Capture

1.2.1.1 Overview

1.2.1.2 Input Interface

1.2.1.3 Image Scaler

1.2.1.4 Reduced Instruction Set Computer Engine

1.2.1.5 UltraLock™

1.2.1.6 Vertical Blanking Interval (VBI) Data Capture

1.2.2 Analog Audio Capture

1.2.3 ITU-R 656 4:2:2 Data Output

1.2.4 ITU-R 656/VIP 2.0 Pixel Data Input

1.2.5 MPEG Data Port

1.2.6 General Purpose Host Interface Port

1.2.7 GPIO Port

1.2.8 Serial Bus Interface

1.2.9 PCI Bus Interface

1.3 Pin Descriptions

Functional Description

2.1 Audio Input

2.1.1 Overview

2.1.2 Analog Input ADC

2.1.3 Audio PLL Initialization

2.1.4 Input Source Select

2.1.5 Audio Control and Sample Rate Converter

2.1.5.1 Audio Demodulator Sample Rate Converter

2.1.5.2 Volume

2.1.5.3 Balance

2.1.6 I2S Input and Output

2.1.6.1 I2S Input

2.1.6.2 I2S Output

2.1.7.1 Normal Mode

2.1.7.2 OSR DAC Mode

2.1.7.3 OSR ADC Mode

2.1.7.4 Passthrough Mode

2.1.7.5 Full Functionality Mode

2.1.8 Audio DACs

2.2 General Purpose Host Port

2.2.1 Introduction

2.2.2 Host Port Overview

2.2.3 General Purpose Host Port Memory Space

2.2.4 General Purpose Host Port Interface Register Access

2.2.5 General Purpose Host Interface External DMA Transfers

2.3 GPIO

2.3.1 GPIO Pin Architecture

2.3.2 GPIO Modes in CX25800

2.3.3 GPIO Normal Mode

2.3.4 MPEG Parallel Port

2.3.5 8-Bit Parallel VIP Host Master

2.3.6 4-Bit Parallel VIP Host Master

2.3.7 Video Synchronous Pixel (SPI) Mode

2.3.8 10-Bit ITU-R. BT656 Output Mode

2.3.9 8-Bit ITU-R. BT656/VIP 2.0 Pixel Input Mode

2.3.10 Host Port Chip Select Enable Mode

2.4 Peripheral Component Interface

2.4.1 PCI Functions

2.4.2 PCI Configuration Space

2.4.3 PCI Subsystem IDs

2.4.4 Accessing VPD on the CX25800

2.4.5 PCI Specification Regarding VPD Implementation

2.4.6 Using VPD Data with Multiple Functions on One Card

2.4.7 PCI Power Management

2.4.8 Memory Space

2.4.9 PCI Data Streaming

2.4.10 SRAM

2.4.11 FIFO Size Calculation

2.4.12 Programmable FIFO

2.4.13 RISC Instruction Queue