Conexant CX23880, CX23881, CX23882, CX23883 Data Sheet

CX23880/CX23881/CX23882/CX23883

PCI Audio/Video Broadcast Decoder

Data Sheet

101069A

August 2002

Ordering Information

Model Number Package Operating Te mperature

CX23880/CX23881/CX23882/CX23883 176-pin LQFP

Revision History

Revision Level Date Description

A Preliminary August 2002

Related Documents

CX23490 HD Theater MPEG2 Decoder Data Sheet
CX22702 COFDM Demodulator Data Sheet
CX24110 QPSK Demodulator Data Sheet
CX24108 Satellite Tuner Data Sheet
CX25870/871 Flicker Filter Encoder Data Sheet

Created

0 to +70

o

C

© 2002, Conexant Systems, Inc.

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ii

Preliminary Information/Conexant Proprietary and Confidential 08/26/02

Conexant 101069A

Preliminary Information

This document contains information on a new product. The parametric information, although not
fully characterized, is the result of testing initial devices.

CX23880/CX23881/CX23882/CX23883

PCI Audio/Video Broadcast Decoder

The CX23880/CX23881/CX23882/CX23883 decoders are a pin-compatible family of
highly flexible single chip solutions that enable television, radio, DTV, and broadband
data capture over the PCI bus.

The CX23880 family supports all analog broadcast video and audio formats used
worldwide today. This enables audio/video capture, video display, and audio playback on
the host PC, or storage and playback at a later time via software or hardware audio/video
codecs.

The CX23880 family is fully compatible with Conexant's family of digital channel
demodulators for capture of High and Standard Definition digital television streams and
broadband data over terrestrial, satellite, or cable links.

The CX23880 family supports a variety of third-party peripheral connectivity options via
its GPIO pins and CPU host port interface to enable board vendor-specific functionality
and market place differentiation.

CX23880 Functional Block Diagram

To

From
Video

Decompressor

656/VIP 2.0

Pixel Input

Scaler

Pixel

Engine

Audio

FIFO

DMA

FIFO

Video
FIFO

DMA

DMA

FIFO

DMA

DMA

FIFO

PCI Interface

PCI
Bus

Composite 1
Composite 2
Composite 3
Composite 4

Video

Composite

Audio

Broadcast

Stereo Right

Broadband/

Low IF

S-Video

2

S In

I

2

I

S Out

Stereo Left

Serial or

Parallel

Data

MPEG

ADAC
ADAC

10-Bit

ADC

10-Bit

ADC

Video

Decode

Audio

Decode

Data

FIFO

Video

Compressor

656 Pixel

Output

Scaler

and SRC

Format

Converter

DMA

CX23880 Distinguishing Features

Video Subsystem

! 10-bit video ADCs
! Global video standards that support

[NTSC (M,J, 4.43), PAL (B, D, G, H, I,
M, N, N-combination), SECAM (K, L)]

! Capture resolution up to 768x576

(Square Pixel PAL/SECAM)

! NTSC and PAL adaptive comb filter for

2-D Y/C luminance and chrominance
separation

! AGC video circuit
! Multiple YCrCb and RGB pixel formats

and YUV planar formats support on
output

! Selectable pixel density: 8, 16, 24, and

32 bits per pixel

! Complex clipping of video source and

VGA video overlay

! Allowance for different program control

and color space/scaling for even and
odd fields

! Support of Windows “Scatter/Gather”

DMA

! High-quality multitap horizontal and

vertical image scaler for decoded video
or 4:2:2 sources

! ITU-R BT.656 8-bit or 10-bit 4:2:2

output port for MPEG II Encoder
connection

! ITU-R BT.656/VIP 2.0 pixel input port

for MPEG II ML or HL Decoder
connection

! Flexible VBI data capture for closed

captioning, teletext, other analog
broadcast data types

! Hue, Brightness, Contrast, Saturation

control for video decoder

JTAG

Clocks

and PLL

Serial

Bus

Host PortGPIO

ViP 2.0

Host Port

—Continued on the next page—

101069A Conexant iii
08/26/02 Preliminary Information/Conexant Proprietary and Confidential

Distinguishing Features (continued)
Audio Subsystem

! Low IF sampling direct from tuner
! CX23880: Global broadcast audio

support (BTSC-dbx, NICAM728, A2,
System L, EIA-J, FM)

! CX23881: European broadcast audio

support (NICAM, A2, FM)

! Decoded 48 kHz audio stream to PCI bus

for real time encoding to MP3

! Integrated 90 dB SNR stereo audio DACs

to drive sound card or headphones

2

! I

S Input port for external source

connectivity to on-board stereo DACs

2

! I

S Output port to drive coaxial/optical

digital audio interface

! Flexible audio sample rate converter

Multipurpose I/O Subsystem

! Bidirectional 33 MBps VIP 2.0 Host port.

Compatible with the CX23490 All-Format
MPEG 2 Decoder (CX23880 only)

! Bidirectional 10 MBps Intel/Motorola-

compatible General Purpose Host port

! Unidirectional 10 MBps parallel/serial

MPEG Transport/Data Stream port.
Compatible with all Conexant digital
television channel demodulator ICs.

! MPEG Packet Synchronization
! User-defined General Purpose Input/

Output pins

Applications

! PC television
! PC theater
! Digital television
! Digital VCR
! Analog and digital video editing
! MP3 radio
! PCI cable modem
! PCI satellite modem
! Data broadcast receiver
! Media hub for home server

PCI Subsystem

! 5 independent functions each with

Target/Master and Local register space
(Video, Audio, MPEG Port, VIP 2.0 Host
Port, GP Host Port)

! All RISC/Control programs executed on-

chip

! On-chip SRAM for PCI data buffering

Up/Down

! Vital product data
! DMA byte alignment
! PCI revision 2.2-compliant

Miscellaneous

! ACPI and power-down support
! Only one crystal for all video and audio

decoding required

! 400 kHz serial bus master
! JTAG boundary scan interface
! Compact 176-pin TQFP
! Low power

iv Conexant 101069A

Preliminary Information/Conexant Proprietary and Confidential 08/26/02

Contents

Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

1.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Detailed Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.1 Analog Video Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.1.2 Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.1.3 Image Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.1.4 Reduced Instruction Set Computer Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.2.1.5 UltraLock™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.2.1.6 Vertical Blanking Interval (VBI) Data Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.2.1.7 Macrovision Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.2.2 Analog Audio Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -6

1.2.3 ITU-R 656 4:2:2 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.2.4 ITU-R 656/VIP 2.0 Pixel Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.2.5 MPEG Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.2.6 VIP 2.0 Host-Master Interface Port (CX23880). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.2.7 General Purpose Host Interface Port (CX23880/CX23882). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.2.8 GPIO Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.2.9 Serial Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.2.10 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Audio Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1.2 Analog Front End (AFE) and Chroma-ADC (C-ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.2.1 Selecting Optional Gain Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.1.3 Multistandard Audio Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.4 Selecting the Broadcast Audio Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

2.1.5 Audio PLL Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.1.6 Input Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.1.6.1 BTSC-Stereo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.1.6.2 FM Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.1.6.3 A2 and Electronic Industries Association of Japan (EIAJ) . . . . . . . . . . . . . . . . . . . . . 2-10

101069A Conexant v
08/26/02 Preliminary Information/Conexant Proprietary and Confidential

CX23880/CX23881/CX23882/CX23883 Data Sheet

2.1.6.4 NICAM Stereo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

2.1.6.5 Force/Auto Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.1.7 Dematrix Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.1.8 Audio Control and Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.1.8.1 Audio Demodulator Sample Rate Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.1.8.2 Volume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.1.8.3 Balance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.1.9 I

2.1.10 I

2

S Input and Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.1.9.1 I

2.1.9.2 I

2

S Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2

S Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2

S Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.1.10.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18

2.1.10.2 OSR DAC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.1.10.3 OSR ADC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.1.10.4 Pass-Thru Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.1.10.5 Full Functionality Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.1.11 Audio DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.1.12 Broadcast Audio Programming Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.2 General Purpose Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.2.2 Host Port Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

2.2.3 General Purpose Host Port Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

2.2.4 General Purpose Host Port Interface Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

2.2.5 General Purpose Host Interface External DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

2.2.6 General Purpose Host Interface Signaling—Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . 2-39

2.2.7 General Purpose Host Interface Signaling—Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . 2-41

2.3 General Purpose Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.3.1 GPIO Pin Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.3.2 GPIO Modes in CX2388x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

2.3.3 GPIO Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

2.3.4 MPEG Parallel Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

2.3.5 8-bit Parallel VIP Host Master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

2.3.6 4-bit Parallel VIP Host Master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

2.3.7 Video Synchronous Pixel (SPI) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

2.3.8 10-bit ITU-R. BT656 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52

2.3.9 8-bit ITU-R. BT656/VIP 2.0 Pixel Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.3.10 Host Port Chip Select Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-54

2.4 Peripheral Component Interface (PCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

2.4.1 PCI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

2.4.2 PCI Configuration Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

2.4.3 PCI Subsystem IDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

2.4.4 Accessing VPD on the CX23880. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-56

2.4.5 PCI Specification Regarding VPD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

2.4.6 Using VPD Data with Multiple Functions on One Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

2.4.7 PCI Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

2.4.8 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

vi

Preliminary Information/Conexant Proprietary and Confidential 08/26/02

Conexant 101069A

CX23880/CX23881/CX23882/CX23883 Data Sheet

2.4.9 PCI Data Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58

2.4.10 SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

2.4.11 FIFO Size Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

2.4.12 Programmable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60

2.4.13 RISC Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61

2.4.14 Channel Management Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

2.4.15 RISC Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66

2.4.16 RISC Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66

2.4.17 Data Stream Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74

2.4.18 Data Stream User’s Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74

2.4.19 PCI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77

2.5 MPEG Data Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

2.5.1 Digital Television Channel Demodulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

2.5.2 Video Compressors/Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

2.5.3 Serial vs. Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

2.6 Video Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83

2.6.1 Video Input Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83

2.6.2 10-bit Video Analog-to-Digital Converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83

2.6.3 Video Signal Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84

2.6.3.1 UltraLock Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84

2.6.4 Video Sample Rate Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86

2.6.4.1 Flexible Video Timing Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86

2.6.5 Composite Video Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-88

2.6.6 Y/C Separation and Chroma Demodulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89

2.6.6.1 The Y/C Separation Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89

2.6.6.2 Conexant Adaptive Comb Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89

2.6.7 Y/C Separation and Chroma Demodulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91

2.6.8 Video Scaling, Cropping, and Temporal Decimation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95

2.6.8.1 Down-Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-95

2.6.8.2 Vertical Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99

2.6.8.3 Chrominance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99

2.6.8.4 Video Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100

2.6.8.5 The Horizontal Scaling Ratio (HSCALE) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101

2.6.8.6 The Vertical Scaling Ratio Register (VSCALE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102

2.6.9 Image Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-103

2.6.10 Cropping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-105

2.6.10.1 Horizontal Delay Register (HDELAY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-105

2.6.10.2 Horizontal Active Register (HACTIVE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-105

2.6.10.3 The Vertical Delay Register (VDELAY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106

2.6.10.4 The Vertical Active Register (VACTIVE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106

2.6.11 Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -106

2.6.12 Video Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107

2.6.12.1 The Hue Adjust Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107

2.6.12.2 The Contrast Adjust Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107

2.6.12.3 The Saturation Adjust Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107

2.6.12.4 The Brightness Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107

2.6.12.5 Automatic Chrominance Gain Control (ACGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107

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2.6.13 Low Color Detection and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108

2.6.14 Coring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108

2.6.15 VBI Data Output Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -109

2.6.16 VBI Line Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -110

2.6.16.1 Macrovision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111

2.6.17 ITU-R656 Output Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111

2.6.18 ITU-R656/VIP 2.0 8-bit Pixel Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112

2.7 VIP 2.0 Host Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-114

2.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-114

2.7.2 VIP 2.0 Host Master Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-114

2.7.3 VIP 2.0 Host Master System Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -118

2.7.3.1 Downstream DMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-122

2.7.3.2 Upstream DMA Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-123

2.7.3.3 VIP External Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-124

2.7.3.4 VIP Local Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-124

2.7.4 VIP Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-125

2.7.5 VIP Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-125

3 Electrical Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Input Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Analog Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.2 Multiplexer Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.2.1 ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.3 Power-Up Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.4 Crystal Inputs and Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.3 Serial Bus Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.3.1 EEPROM Upload at PCI Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.3.2 Register load from BIOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.3.3 Programming and Write-Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10

3.3.4 Page-Mode limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -10

3.4 Vital Product Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.4.1 Required VPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.4.2 VPD Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.4.3 VPD Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.4.4 VPD Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.4.5 VPD Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.5 Power Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.5.1 PME# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.5.2 D3 Power States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.6 JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.6.1 Need for Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.6.2 JTAG Approach to Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.6.3 Optional Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.6.4 Verification with the TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

viii

Conexant 101069A

Preliminary Information/Conexant Proprietary and Confidential 08/26/02

CX23880/CX23881/CX23882/CX23883 Data Sheet

4 PC Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.2 Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

5 Applications Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Broadcast TV/Audio/FM Radio Capture Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Digital Video Recorder Capture Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.3 ATSC HDTV Hardware Decode Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.4 DVB DTV Software Decode Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.5 IEEE 1394 DV Editing and Broadcast TV/Audio/FM Radio Capture Card . . . . . . . . . . . . . . . . . . . . . . . 5-1

6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1 PCI Configuration Registers: Function 0: Video. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 PCI Configuration Registers: Function 1: Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.3 PCI Configuration Registers: Function 2: MPEG TS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

6.4 PCI Configuration Registers: Function 3: VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

6.5 PCI Configuration Registers: Function 4: Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36

6.6 Memory Mapped Registers: Miscellaneous Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46

6.7 Memory Mapped Registers: Function 0: Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59

6.8 Memory Mapped Registers: Function 1: Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89

6.9 Memory Mapped Registers: Function 2: MPEG TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97

6.10 Memory Mapped Registers: Function 3: VIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103

6.11 Memory Mapped Registers: Function 4: Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-110

7 Electrical and Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1 DC Electrical Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.3 Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

A Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

101069A Conexant ix
08/26/02 Preliminary Information/Conexant Proprietary and Confidential

CX23880/CX23881/CX23882/CX23883 Data Sheet

x

Preliminary Information/Conexant Proprietary and Confidential 08/26/02

Conexant 101069A

Figures

Figure 1-1. CX2 3880 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-2. CX2 3880 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Figure 2-1. Simplified Block Diagram of CX2388x Audio Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2. Normal Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Figure 2-3. OSR DAC Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Figure 2-4. OSR ADC Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Figure 2-5. Pass-Thru Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

Figure 2-6. Full Functionality Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Figure 2-7. Host Interface Write Operation—Intel Style (Accessing an External Device) . . . . . . . . . . 2-39

Figure 2-8. Host Interface Write Operation—Motorola Style (Accessing an External Device) . . . . . . 2-39

Figure 2-9. Host Interface Read Operation—Intel Style (Accessing an External Device) . . . . . . . . . . 2-40

Figure 2-10. Host Interface Read Operation—Motorola Style (Accessing an External Device) . . . . . . . 2-40

Figure 2-11. Host Interface Read Operation—Intel Style Multiplexed Address/Data Bus

Figure 2-12. Host Interface Read Operation—Motorola Style Multiplexed Address/Data Bus

Figure 2-13. Host Interface Write Operation—Intel Style Multiplexed Address/Data Bus

Figure 2-14. Host Interface Write Operation—Motorola Style Multiplexed Address/Data Bus

Figure 2-15. GPIO Pin Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Figure 2-16. MPEG Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

Figure 2-17. 8-bit Parallel VIP Host Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

Figure 2-18. Video Synchronous Pixel (SPI) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

Figure 2-19. 10-bit ITU-R. BT656 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52

Figure 2-20. 8-bit ITU-R. BT656/VIP 2.0 Pixel Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Figure 2-21. Host Port Chip Select Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Figure 2-22. SRAM Resource Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

Figure 2-23. Channel Management Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64

Figure 2-24. SYNC downstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67

Figure 2-25. WRITE downstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67

Figure 2-26. WRITEC downstream RISC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68

Figure 2-27. READ upstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68

Figure 2-28. READC upstream RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68

Figure 2-29. SKIP RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

Figure 2-30. Jump RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

(Accessing an External Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

(Accessing an External Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

(Accessing an External Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

(Accessing an External Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

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Figure 2-31. WRITERM RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

Figure 2-32. WRITECM RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

Figure 2-33. WRITECR RISC Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

Figure 2-34. MPEG Port Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79

Figure 2-35. MPEG Port Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79

Figure 2-36. MPEG Port Parallel Mode Operation: Nonpunctured Clock, Default 188 Bytes/Pkt . . . . . . 2-80

Figure 2-37. MPEG Port Parallel Mode Operation: Punctured Clock, Default 188 Bytes/Pkt . . . . . . . . . 2-80

Figure 2-38. MPEG Port Serial Mode Operation: Nonpunctured Clock . . . . . . . . . . . . . . . . . . . . . . . . . 2-81

Figure 2-39. MPEG Port Parallel Mode Operation: Internally Gated Punctured Clock . . . . . . . . . . . . . . 2-81

Figure 2-40. MPEG Port Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

Figure 2-41. UltraLock Behavior for NTSC Square Pixel Output using 4x Fsc sampling rate . . . . . . . . 2-85

Figure 2-42. Ultra Lock and Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86

Figure 2-43. Y/C Separation and Chroma Demodulation Circuit for Composite NTSC/PAL Video . . . . 2-90

Figure 2-44. Luma Notch Filter Frequency Responses for NTSC and PAL/SECAM @ 4x Fsc

Decoding Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91

Figure 2-45. Luma Notch Filter Frequency Responses for NTSC and PAL/SECAM @ Square Pixel

Decoding Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91

Figure 2-46. Luma Notch Filter Frequency Responses for NTSC and PAL/SECAM @ 13.5 MHz

Decoding Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92

Figure 2-47. Chroma Band Pass Filter Frequency Responses for NTSC and PAL/SECAM @ 4x Fsc

Decoding Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92

Figure 2-48. Chroma Band Pass Filter Frequency Responses for NTSC and PAL/SECAM @

Square Pixel Decoding Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93

Figure 2-49. Chroma Band Pass Filter Frequency Responses for NTSC and PAL/SECAM @

13.5 MHz Decoding Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93

Figure 2-50. Optional Horizontal Luma Low-Pass Filter Responses for NTSC . . . . . . . . . . . . . . . . . . . 2-96

Figure 2-51. Optional Horizontal Luma Low-Pass Filter Responses for PAL/SECAM . . . . . . . . . . . . . . 2-97

Figure 2-52. Combined Luma Notch 2x Oversampling and Optional Low-Pass Filter Response

for NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-98

Figure 2-53. Combined Luma Notch 2x Oversampling and Optional Low-Pass Filter Response

for PAL/SECAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-98

Figure 2-54. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters . . . . . . . . . . 2-99

Figure 2-55. NTSC Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100

Figure 2-56. PAL/SECAM Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100

Figure 2-57. Effect of the Delay and Active Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-104

Figure 2-58. Regions of the Video Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-105

Figure 2-59. Coring Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108

Figure 2-60. Regions of the NTSC Video Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-109

Figure 2-61. Regions of the PAL Video Frame (Fields 1, 2, 5, and 6) . . . . . . . . . . . . . . . . . . . . . . . . 2-109

Figure 2-62. VBI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-110

Figure 2-63. Video ITU-R 656 Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111

Figure 2-64. MPEG 2 Decoder to CX23880/CX23882 ITU-R656 Connection, Example 1 . . . . . . . . . . 2-112

Figure 2-65. MPEG 2 Decoder to CX23880/CX23882 ITU-R656 Connection, Example 2 . . . . . . . . . . 2-113

Figure 2-66. Data Transfer from VIP 2.0 Slave to Host via CX23880 . . . . . . . . . . . . . . . . . . . . . . . . . 2-122

Figure 2-67. Data Transfer from Host to VIP Slave via CX23880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-123

Figure 2-68. VIP External Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-124

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Figure 3-1. Resistor-Divider Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Figure 3-2. Fundamental Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Figure 3-3. 3rd Overtone Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Figure 3-4. The Relationship Between SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-5. Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Figure 7-1. Clock Timing Diagram (TBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

Figure 7-2. JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Figure 7-3. 176-pin TQFP Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

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Tables

Table 2-1. ADC Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Table 2-2. Supported Broadcast Audio Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Table 2-5. System L (AM Mono) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Table 2-6. EIA-J (FM/FM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-7. FM Radio (FM/AM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-8. NICAM (DQPSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table 2-9. Audio Mono and Stereo Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Table 2-10. Dematrix Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Table 2-16. CX23880/CX23882 Applications Enabled by Host Port Peripherals. . . . . . . . . . . . . . . . . . . 2-28

Table 2-18. GPHP Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

Table 2-19. GPIO Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

Table 2-22. PCI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

Table 2-23. CX23880 Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Table 2-25. Channel Management Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Table 2-26. SOL/EOL Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71

Table 2-27. WRITERM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73

Table 2-31. Video Decoding Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87

Table 7-1. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

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1

Product Overview

1.1 Functional Overview

The CX23880/CX23881/CX23882/CX23883 devices are a pin and software
compatible family of mixed-signal monolithic integrated circuits, enabling a new
platform for analog and digital broadcast video and audio in the PC. They are
implemented as a multifunction PCI bus master and fabricated in an advanced CMOS
process operating from +3.3 V I/P and 1.8 V (digital core) powe r supplies. PCI inputs
are +5 V/3.3 V tolerant.

The CX23880 family is designed to be a higher quality, more flexible, and
configurable successor to the previous generation Fusion 878A. The key differences
between the Fusion 878A and the CX2388x family are summarized in Table 1-1.

The pin and software compatible nature of the CX2338x family enables a board
vendor to build a wide variety of analog and digital TV capture products from a
common code base.

The CX23880 and CX23882 are designed to enable high-functionality broadcast­centric PC cards that require high speed I/O capability. This capability is necessary to
support simultaneous compressed and uncompressed digital video/audio data flo ws in
conjunction with hardware MPEG II/MPEG IV encoders an d decoders. The CX23382
has the same feature set as the CX23880, with the exception of BTSC stereo with dbx
audio companding and VIP Host Port.

The CX23881 and CX23883 are designed to enable entry-level analog TV and stereo
broadcast PC cards. Additionally, TV channel demodulators can be connected to
enable software-based decoding of MPEG transport streams. The CX23881 has the
same feature set as the CX23882, with the exception of BTSC stereo with dbx audio
companding.

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Product Overview CX23880/CX23881/CX23882/CX23883 Data Sheet

Table 1-1. Feature Comparison of CX2388x and Fusion 878A

Conexant PCI Decoder

Standard Features

Fusion 878A CX23881 CX23883 CX23882 CX23880

4-input CVBS ADC X X X X X
Chroma ADC (S-Video) X X X X X
NTSC/PAL/SECAM Video X X X X X
Multiple YCrCb and RGB Formats X X X X X
Notch and Comb Y/C Separation X X X X X
Serial MPEG Input Port X X X X X

S Input Port XXXXX

I

2

24-bit General Purpose I/O X X X X X
Number of DMA Channels 2 7 11 7 11
WHQL Certification X X X X X

CX2388x Family

Standard Features

Fusion 878A CX23881 CX23883 CX23882 CX23880

10-bit Video ADCs X X X X
Multi-Line 2D-Adaptive Comb Filter X X X X
High Speed Parallel MPEG Port X X X X

2

S Output Port X X X X

I
Stereo Line Out DACs X X X X
EIAJ/NICAM/A2/FM Stereo Decode X X X X

CX2388x Family

Speciality Functions

Fusion 878A CX23881 CX23883 CX23882 CX23880

BTSC with dbx Stereo Decode X X
ITU-R 656 Output Port XX
ITU-R 656 Input Port XX
Intel/Motorola Host Port (I/O) X X
VIP 2.0 Host Master Port (I/O) X

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CX23880/CX23881/CX23882/CX23883 Data Sheet Product Overview

Figure 1-1 illustrates a block diagram of the CX23880.

Figure 1-1. CX23880 Detailed Block Diagram

Digital

MPEG TS/PS/ES,

Broadband Data

Broadband,

MPEG Port

Baseband

Audio

Output

Audio/
SPDIF
Output

2

Sout I2Sin

I

Digital
Audio/

S-Video/

SPDIF

Audio

Input

i/f

A/V MUX Video MUX

Composite

Video

User

Configurable

1–24 GPI/O

Available

9 MBps

Bidirectional

General

Purpose

Host Port

JTAG

Clocks

and PLL

Serial

Bus

GPI/O

16-Bit

Intel/

Motorola

Host Port

FIFO

DMA

16-Bit Audio DAC

16-Bit Audio DAC

FIFO

DMA

PCI Bus Interface

FIFO

DMA

10-Bit

ADC

Broadcast

Audio Decoder

FM, AM
NICAM/

QPSK

Audio

Control

and

Format

Conversion

FIFO

DMA

10-Bit

AGC

ADC

NTSC/PAL/SECAM

Decoder, Adaptive

Comb Filter and

Scaler

Pixel

Engine

VIP 2.0

Host Port

Interface

FIFO

DMA

Scaler

FIFO

DMA

AGC

8-Bit or 10-Bit
CCIR 656
Output

8-Bit CCIR 656
8-Bit VIP 2.0
Pixel Port

33 MBps
Bidirectional
Interface

PCI Bus

101069_052

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Product Overview CX23880/CX23881/CX23882/CX23883 Data Sheet

1.2 Detailed Features

1.2.1 Analog Video Capture

1.2.1.1 Overview

The CX2388x integrates a 10-bit NTSC/PAL/SECAM composite and an
S-Video decoder, image resizer/scaler, Direct Memory Access (DMA) controller , and
Peripheral Component Interface (PCI) Bus master on a single device. The CX2388x
can place video data directl y into host memory for video capture appl ications and into
a target video display frame buffer for video overlay applications. As a PCI initiator,
the CX2388x can take control of the PCI bus as soon as it is available, thereby
avoid ing the need for onbo ard frame buf fers. The CX2388 x contains a pixel data First
In, First Out (FIFO) to decouple the high-speed PCI bus from the continuous video
data stream. The video data input can be scaled, color -translated, and burst-transferred
to a target location on a field basis. This allows for simultaneous preview of one field,
and capture of the other field. Alternatively, the CX2388x can capture or preview both
fields simultaneously. The fields can be interlaced into memory or sent to separate
field buffers.

1.2.1.2 Input Interface

Analog video signals are input to the CX2388x via a four-input multiplexer. The
multiplexer can select between four composite source inputs, or between three
composite and a single S-Video input source. When an S-Video source is input to the
CX2388x, the luma component is fed through the input analog multiplexer, and the
chroma component feeds directly into the C-input pin. An Automatic Gain Control
(AGC) circuit enables the CX2388x to compensate for nonstandard amplitudes in the
analog signal input.

1.2.1.3 Image Scaler

The CX2388x can reduce the video image size in both horizontal and vertical
directions independently, using arbitrarily selected scaling ratios. The X and Y
dimensions can be scaled down to one-sixteenth of the full resolution. Horizontal
scaling is implemented with a six-tap interpolation filter, while up to five-tap
interpolation is used for vertical scaling with a line store. The video image can be
arbitrarily cropped by reducing the number of active scan lines and active horizontal
pixels per line. The CX2388x supports a temporal decimation feature that reduces
video bandwidth. This is accomplished by allowing frames or fields to be dropped
from a video sequence at fixed but arbitrarily selected intervals.

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CX23880/CX23881/CX23882/CX23883 Data Sheet Product Overview

1.2.1.4 Reduced Instruction Set Computer Engine

The CX2388x enables separate destinations for the odd and even video fields, each
controlled by a pixel Reduced Instruction Set Comptuter (RISC) instruction list. This
instruction list is created by the CX2388x device dri ve r and can be run in the onboard
memory or host memory. The instructions control the transfer of pixels to target
memory locations on a byte resolution basis. Complex clipping can be accomplished
by the instruction list, blocking the generation of PCI bus cycles for pix els that are not
to be seen on the display.

The DMA channels can be programmed on a field basis to deliver the video data in
packed or planar format. In packed mode, YCrCb data is stored in a single continuous
block of memory. In planar mode, the YCrCb data is separated into three streams
which are burst to different target memory blocks. Having the video data in planar
format is useful for applications where the data compression is accomplished via
software and the CPU.

1.2.1.5 UltraLock™

The CX2388x employs a proprietary technique known as UltraLock to lock to the
incoming analog video signal. It always generates the required number of pixels per
line from an analog source in which line length can vary by as much as a few
microseconds. UltraLock’s digital locking circuitry enables the CX2388x to lock onto
video signals quickly and accura tel y, regardless of their source. Because the t echnique
is completely digital, UltraLock can recognize unstable signals caused b y VC R head
switches or any ot her de viation and adapt the locking mechanism to accommodate the
source. UltraLock uses nonlinear techniques that are difficult, if not impossible, to
implement in genlock systems. And, unlike linear techniques, it adapts the locking
mechanism automatically.

1.2.1.6 Vertical Blanking Interval (VBI) Data Capture

The CX2388x provides a flexible solution for capturing and decoding disparate VBI
data types such as closed caption data, teletext, Vertical Internal Time and Control
(VITC) codes, HTML data, or multicast data. The CX2388x can operate in a VBI
Line Output mode, in which the VBI data is only captured during selected lines. This
mode of operation enables concurrent capture of VBI lines containing ancillary data
and normal video image data. In addition, the CX2388x supports a VBI Frame Output
mode in which every line in the video frame is treated as if it were a VBI line. This
mode of operation is designed for use with still-frame capture and processing
applications where sophisticated image decoding can be performed in the software
domain.

1.2.1.7 Macrovision Detector

With the advent of powerful Central Processing Units (CPUs) that enable software­based video compression, low-cost hardware MPEG encoders, cheap and rewritable
storage media, and pervasive broadband communications, original content protection
is paramount. To this end, the CX2388x fully implements Macrovision 7.01. When an
end user attempts to connect a Digital Video Disk (DVD) player, a digital satellite/
cable decoder’s composite, or S-Video outputs to the input of a CX2388x-based PCI
card , t he Macrovision pulses, signals are detected, and a bit is set . It is up to the board
vendor to read the bit and determine what action will be taken.

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Product Overview CX23880/CX23881/CX23882/CX23883 Data Sheet

1.2.2 Analog Audio Capture

The CX2388x captures and decodes all major terrestrial broadcast audio standards.
The CX2388x digitizes and oversamples the low Intermediate Frequency (IF) signal
from a Television (TV) tuner, and extracts and decodes the broadcast audio signal.
The decoded audio is sample rate converted to a 48 kHz Pulse Code Modulation
(PCM) stereo signal to simplify processing and interfacing. This 48 kHz stream can
be routed to the built-in +85 dB Signal-to-Noise Ratio (SNR) stereo audio Digital-to­Analog Con verters (D A Cs) for connection to the PC’s sound card or headphones, to an
external digital-audio interface, or to the PCI bus and host for direct capture by a
software audio codec.

If capture of line-level stereo audio signals is required, an inexpensive audio Analog­to-Digital Conv erter (ADC) can be directl y connected to the CX2388x’s I
and controlled via the serial bus master.

2

S input port

1.2.3 ITU-R 656 4:2:2 Data Output

The CX23880/CX23882 provides a 27-MHz, 8- or 10-bit ITU-R 656 decoded video
output interface to allow connection of a third-party MPEG II encoder or other type of
video codec. This is useful when the host CPU is not powerful enough to perform
such tasks in software, or when high-quality encoding must be achieved. Please
contact Conexant Application Engineering for a list of supported third-party video
compressors.

1.2.4 ITU-R 656/VIP 2.0 Pixel Data Input

The CX23880/CX23882 provides a 27-MHz, 8-bit ITU-R 656 decoded video input
interface to allow a third-party MPEG II decoder or codec to send 4:2:2 data over the
PCI bus to a target video display frame buffer for video overlay. Alternatively, 480­line progressive scan video from the CX23490 All-Format MPEG II decoder can be
input to this port using Video Interface P ort (VIP) 2.0-compliant pixel timing at up to
54 MHz.

1.2.5 MPEG Data Port

Channel demodulators used for digital television or broadband data applications over
terrestrial, satellite, or cable networks can be directly connected to the CX2388x’s
MPEG data port to deliv er transport streams to the host for subseq uent sto rage to disk
or software decode. Either parallel, common-interface Digital Video Broadcasting
(DVB) or serial data paths from the channel demodulator can be supported at data
transfer rates of up to 80 Mbps. If the Serial Interface mode is used, the remaining
unused pins on this port can be allocated as General Purp ose Input/Output (GPIO).

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1.2.6 VIP 2.0 Host-Master Interface Port (CX23880)

The VIP 2.0 Host-Master interface allows the CX23880 to communicate with all
devices that are compliant with the VIP slave specification. This implementation of a
VIP 2.0 master is backward-compatible with all VIP 1.1-compliant slave interfaces.
The CX23880 is designed to connect to the CX23490 All-F ormat MPEG II decoder
via this interface.

The functionality of the VIP Host Master Interface is threefold. The first concept is to
stream data from a VIP slave into host memory via the PCI bus. The second concept is
to stream out data to a VIP slave that is sent over the PCI bus by the host. The third
concept is for the host to be able to access register space on connected VIP slave
devices.

1.2.7 General Purpose Host Interface Port (CX23880/CX23882)

The General Purpose Host interface allows the connection of moderate-to-relatively
slow speed third party peripherals such as infrared remote control processors, codec
host ports, smart card controllers, etc., to the CX23880/CX23882. This port allows
simultaneous connection to two peripherals gluelessly, or as many as four peripherals
with the use of external glue logi c to pro vide the addi tional chip selects. This interface
can have one upstream and one downstream DMA channel active to or from the
external peripherals at any given time. Data bursting is not supported.

1.2.8 GPIO Port

The CX2388x provides up to 24 GPIO pins. These GPIO pins are shared with the
following pins/ports groups so that the user can determine exactly which pins can be
dedicated to specific functions versus general purpose I/O functions.

1. MPEG Parallel Data Port

2. ITU–R 656 4:2:2 Data Output

3. ITU–R 656 4:2:2 Data Input

4. Extended VIP Host Port

5. Extended General Purpose Host Port

1.2.9 Serial Bus Interface

The CX2388x’s serial bus interface supports both 99.2 kHz timing transactions and

396.8 kHz, repeated start, multibyte sequential transactions. As a serial bus master,
CX23880/CX23881 can program other devices on the video card, such as a TV tuner,
as long as the device address is known. The CX2388x supports multibyte sequential
reads (more than one transaction) and multibyte write transactions (greater than three
transactions), which enable communication to devices that support auto-incremental
internal addressin g.

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Product Overview CX23880/CX23881/CX23882/CX23883 Data Sheet

1.2.10 PCI Bus Interface

The CX2388x is designed to efficiently utilize the available 132 MBps PCI bus. The
32-bit dwords are output on the PCI bus with the appropriate image data under the
control of the DMA channels. The video stream consumes bus bandwidth with
average data rates va rying from 44 MBps for full-size 768 × 576 PAL RGB32, to 4.6
MBps for NTSC CIF 320 × 240 RGB16, to 0.14 MBps for NTSC ICON 80 × 60 8-bit
mode.

The pixel instruction stream for the DMA channels consumes a minimum of

0.1 MBps. The CX2388x provides the means for mitigating the bandwidth
bottlenecks caused by slow targets and long bus access latencies that can occur in
some system configurations. To overcome these system bottlenecks, the CX2388x
gracefully degrades and recov ers from FIFO overruns to the nearest pixel in real-time.

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1.3 Pin Descriptions

Figure 1-2 displays the CX23880 Pinout diagram. Table 1-2 provides a description of

pin functions grouped by common function.

Figure 1-2. CX23880 Pinout Diagram

TSCLK

TSVAL/ERR

TSSOP

TSDAT[0]

VDDIO

V

GND

G

PIO[23]

G

PIO[22]

G

PIO[21]
PIO[20]

G
G

PIO[19]

G

PIO[18]

G

PIO[17]

G

PIO[16]

V

HAD[1]
HAD[0]

V

V

HCTL

VIRQ#

VIPCLK

INTA#

R

ST#

EQ#

R

NT#

G

VDDIO

VDD

GND

AD[31]
A

D[30]

A

D[29]
D[28]

A

D[27]

A
AD[26]

D[25]

A

D[24]

A

BE[3]#

C

I

DSEL

AD[23]

D[22]

A
A

D[21]

A

D[20]

AD[19]
A

D[18]

G

#

RSTO

174

173

172

171

_

YS

S

170

TCKT

169

MS

168

DI

T

167

SCKO

LRCKOADATOASCKIALRCKIADATI

A

A

175

176

1
2
3
4
5

DD

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

ND

44

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

2

PP

GNDAGDA

V

P

164

165

166

1

REF

_

WM

ACSO

L

P

162

163

2

REF

_

WM

P

161

ASCO

ADA

V

R

159

160

DO

_T

REFX

I

158

CR

2

AA

V

157

2

CM

V

156

2

REFP

V

155

2

REFN

V

154

CR

2

GA

BGOUT

A

V

152

153

INIFAVINC

V

151

150

GND

V

149

GASH

A

148

AASH

V

147

SUB

A

146

1

MUX

V

145

2

MUX

V

144

3

MUX

V

143

4

MUX

V

142

CR

1

GA

A

141

1

REFN

V

140

1

REFP

V

139

1

CM

V

138

CR

1

AA

V

137

GXTL

A

136

1

T

X

135

2

T

X

134

AXTL

V

133

132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89

88

SDA
S

CL
PIO[0]

G

PIO[1]

G
G

PIO[2]
PIO[3]

G

PIO[4]

G
G

PIO[5]
PIO[6]

G

PIO[7]

G
GPCLKI
VDDIO

ND

G
G

PIO[8]
PIO[9]

G

PIO[10]

G
G

PIO[11]
PIO[12]

G

PIO[13]

G

PIO[14]

G
GPIO[15]
G

PCLKO
AD[0]

H

AD[1]

H

AD[2]

H
H

AD[3]
AD[4]

H
VPP1

PGND
VDD
VDDIO

AD[5]

H

AD[6]

H
H

AD[7]

H

AD[8]
AD[9]

H

AD[10]

H
H

AD[11]
AD[12]

H
H

AD[13]

H

AD[14]
AD[15]

H

CS#

H
HRD/HDS#

#

#

#

#

#

[17]

D

A

[16]

D

A

#

[2]#

RDY

I

BE

RAME

F

C

IO

DD

V

V

DDIO

V

RDY

T

TOP

S

EVSEL

D

ERR

P

#

ERR

S

#

#

IO

AR

P

LK

ND

[14]

D

A

[13]

D

A

DD

C

V

G

DDIO

V

[1]#

[15]

D

BE

A

C

[9]

[8]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

ND

V

[12]

[11]

[10]

[0]#

D

D

D

D

D

D

D

D

D

A

A

A

A

BE

A

C

D

A

A

A

A

A

DD

D

D

D

V

G

A

A

A

#

DDIO

EXFB

ALE

RDY

HRW

V

/

H

H

H

WR

H

VDD: 1.8 V digital core supply
Vpp,Pgnd: 1.8 V PLLs supply, return
Vddio: 3.3 V digital I/O supply
Gnd: Digital core, I/O return supply
VIO: PCI 5 V diode clamp supply

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Product Overview CX23880/CX23881/CX23882/CX23883 Data Sheet

Table 1-2. Pin Descriptions Grouped by Pin Function (1 of 5)

Pin Number Pin Name Dir Type Signal Description

PCI Interface (50 Pins)

63 CLK I — Clock All PCI signals except RST# and INT A #

are sampled on the rising edge of this

33.3333 MHz clock.

22 RST# I — Reset Bus reset causes all PCI outputs to

asynchronously three-state.
23 REQ# O t/s Request Agent requests bus
24 GNT# I — Grant Agent granted bus
37 IDSEL I — Initialization Device

Select

[28–35, 38–43,

AD[31:0] I/O t/s Address/Data Address phase when FRAME# is 1st
48, 49, 60–62,
68–72, 74–81]

[36, 50, 59, 73] CBE[3:0]# I/O t/s Bus Command/

Byte Enables

Selects device during configuration read
and write transactions.

asserted, and data transfer when IRDY#
and TRDY# are both asserted.

Bus transaction-type command during
address phase, and byte enables during
entire data phase.

58 P AR I/O t/s Parity Even parity across {AD, C/BE#}, lags

address/data phase

51 FRAME# I/O s/t/s Cycle Frame Asserted to begin bus transaction.

Deasserted when transaction in final data
phase.

52 IRDY# I/O s/t/s Initiator Ready Indicates the Initiator is ready to accept

read data or has placed valid write data
on the AD.

53 TRDY# I/O s/t/s Target Ready Indicates the Target is ready to accept

write data or has presented valid data on
AD during a read.

54 DEVSEL# I/O s/t/s Device Select Indicates the driving device has decoded

the address as the target of the current
access.

55 STOP# I/O s/t/s Stop Target requesting master to stop current

transaction
56 PERR# I/O s/t/s Parity Error Report data parity error
57 SERR# O t/ s System Error Report address parity or system error
21 INTA# O t/s Interrupt A Request an interrupt

JTAG Signals (4 Pins)

169 TCK I — Test Clock Used to synchronize all JTAG test

structures. Tie low when not using
JTAG.

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Table 1-2. Pin Descriptions Grouped by Pin Function (2 of 5)

Pin Number Pin Name Dir Type Signal Description

168 TMS I r T es t Mode Select T ransitions drive JT A G st ate machine

sequence. Tie high or leave floating when

not using JTAG. A fixed sequence on this

pin initializes the JTAG tap controller.
167 TDI I r Test Data In Load input instructions and /or test vector

data for boundary scan and internal scan.

Tie high or leave floating when not using

JTAG.
158 IREFX—TDO O Test Data Ou t Output for verifying JTAG serial

operations. The output is 3-stated when

not using JTAG port.

VIP 2.0 Host Master Signals (5 or 11 Pins)

16, 17
8–15

VHAD[1:0]

GPIO[23:16]

(1)

I/O — VIP Host Address/

Data

VIP Address and Data bus, defaults to

VIP1.1 interface with 2 addr/data pins.

Can be configured as VIP 2.0 with 8 addr/

data pins (GPIO).
18 VHCTL I/O — VIP Host Control VIP System Host control
19 VIRQ# I/O od VIP Interrupt

VIP Interrupt Request (open drain)

Request

20 VIPCLK O — VIP Clock VIP master output clock. This clock is

buffered. PCI CLK = 33.3333 MHz

Transport Stream Signals (4 or 11 Pins)

4

TSDAT[0]

3 TSSOP I — Transport Stream

(2)

I — Transport Stream

Data

Start of Packet

Transport Stream Input data bus.

TSDAT[0] is used in serial mode.

Tr ansport Stream Start-of-Packet

indicator. Indicates first byte in serial or

parallel transport packet.
2 TSVAL/ERR I — Transport Stream

Transport Stream Error or Valid indicator

Error/Valid

1 TSCLK I — Transport Stream

Clock

Transport Stream input clock. All other

transport stream inputs are sampled on

the rising (falling) edge of TSCLK

Host Master Signals (22 Pins)

[91–101, 106–
110]

90 HCS# O — General Purpose

HAD[15:0] I/O — General Purpose

Host Address/Data

Bidirectional address/data access bus

External chip select

Host Chip Select

89 HRD#/

HDS#

O — General Purpose

Host Read/Data

Either the active-low read signal or the

programmable polarity data strobe signal

Strobe

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Product Overview CX23880/CX23881/CX23882/CX23883 Data Sheet

Table 1-2. Pin Descriptions Grouped by Pin Function (3 of 5)

Pin Number Pin Name Dir Type Signal Description

88 HALE# O — General Purpose

Host Address Latch

Address Latch Enable signal, used only in

multiplexed 16-bit address/data mode

Enable

87 HWR/

HRW#

O — General Purpose

Host Write/Read,

Either the active-low write signal or the

read/write bar

not Write

86 HRDY# I r General Purpose

External data transfer acknowledge signal

Host Ready

85 HEXFB I r General Purpose

Host External
Status

Handshaking signal for use in DMA mode

to indicate the status of the external

source or destination FIFO.

GPIO/Serial Bus/Reset (29 Pins)

[8–15, 112–119,
123–130]

122 GPCLKI I I General Purpose

GPIO[23:0] I/O I/O General Purpose

Input/Output

See GPIO Cross-Reference Table

Digital Video Input Reference clock

Input Clock

111 GPCLKO O O General Purpose

Digital Video Output Reference clock

Output Clock
132 SDA I/O od Serial Data Bit data or acknowledge
131 SCL I/O od Serial Clock Bit clock
170 SYS_RSTO# O t/s System Reset Out Logical PCI reset, soft reset, or power-on

reset output. This is used to reset
CX23880’s peripheral under software
control or with hard reset.

Digital Audio (6 Pins)

171 ADATI I r Audio Data In Bit Serial Input data
172 ALRCKI I r Audio Left/Right

Left/Right Framing Input clock

Clock In
173 ASCKI I r Audio Serial Clock

Bit Serial Input clock

Input
174 ADATO O r Audio Data Out Bit Serial Output data
175 ALRCKO O r Audio Left/Right

Left/Right Framing Output clock

Clock Out
176 ASCKO O r Audio Serial Clock

Bit Serial Output clock

Output

Crystal Interface Signals (4 Pins)

134 XT2 O — XT2 Crystal oscillator input pin
135 XT1 I — XT1 Crystal oscillator or clock oscillator

input pin can be connected to XT1.

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Table 1-2. Pin Descriptions Grouped by Pin Function (4 of 5)

Pin Number Pin Name Dir Type Signal Description

133 VAXTL — — PSUP_XTAL XTAL and Sample and Hold digital
136 AGXTL — — NSPU_XTAL

power/ground. Nominal VA = 3.3 V

ADC Interface (23 Pins)

[145:142] VMUX[1:4] I A Video Mux {1:4} Analog composite video inputs to the

on-chip 4:1 analog multiplexer. Unused
inputs should be tied to AGA1.

150
151

VINC

VINIFA

I A Chroma baseband

vid: Audio low IF

Analog chroma input to the C-A/D,
multiplexed with Audio IF input from the
tuner. Unused inp ut should be tied to
AGA2.

138
156

140
154

139
155

VCM1
VCM2

VREFN1
VREFN2

VREFP1
VREFP2

O A VCM_ADC{1:2} Common mode voltage referenc e

O A VREFN{1:2} Input Negative reference (1.0 V)—one

for each Y and C/Aud ADCs, cap to AGA.

O A VREFP{1:2} Input Positive reference (1.8 V)—one

for each Y and C/Aud ADCs, cap to AGA.

153 VBGOUT O A VBGOUT Voltage reference 1.21 V nominal, cap to

AGA
137, 157 VAA{1:2}CR — A VAA{1:2}CR A/D core power/ground. Nominal
141, 152 AGA{1:2}CR — A AGA{1:2}CR

VA = 3.3 V

146 ASUB — — ASUB A/D core substrate (ground)
147 VAASH — — PSUPA_SHA_ADC A/D Sample and Hold Analog power/
148 AGASH — — NSUPA_SHA_ADC

ground. Nominal VA = 3.3 V

149 VGND I A/D Virtual Ground Single-end-to-differential converter

input for common-mode noise rejection.

Connect to analog ground via 3.3 µF

series capacitor.
105, 165 VPP1/VPP2 — — VPP1, VPP2 PLL power supply. VD= 1.8 V
104, 166 PGND — — PGND PLL return supply
158 IREFX_TDO I/O A/D IREF_EXT/TDO Shared analog current ref pin JTAG TDO

pin

Audio Output DAC Signals (6 Pins)

159 VADA — — VADA DAC analog core power and ground.
164 AGDA — — AGDA

VA = 3.3 V

163 LASCO O A LASCO DAC Pulse Width Modulator (PWM), left

stereo audio output channel
160 RASCO O A RASCO DAC PWM, right stereo audio output

channel
161 PWM_REF2 O A PWM_REF2 Audio DAC reference, right
162 PWM_REF1 O A PWM_REF1 Audio DAC reference, left

101069A Conexant 1-13
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Product Overview CX23880/CX23881/CX23882/CX23883 Data Sheet

Table 1-2. Pin Descriptions Grouped by Pin Function (5 of 5)

Pin Number Pin Name Dir Type Signal Description

I/O and Core Power and Ground (23 Pins)

6, 26, 45, 65,
83, 103

7, 27, 44, 64,

VDD — — VDD Digital core power supply. Nominal

VDD = 1.8 V

GND — — GND Ground for digital core (GND)

82, 120
5, 25, 46, 66,

84, 102, 121

VDDIO — — VDDI and VDDO Digital inputs/outputs power supply.

VD = 3.3 V
47, 67 VIO — — VIO +5 V reference for 5 V-tolerant PCI input

buffers
Note(s):

(1)

VHAD[1:0] is the default for the 5-pin VIP Host Port setting.

(2)

TSDAT[0] is the default for the 4-pin serial MPEG Data Port setting. The 11-pin setting shares GPIO pins.

3. Type: r active resistive pull-up

od open-drain
t/s three-state
s/t/s sustained three-state
[x:y] Bus
{u:v} Array of signal ports—expand to number without braces.

4. All signal I/O are LVTTL compatible (3.3 V operation with 3.9 V tolerance), except for the PC I signals whic h are all 5 .5 V tolerant.

5. All inputs are Schmitt unless otherwise noted. The PCI inputs do not have hysteresis.

6. All outputs have drive capability I

= 4 mA unless otherwise noted.

OL

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