Compal LA-9642P Shark Bay UMA, G410, G510 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

UMA M/B Schematics Document

Haswell with DDRIII + Lynx Point PCH

2012-10-03

3 3

L

A-9642P

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-9641P

E

1 60Wednesday, October 03, 2012

2.0

A

Compal confidential

File Name :

B

C

D

E

1 1

Shark Bay

Intel Processor Haswell

L

LVDS Conn.

page 28

HDMI Conn.

page 30

VDS Translator

RTD2132S(Single)

page 27

FDI *2

2.7GT/s

2 2

CRT Conn.

page 29

LAN

RJ45 Conn.

page 28

3 3

Atheros AR8162/QCA8172(10/100)

page 28

PCIe Mini Card WiMax

USB20 Port 10

page 28

PCIe Mini Card WLAN

PCIe Port 0

page 28

PCIe x1

USB20 x1

Sub-borad

rPGA946

37.5mm x 37.5mm

page 5,~9

Intel

PCH

Lynx Point

FCBGA 695Balls 20mm x 20mm

Memory Bus Dual Channel

DDR3L DDR3L

DMI2 *4 5

GT/s

USB30 x2

USB20 x6

SATA Gen3

SATA

AZALIA

1600MHz 1333MHz

204pin DDRIII-SO-DIMM X2

Left USB3.0 x2

USB30 Port 0,1

page 28

Touch Screen

USB20 Port 2

HDD Conn.

SATA Port 4

page 28

ODD Conn.

SATA Port 5

Audio Codec

CONEXANT CX20757

page 28

BANK 0, 1, 2

Right USB2.0

USB20 Port 9

Card Reader

Realtek RTS5170

USB20 Port 11

page 28

page 10,11

Int. Camera

USB20 Port 3

page 28

Int. MIC Conn.

page 28

SPI ROM

2MB + 4MB

page 28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

ODD/B

LSXXXP

LED/B

LSXXXP

page 28

CR/B

LSXXXP

page 28

B

15"

14"

Power/B

USB/B

LSXXXP

page 28

4 4

EC

ENE KB9012

page 28

Thermal Sensor

C

page 28

2011/06/15 2012/07/11

Touch Pad

page 28

Compal Secret Data

Deciphered Date

Int. KBD

page 28

D

Int. Speaker Conn.

page 28

Title

Size Document Number Rev

Custom

Date: Sheet of

Audio Combo Jacks

HP & MIC

Compal Electronics, Inc.

Block Diagram

LA-9641P

page 28

2 60Wednesday, October 03, 2012

E

2 60Wednesday, October 03, 2012

2.0

A

Voltage Rails

power

State

S0

S3

S5 S4/AC

Device

Smart Battery

plane

Address

0001 011X b

+B

O

X

+5VALW

+3VALW

O

X

X X X

+1.35V

EC SM Bus2 address

Device

Thermal Sen sor F75303M

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery

on't exist

d

EC SM Bus1 address

PCH SM Bus address

Device Address

DDR DIMM0

3 3

DDR DIMM2

1001 000Xb

1001 010Xb

NV-GPU SM Bus address

Device Address

Internal thermal sensor

1001 111Xb (0x9E)

B

+5VS

+3VS

+VCC_CORE

+VGA_CORE

+1.5VS

+0.675VS

+1.05VS

O

X X

X

Address

1001_101xb

BOARD ID Table

Board ID

0 1 2 3 4 5

C

PCB Revision

0.1

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

D

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

E

ON

OFF

ON ON

ON

OFF

LOW

OFF

6 7

OO

USB Port Table

X

EHCI1

EHCI2

USB 2.0 Port

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

0 1 2 3 4 5 6 7 8

9 10 11 12 13

3 External USB Port

Touch screen

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

Left USB3.0 Left USB3.0

Camera

Right USB2.0 WLAN Card reader

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

Board ID / SKU ID Table for AD channel

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

BOM Structure Table

BTO Item BOM Structure

HDMI HDMI@

Connector ME@ 45 LEVEL 45@ 10/100 LAN

LAN LDO Mode LDO@ LAN Switch mode SWR@

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

Porject Phase

G-series

MP

G-series

PVT

G-series

DVT

G-series

EVT

Y-series

EVT

Y-series

DVT

Y-series

PVT

Y-series

MP

Cameara CMOS@ For QIWG5 (14") 14@ For QIWG6 (15") 15@ Unpop

@

SMBUS Control Table

X X

V

+3VS

X

WLAN WWAN

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2

4 4

SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012 SODIMM

X V

+3VALW

X X X

V

+3VS

A

X X X

X

X X

V

+3VS

X XX

V

+3VS

X

B

Thermal Sensor

X X X XX

V

+3VS

PCH

X

V

+3VS

X X XX X

RTD2132

X

V

+3VS

X X

Security Classification

Issued Date

V

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

LA-9641P

Date: Sheet of

Compal Electronics, Inc.

Notes List

3 60Wednesday, October 03, 2012

E

2.0

5

ZZZ1

D D

C C

B B

PCB LA9641

DMI_CRX_PTX_N0<14> DMI_CRX_PTX_N1<14> DMI_CRX_PTX_N2<14> DMI_CRX_PTX_N3<14>

DMI_CRX_PTX_P0<14> DMI_CRX_PTX_P1<14> DMI_CRX_PTX_P2<14> DMI_CRX_PTX_P3<14>

DMI_CTX_PRX_N0<14> DMI_CTX_PRX_N1<14> DMI_CTX_PRX_N2<14> DMI_CTX_PRX_N3<14>

DMI_CTX_PRX_P0<14> DMI_CTX_PRX_P1<14> DMI_CTX_PRX_P2<14> DMI_CTX_PRX_P3<14>

FDI_CSYNC<14>

FDI_INT<14>

Note: Trace width=4 mils ,Spacing=5mil Max length= 10000 mils.

4

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

D21 C21 B21 A21

D20 C20 B20 A20

D18 C17 B17 A17

D17 C18 B18 A18

H29

J29

Haswell rPGA EDS

JCPU1A

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

FDI_CSYNC DISP_INT

ME@

DMI FDI

I

NTEL_HASWELL_HASWELL

3

+VCOMP_OUT

PEG_RCOMP

Note: Trace width=12 mils ,Spacing=15mils Max length= 400 mils.

E23

PEG_RCO MP

PEG_RXN _0 PEG_RXN _1 PEG_RXN _2 PEG_RXN _3 PEG_RXN _4 PEG_RXN _5 PEG_RXN _6

PEG

PEG_RXN _7 PEG_RXN _8

PEG_RXN _9 PEG_RXN _10 PEG_RXN _11 PEG_RXN _12 PEG_RXN _13 PEG_RXN _14 PEG_RXN _15

PEG_RXP _0 PEG_RXP _1 PEG_RXP _2 PEG_RXP _3 PEG_RXP _4 PEG_RXP _5 PEG_RXP _6 PEG_RXP _7 PEG_RXP _8

PEG_RXP _9 PEG_RXP _10 PEG_RXP _11 PEG_RXP _12 PEG_RXP _13 PEG_RXP _14 PEG_RXP _15

PEG_TXN _0

PEG_TXN _1

PEG_TXN _2

PEG_TXN _3

PEG_TXN _4

PEG_TXN _5

PEG_TXN _6

PEG_TXN _7

PEG_TXN _8

PEG_TXN _9 PEG_TXN _10 PEG_TXN _11 PEG_TXN _12 PEG_TXN _13 PEG_TXN _14 PEG_TXN _15

PEG_TXP _0

PEG_TXP _1

PEG_TXP _2

PEG_TXP _3

PEG_TXP _4

PEG_TXP _5

PEG_TXP _6

PEG_TXP _7

PEG_TXP _8

PEG_TXP _9 PEG_TXP _10 PEG_TXP _11 PEG_TXP _12 PEG_TXP _13 PEG_TXP _14 PEG_TXP _15

1 OF 9

M29 K28 M31 L30 M33 L32 M35 L34 E29 D28 E31 D30 E35 D34 E33 E32 L29 L28 L31 K30 L33 K32 L35 K34 F29 E28 F31 E30 F35 E34 F33 D32 H35 H34 J33 H32 J31 G30 C33 B32 B31 A30 B29 A28 B27 A26 B25 A24 J35 G34 H33 G32 H31 H30 B33 A32 C31 B30 C29 B28 C27 B26 C25 B24

PEG_RCOMP

12

R124.9_0402_1% R124.9_0402_1%

2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

Compal Secret Data

3

Deciphered Date

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet

4 60Wednesday, October 03, 2012

1

0.1

of

5

D D

+1.05VS +VCCST

R4 0_0603_5%

4

Note:

12

@

22U_0805_6.3V6M@C33

22U_0805_6.3V6M

1

2

0 ohm Resistor should be placed cloose to CPU

C33

C34

22U_0805_6.3V6M@C34

22U_0805_6.3V6M

1

@

2

3

H_DRAMRST#

2

+1.35V

12

R42

@R42

@

1K_0402_1%

R46

R46 1K_0402_5%

1K_0402_5%

1 2

DDR3_DRAMRST# <11,12>

1

DDR3 COMPENSATION SIGNALS

+VCCIO_OUT

Haswell rPGA EDS

12

R8

62_0402_5%

1 2

R9

H_PROCHOT#<32,37,38,44>

C C

H_CPUPWRGD<18>

@

C536

100P_0402_50V8J

C536 ESD reserve

R9

56_0402_5%

1

R15

R15 10K_0402_5%

10K_0402_5%

2

1 2

Note: PECI/THERMTRIP: Trace width=4 mils ,Spacing=18mil Zo=50 ohm

H_PECI<18,32>

H_PROCHOT#_RH_PROCHOT#

H_THRMTRIP#<18>

1 2

H_PM_SYNC<14>

PM_SYS_PWRGD_BUF PM_DRAM_PWR GD_R

CPU_PLTRST#<18>

CLK_CPU_DPLL#<15> CLK_CPU_DPLL<15> CLK_CPU_SSC_DPLL#<15> CLK_CPU_SSC_DPLL<15> CLK_CPU_DMI#<15> CLK_CPU_DMI<15>

R10 0_0402_5%R10 0_0402_5%

1 2

R13 0_0402_5%R13 0_0402_5%

1 2

R17 0_0402_5%R17 0_0402_5%

1 2

R19 0_0402_5%R19 0_0402_5%

1 2

R20 0_0402_5%R20 0_0402_5%

1 2

R22 0_0402_5%R22 0_0402_5%

1 2

R24 0_0402_5%R24 0_0402_5%

1 2

R25 0_0402_5%R25 0_0402_5%

CLK_CPU_SSC_DPLL_R

CLK_CPU_SSC_DPLL#_R

T31T31

1 2

0_0402_5%

place near CPU

R26 10K_0402_5%@R26 10K_0402_5%@

R27 10K_0402_5%@R27 10K_0402_5%@

R37

12

H_CATERR#

+VCCST

H_PM_SYNC_R

BUF_CPU_RST#

CLK_CPU_DPLL#_R CLK_CPU_DPLL_R CLK_CPU_SSC_DPLL#_R CLK_CPU_SSC_DPLL_R CLK_CPU_DMI#_R CLK_CPU_DMII_R

+VCCIO_OUT

JCPU1B

AP32

SKTOCC

AN32

CATERR

AR27

PECI

AK31

FC_AK31

AM30

PROCHOT

AM35

THERMTRIP

AT28

PM_SYNC

AL34

PWRGOOD

AC10

SM_DRAMPWR OK

AT26

PLTRSTIN

G28

DPLL_REF_CLKN

H28

DPLL_REF_CLKP

F27

SSC_DPLL_REF_CLKN

E27

SSC_DPLL_REF_CLKP

D26

BCLKN

E26

BCLKP

ME@

Haswell rPGA EDS

MISC

THERMAL

PWR

INTEL_HASWELL_HAS WELL

DDR3

CLOCK

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

SM_DRAMRST

JTAG

BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7

2 OF 9

PRDY PREQ

TCK TMS

TRST

TDO DBR

AP3

SM_RCOMP0

AR3

SM_RCOMP1

AP2

SM_RCOMP2

AN3

H_DRAMRST#

AR29

XDP_PRDY#

AT29

XDP_PREQ#

AM34

XDP_TCLK

AN33

XDP_TMS

AM33

XDP_TRST#

AM31

XDP_TDI

TDI

AL33

XDP_TDO

AP33

XDP_DBRESET#

AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

12

@

C186

0.047U_0402_16V7K

For EMI Near Chip

TMS/TDI no require pull high on Check list

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mils

PU/PD for JTAG signals

XDP_DBRESET#

XDP_TMS XDP_TDI XDP_TDO

XDP_TCLK XDP_TRST#

1 2

R5 100_0402_1%R5 100_0402_1%

1 2

R6 75_0402_1%R6 75_0402_1%

1 2

R7 100_0402_1%R7 100_0402_1%

R11 1K_0402_5%R11 1K_0402_5%

R14 51_0402_5%@R14 51_0402_5%@ R16 51_0402_5%@R16 51_0402_5%@ R18 51_0402_5%R18 51_0402_5%

R21 51_0402_5%R21 51_0402_5% R23 51_0402_5%R23 51_0402_5%

12

12 12 12

12 12

+3VS

+1.05VS

SSC CLOCK TERMINATION, IF NOT USED, stuff R26,R27

B B

SM_DRAMPWROK with DDR Power Gating Topology

+3V_PCH +3V_PCH

Q1

@

Q1

@

2N7002H_SOT23-3

+1.35V_CPU_VDDQ

12

R30

1.8K_0402_1%

PM_SYS_PWRGD_BUF

12

R36

3.3K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

LA-9641P

1

5 60Wednesday, October 03, 2012

0.1

@

1

C35

12

DS3@

R28

100K_0402_5%

1 2

R32

DS3@ R32

SYS_PWROK<14>

PM_DRAM_PWR GD<14>

A A

DS3@

0_0402_5%

5

R29

R29 200_0402_1%

200_0402_1%

C35

0.1U_0402_16V4Z

R133

2

U1

5

1

P

B

2

A

G

74AHC1G09GW_TSSOP5

3

NODS3@

1 2

0_0402_5%

SUSP<36>

4

DS3@

4

O

12

@

R35

R35 39_0402_5%

39_0402_5%

13

D

2

G

S

5

JCPU1C

DDR_A_D[0..63]<11>

D D

C C

+VREF_CA_R +VREF_DQ_DIMMA_R +VREF_DQ_DIMMB_R

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62

DDR_A_D63 +VREF_CA_R +VREF_DQ_DIMMA_R +VREF_DQ_DIMMB_R

AR15 AT14 AM14 AN14 AT15 AR14 AN15 AM15

AJ10

AK10

AM9 AN9 AM8 AN8 AR9

AT9

AR8

AT8 AJ9

AK9

AJ6

AK6

AJ7

AK7

AF4 AF5 AF1

AF2 AG4 AG5 AG1 AG2

J1 J2

J5 H5 H2 H1

J4 H4 F2 F1 D2 D3 D1 F3 C3 B3 B5 E6 A5 D6 D5 E5 B6 A6

E12

D12

B11 A11 E11

D11

B12 A12

AM3

F16 F13

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ

ME@

JCPU1C

I

NTEL_HASWELL_HASWELL

Haswell rPGA EDS

SA_CK_N_0 SA_CK_P_0

SA_CKE_0 SA_CK_N_1 SA_CK_P_1

SA_CKE_1 SA_CK_N_2 SA_CK_P_2

SA_CKE_2 SA_CK_N_3 SA_CK_P_3

SA_CKE_3

SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3

SA_ODT_0 SA_ODT_1 SA_ODT_2 SA_ODT_3

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS

SA_CAS

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7

3 OF 9

4

RSVD

SA_WE

VSS

AC7 U4

M_CLK_DDR#0

V4

M_CLK_DDR0

AD9

DDR_CKE0_DIMMA

U3

M_CLK_DDR#1

V3

M_CLK_DDR1

AC9

DDR_CKE1_DIMMA

U2 V2 AD8 U1 V1 AC8

M7

DDR_CS0_DIMMA#

L9

DDR_CS1_DIMMA#

M9 M10 M8

M_ODT0

L7

M_ODT1

L8 L10 V5

DDR_A_BS0

U5

DDR_A_BS1

AD1

DDR_A_BS2

V10 U6

DDR_A_RAS#

U7

DDR_A_WE#

U8

DDR_A_CAS#

V8

DDR_A_MA0

AC6

DDR_A_MA1

V9

DDR_A_MA2

U9

DDR_A_MA3

AC5

DDR_A_MA4

AC4

DDR_A_MA5

AD6

DDR_A_MA6

AC3

DDR_A_MA7

AD5

DDR_A_MA8

AC2

DDR_A_MA9

V6

DDR_A_MA10

AC1

DDR_A_MA11

AD4

DDR_A_MA12

V7

DDR_A_MA13

AD3

DDR_A_MA14

AD2

DDR_A_MA15

AP15

DDR_A_DQS#0

AP8

DDR_A_DQS#1

AJ8

DDR_A_DQS#2

AF3

DDR_A_DQS#3

J3

DDR_A_DQS#4

E2

DDR_A_DQS#5

C5

DDR_A_DQS#6

C11

DDR_A_DQS#7

AP14

DDR_A_DQS0

AP9

DDR_A_DQS1

AK8

DDR_A_DQS2

AG3

DDR_A_DQS3

H3

DDR_A_DQS4

E3

DDR_A_DQS5

C6

DDR_A_DQS6

C12

DDR_A_DQS7

T12T12

M_CLK_DDR#0 <11> M_CLK_DDR0 <11> DDR_CKE0_DIMMA <11> M_CLK_DDR#1 <11> M_CLK_DDR1 <11> DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA# <11> DDR_CS1_DIMMA# <11>

M_ODT0 <11> M_ODT1 <11>

DDR_A_BS0 <11> DDR_A_BS1 <11> DDR_A_BS2 <11>

DDR_A_RAS# <11> DDR_A_WE# <11> DDR_A_CAS# <11>

DDR_A_MA[0..15] <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

3

DDR_B_D[0..63]<12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AR18 AT18 AM17 AM18 AR17 AT17 AN17 AN18 AT12 AR12 AN12 AM11 AT11 AR11 AM12 AN11

AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6

AJ4

AK4

AJ1

AJ2 AM1 AN1 AK2 AK1

L2

M2

L4

M4

L1

M1

L5 M5 G7

J8 G8 G9

J7

J9

G10

J10

A8 B8

A9 B9 D8 E8 D9 E9

E15 D15 A15 B15 E14 D14 A14 B14

JCPU1D

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

I

NTEL_HASWELL_HASWELL

ME@

2

Haswell rPGA EDS

SB_CKN0

SB_CK0

SB_CKE_0

SB_CKN1

SB_CK1

SB_CKE_1

SB_CKN2

SB_CK2

SB_CKE_2

SB_CKN3

SB_CK3

SB_CKE_3

SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS

SB_CAS

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7

4 OF 9

RSVD

SB_WE

VSS

AG8 Y4

M_CLK_DDR#2

AA4

M_CLK_DDR2

AF10

DDR_CKE2_DIMMB

Y3

M_CLK_DDR#3

AA3

M_CLK_DDR3

AG10

DDR_CKE3_DIMMB

Y2 AA2 AG9 Y1 AA1 AF9

P4

DDR_CS2_DIMMB#

R2

DDR_CS3_DIMMB#

P3 P1

R4

M_ODT2

R3

M_ODT3

R1 P2 R7

DDR_B_BS0

P8

DDR_B_BS1

AA9

DDR_B_BS2

R10 R6

DDR_B_RAS#

P6

DDR_B_WE#

P7

DDR_B_CAS#

R8

DDR_B_MA0

Y5

DDR_B_MA1

Y10

DDR_B_MA2

AA5

DDR_B_MA3

Y7

DDR_B_MA4

AA6

DDR_B_MA5

Y6

DDR_B_MA6

AA7

DDR_B_MA7

Y8

DDR_B_MA8

AA10

DDR_B_MA9

R9

DDR_B_MA10

Y9

DDR_B_MA11

AF7

DDR_B_MA12

P9

DDR_B_MA13

AA8

DDR_B_MA14

AG7

DDR_B_MA15

AP18

DDR_B_DQS#0

AP11

DDR_B_DQS#1

AP5

DDR_B_DQS#2

AJ3

DDR_B_DQS#3

L3

DDR_B_DQS#4

H9

DDR_B_DQS#5

C8

DDR_B_DQS#6

C14

DDR_B_DQS#7

AP17

DDR_B_DQS0

AP12

DDR_B_DQS1

AP6

DDR_B_DQS2

AK3

DDR_B_DQS3

M3

DDR_B_DQS4

H8

DDR_B_DQS5

C9

DDR_B_DQS6

C15

DDR_B_DQS7

T13T13

1

M_CLK_DDR#2 <12> M_CLK_DDR2 <12> DDR_CKE2_DIMMB <12> M_CLK_DDR#3 <12> M_CLK_DDR3 <12> DDR_CKE3_DIMMB <12>

DDR_CS2_DIMMB# <12> DDR_CS3_DIMMB# <12>

M_ODT2 <12> M_ODT3 <12>

DDR_B_BS0 <12> DDR_B_BS1 <12> DDR_B_BS2 <12>

DDR_B_RAS# <12> DDR_B_WE# <12> DDR_B_CAS# <12>

DDR_B_MA[0..15] <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

CPI DRIVER VREF PATH IS DEFAULT

*M3+M1:Default Recommendation

B B

A A

5

4

M1:VREF_DQ driven by a voltage Divider Network during Processor power-off state. M3:VREF_DQ driven by Processor.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

6 60Wednesday, October 03, 2012

1

0.1

5

D D

4

3

2

1

COMPENSATION PU FOR eDP

+VCOMP_OUT

EDP_COMP

Note: Trace width=20 mils ,Spacing=25mil,

EDP_AUXN EDP_AUXP

EDP_HPD

FDI_TXN_0

FDI_TXP_0

FDI_TXN_1

FDI_TXP_1

DDI

8 OF 9

Max length=100 mils.

M27

EDP_CPU_AUX#

N27

EDP_CPU_AUX

P27

EDP_HPD#

E24

EDP_COMP

R27

P35

EDP_CPU_LANE_N0

R35

EDP_CPU_LANE_P0

N34

EDP_CPU_LANE_N1

P34

EDP_CPU_LANE_P1

P33

FDI_CTX_PRX_N0

R33

FDI_CTX_PRX_P0

N32

FDI_CTX_PRX_N1

P32

FDI_CTX_PRX_P1

T14T14

HPD INVERSION FOR EDP

Haswell rPGA EDS

1 2

HDMI D2

HDMI D1

HDMI D0

C C

HDMI CLK

HDMI

HDMI_TX2-_CK<25> HDMI_TX2+_CK<25> HDMI_TX1-_CK<25> HDMI_TX1+_CK<25> HDMI_TX0-_CK<25> HDMI_TX0+_CK<25> HDMI_CLK-_CK<25> HDMI_CLK+_CK<25>

C48 0.1U_0402_10V6KHDMI@ C48 0.1U_0402_10V6KHDMI@

1 2

C41 0.1U_0402_10V6KHDMI@ C41 0.1U_0402_10V6KHDMI@

1 2

C42 0.1U_0402_10V6KHDMI@ C42 0.1U_0402_10V6KHDMI@

1 2

C43 0.1U_0402_10V6KHDMI@ C43 0.1U_0402_10V6KHDMI@

1 2

C44 0.1U_0402_10V6KHDMI@ C44 0.1U_0402_10V6KHDMI@

1 2

C45 0.1U_0402_10V6KHDMI@ C45 0.1U_0402_10V6KHDMI@

1 2

C46 0.1U_0402_10V6KHDMI@ C46 0.1U_0402_10V6KHDMI@

1 2

C47 0.1U_0402_10V6KHDMI@ C47 0.1U_0402_10V6KHDMI@

TMDS_B_DATA2#_PCH TMDS_B_DATA2_PCH TMDS_B_DATA1#_PCH TMDS_B_DATA1_PCH TMDS_B_DATA0#_PCH TMDS_B_DATA0_PCH TMDS_B_CLK#_PCH TMDS_B_CLK_PCH

Place on connector side

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HAS WELL

ME@

JCPU1H

eDP

EDP_RCOMP

EDP_DISP_UT IL

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1

12

R6024.9_0402_1% R6024.9_0402_1%

EDP_CPU_AUX# <22> EDP_CPU_AUX <22>

EDP_CPU_LANE_N0 <22>

EDP_CPU_LANE_P0 <22>

FDI_CTX_PRX_N0 <14>

FDI_CTX_PRX_P0 <14>

FDI_CTX_PRX_N1 <14>

FDI_CTX_PRX_P1 <14>

+VCCIO_OUT

10K_0402_5%

RC1

1 2

B B

R458

1 2

1K_0402_5%

TL_HPD<22>

1K_0402_5%

100K_0402_5%

12

R61

@

2

1

OUT

IN

GND

DTC124EKAT146_SC59-3

3

EDP_HPD#

Q6

HPD is a active high signal from device. The HPD processor input is a low voltage active signal.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet

1

7 60Wednesday, October 03, 2012

0.1

of

5

4

3

2

1

CFG Straps for Processor

CFG2

12

R62

R62 1K_0402_1%

1K_0402_1%

@

D D

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

Haswell rPGA EDS

AT1

RSVD_TP

AT2

RSVD_TP

AD10

RSVD

A34

RSVD_TP

A35

RSVD_TP

W29

RSVD_TP

W28

RSVD_TP

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7

G26

TESTLO_G26

W33

RSVD

AL30

RSVD

AL29

RSVD

F25

VCC

C35

RSVD_TP

B35

RSVD_TP

AL25

RSVD_TP

W30

RSVD_TP

W31

RSVD_TP

W34

TESTLO

AT20

CFG_0

AR20

CFG_1

AP20

CFG_2

AP22

CFG_3

AT22

CFG_4

AN22

CFG_5

AT25

CFG_6

AN23

CFG_7

AR24

CFG_8

AT23

CFG_9

AN20

CFG_10

AP24

CFG_11

AP26

CFG_12

AN25

CFG_13

AN26

CFG_14

AP25

CFG_15

INTEL_HASWELL_HAS WELL

ME@

H_CPU_RSVD

C C

B B

1 2

H_CPU_TESTLO

CFG_RCOMP

H_CPU_RSVD

R64 49.9_0402_1%R64 49.9_0402_1%

R309 49.9_0402_1%R309 49.9_0402_1%

R66 49.9_0402_1%R66 49.9_0402_1%

+CPU_CORE

T16T16 T17T17

T18T18

H_CPU_TESTLO

JCPU1I

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

CFG_RCOMP

CFG_16 CFG_18 CFG_17 CFG_19

RSVD

FC_G6

RSVD RSVD RSVD RSVD RSVD

RSVD

RSVD RSVD

RSVD

RSVD_TP

RSVD_TP RSVD_TP

RSVD RSVD

VSS VSS

9 OF 9

C23 B23 D24 D23

AT31

CFG_RCOMP

AR21

CFG16

AR23 AP21 AP23

AR33 G6 AM27 AM26 F5 AM2 K6

E18

U10 P10

B1

NC

A2 AR1

E21 E20

AP27 AR26

AL31 AL32

T19T19

@ R51

@

2K_0402_1%

@ R52

@

1K_0402_1%

12

R51

R52

1 2

PCH_PWROK <14,32>

Embedded Display Port Presence Strap

PCIE Port Bifurcation Straps

CFG[6:5]

*

CFG4

*

@ R67

@

1K_0402_1%

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

*

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

@

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

12

R63

R63 1K_0402_1%

1K_0402_1%

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

12

R67

R68

@R68

@

1K_0402_1%

CFG7

12

R69

@R69

@

1K_0402_1%

PEG DEFER TRAINING

CFG7

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

1: (Default) PEG Train immediately following xxRESETB de assertion

*

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-9641P

0.1

8 60Wednesday, October 03, 2012

1

8 60Wednesday, October 03, 2012

0.1

5

4

3

2

1

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC

VCC VCC

AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25

U25 U26 V25 V26

W26 W27

+CPU_CORE

Haswell rPGA EDS

JCPU1E

+CPU_CORE

AB11

AE11

AH11

W11

AL27 AK27

AL35

AN35

W32

AL16

AL13

AM28 AM29

AL28

AP35

AP34

AT35 AR35 AR32

AL26

AT34

AL22

AT33 AM21 AM25 AM22 AM20 AM24

AL19 AM23

AT32

K27 L27 T27 V27

AB2 AB5 AB8

AE2 AE5 AE8

K11 N11

N8

T11

T2 T5 T8

W2 W5 W8

N26 K26

E17

A23 F22

J27

H27

Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35

RSVD RSVD RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

RSVD VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT RSVD VCOMP_OUT RSVD RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

ME@

I

NTEL_HASWELL_HASWELL

5 OF 9

+1.35V_CPU_VDDQ Source

R87

R87 130_0402_1%

130_0402_1%

+1.35V

+1.05VS

C51

@C51

@

0.1U_0402_10V6K

1 2

C49

0.1U_0402_10V6K

1 2

@

+CPU_CORE

+VCCIO_OUT

+VCOMP_OUT

R88

150_0402_1%

10K_0402_5%

12

R89

D D

VCCSENSE

VSSSENSE

+CPU_CORE

100_0402_1%

12

100_0402_1%

12

R79

R84

VCC_SENSE

Note: 0 ohm Resistor should be placed cloose to CPU

C C

VCCSENSE<44>

VSSSENSE<10,44>

+1.35V +1.35V_CPU_VDDQ

J1

@J1

@

1 2

PAD-OPEN 4x4m

+1.05VS

R78 0_0603_5%@R78 0_0603_5%@

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

12

+VCCIO_OUT

1

2

@

C53

4.7U_0402_6.3V6M

VR_SVID_ALRT#<44> VR_SVID_CLK<44> VR_SVID_DAT<44>

Note: Place the UP resistor close to CPU

+VCCIO_OUT

Note: Place the UP resistor close to CPU

12

R81

R81 75_0402_1%

75_0402_1%

1 2

R83 43_0402_5%R83 43_0402_5%

+VCCIO_OUT

12

+1.35V_CPU_VDDQ

VCCSENSE

H_CPU_SVIDALRT#

T23T23

@

1 2

VDDQ DECOUPLING

+1.35V_CPU_VDDQ

10U_0603_6.3V6M

C54

1

B B

1

2

22U_0805_6.3V6M

1

2

10U_0603_6.3V6M

C55

C56

1

2

22U_0805_6.3V6M

C61

C60

1

2

10U_0603_6.3V6M

C57

C58

1

+

C59

C59 330U_2.5V_M

2

22U_0805_6.3V6M

C62

1

2

330U_2.5V_M

2

22U_0805_6.3V6M

C63

C64

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet of

1

9 60Wednesday, October 03, 2012

0.1

5

D D

C C

B B

AA11 AA25 AA27 AA31 AA29

AB10 AA33 AA35

AC25 AC27

AC11 AD11 AC29 AC31 AC33 AC35

AE10 AE25 AE29

AE27 AE35

AF11

AG11 AG25 AE31 AG31 AE33

AH10

AG27 AG29

AG33 AG35

AJ11

AK11 AK25 AK26 AK28 AK29 AK30 AK32

AB1

AB3

AB4 AB6 AB7 AB9

AD7 AE1

AE3

AE4 AE6 AE7 AE9

AF6 AF8

AG6 AH1

AH2

AH3

AH4 AH5 AH6 AH7 AH8 AH9

E19

A10 A13 A16 A19 A22 A25 A27 A29

A3 A31 A33

A4

A7

AJ5

4

Haswell rPGA EDS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

I

ME@

JCPU1F

NTEL_HASWELL_HA SWELL

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

6 OF 9

AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22

3

Haswell rPGA EDS

B34

VSS

B4

VSS

B7

VSS

C1

VSS

C10

VSS

C13

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C24

VSS

C26

VSS

C28

VSS

C30

VSS

C32

VSS

C34

VSS

C4

VSS

C7

VSS

D10

VSS

D13

VSS

D16

VSS

D19

VSS

D22

VSS

D25

VSS

D27

VSS

D29

VSS

D31

VSS

D33

VSS

D35

VSS

D4

VSS

D7

VSS

E1

VSS

E10

VSS

E13

VSS

E16

VSS

E4

VSS

E7

VSS

F10

VSS

F11

VSS

F12

VSS

F14

VSS

F15

VSS

F17

VSS

F18

VSS

F20

VSS

F21

VSS

F23

VSS

F24

VSS

F26

VSS

F28

VSS

F30

VSS

F32

VSS

F34

VSS

F4

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G1

VSS

G11

VSS

G2

VSS

G27

VSS

G29

VSS

G3

VSS

G31

VSS

G33

VSS

G35

VSS

G4

VSS

G5

VSS

H10

VSS

H26

VSS

H6

VSS

H7

VSS

J11

VSS

J26

VSS

J28

VSS

J30

VSS

J32

VSS

J34

VSS

J6

VSS

K1

VSS

I

NTEL_HASWELL_HA SWELL

ME@

JCPU1G

2

VSS_SENSE

RSVD

7 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33

VSSSENSE <44,9>

T15T15

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet of

1

10 60Wednesday, October 03, 2012

0.1

5

+1.35V +1.35V

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

JDIMM1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C65

C65

1

2

+3V_DIMM

0.1U_0402_10V6K

0.1U_0402_10V6K C87

C87

1

2

5

1

2

@

R141

R141 0_0402_5%

0_0402_5%

R137

R137 0_0402_5%

0_0402_5%

@

DDR_CKE0_DIMMA<6>

DDR_A_BS2<6>

M_CLK_DDR0<6> M_CLK_DDR#0<6>

DDR_A_BS0<6>

DDR_A_WE#<6> DDR_A_CAS#<6>

DDR_CS1_DIMMA#<6>

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C86

C86

1

@

2

D D

C C

B B

+3VS

1 2

+3V_DIMM

+3VALW

A A

+VREF_DQ_DIMMA

0.1U_0402_10V6K

DDR_A_D0

C66

DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U8SN-7F

ME@

VREF_CA

EVENT#

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

DM6

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

SDA

VTT2

4

DDR_A_D[0..63]<6>

DDR_A_DQS[0..7]<6>

1

2

+VREF_CA

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C68

C68

@

DDR_A_DQS#[0..7]<6>

DDR_A_MA[0..15]<6>

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

4

+0.675VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR3_DRAMRST# <12,5>

DDR_CKE1_DIMMA <6>

M_CLK_DDR1 <6> M_CLK_DDR#1 <6>

DDR_A_BS1 <6> DDR_A_RAS# <6>

DDR_CS0_DIMMA# <6> M_ODT0 <6>

M_ODT1 <6>

0.1U_0402_10V6K

0.1U_0402_10V6K C67

C67

1

2

SMB_DATA_S3 <12,16,26> SMB_CLK_S3 <12,16,26>

DQ4 DQ5

DQ6 DQ7

A15 A14

A11

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC2

SCL

G2

3

+VREF_DQ_DIMMA_R

1

C39

0.022U_0402_16V7K

2

12

+VREF_CA_R+1.35V

12

R40

1K_0402_1%

+VREF_CA

12

R44

1K_0402_1%

+VREF_CA <12>

Layout Note: Place near DIMM

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

R472_0402_5% R472_0402_5%

1

C37

0.022U_0402_16V7K

2

12

R45

24.9_0402_1%

Layout Note: Place near DIMM

C70

10U_0603_6.3V6M@C70

10U_0603_6.3V6M

C69

10U_0603_6.3V6M@C69

10U_0603_6.3V6M

1

@

2

@

C85

1U_0402_6.3V6K@C85

1U_0402_6.3V6K

C84

1U_0402_6.3V6K

C84

1U_0402_6.3V6K

1

2

Compal Secret Data

1

2

1

2

1

@

2

+0.675VS

@

C82

C83

1U_0402_6.3V6K@C83

1U_0402_6.3V6K

1

2

2011/06/15 2012/07/11

2

1 2

R48 2_0402_5%R48 2_0402_5%

R54

24.9_0402_1%

Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket

OSCAN

(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

+1.35V

C72

10U_0603_6.3V6M

C72

10U_0603_6.3V6M

C73

10U_0603_6.3V6M

C73

1

2

1

2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

10U_0603_6.3V6M

1

2

Layout Note: Place near DIMM

C71

10U_0603_6.3V6M

C71

10U_0603_6.3V6M

Deciphered Date

+1.35V

10U_0603_6.3V6M

12

R50

R50 1K_0402_1%

1K_0402_1%

12

R53

R53 1K_0402_1%

1K_0402_1%

C74

1

2

+VREF_DQ_DIMMA

C75

10U_0603_6.3V6M

C75

10U_0603_6.3V6M

1

Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket

C79

0.1U_0402_10V6K

C79

C76

10U_0603_6.3V6M

C76

10U_0603_6.3V6M

C77

0.1U_0402_10V6K

C77

0.1U_0402_10V6K

1

2

Title

Size Document Number Rev

Custom

Date: Sheet of

0.1U_0402_10V6K

C80

0.1U_0402_10V6K

C80

C78

0.1U_0402_10V6K

C78

0.1U_0402_10V6K

1

2

Compal Electronics, Inc.

0.1U_0402_10V6K

1

2

LA-7981P

1

+

2

1

2

DDRIII-SODIMM SLOT1

EVT Check

C81

@+C81

@

220U_6.3V_M

11 60Wednesday, October 03, 2012

2.0

5

3A@1.35V

3A@1.35V3A@1.35V

JDIMM2

+VREF_DQ_DIMMB

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

@

1

C88

D D

C C

B B

+3V_DIMM

A A

2

DDR_CKE2_DIMMB<6>

DDR_B_BS2<6>

M_CLK_DDR2<6> M_CLK_DDR#2<6>

DDR_B_BS0<6>

DDR_B_WE#<6> DDR_B_CAS#<6>

DDR_CS3_DIMMB#<6>

C109

0.1U_0402_10V6K

C109

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C108

C108

1

@

2

5

DDR_B_D0 DDR_B_D1

DDR_B_DM0

1

C89

DDR_B_D2 DDR_B_D3

2

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

1 2

+3VS

R93 10K_0402_5%R93 10K_0402_5%

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F M

M

4

+1.35V+1.35V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3

0.65A@0.675V

0.65A@0.675V0.65A@0.675V

DDR3_DRAMRST# <11,5>

DDR_CKE3_DIMMB <6>

M_CLK_DDR3 <6> M_CLK_DDR#3 <6>

DDR_B_BS1 <6> DDR_B_RAS# <6>

DDR_CS2_DIMMB# <6> M_ODT2 <6>

M_ODT3 <6>

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

C90

1

2

SMB_DATA_S3 <11,16,26> SMB_CLK_S3 <11,16,26>

+0.675VS

C91

@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

A15 A14

VDD4

A11

A7

VDD6

A6 A4

VDD8

A2 A0

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

G2

E@

4

3

DDR_B_D[0..63]<6>

DDR_B_DQS[0..7]<6>

DDR_B_DQS#[0..7]<6>

DDR_B_MA[0..15]<6>

Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes

Layout Note: Place near DIMM

+VREF_CA <11>

10U_0603_6.3V6M

C92

1

@

2

Layout Note: Place near DIMM

+0.675VS

@

C104

1U_0402_6.3V6K@C104

1U_0402_6.3V6K

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

C185

1

@

2

@

C106

1U_0402_6.3V6K@C106

1U_0402_6.3V6K

C105

1U_0402_6.3V6K

C105

1U_0402_6.3V6K

1

2

Compal Secret Data

C94

1

2

+VREF_DQ_DIMMB_R

R49 2_0402_5%R49 2_0402_5%

1

C40

0.022U_0402_16V7K

2

12

R59

24.9_0402_1%

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

+1.35V

10U_0603_6.3V6M

C96

C95

1

2

C107

1U_0402_6.3V6K

C107

1U_0402_6.3V6K

1

2

Deciphered Date

2

1 2

10U_0603_6.3V6M

C97

1

2

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

Layout Note: Place near DIMM

1

+1.35V

12

R56

R56 1K_0402_1%

1K_0402_1%

+VREF_DQ_DIMMB

12

R58

R58 1K_0402_1%

1K_0402_1%

0.1U_0402_10V6K

10U_0603_6.3V6M

C98

1

2

0.1U_0402_10V6K

10U_0603_6.3V6M

C100

C99

C100

1

2

Title

Size Document Number Rev

Date: Sheet of

0.1U_0402_10V6K

1

2

C102

LA-7981P

0.1U_0402_10V6K C103

C103

1

2

1

0.1U_0402_10V6K

0.1U_0402_10V6K C101

C101

1

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

2.0

12 60Wednesday, October 03, 2012

2.0

5

1K_0402_5%

1 2

33_0804_8P4R_5%

R311

200_0402_1%

R123

R123 100_0402_1%

100_0402_1%

W=20milsW

+RTCBATT+RTCVCC

R94

SM_INTRUDER#

PCH_INTVRMEN

HDA_SYNC

PCH_GPIO33

HDA_SPKR HDA_SDIN0

+RTCVCC

1U_0603_10V4Z

1 2

R98 20K_0402_5%R98 20K_0402_5%

1 2

R99 20K_0402_5%R99 20K_0402_5%

1U_0603_10V4Z

C113

C115

1

2

1

2

ME FALSH

HDA_SDOUT<32>

HDA_SDOUT

+5VS

G

RP12

18 27 36 45

12

@

12

@

HDA_BIT_CLK HDA_SYNC_R HDA_RST# HDA_SDOUT

R121

200_0402_1%

R124

100_0402_1%

R115

1M_0402_5%@

1 2

DG remove Q10 on Version 1.5

2

S

@

1 2

R118

0_0402_5%

=20mils

1

C110

C110 1U_0603_10V4Z

D D

C C

B B

1U_0603_10V4Z

2

+RTCVCC

R96 1M_0402_5%R96 1M_0402_5%

R97 330K_0402_5%R97 330K_0402_5%

INTVRMEN

(INTEGRATED SUS 1.05V VR)

*

H

：：：：

L

：：：：

(INTVRMEN should always be pull high.)

+3V_PCH

R100 1K_0402_5%R100 1K_0402_5%

+3VS

R101 1K_0402_5%@R101 1K_0402_5%@

+3VS

R102 1K_0402_5%@R102 1K_0402_5%@

HIGH= Enable ( No Reboot )

*

LOW= Disable (Default)

+3V_PCH

R105 1K_0402_5%@R105 1K_0402_5%@

*

Low = Disabled (Default) High = Enabled [Flash Descriptor Security Override]

HDA_BITCLK_AUDIO<31>

HDA_SYNC_AUDIO<31> HDA_RST_AUDIO#<31>

HDA_SDOUT_AUDIO<31>

+3V_PCH +3V_PCH+3V_PCH

12

@

200_0402_1%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

100_0402_1%

@

12

CLRP1

SHORT PADS

1 2

Integrated VRM enable

Integrated VRM disable

12

1 2

12

R119

R122

12

@

12

@

4

Note: PCH_RTCX1/PCHRTCX2 Trace length <1000 mils

1

C111

18P_0402_50V8J

2

NOGCLK@

CLRP2

SHORT PADS

CLRP2

SHORT PADS

O

PEN SAVE ME RTC REGISTER

12

SHORT CLEAR ME RTC REGISTER

PCH_SRTCRST#

PCH_RTCRST#

CLRP3

SHORT PADS

CLRP3

SHORT PADS

12

OPEN SAVE CMOS

SHORT CLEAR CMOS

+3V_PCH

Q10

Q10 LBSS138LT1G_SOT-23-3

LBSS138LT1G_SOT-23-3

13

HDA_SYNC

D

1 2

R95 10M_0402_5%

NOGCLK@

Y1

1 2

NOGCLK@

CLRP2

CLRP3

HDA_SPKR<31>

HDA_SDIN0<31>

1 2

R104 1K_0402_1%@R104 1K_0402_1%@

1 2

R106 10K_0402_5%@R106 10K_0402_5%@

PCH_RTCX1

PCH_RTCX2

32.768KHZ_12.5PF_CM31532768DZFT

1

C112

C112 18P_0402_50V8J

18P_0402_50V8J

NOGCLK@

2

PCH_RTCX1

PCH_RTCX2

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDOUT

PCH_GPIO33

PCH_GPIO13

12

PCH_JTAG_TCK

R110

51_0402_5%

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

@

1 2

R196

0_0402_5%

U4A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

D

H82LPMS-QC4C-A1_FCBGA695~D

GCLK_32K

3

LPT_PCH_M_EDS

JTAGRTC AZALIA

1 OF 11

GCLK_32K <34>

SATA

SATA_RXN_0 SATA_RXP_0

SATA_TXN_0 SATA_TXP_0

SATA_RXN_1 SATA_RXP_1

SATA_TXN_1 SATA_TXP_1

SATA_RXN_2 SATA_RXP_2

SATA_TXN_2 SATA_TXP_2

SATA_RXN_3 SATA_RXP_3

SATA_TXN_3 SATA_TXP_3

SATA_RXN4/PERN1 SATA_RXP4/PERP1

SATA_TXN4/PETN1 SATA_TXP4/PETP1

SATA_RXN5/PERN2 SATA_RXP5/PERP2

SATA_TXN5/PETN2 SATA_TXP5/PETP2

SATA_RCOMP

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_IREF

2

BC8 BE8

AW8 AY8

BC10 BE10

AV10 AW10

BB9 BD9

AY13 AW13

BC12 BE12

AR13 AT13

BD13 BB13

AV15 AW15

BC14 BE14

AP15 AR15

AY5

SATA_COMP

AP3

SATA_ACT#

AT1

HDD_DET#

AU2

BBS_BIT0_R

BD4

BA2

TP9

BB2

TP8

12

R108 10K_0402_5%R108 10K_0402_5%

HDD_DET# <18>

BBS_BIT0_R <18>

+1.5VS

HDD_DET# and BBS_BIT0_R pull high by 10P8R

SATA_DTX_C_PRX_N4

SATA_DTX_C_PRX_P4

SATA_PTX_C_DRX_N4 SATA_PTX_C_DRX_P4

SATA_DTX_C_PRX_N5 SATA_DTX_C_PRX_P5

SATA_PTX_C_DRX_N5 SATA_PTX_C_DRX_P5

+3VS

SATA_DTX_C_PRX_N4 <30>

SATA_DTX_C_PRX_P4 <30>

SATA_PTX_C_DRX_N4 <30> SATA_PTX_C_DRX_P4 <30>

SATA_DTX_C_PRX_N5 <30>

SATA_DTX_C_PRX_P5 <30>

SATA_PTX_C_DRX_N5 <30> SATA_PTX_C_DRX_P5 <30>

SATA Impedance Compensation

SATA_COMP

Note: Trace width:4mils Place the resistor to PCH <500 mils, to 1.5V <100 mils.Avoid routing next to clock pins.

1 2

1

HDD

SATA 6G

ODD

+1.5VS

R1077.5K_0402_1% R1077.5K_0402_1%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

Date: Sheet

1

of

13 60Wednesday, October 03, 2012

0.1

5

4

3

2

1

+3VS

12

R126

R125

2.2K_04 02_5%

LPT_PCH_M_EDS

U4B

D D

C C

DMI_CTX_PRX _N0<4> DMI_CTX_PRX _N1<4>

DMI_CTX_PRX _N2<4> DMI_CTX_PRX _N3<4>

DMI_CTX_PRX _P0<4> DMI_CTX_PRX _P1<4>

DMI_CTX_PRX _P2<4> DMI_CTX_PRX _P3<4>

DMI_CRX_P TX_N0<4> DMI_CRX_P TX_N1<4>

DMI_CRX_P TX_N2<4> DMI_CRX_P TX_N3<4>

DMI_CRX_P TX_P0<4> DMI_CRX_P TX_P1<4>

DMI_CRX_P TX_P2<4> DMI_CRX_P TX_P3<4>

+1.5VS

SUSACK# is only used on platform that support the Deep Sx state.

+1.5VS

R135 7.5K_ 0402_1%R135 7.5 K_0402_1%

+3VS

ACIN<32,37,3 9>

R136 0_04 02_5%DS 3@R136 0_04 02_5%DS 3@

R148 0_04 02_5%DS 3@R148 0_04 02_5%DS 3@

D1 CH751H-40 PT_SOD323-2D1 CH751H-40 PT_SOD323-2

SUSACK#<32>

PCH_PW ROK<32,8 >

PM_DRAM_P WRGD<5>

EC_RSMRST#<32>

SUSWAR N#<32>

PBTN_OUT#<32>

AEPWROK can be connect to PWROK if iAMT disable

1 2

21

DMI_CTX_PRX _N0 DMI_CTX_PRX _N1

DMI_CTX_PRX _N2 DMI_CTX_PRX _N3

DMI_CTX_PRX _P0 DMI_CTX_PRX _P1

DMI_CTX_PRX _P2 DMI_CTX_PRX _P3

DMI_CRX_P TX_N0 DMI_CRX_P TX_N1

DMI_CRX_P TX_N2 DMI_CRX_P TX_N3

DMI_CRX_P TX_P0 DMI_CRX_P TX_P1

DMI_CRX_P TX_P2 DMI_CRX_P TX_P3

12

R13810K_0 402_5% R1 3810K_0402_ 5%

DMI_RCOMP

SUSACK#_ R

SYS_RST#

SYS_PW ROK

PCH_PW ROK

PM_DRAM_P WRGD

SUSWAR N#_R

AC_PRESE NT_R

PCH_GPIO 72

RI#

U4B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESET#

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

J2

RSMRST#

J4

SUSWARN#/SUSPWRNACK/GPIO30

K1

PWRBTN#

E6

ACPRESENT/GPIO31

K7

BATLOW#/GPIO72

N4

RI#

AB10

TP21

D2

SLP_WLAN#/GPIO29

LPT_PCH_M_EDS

DMI

System Power

Management

D

H82LPMS-Q C4C-A1_FCBGA 695~D

FDI

FDI_RCOMP

DSWVRMEN

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

4 OF 11

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

TP16

TP15

TP10

FDI_CSYNC

FDI_INT

FDI_IREF

TP17

TP13

DPWROK

WAKE#

CLKRUN#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#

AJ35

FDI_CTX_PRX _N0

AL35

FDI_CTX_PRX _N1

AJ36

FDI_CTX_PRX _P0

AL36

FDI_CTX_PRX _P1

AV43

AY45

TP5

AV45

AW44

AL39

FDI_CSYNC

AL40

FDI_INT

AT45

AU42

AU44

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

1 2

FDI_RCOMP

R145 7.5K_ 0402_1%R14 5 7.5 K_0402_1%

DSWODV REN

NODS3@

1 2

PCH_DPW ROK EC_RSMRST#

PM_CLKRUN #

SUS_STAT#

SLP_A#

SLP_SUS #

H_PM_SYNC

R139 0_0402_5%

T20T20

T22T22

FDI_CTX_PRX _N0 <7>

FDI_CTX_PRX _N1 <7>

FDI_CTX_PRX _P0 <7>

FDI_CTX_PRX _P1 <7>

FDI_CSYNC <4>

FDI_INT <4 >

+1.5VS

SUSCLK <32>

PM_SLP_ S5# <32>

PM_SLP_ S4# <32>

PM_SLP_ S3# <32>

SLP_SUS # <32,36>

H_PM_SYNC <5>

PCIE_W AKE# <26,27>

PCH_DPW ROK

SLP_A# can be left NC when IAMT is not support on the platfrom

SLP_LAN# can be left NC if no use integrated LAN.

1 2

R149 0_04 02_5%DS 3@R149 0_04 02_5%DS 3@

DAC_BLU<24>

DAC_GRN<24>

DAC_RED<24>

2.2K_04 02_5%

CRT_DDC_CLK CRT_DDC_DATA

DAC_BLU

DAC_GRN

CRT_DDC_CLK<2 4>

CRT_DDC_DATA<24>

CRT_HSYNC<2 4>

CRT_VSYNC<24>

PCH_PW M<22>

DPWROK _EC <32>

BBS_BIT1

DAC_RED

1 2

R132 649 _0402_1%R132 649 _0402_1%

PCI_PIRQA #

PCI_PIRQB #

PCI_PIRQC #

PCI_PIRQD #

DGPU_HOL D_RST#

PCH_GPIO 52

DGPU_PW R_EN

BBS_BIT1

PCH_GPIO 53

T21T21

1 2

R182 10K_040 2_5%R182 10K_0 402_5%

1 2

R153 1K_04 02_5%@R153 1 K_0402_5%@

Boot BIOS Strap (GPIO51)

BBS_BIT1 Boot BIOS Location

SATA_SLPD (BBS_BIT0)

00 LPC

0 1 Reserved (NAND)

B B

U6

U6 MC74VHC1G 08DFT2G SC70 5P

MC74VHC1G 08DFT2G SC70 5P

3

VGATE<44>

PCH_PW ROK

SUSACK# and SUSWARN# can be tied together if EC does not want to involve in the handshake mechanism for the Deep Sleep state entry and exit.

A A

+3V_PCH

1

2

1 2

R169 0_04 02_5%@R1 69 0_0402_ 5%@

1 2

R173 200K_04 02_5%R173 200K_0 402_5%

R312 10K_040 2_5%R312 10K_0 402_5%

5

G

A

4

SYS_PW ROK

Y

B

P

5

+3VS

SUSACK#_ RSUSWAR N#_R

AC_PRESE NT_R

12

EC_RSMRST#

12

R157 100K_04 02_1%

100K_04 02_1%

SYS_PW ROK <5>

@R157

@

CLKRUN#: External pull up to core well is required.

+3VS

1 2

+3V_PCH

+3VALW

R172 8.2K_0402_5 %R172 8.2K_040 2_5%

12

R174 10K_0402_5%

@

4 5 3 6 2 7 1 8

RP10

10K_080 4_8P4R_5%

PM_CLKRUN #

4

SUSWAR N#_R

PCIE_W AKE# PCH_GPIO 72 RI#

+RTCVCC

12

DSWODV REN

DSWODVREN - On Die DSW VR Enable H：Enable (DEFAULT)

*

L：Disable

12

R134

R134 330K_04 02_5%

330K_04 02_5%

R143

R143 330K_04 02_5%

330K_04 02_5%

@

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1

PCH_GPIO 55

A16 swap overide Strap/Top-Block Swap Override ju mper

PCI_GNT3#

PCH_GPIO 55

0

11 SPI

GPIO51 has internal pull up.

1 2

R158 1K_04 02_5%@R158 1 K_0402_5%@

Low=A16 swap override/Top-Blo ck Swap Override en abled High=Default

1 2

R176 10K_040 2_5%R176 10K_0 402_5%

2011/06/15 2012/07/11

RP23

4 5 3 6 2 7 1 8

150_080 4_8P4R_5%

CRT_DDC_CLK

CRT_DDC_DATA

CRT_IREF

PCH_PW M

PCH_ENBK L

PCH_ENVDD

PCH_GPIO 55

PCI

*

GPIO55

*

Compal Secret Data

Deciphered Date

2

T45

U44

V45

M43

M45

N42

N44

U40

U39

N36

K36

G36

H20

L20

K17

M20

A12

B13

C12

C10

A10

AL6

+3VS

VGA_BLUE

VGA_GREEN

VGA_RED

VGA_DDC_CLK

VGA_DDC_DATA

VGA_HSYNC

VGA_VSYNC

DAC_IREF

VGA_IRTN

EDP_BKLTCTL

EDP_BKLTEN

EDP_VDDEN

PIRQA#

PIRQB#

PIRQC#

PIRQD#

GPIO50

GPIO52

GPIO54

GPIO51

GPIO53

GPIO55

+3VS

DAC_BLU DAC_GRN DAC_RED

Change PN

U4E

D

LPT_PCH_M_EDS

LVDSCRT

PCI

H82LPMS-Q C4C-A1_FCBGA 695~D

PLT_RST#<26,2 7,32>

R40

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DISPLAY

DDPD_AUXN

DDPB_AUXP

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

5 OF 11

1U_0402 _6.3V4Z

PCH_GPIO 2 DGPU_PW R_EN ODD_DA#_ R

+3VS

Title

Size Doc ument Numb er Rev

Custom

Date: S heet of

HDMICLK_NB

R39

HDMIDAT_NB

R35

R36

N40

N38

H45

K43

J42

H43

K45

J44

K40

K38

H39

G17

PCH_GPIO 2

F17

ODD_DA#_ R

L15

PCH_GPIO 4

M15

PCH_GPIO 5

AD10

PCI_PME#

PME#

Y11

PCH_PLTRST#

PLTRST#

12

1

C117

@C117

@

2

PCI_PIRQA # PCI_PIRQB # PCI_PIRQC # PCI_PIRQD #

DGPU_HOL D_RST#

RP13

6 7 8 9

10

10K_120 6_10P8R_5 %

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

LA-9641P

TMDS_B_HPD# <2 5>

R140

1 2

0_0402_ 5%

1 2

R151

0_0402_ 5%

4

Y

R156

R156 100K_04 02_5%

100K_04 02_5%

5 4 3 2 1

1

HDMICLK_NB <25>

HDMIDAT_NB <25>

@R140

@

3

1

G

A

2

B

P

U5

@U5

@

5

MC74VHC1G 08DFT2G SC70 5P

+3VS

RP1

18 27 36 45

8.2K_08 04_8P4R_5 %

12

R167 10K_0 402_5%R167 10K_040 2_5%

12

R168 10K_0 402_5%

@

+3VS

PCH_GPIO 4 PCH_GPIO 5 PCH_GPIO 52

14 6 0W ednesday, October 0 3, 2012

ODD_DA# <3 0,32>

PCH_PLTRST#

+3VS

0.1

5

D D

4

3

R177 10K_0402_5%R177 10K_0402_5 %

12

+3V_PCH

2

1

PEG_CLKREQ#_R

LPT_PCH_M_EDS

U4C

1 2

LAN

WLAN

C C

+3V_PCH

B B

CLK_PCIE_LAN#< 27>

CLK_PCIE_LAN<27>

CLKREQ_LAN#<27>

CLK_PCIE_WLAN1#<26> CLK_PCIE_WLAN1<26>

CLKREQ_WLAN#<26>

4 5 3 6 2 7 1 8

RP9

10K_0804_8P4R_5%

PCH_GPIO26 PCH_GPIO44 PCH_GPIO45 PCH_GPIO46

R185 0_0402_5%R185 0_0402_5%

1 2

R187 0_0402_5%R187 0_0402_5%

R181 10K_0402_5%R181 10K_0402_5%

+3V_PCH

1 2

R313 0_0402_5%R313 0_0402_5%

1 2

R189 0_0402_5%R189 0_0402_5%

R184 10K_0402_5%R184 10K_0402_5 %

+3VS

+3V_PCH

CLK_PCI_EC<32>

12

R195 10K_0402_5%R195 10K_0402_5%

R201 10K_0402_5%R201 10K_0402_5%

CLK_PCIE_LAN#_R

CLK_PCIE_LAN_R

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

12

1 2

R20922_040 2_5% R20922_0402_5%

R21122_040 2_5% R21122_0402_5%

PCH_GPIO20

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO45

PCH_GPIO46

CLK_PCI_LPBACK_RCLK_PCI_LPBACK

CLK_PCI_EC_R

CLK_PCI_DB_R

Y43

CLKOUT_PCIE_N_0

Y45

CLKOUT_PCIE_P_0

AB1

PCIECLKRQ0#/GPIO73

AA44

CLKOUT_PCIE_N_1

AA42

CLKOUT_PCIE_P_1

AF1

PCIECLKRQ1#/GPIO18

AB43

CLKOUT_PCIE_N_2

AB45

CLKOUT_PCIE_P_2

AF3

PCIECLKRQ2#/GPIO20/SMI#

AD43

CLKOUT_PCIE_N_3

AD45

CLKOUT_PCIE_P_3

T3

PCIECLKRQ3#/GPIO25

AF43

CLKOUT_PCIE_N_4

AF45

CLKOUT_PCIE_P_4

V3

PCIECLKRQ4#/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P_5

AA2

PCIECLKRQ5#/GPIO44

AB40

CLKOUT_PCIE_N_6

AB39

CLKOUT_PCIE_P_6

AE4

PCIECLKRQ6#/GPIO45

AJ44

CLKOUT_PCIE_N_7

AJ42

CLKOUT_PCIE_P_7

Y3

PCIECLKRQ7#/GPIO46

AH43

CLKOUT_ITPXDP

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

D

H82LPMS-QC4C-A1_FCBGA695~D

LPT_PCH_M_EDS

CLOCK SIGNAL

CLKOUT_PEG_A

CLKOUT_PEG_A_P

PEGA_CLKRQ#/GPIO47

CLKOUT_PEG_B

CLKOUT_PEG_B_P

PEGB_CLKRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_P

CLKOUT_DP

CLKOUT_DP_P

CLKOUT_DPNS

CLKOUT_DPNS_P

CLKIN_DMI

CLKIN_DMI_P

CLKIN_GND

CLKIN_GND_P

CLKIN_DOT96N

CLKIN_DOT96P

CLKIN_SATA

CLKIN_SATA_P

REFCLK14IN

CLKIN_33MHZLOOPBACK

XTAL25_IN

XTAL25_OUT

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

ICLK_IREF

TP19 TP18

DIFFCLK_BIASREF

2 OF 11

AB35

CLK_PCIE_VGA#_R

AB36

CLK_PCIE_VGA_R

AF6

PEG_CLKREQ#_R

Y39

Y38

U4

PCH_GPIO56

AF39

CLK_CPU_DMI#

AF40

CLK_CPU_DMI

AJ40

CLK_CPU_SSC_DPLL#

AJ39

CLK_CPU_SSC_DPLL

AF35

CLK_CPU_DPLL#

AF36

CLK_CPU_DPLL

AY24

CLK_BUF_DMI#

AW24

CLK_BUF_DMI

AR24

CLK_BUF_BCLK#

AT24

CLK_BUF_BCLK

H33

CLK_BUF_DOT96#

G33

CLK_BUF_DOT96

BE6

CLK_BUF_CKSSCD#

BC6

CLK_BUF_CKSSCD

F45

CLK_PCH_14M

D17

CLK_PCI_LPBACK

AM43

XTAL25_IN

AL44

XTAL25_OUT

C40

F38

F36

F39

PCH_GPIO67

AM45

ICLK_IREF

AD39 AD38

AN44

PCH_CLK_BIASREF

1 2

R179 10K_0402_5%

@

R191 10K_0402_5%R191 10K_0402_5 %

12

CLK_CPU_DMI# <5>

CLK_CPU_DMI <5>

CLK_CPU_SSC_DPLL# <5> CLK_CPU_SSC_DPLL <5>

CLK_CPU_DPLL# <5> CLK_CPU_DPLL <5>

1 2

R198

0_0402_5%

GCLK@

1 2

R213

R213 0_0402_5%

0_0402_5%

1 2

R214

7.5K_0402_1%

+3V_PCH

GCLK_PCH_25MHZ

PCH_GPIO67 <18>

+1.5VS

+1.05V_+1.5V_RUN

CLK_BUF_DMI# CLK_BUF_DMI

CLK_BUF_BCLK# CLK_BUF_BCLK

CLK_BUF_DOT96# CLK_BUF_DOT96

CLK_BUF_CKSSCD# CLK_BUF_CKSSCD

CLK_PCH_14M

R183 10K_0402_5%R183 10K_0402_5 % R192 10K_0402_5%R192 10K_0402_5 %

R193 10K_0402_5%R193 10K_0402_5 % R194 10K_0402_5%R194 10K_0402_5 %

R197 10K_0402_5%R197 10K_0402_5 % R199 10K_0402_5%R199 10K_0402_5 %

R202 10K_0402_5%R202 10K_0402_5 % R203 10K_0402_5%R203 10K_0402_5 %

R205 10K_0402_5%R205 10K_0402_5 %

12 12

12

CLOCK TERMINATION for FCIM and need close to PCH

GCLK_PCH_25MHZ <34>

XTAL25_IN

XTAL25_OUT

C118

12P_0402_50V8J

1 2

R215 1M_0402_5%R215 1M_0402_5%

3

OSC

2

OSC

NC

Y2

25MHZ_10PF_7V25000014

1

2

4

NC

1

R02

1

C119

12P_0402_50V8J

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH (3/9) DMI,FDI,PM,

LA-9641P

1

0.1

of

15 60Wednesday, October 03, 2012

Compal LA-9642P Shark Bay UMA, G410, G510 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual