Compal LA-9641P, G410, G510 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

DIS M/B Schematics Document

Haswell with DDRIII + Lynx Point PCH

MARS XT / SUN PRO

2013-04-18

3 3

LA-9641P

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-9641P

E

1 61Friday, April 19, 2013

1.0

of

A

Compal confidential

File Name :

B

C

D

E

1 1

2 2

RJ45 Conn.

3 3

Sub-borad

AMD MARS XT M2 128 bits

UN PRO M2 64 bits

/ S

VRAM 512MB/1GB/2GB MARS XT : DDR3 x 8 SUN PRO : DDR3 x 4

LVDS Conn.

page 34

HDMI Conn.

page 36

CRT Conn.

page 35

LAN

Atheros

page 39

AR8162/QCA8172(10/100)

PCIe Mini Card WLAN

PCIe Port 0

PCIe Mini Card

USB20 Port 10

page 23~32

LVD

S Translator

RTD2132R(Single)

page 38

page 28

PEG 8x

Gen2 / Gen3

page 33

PCIe x1

Ie x1

PC

USB20 x1

FDI *2

2.7GT/s

Intel

ocessor

Pr

Haswell

rPGA946

37.5mm x 37.5mm

page 5,~11

Intel PCH

Lynx Point

FCBGA 695Balls 20mm x 20mm

Me

mory Bus

Dual Channel

DDR3L DDR3L

DMI2 *4 5GT

/s

USB30 x2

USB20 x6

SATA Gen3

SATA

AZALIA

1600MHz 1333MHz

204pin DDRIII-SO-DIMM X2

Left USB3.0 x2

USB30 Port 0,1

page 46

Touch Screen

USB20 Port 2

HDD Conn.

SATA Port 4

page 41

ODD Conn.

SATA Port 5

Audio Codec

CONEXANT CX20757

page 41

page 42

BANK 0, 1, 2

Right USB2.0

USB20 Port 9

Card Reader

Realtek RTS5170

USB20 Port 11

page 46

page 44

page 12,13

Int. Camera

USB20 Port 3

page 33

Shark Bay

Int. MIC Conn.

page 42

SPI ROM

2MB + 4MB

page 17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

ODD/B

LSXXXP

LED/B

LSXXXP

page 44

CR/B

LSXXXP

page 44

B

15"

14"

Power/B

USB/B

LSXXXP

page 44

4 4

EC

ENE KB9012

page 44

Thermal Sensor

C

page 40

2011/06/15 2012/07/11

Touch Pad

page 44

Compal Secret Data

Deciphered Date

Int. KBD

page 44

D

Int. Speaker Conn.

page 42

Title

Size Document Number Rev

Custom

Date: Sheet of

Audio Combo Jacks

HP & MIC

Compal Electronics, Inc.

Block Diagram

LA-9641P

page 42

2 61Friday, April 19, 2013

E

2 61Friday, April 19, 2013

1.0

A

Voltage Rails

power

State

plane

+B

+5VALW

+3VALW

+1.35V

1 1

B

BOARD ID Table

Board ID

+5VS

+3VS

+VCC_CORE

+VGA_CORE

+1.5VS

+0.675VS

+1.05VS

0 1 2 3 4 5 6 7

C

PCB Revision

0.1

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

Vcc 3.3V +/- 5%

Board ID

0 1 2 3

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5%

D

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

OFF

E

ON ON

ON

OFF

Board ID / SKU ID Table for AD channel

AD_BID

0 V

V typ

AD_BID

V

AD_BID

0 V 0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

0.503 V

0.819 V

0.538 V

0.875 V

max

Porject Phase

G-series

LOW

OFF

MP PVT DVT EVT

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

X

EC SM Bus1 address

Device

Smart Battery

0001 011X b

PCH SM Bus address

Device Address

3 3

DDR DIMM1 ChannelA

DDR DIMM2 ChannelB

0xA0

0xA4

O

X

O

X X

X

X X X

EC SM Bus2 address

Device

Thermal Sen sor

AMD-GPU SM Bus address

Device Address

Internal thermal sensor

Address

1001_100xb

1000_001xb

OO

USB Port Table

X

EHCI1

EHCI2

USB 2.0 Port

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

0 1 2 3 4 5 6 7 8

9 10 11 12 13

3 External USB Port

Left USB3.0 Left USB3.0

Touch screen

Camera

Right USB2.0 WLAN Card reader

BOM Structure Table

BTO Item BOM Structure

DIS PX@ MARS XT SUN PRO HDMI HDMI@ Deep S3 NO Deep S3 NODS3@ 8162 LAN 8172 LAN LAN LDO MODE LAN SWR MODE LAN Surge GAS@ USB30 Cameara CMOS@ LAN Switch mode SWR@ Touch screen TS@ Righ side USB RUSB@

MARS@ SUN@

DS3@

8162@ 8172@ LDO@ SWR@

USB30@

Zero ODD circuit R_USB@ZODD@

Device Address

RTD2132R

1101 010Xb

Share ROM SROM@ Non-share ROM NOSROM@ 14" 14@

15" 15@

45 LEVEL 45@

SMBUS Control Table

X

X X

V

+3VS

SODIMM

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2

4 4

SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012

X V X X X

V

+3VS

A

+3VALW

X X X

X X

V

+3VS

X

WLAN WWAN

X XX

V

+3VS

X

B

Thermal Sensor

X X X XX

V

+3VS

PCH

X

V

+3VS

X X XX X

RTD2132

X

V

+3VS

X X

Security Classification

Issued Date

V

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

D

X76 LEVEL X76@

Unpop

@

AUDIO PART MIC@

Connector ME@

VRAM BOM STRUCTURE Refer P4. VGA NOTE

Compal Electronics, Inc.

Title

Size Document Number Rev

B

LA-9641P

Date: Sheet of

Compal Electronics, Inc.

Notes List

E

3 61Friday, April 19, 2013

1.0

5

4

3

2

1

Mars XT VRAM STRAP

Vendor

UV5, UV6, UV7, UV8 UV9, UV10, UV11, UV12

Samsung 2048Mbits

ZZZ4

SA000068U00 128Mx16 K4W2G1646E-BC1A

D D

2GBytes

1GBytes

2GBytes

C C

MS2G@

ZZZ5 MM2G@

ZZZ6 MH2G@

ZZZ7 MS1G@

ZZZ8 MH1G@

ZZZ15 MH2GN@

ZZZ4

Samsung_2G

MS2G@

MS2G@ X7646738L01

X7646738L01

Micron 2048Mbits SA000067500 128Mx16 MT41J128M16JT-093G:K

Hynix 2048Mbits SA000065300 H5TQ2G63DFR-N0C

Samsung 1028Mbits SA00004GS00 64Mx16 K4W1G1646G-BC11

Hynix 1024Mbits SA

000041SB0

64Mx16 H5TQ1G63EFR-11C

ynix 2048Mbits

H SA

00006H400

128Mx16 H5TC2G63FFR-11C

2GBytes 1GBytes

ZZZ6

ZZZ5

Micron_2G

MM2G@

MM2G@ X7646738L02

X7646738L02

ZZZ6

Hynix_2G

MH2G@

X7646738L09

0 0

0 1 1

ZZZ15

Hynix_2G

MH2GN@

X7646738L10

PS_3[ 1 ]PS_3[ 2 ]PS_3[ 3 ]

0

10 0

00 1

1 1 4.75K NC1

01 0 4.99K4.53K

ZZZ7

Samsung_1G

MS1G@

MS1G@ X7646738L03

X7646738L03

X76@X76@

R_pu R_pd

RV20 RV27

NC 4.75K

8.45K 2K

4.53K 2K

6.98K 4.99K

ZZZ8

Hynix_1G

MH1G@

MH1G@ X7646738L04

X7646738L04

Power-Up/Down Sequence

"Mars" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms

‧

of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/µs.

The external pull ups on the DDC/AUX signals (if applicable) should ramp up

‧

before or after both VDDC and VDD_CT have ramped up.

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC

‧

should reach 90% before VDD_CT starts to ramp up (or vice versa).

For power down, reversing the ramp-up sequence is recommended.

‧

VDDR3(3.3VGS)

PCIE_VDDC(0.95VGSV)

VDDR1(1.5VGS)

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

PERSTb

REFCLK

Sun PRO VRAM STRAP

Vendor

UV9, UV10, UV11, UV12

Samsung 4096Mbits

ZZZ9

SA000068R00 256Mx16 K4W4G1646B-HC11

SS2G@

B B

2GBytes

1GBytes

Micron 4096Mbits

ZZZ10

SA000065D00 256Mx16/1866 MT41K256M16HA-107G:E

SM2G@

Hynix 4096Mbits

ZZZ11

SA00006DG00 256MX16 H5TQ4G63MFR-11C

SH2G@

Samsung 2048Mbits

ZZZ12

SA000068U00 128Mx16 K4W2G1646E-BC1A

SS1G@

ZZZ13 SM1G@

ZZZ14 SH1G@

ZZZ16 SH1GN@

icron 2048Mbits

M SA000067500 128Mx16 MT41J128M16JT-093G:K

Hynix 2048Mbits SA000065300 H5TQ2G63DFR-N0C

Hynix 2048Mbits SA

00006H400

H5TC2G63FFR-11C

0 0

0 1 1

1

1 0 0 4.53K 4.99K

PS_3[ 1 ]PS_3[ 2 ]PS_3[ 3 ]

1 0

1 11

0

10 0

00 1

R_pu R_pd

RV20 RV27

NC 4.75K

8.45K 2K

4.53K 2K

6.98K 4.99K

3.4K 10K

4.75K NC

X76@X76@

Straps Reset

Straps Valid

Global ASIC Reset

T4+16clock

A A

ZZZ9

Samsung_2G

SS2G@

SS2G@ X7646738L05

X7646738L05

2GBytes 1GBytes

ZZZ10

Micron_2G

SM2G@

SM2G@ X7646738L06

X7646738L06

ZZZ11

Hynix_2G

SH2G@

SH2G@ X7646738L11

X7646738L11

5

ZZZ12

Samsung_1G

SS1G@

SS1G@ X7646738L07

X7646738L07

ZZZ13

Micron_1G

SM1G@

SM1G@ X7646738L08

X7646738L08

4

ZZZ14

Hynix_1G

SH1G@

SH1G@ X7647538L01

X7647538L01

ZZZ16

Hynix_1G

SH1GN@

SH1GN@ X7646738L13

X7646738L13

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

VGA Notes List

LA-9641P

4 61Friday, April 19, 2013

1

1.0

5

ZZZ2

15@ZZZ2

ZZZ1

14@ZZZ1

14@

14" PCB LA9641

DA6000WQ000

D D

C C

B B

FDI_CSYNC<15>

FDI_INT<15>

Note: Trace width=4 mils ,Spacing=5mil Max length= 10000 mils.

15@

15" PCB LA9641

DA6000WQ100

DMI_CRX_PTX_N0<15> DMI_CRX_PTX_N1<15> DMI_CRX_PTX_N2<15> DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15> DMI_CRX_PTX_P1<15> DMI_CRX_PTX_P2<15> DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15> DMI_CTX_PRX_N1<15> DMI_CTX_PRX_N2<15> DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15> DMI_CTX_PRX_P1<15> DMI_CTX_PRX_P2<15> DMI_CTX_PRX_P3<15>

4

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

D21 C21 B21 A21

D20 C20 B20 A20

D18 C17 B17 A17

D17 C18 B18 A18

H29

J29

Haswell rPGA EDS

JCPU1A

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

FDI_CSYNC DISP_INT

INT

EL_HASWELL_HASWELL

ME@

3

+VCOMP_OUT

PEG_RCOMP

Note: Trace width=12 mils ,Spacing=15mils Max length= 400 mils.

E23

PEG_RCO MP

PEG_RXN _0 PEG_RXN _1 PEG_RXN _2 PEG_RXN _3 PEG_RXN _4 PEG_RXN _5 PEG_RXN _6

PEG

PEG_RXN _7

DMI FDI

PEG_RXN _8

PEG_RXN _9 PEG_RXN _10 PEG_RXN _11 PEG_RXN _12 PEG_RXN _13 PEG_RXN _14 PEG_RXN _15

PEG_RXP _0 PEG_RXP _1 PEG_RXP _2 PEG_RXP _3 PEG_RXP _4 PEG_RXP _5 PEG_RXP _6 PEG_RXP _7 PEG_RXP _8

PEG_RXP _9 PEG_RXP _10 PEG_RXP _11 PEG_RXP _12 PEG_RXP _13 PEG_RXP _14 PEG_RXP _15

PEG_TXN _0

PEG_TXN _1

PEG_TXN _2

PEG_TXN _3

PEG_TXN _4

PEG_TXN _5

PEG_TXN _6

PEG_TXN _7

PEG_TXN _8

PEG_TXN _9 PEG_TXN _10 PEG_TXN _11 PEG_TXN _12 PEG_TXN _13 PEG_TXN _14 PEG_TXN _15

PEG_TXP _0

PEG_TXP _1

PEG_TXP _2

PEG_TXP _3

PEG_TXP _4

PEG_TXP _5

PEG_TXP _6

PEG_TXP _7

PEG_TXP _8

PEG_TXP _9 PEG_TXP _10 PEG_TXP _11 PEG_TXP _12 PEG_TXP _13 PEG_TXP _14 PEG_TXP _15

1 OF 9

PEG_RCOMP

M29 K28 M31 L30 M33 L32 M35 L34 E29

PCIE_CRX_GTX_N7

D28

PCIE_CRX_GTX_N6

E31

PCIE_CRX_GTX_N5

D30

PCIE_CRX_GTX_N4

E35

PCIE_CRX_GTX_N3

D34

PCIE_CRX_GTX_N2

E33

PCIE_CRX_GTX_N1

E32

PCIE_CRX_GTX_N0

L29 L28 L31 K30 L33 K32 L35 K34 F29

PCIE_CRX_GTX_P7

E28

PCIE_CRX_GTX_P6

F31

PCIE_CRX_GTX_P5

E30

PCIE_CRX_GTX_P4

F35

PCIE_CRX_GTX_P3

E34

PCIE_CRX_GTX_P2

F33

PCIE_CRX_GTX_P1

D32

PCIE_CRX_GTX_P0

H35 H34 J33 H32 J31 G30 C33 B32 B31

PCIE_CTX_GRX_C_N7

A30

PCIE_CTX_GRX_C_N6

B29

PCIE_CTX_GRX_C_N5

A28

PCIE_CTX_GRX_C_N4

B27

PCIE_CTX_GRX_C_N3

A26

PCIE_CTX_GRX_C_N2

B25

PCIE_CTX_GRX_C_N1

A24

PCIE_CTX_GRX_C_N0

J35 G34 H33 G32 H31 H30 B33 A32 C31

PCIE_CTX_GRX_C_P7

B30

PCIE_CTX_GRX_C_P6

C29

PCIE_CTX_GRX_C_P5

B28

PCIE_CTX_GRX_C_P4

C27

PCIE_CTX_GRX_C_P3

B26

PCIE_CTX_GRX_C_P2

C25

PCIE_CTX_GRX_C_P1

B24

PCIE_CTX_GRX_C_P0

12

C9 0.22U_0402_10V6KPX@C9 0.22U_0402_10V6KPX@ C10 0.22U_0402_10V6KPX@C10 0.22U_0402_10V6KPX@ C11 0.22U_0402_10V6KPX@C11 0.22U_0402_10V6KPX@ C12 0.22U_0402_10V6KPX@C12 0.22U_0402_10V6KPX@ C13 0.22U_0402_10V6KPX@C13 0.22U_0402_10V6KPX@ C14 0.22U_0402_10V6KPX@C14 0.22U_0402_10V6KPX@ C15 0.22U_0402_10V6KPX@C15 0.22U_0402_10V6KPX@ C16 0.22U_0402_10V6KPX@C16 0.22U_0402_10V6KPX@

C25 0.22U_0402_10V6KPX@C25 0.22U_0402_10V6KPX@ C26 0.22U_0402_10V6KPX@C26 0.22U_0402_10V6KPX@ C27 0.22U_0402_10V6KPX@C27 0.22U_0402_10V6KPX@ C28 0.22U_0402_10V6KPX@C28 0.22U_0402_10V6KPX@ C29 0.22U_0402_10V6KPX@C29 0.22U_0402_10V6KPX@ C30 0.22U_0402_10V6KPX@C30 0.22U_0402_10V6KPX@ C31 0.22U_0402_10V6KPX@C31 0.22U_0402_10V6KPX@ C32 0.22U_0402_10V6KPX@C32 0.22U_0402_10V6KPX@

R124.9_0402_1% R124.9_0402_1%

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

PCIE_CRX_GTX_N[0..7] <23>

PCIE_CRX_GTX_P[0..7] <23>

2

PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0

1

PCIE_CTX_GRX_N[0..7] <23>

PCIE_CTX_GRX_P[0..7] <23>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

Compal Secret Data

3

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet of

5 61Friday, April 19, 2013

1

1.0

5

D D

4

3

H_DRAMRST#

2

R46

R46 1K_0402_5%

1K_0402_5%

1 2

DDR3_DRAMRST# <12,13>

1

+VCCIO_OUT

Haswell rPGA EDS

12

R8

62_0402_5%

1 2

R9

H_PROCHOT#<43,48,49,56>

C C

H_CPUPWRGD<19>

C536

22P_0402_50V8J

C536 ESD reserve

R9

56_0402_5%

1

R15

R15 10K_0402_5%

10K_0402_5%

2

1 2

Note: PECI/THERMTRIP: Trace width=4 mils ,Spacing=18mil Zo=50 ohm

H_PECI<19,43>

H_PROCHOT#_RH_PROCHOT#

H_THRMTRIP#<19>

H_PM_SYNC<15>

PM_SYS_PWRGD_BUF

CPU_PLTRST#<19>

CLK_CPU_DPLL#<16> CLK_CPU_DPLL<16> CLK_CPU_SSC_DPLL#<16> CLK_CPU_SSC_DPLL<16> CLK_CPU_DMI#<16> CLK_CPU_DMI<16>

CLK_CPU_SSC_DPLL

CLK_CPU_SSC_DPLL#

T31T31

1 2

R10 0_0402_5%R10 0_0402_5%

1 2

R37 0_0402_5%R37 0_0402_5%

R26 10K_0402_5%@R26 10K_0402_5%@

R27 10K_0402_5%@R27 10K_0402_5%@

H_CATERR#

+VCCST

H_PM_SYNC_R

BUF_CPU_RST#

+VCCIO_OUT

12

JCPU1B

AP32

SKTOCC

AN32

CATERR

AR27

PECI

AK31

FC_AK31

AM30

PROCHOT

AM35

THERMTRIP

AT28

PM_SYNC

AL34

PWRGOOD

AC10

SM_DRAMPWR OK

AT26

PLTRSTIN

G28

DPLL_REF_CLKN

H28

DPLL_REF_CLKP

F27

SSC_DPLL_REF_CLKN

E27

SSC_DPLL_REF_CLKP

D26

BCLKN

E26

BCLKP

ME@

Haswell rPGA EDS

MISC

THERMAL

PWR

INTEL_HASWELL_HAS WELL

DDR3

CLOCK

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

SM_DRAMRST

JTAG

BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7

2 OF 9

PRDY PREQ

TCK TMS

TRST

TDO DBR

AP3

SM_RCOMP0

AR3

SM_RCOMP1

AP2

SM_RCOMP2

AN3

H_DRAMRST#

AR29

XDP_PRDY#

AT29

XDP_PREQ#

AM34

XDP_TCLK

AN33

XDP_TMS

AM33

XDP_TRST#

AM31

XDP_TDI

TDI

AL33

XDP_TDO

AP33

XDP_DBRESET#

AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

1

C186

C186 47P_0402_50V8J

47P_0402_50V8J

2

For EMI Near Chip

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mils

PU/PD for JTAG signals

XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TCLK

SSC CLOCK TERMINATION, IF NOT USED, stuff R26,R27

B B

1 2

R5 100_0402_1%R5 100_0402_1%

1 2

R6 75_0402_1%R6 75_0402_1%

1 2

R7 100_0402_1%R7 100_0402_1%

R11 1K_0402_5%R11 1K_0402_5%

12

51_0804_8P4R_5%

45 36 27 18

RP19

+3VS

+1.05VS

SM_DRAMPWROK with DDR Power Gating Topology

+3V_PCH +3V_PCH

DDR3 COMPENSATION SIGNALS

Q1

@

Q1

@

2N7002H_SOT23-3

+1.35V_CPU_VDDQ

12

R30

1.8K_0402_1%

PM_SYS_PWRGD_BUF

12

R36

3.3K_0402_1%

@

1

C35

12

@

R28

100K_0402_5%

1 2

R32

@ R32

SYS_PWROK<15,43>

PM_DRAM_PWR GD<15>

A A

@

0_0402_5%

R29

R29 200_0402_1%

200_0402_1%

C35

0.1U_0402_16V7K

2

1

B

2

A

1 2

R133 0_0402_5%@R133 0_0402_5%@

SUSP<47>

U1

5

@

P

4

O

G

74AHC1G09GW_TSSOP5

3

12

@

R35

R35 39_0402_5%

39_0402_5%

13

D

2

G

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet of

1

6 61Friday, April 19, 2013

1.0

5

JCPU1C

DDR_A_D[0..63]<12>

D D

C C

+VREF_CA_R +VREF_DQ_DIMMA_R +VREF_DQ_DIMMB_R

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62

DDR_A_D63 +VREF_CA_R +VREF_DQ_DIMMA_R +VREF_DQ_DIMMB_R

AR15 AT14 AM14 AN14 AT15 AR14 AN15 AM15

AK10

AM9 AN9 AM8 AN8 AR9

AR8

AJ10

AG4 AG5 AG1 AG2

AM3

AT9

AT8 AJ9 AK9 AJ6 AK6

AJ7 AK7 AF4 AF5 AF1 AF2

J1 J2

J5 H5 H2 H1

J4 H4 F2 F1 D2 D3 D1 F3 C3 B3 B5 E6 A5 D6 D5 E5 B6 A6

E12 D12 B11 A11 E11 D11 B12 A12

F16 F13

JCPU1C

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ

EL_HASWELL_HASWELL

INT

ME@

Haswell rPGA EDS

SA_CK_N_0 SA_CK_P_0

SA_CKE_0 SA_CK_N_1 SA_CK_P_1

SA_CKE_1 SA_CK_N_2 SA_CK_P_2

SA_CKE_2 SA_CK_N_3 SA_CK_P_3

SA_CKE_3

SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3

SA_ODT_0 SA_ODT_1 SA_ODT_2 SA_ODT_3

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS

SA_CAS

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7

3 OF 9

4

RSVD

SA_WE

VSS

AC7 U4

M_CLK_DDR#0

V4

M_CLK_DDR0

AD9

DDR_CKE0_DIMMA

U3

M_CLK_DDR#1

V3

M_CLK_DDR1

AC9

DDR_CKE1_DIMMA

U2 V2 AD8 U1 V1 AC8

M7

DDR_CS0_DIMMA#

L9

DDR_CS1_DIMMA#

M9 M10 M8

M_ODT0

L7

M_ODT1

L8 L10 V5

DDR_A_BS0

U5

DDR_A_BS1

AD1

DDR_A_BS2

V10 U6

DDR_A_RAS#

U7

DDR_A_WE#

U8

DDR_A_CAS#

V8

DDR_A_MA0

AC6

DDR_A_MA1

V9

DDR_A_MA2

U9

DDR_A_MA3

AC5

DDR_A_MA4

AC4

DDR_A_MA5

AD6

DDR_A_MA6

AC3

DDR_A_MA7

AD5

DDR_A_MA8

AC2

DDR_A_MA9

V6

DDR_A_MA10

AC1

DDR_A_MA11

AD4

DDR_A_MA12

V7

DDR_A_MA13

AD3

DDR_A_MA14

AD2

DDR_A_MA15

AP15

DDR_A_DQS#0

AP8

DDR_A_DQS#1

AJ8

DDR_A_DQS#2

AF3

DDR_A_DQS#3

J3

DDR_A_DQS#4

E2

DDR_A_DQS#5

C5

DDR_A_DQS#6

C11

DDR_A_DQS#7

AP14

DDR_A_DQS0

AP9

DDR_A_DQS1

AK8

DDR_A_DQS2

AG3

DDR_A_DQS3

H3

DDR_A_DQS4

E3

DDR_A_DQS5

C6

DDR_A_DQS6

C12

DDR_A_DQS7

T12T12

M_CLK_DDR#0 <12> M_CLK_DDR0 <12> DDR_CKE0_DIMMA <12> M_CLK_DDR#1 <12> M_CLK_DDR1 <12> DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12>

M_ODT0 <12> M_ODT1 <12>

DDR_A_BS0 <12> DDR_A_BS1 <12> DDR_A_BS2 <12>

DDR_A_RAS# <12> DDR_A_WE# <12> DDR_A_CAS# <12>

DDR_A_MA[0..15] <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

3

DDR_B_D[0..63]<13>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AR18 AT18 AM17 AM18 AR17 AT17 AN17 AN18 AT12 AR12 AN12 AM11 AT11 AR11 AM12 AN11

AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6

AJ4

AK4

AJ1

AJ2 AM1 AN1 AK2 AK1

L2

M2

L4

M4

L1

M1

L5 M5 G7

J8 G8 G9

J7

J9

G10

J10

A8 B8

A9 B9 D8 E8 D9 E9

E15 D15 A15 B15 E14 D14 A14 B14

JCPU1D

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

EL_HASWELL_HASWELL

INT

ME@

2

Haswell rPGA EDS

SB_CKN0

SB_CK0

SB_CKE_0

SB_CKN1

SB_CK1

SB_CKE_1

SB_CKN2

SB_CK2

SB_CKE_2

SB_CKN3

SB_CK3

SB_CKE_3

SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS

SB_CAS

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7

4 OF 9

RSVD

SB_WE

VSS

AG8 Y4

M_CLK_DDR#2

AA4

M_CLK_DDR2

AF10

DDR_CKE2_DIMMB

Y3

M_CLK_DDR#3

AA3

M_CLK_DDR3

AG10

DDR_CKE3_DIMMB

Y2 AA2 AG9 Y1 AA1 AF9

P4

DDR_CS2_DIMMB#

R2

DDR_CS3_DIMMB#

P3 P1

R4

M_ODT2

R3

M_ODT3

R1 P2 R7

DDR_B_BS0

P8

DDR_B_BS1

AA9

DDR_B_BS2

R10 R6

DDR_B_RAS#

P6

DDR_B_WE#

P7

DDR_B_CAS#

R8

DDR_B_MA0

Y5

DDR_B_MA1

Y10

DDR_B_MA2

AA5

DDR_B_MA3

Y7

DDR_B_MA4

AA6

DDR_B_MA5

Y6

DDR_B_MA6

AA7

DDR_B_MA7

Y8

DDR_B_MA8

AA10

DDR_B_MA9

R9

DDR_B_MA10

Y9

DDR_B_MA11

AF7

DDR_B_MA12

P9

DDR_B_MA13

AA8

DDR_B_MA14

AG7

DDR_B_MA15

AP18

DDR_B_DQS#0

AP11

DDR_B_DQS#1

AP5

DDR_B_DQS#2

AJ3

DDR_B_DQS#3

L3

DDR_B_DQS#4

H9

DDR_B_DQS#5

C8

DDR_B_DQS#6

C14

DDR_B_DQS#7

AP17

DDR_B_DQS0

AP12

DDR_B_DQS1

AP6

DDR_B_DQS2

AK3

DDR_B_DQS3

M3

DDR_B_DQS4

H8

DDR_B_DQS5

C9

DDR_B_DQS6

C15

DDR_B_DQS7

T13T13

1

M_CLK_DDR#2 <13> M_CLK_DDR2 <13> DDR_CKE2_DIMMB <13> M_CLK_DDR#3 <13> M_CLK_DDR3 <13> DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13>

M_ODT2 <13> M_ODT3 <13>

DDR_B_BS0 <13> DDR_B_BS1 <13> DDR_B_BS2 <13>

DDR_B_RAS# <13> DDR_B_WE# <13> DDR_B_CAS# <13>

DDR_B_MA[0..15] <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

CPI DRIVER VREF PATH IS DEFAULT

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet of

7 61Friday, April 19, 2013

1

1.0

5

D D

4

3

2

1

COMPENSATION PU FOR eDP

+VCOMP_OUT

EDP_COMP

Note: Trace width=20 mils ,Spacing=25mil,

EDP_AUXN EDP_AUXP

EDP_HPD

FDI_TXN_0

FDI_TXP_0

FDI_TXN_1

FDI_TXP_1

DDI

8 OF 9

Max length=100 mils.

M27

EDP_CPU_AUX#

N27

EDP_CPU_AUX

P27

EDP_HPD#

E24

EDP_COMP

R27

P35

EDP_CPU_LANE_N0

R35

EDP_CPU_LANE_P0

N34

EDP_CPU_LANE_N1

P34

EDP_CPU_LANE_P1

P33

FDI_CTX_PRX_N0

R33

FDI_CTX_PRX_P0

N32

FDI_CTX_PRX_N1

P32

FDI_CTX_PRX_P1

T14T14

HPD INVERSION FOR EDP

Haswell rPGA EDS

1 2

HDMI D2

HDMI D1

HDMI D0

C C

HDMI CLK

HD

MI

HDMI_TX2-_CK<36> HDMI_TX2+_CK<36> HDMI_TX1-_CK<36> HDMI_TX1+_CK<36> HDMI_TX0-_CK<36> HDMI_TX0+_CK<36> HDMI_CLK-_CK<36> HDMI_CLK+_CK< 36>

C48 0.1U_0402_16V7KHDMI@ C48 0.1U_0402_16V7KHDM I@

1 2

C41 0.1U_0402_16V7KHDMI@ C41 0.1U_0402_16V7KHDM I@

1 2

C42 0.1U_0402_16V7KHDMI@ C42 0.1U_0402_16V7KHDM I@

1 2

C43 0.1U_0402_16V7KHDMI@ C43 0.1U_0402_16V7KHDM I@

1 2

C44 0.1U_0402_16V7KHDMI@ C44 0.1U_0402_16V7KHDM I@

1 2

C45 0.1U_0402_16V7KHDMI@ C45 0.1U_0402_16V7KHDM I@

1 2

C46 0.1U_0402_16V7KHDMI@ C46 0.1U_0402_16V7KHDM I@

1 2

C47 0.1U_0402_16V7KHDMI@ C47 0.1U_0402_16V7KHDM I@

TMDS_B_DATA2#_PCH TMDS_B_DATA2_PCH TMDS_B_DATA1#_PCH TMDS_B_DATA1_PCH TMDS_B_DATA0#_PCH TMDS_B_DATA0_PCH TMDS_B_CLK#_PCH TMDS_B_CLK_PCH

Place on connector side

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HAS WELL

ME@

JCPU1H

eDP

EDP_RCOMP

EDP_DISP_UT IL

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1

12

R6024.9_0402_1% R6024.9_0402_1%

EDP_CPU_AUX# <33> EDP_CPU_AUX <33>

EDP_CPU_LANE_N0 <33>

EDP_CPU_LANE_P0 <33>

FDI_CTX_PRX_N0 <15>

FDI_CTX_PRX_P0 <15>

FDI_CTX_PRX_N1 <15>

FDI_CTX_PRX_P1 <15>

+VCCIO_OUT

10K_0402_5%

RC1

1 2

B B

R458

1 2

1K_0402_5%

TL_HPD<33>

1K_0402_5%

2

1

OUT

IN

GND

DTC124EKAT146_SC59-3

3

EDP_HPD#

Q6

HPD is a active high signal from device. The HPD processor input is a low voltage active signal.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet of

1

8 61Friday, April 19, 2013

1.0

5

4

3

2

1

CFG Straps for Processor

CFG2

12

R62

R62 1K_0402_1%

1K_0402_1%

PX@

D D

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

Haswell rPGA EDS

AT1

RSVD_TP

AT2

RSVD_TP

AD10

RSVD

A34

RSVD_TP

A35

RSVD_TP

W29

RSVD_TP

W28

RSVD_TP

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7

G26

TESTLO_G26

W33

RSVD

AL30

RSVD

AL29

RSVD

F25

VCC

C35

RSVD_TP

B35

RSVD_TP

AL25

RSVD_TP

W30

RSVD_TP

W31

RSVD_TP

W34

TESTLO

AT20

CFG_0

AR20

CFG_1

AP20

CFG_2

AP22

CFG_3

AT22

CFG_4

AN22

CFG_5

AT25

CFG_6

AN23

CFG_7

AR24

CFG_8

AT23

CFG_9

AN20

CFG_10

AP24

CFG_11

AP26

CFG_12

AN25

CFG_13

AN26

CFG_14

AP25

CFG_15

INTEL_HASWELL_HAS WELL

ME@

H_CPU_RSVD

C C

B B

1 2

H_CPU_TESTLO

CFG_RCOMP

H_CPU_RSVD

R64 49.9_0402 _1%R64 49.9_0402 _1%

R309 49.9_0402_1%R309 49.9_0402_1%

R66 49.9_0402_1%R66 49.9_0402_1%

+CPU_CORE

T16T16 T17T17

T18T18

H_CPU_TESTLO

JCPU1I

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

CFG_RCOMP

CFG_16 CFG_18 CFG_17 CFG_19

RSVD

FC_G6

RSVD RSVD RSVD RSVD RSVD

RSVD

RSVD RSVD

RSVD

RSVD_TP

RSVD_TP RSVD_TP

RSVD RSVD

VSS VSS

9 OF 9

C23 B23 D24 D23

AT31

CFG_RCOMP

AR21

CFG16

AR23 AP21 AP23

AR33 G6 AM27 AM26 F5 AM2 K6

E18

U10 P10

B1

NC

A2 AR1

E21 E20

AP27 AR26

AL31 AL32

T19T19

Embedded Display Port Presence Strap

PCIE Port Bifurcation Straps

CFG[6:5]

*

CFG4

*

@ R67

@

1K_0402_1%

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2

01: Reserved - (Device 1 function 1 disabled ; function

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PX@

1: Normal Operation; Lane # definition matches socket pin map definition

0:L

ane Reversed

12

R63

R63 1K_0402_1%

1K_0402_1%

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is con

nected to the Embedded Display Port

CFG6

CFG5

12

R67

R68

@R68

@

1K_0402_1%

disabled

2 enabled)

PEG DEFER TRAINING

(Default) PEG Train immediately following xxRESETB

CFG7

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

1: de assertion

*

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-9641P

1

9 61Friday, April 19, 2013

1.0

5

4

3

2

1

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC

VCC VCC

AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25

U25 U26 V25 V26

W26 W27

+CPU_CORE

Haswell rPGA EDS

JCPU1E

+CPU_CORE

AB11

AE11

AH11

W11

AL27 AK27

AL35

AN35

W32

AL16

AL13

AM28 AM29

AL28

AP35

AP34

AT35 AR35 AR32

AL26

AT34

AL22

AT33 AM21 AM25 AM22 AM20 AM24

AL19 AM23

AT32

K27 L27 T27 V27

AB2 AB5 AB8

AE2 AE5 AE8

K11 N11

N8

T11

T2 T5 T8

W2 W5 W8

N26 K26

E17

A23 F22

J27

H27

Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35

RSVD RSVD RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

RSVD VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT RSVD VCOMP_OUT RSVD RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

ME@

EL_HASWELL_HASWELL

INT

5 OF 9

+1.35V_CPU_VDDQ Source

D D

VCCSENSE

VSSSENSE

+CPU_CORE

100_0402_1%

12

100_0402_1%

12

R79

R84

VCC_SENSE

Note: 0 ohm Resistor should be placed cloose to CPU

C C

VCCSENSE<56>

VSSSENSE<11,56>

+1.35V +1.35V_CPU_VDDQ

J1

@J1

@

1 2

PAD-OPEN 43x118m

+1.05VS

R78 0_0603_5%@R78 0_0603_5%@

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

12

+VCCIO_OUT

1

2

+CPU_CORE

@

C53

4.7U_0402_6.3V6M

VR_SVID_ALRT#<56> VR_SVID_CLK<56> VR_SVID_DAT<56>

Note: Place the UP resistor close to CPU

+VCCIO_OUT

Note: Place the UP resistor close to CPU

12

R81

R81 75_0402_1%

75_0402_1%

1 2

R83 43_0402_5%R83 43_0402_5%

+VCCIO_OUT

12

R87

R87 130_0402_1%

130_0402_1%

+1.05VS

+VCCIO_OUT

+VCOMP_OUT

R88

150_0402_1%

10K_0402_5%

12

R89

+1.35V_CPU_VDDQ

VCCSENSE

H_CPU_SVIDALRT#

T23T23

@

1 2

VDDQ DECOUPLING

+1.35V_CPU_VDDQ

10U_0603_6.3V6M

C55

C54

1

B B

1

2

22U_0805_6.3V6M

C60

1

2

10U_0603_6.3V6M

C56

1

2

22U_0805_6.3V6M

C61

1

2

10U_0603_6.3V6M

C57

C58

1

+

C59

C59 220U_2.5V_M

2

22U_0805_6.3V6M

C62

1

2

220U_2.5V_M

2

22U_0805_6.3V6M

C63

C64

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet of

1

10 61Friday, April 19, 2013

1.0

5

D D

C C

B B

AA11 AA25 AA27 AA31 AA29

AB10 AA33 AA35

AC25 AC27

AC11 AD11 AC29 AC31 AC33 AC35

AD7

AE10 AE25 AE29

AE27 AE35

AF11

AG11 AG25 AE31 AG31 AE33

AG6 AH1

AH10

AH2 AG27 AG29

AH3 AG33 AG35

AH4

AH5

AH6

AH7

AH8

AH9

AJ11

AK11 AK25 AK26 AK28 AK29 AK30 AK32

A10 A13 A16 A19 A22 A25 A27 A29

A3 A31 A33

A4

A7

AB1

AB3

AB4 AB6 AB7 AB9

AE1

AE3

AE4 AE6 AE7 AE9

AF6 AF8

AJ5

E19

Haswell rPGA EDS

4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

EL_HASWELL_HASW ELL

INT

ME@

JCPU1F

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

6 OF 9

AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22

3

Haswell rPGA EDS

B34

VSS

B4

VSS

B7

VSS

C1

VSS

C10

VSS

C13

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C24

VSS

C26

VSS

C28

VSS

C30

VSS

C32

VSS

C34

VSS

C4

VSS

C7

VSS

D10

VSS

D13

VSS

D16

VSS

D19

VSS

D22

VSS

D25

VSS

D27

VSS

D29

VSS

D31

VSS

D33

VSS

D35

VSS

D4

VSS

D7

VSS

E1

VSS

E10

VSS

E13

VSS

E16

VSS

E4

VSS

E7

VSS

F10

VSS

F11

VSS

F12

VSS

F14

VSS

F15

VSS

F17

VSS

F18

VSS

F20

VSS

F21

VSS

F23

VSS

F24

VSS

F26

VSS

F28

VSS

F30

VSS

F32

VSS

F34

VSS

F4

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G1

VSS

G11

VSS

G2

VSS

G27

VSS

G29

VSS

G3

VSS

G31

VSS

G33

VSS

G35

VSS

G4

VSS

G5

VSS

H10

VSS

H26

VSS

H6

VSS

H7

VSS

J11

VSS

J26

VSS

J28

VSS

J30

VSS

J32

VSS

J34

VSS

J6

VSS

K1

VSS

EL_HASWELL_HASW ELL

INT

ME@

JCPU1G

2

VSS_SENSE

RSVD

7 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33

VSSSENSE <10,56>

T15T15

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

2

Date: Sheet of

1

11 61Friday, April 19, 2013

1.0

5

+1.35V +1.35V

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

JDIMM1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C65

C65

1

@

D D

C C

B B

A A

+3VS

2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

2.2U_0603_6.3V4Z

0.1U_0402_16V7K

C86

C87

1

@

2

5

+VREF_DQ_DIMMA

0.1U_0402_16V7K

DDR_A_D0

C66

DDR_A_D1

1

DDR_A_DM0

2

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U8SN-7F

ME@

VREF_CA

EVENT#

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

DM6

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

SDA

VTT2

4

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

1

2

+VREF_CA

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C68

C68

@

DDR_A_DQS#[0..7]<7>

DDR_A_MA[0..15]<7>

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

4

+0.675VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR3_DRAMRST# <13,6>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_16V7K

0.1U_0402_16V7K C67

C67

1

2

SMB_DATA_S3 <13,17,37> SMB_CLK_S3 <13,17,37>

DQ4 DQ5

DQ6 DQ7

A15 A14

A11

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC2

SCL

G2

3

+VREF_DQ_DIMMA_R

1

C39

@

0.022U_0402_16V7K

2

12

@

+VREF_CA_R+1.35V

12

R40

1K_0402_1%

+VREF_CA

12

R44

1K_0402_1%

+VREF_CA <13>

Layout Note: Place near DIMM

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

R472_0402_5% R472_0402_5%

1

C37

@

0.022U_0402_16V7K

2

12

R45

@

C69

1

@

2

C84

1U_0402_6.3V6K

C84

1U_0402_6.3V6K

1

2

@

C70

10U_0603_6.3V6M@C70

10U_0603_6.3V6M

1

2

@

C85

1U_0402_6.3V6K@C85

1U_0402_6.3V6K

1

2

Compal Secret Data

24.9_0402_1%

Layout Note: Place near DIMM

10U_0603_6.3V6M@C69

10U_0603_6.3V6M

1

@

2

+0.675VS

@

C82

C83

1U_0402_6.3V6K@C83

1U_0402_6.3V6K

1

2

2011/06/15 2012/07/11

2

1 2

R48 2_0402_5%R48 2_0402_5%

R54

24.9_0402_1%

Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket

+1.35V

C72

10U_0603_6.3V6M

C72

10U_0603_6.3V6M

C73

10U_0603_6.3V6M

C73

1

2

1

2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

10U_0603_6.3V6M

1

2

Layout Note: Place near DIMM

C71

10U_0603_6.3V6M

C71

10U_0603_6.3V6M

Deciphered Date

C74

10U_0603_6.3V6M

C74

10U_0603_6.3V6M

1

2

+VREF_DQ_DIMMA

C75

10U_0603_6.3V6M

C75

10U_0603_6.3V6M

1

+VREF_DQ_DIMMA

Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket

RP18

1K_0804_8P4R_1%

C80

0.1U_0402_16V7K

C80

0.1U_0402_16V7K

1

2

LA-9641P

1

18 27 36 45

1

+

2

+VREF_DQ_DIMMA

+VREF_DQ_DIMMB

C79

0.1U_0402_16V7K

C79

C76

10U_0603_6.3V6M

C76

10U_0603_6.3V6M

C77

0.1U_0402_16V7K

C77

0.1U_0402_16V7K

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

0.1U_0402_16V7K

C78

0.1U_0402_16V7K

C78

0.1U_0402_16V7K

1

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

+1.35V

EVT Check

C81

@+C81

@

220U_6.3V_M

12 61Friday, April 19, 2013

1.0

of

5

3A@1.35V

3A@1.35V3A@1.35V

JDIMM2

+VREF_DQ_DIMMB

2.2U_0603_6.3V4Z

0.1U_0402_16V7K

@

1

C88

D D

C C

B B

+3VS

A A

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

C109

0.1U_0402_16V7K

C109

0.1U_0402_16V7K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C108

C108

1

@

2

5

DDR_B_D0 DDR_B_D1

DDR_B_DM0

1

C89

DDR_B_D2 DDR_B_D3

2

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

1 2

+3VS

R93 10K_0402_5%R93 10K_0402_5%

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F M

M

4

+1.35V+1.35V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3

0.65A@0.675V

0.65A@0.675V0.65A@0.675V

DDR3_DRAMRST# <12,6>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

2.2U_0603_6.3V4Z

0.1U_0402_16V7K

C90

1

2

SMB_DATA_S3 <12,17,37> SMB_CLK_S3 <12,17,37>

+0.675VS

C91

@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

A15 A14

VDD4

A11

A7

VDD6

A6 A4

VDD8

A2 A0

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

G2

E@

4

3

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_DQS#[0..7]<7>

DDR_B_MA[0..15]<7>

Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes

Layout Note: Place near DIMM

+VREF_CA <12>

10U_0603_6.3V6M

C92

1

@

2

Layout Note: Place near DIMM

+0.675VS

@

C104

1U_0402_6.3V6K@C104

1U_0402_6.3V6K

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

C185

1

@

2

@

C106

1U_0402_6.3V6K@C106

1U_0402_6.3V6K

C105

1U_0402_6.3V6K

C105

1U_0402_6.3V6K

1

2

Compal Secret Data

C94

1

2

+VREF_DQ_DIMMB_R

@

+1.35V

10U_0603_6.3V6M

C95

1

2

C107

1U_0402_6.3V6K

C107

1U_0402_6.3V6K

1

2

Deciphered Date

2

1 2

R49 2_0402_5%R49 2_0402_5%

1

C40

0.022U_0402_16V7K

2

12

R59

24.9_0402_1%

10U_0603_6.3V6M

C96

C97

1

2

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

Layout Note: Place near DIMM

2

1

+VREF_DQ_DIMMB

0.1U_0402_16V7K

10U_0603_6.3V6M

C98

1

2

0.1U_0402_16V7K

10U_0603_6.3V6M

C100

C99

C100

1

2

Title

Size Document Number Rev

Date: Sheet of

0.1U_0402_16V7K

0.1U_0402_16V7K C101

C101

1

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

0.1U_0402_16V7K

C102

C103

1

2

C103

1

2

LA-9641P

1

13 61Friday, April 19, 2013

1.0

5

0mils

1

C110

C110 1U_0603_10V6K

D D

C C

B B

1U_0603_10V6K

2

+RTCVCC

1 2

R96 1M_0402_5%R96 1M_0402_5%

1 2

R97 330K_0402_5%R97 330K_0402_5%

INTVRMEN

(INTEGRATED SUS 1.05V VR)

*

H

：：：：

Integrated VRM enable

L

：：：：

Integrated VRM disable

(INTVRMEN should always be pull high.)

+3V_PCH

R100 1K_0402_5%@R100 1K_0402_5%@

+3VS

R101 1K_0402_5%@R101 1K_0402_5%@

+3VS

R102 1K_0402_5%@R102 1K_0402_5%@

HIGH= Enable ( No Reboot )

*

LOW= Disable (Default) / weak internal pull low

+3V_PCH

R105 1K_0402_5%@R105 1K_0402_5%@

*

Low = Disabled (Default) High = Enabled [Flash Descriptor Security Override]

HDA_BITCLK_AUDIO<42>

HDA_SYNC_AUDIO<42> HDA_RST_AUDIO#<42>

HDA_SDOUT_AUDIO<42>

+3V_PCH +3V_PCH+3V_PCH

12

R119

@

200_0402_1%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

R122

100_0402_1%

@

1 2

12

@

12

@

1K_0402_5%

1 2

33_0804_8P4R_5%

R311

200_0402_1%

R123

R123 100_0402_1%

100_0402_1%

W=20milsW=2

+RTCBATT+RTCVCC

R94

Note: PCH_RTCX1/PCHRTCX2 Trace length <1000 mils

SM_INTRUDER#

PCH_INTVRMEN

HDA_SYNC

PCH_GPIO33

HDA_SPKR HDA_SDIN0

+RTCVCC

1U_0603_10V6K

1 2

R98 20K_0402_5%R98 20K_0402_5%

1 2

R99 20K_0402_5%R99 20K_0402_5%

1U_0603_10V6K

C113

C115

1

2

1

2

ME FALSH

ME_FLASH<43>

ME_FLASH

RP12

18

HDA_BIT_CLK

27

HDA_SYNC

36

HDA_RST#

45

ME_FLASH

12

R121

@

200_0402_1%

12

R124

100_0402_1%

@

4

R95 10M_0402_5%R95 10M_0402_5%

12

0_0402_5%

0_0402_5% R689

R689

@

1

C111

15P_0402_50V8J

2

CLRP2

SHORT PADS

CLRP2

SHORT PADS

OPE

N SAVE ME RTC REGISTER

12

SHORT CLEAR ME RTC REGISTER

PCH_SRTCRST#

PCH_RTCRST#

CLRP3

SHORT PADS

CLRP3

SHORT PADS

12

CLRP3

OPEN SAVE CMOS

SHORT CLEAR CMOS

R104 1K_0402_5%@R104 1K_0402_5%@

+3V_PCH

R106 10K_0402_5%@R106 10K_0402_5%@

1 2

Y1

1 2

RP2

CL

HDA_SPKR<42>

HDA_SDIN0<42>

1 2

PCH_RTCX1

PCH_RTCX2

32.768KHZ_12.5PF_CM31532768DZFT

1

C112

C112 15P_0402_50V8J

15P_0402_50V8J

2

PCH_RTCX1

PCH_RTCX2

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

ME_FLASH

PCH_GPIO33

PCH_GPIO13

12

PCH_JTAG_TCK

R110

51_0402_5%

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

U4A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

DH8

2LPMS-QC4C-A1_FCBGA695~D

3

LPT_PCH_M_EDS

JTAGRTC AZALIA

1 OF 11

SATA

SATA_RXN_0 SATA_RXP_0

SATA_TXN_0 SATA_TXP_0

SATA_RXN_1 SATA_RXP_1

SATA_TXN_1 SATA_TXP_1

SATA_RXN_2 SATA_RXP_2

SATA_TXN_2 SATA_TXP_2

SATA_RXN_3 SATA_RXP_3

SATA_TXN_3 SATA_TXP_3

SATA_RXN4/PERN1 SATA_RXP4/PERP1

SATA_TXN4/PETN1 SATA_TXP4/PETP1

SATA_RXN5/PERN2 SATA_RXP5/PERP2

SATA_TXN5/PETN2 SATA_TXP5/PETP2

SATA_RCOMP

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_IREF

2

BC8 BE8

AW8 AY8

BC10 BE10

AV10 AW10

BB9 BD9

AY13 AW13

BC12 BE12

AR13 AT13

BD13 BB13

AV15 AW15

BC14 BE14

AP15 AR15

AY5

SATA_COMP

AP3

SATA_ACT#

AT1

HDD_DET#

AU2

BBS_BIT0_R

BD4

BA2

TP9

BB2

TP8

12

R108 10K_0402_5%R108 10K_0402_5%

HDD_DET# <19>

BBS_BIT0_R <19>

+1.5VS

HDD_DET# and BBS_BIT0_R pull high by 10P8R

SATA_DTX_C_PRX_N4

SATA_DTX_C_PRX_P4

SATA_PTX_C_DRX_N4 SATA_PTX_C_DRX_P4

SATA_DTX_C_PRX_N5 SATA_DTX_C_PRX_P5

SATA_PTX_C_DRX_N5 SATA_PTX_C_DRX_P5

+3VS

SATA_DTX_C_PRX_N4 <41>

SATA_DTX_C_PRX_P4 <41>

SATA_PTX_C_DRX_N4 <41> SATA_PTX_C_DRX_P4 <41>

SATA_DTX_C_PRX_N5 <41>

SATA_DTX_C_PRX_P5 <41>

SATA_PTX_C_DRX_N5 <41> SATA_PTX_C_DRX_P5 <41>

SATA Impedance Compensation

SATA_COMP

Note: Trace width:4mils Place the resistor to PCH <500 mils, to 1.5V <100 mils.Avoid routing next to clock pins.

1 2

1

HDD

SATA 6G

ODD

+1.5VS

R1077.5K_0402_1% R1077.5K_0402_1%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

1

14 61Friday, April 19, 2013

1.0

5

4

3

2

1

+3VS

12

R126

R125

2.2K_04 02_5%

LPT_PCH_M_EDS

U4B

D D

C C

DMI_CTX_PRX _N0<5> DMI_CTX_PRX _N1<5>

DMI_CTX_PRX _N2<5> DMI_CTX_PRX _N3<5>

DMI_CTX_PRX _P0<5> DMI_CTX_PRX _P1<5>

DMI_CTX_PRX _P2<5> DMI_CTX_PRX _P3<5>

DMI_CRX_P TX_N0<5> DMI_CRX_P TX_N1<5>

DMI_CRX_P TX_N2<5> DMI_CRX_P TX_N3<5>

DMI_CRX_P TX_P0<5> DMI_CRX_P TX_P1<5>

DMI_CRX_P TX_P2<5> DMI_CRX_P TX_P3<5>

+1.5VS

SUSACK# is only used on platform tha

t support the Deep Sx state.

+1.5VS

R135 7.5K_ 0402_1%R135 7.5 K_0402_1%

+3VS

ACIN<24,43,4 8,50>

R136 0_04 02_5%@R136 0_04 02_5%@

R148 0_04 02_5%@R148 0_04 02_5%@

D1 CH751 H-40PT_SOD32 3-2D1 CH751 H-40PT_SOD32 3-2

SUSACK#<43>

PCH_PW ROK<43>

PM_DRAM_P WRGD<6>

EC_RSMRST#<43>

SUSWAR N#<43>

PBTN_OUT#<43>

AEPWROK can be connect to PWROK if iAMT disable

1 2

21

DMI_CTX_PRX _N0 DMI_CTX_PRX _N1

DMI_CTX_PRX _N2 DMI_CTX_PRX _N3

DMI_CTX_PRX _P0 DMI_CTX_PRX _P1

DMI_CTX_PRX _P2 DMI_CTX_PRX _P3

DMI_CRX_P TX_N0 DMI_CRX_P TX_N1

DMI_CRX_P TX_N2 DMI_CRX_P TX_N3

DMI_CRX_P TX_P0 DMI_CRX_P TX_P1

DMI_CRX_P TX_P2 DMI_CRX_P TX_P3

12

R13810 K_0402_5 % R1381 0K_0402_5 %

DMI_RCOMP

SUSACK#_ R

SYS_RST#

SYS_PW ROK

PCH_PW ROK

PM_DRAM_P WRGD

SUSWAR N#_R

AC_PRESE NT_R

PCH_GPIO 72

RI#

U4B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESET#

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

J2

RSMRST#

J4

SUSWARN#/SUSPWRNACK/GPIO30

K1

PWRBTN#

E6

ACPRESENT/GPIO31

K7

BATLOW#/GPIO72

N4

RI#

AB10

TP21

D2

SLP_WLAN#/GPIO29

LPT_PCH_M_EDS

DMI

System Power

Management

LPMS-QC4C -A1_FCBGA69 5~D

DH82

FDI

FDI_RCOMP

DSWVRMEN

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

4 OF 11

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

TP16

TP15

TP10

FDI_CSYNC

FDI_INT

FDI_IREF

TP17

TP13

DPWROK

WAKE#

CLKRUN#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#

AJ35

FDI_CTX_PRX _N0

AL35

FDI_CTX_PRX _N1

AJ36

FDI_CTX_PRX _P0

AL36

FDI_CTX_PRX _P1

AV43

AY45

TP5

AV45

AW44

AL39

FDI_CSYNC

AL40

FDI_INT

AT45

AU42

AU44

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

1 2

FDI_RCOMP

R145 7.5K_ 0402_1%R145 7. 5K_0402_1 %

DSWODV REN

1 2

PCH_DPW ROK EC_RSMRST#

PM_CLKRUN #

SUS_STAT#

SLP_A#

SLP_SUS #

H_PM_SYNC

R139

T20T20

T22T22

FDI_CTX_PRX _N0 <8>

FDI_CTX_PRX _N1 <8>

FDI_CTX_PRX _P0 <8>

FDI_CTX_PRX _P1 <8>

FDI_CSYNC <5>

FDI_INT <5 >

+1.5VS

0_0402_ 5%@

SUSCLK <43>

PM_SLP_ S5# <43>

PM_SLP_ S4# <43>

PM_SLP_ S3# <43>

SLP_SUS # <43,47>

H_PM_SYNC <6>

PCIE_W AKE# <37,38>

PCH_DPW ROK

SLP_A# can be left NC when IAMT is not support on the platfrom

SLP_LAN# can be left NC if no use integrated LAN.

R149 0_04 02_5%@R149 0_04 02_5%@

DGPU_HOL D_RST#<23>

DGPU_PW R_EN<25,43,5 3,55>

1 2

DAC_BLU<35>

DAC_GRN<35>

DAC_RED<35 >

2.2K_04 02_5%

CRT_DDC_CLK CRT_DDC_DATA

DAC_BLU

DAC_GRN

DAC_RED

1 2

R132 649 _0402_1%R132 649 _0402_1%

PCI_PIRQA #

PCI_PIRQB #

PCI_PIRQC #

PCI_PIRQD #

PCH_GPIO 52

DGPU_PW R_EN

BBS_BIT1

PCH_GPIO 53

T21T21

1 2

R182 10K_040 2_5%R182 10K_0 402_5%

PCH_WL _OFF#<37>

CRT_DDC_CLK<3 5>

CRT_DDC_DATA<35>

CRT_HSYNC<35>

CRT_VSYNC<3 5>

PCH_PW M<33>

DPWROK _EC <43>

BBS_BIT1

Boot BIOS Strap (GPIO51)

SATA_SLPD

BBS_BIT1 Boot BIOS Location

(BBS_BIT0)

150_080 4_8P4R_5%

CRT_DDC_CLK

CRT_DDC_DATA

CRT_IREF

PCH_PW M

PCH_ENBK L

PCH_ENVDD

PCH_WL _OFF#

RP23

4 5 3 6 2 7 1 8

T45

U44

V45

M43

M45

N42

N44

U40

U39

N36

K36

G36

H20

L20

K17

M20

A12

B13

C12

C10

A10

AL6

DAC_BLU DAC_GRN DAC_RED

U4E

VGA_BLUE

VGA_GREEN

VGA_RED

VGA_DDC_CLK

VGA_DDC_DATA

VGA_HSYNC

VGA_VSYNC

DAC_IREF

VGA_IRTN

EDP_BKLTCTL

EDP_BKLTEN

EDP_VDDEN

PIRQA#

PIRQB#

PIRQC#

PIRQD#

GPIO50

GPIO52

GPIO54

GPIO51

GPIO53

GPIO55

+3VS

LPT_PCH_M_EDS

LVDSCRT

PCI

LPMS-QC4C -A1_FCBGA69 5~D

DH82

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DISPLAY

DDPD_AUXN

DDPB_AUXP

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

PME#

PLTRST#

5 OF 11

R40

HDMICLK_NB

R39

HDMIDAT_NB

R35

R36

N40

N38

H45

K43

J42

H43

K45

J44

K40

K38

H39

G17

PCH_GPIO 2

F17

PCH_GPIO 3

L15

PCH_GPIO 4

M15

PCH_GPIO 5

AD10

PCI_PME#

Y11

PLT_RST#

12

C494

22P_040 2_50V8J

DVT ESD request

HDMICLK_NB <36>

HDMIDAT_NB <36>

TMDS_B_HPD <36 >

12

R156

R156 100K_04 02_5%

100K_04 02_5%

PLT_RST# <23 ,37,38,43>

00 LPC

0 1 Reserved (NAND)

B B

1 0

11 SPI

U6 MC74VHC1G 08DFT2G SC70 5P@U6MC74VHC1G 08DFT2G SC70 5P@

3

1

VGATE<43,56>

PCH_PW ROK

SU

SACK# and SUSWARN# can be tied together if

does not want to involve in the handshake

EC mechanism for the Deep Sleep state entry and exit.

A A

+3V_PCH

1 2

G

A

2

B

P

5

+3VS

1 2

R169 0_04 02_5%@R169 0_0402 _5%@

R173 200K_04 02_5%R173 200K_ 0402_5%

Y

4

SYS_PW ROK

SUSACK#_ RSUSWAR N#_R

AC_PRESE NT_R

12

R157 100K_04 02_5%

100K_04 02_5%

SYS_PW ROK <43,6>

@R157

@

CLKRUN#: External pull up to core well is required.

+3VS

1 2

+3V_PCH

+3VALW

R172 8. 2K_0402_ 5%R17 2 8.2K_0 402_5%

4 5 3 6 2 7 1 8

RP10

10K_080 4_8P4R_5%

PM_CLKRUN #

SUSWAR N#_R

PCIE_W AKE# PCH_GPIO 72 RI#

+RTCVCC

12

DSWODV REN

DSWODVREN - On Die DSW VR Enable H：Enable (DEFAULT)

*

L：Disable

12

R134

R134 330K_04 02_5%

330K_04 02_5%

R143

R143 330K_04 02_5%

330K_04 02_5%

@

PCH_WL _OFF#

A16 swap overide Strap/Top-Block Swap Override ju mper

PCI_GNT3#

PCH_WL _OFF#

1 2

R158 1K_040 2_5%@R158 1K_ 0402_5%@

Low=A16 swap override/Top-Blo ck Swap Override en abled High=Default

1 2

R176 10K_040 2_5%R176 10K_0 402_5%

PCI

*

GPIO51 has internal pull up.

GPIO55

*

+3VS

PCH_GPIO 2 DGPU_PW R_EN PCH_GPIO 3

+3VS

PCI_PIRQA # PCI_PIRQB # PCI_PIRQC # PCI_PIRQD #

DGPU_HOL D_RST#

RP13

6 7 8 9

10

10K_120 6_10P8R_5 %

8.2K_08 04_8P4R_5 %

5 4 3 2 1

RP1

18 27 36 45

12

R167 10 K_0402_5 %R167 10K_0402_ 5%

12

R168 10 K_0402_5 %

@

+3VS

PCH_GPIO 4 PCH_GPIO 5 PCH_GPIO 52

+3VS

12

R312 10K_040 2_5%R312 10K_0 402_5%

5

EC_RSMRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

4

3

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (2/9) PCIE, SMBUS, CLK

Size Doc ument Numb er Rev

Custom

LA-9641P

Date: S heet of

1

15 6 1Friday, April 19, 2013

1.0

5

D D

SW set GPO

+3V_PCH

WLAN

C C

LAN

B B

+3V_PCH

CLK_PCIE_WLAN#<37>

CLK_PCIE_WLAN<37>

CLKREQ_WLAN#<37>

CLK_PCIE_LAN#< 38> CLK_PCIE_LAN<38>

CLKREQ_LAN#<38>

SW set GPO

4 5 3 6 2 7 1 8

RP9

10K_0804_8P4R_5%

PCH_GPIO26 PCH_GPIO44 PCH_GPIO45 PCH_GPIO46

@

R181 10K_04 02_5%@R181 1 0K_0402_5%@

R184 10K _0402_5%@R184 10K_0402_5%@

+3VS

R313 0_04 02_5%R3 13 0_0402_5%

R189 0_04 02_5%R1 89 0_0402_5%

+3V_PCH

CLK_PCI_EC<43>

12

1 2

R195 10K_04 02_5%R195 10K_0402_5%

+3VS

1 2

R185 0_04 02_5%R1 85 0_0402_5%

1 2

R187 0_04 02_5%R1 87 0_0402_5%

R201 10K_04 02_5%R201 10K_0402_5%

12

1 2

CLK_PCIE_WLAN#_R

CLK_PCIE_WLAN_R

4

PCH_GPIO73

PCH_GPIO18

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

PCH_GPIO26

PCH_GPIO44

PCH_GPIO45

PCH_GPIO46

CLK_PCI_LPBACK_RCLK_PCI_LPBACK

R20922_0402_5% R20922_0402_5%

CLK_PCI_EC_R

R21122_0402_5% R21122_0402_5%

CLK_PCI_DB_R

U4C

Y43

CLKOUT_PCIE_N_0

Y45

CLKOUT_PCIE_P_0

AB1

PCIECLKRQ0#/GPIO73

AA44

CLKOUT_PCIE_N_1

AA42

CLKOUT_PCIE_P_1

AF1

PCIECLKRQ1#/GPIO18

AB43

CLKOUT_PCIE_N_2

AB45

CLKOUT_PCIE_P_2

AF3

PCIECLKRQ2#/GPIO20/SMI#

AD43

CLKOUT_PCIE_N_3

AD45

CLKOUT_PCIE_P_3

T3

PCIECLKRQ3#/GPIO25

AF43

CLKOUT_PCIE_N_4

AF45

CLKOUT_PCIE_P_4

V3

PCIECLKRQ4#/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P_5

AA2

PCIECLKRQ5#/GPIO44

AB40

CLKOUT_PCIE_N_6

AB39

CLKOUT_PCIE_P_6

AE4

PCIECLKRQ6#/GPIO45

AJ44

CLKOUT_PCIE_N_7

AJ42

CLKOUT_PCIE_P_7

Y3

PCIECLKRQ7#/GPIO46

AH43

CLKOUT_ITPXDP

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

LPT_PCH_M_EDS

DH8

2LPMS-QC4C-A1_FCBGA695~D

CLOCK SIGNAL

3

CLKOUT_PEG_A

CLKOUT_PEG_A_P

PEGA_CLKRQ#/GPIO47

CLKOUT_PEG_B

CLKOUT_PEG_B_P

PEGB_CLKRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_P

CLKOUT_DP

CLKOUT_DP_P

CLKOUT_DPNS

CLKOUT_DPNS_P

CLKIN_DMI

CLKIN_DMI_P

CLKIN_GND

CLKIN_GND_P

CLKIN_DOT96N

CLKIN_DOT96P

CLKIN_SATA

CLKIN_SATA_P

REFCLK14IN

CLKIN_33MHZLOOPBACK

XTAL25_IN

XTAL25_OUT

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

ICLK_IREF

TP19 TP18

DIFFCLK_BIASREF

2 OF 11

+3V_PCH

R177 10K _0402_5%R177 10K_0402_5%

XTAL25_IN XTAL25_OUT

R178 0_04 02_5%@R178 0_040 2_5%@

PEG_CLKREQ#_R

AB35

CLK_PCIE_VGA#_R CLK_PCIE_VGA#

AB36

AF6

PEG_CLKREQ#_R

Y39

Y38

U4

PCH_GPIO56

AF39

CLK_CPU_DMI#

AF40

CLK_CPU_DMI

AJ40

CLK_CPU_SSC_DPLL#

AJ39

CLK_CPU_SSC_DPLL

AF35

CLK_CPU_DPLL#

AF36

CLK_CPU_DPLL

AY24

CLK_BUF_DMI#

AW24

CLK_BUF_DMI

AR24

CLK_BUF_BCLK#

AT24

CLK_BUF_BCLK

H33

CLK_BUF_DOT96#

G33

CLK_BUF_DOT96

BE6

CLK_BUF_CKSSCD#

BC6

CLK_BUF_CKSSCD

F45

CLK_PCH_14M

D17

CLK_PCI_LPBACK

AM43 AL44

C40

F38

F36

F39

PCH_GPIO67

AM45

AD39 AD38

AN44

PCH_CLK_BIASREF

12

1 2

R186 0_04 02_5%R1 86 0_0402_5%

1 2

R188 0_04 02_5%R1 88 0_0402_5%

SW set GPO

R191 10K _0402_5%@R191 10K_0402_5%@

12

CLK_CPU_DMI# <6>

CLK_CPU_DMI <6>

CLK_CPU_SSC_DPLL# <6> CLK_CPU_SSC_DPLL <6>

CLK_CPU_DPLL# <6> CLK_CPU_DPLL <6>

1 2

R214

7.5K_0402_1%

CLK_PCIE_VGACLK_PCIE_VGA_R

PCH_GPIO67 <19>

+1.5VS

+1.05V_+1.5V_RUN

2

CLK_REQ_VGA# <24>

+3V_PCH

1

CLK_PCIE_VGA# <23>

CLK_PCIE_VGA <23>

CLK_BUF_DMI# CLK_BUF_DMI

CLK_BUF_BCLK# CLK_BUF_BCLK

CLK_BUF_DOT96# CLK_BUF_DOT96

CLK_BUF_CKSSCD# CLK_BUF_CKSSCD

CLK_PCH_14M

R183 10K _0402_5%R183 10K_0402_5% R192 10K _0402_5%R192 10K_0402_5%

R193 10K _0402_5%R193 10K_0402_5% R194 10K _0402_5%R194 10K_0402_5%

R197 10K _0402_5%R197 10K_0402_5% R199 10K _0402_5%R199 10K_0402_5%

R202 10K _0402_5%R202 10K_0402_5% R203 10K _0402_5%R203 10K_0402_5%

R205 10K _0402_5%R205 10K_0402_5%

12 12

12

CLOCK TERMINATION for FCIM and need close to PCH

XTAL25_IN

XTAL25_OUT

C118

12P_0402_50V8J

1 2

R215 1M_0402_5%R215 1M_0402_5%

3

OSC

2

OSC

NC

Y2

25MHZ_10PF_7V25000014

1

2

4

NC

1

C119

R02

C119

12P_0402_50V8J

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (3/9) DMI,FDI,PM,

LA-9641P

1

16 61Friday, April 19, 2013

1.0

5

D D

LPC_AD0<43>

LPC_AD1<43>

LPC_AD2<43>

LPC_AD3<43>

+3VS

SPI_CLK_PCH

SPI_CS#

C C

SPI_WP#

SPI_HOLD#

+3V_ROM

1 2

R229 1K _0402_5%R229 1K_0402_5%

1 2

R230 1K _0402_5%R230 1K_0402_5%

SPI_CLK_PCH_R

12

R237

33_0402_5%

@

B B

C120

22P_0402_50V8J

@

R124;c190 close to U4.T3 pin

LPC_FRAME#<43>

R223 10K_04 02_5%R223 10K_0402_5%

R240 33_0402_5 %R240 33_0402_5%

R246 0_0402_5%R246 0_0402_5%

R245 0_0402_5%R245 0_0402_5%

SPI_IO2

SPI_IO3

12

SERIRQ<43>

1 2

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

SERIRQ

SPI_CLK_PCH_R

SPI_SB_CS1#

SPI_SI

SPI_SO

SPI_IO2

SPI_IO3

A20

C20

A18

C18

B21

D21

G20

AL11

AJ11

AJ7

AL7

AJ10

AH1

AH3

AJ4

AJ2

4

LPT_PCH_M_EDS

U4D

LAD_0

LAD_1

LAD_2

LAD_3

LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_CS2#

SPI_MOSI

SPI_MISO

SPI_IO2

SPI_IO3

DH8

LPT_PCH_M_EDS

LPC

SPI

2LPMS-QC4C-A1_FCBGA695~D

8MB SPI ROM FOR ME & Non-share ROM.

SPI_CS#

SPI_WP#

SPI_SO SPI_SI SPI_CLK_PCH SPI_CS#

SMBus

SML1ALERT#/PCHHOT#/GPIO74

C-Link

Thermal

3 OF 11

U8

1

CS#

2

SO

3

WP#

4

GND

16M W25Q64DVSSIQ SOIC 8P

1 8 2 7 3 6 4 5

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1CLK/GPIO58

SML1DATA/GPIO75

8

VCC

7

HOLD#

6

SCLK

5

SI

hare ROM

S

RP2

SROM@

0_0804_8P4R_5%

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK

CL_DATA

CL_RST#

TP1

TP2

TP4

TP3

TD_IREF

SPI_HOLD#SPI_SO SPI_CLK_PCH SPI_SI

EC_SPI_SO EC_SPI_SI EC_SPI_CLK EC_SPI_CS#

3

N7

PCH_GPI011

R10

PCH_SMBCLK

U11

PCH_SMBDATA

N8

PCH_GPIO60

U8

PCH_SML0CLK

R7

PCH_SML0DATA

H6

PCH_HOT#

K6

SML1CLK

N11

SML1DATA

AF11

AF10

AF7

BA45

BC45

BE43

BE44

AY43

PCH_TD_IREF

R228 8.2K_0402_1%R228 8.2K_0402_1%

+3V_ROM

PJ2 JUMP_43X39

PJ3 JUMP_43X39

12

R216

10K_0402_5%

R221

@ R221

@

1K_0402_5%

SW set GPO

12

R222 10K_0402_5%R222 10K_0402_5%

1 2

@

2

112

@

2

112

EC_SPI_SO <43>

EC_SPI_SI <43>

EC_SPI_CLK <43>

EC_SPI_CS# <43>

+3V_PCH

12

+3V_PCH

+3VS

+3VALW

2

2N7002DW-T/R7_SOT363-6

Q11A

6 1

2

5

3

Q11B

Q130A

6 1

3

Q130B

+3VS

4

2

5

4

SMB_CLK_S3

SMB_DATA_S3

EC_SMB_CK2

+3VS

EC_SMB_DA2

PCH_SML0CLK

PCH_SML0DATA

PCH_SMBDATA SMB_CLK_S3 SMB_DATA_S3 PCH_SMBCLK

EC_SMB_CK2 EC_SMB_DA2

SML1DATA SML1CLK

SMB_CLK_S3 <12,13,37>

DIMM1 DIMM2 MINI CARD

SMB_DATA_S3 <12,13,37>

EC_SMB_CK2 <24,33,40,43>

VGA EC thermal sensor

2.2K_0402_5%

2.2K_0804_8P4R_5%

Translator

EC_SMB_DA2 <24,33,40,43>

+3V_PCH

R226

RP16

RP17

1 2

R227

2.2K_0402_5%

1 2

+3VS

18 27 36 45

+3VS

18 27 36 45

1

+3V_PCH

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH (4/9) LVDS,CRT,DP,HDMI

LA-9641P

1

17 61Friday, April 19, 2013

1.0

of

5

D D

PCIE_PRX_DTX_N2<37>

N

WLA

LAN

C C

B B

PCIE_PRX_DTX_P2<37>

PCIE_PTX_C_DRX_N2<37> PCIE_PTX_C_DRX_P2<37>

PCIE_PRX_DTX_N3<38> PCIE_PRX_DTX_P3<38>

PCIE_PTX_C_DRX_N3<38> PCIE_PTX_C_DRX_P3<38>

C125 0.1U_0402_16V7KC125 0.1U_0402_16V7K C123 0.1U_0402_16V7KC123 0.1U_0402_16V7K

C122 0.1U_0402_16V7KC122 0.1U_0402_16V7K C124 0.1U_0402_16V7KC124 0.1U_0402_16V7K

+1.5VS

4

1 2 1 2

1 2

R244 7.5K_0402_1%R244 7.5K_0402_1%

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCH_PCIE_RCOMP

AW31

AY31

BE32 BC32

AT31

AR31

BD33 BB33

AW33

AY33

BE34 BC34

AT33

AR33

BE36 BC36

AW36

AV36

BD37 BB37

AY38

AW38

BC38 BE38

AT40 AT39

BE40 BC40

AN38 AN39

BD42 BD41

BE30

BC30

BB29

BD29

U4I

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

PERN_3 PERP_3

PETN_3 PETP_3

PERN_4 PERP_4

PETN_4 PETP_4

PERN_5 PERP_5

PETN_5 PETP_5

PERN_6 PERP_6

PETN_6 PETP_6

PERN_7 PERP_7

PETN_7 PETP_7

PERN_8 PERP_8

PETN_8 PETP_8

PCIE_IREF

TP11

TP6

PCIE_RCOMP

DH8

2LPMS-QC4C-A1_FCBGA695~D

LPT_PCH_M_EDS

PCIe

3

USB

9 OF 11

USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9

USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USB3RN5 USB3RP5

USB3TN5 USB3TP5

USB3RN6 USB3RP6

USB3TN6 USB3TP6

USBRBIAS#

USBRBIAS

TP24 TP23

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

USB DEBUG=PORT1 AND PORT9

B37 D37 A38 C38 A36 C36 A34 C34 B33 D33 F31 G31 K31 L31 G29 H29 A32 C32 A30 C30 B29 D29 A28 C28 G26 F26 F24 G24

AR26 AP26 BE24 BD23 AW26 AV26 BD25 BC24 AW29 AV29 BE26 BC26 AR29 AP29 BD27 BE28

K24 K26

M33 L33

P3 V1 U2 P1 M3 T1 N2 M1

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11

USB3_RX1_N USB3_RX1_P USB3_TX1_N USB3_TX1_P USB3_RX2_N USB3_RX2_P USB3_TX2_N USB3_TX2_P

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

USBRBIAS

USB20_N0 <46> USB20_P0 <46> USB20_N1 <46> USB20_P1 <46> USB20_N2 <46> USB20_P2 <46> USB20_N3 <34> USB20_P3 <34>

USB20_N9 <46> USB20_P9 <46> USB20_N10 <37> USB20_P10 <37> USB20_N11 <44> USB20_P11 <44>

1 2

R242

22.6_0402_1%

USB_OC0# <46>

USB_OC4# <46>

2

LEFT USB

(USB 3.0)

Touch panel

US

B Camera

RIGHT USB

WLAN

D READER

CAR

USB3_RX1_N <46> USB3_RX1_P <46> USB3_TX1_N <46> USB3_TX1_P <46> USB3_RX2_N <46> USB3_RX2_P <46> USB3_TX2_N <46> USB3_TX2_P <46>

CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.

EHCI1

EHC

I2

1

RP14

USB_OC1# USB_OC2# USB_OC5#

USB_OC3#

+3V_PCH

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

6 7 8 9

10

10K_1206_10P8R_5%

Compal Electronics, Inc.

PCH (5/9) PCI, USB

LA-9641P

+3V_PCH

5 4

USB_OC4#

3

USB_OC7#

2

USB_OC6#

1

USB_OC0#

18 61Friday, April 19, 2013

1

18 61Friday, April 19, 2013

1.0

+3V_PCH

S

1 2

GPIO8 Weak internal pull-high but requires an ext

ernal pull down.

D D

C C

B B

1 2

Remove strap description inform SW set GPO

+3V_PCH

1 2

R256 10K_0402_5%@R256 10K_0402_5%@

1 2

R260 1K_0402_5%@R260 1K_0402_5%@

+3VALW

1 2

R266 10K_0402_5%R266 10K_0402_5%

R267 10K_0402_5%@R267 10K_0402_5%@

1 2

+3VS +3VS

12

R270

200K_0402_5%

@

12

R274

R274 10K_0402_5%

10K_0402_5%

BIO

S Request SKU ID

+3VS

12

R278

R277

@

1 2

10K_0402_5%

12

R283

R282

1 2

10K_0402_5%

5

et GPO

W s

R273 10K_0402_5%@ R273 10K_0402_5%@

R261 10K_0402_5%@ R261 10K_0402_5%@

R247 10K_0402_5%@ R247 10K_0402_5%@

PCH_GPIO37 PCH_GPIO36

10K_0402_5%

PCH_GPIO38

PCH_GPIO67

10K_0402_5%

PCH_GPIO24

EC_SCI#

EC_SMI#

PCH_GPIO28

PCH_GPIO27

12

R271

200K_0402_5%

@

12

R275

R275 10K_0402_5%

10K_0402_5%

PCH_GPIO67 <16>

PCH_GPIO38 PCH_GPIO67

*

0

0 1

1

1 1

+3VS

+3V_PCH

EC_LID_OUT#<43>

DGPU_PWROK<55>

PU on power side

SW set GPO

+3VS

+3V_PCH

ODD_EN<41>

Function

0

MUX

LESS

Reserved

0

DIS

UMA

+3VS

INTEL_BT_OFF#<37>

R268 10K_0402_5%@R268 10K_0402_5%@

R272 10K_0402_5%@R272 10K_0402_5%@

ODD_EN

4

SW set GPO

1 2

R248 10K_0402_5%@ R248 10K_0402_5%@

R249 10K_0402_5%@ R249 10K_0402_5%@

1 2

R252 10K_0402_5%@R252 10K_0402_5%@

1 2

R253 1K_0402_5%R253 1K_0402_5%

R259 10K_0402_5%@R259 10K_0402_5%@

1 2

PCH_BT_ON#<37>

1 2

R265 10K_0402_5%

@

1 2

3

LPT_PCH_M_EDS

U4F

PCH_GPIO0

PCH_GPIO1

PCH_GPIO6

EC_SCI#<43>

EC_SMI#<43>

+3VS

EC_SCI#

EC_SMI#

PCH_GPIO12

PCH_GPIO16

PCH_BT_ON#

PCH_GPIO24

PCH_GPIO27

PCH_GPIO28

INTEL_BT_OFF#

PCH_GPIO35

PCH_GPIO36

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO48

PCH_GPIO49

PCH_GPIO57

PCH_GPIO69

PCH_GPIO70

PCH_GPIO71

AT8

BMBUSY#/GPIO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_PWR_CTRL/GPIO12

AB11

GPIO15

AN2

SATA4GP/GPIO16

C14

TACH0/GPIO17

BB4

SCLOCK/GPIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/NMI#

AT3

SATA2GP/GPIO36

AK1

SATA3GP/GPIO37

AT7

SLOAD/GPIO38

AM3

SDATAOUT0/GPIO39

AN4

SDATAOUT1/GPIO48

AK3

SATA5GP/GPIO49

U12

GPIO57

C16

TACH4/GPIO68

D13

TACH5/GPIO69

G13

TACH6/GPIO70

H15

TACH7/GPIO71

BE41

VSS

BE5

VSS

C45

VSS

A5

VSS

12

PCH_GPIO16

R280 10K_0402_5%R280 10K_0402_5%

12

PCH_GPIO49

R281 10K_0402_5%R281 10K_0402_5%

LPMS-QC4C-A1_FCBGA695~D

DH82

LPT_PCH_M_EDS

GPIO

NCTF

6 OF 11

CPU/Misc

PROCPWRGD

THRMTRIP#

PLTRST_PROC#

TP14

PECI

RCIN#

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AN10

AY1

AT6

AV3

AV1

AU4

N10

A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4

GATEA20

PCH_PECI_R

KBRST#

PCH_THRMTRIP#_R

CPU_PLTRST#

1 2

@

R2550_0402_5%@R2550_0402_5%

2

GATEA20 <43>

H_PECI <43,6>

KBRST# <43>

H_CPUPWRGD <6>

CPU_PLTRST# <6>

+1.05VS

1 2

PCH_GPIO69

0 1

PCH_GPIO70

0 1

_GPIO71

PCH

0 1

R258

R258 1K_0402_5%

1K_0402_5%

@

1 2

R262 390_0402_5%R262 390_0402_5%

Need Update

Function

SUN

PRO

XT

Mars

1

H_THRMTRIP# <6>

R276

@R276

@

PCH_GPIO69

R279

@R279

@

MARS@

R286

R288

200K_0402_5%

SUN@

+3VS

1 2

10K_0402_5%

1 2

10K_0402_5%

+3VS +3VS

R287

@R287

@

1 2

PCH_GPIO70PCH_GPIO71

10K_0402_5%

R289

200K_0402_5%

@

1 2

10K_0402_5%

1 2

RP15

A A

5

PCH_GPIO48 INTEL_BT_OFF# GATEA20 KBRST# PCH_GPIO0

+3VS

RP15

6 7 8 9

10

10K_1206_10P8R_5%

5 4

HDD_DET#

3

BBS_BIT0_R

2 1

PCH_BT_ON#

+3VS

HDD_DET# <14> BBS_BIT0_R <14>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (6/9) GPIO, CPU, MISC

Size Document Number Rev

Custom

LA-9641P

Date: S heet of

Date: S heet

2

Date: S heet

1

19 61Friday, April 19, 2013

1.0

of

5

D D

+1.05VS

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

C129

C130

1

2

C C

+1.05VS

22U_0805_6.3V6M

C137

1

2

1U_0402_6.3V6K

C132

C131

1

2

+PCH_VCCDSW

1U_0402_6.3V6K

C138

C139

1

2

AA24 AA26 AD20 AD22 AD24 AD26 AD28 AE18 AE20 AE22 AE24 AE26 AG18 AG20 AG22 AG24

U14

AA18

U18 U20 U22 U24

Y26

V18 V20 V22 V24 Y18 Y20 Y22

U4G

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

DCPSUSBYP VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW

4

Core

DH82

LPMS-QC4C-A1_FCBGA695~D

LPT_PCH_M_EDS

CRT DAC

FDI

HVCMOS

USB3

PCIe/DMI

SATA

VCCMPHY

VCCADACBG3_3

7 OF 11

VCCADAC1_5

VSS

VCCVRM

VCCIO

VCC3_3_R30 VCC3_3_R32

DCPSUS1

VCCSUS3_3 VCCSUS3_3

DCPSUS3 DCPSUS3

VCCIO VCCVRM VCCVRM

VCCVRM

VCCIO

VCCVRM

VCCIO

P45

P43

M31

BB44

AN34

AN35

R30 R32

Y12

+PCH_USB_DCPSUS1

AJ30 AJ32

AJ26

+PCH_USB_DCPSUS3

AJ28 AK20 AK26 AK28

BE22

AK18

AN11

AK22

AM18 AM20 AM22 AP22 AR22 AT22

3

LH1

LH1 1_0603_1%

1_0603_1%

LH1

BLM18PG181SN1_0603

~@

10U_0603_6.3V6M

C133

1

@

2

1

2

0.01U_0402_16V7K

+VCCADAC

1

C126

2

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K C128

C128

1

C127

2

12

+1.5VS

1

PCH Power Rail Table

+3VS

+1.05VS

Voltage Rail

VCC 1.05V 1.29 A

VCCIO 1.05V 3.629 A

VCCADAC1_5

VCCADAC3_3 0.0133 A3.3V

VCCCLK 0.306 A1.05V

VCCCLK3_3 0.055 A

VCCVRM 0.179 A1.5V

VCC3_3 3.3V 0.133 A

VCCASW

VCCSUSHDA 3.3V 0.01 A

VCCSPI 3.3V 0.022 A

+3V_PCH

1

2

+1.05V_+1.5V_RUN

+1.05VS

1U_0402_6.3V6K

C134

1

+3VS

2

0.1U_0402_16V7K

1

0.1U_0402_16V7K

C136

C135

2

+1.05V_+1.5V_RUN

+1.05VS

+1.05V_+1.5V_RUN

VCCSUS3_3 3.3V 0.261 A

1U_0402_6.3V6K

C143

1

2

1U_0402_6.3V6K

C145

C144

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

C147

C146

1

2

VCCDSW3_3 3.3V 0.015 A

V_PROC_IO 1.05V 0.004 A

Voltage S0 Iccmax Current (A)

1.5V 0.070 A

3.3V

1.05V 0.67 A

1 2

B B

A A

5

R290 5.1_0402_1%R290 5.1_0402_1%

+PCH_VCCDSW_R

1U_0402_6.3V6K

C149

1

2

+PCH_VCCDSW

+1.5VS +1.05V_+1.5V_RUN

R291 0_0603_5%R291 0_0603_5%

4

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

2

Date: Sheet of

Title

Size Document Number Rev

Compal Electronics, Inc.

PCH (7/9) PWR

LA-9641P

1

20 61Friday, April 19, 2013

1.0

5

4

3

2

1

+3V_PCH

LPT_PCH_M_EDS

U4H

AF34

AP45

AD34

AA30 AA32

AD35

AG30 AG32

AD36

AE30 AE32

R24 R26 R28 U26

M24

U35

L24

U30

V28 V30 Y30

Y35

Y32

M29

L29

L26

M26

U32

V32

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VSS

VCCUSBPLL

VCC3_3

VCCIO VCCIO VCCIO VCCIO

DCPSUS2

VCCVRM

VCC

VCCCLK

VCCCLK3_3

VCCCLK3_3 VCCCLK3_3

VCCCLK

VCCCLK VCCCLK

VCCCLK

VCCCLK VCCCLK

VCCCLK

VCCCLK VCCCLK

U4H

2LPMS-QC4C-A1_FCBGA695~D

DH8

LH2

1 2

+3V_PCH

0.1U_0402_16V7K

+1.05VS

1

C152

2

+3VS

0.1U_0402_16V7K

1

C153

0.1U_0402_16V7K

2

+1.05VS

1

C157

2

1U_0402_6.3V6K

1

2

+PCH_VCC

+1.05V_+1.5V_RUN

C159

1

2

1

2

10U_0603_6.3V6M

C172

10U_0603_6.3V6M

C140

+PCH_VCCCLK3_3

1U_0402_6.3V6K

C174

1

2

+PCH_USB_DCPSUS2

+PCH_VCC

+PCH_VCCCLK

D D

C C

+1.05VS

4.7UH_LQM18FN4R7M00D_20%

LPT_PCH_M_EDS

USB

1

R20

VCCSUS3_3

R22

8 OF 11

VCCSUS3_3

VCCDSW3_3

DCPSST

VCC3_3 VCC3_3 VCC3_3

VCCIO

VCCSUSHDA

VCCSUS3_3

VCCRTC

DCPRTC DCPRTC

V_PROC_IO V_PROC_IO

VCCSPI

VCCASW

VCCVRM

VCC3_3

A16

+PCH_VCCDSW3_3

AA14

+PCH_VCCSST

+PCH_DCPRTC

+PCH_VPROC

Share ROM

+PCH_VCCCFUSE

C156 0.1U_0402_16V7KC156 0.1U_0402_16V7K

+1.05VS

0.1U_0402_16V7K

+1.05VS

+1.05V_+1.5V_RUN

AE14 AF12 AG14

U36

A26

K8

A6

P14 P16

AJ12 AJ14

AD12

P18

VCC

P20

VCC

L17

R18

AW40

AK30

AK32

GPIO/LPC

Azalia

RTC

CPU

ICC

SPI

Thermal

1 2

C163

1 2

2

+3V_ROM

1

2

+3VS

+PCH_VCCDSW3_3

0.1U_0402_16V7K

C154

0.1U_0402_16V7K

1

C164

2

1U_0402_6.3V6K

C167

1

2

+RTCVCC

0.1U_0402_16V7K

C165

1

2

0.1U_0402_16V7K

1

2

+3V_PCH

1U_0402_6.3V6K

C166

C155

+3V_PCH

1U_0402_6.3V6K

C162

1

2

R307

1 2

0_0402_5%

+3VS

0.1U_0402_16V7K

1

C158

2

0.1U_0402_16V7K

1

C160

2

+3VALW

PCH Power Rail Table

Voltage Rail

VCC 1.05V 1.29 A

VCCIO 1.05V 3.629 A

VCCADAC1_5 1.5V 0.070 A

VCCADAC3_3 0.0133 A3.3V

Voltage S0 Iccmax Current (A)

VCCCLK 0.306 A1.05V

VCCCLK3_3 0.055 A

3.3V

VCCVRM 0.179 A1.5V

VCC3_3

3.3V 0.133 A

VCCASW 1.05V 0.67 A

VCCSUSHDA 3.3V 0.01 A

0_0805_5%

+1.05VS

+PCH_VPROC

0.1U_0402_16V7K

1

C169

0.1U_0402_16V7K

1

C173

2

C169

2

1

C170

2

1 2

R297

1U_0402_6.3V6K

C171

VCCSPI 3.3V 0.022 A

VCCSUS3_3 3.3V 0.261 A

VCCDSW3_3

3.3V 0.015 A

V_PROC_IO 1.05V 0.004 A

Place near pin AP45

+1.05VS

1 2

R300

B B

R300

0_0805_5%

+PCH_VCCCLK

1

2

1U_0402_6.3V6K

C176

1U_0402_6.3V6K

C177

1

2

1U_0402_6.3V6K

C178

1

2

1U_0402_6.3V6K

C180

C179

1

@

2

+PCH_VCCCFUSE

1U_0402_6.3V6K

1

2

C175

R299

1 2

0_0805_5%

+1.05VS

+3VS

R302

1 2

Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36

+PCH_VCCCLK3_3

0_0805_5%

1U_0402_6.3V6K

C181

1

2

1U_0402_6.3V6K

C182

1

2

1U_0402_6.3V6K

C183

1

2

Place near pin AG30,AG32,AE30,AE32

1U_0402_6.3V6K

C184

1

2

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

PCH (8/9) PWR

LA-9641P

1

of

21 61Friday, April 19, 2013

1.0

5

D D

C C

B B

AL34 AL38

AM14 AM24 AM26 AM28 AM30 AM32 AM16

AN36 AN40 AN42

AP13 AP24 AP31 AP43

AK16 AT10 AT15 AT17 AT20 AT26 AT29 AT36 AT38

AV13 AV22 AV24 AV31 AV33 BB25 AV40

AW2

AY10 AY15 AY20 AY26 AY29

AN8

AR2

D42

AV6

AY7

4

U4J

VSS VSS

AL8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F43

VSS VSS VSS VSS VSS VSS VSS

B11

VSS

B15

VSS

DH8

LPT_PCH_M_EDS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

2LPMS-QC4C-A1_FCBGA695~D

10 OF 11

K39 L2 L44 M17 M22 N12 N35 N39 N6 P22 P24 P26 P28 P30 P32 R12 R14 R16 R2 R34 R38 R44 R8 T43 U10 U16 U28 U34 U38 U42 U6 V14 V16 V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36 Y40 Y8

3

U4K

AA16

VSS

AA20

VSS

AA22

VSS

AA28

VSS

AA4

VSS

AB12

VSS

AB34

VSS

AB38

VSS

AB8

VSS

AC2

VSS

AC44

VSS

AD14

VSS

AD16

VSS

AD18

VSS

AD30

VSS

AD32

VSS

AD40

VSS

AD6

VSS

AD8

VSS

AE16

VSS

AE28

VSS

AF38

VSS

AF8

VSS

AG16

VSS

AG2

VSS

AG26

VSS

AG28

VSS

AG44

VSS

AJ16

VSS

AJ18

VSS

AJ20

VSS

AJ22

VSS

AJ24

VSS

AJ34

VSS

AJ38

VSS

AJ6

VSS

AJ8

VSS

AK14

VSS

AK24

VSS

AK43

VSS

AK45

VSS

AL12

VSS

AL2

VSS

BC22

VSS

BB42

VSS

DH8

2LPMS-QC4C-A1_FCBGA695~D

LPT_PCH_M_EDS

11 OF 11

2

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

BA40

VSS

BD11

VSS

BD15

VSS

BD19

VSS

AY36

VSS

AT43

VSS

BD31

VSS

BD35

VSS

BD39

VSS

BD7

VSS

D25

VSS

AV7

VSS

F15

VSS

F20

VSS

F29

VSS

F33

VSS

BC16

VSS

D4

VSS

G2

VSS

G38

VSS

G44

VSS

G8

VSS

H10

VSS

H13

VSS

H17

VSS

H22

VSS

H24

VSS

H26

VSS

H31

VSS

H36

VSS

H40

VSS

H7

VSS

K10

VSS

K15

VSS

K20

VSS

K29

VSS

K33

VSS

BC28

VSS

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (9/9) VSS

LA-9641P

1

22 61Friday, April 19, 2013

1.0

A

B

C

D

E

PCIE_CTX_GRX_P[7..0]<5>

PCIE_CTX_GRX_N[7..0]<5>

1 1

2 2

3 3

CLK_PCIE_VGA<16> CLK_PCIE_VGA#<16>

PCIE_CTX_GRX_P[7..0]

PCIE_CTX_GRX_N[7..0]

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

CLK_PCIE_VGA CLK_PCIE_VGA#

PX@

RV2 1K_0402_5%

GPU_RST#

12

PX@

RV4

RV4 100K_0402_5%

100K_0402_5%

AA38

W36

W38

AB35 AA36

AH16

AA30

Y37

Y35

V37

V35 U36

U38 T37

T35 R36

R38 P37

P35 N36

N38 M37

M35

K37

K35

H37

H35 G36

G38

L36

L38

J36

J38

F37

F35 E37

UV1A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC NC

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

TEST_PG

PERSTB

MARS@

PART 1 0F 9

PCI EXPRESS INTERFACE

MARS-XT M2_FCBGA962

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

Y33

PCIE_CRX_C_GTX_P0

Y32

PCIE_CRX_C_GTX_N0

W33

PCIE_CRX_C_GTX_P1

W32

PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_N1

U33

PCIE_CRX_C_GTX_P2

U32

PCIE_CRX_C_GTX_N2

U30

PCIE_CRX_C_GTX_P3

U29

PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3

T33

PCIE_CRX_C_GTX_P4

T32

PCIE_CRX_C_GTX_N4 PCIE_CRX_GTX_N4

T30

PCIE_CRX_C_GTX_P5

T29

PCIE_CRX_C_GTX_N5 PCIE_CRX_GTX_N5

P33

PCIE_CRX_C_GTX_P6

P32

PCIE_CRX_C_GTX_N6

P30

PCIE_CRX_C_GTX_P7

P29

PCIE_CRX_C_GTX_N7 PCIE_CRX_GTX_N7

N33

NC

N32

NC

N30

NC

N29

NC

L33

NC

L32

NC

L30

NC

L29

NC

K33

NC

K32

NC

J33

NC

J32

NC

K30

NC

K29

NC

H33

NC

H32

NC

Y30

1 2

RV1 1.69K_0402_1%PX@R V1 1.69K_0402_1%PX@

Y29

1 2

RV3 1K_0402_1%PX@RV3 1K_0402_1%PX@

PCIE_CRX_GTX_P[7..0] <5>

PCIE_CRX_GTX_N[7..0] <5>

1 2

CV10.22U_0402_10V6K PX@CV10.22U_0402_ 10V6K PX@

1 2

CV20.22U_0402_10V6K PX@CV20.22U_0402_ 10V6K PX@

1 2

CV30.22U_0402_10V6K PX@CV30.22U_0402_ 10V6K PX@

1 2

CV40.22U_0402_10V6K PX@CV40.22U_0402_ 10V6K PX@

1 2

CV50.22U_0402_10V6K PX@CV50.22U_0402_ 10V6K PX@

1 2

CV60.22U_0402_10V6K PX@CV60.22U_0402_ 10V6K PX@

1 2

CV70.22U_0402_10V6K PX@CV70.22U_0402_ 10V6K PX@

1 2

CV80.22U_0402_10V6K PX@CV80.22U_0402_ 10V6K PX@

1 2

CV90.22U_0402_10V6K PX@CV90.22U_0402_ 10V6K PX@

1 2

CV100.22U_0402_10V6K PX@CV100.22U_0402_10V6K PX@

1 2

CV110.22U_0402_10V6K PX@CV110.22U_0402_10V6K PX@

1 2

CV120.22U_0402_10V6K PX@CV120.22U_0402_10V6K PX@

1 2

CV130.22U_0402_10V6K PX@CV130.22U_0402_10V6K PX@

1 2

CV140.22U_0402_10V6K PX@CV140.22U_0402_10V6K PX@

1 2

CV150.22U_0402_10V6K PX@CV150.22U_0402_10V6K PX@

1 2

CV160.22U_0402_10V6K PX@CV160.22U_0402_10V6K PX@

+0.95VGS

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3

PCIE_CRX_GTX_P4

PCIE_CRX_GTX_P5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7

UV1

SUN@

UV1

SUN@

S IC 216-0841000-00 A0 SUN PRO M2 FCBGA 962P C38

SA00006BA10

DGPU_HOLD_RST#<15>

PLT_RST#<15,37,38,43>

LVDS Interface

UV1D

PART 7 0F 9

RSVD/VARY_BL

RSVD/DIGON

LVDS CONTROL

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

NC#AF35 NC#AG36

LVTMDP

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

NC NC

MARS-XT M2_FCBGA962

MARS@

+3VGS

5

2

P

B

4

Y

1

A

G

PX@

UV2

3

MC74VHC1G08DFT2G SC70 5P

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36 AP37

GPU_RST#

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXTX_M2_PCIE/LVDS

LA-9641P

23 61Friday, April 19, 2013

E

1.0

A

UV1B

MUTI GFX

+VREFG_GPU

PX_EN

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

GPIO_28_FDO

+TSVDD

1

CV32

2

0.1U_0402_16V7K

PX@ CV32

PX@

AD29 AC29

AJ21 AK21

AR10

AW10

AU10 AP10 AV11 AT11 AR12

AW12

AU12 AP12

AJ23 AH23

AK26 AJ26

AH20 AH18 AN16

AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16

AL16 AM16 AM14 AM13

AK14 AG30

AN14 AM17

AL13

AJ14

AK13

AN13

AG32 AG33

AJ19

AK19

AJ20

AK20

AJ24

AH26

AH24

AC30

AK24

AH13

AL21

AD28

AM23

AN23

AK23

AL24 AM24

AF29 AG29

AK32

AL31

AJ32

AJ33

AR8 AU8 AP8

AW8

AR3 AR1 AU1 AU3

AW3

AP6

AW5

AU5 AR6

AW6

AU6 AT7 AV7 AN7 AV9 AT9

GENLK_CLK GENLK_VSYNC

SWAPLOCKA SWAPLOCKB

NC NC DBG_CNTL0 NC NC NC DBG_DATA0 DBG_DATA1 DBG_DATA2 DBG_DATA3 DBG_DATA4 DBG_DATA5 DBG_DATA6 DBG_DATA7 DBG_DATA8 DBG_DATA9 DBG_DATA10 DBG_DATA11 DBG_DATA12 DBG_DATA13 DBG_DATA14 DBG_DATA15 DBG_DATA16 DBG_DATA17 DBG_DATA18 DBG_DATA19 DBG_DATA20 DBG_DATA21 DBG_DATA22 DBG_DATA23

SMBCLK

SMBus

SMBDATA

SCL

I2C

SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2

GPIO_5_AC_BATT GPIO_6_TACH GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB CLKREQB

GPIO_29 GPIO_30

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

CEC_1

HPD1

DBG_VREFG

BACO

PX_EN

DEBUG

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

THERMAL

DPLUS DMINUS

GPIO_28_FDO

TS_A

TSVDD TSVSS

MARS@

GENLK_CLK

T1T1

GENLK_VSYNC

T2T2

1 1

VGA_SMB_CK2 VGA_SMB_DA2

2 2

3 3

+1.8VGS

4 4

TSVDD MarsCR B Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

PX@

RV13 499_0402_1%

PX@

RV14 249_0402_1%

CV23

PX@

GPIO_28_FDO

H

L

REMOTE1+<40> REMOTE1-<40>

GPU_GPIO0<55>

GPU_VID5<55>

GPU_VID1<55>

GPU_VID2<55>

CLK_REQ_VGA#<16>

GPU_VID3<55> GPU_VID4<55>

12

0.1U_0402_16V7K

MLPS

Disable

Enable

ACIN<15,43,48,50>

+VREFG_GPU

LV3

1 2

0_0402_5%

A

DV1

DV1 RB751V_SOD323 @

RB751V_SOD323 @

+3VGS

1 2

RV16 0_0402_5%@RV16 0_0402_5%@

1 2

RV17 0_0402_5%@RV17 0_0402_5%@

+3VGS

RV12 10K_0402_5%@RV12 10K_0402_5%@

0.60 V level, Please VREFG Divider ans cap close to ASIC

RV18 5.11K_0402_5%

RV19 1K_0402_5%

+TSVDD+1.8VGS

GPU_GPIO0

21

GPU_GPIO5 GPU_VID5

GPU_VID1

THM_ALERT#

1 2

GPU_VID2

CLK_REQ_VGA#

GPU_VID3 GPU_VID4

1 2

@

1 2

PX@

THERM_D+ THERM_D-

1 2

@

RV26 10K_0402_5%

1 2

PX@

RV31 10K_0402_5%

(1.8V@13mA TSVDD)

1

CV30

CV31

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@ CV31

PX@

PX@ CV30

PX@

PART 2 0F 9

B

DPA

DPB

DPC

DPD

DAC1

MLPS

DDC/AUX

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

DDCVGACLK

DDCVGADATA

MARS-XT M2_FCBGA962

B

AVSSN

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI

VSS1DI

NC_SVI2 NC_SVI2 NC_SVI2

PS_0

PS_1

PS_2

PS_3

AUX1P AUX1N

AUX2P AUX2N

C

AU24

NC

AV23

NC

AT25

NC

AR24

NC

AU26

NC

AV25

NC

AT27

NC

AR26

NC

AR30

NC

AT29

NC

AV31

NC

AU30

NC

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

VGA_R

R

AD37

AE36

VGA_G

G

AD35

AF37

VGA_B

B

AE38

AC36

HSYNC

AC38

VSYNC

AB34

RV11 499_0402_1%PX@RV11 499_0402_1%PX@

AD34

+AVDD

AE34

AC33

+VDD1DI

AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26

VGA_CLK

AN26

VGA_DAT

AM27 AL27

AM19 AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30 AJ31

T24T24

T25T25

T26T26

T4T4 T6T6

1 2

(1.8V@70mA AVDD)

(1.8V@117mA VDD1DI)

T27T27 T28T28

GPU_GPIO5

THM_ALERT#

1

CV20

2

@ CV20

@

0.1U_0402_16V7K

10K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

1U_0402_6.3V6K

@

RV24

CV21

@ CV21

@

+AVDD

0.1U_0402_16V7K

1

2

+3VGS

STRAPS

RV5 100K_0402_5%@RV5 100K_0402_5%@

RV6 2.2K_0402_5%@RV6 2.2K_0402_5%@

1

CV17

CV18

2

@ CV17

@

@ CV18

@

1U_0402_6.3V6K

1 2

0_0402_5%

1

CV22

2

@ CV22

@

10U_0603_6.3V6M

12

@

RV25

RV25 10K_0402_5%

10K_0402_5%

2N7002DW-T/R7_SOT363-6

C

+3VGS

12

AVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

LV1

1 2

0_0402_5%

1

CV19

2

@ CV19

@

10U_0603_6.3V6M

+1.8VGS+VDD1DI

LV2

VDD1DI MarsC RB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+3VGS

2

61

5

QV3A

@QV3A

@

4

QV3B

2N7002DW-T/R7_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

EC_SMB_CK2 <17,33,40,43>

3

EC_SMB_DA2 <17,33,40,43>

@QV3B

@

Compal Secret Data

2012/07/03 2013/07/03

Compal Secret Data

D

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

TX_PWRS_ENB

TX_DEEMPH_EN

BIF_GEN3_EN_A

BIF_VGA DIS

ROMIDCFG[2:0]

BIOS_ROM_EN PS_2[3]

AUD[1]

AUD[0]

CEC_DIS PS_0[4]

RESERVED PS_1[3]

RESERVED PS_1[2]

RESERVED NA

AUD_PORT_CONN_PINSTRAP[2] PS_3[5]

AUD_PORT_CONN_PINSTRAP[1] PS_3[4]

AUD_PORT_CONN_PINSTRAP[0] PS_0[5]

PS_1[4] 0:50% Tx output sw ing

PS_1[5] 0:Tx de-emphasis disabled

PS_1[1]

PS_2[4]

PS_0[3..1]

NA

DESCRIPTION OF DEFAULT SETTINGSMLPS

Transmitter Power Savings Enable

1:Full Tx output swing

PCIE Transmitter De-emphasis Enable

1:Tx

de-emphasis enabled

PCIE Gen3 Enable (NOTE:RESERVED for Thames/Seymour and should be strapped to 0)

0:GEN3 not support at power-on 1:GEN3 supported at power-on

VGA control

0:VGA controller capacity enabled 1:VGA controller capacity disabled (for multi-GPU)

Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture siz e If PS_2[3]=1, defines ROM type 100 - 512Kbit M25P05A (ST) 101 - 1Mbit M25P10A (ST) 101 - 2Mbit M25P20 (ST) 101 - 4Mbit M25P40 (ST) 101 - 8Mbit M25P80 (ST) 100 - 512Kbit Pm25LV010 (Chingis) 101 - 1Mbit Pm25LV010 (Chingis)

Enable external BIOS ROM device

0:Disabled 1:Enabled

00 - No audio function 01 - Audio for DP only 10 - Audio for DP and HDMI if dongle is detected 11 - Audio for both DP and HDMI

HDMI must only be enabled on systems that are legally entitled. It isthe responsibility of the system designer to ensure that the system is entitled to support this feature.

Reserved for future ASIC

NOTE:ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET

Reserved

Reserved (for Thames/Whistler/Seymour only)

STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS

111 = 0 usable endpoints

= 1 usable endpoints

110 101 = 2 usable endpoints 100 = 3 usable endpoints 011 = 4 usable endpoints 010 = 5 usable endpoints 001 = 6 usable endpoints 000 = all endpoints are usable

MLPS Strap

CapacitorBits[5:4]

Deciphered Date

D

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

PS_0 PS_1 PS_2 PS_3

@

CV26

0.01U_0402_16V7K

Bits[3:1]

000

1 1

0 0 1

01

0 0 0

10

1 1

X X XNCNC

@

1

CV27

2

@

1

CV28

PX@

CV29

2

0.01U_0402_16V7K

0.082U_0402_16V7K

R_pu R_pd

NC 4.75K

8.45K 2K

82 nF

NC

NCX4.75K

12

RV20

X76@ RV20

X76@

8.45K_0402_1%

X76@ RV27

X76@

RV27

8.45K_0402_1%

12

4.75K_0402_1%

PX@RV28

PX@

8.45K_0402_1%

4.75K_0402_1%

Place CLOSE VGA CHIP

Title

ATI_MarsXTX_M2_Main_MSIC

Size Document Number Rev

C

Date: Sheet

Date: Sheet of

E

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

Mapping to VRAM type please refer to page 4

X

12

RV21

@RV21

@

12

RV28

Compal Electronics, Inc.

PX@RV22

PX@

8.45K_0402_1%

RV29

PX@RV29

PX@

2K_0402_1%

RV22

12

8.45K_0402_1%

12

PX@ RV30

PX@

4.75K_0402_1%

@ RV23

@

LA-9641P

E

RV30

RV23

24 61Monday, April 22, 2013

Default Setting

1

0

1

0

000

0

XX

1

0

XXX

+1.8VGS

12

1.0

of

A

MPLL_PVDD MarsCRB Design

1 1

2 2

220ohm 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_PVDD MarsCRB Design 120ohm 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_VDDC MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

1

+1.8VGS

+0.95VGS

B

LV4

1 2

0_0603_5%

LV5

1 2

0_0402_5%

LV6

1 2

0_0402_5%

+MPV18

(MPLL_PVDD:1.8V@130mA )

1

CV34

CV33

2

PX@ CV33

PX@

1U_0402_6.3V6K

PX@ CV34

1U_0402_6.3V6K

PX@

0.1U_0402_16V7K

10U_0603_6.3V6M

+SPV18

(SP

1

CV39

CV38

2

PX@ CV 39

PX@

PX@ CV 38

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

+SPLL_VDDC

(SPLL_VDDC:0.95V@100mA )

1

CV44

CV43

2

PX@ CV44

PX@

PX@ CV43

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

1

CV35

2

PX@ CV35

PX@

LL_PVDD:1.8V@75mA )

1

CV40

2

PX@ CV 40

PX@

1

CV45

2

PX@ CV45

PX@

+MPV18

+SPV18

+SPLL_VDDC

C

AM10

AN9

AN10

AF30 AF31

H7 H8

UV1C

MPLL_PVDD MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD NC_XTAL_PVSS

MARS@

PART 9 0F 9

PLLS/XTAL

MARS-XT M2_FCBGA962

XTALIN

XTALOUT

XO_IN

XO_IN2

CLKTESTA CLKTESTB

AV33

AU34

AW34

AW35

AK10 AL10

XTALIN

XTALOUT

D

12

@

CV41

0.1U_0402_16V7K

12

@

RV33

51.1_0402_1%

12

@

CV42

0.1U_0402_16V7K

12

@

RV34

51.1_0402_1%

PX@

CV36

8.2P_0402_50V8D

1 2

RV32 1M_0402_5%PX@ RV32 1M_0402_5%PX@

YV1

4

NC

OSC

1

2

1

XTALIN

OSC

PX@

NC

27MHZ 10PF +-20PPM X3G027000DA1H

E

3

XTALOUT

2

PX@

CV37

8.2P_0402_50V8D

1

+3VALW

+1.5VS to +1.5VGS Transfer

+1.5VS +1.5VGS

3 3

AO4430: Rdson: 5.5mohm @ VGS=10V

300mil(7.2A) 300

1

CV48

PX@CV48

4.7U_0603_6.3V6K

4 4

PX@

2

+VSB

RV41 240K_0402_5%

QV2

QV2 2N7002_SOT23

2N7002_SOT23

DGPU_PWR_EN#

PX@

2

G

8 7 6 5

12

13

D

1 2

S

PX@

A

AO4304L_SO8

PX@

R02

RV42

@RV42

@

0_0402_5%

UV4

1 2 3

4

1

PX@

CV53

0.1U_0402_25V6

2

PX@

1

CV49

4.7U_0603_6.3V6K

2

mil(7.2A)

@

2N7002_SOT23@G

2N7002_SOT23

B

QV1

D

S

1 2

13

RV39

@RV39

@

470_0603_5%

2

G

DGPU_PWR_EN<15,43,53,55>

DGPU_PWR_EN#

DGPU_PWR_EN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

12

PX@

RV35

RV35 100K_0402_5%

100K_0402_5%

DGPU_PWR_EN#

13

D

PX@

2

QV9

G

2N7002K_SOT23-3

S

Compal Secret Data

2012/07/03 2013/07/03

Compal Secret Data

<+3VS TO +3VGS>

DGPU_PWR_EN

Deciphered Date

+5VALW

RV37

PX@RV37

PX@

20K_0402_5%

D

2

G

+3VS +3VGS

RV38

PX@RV 38

PX@

20K_0402_5%

13

D

PX@

QV6

QV6 2N7002K_SOT23-3

2N7002K_SOT23-3

S

3 1

PX@

QV8

QV8 LP2301ALT1G_SOT23-3

LP2301ALT1G_SOT23-3

2

PX@

1

CV46

4.7U_0603_6.3V6K

2

1

PX@

CV52

0.1U_0402_16V7K

2

Title

ATI_MarsXTX_M2_BACO POWER

Size Document Number Rev

Siz

e Document Number Rev

Custom

Date: Sheet of

Date: Sheet

DGPU_PWR_EN#

Compal Electronics, Inc.

LA-9641P

12

@

RV36

RV36 470_0603_5%

470_0603_5%

13

D

2

G

@

S

QV7

QV7 2N7002K_SOT23-3

2N7002K_SOT23-3

25 61Friday, April 19, 2013

of

25 61Friday, April 19, 2013

of

25 61Friday, April 19, 2013

E

1.0

A

UV1G

PART 6 0F 9

AB39

GND

E39

GND

F34

GND

F39

GND

G33

GND

G34

GND

H31

GND

H34

GND

H39

GND

J31

W31 W34

M34 M39

M17 M22 M24

GND

J34

GND

K31

GND

K34

GND

K39

GND

L31

GND

L34

GND GND GND

N31

GND

N34

GND

P31

GND

P34

GND

P39

GND

R34

GND

T31

GND

T34

GND

T39

GND

U31

GND

U34

GND

V34

GND

V39

GND GND GND

Y34

GND

Y39

GND

F15

GND

F17

GND

F19

GND

F21

GND

F23

GND

F25

GND

F27

GND

F29

GND

F31

GND

F33

GND

F7

GND

F9

GND

G2

GND

G6

GND

H9

GND

J2

GND

J27

GND

J6

GND

J8

GND

K14

GND

K7

GND

L11

GND

L17

GND

L2

GND

L22

GND

L24

GND

L6

GND GND GND GND

N16

GND

N18

GND

N2

GND

N21

GND

N23

GND

N26

GND

N6

GND

R15

GND

R17

GND

R2

GND

R20

GND

R22

GND

R24

GND

R27

GND

R6

GND

T11

GND

T13

GND

T16

GND

T18

GND

T21

GND

T23

GND

T26

GND

U15

GND

U17

GND

U2

GND

U20

GND

U22

GND

U24

GND

U27

GND

U6

GND

V11

GND

V16

GND

V18

GND

V21

GND

V23

GND

V26

GND

W2

GND

W6

GND

Y15

GND

Y17

GND

Y20

GND

Y22

GND

Y24

GND

Y27

GND

MARS@

GND

VSS_MECH VSS_MECH VSS_MECH

MARS-XT M2_FCBGA962

1 1

2 2

3 3

4 4

A

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

NC

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20

AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20

AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

AG22

A39 AW1 AW39

B

MECH#1 MECH#2 MECH#3

B

DP_VDDR MarsCRB Design

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

TV12 PADTV12 PAD TV13 PADTV13 PAD TV14 PADTV14 PAD

RV43

1 2

0_0402_5%

+DP_VDDR

(DP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

_VDDR:1.8V@237mA/link )

+DP_VDDR

1

CV57

2

PX@ CV57

PX@

10U_0603_6.3V6M

RV44 150_0402_1%PX@RV44 150_0402_1%PX@

C

1

CV58

CV59

2

PX@ CV58

PX@

PX@ CV59

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

12

D

UV1F

AN24

NC

AP24

NC

AP25

NC

AP26

NC

AU28

NC

AV29

NC

AP20

NC

AP21

NC

AP22

NC

AP23

NC

AU18

NC

AV19

NC

AH34

DP_VDDR

AJ34

DP_VDDR

AF34

DP_VDDR

AG34

DP_VDDR

AM37

DP_VDDR

AL38

DP_VDDR

AM32

DP_VDDR

AW28

NC

AW18

NC

AM39

DP_CALR

MARS@

2012/07/03 2013/07/03

PART 8 0F 9

DP_VDDR DP_VDDC

DP GND

CALIBRATION

MARS-XT M2_FCBGA962

Compal Secret Data

Deciphered Date

DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC

DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR

D

NC NC NC NC

(DP_VDDC:0.95V@280mA/link )

AP31 AP32 AN33 AP33 AL33 AM33 AK33 AK34 AN31

AP13 AT13 AP14 AP15

AN27 AP27 AP28 AW24 AW26 AN29 AP29 AP30 AW30 AW32 AN17 AP16 AP17 AW14 AW16 AN19 AP18 AP19 AW20 AW22 AN34 AP39 AR39 AU37 AF39 AH39 AK39 AL34 AV27 AR28 AV17 AR18 AN38 AM35 AN32

CV54

1

2

PX@ CV54

PX@

0.1U_0402_16V7K

E

+0.95VGS

1

CV55

CV56

2

PX@ CV55

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

DP_VDDC MarsCRB Design

0.1u 1 1u 1 1 10u 1 1

Compal Electronics, Inc.

Title

Size Document Number Rev

S

ize Document Number Rev

ize Document Number Rev Custom

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

ATI_MarsXTX_M2_PWR_GND

LA-9641P

E

1

26 61Friday, April 19, 2013

of

26 61Friday, April 19, 2013

of

26 61Friday, April 19, 2013

1.0

A

B

C

D

E

UV1E

AD11

AG10

AF26

AF27 AG26 AG27

AF23

AF24 AG23 AG24

AD12

AF11

AF12

AF13

AF15 AG11 AG13 AG15

AF28

AG28

AH29

AC7

AF7

AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10

J7

J9 K11 K13

K8 L12 L16 L21 L23 L26

L7 M11 N11

P7 R11 U11

U7 Y11

Y7

UV1E

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL

TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

I/O

VDDR3 VDDR3 VDDR3 VDDR3

DVP

VDDR4 VDDR4 VDDR4 VDDR4

VOLTAGE

VOLTAGE SENESE

SENESE

FB_VDDC

FB_VDDCI

FB_GND

MARS@

PART 5 0F 9

NC_BIF_VDDC NC_BIF_VDDC

PCIE_PVDD

PCIE

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

BIF_VDDC

BACO

BIF_VDDC

CORE

CORE I/O

ISOLATED

MARS-XT M2_FCBGA962

NC NC NC NC NC NC

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

AA31 AA32 AA33 AA34 W30 Y31 V28 W29 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

N27 T27

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18

AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

+1.5VGS

1

CV66

+

@

1 1

VDDR1 MarsCR B Design

0.01u 5 0

0.1u 5 5 1u 0 5

2.2u 5 0 10u 3 5 220u 0 1

VDD_CT MarsC RB Design 120ohm 1 1

0.1u 1 1 1u 1 3 10u 1 1

VDDR3 MarsCR B Design 120ohm 1 0

2 2

0.1u 1 0 1u 2 3 10u 0 1

VDDR4 MarsCR B Design 220ohm 1 1

0.1u 1 1 1u 1 1 10u 1 0

3 3

2

220U_B2_2.5VM_R35

1

CV68

CV60

CV67

CV69

2

@ CV68

@

@ CV67

@

PX@ CV60

PX@

10U_0603_6.3V6M

PX@ CV69

PX@

10U_0603_6.3V6M

+1.8VGS +VDDC_CT

+3VGS

+1.8VGS

1

CV70

2

@ CV70

@

1U_0402_6.3V6K

LV8

1 2

0_0402_5%

LV9

1 2

0_0402_5%

LV10

1 2

0_0603_5%

1

CV72

CV71

2

PX@ CV72

PX@

PX@ CV71

PX@

1U_0402_6.3V6K

1

CV73

2

PX@ CV73

PX@

1U_0402_6.3V6K

1

CV75

CV76

CV74

2

PX@ CV75

PX@

PX@ CV74

PX@

PX@ CV76

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

(VDD_CT:1.8V@13mA )

1

CV90

CV89

2

@ CV90

@

PX@ CV89

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

+VDDR3

(VDDR3:3.3V@25mA)

1

CV92

CV94

2

PX@ CV92

PX@

PX@ CV94

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

+VDDR4

( VDDR4:1.8V@300mA)

1

CV96

2

PX@ CV96

PX@

1U_0402_6.3V6K

+1.5VGS

1

CV61

CV77

CV79

CV78

2

PX@ CV61

PX@

PX@ CV77

PX@

PX@ CV79

PX@

PX@ CV78

PX@

0.1U_0402_16V7K

1

CV91

2

+VDDC_CT

PX@ CV91

PX@

0.1U_0402_16V7K

+VDDR3

1

CV95

2

PX@ CV95

PX@

+VDDR4

1

CV97

2

PX@ CV97

PX@

0.1U_0402_16V7K

Route as differential pair

VCCSENSE_VGA<55>

VSSSENSE_VGA<55>

TV15TV15

(PCIE_VDDR:1.8V@100mA )

+PCIE_VDDR

1

12

CV63

CV62

2

0.1U_0402_16V7K

PX@ CV63

PX@

PX@ CV62

PX@

1U_0402_6.3V6K

0.01U_0402_16V7K

(PCIE_VDDC:0.95V@2.5A_GEN3.0 )

+0.95VGS

1

CV81

CV80

2

PX@ CV81

PX@

PX@ CV80

PX@

1U_0402_6.3V6K

(BIF_VDDC:0.95V@1.4A)

+0.95VGS

1

CV87

CV86

2

PX@ CV87

PX@

PX@ CV86

PX@

1U_0402_6.3V6K

(VDDCI:0.9~1.15V@8.8A)

1

CV64

2

PX@ CV64

PX@

1

CV82

2

PX@ CV82

PX@

1U_0402_6.3V6K

CV88

PX@

10U_0603_6.3V6M

+PCIE_VDDR

1

CV65

2

PX@ CV65

PX@

10U_0603_6.3V6M

1

CV85

CV84

CV83

2

@ CV84

@

PX@ CV85

PX@

PX@ CV83

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

1

2

LV7

0_0603_5%

+VGA_CORE

12

+1.8VGS

+0.95VGS

PCIE_VDDR Ma rsCRB Design

0.1u 0 2 1u 2 3 10u 1 1

PCIE_VDDC Ma rsCRB Design 1u 7 5 10u 2 1

+VGA_CORE

VGA_CORE Cap in power side sheet

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date:

Compal Electronics, Inc.

ATI_MarsXTX_M2_Power

Friday, April 19, 2013 Sheet

LA-9641P

E

27 61

of

1.0

A

UV1H

PART 3 0F 9

GDDR5/DDR3

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MVREFDA MVREFSA

NC NC NC

MEM_CALRP0

NC NC

MARS@

GDDR5/DDR3

MEMORY INTERFACE A

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0 EDCA0_1/QSA_1 EDCA0_2/QSA_2 EDCA0_3/QSA_3 EDCA1_0/QSA_4 EDCA1_1/QSA_5 EDCA1_2/QSA_6 EDCA1_3/QSA_7

DDBIA0_0/QSA_0B DDBIA0_1/QSA_1B DDBIA0_2/QSA_2B DDBIA0_3/QSA_3B DDBIA1_0/QSA_4B DDBIA1_1/QSA_5B DDBIA1_2/QSA_6B DDBIA1_3/QSA_7B

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA0_8/MAA_13 MAA1_8/MAA_14 MAA0_9/MAA_15

MAA1_9/RSVD

MARS-XT M2_FCBGA962

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

A32 C32 D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27 G27

J14 H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19 M21 M20

C37

MDA0

C35

MDA1

A35

MDA2

E34

MDA3

G32

MDA4

D33

MDA5

F32

MDA6

E32

MDA7

D31

MDA8

F30

MDA9

C30

MDA10

A30

MDA11

F28

MDA12

C28

+VDD_MEM15_REFDA +VDD_MEM15_REFSA

1 2

PX@

MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

AG12

AH12

A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13

J13 H11 G10

G8 K9

K10

G9 A8 C8 E8 A6 C6 E6 A5

L18 L20

L27 N12

M27

M12

1 1

2 2

RV47 120_0402_1%

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 A_BA2 A_BA0

A_BA1

ODTA0 ODTA1

CLKA0 CLKA0#

CLKA1 CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0

CSA1#_0

CKEA0 CKEA1

WEA0# WEA1#

MAA13 MAA14

DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7

QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7

QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7

B

DQMA0 <29> DQMA1 <29> DQMA2 <29> DQMA3 <29> DQMA4 <30> DQMA5 <30> DQMA6 <30> DQMA7 <30>

QSA0 <29> QSA1 <29> QSA2 <29> QSA3 <29> QSA4 <30> QSA5 <30> QSA6 <30> QSA7 <30>

QSA#0 <29> QSA#1 <29> QSA#2 <29> QSA#3 <29> QSA#4 <30> QSA#5 <30> QSA#6 <30> QSA#7 <30>

ODTA0 <29> ODTA1 <30>

CLKA0 <29> CLKA0# <29>

CLKA1 <30> CLKA1# <30>

RASA0# <29> RASA1# <30>

CASA0# <29> CASA1# <30>

CSA0#_0 <29>

CSA1#_0 <30>

CKEA0 <29> CKEA1 <30>

WEA0# <29> WEA1# <30>

C

MDB[0..63]<31,32>

MAA[15..0]

A_BA[2..0]

MDA[0..63]

MAA[15..0] <29,30>

A_BA[2..0] <29,30>

MDA[0..63]<29,30>

MDB[0..63]

MAB[15..0]

B_BA[2..0]

MAB[15..0] <31,32>

B_BA[2..0] <31,32>

+VDD_MEM15_REFDB +VDD_MEM15_REFSB

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

D

AA12

E

UV1I

PART 4 0F 9

GDDR5/DDR3

DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4 DQB0_5 DQB0_6 DQB0_7 DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31 DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8 DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31

MVREFDB MVREFSB

MARS@

GDDR5/DDR3

MEMORY INTERFACE B

MARS-XT M2_FCBGA962

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0 EDCB0_1/QSB_1 EDCB0_2/QSB_2 EDCB0_3/QSB_3 EDCB1_0/QSB_4 EDCB1_1/QSB_5 EDCB1_2/QSB_6 EDCB1_3/QSB_7

DDBIB0_0/QSB_0B DDBIB0_1/QSB_1B DDBIB0_2/QSB_2B DDBIB0_3/QSB_3B DDBIB1_0/QSB_4B DDBIB1_1/QSB_5B DDBIB1_2/QSB_6B DDBIB1_3/QSB_7B

ADBIB0/ODTB0 ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0 CKEB1

WEB0B WEB1B

MAB0_8/MAB_13 MAB1_8/MAB_14 MAB0_9/MAB_15

MAB1_9/RSVD

DRAM_RST

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8 U12 V12

AH11

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 B_BA2 B_BA0 B_BA1

DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7

QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7

QSB#0 QSB#1 QSB#2 QSB#3 QSB#4 QSB#5 QSB#6 QSB#7

ODTB0 ODTB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

CKEB0 CKEB1

WEB0# WEB1#

MAB13 MAB14MAA15 MAB15

DRAM_RST#_R

DQMB0 <31> DQMB1 <31> DQMB2 <31> DQMB3 <31> DQMB4 <32> DQMB5 <32> DQMB6 <32> DQMB7 <32>

QSB0 <31> QSB1 <31> QSB2 <31> QSB3 <31> QSB4 <32> QSB5 <32> QSB6 <32> QSB7 <32>

QSB#0 <31> QSB#1 <31> QSB#2 <31> QSB#3 <31> QSB#4 <32> QSB#5 <32> QSB#6 <32> QSB#7 <32>

ODTB0 <31> ODTB1 <32>

CLKB0 <31> CLKB0# <31>

CLKB1 <32> CLKB1# <32>

RASB0# <31> RASB1# <32>

CASB0# <31> CASB1# <32>

CSB0#_0 <31>

CSB1#_0 <32>

CKEB0 <31> CKEB1 <32>

WEB0# <31> WEB1# <32>

C5 C3 E3 E1

F1 F3

F5 G4 H5 H6

J4 K6 K5

L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5

AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6

AG4

AH5 AH6 AJ4 AK3 AF8

AF9 AG8 AG7

AK9

AL7 AM8 AM7

AK1

AL4 AM6 AM1

AN4

AP3

AP1

AP5

Y12

3 3

Ball to RV57 < 1"

+1.5VGS +1.5VGS

12

RV49

40.2_0402_1%

MARS@

+VDD_MEM15_REFDA DRAM_RST#_R

12

RV55

100_0402_1%

MARS@

4 4

A

1

CV98

CV98 1U_0402_6.3V6K

1U_0402_6.3V6K

2

MARS@

RV50

40.2_0402_1%

RV56

100_0402_1%

12

MARS@

+VDD_MEM15_REFSA +VDD_MEM15_REFSB+VDD_MEM15_REFDB

12

1

CV99

CV99 1U_0402_6.3V6K

MARS@

1U_0402_6.3V6K

2

MARS@

B

CV100 to RV57 < 200 mil CV100 to RV53 < 1"

1 2

PX@

DRAM_RST#<29,30,31,32>

DRAM_RST# is a daisy-chain ne t that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec. Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except Rser2

PX@

RV53 51.1_0402_1%

+1.5VGS

12

RV48

4.7K_0402_5%

@

1 2

PX@

RV54 10_0402_5%

12

CV100

120P_0402_50V9

PX@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C

RV57

4.99K_0402_1%

PX@

1 2

Compal Secret Data

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

D

+1.5VGS +1.5VGS

RV51

40.2_0402_1%

PX@

RV58

100_0402_1%

PX@

12

1

CV101

CV101 1U_0402_6.3V6K

1U_0402_6.3V6K

2

PX@

Title

Size Document Number Rev

C

Date:

12

RV52

40.2_0402_1%

PX@

12

RV59

100_0402_1%

PX@

Friday, April 19, 2013 Sheet

1

2

Compal Electronics, Inc.

ATI_MarsXTX_M2_MEM IF

LA-9641P

E

CV102

CV102 1U_0402_6.3V6K

1U_0402_6.3V6K

PX@

28 61

of

1.0

5

D D

C C

B B

MDA[0..31]<28>

MAA[15..0]<28,30>

CLKA0

RV60 40.2_0402_1%

CLKA0#

RV61 40.2_0402_1%

1 2

MARS@

1 2

MARS@

MDA[0..31]

MAA[15..0]

12

CV195

0.01U_0402_16V7K

MARS@

4

UV5

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 MAA15

QSA2 QSA0

DQMA2 DQMA0

QSA#2 QSA#0

12

4.99K_0402_1%

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

+1.5VGS

12

MARS@

RV62

+VREFC_A0

A_BA0<28,30> A_BA1<28,30> A_BA2<28,30>

CLKA0<28> CLKA0#<28> CKEA0<28>

ODTA0<28> CSA0#_0<28> RASA0#<28> CASA0#<28> WEA0#<28>

QSA2<28> QSA0<28>

DQMA2<28> DQMA0<28>

QSA#2<28> QSA#0<28>

DRAM_RST#<28,30,31,32>

RV84

RV84 240_0402_1%

240_0402_1%

MARS@

15mil

CV103

0.1U_0402_16V7K

CV103

0.1U_0402_16V7K

12

MARS@

RV64

4.99K_0402_1%

+VREFC_A0

12

MARS@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDA23

F7

MDA19

F2

MDA22

F8

MDA18

H3

MDA21

H8

MDA17

G2

MDA20

H7

MDA16

D7

MDA0

C3

MDA5

C8

MDA1

C2

MDA6

A7

MDA3

A2

MDA4

B8

MDA2

A3

MDA7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.5VGS

3

QSA3<28> QSA1<28>

DQMA3<28> DQMA1<28>

QSA#3<28> QSA#1<28>

RV85

RV85 240_0402_1%

240_0402_1%

MARS@

+VREFC_A1

12

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 MAA15

A_BA0 A_BA1 A_BA2

CLKA0 CLKA0# CKEA0

ODTA0 CSA0#_0 RASA0# CASA0# WEA0#

QSA3 QSA1

DQMA3 DQMA1

QSA#3 QSA#1

DRAM_RST#

4.99K_0402_1%

UV6

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

+1.5VGS

12

MARS@

RV63

15mil

CV104

0.1U_0402_16V7K

CV104

0.1U_0402_16V7K

12

MARS@

RV65

12

MARS@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+VREFC_A1

2

E3

MDA24

F7

MDA30

F2

MDA27

F8

MDA29

H3

MDA25

H8

MDA28

G2

MDA26

H7

MDA31

D7

MDA12

C3

MDA10

C8

MDA14

C2

MDA11

A7

MDA13

A2

MDA9

B8

MDA15

A3

MDA8

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

+1.5VGS

CV113

1U_0402_6.3V6K

CV107

1U_0402_6.3V6K

CV109

1U_0402_6.3V6K

CV108

1U_0402_6.3V6K

CV105

10U_0603_6.3V6M

1

MARS@CV105

MARS@

2

A A

5

1U_0402_6.3V6K

CV106

1U_0402_6.3V6K

1

MARS@CV107

MARS@

MARS@CV109

MARS@

MARS@CV108

MARS@

MARS@CV106

MARS@

2

4

1U_0402_6.3V6K

CV112

1U_0402_6.3V6K

1

MARS@CV113

MARS@

MARS@CV112

MARS@

2

+1.5VGS

CV115

10U_0603_6.3V6M

@CV115

@

+1.5VGS

CV118

1U_0402_6.3V6K

CV119

1U_0402_6.3V6K

CV121

1U_0402_6.3V6K

CV122

1U_0402_6.3V6K

CV120

1U_0402_6.3V6K

CV117

1U_0402_6.3V6K

CV116

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

MARS@CV117

MARS@

MARS@CV116

MARS@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN

AN DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1U_0402_6.3V6K

1

MARS@CV118

MARS@

MARS@CV119

MARS@

MARS@CV120

MARS@

2

1U_0402_6.3V6K

1

2

2010/08/25 2012/08/25

1

MARS@CV121

MARS@

MARS@CV122

MARS@

2

CV125

0.1U_0402_16V7K

CV124

0.1U_0402_16V7K

1

@CV125

@

@CV124

@

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_A

Size Document Number Rev

C

LA-9641P

Date: Sheet of

2

Date: Sheet of

1

29 61Friday, April 19, 2013

1.0

5

D D

MDA[32..63]<28>

MAA[15..0]<28,29>

C C

MDA[32..63]

MAA[15..0]

DRAM_RST#<28,29,31,32>

4

QSA4<28> QSA5<28>

DQMA4<28> DQMA5<28>

QSA#4<28> QSA#5<28>

3

UV7

M8

VREFCA

H1

VREFDQ

N3

MAA0

A0

P7

A1

P3

MAA2

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

MAA10

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

MAA15

A15/BA3

M2

A_BA0

QSA4 QSA5 QSA6

DQMA4 DQMA5 DQMA6

QSA#4 QSA#5 QSA#6

DRAM_RST#

12

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

A_BA0<28,29> A_BA1<28,29> A_BA2<28,29>

RV86

RV86 240_0402_1%

240_0402_1%

MARS@

+VREFC_A2

CLKA1<28> CLKA1#<28> CKEA1<28>

ODTA1<28> CSA1#_0<28> RASA1#<28> CASA1#<28> WEA1#<28>

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDA38

F7

MDA36

F2

MDA39

F8

MDA34

H3

MDA35

H8

MDA33

G2

MDA37

H7

MDA32

D7

MDA42

C3

MDA44

C8

MDA40

C2

MDA46

A7

MDA43 MDA56

A2

MDA45

B8

MDA41

A3

MDA47

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

QSA6<28> QSA7<28>

DQMA6<28> DQMA7<28>

QSA#6<28> QSA#7<28>

RV87

RV87 240_0402_1%

240_0402_1%

MARS@

+VREFC_A3

12

MAA0MAA1 MAA1 MAA2MAA3 MAA3MAA4 MAA4MAA5 MAA5MAA6 MAA6MAA7 MAA7MAA8 MAA8MAA9 MAA9 MAA10MAA11 MAA11MAA12 MAA12MAA13 MAA13MAA14 MAA14 MAA15

A_BA0A_BA1 A_BA1A_BA2 A_BA2

CLKA1 CLKA1# CKEA1

ODTA1 CSA1#_0 RASA1# CASA1# WEA1#

QSA7

DQMA7

QSA#7

DRAM_RST#

2

UV8

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

E3

MDA49

F7

MDA51

F2

MDA48

F8

MDA52

H3

MDA50

H8

MDA53

G2

MDA55

H7

MDA54

D7

MDA60

C3

MDA57

C8

MDA63

C2 A7

MDA61

A2

MDA59

B8

MDA62

A3

MDA58

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

B B

1 2

CLKA1

MARS@

RV66 40.2_0402_1%

1 2

CLKA1#

MARS@

RV69 40.2_0402_1%

A A

5

12

CV196

0.01U_0402_16V7K

MARS@

+1.5VGS

CV128

10U_0603_6.3V6M

4

CV130

0.1U_0402_16V7K

CV129

1U_0402_6.3V6K

1

MARS@CV128

MARS@

@CV130

@

MARS@CV129

MARS@

2

4.99K_0402_1%

CV132

1U_0402_6.3V6K

1

MARS@CV132

MARS@

2

MARS@

RV68

MARS@

RV71

+1.5VGS

12

15mil

0.1U_0402_16V7K

CV134

0.1U_0402_16V7K

1

@CV134

@

2

CV127

1U_0402_6.3V6K

12

CV135

1

MARS@CV135

MARS@

2

+VREFC_A2

MARS@

CV136

1U_0402_6.3V6K

1

MARS@CV136

MARS@

2

+1.5VGS

CV138

10U_0603_6.3V6M

1

@CV138

@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN

AN DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.5VGS

CV139

10U_0603_6.3V6M

MARS@CV139

MARS@

1

2

+1.5VGS

12

MARS@

RV67

4.99K_0402_1%

15mil

+VREFC_A3

CV126

0.1U_0402_16V7K

CV126

0.1U_0402_16V7K

12

MARS@

RV70

CV141

1U_0402_6.3V6K

MARS@CV141

MARS@

2010/08/25 2012/08/25

1

2

12

MARS@

CV144

1U_0402_6.3V6K

CV145

1U_0402_6.3V6K

1

MARS@CV144

MARS@

MARS@CV145

MARS@

2

Compal Secret Data

Deciphered Date

2

CV148

1U_0402_6.3V6K

CV147

0.1U_0402_16V7K

CV146

1

MARS@CV148

MARS@

@CV147

@

MARS@CV146

MARS@

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_A

Size Document Number Rev

C

LA-9641P

Date: Sheet of

1

30 61Friday, April 19, 2013

1.0

5

D D

MDB[0..31]<28>

MAB[15..0]<28,32>

C C

CLKB0

RV72 40.2_0402_1%

CLKB0#

RV73 40.2_0402_1%

1 2

PX@

1 2

PX@

MDB[0..31]

MAB[15..0]

12

CV197

0.01U_0402_16V7K

PX@

4

UV9

M8 H1

N3

MAB0

P7

MAB1

P3

MAB2

N2

MAB3

P8

MAB4

P2

MAB5

R8

MAB6

R2

MAB7

T8

MAB8

R3

MAB9

L7

MAB10 MAB10

R7

MAB11

N7

MAB12

T3

MAB13

T7

MAB14

M7

MAB15 MAB15

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3

QSB2

C7

QSB0 QSB1

E7

DQMB2 DQMB3

D3

DQMB0 DQMB1

G3

QSB#2 QSB#3

B7

QSB#0 QSB#1

T2

L8

12

J1

L1

J9

L9

K4W1G1646E-HC12_FBGA96

X76@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

QSB2<28> QSB0<28>

DQMB2<28> DQMB0<28>

QSB#2<28> QSB#0<28>

RV88

RV88 240_0402_1%

240_0402_1%

CLKB0<28> CLKB0#<28> CKEB0<28>

DRAM_RST#<28,29,30,32>

PX@

+VREFC_B0

B_BA0<28,32> B_BA1<28,32> B_BA2<28,32>

ODTB0<28> CSB0#_0<28> RASB0#<28> CASB0#<28> WEB0#<28>

3

UV10

B_BA0 B_BA1 B_BA2

CLKB0 CLKB0# CKEB0

ODTB0 CSB0#_0 RASB0# CASB0# WEB0#

QSB3

DRAM_RST#

12

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9

MAB11 MAB12 MAB13 MAB14

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3

MDB19

F7

MDB20

F2

MDB22

F8

MDB16

H3

MDB23

H8

MDB17

G2

MDB21

H7

MDB18

D7

MDB0

C3

MDB4

C8

MDB1

C2

MDB6

A7

MDB3

A2

MDB7

B8

MDB2

A3

MDB5

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

QSB3<28> QSB1<28>

DQMB3<28> DQMB1<28>

QSB#3<28> QSB#1<28>

RV89

RV89 240_0402_1%

240_0402_1%

PX@

+VREFC_B1

2

E3

MDB26

F7

MDB30

F2

MDB24

F8

MDB29

H3

MDB27

H8

MDB28

G2

MDB25

H7

MDB31

D7

MDB15

C3

MDB10

C8

MDB14

C2

MDB11

A7

MDB12

A2

MDB9

B8

MDB13

A3

MDB8

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

+1.5VGS

12

PX@

RV74

4.99K_0402_1%

B B

+1.5VGS

CV154

1U_0402_6.3V6K

CV156

1U_0402_6.3V6K

CV152

1U_0402_6.3V6K

1

PX@CV152

PX@

2

A A

5

1U_0402_6.3V6K

CV155

1U_0402_6.3V6K

1

PX@CV154

PX@

PX@CV156

PX@

PX@CV155

PX@

2

4.99K_0402_1%

CV158

0.1U_0402_16V7K

CV159

0.1U_0402_16V7K

1

@CV158

@

@CV159

@

2

4

15mil

+VREFC_B0

CV149

0.1U_0402_16V7K

CV149

0.1U_0402_16V7K

12

PX@

12

RV76

CV160

1

@CV160

@

2

+1.5VGS

CV161

10U_0603_6.3V6M

@CV161

@

PX@

+1.5VGS

CV162

10U_0603_6.3V6M

1

2

1

PX@CV162

PX@

2

CV165

1U_0402_6.3V6K

CV166

1U_0402_6.3V6K

CV167

1U_0402_6.3V6K

CV164

1U_0402_6.3V6K

PX@CV164

PX@

1U_0402_6.3V6K

1

2

1

PX@CV165

PX@

PX@CV166

PX@

PX@CV167

PX@

2

3

+1.5VGS

12

PX@

RV75

4.99K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN

AN DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

15mil

+VREFC_B1

CV150

0.1U_0402_16V7K

CV150

0.1U_0402_16V7K

12

PX@

12

RV77

0.1U_0402_16V7K

CV168

0.1U_0402_16V7K

1

@CV168

@

2

PX@

CV170

0.1U_0402_16V7K

CV171

0.1U_0402_16V7K

CV169

1

@CV170

@

@CV171

@

@CV169

@

2

Compal Secret Data

2010/08/25 2012/08/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_B

Size Document Number Rev

C

LA-9641P

Date: Sheet of

1

31 61Friday, April 19, 2013

1.0

5

D D

C C

MDB[32..63]<28>

MAB[15..0]<28,31>

MDB[32..63]

MAB[15..0]

DRAM_RST#<28,29,30,31>

4

B_BA0<28,31> B_BA1<28,31> B_BA2<28,31>

QSB4<28> QSB5<28>

DQMB4<28> DQMB5<28>

QSB#4<28> QSB#5<28>

RV90

RV90 240_0402_1%

240_0402_1%

PX@

3

UV11

+VREFC_B2

CLKB1<28> CLKB1#<28> CKEB1<28>

ODTB1<28> CSB1#_0<28> RASB1#<28> CASB1#<28> WEB1#<28>

M8

VREFCA

H1

VREFDQ

N3

MAB0 MAB0

A0

P7

MAB1 MAB1

A1

P3

MAB2 MAB2

A2

N2

MAB3 MAB3

A3

P8

MAB4 MAB4

A4

P2

MAB5 MAB5

A5

R8

MAB6 MAB6

A6

R2

MAB7 MAB7

A7

T8

MAB8 MAB8

A8

R3

MAB9 MAB9

A9

L7

MAB10 MAB10

A10/AP

R7

MAB11

A11

N7

MAB12 MAB12

A12

T3

MAB13 MAB13

A13

T7

MAB14 MAB14

A14

M7

MAB15 MAB15

A15/BA3

M2

B_BA0 B_BA1 B_BA2

QSB4 QSB5

DQMB4 DQMB5

QSB#4 QSB#5

DRAM_RST# DRAM_RST#

12

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDB33

F7

MDB37

F2

MDB35

F8

MDB39

H3

MDB32

H8

MDB36

G2

MDB34

H7

MDB38

D7

MDB44

C3

MDB41

C8

MDB47

C2

MDB43

A7

MDB45

A2

MDB40

B8

MDB46

A3

MDB42

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

QSB6<28> QSB7<28>

DQMB6<28> DQMB7<28>

QSB#6<28> QSB#7<28>

RV91

RV91 240_0402_1%

240_0402_1%

PX@

+VREFC_B3

12

B_BA0 B_BA1 B_BA2

CLKB1 CLKB1# CKEB1

ODTB1 CSB1#_0 RASB1# CASB1# WEB1#

QSB6 QSB7

DQMB6 DQMB7

QSB#6 QSB#7

MAB11

UV12

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

E3

MDB55

F7

MDB50

F2

MDB54

F8

MDB51

H3

MDB53

H8

MDB49

G2

MDB52

H7

MDB48

D7

MDB56

C3

MDB59

C8

MDB63

C2

MDB62

A7

MDB57

A2

MDB61

B8

MDB58

A3

MDB60

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

4.99K_0402_1%

+1.5VGS

CV184

10U_0603_6.3V6M

1

@CV184

@

2

+1.5VGS

12

PX@

RV78

15mil

+VREFC_B3

CV172

0.1U_0402_16V7K

CV172

0.1U_0402_16V7K

12

PX@

RV82

3

12

PX@

CV190

1U_0402_6.3V6K

CV186

1U_0402_6.3V6K

CV187

1U_0402_6.3V6K

CV185

10U_0603_6.3V6M

1

PX@CV186

PX@

PX@CV187

PX@

PX@CV185

PX@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN

AN DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1U_0402_6.3V6K

CV189

1U_0402_6.3V6K

CV188

1U_0402_6.3V6K

1

2

1

PX@CV190

PX@

PX@CV189

PX@

PX@CV188

PX@

2

2010/08/25 2012/08/25

0.1U_0402_16V7K

CV191

0.1U_0402_16V7K

CV192

0.1U_0402_16V7K

1

@CV191

@

@CV192

@

2

Compal Secret Data

CV193

CV194

0.1U_0402_16V7K

1

@CV193

@

@CV194

@

2

Deciphered Date

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_A

Size Document Number Rev

C

LA-9641P

Date: Sheet of

1

32 61Friday, April 19, 2013

1.0

+1.5VGS

1 2

CLKB1

PX@

RV79 40.2_0402_1%

1 2

CLKB1#

PX@

RV81 40.2_0402_1%

B B

A A

RV81 40.2_0402_1%

5

12

CV198

0.01U_0402_16V7K

PX@

12

PX@

RV80

4.99K_0402_1%

+1.5VGS +1.5VGS

CV174

10U_0603_6.3V6M

PX@CV174

PX@

15mil

+VREFC_B2

CV173

0.1U_0402_16V7K

CV173

0.1U_0402_16V7K

12

PX@

12

RV83

CV175

1U_0402_6.3V6K

1

PX@CV175

PX@

2

4

PX@

CV176

1U_0402_6.3V6K

CV178

1U_0402_6.3V6K

CV177

1U_0402_6.3V6K

CV179

1U_0402_6.3V6K

1

PX@CV176

PX@

PX@CV178

PX@

PX@CV177

PX@

PX@CV179

2

PX@

2

CV181

0.1U_0402_16V7K

CV183

1U_0402_6.3V6K

1

@CV181

@

PX@CV183

PX@

2

5

4

3

2

1

+3VS +3VS_PS

80mil 80mil

1 2

RT1 0_0805_5%RT1 0_0805_5%

1 2

@

R551 0_0805_5%

Close to Pin3

10U_0603_6.3V6M

0.1U_0402_16V7K

D D

1

CT1

2

0.1U_0402_16V7K

1

CT2

2

Close to pin11

10U_0603_6.3V6M

0.1U_0402_16V7K

1

CT4

2

10U_0603_6.3V6M

1

CT5

2

+DP_V33

1

CT3

2

EDP_CPU_AUX<8>

Close to Pin18

+SWR_VDD

0.1U_0402_16V7K

1

CT6

2

0.1U_0402_16V7K

1

2

1

CT8

CT7

CT8

2

EDP_CPU_AUX#<8>

EDP_CPU_LANE_P0<8> EDP_CPU_LANE_N0<8>

Close to Pin13

Close to LT3

C C

0.1U_0402_16V7K

10U_0603_6.3V6M

1

CT9

2

B B

0.1U_0402_16V7K

1

2

1

CT10

2

Close to Pin27

CT11

0.1U_0402_16V7K

1

CT12

2

Close to Pin7

+SWR_V12

RTD2132R LDO MODE

+SWR_LX+SW R_V12

+3VS_PS

1 2

C190 0.1U_0402_16V 7KC190 0.1U_0402_16V7K

1 2

C191 0.1U_0402_16V 7KC191 0.1U_0402_16V7K

1 2

C192 0.1U_0402_16V 7KC192 0.1U_0402_16V7K

1 2

C193 0.1U_0402_16V 7KC193 0.1U_0402_16V7K

EC_SMB_CK2<17,24,40,43> EC_SMB_DA2<17,24,40,43>

TL_HPD<8>

12

LT1

LT1 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

LT2

LT2 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1 2

LT3

~@ LT3

~@

4.7UH_PG031B-4R7MS_1.1A_20%

+DP_V33

12

+SWR_VDD

+SWR_LX+SWR_V12

EDP_CPU_AUX_R EDP_CPU_AUX#_R

EDP_CPU_LANE_P0_R EDP_CPU_LANE_N0_R

RT8

12K_0402_1%

UT2

3

40mil

DP_V33

13

60mil

SWR_VDD

18

PVCC

12

20mil

SWR_LX

11

60mil60mil

SWR_VCCK

27

VCCK

7

DP_V12

2

AUX_P

1

AUX_N

5

LANE0P

6

LANE0N

9

CIICSCL1

10

CIICSDA1

32

HPD

8

DP_REXT

4

DP_GND

1 2

Power

LVDS

RTD2132S

DP-IN

GPIO(PWM OUT)

GPIO(Panel_VCC)

GPIO(PWM IN)

GPIO

GPIO(BL_EN)

LVDS

Other

EDID

ROM

RTD2132R-VE-CG_QFN32_5X5

R438

100K_0402_5%

1 2

TXEC+

TXEC-

TXE2+

TXE2-

TXE1+

TXE1-

TXE0+

TXE0-

MIICSCL1

MIICDA1

MIICSCL0 MIICSDA0

GND

ENBKL

19 20

21 22

23 24

25 26

14 15 16 17

29 28

31

MIIC_SCL

30

MIIC_SDA

33

LVDS_ACLK <34> LVDS_ACLK# <34>

LVDS_A2 <34> LVDS_A2# <34>

LVDS_A1 <34> LVDS_A1# <34>

LVDS_A0 <34> LVDS_A0# <34>

TL_ENVDD need 60 mil if use for LVDS power on R version

TL_INVT_PWM <34>

TL_ENVDD <34>

PCH_PWM <15>

ENBKL <43>

EDID_CLK <34> EDID_DATA <34>

ADD TP on trace or via

MIIC_SCL

+3VS_PS

1 2

RT4

4.7K_0402_5%

EDID_DATA

EDID_CLK

MIIC_SDA

RT9 4.7K_0402_5%RT9 4.7K_0402_5%

RT10 4.7K_0402_5%RT10 4.7K_0402_5%

1 2

RT12

4.7K_0402_5%

1 2

+3VS_PS

MI

MIIC_SCL

IC_SDA

0

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/30 2013/06/30

Compal Secret Data

Deciphered Date

2

0 1

X

Internal ROM

EC CODE

EEPROM

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

LVDS Translator - RTD2132S

LA-9641P

1

33 61Friday, April 19, 2013

1.0

5

4

3

2

1

LCD POWER CIRCUIT

+3VS +LCDVDD_C ONN

D D

W=60mils W=60mils

U72

@U72

@ C4

@

1500P_0402_50V7K

@

5

VIN

4

1

C4

2

SS

APL3512ABI-TRG_SOT23-5

TL_ENVDD<33>

+LCDVDD_C ONN

VOUT

GND

EN

1

+LCDVDD_C ONN

2

3

W=60mils

TL_ENVDD

1 2

@

R553 0_0805_5%

1

C516

2

4.7U_0603_6.3V6K

R408

100K_0402_5%

CMOS_ON#<43>

12

+3VS

CMOS@

150K_0402_5%

R435

CMOS@

1

C520

CMOS@C520

CMOS@

0.1U_0402_16V7K

2

(20 MIL)

S

CMOS Camera

Q83

Q83 LP2301ALT1G_SOT23-3

LP2301ALT1G_SOT23-3

D

13

G

2

+3VS_CMOS

)

(20 MIL

R02

R296 for CMOS shake issue reserve

10U

1

C519 10U_0603_6.3V6M

10U_0603_6.3V6M

2

@C519

@

VGA LCD/PANEL BD. Conn.

C C

B B

A A

RTD2132R Internal load switch for +LCD_VCC

BKOFF#

12

R716

R716 10K_0402_5%

10K_0402_5%

TL_INVT_PWM<33>

+3VS

1 2

R441 0_0402_5%R441 0_0402_5%

USB20_P3 USB20_N3

USB20_P3<18> USB20_N3<18>

CMOS

B++LEDVDD

1 2

R813

1

@

C541

4.7U_0805_25V6-K

2

JLVDS1

1

2

3

4

BKOFF#<43>

INVT_PWM

LVDS_ACLK<33> LVDS_ACLK#<33>

12

R6880_0402_5% R6880_0402_5%

12

R6840_0402_5% R6840_0402_5%

4

1

L58

WCM- 2012-900T_4P

~@

R39 0_0402_5%@R39 0_0402_5%@

LVDS_A2<33> LVDS_A2#<33> LVDS_A1<33> LVDS_A1#<33> LVDS_A0<33> LVDS_A0#<33>

EDID_DATA<33> EDID_CLK<33>

+LCDVDD_C ONN

+3VS_CMOS

3

USB20_P3_R

3

2

USB20_N3_R

2

1 2

+3VS

BKOFF#

(60 MIL)

USB20_P3_R

USB20_N3_R

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_88341-3001 ME@

31

G1

32

G2

33

G3

34

G4

0_0805_5%

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Docume nt Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LVDS/CAMERA

LA-9641P

34 61Friday, April 19, 2013

1

1.0

A

B

C

D

E

1 1

FCM1608 CF-121T03 0603

1

C523

2

10P_0402_50V8J

1 2

L30

FCM1608 CF-121T03 0603

1 2

L31

FCM1608 CF-121T03 0603

1 2

L32

1

C524

2

BYP

VIDEO1

VIDEO2

VIDEO3

DDC_OUT1

DDC_OUT2

SYNC_OUT1

SYNC_OUT2

1

C525

2

10P_0402_50V8J

1 2

8

C6 0.22U_04 02_10V6KC6 0.22U_04 02_10V6K

3

RED

4

GREEN

5

BLUE

9

CRT_DDC _DAT_CONN

12

CRT_DDC _CLK_CONN

14

JVGA_VS

16

JVGA_HS

C526

10P_0402_50V8J

DAC_RED<15>

DAC_GRN<15>

DAC_BLU<15>

RP22

4 5 3 6 2 7 1 8

150_080 4_8P4R_5%

2 2

+5VS

1

C529

0.1U_040 2_16V7K

3 3

1

2

C537

0.1U_040 2_16V7K

C531

0.1U_040 2_16V7K

+3VS

DAC_BLU DAC_GRN DAC_RED

@C5 31

@

1

2

CRT_DDC _DATA<1 5>

CRT_DDC _CLK<15>

CRT_VSYNC<15>

CRT_HSYNC< 15>

1

C522

2

10P_0402_50V8J

U10

1

VCC_SYNC

2

VCC_VIDEO

7

VCC_DDC

10

DDC_IN1

11

DDC_IN2

13

SYNC_IN1

15

SYNC_IN2

6

GND

TPD7S01 9-15DBQR_SSOP 16

1

2

10P_0402_50V8J

1 2

R411

22_0402 _5%

1 2

R412

22_0402 _5%

RED

GREEN

BLUE

1

C527

2

4.7K_040 2_5%

12

R31

JVGA_VS _R

JVGA_HS _R

T66PAD T66PAD

+5V_Display

1

C411

2

@

12

R33

4.7K_040 2_5%

@

10P_0402_50V8J

C412

NC11 RED

CRT_DDC _DAT_CONN GREEN

JVGA_HS _R BLUE

JVGA_VS _R

CRT_DDC _CLK_CONN

1

2

10P_0402_50V8J

CRT Connector

+5V_Display

CONTE_8 0431-5K1-152

JCRT1

ME@

JCRT1

ME@

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

16

G

17

G

4 4

Security Class ification

2011/06/ 15 2012/07/ 11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/ 15 2012/07/ 11

Compal Secret Data

C

Deciphered Date

Compal Electronics, Inc.

Title

Size Do cument Number Rev

Date: Sheet o f

D

Date: Sheet o f

Compal Electronics, Inc.

CRT Connector

Custom

LA-9641P

35 61Friday, April 19, 2013

E

1.0

5

4

3

2

1

U73

+5VS

L35

HDMI@L35

HDMI@

HDMICLK_R

1

4

WCM-2012HS-900T

L36

1

4

WCM-2012HS-900T

L37

1

4

WCM-2012HS-900T

L38

1

4

WCM-2012HS-900T

+3VS

4

HDMI_CLK+_CK<8>

D D

HDMI_CLK-_CK<8>

HDMI_TX0+_CK<8>

HDMI_TX0-_CK<8 >

HDMI_TX1+_CK<8>

HDMI_TX1-_CK<8 >

HDMI_TX2+_CK<8>

C C

HDMI_TX2-_CK<8 >

HDMICLK_NB<15>

HDMIDAT_NB<15>

B B

9

10

HDMIDAT_R

HDMI_DET HDMI_DET

A A

8

9

7

6

6 5

YSCLAMP0524P_SLP2510P8-10-9

HDMI_CLK+_CK

HDMI_CLK-_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_TX1+_CK

HDMI_TX1-_CK

HDMI_TX2-_CK HDMI_TX2-_CONN

D32

@

1

2

HDMIDAT_R HD MI_TX1-_CONN

2

4

5

3

8

2

HDMI_CLK+_CONN

2

3

HDMI_CLK-_CONN

3

HDMI@L36

HDMI@

2

HDMI_TX0+_CONN

2

3

HDMI_TX0-_CONN

3

HDMI@L37

HDMI@

2

HDMI_TX1+_CONN

2

3

HDMI_TX1-_CONN

3

HDMI@L38

HDMI@

2

HDMI_TX2+_CONNHDMI_TX2+_CK

2

3

Q63A

HDMI@

2

2N7002DW-T /R7_SOT363-6

5

3

Q63B

HDMI@

2N7002DW-T /R7_SOT363-6

HDMI_TX1+_CONNHDMICLK_R

HDMI_TX1-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN

YSCLAMP0524P_SLP2510P8-10-9

61

HDMICLK_R

HDMIDAT_R

@

9

10

8

9

7

6

6 5

D28

1

2

4

3

8

+3VS

1

HDMI_TX1+_CONN

2

4

HDMI_CLK+_CONN

5

HDMI_CLK-_CONN

3

TMDS_B_HPD<15>

+5V_Display

2.2K_0804_8P4R_5%

1

C544

R488

R488 20K_0402_5%

20K_0402_5%

HDMI@

1 2

2

+3VS

R485

1M_0402_5%

HDMI@

TMDS_B_HPD HDMI_DET

RP21

18

HDMIDAT_R

27

HDMICLK_R

36

HDMIDAT_NB

45

HDMICLK_NB

HDMI@

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

YSCLAMP0524P_SLP2510P8-10-9

G

2

1 2

S

9

10

8

9

7

6

6 5

Q93

HDMI@

2N7002H_SOT23-3

13

D

@

D29

1

2

4

3

8

0.1U_0402_16V7K

1

HDMI_TX0+_CONN

2

HDMI_TX0-_CONN

4

HDMI_TX2+_CONN

5

HDMI_TX2-_CONN

3

U73

1

IN

AP2330W-7_SC59-3

HDMI_TX1+_CONN HDMI_TX1-_CONN HDMI_CLK+_CONN HDMI_CLK-_CONN

HDMI_TX0+_CONN HDMI_TX0-_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN

OUT

GND

W=40mils

3

2

+5V_Display

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

680 +-5% 8P4R

RP5

RP6

+5V_Display

C543

0.1U_0402_16V7K

45 36 27 18

HDMI@RP5

HDMI@

45 36 27 18

HDMI@RP6

HDMI@

1

2

JHDMI1

ME@JHDMI1

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

13

D

S

ME@

20

G1

21

G2

22

G3

23

G4

+3VS

2

G

Q95

HDMI@

2N7002H_SOT23-3

19 18 17 16 15 14 13 12 11 10

SUYIN_100042GR019M23DZL

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Size Doc ument Number Rev

B

Date: Sheet of

2

Date: Sheet of

HDMI CONN

LA-9641P

1.0

36 61Friday, April 19, 2013

1

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half)

1 1

+3VS_WLAN

+3VS_WLAN+3VS

80mil

J6

@

Mini-Express Card(WLAN/WiMAX)

JWLN1

@

100_0402_1%

R505

1 2 1 2

R506

100_0402_1%

1 2

R41 0_0402_5%

+3VS_WLAN

R507

R507 100K_0402_5%

100K_0402_5%

For EC to detect

1 2

debug card insert.

DVT

PCIE_WAKE#

1 2

R405

1K_0402_5%

PCIE_WAKE#<15,38>

PCH_BT_ON#<19>

2 2

INTEL_BT_OFF#<1 9>

3 3

CLKREQ_WLAN#<16>

CLK_PCIE_WLAN#<16 >

CLK_PCIE_WLAN<16>

PCIE_PRX_DTX_N2<18> PCIE_PRX_DTX_P2<18>

PCIE_PTX_C_DRX_N2<18> PCIE_PTX_C_DRX_P2<18>

EC_TX<43,44>

EC_RX<43,44>

JWLN1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

BELLW_80003-8041

ME@

GND2

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

112

JUMP_43X79

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

2

+1.5VS

1 2

R501 0_0402_5%@R501 0_0402_5%@

1 2

R502 0_0402_5%@R502 0_0402_5%@

R02

USB20_N10 <18 > USB20_P10 <18>

C548

4.7U_0603_6.3V6K

+3VS_WLAN

1

C547

@C547

0.1U_0402_16V7K

2

@

@C548

@

EMI reserve

PCH_WL_OFF# <15> PLT_RST# <1 5,23,38,43>

SMB_CLK_S3 <12,13,17> SMB_DATA_S3 < 12,13,17>

4 4

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Date: Sheet

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Mini-Card/NEW Card/SIM

LA-9641P

E

of

37 61Friday, April 19, 2013

1.0

5

4

3

2

1

+3VALW

Layout Notice : Place as close chip as possible.

D D

RL3

LAN_PWR_ON#<43>

LAN_PWR_ON#

Vendor recommand reseve the PU resistor close LAN chip

+3V_LAN

PLT_RST#<15,23,37,43>

12

10K_0402_5%

@

2

1

@

1 2

RL4 4.7K_0402 _5%

@

CL7

0.1U_0402_16V7K

J10

112

JUMP_43X79

S

G

2

@

+3V_LAN

@

2

D

13

QL1

QL1 LP2301ALT1G_SOT23-3

LP2301ALT1G_SOT23-3

PLT_RST#

+LX

+1.1_DVDDL

UL1

8162@UL1

8162@

AR8162-AL3A-R

CL1

1000P_0402_50V7K

SWR@

Close to Pin40

Close together

1

CL2

2

0.1U_0402_16V7K

10U_0603_6.3V6M

SWR@

LL1

SWR@LL1

SWR@

1 2

4.7UH_SIA4012-4R7M_20%

Note: Place Close to LAN chip LL1 DCR< 0.15 ohm

Rate current > 1A

CL3

10U

SA000065410 S IC QCA8172-BL3A-R QFN 40P E-LAN CTRL

FBMA-L11160808601LMA10T_2P

1 2

1

CL4

2

1

CL6

CL5

2

1U_0402_6.3V6K

0.1U_0402_16V7K

4.7U_0603_6.3V6K

Place close to Pin34

LL3

SWR@LL3

LL2

FBMA-L11160808601LMA10T_2P

SWR@

1 2

+1.1_DVDDL+1.1_AVDDL+1.1_AVDDL_L

SA000052J20 S IC AR8162-AL3A-R QFN 40P E-LAN CTRL

C C

Place Close to Chip

1 2

PCIE_PRX_DTX_N3<18>

PCIE_PRX_DTX_P3<18>

PCIE_PTX_C_DRX_N3<18>

PCIE_PTX_C_DRX_P3<18>

CLK_PCIE_LAN#<16> CLK_PCIE_LAN< 16>

PCIE_WAKE#<15,37>

LAN_WAKE#<43>

+3V_LAN

Vendor recommand reseve the PU resistor close LAN chip

B B

+3V_LAN

CLKREQ_LAN#<16>

Near Pin13

CL9 0.1U_0402_16V7KCL9 0.1U_0402_16V7K

CL11 0.1U_0402_16V7KCL11 0.1U_0402_16V7K

1 2

RL6 0_0402 _5%@RL6 0_0402_5%@

1 2

RL7 0_0402 _5%@RL7 0_0402_5%@

1 2

RL9 4.7K_0402 _5%

1 2

RL11 4.7K_0402 _5%@RL11 4.7K_0402_5%@

1

CL17

CL18

2

0.1U_0402_16V7K

Near Pin19

1 2

@

Near Pin31

1

CL19

2

0.1U_0402_16V7K

PCIE_PRX_C_DTX_N3

PCIE_PRX_C_DTX_P3

PLT_RST#

LAN_XTALO LAN_XTALI

+1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL_L +1.1_AVDDL

1

CL20

2

Near Pin6

1

CL21

2

1U_0402_6.3V6K

UL1

29

TX_N

Atheros

30

36

35

32 33

2

3

25 26

28 27

7 8

4

13 19 31 34

6

41

@

0.1U_0402_16V7K

Atheros

TX_P

AR8151/AR8161

RX_N

RX_P

REFCLK_N REFCLK_P

PERST#

WAKE#

SMCLK SMDATA

NC TESTMODE

XTLO XTLI

CLKREQ#

AVDDL AVDDL AVDDL AVDDL AVDDL_REG/AVDD L

GND

QCA8172-BL3A-R_QFN40_5X5

8172@

VDDCT/ISOLAN

DVDDL_REG/DVDD L

AVDDH/AVDD33

AVDDH_REG

LED_0 LED_1 LED_2

TRXN0

TRXP0

TRXN1

TRXP1

TRXN2

TRXP2

TRXN3

TRXP3

RBIAS

VDD33

DVDDL/PPS

AVDDH

38 39 23

12 11 15 14 18 17 21 20

10

1

40

LX

5

24 37

16 22 9

RL12 10K_0402_5%

12

LDO@

MDI0MDI0+ MDI1MDI1+

LAN_RBIAS

+3V_LAN

+LX

+1.7_VDDCT

+1.1_DVDDL

+2.7_AVDDH +2.7_AVDDH

@

Near Pin9

1 2

RL8 2.37K_0402_1%RL8 2.37K_0402_1%

Place Close to P IN1

+LX

RL10 30K_0402_5%RL10 30K_0402_5%

+3V_LAN

1

CL23

CL22

2

1U_0402_6.3V6K

0.1U_0402_16V7K

Near Pin22

mount RL12 if us e LDO modue

MDI0- <39> MDI0+ <39> MDI1- <39> MDI1+ <39>

1 2

+2.7_AVDDH

1

CL24

2

0.1U_0402_16V7K

@

Near Pin3

+3V_LAN

1

CL25

CL26

2

0.1U_0402_16V7K

7

Place Close to PIN1

CL13

CL12

1 2

0.1U_0402_16V7K

1000P_0402_50V7K

@

EMI reserve

1U_0402_6.3V6K

+3V_LAN

1

2

1

CL14

2

1U_0402_6.3V6K

1

CL15

CL16

2

@

10U_0603_6.3V6M

10U

+3V_LAN

1

CL8

CL10

@

2

1U_0402_6.3V6K

0.1U_0402_16V7K

Place close to Pin16

LAN_XTALI

YL1

A A

1

25MHZ_10PF_7V25000014

CL28

15P_0402_50V8J

5

4

2

4

1

NC

OSC

15P_0402_50V8J

OSC

YL1

NC

LAN_XTALO

3

2

1

CL29

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sh eet of

Compal Electronics, Inc.

LAN-AR8162/8172

Friday, April 19, 2013

LA-9641P

1

38 6 1

1.0

5

4

Place Close to TL1

3

@

DL1

AZC099-04S.R7G_SOT23- 6

MDI1+ MDI0+

1

I/O1

I/O3

4

2

Reserve gas tube for EMI go rural solution

1

TX+

TX-

RX+

CT NC NC CT

VDD

I/O4

5

6

RL14

1 2

75_0805_5%

DLL1

16

MDO0+

15

MDO0-

14

MCT

13 12 11

MCT

10

MDO1+

9

MDO1-

DLL1 BS4200N-C-LV_SMB-F2

BS4200N-C-LV_SMB-F2

GAS@

Place Close to TL1

CL30

1 2

10P_0603_50V

12

1 2

CL63 0.1U_0603_50V7KCL63 0.1U_0603_50V7K

1 2

CL61 0.1U_0603_50V7KCL61 0.1U_0603_50V7K

1 2

CL62 0.1U_0603_50V7KCL62 0.1U_0603_50V7K

CHASSIS1_GND

1

DL

D D

C C

1'S PN:SC300001G00 2'S PN:SC300002E00

1

CL31

@ CL31

@

0.01U_0402_16V7K

2

MDI0- MDI1-

MDI0+<38> MDI0-<38>

MDI1+<38> MDI1-<38>

MDI0+ MDI0-

MDI1+ MDI1-

2

GND

3

I/O2

TL1

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

MHPC_NS681612A

Need check Symbol

1 2

CL64 0.1U_0603_50V7KCL64 0.1U_0603_50V7K

JLAN1

MDO0+

MDO0-

MDO1+

MCT

B B

MDO1-

MCT

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

SANTA_130456-121

ME@

GND GND

9 10

CHASSIS1_GND

A A

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

B

Date:

Date: of

2

Date: of

Compal Electronics, Inc.

LAN_Transformer

Friday, April 19, 2013 Sheet

LA-9641P

1

of

39 61

1.0

5

4

3

2

1

D D

REMOTE1+<24>

2200P_0402_50V7K

REMOTE1-<24>

C C

2200P_0402_50V7K

C587

1

2

REMOTE1+ EC_SMB_DA2

REMOTE1-

+3VS

+3VGS

1 2

R335

4.7K_0402_5%

@

U9

1

VDD

2

D+

3

D-

THERM#4GND

EMC1402-2-ACZL-TR MSOP 8P

SCLK

SDATA

ALERT#

EMC1412-A (SA00003YA00) Address 1111_100xb S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR

8

7

6

5

EC_SMB_CK2

EC_SMB_CK2 <17,24,33,43>

EC_SMB_DA2 <17,24,33,43>

REMOTE1,2+/-: Tra

ce width/space:10/10 mil

Trace length:<8"

H2

H1

H1 HOLEA

HOLEA

B B

1

H_3P8

HOLEA

1

H_3P8

H3

H3 HOLEA

HOLEA

1

H_3P8

VGA_L VGA_RCPU

H4

H4 HOLEA

HOLEA

1

H_3P3

H5

H5 HOLEA

HOLEA

1

H_3P3

FD1FD1

FD2FD2

FD3FD3

FD4FD4

1

A

H7

H8

FAN1 Conn

+5VS

R581 0_0603_5%R58 1 0_0603_5%

A A

2

C591

C591 10U_0603_6.3V6M

10U_0603_6.3V6M

1

10U

5

12

EC_TACH<43>

EC_FAN_PWM<43>

ACES_85205-04001

JFAN1

1

2

3

4

5

G5

6

G6

Security Classification

ME@

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2P8 * 7 pcd

2011/06/15 2012/07/11

3

H8

HOLEA

1

H_2P8

Compal Secret Data

Deciphered Date

H10

H10 HOLEA

HOLEA

1

H_2P8

B

H18

H11

H11 HOLEA

HOLEA

1

H_2P8

H12

H12 HOLEA

HOLEA

H_2P8

H18 HOLEA

HOLEA

1

H_2P8

D

Title

Size Doc ument Number Rev

B

Date: Sheet of

2

Date: Sheet of

M/

橢橢橢

B

H16

H16 HOLEA

HOLEA

1

H_2P5X3P5N

M/B

H17

H17 HOLEA

HOLEA

1

H_3P0N

E

Compal Electronics,Ltd.

Fintek-Thermal IC/FAN/screw

LA-9641P

1

橢橢

40 61Friday, April 19, 2013

1.0

A

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD1

1

GND

12

SATA_PTX_DRX_P4

1 2 1 2

12

+3VS

+5VS

C1160.01U_0402_16V7K C1160.01U_0402_16V7K C1140.01U_0402_16V7K C1140.01U_0402_16V7K

SATA_PTX_DRX_N4

1 2

R552

1 2

R550

10U

1

C602

C602 10U_0603_6.3V6M

10U_0603_6.3V6M

2

SATA_DTX_PRX_N4SATA_DTX_C_IRX_N4 SATA_DTX_PRX_P4

@

0_0805_5%

@

0_0805_5%

+3V_HDD

+5V_HDD

SATA_PTX_C_DRX_P4<14> SATA_PTX_C_DRX_N4<14>

SATA_DTX_C_PRX_N4<14> SATA_DTX_C_PRX_P4<14>

1 1

+5V_HDD

R02

1

C598

@C598

@

1000P_0402_50V7K

2

SATA_DTX_C_IRX_P4

1

C599

0.1U_0402_16V7K

2

C596 0.01U_0402_16V7KC596 0.01U_0402_16V7K C597 0.01U_0402_16V7KC597 0.01U_0402_16V7K

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18

Reserved

19

GND

20

12V

21 22

SUYIN_127043FB022G278ZR

GND

12V

GND

12V

23 24

2 2

+5VS

+5VALW

12

ZODD@

R568

10K_0402_5%

1

OUT

ODD_EN<19>

3 3

2

IN

GND

Q100

Q100 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

3

ODD Power Control

JUMP_43X79

R675

R675 100K_0402_5%

100K_0402_5%

1 2

ZODD@

J9

@ J9

@

112

D

S

D

S

13

Q99

G

LP2301ALT1G_SOT23-3

2

1

ZODD@

C607

0.01U_0402_16V7K

2

ZODD@

+5V_ODD

1

2

EMI reserve

1

C604

0.1U_0402_16V7K@

2

C608

C608 10U_0603_6.3V6M

10U_0603_6.3V6M

FOR 15"

SATA ODD FFC Conn.

JODD2

1

SATA_PTX_C_DRX_P5<14> SATA_PTX_C_DRX_N5<14>

SATA_DTX_C_PRX_N5<14>

SATA_DTX_C_PRX_P5<14>

SATA_PTX_C_DRX_P5 SATA_PTX_C_DRX_N5

SATA_DTX_C_PRX_N5 SATA_DTX_C_PRX_P5 SATA_DTX_PRX_P5_15

ODD_DA#<43>

1 2

R401 0_0402_5%15@R401 0_0402_5%15@

1 2

R402 0_0402_5%15@R402 0_0402_5%15@

1 2

R403 0_0402_5%15@R403 0_0402_5%15@

1 2

R404 0_0402_5%15@R404 0_0402_5%15@

+3VS

ODD_DA#

1 2

R555

10K_0402_5%

R710 0_0402_5%ZODD@R710 0_0402_5%ZODD@

1 2

SATA_PTX_DRX_P5_15 SATA_PTX_DRX_N5_15

SATA_DTX_PRX_N5_15

ODD_DETECT#

+5V_ODD

R02

Co-lay

2

3

4

5

6

7

8

9

10

HB_A051020-SAHR21

ME@

GND GND

11 12

FOR 14"

SATA ODD Conn.

JODD1

1

1 2

C616 0.01U_0402_16V7K14@ C616 0.01U_0402_16V7K14@

SATA_PTX_C_DRX_N5

SATA_DTX_C_PRX_N5 SATA_DTX_C_PRX_P5 SATA_DTX_PRX_P5_14

4 4

1 2

C615 0.01U_0402_16V7K14@ C615 0.01U_0402_16V7K14@

1 2

C614 0.01U_0402_16V7K14@ C614 0.01U_0402_16V7K14@

1 2

C613 0.01U_0402_16V7K14@ C613 0.01U_0402_16V7K14@

SATA_PTX_DRX_P5_14SATA_PTX_C_DRX_P5 SATA_PTX_DRX_N5_14

SATA_DTX_PRX_N5_14

ODD_DETECT# +5V_ODD

ODD_DA#

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND GND13GND

ALLTO_C18518-11305-L

ME@

GND

15 14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

D

Compal Secret Data

Deciphered Date

E

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

HDD/ODD/BT Connector

LA-9641P

G

of

41 61Friday, April 19, 2013

H

1.0

5

CX20751 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO).

An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).

D D

+3VLP

+3V_PCH

+3VS

Should be same supply rail as used for PCH

For EMI Near Audio Chip

+3VS

12

@

RA15

4.7K_04 02_5%

HDA_RST_AUD IO#

1

@

CA11

0.1U_040 2_16V7K

C C

2

using wide copper bridge under codec (100 mils or more)

HDA bus controller section

1 2

RA4 0_0402_5%RA4 0_0402 _5%

+3V_PCH

HDA_BITCLK_ AUDIO<14 >

HDA_SYNC_A UDIO<14>

HDA_SDIN0<14>

HDA_SDOUT_A UDIO<14 >

1 2

RA1 0_0402_5%RA1 0_0402 _5%

1 2

RA2 0_0402_5%@RA2 0_0 402_5%@

HDA_RST_AUD IO#<14>

HDA_BITCLK_ AUDIO

RA9 33_0402_5 %RA 9 33_ 0402_5%

EC_MUTE#<43>

CA8

@

1 2

1

CA9

2

1U_0603_10V6K

1

CA16

CA17

2

4.7U_0603_6.3V6K

Internal analog MIC

1 2

CA64 0 .1U_0402_1 6V7K@CA64 0.1U _0402_16V 7K@

1 2

CA65 0 .1U_0402_1 6V7K@CA65 0.1U _0402_16V 7K@

1 2

CA66 0 .1U_0402_1 6V7K@CA66 0.1U _0402_16V 7K@

B B

22P_040 2_50V8J

follow vendor suggest & reserver default design

CA7

@

Internal SPEAKER

1 2

33_0402 _5%

HDA_BITCLK_ AUDIO

RA21

@RA 21

@

EMI request reserve RA21 & CA7

PC Beep

EC Beep

ICH Beep

A A

BEEP#<43>

HDA_SPKR<14>

5

1 2

CA37 0.1U_0402_16 V7KCA3 7 0.1U _0402_16V 7K

1 2

CA45 0.1U_0402_16 V7KCA4 5 0.1U _0402_16V 7K

12

RA22

RA22 10K_040 2_5%@

10K_040 2_5%@

RA492

1 2

33_0402 _5%

PC_BEEP

1

CA5

2

0.1U_0402_16V7K

HDA_RST_AUD IO#

HDA_SYNC_A UDIO

HDA_SDOUT_A UDIO

PC_BEEP

T3T3

MIC_IN

SPK_L2+ SPK_L1-

SPK_R2+ SPK_R1-

WM-64PC Y_2P

4

0.1U_0402_16V7K

+3VS

+LDO_1.8V

CA24

MIC1

MIC@

4

3

+VREF_1V6 5

1

CA1

1

CA6

2

@

4.7U_0603_6.3V6K

CA1

2

1U_0603_10V6K

1

@

CA15

@

CA10

2

1U_0603_10V6K

0.1U_0402_16V7K

10 mils

1

CA25

2

0.1U_0402_16V7K

4.7U_0603_6.3V6K

9

5 8 6 4

10 39

1

40

36 37

12 14

17 15

1 2

GNDA

2

3

7

UA1

VDD_IO

FILT_1.8

RESET#

BIT_CLK SYNC SDATA_IN SDATA_OUT

PC_BEEP SPKR_MUTE#

DMIC_DAT/GPIO1 DMIC_CLK / MUSIC_REQ/GPIO0

MUSIC_REQ/GPIO0/PORTC_L_MIC GPIO1/PORTC_R_MIC

LEFT+ LEFT-

RIGHT+ RIGHT-

GND

41

Place colose to Codec chip

+MICBIASC

1

2

CA42

CA44

0.1U_0402_16V7K

@

CA3 vendor suggest change to 2.2U

1

CA2

2

0.1U_0402_16V7K

18

24

27

28

29

AVDD_5V

AVDD_3.3

DVDD_3.3

AVDD_HP

VDDO_3.3

CLASS-D_REF

VREF_1.65V

PORTB_L_LINE

PORTB_R_LINE

PORTD_A_MIC PORTD_B_MIC

CX20757 -11Z_QFN40

12

RA23

2.2K_04 02_5%

CA41 1U_0 603_10V6KCA41 1U_0 603_10V6 K

1 2

CA41 vendor suggest change to 1U

+5VS

SPK_R1-_ CONN

SPK_R2+_ CONN

2

CA3

1

LPWR_5.0

RPWR_5.0

JSENSE

MICBIASB MICBIASC

HGNDA HGNDB

PORTA_L

PORTA_R

AVEE

FLY_P

FLY_N

CA4

2.2U_0603_6.3V4Z

6

5

4

AVDD_3.3 pinis output of

1

internal LDO. NOT connect to external supply.

2

0.1U_0402_16V7K

1

CA19

CA18

@

2

0.1U_0402_16V7K

4.7U_0603_6.3V6K

13 16 11

38

JSENSE

34 35

32

MICB_L

33

MICB_R

30

APPLE_M IC

31

NOKIA_MIC

25

HGNDA

26

HGNDB

22

HP_L

23

HP_R

Headphone

21 19

1 2

20

CA29 1U_0 603_10V6KCA29 1U _0603_10V 6K

MIC_INEXT_MIC

DA3

I/O4

I/O2

VDD

GND

I/O3

I/O1

AZC099-04 S.R7G_SOT23 -6

@

+LDO_OUT_3 .3V

+5VS

1

CA26

2

0.1U_0402_16V7K

+MICBIASB +MICBIASC

Universal Jack

External MIC

SPK_R1SPK_R2+ SPK_L1SPK_L2+

wide 20MIL

3

SPK_L1-_ CONN

2

1

SPK_L2+ _CONN

3

Layout Note:Path from +5VS to LPWR_5.0

RPWR_5.0 must be very low resistance (<0.01 ohms)

1

CA20

2

1

CA22

CA23

CA21

0.1U_0402_16V7K

CA23

@

2

0.1U_0402_16V7K

4.7U_0603_6.3V6K

Please bypass caps very close to device.

APPLE_M IC HGNDB NOKIA_MIC HGNDA HP_L HPOUT_L HP_R HPOUT_R

MICB_L HP_L

MICB_R HP_R

+MICBIASB

2

1

CA30

CA35

1

2

0.1U_0402_16V7K

2.2U_0603_6.3V4Z

CA30 vendor suggest change to 2.2U

~@

LA1

LA1 0_0603_ 5%

0_0603_ 5%

LA3

LA3 0_0603_ 5%

0_0603_ 5%

LA1 FB MA-L11-1608 08-121LMT_06 03LA 1 FBMA-L11 -160808-12 1LMT_0603 LA2 FB MA-L11-1608 08-121LMT_06 03LA 2 FBMA-L11 -160808-12 1LMT_0603 LA3 FB MA-L11-1608 08-121LMT_06 03LA 3 FBMA-L11 -160808-12 1LMT_0603 LA4 FB MA-L11-1608 08-121LMT_06 03LA 4 FBMA-L11 -160808-12 1LMT_0603

LA2

LA2 0_0603_ 5%

0_0603_ 5%

~@

LA4

LA4 0_0603_ 5%

0_0603_ 5%

1 2 1 2 1 2 1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1 2

RA17 100_0402 _1%RA17 100_0 402_1%

1 2

RA18 100_0402 _1%RA18 100_0 402_1%

1 2

RA20 3K_0402_ 5%RA20 3K_0 402_5%

1 2

RA19 3K_0402_ 5%RA19 3K_0 402_5%

HPOUT_L

HPOUT_R

HGNDB

HGNDA

LA1~LA4 vendor suggest mount 0 ohm first~ Bead reserve for EMI if needed

SPK_R1-_ CONN SPK_R2+_ CONN SPK_L1-_ CONN SPK_L2+ _CONN

vendor suggest change to 1000p

2011/06/15 2012/07/11

2

+5VS

1 2

RA16 100_0402 _1%RA16 100_0 402_1%

1 2

RA12 100_0402 _1%RA12 100_0 402_1%

1 2

RA13 15_0402_ 5%RA13 15_0402_ 5%

1 2

RA14 15_0402_ 5%RA14 15_0402_ 5%

1

CA31

CA32

CA33

2

220P_0402_50V8K

1

CA39

CA38

2

1000P_0402_50V7K

Compal Secret Data

2

JSENSE

CA36

1 2

2.2U_040 2_6.3V6M

CA46

1 2

2.2U_040 2_6.3V6M

1

CA34

2

220P_0402_50V8K

1

CA40

2

1000P_0402_50V7K

Deciphered Date

1 2

RA5 5.11K_0 402_1%RA5 5.11K_ 0402_1%

RA6 10K_04 02_1%RA6 10 K_0402_1 %

1 2

RA7 20K_04 02_1%RA7 20 K_0402_1 %

1 2

RA8 39.2K_0 402_1%RA8 39.2K_ 0402_1%

1 2

CA28 2.2U_04 02_6.3V6MCA28 2.2U_0 402_6.3V6 M

1 2

CA27 2.2U_04 02_6.3V6MCA27 2.2U_0 402_6.3V6 M

for Universal jack

HPOUT_L

HPOUT_R

HGNDB

HGNDA

220P_0402_50V8K

1

CA43

2

1000P_0402_50V7K

HGNDA, HGNDB 80mils

2

3

DA1

@

1

AZ5125-02S.R7G_SOT23-3

1

Sense resistors must be connected same power that is used for VAUX_3.3

+3VS

mount RA6 on the Jack Sense circuit

configure Port-C for mono MIC.

to

PLUG_IN

Don't support LINE_IN function RA7 could be @

Check footprint

JHP1

4 3 1 2

PLUG_IN

2

3

DA2

@

1

AZ5125-02S.R7G_SOT23-3

Title

Size Doc ument Numb er Rev

Custom

Date: S heet of

5

6

SINGA_2S J2352-0001 31F

ME@

Pin Ref

1:L 2:R 3:GND/MIC 4

:MIC/GND 5:normal open 6:GND

JSPK1

1

2

3

4

5

G5

6

G6

ME@

ACES_85 205-04001

Compal Electronics, Inc.

CX20751 Codec

LA-9641P

1

42 6 1Friday, April 19, 2013

1.0

L44

FBM-11-160808-6 01-T_0603

+3VALW_EC +EC_VCCA

+3VALW_EC

+3VS

1 2

0.1U_0402_16V7K

1 2

L45

FBM-11-160808-6 01-T_0603

C660 22P_0402_50V8J@C660 22P_0402 _50V8J@

1 2

R590 47K_0402_5%R590 47K_0402_5 %

0.1U_0402_16V7K

KSO[0..15]<4 4>

KSI[0..7]<44>

R600

1 2

2.2K_0402_5%

R604

1 2

2.2K_0402_5%

R605 10K_0402_5%R605 10K_0402_5 %

EC_TACH

C656

12

C661

KSO[0..15]

KSI[0..7]

EC_SMB_CK1

EC_SMB_DA1

PCH_PWROK<15>

DGPU_PWR_EN<15,25 ,53,55>

1

2

ECAGND

R589 10_0402_5%@ R589 10_0402_5%@

2

1

R608

@ R608

@

10K_0402_5%

@

12

1

C659

1000P_0402_50V7K

2

SLP_SUS#<15,4 7>

SUSCLK<15>

+3VLP

+3VALW

0.1U_0402_16V7K

EC_VGA_EN<55>

EC_TACH<40>

LAN_WAKE#<38> EC_TX<37,44> EC_RX<37,44>

DGPU_PWR_EN

LAN_WAKE#

C653

1

2

LPC_FRAME#<17>

CLK_PCI_EC<16>

PLT_RST#<15,23 ,37,38>

EC_SCI#<19> BATT_LEN#<49>

EC_SMB_CK1<49,50> EC_SMB_DA1<49,50> EC_SMB_CK2<17,24,33,4 0> EC_SMB_DA2<17,24,33,4 0>

PM_SLP_S3#<15> PM_SLP_S5#<15> EC_SMI#<19> CMOS_ON#<34>

ODD_DA#<41>

NOVO#<44>

100K_0402_5%

C654

0.1U_0402_16V7K

C654

0.1U_0402_16V7K

GATEA20<19> KBRST#<19>

SERIRQ<17>

LPC_AD3<17> LPC_AD2<17> LPC_AD1<17> LPC_AD0<17>

KSO16<44> KSO17<44>

NUM_LED#: NC

R740

+3VALW

1 2

1

2

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

+3VLP

1

C535

C535 100P_0402_50V8J@

100P_0402_50V8J@

2

+EC_VCCA

9

22

33

96

125

111

EC_VDD0

EC_VDD/VCC

PWM Output

AD Input

DA Output

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

GPIO

H_PROCHOT#_EC/GPXIOA06

GPO

GPIO

GPI

GND/GND

GND0

11

24

35

94

113

ECAGND

U31

67

EC_VDD/AVCC

BATT_TEMP/GPIO38

EC_MUTE#/GPIO4A

WOL_EN/GPXIOA01

HDA_SDO/GPXIOA02

VCIN0_PH/GPXIOD00

PECI_KB930/GPIO41

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

VCOUT0_PH/GPXIOA07

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

LID_SW#/GPXIOD04

PECI_KB9012/GPXIOD07

AGND/AGND

69

PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER

ECAGND

U31

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

SPIDI/GPIO5B

SPIDO/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/GPIO40

FSTCHG/GPIO50

SYSON/GPIO56 VR_ON/GPIO57

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

SUSP#/GPXIOD05

GPXIOD06

V18R

KB9012QF A3 LQFP 128P_1 4X14

EMC Request

SYSON

C492

1

@

2

0.1U_0402_16V7K

R301 0_0603_5%@R301 0_0603_5%@

R304 0_0 603_5%@R304 0_0603_5%@

C662

1000P_0402_50V7K

C662

1000P_0402_50V7K

1

2

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMI#

ODD_DA#

EC_TACH

EC_TX EC_RX PCH_PWROK

12

@

R606

R606 10K_0402_5%

10K_0402_5%

12

C655

0.1U_0402_16V7K@C655

0.1U_0402_16V7K

1

@

2

LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMP LPC_AD0

EC_RST# EC_SCI# BATT_LEN#

NOVO#

122 123

12

C93

C93 20P_0402_50V8

20P_0402_50V8

@

1000P_0402_50V7K

C657

0.1U_0402_16V7K@C657

0.1U_0402_16V7K

1

@

2

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC & MISC

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

XCLKI/GPIO5D XCLKO/GPIO5E

+3VALW_EC

C658

3.3V +/- 5%

Vcc

100K +/- 5%

R694

Board ID

0

12K +/- 5%

1

15K +/- 5%

2

33K +/- 5%

3

21

ADP_65

23

BEEP#

26

EC_FAN_PWM

27

ACOFF

63 64 65 66

ADP_ID

75

BRDID

76

68

ADP_90

70 71 72

83 84

USB_ON#

85

ADP_135

86 87

TP_CLK

88

TP_DATA

97

EC_TS_ON#

98 99 109

119

EC_SPI_SO

120

EC_SPI_SI

126

EC_SPI_CLK

128

EC_SPI_CS#

73 74 89 90

BATT_CHG_LED#

91

CAPS_LED#

92 93

BATT_LOW_LED#

95

SYSON

121 127

100 101

EC_LID_OUT#

102

Turbo_V

103

PROCHOT

104 105

BKOFF#

106

PBTN_OUT#

107

PCH_PWR_EN

108

1.05VS_EN

110

ACIN

112

EC_ON

114 115

LID_SW#

116

SUSP#

117

NUVOTON_VTT

118

PECI_KB9012

124

+V18R

1

C667

4.7U_0603_6.3V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R406 0_0402_5%@R406 0_04 02_5%@

1 2

R595 10K_0402_5%@R595 10K_0402_5%@

1 2

ADP_65 <49> BEEP# <42> EC_FAN_PWM <40> ACOFF <50>

GPU_IMON <55> ADP_I <49 ,50> ADP_ID <48>

ADP_90 <49>

SUSACK# <15>

DPWROK_EC <15>

SUSWARN# <1 5>

EC_MUTE#

ADP_135 <49>

IMVP_IMON <56>

CAPS_LED# <44> PWR_LED# <44> BATT_LOW_LED# <44>

SYSON <52>

VR_ON <56>

PM_SLP_S4# <15>

EC_RSMRST# <15>

EC_LID_OUT# <19>

BKOFF# <34> PBTN_OUT# <15> PCH_PWR_EN <47>ADP_ID_CLOSE<48>

1.05VS_EN <54>

1 2

R669 43_0402_1%R669 43_0402_1%

BATT_TEMP <48,49>

ENBKL <33>

@

R593 10K_0402_5%

1 2

EC_MUTE# <42> USB_ON# <46>

SYS_PWROK <15,6>

TP_CLK <44>

TP_DATA <44>

EC_SPI_SO <17>

EC_SPI_SI <17>

EC_SPI_CLK <17>

EC_SPI_CS# <17>

2011/06/15 2012/07/11

+3VALW

EC_TS_ON# <46>

+1.5VS_PWRGD < 53>

ME_FLASH <14>

NTC_V <49>

VGATE < 15,56> LAN_PWR_ON# <38>

BATT_CHG_LED# <44>

ACIN <15,24,48,50> EC_ON <51>

ON/OFF <44>

LID_SW# <44>

SUSP# <47,5 2,53,54>

+1.05VS

H_PECI <19,6>

Compal Secret Data

Deciphered Date

Turbo_V <49>

PROCHOT <49> MAINPWON <51>

0

BRDID

+3VALW

1 2

PROCHOT

VR695

AD_BID

0.423 V

0.712 V

R694

R694 100K_0402_1%

100K_0402_1%

R695

R695 0_0402_5%

0_0402_5%

0 V

R04

2N7002H_SOT23-3

min

Q37

Custom

typ

V

AD_BID

0.430 V

0.819 V

13

2

G

Title

Size Document Number Rev

Date: Sheet of

V

max

AD_BID

0 V0 V

0.360 V0.354 V0.347V

0.438 V

0.875 V

USB_ON#

TP_CLK

TP_DATA

D

S

1 2

R603 4.7K_0402_5%R603 4.7K_0402_ 5%

R598 4.7K_0402_5%R598 4.7K_0402_ 5%

1 2

BATT_TEMP

ACIN

LID_SW#

1 2

C663 100P_0402_50V8JC663 100P_0402_ 50V8J

1 2

C664 100P_0402_50V8JC664 100P_0402_ 50V8J

1 2

R522 4.7K_0402_5%@R522 4.7K_0402_5%@

R601 100K_0402_5%R601 100K_0402_5%

12

H_PROCHOT# <48,4 9,56,6>

1

C493

C493 47P_0402_50V8J

47P_0402_50V8J

2

Compal Electronics, Inc.

BIOS & EC I/O Port

LA-9641P

MP PVT DVT EVT

R594

1 2

10K_0402_5%

+3VALW

43 61Friday, April 19, 2013

+5VALW

+5VS

1.0

EC_TX<37,43> EC_RX<37,43>

J11: TOP J1

2: BOT

TP_CLK<43> TP_DATA<43>

5

6

4

3

5

6

4

3

+3VALW

J12

1 2

SHORT PADS

J11

1 2

SHORT PADS

EMI reserve

PSOT24C_SOT23-3

SW4

14@SW4

14@

TJG-533-V-T/R_6P

2

1

SW6

15@SW6

15@

TJG-533-V-T/R_6P

2

1

@D15

@

+5VS

D15

ACES_85205-0400

C696

@ C696

@

0.1U_0402_16V7K

3

1

TP_3

KSI[0..7]

KSO[0..17]

+3VLP

R643

R643 100K_0402_5%

100K_0402_5%

ME@JTP1

ME@

VCC

CLK

DAT

GND

L

R

NOVO#

ON/OFF

1 2

+3VALW

1 2

1

2

3

4

5

6

12

@

R628 0_0402_5%

R642

@R642

@

100K_0402_5%

D26

@D26

@

2

3

DAN202UT106_SC70-3

14"15"

VCC

CLK

DAT

L

R

GND

1

JP3

1

2

3

4

ME@

NOVO#<43>

+3VLP

R701

R701 100K_0402_5%

100K_0402_5%

1 2

ON/OFF

2

R627

R627 0_0402_5%

0_0402_5%

R619 0_0402_5%

0_0402_5%

15@

12

14@R619

14@

ON/OFF <43>

JTP1

8

GND

7

GND

6

TP_CLK TP_DATA TP_3 TP_2

TP_1

TP_3

TP_1

5

4

3

2

1

ACES_88058-060N

RL

SW5

14@SW5

14@

TJG-533-V-T/R_6P

5

6

2

4

3

1

SW7

15@SW7

15@

TJG-533-V-T/R_6P

5

6

2

4

3

1

TP_2

TP_1TP_2

1

2

3

4

5

6

NOVO_BTN#

BATT_LOW_LED#<43>

BATT_CHG_LED#<43>

PWR_LED#<43>

CAPS_LED#<43>

KSI[0..7] <43>

KSO[0..17] <43>

PWR_LED#

BATT_LOW_LED#

BATT_CHG_LED#

CAPS_LED#

USB20_N11<18> USB20_P11<18>

LED1

21

R623 649_0402_1%

19-213A-T1D-CP2Q2HY-3T_WHITE

14@

LED2

21

R764 470_0402_5%

HT-191UD5_AMBER

14@

LED5

21

R765 649_0402_1%

19-213A-T1D-CP2Q2HY-3T_WHITE

14@

LED6

21

R303 649_0402_1%

19-213A-T1D-CP2Q2HY-3T_WHITE

14@

USB20_N11

USB20_P11

14@

12

USB20_N11 USB20_P11

1

4

L67

1

4

+5VALW

+3VALW

+5VALW

+5VS

WCM-2012-900T_4P

2

3

~@

12 12

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16 KSO17

ACES_88514-3001

USB20_N11_R

USB20_P11_R

USB20_N11_R

R6870_0402_5% R6870_0402_5%

USB20_P11_R

R6830_0402_5% R6830_0402_5%

LID_SW#<43>

@

D24

PJSOT24C 3P C/A SOT-23

JKB1

ME@JKB1

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

28 29 30

+3VALW

31

GND

32

GND

+3VS

ME@

CVILU_CF06041H0RB-NH

1

2

3

4

GND GND

JCR1

C605 ESD reserve

JPWRB1

1

2

LID_SW#

PWR_LED# BATT_LOW_LED# BATT_CHG_LED# CAPS_LED#

3

4

5

6

7

GND

8

GND

ACES_88058-060N

ME@

NOVO_BTN# ON/OFF

2

3

1

+5VALW +3VALW

+5VS

29 30

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

5 6

JLED1

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

HB_A091020-SAHR21

ME@

JKB2

26

GND2

25

GND1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_88514-2401

ME@JKB2

ME@

1

C605

0.1U_0402_16V7K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

ROM/KBD/PWR/CR/LED/TP Conn.

LA-9641P

44 61Friday, April 19, 2013

of

1.0

A

1 1

2 2

B

C

D

E

3 3

4 4

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

USB ext. ports

LA-9641P

45 61Friday, April 19, 2013

E

1.0

5

4

3

2

1

+3VS +3 VS_TS

1 2

TS@

R5583 0 _0402_5%

Right Ext.USB Conn.

D D

+USB_VCCB

RUSB@

C C

B B

A A

+USB_VCCB

1

C714

+

220U_6.3 V_M

2

6.3Φ * 5.9 SF000001500

+5VALW +USB3_VCCA

USB_ON#

+USB3_VCC A

1

C736

+

220U_6.3 V_M

2

SF00000 1500

+5VALW

USB_ON#<43> US B_OC4# <18>

R02

U36

RUSB@U36

RUSB@

1

GND

VOUT

2

VOUT7VIN

VIN3VOUT

4

FLG

EN

G547I2P 81U_MSOP8

+USB_VCCB

8

6 5

W=80mils

12

R868 0_04 02_5%~@R8 68 0_0402_5 %~@

12

R869 0_04 02_5%~@R8 69 0_0402_5 %~@

USB_OC0# <1 8>

D22

@

3

I/O2

2

VDD

GND

1

I/O1

AZC099-04 S.R7G_SOT23 -6

USB20_N9

USB20_P 9

2A/A

1 2

4

USB20_N9< 18> USB20_P 9<18>

L66

4

1

WCM-201 2HS-900T

ctive Low

R02

U35

GND

VOUT VOUT7VIN

VIN3VOUT

FLG

EN

G547I2P 81U_MSOP8

5

USB20_N9 USB20_P 9

RUSB@L66

RUSB@

3

USB20_N9 _C

3

2

USB20_P 9_C

2

W=80mils

8

6 5

U2DN1

RIGHT USB PORT X 1

JUSB3

ME@JUSB 3

ME@

8

GND

7

GND

6

5

4

USB20_N9 _C USB20_P 9_C

2

3

D25

@D25

@

1

PJDLC05_ SOT23-3

9

10

8

U3RXDP1

9

7

U3TXDN1

7

6

U3TXDP1

6 5

YSCLAMP05 24P_SLP2 510P8-10-9

@

9

U3RXDN2 U3RXDN2

10

8

9

7

U3TXDN2

7

6

U3TXDP2

6 5

YSCLAMP05 24P_SLP2 510P8-10-9

6

I/O4

5

+5VALW +5VALW

4

U2DP1

I/O3

3

2

1

ACES_88 058-060N

D27

@

1

U3RXDN1U3RXDN1

1

2

U3RXDP1

2

4

U3TXDN1

4

5

U3TXDP1

3

8

D30

1

2

U3RXDP2U3RXDP2

2

4

U3TXDN2

4

5

U3TXDP2

3

8

D31

3

U2DP2

I/O2

2

GND

1

I/O1

AZC099-04 S.R7G_SOT23 -6

4

R5581 100K_04 02_5%

100K_04 02_5%

EC_TS_ON#<43>

USB20_N1<18>

USB20_P 1<18>

USB3_RX2 _N<18>

USB3_RX2 _P<18>

USB3_TX2_ N<18 >

@

I/O4

VDD

I/O3

USB3_TX2_ P<1 8>

6

5

4

U2DN2

1 2

0.1U_040 2_16V7K

C850

0.1U_040 2_16V7K

1 2

C848

0.1U_040 2_16V7K

USB30@C8 50

USB30@

U3TXDN2_L

U3TXDP2_L

USB30@C8 48

USB30@

R5583 0 _0402_5%

@R5581

@

1

C1331

2

@

WCM-201 2-900T_4P

1

4

L55

WCM-201 2HS-900T

1

4

L54

WCM-201 2HS-900T

1

4

L53

3

S

USB30@

G

2

D

13

Q156

Q156 LP2301A LT1G_SOT23-3

LP2301A LT1G_SOT23-3

@

2

3

2

3

2

3

2

1

2

U2DN2

3

U2DP2

2

U3RXDN2

3

U3RXDP2

U3TXDP2

U3TXDN2 U2DP2

U2DN2 U3RXDP2

U3RXDN2

2

U3TXDN2

3

U3TXDP2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C1322

TS@

0.1U_0402_16V7K

+USB3_VCC A

W=80mils

9 1 8 3 7

6 4 5

TAITW_PUB AU1-09FNLSCNN 4H0

USB20_N2< 18> USB20_P 2<1 8>

LP2

JUSB1

SSTX+ VBUS SSTXD+ GND D-2GND

GND

SSRX+ GND

GND GND

SSRX-

ME@

2011/06/15 2012/07/11

R20

1 2

R722 0_0 402_5%@R 722 0_0402 _5%@

10 11 12 13

+3VS_TS

Int

el_PCH_USB2.0

USB20_N0<18>

USB20_P 0<18>

Intel_PCH_USB3.0

USB3_RX1 _N<18>

USB3_RX1 _P<18>

USB3_TX1_ N<18 >

USB3_TX1_ P<1 8>

Compal Secret Data

Deciphered Date

2

TS_RST#EC_TS_ON#

ME@

8

GND

7

GND

6

5

4

3

2

1

JTS1

Touch Screen

1

4

L51

1

4

L50

C849

USB30@C8 49

USB30@

0.1U_040 2_16V7K

1 2

C847

USB30@C8 47

USB30@

0.1U_040 2_16V7K

1

U3TXDN1_L U3TXDN1

4

U3TXDP1_L

WCM-201 2-900T_4P

1

4

WCM-201 2HS-900T

1

4

WCM-201 2HS-900T

1

4

L49

2

U2DN1

2

3

U2DP1

3

2

3

USB30@

2

3

USB30@

Title

Size Doc ument Numb er Rev

Custom

Date: S heet of

+USB3_VCC A

U3RXDN1

U3RXDP1

U3TXDP1

U3TXDN1 U2DP1

U2DN1 U3RXDP1

U3RXDN1

W=80mils

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND D-2GND

6

SSRX+

4

GND

5

SSRX-

TAITW_PUB AU1-09FNLSCNN 4H0

ME@

Compal Electronics, Inc.

USB3.0/Left USB Ports

1

LP1

46 6 1Friday, April 19, 2013

GND GND GND

10 11 12 13

1.0

A

+5VALW

1

C720

4.7U_0603_6.3V6K @

1 1

2 2

4.7U_0603_6.3V6K @

+VSB +VSB

12

13

D

2

SUSP

G

S

SLP_SUS#<15,4 3>

PCH_PWR_EN<43>

先先先

,C phase

2

R646

R646 150K_0402_5%

150K_0402_5%

5VS_GATE

Q110

Q110 2N7002_SOT23

2N7002_SOT23

U38

AP4800BGM_SOP8L-8

8 7

5

R649

12

82K_0402_5%

@

1 2

R34 0_0402_5%

1 2

@

R38 0_0402_5%

再再再

4

5VS_GATE_R

+5VS

1 2 36

1

C726

0.01U_0402_25V6

2

1

C721

4.7U_0603_6.3V6K@

2

DS3_EN

100K_0402_5%

R781

SLP_SUS

100K_0402_5%

12

@R781

@

1

C722

C722 1U_0603_10V6K@

1U_0603_10V6K@

2

R780

Q124

2

IN

12

R644

R644 470_0603_5%

470_0603_5%

@

13

D

Q107

S

2N7002_SOT23

@

+5VALW

12

@R780

@

1

OUT

GND

DTC124EKAT146_SC59-3

3

B

+3VALW TO +3VS+5VALW TO +5VS

+3VALW +3VS

1

C723

4.7U_0603_6.3V6K @

2

SUSP

G

SUSP

@

2

G

@ R652

@

220K_0402_5%

SUSP<6>

DTC124EKAT146_SC59-3

SUSP#<43,52,53,54>

2

12

R647

R647 470K_0402_1%

470K_0402_1%

13

D

S

R652

SUSP

Q111

Q111 2N7002_SOT23

2N7002_SOT23

+RTCVCC

U39

AP4800BGM_SOP8L-8

8 7

5

4

R650

R650 0_0402_5%

0_0402_5%

1 2

+3VLP

12

R653

R653 220K_0402_5%

220K_0402_5%

1 2

Q117

1

OUT

2

IN

GND

3

@

1 2 36

1

C727

0.01U_0402_25V6

2

C

D

E

+3VALW TO +3VALW(PCH AUX Power)

1

C724

4.7U_0603_6.3V6K@

2

1

2

C725

C725 1U_0603_10V6K@

1U_0603_10V6K@

12

13

D

S

R645

R645 470_0603_5%

470_0603_5%

2

SUSP

G

Q108

Q108 2N7002_SOT23

2N7002_SOT23

+5VALW

R778

1 2

47K_0402_5%

@

DS3_EN

C782

4.7U_0603_6.3V6K

13

2

G

+3VALW +3V_PCH

JUMP_43X79

1

@C782

@

2

D

@

Q120

Q120 2N7002K_SOT23-3

2N7002K_SOT23-3

S

PJ1

@

2

112

3 1

@

Q121

LP2301ALT1G_SOT23-3

2

1

@

C781

0.1U_0402_16V7K

2

4.7U_0603_6.3V6K

1

@

2

C783

SLP_SUS

@

1U_0603_10V6K

1

C780

2

12

13

D

S

@

R777

R777 470_0603_5%

470_0603_5%

2

G

@

Q118

Q118 2N7002K_SOT23-3

2N7002K_SOT23-3

+1.5VS +1.05VS

12

3 3

4 4

13

D

S

R655

R655 470_0603_5%

470_0603_5%

@

2

SUSP

G

Q113

Q113 2N7002_SOT23

2N7002_SOT23

@

A

12

R659

R659 470_0603_5%

470_0603_5%

@

13

D

S

2

SUSP

G

Q116

Q116 2N7002_SOT23

2N7002_SOT23

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DC Interface

LA-9641P

E

47 61Friday, April 19, 2013

1.0

5

PF101

12A_65V_451012MRL

21

PQ102A

APDIN1

2

D D

C C

JDCIN1

1 2 3 4

ACES_50312-00541-001

5

@

VIN

1 2 3 4 5

ADP_ID

PR110

1 2

100K_0402_1%

+3VALW

12

PR111

APDIN

PR103

1 2

750_0402_1%

100K_0402_1%

2N7002KDW-2N_SOT363-6

6 1

34

5

PQ102B

2N7002KDW-2N_SOT363-6

12

PC101

1000P_0402_50V7K

12

PC108

0.1U_0402_16V7K

ADP_ID_CLOSE

4

FBMA-L11-453215800LMA90T_2P

1 2

FBMA-L11-453215800LMA90T_2P

1 2

12

PC102

100P_0402_50V8J

12

PC109

680P_0402_50V7K

PL101

PL102

135W@PL102

135W@

ADP_ID

3

2

1

VIN

12

PC103

PC104

100P_0402_50V8J

1000P_0402_50V7K

+5VS

H_PROCHOT#

PU101A

61

2

PQ101A

B B

PD101

S SCH DIO BAS40CW SOT-323

+RTCBATT

2

1

3

+CHGRTC

PR102

1K_0603_1%

1 2

PR101

1K_0603_1%

1 2

+CHGRTC_R

1 2 3 4

+3VLP

JRTC1

@JRTC1

@

1 2 GND GND

ACES_50271-0020N-001

RTC Battery

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

PQ101A

H_PROCHOT#

PQ101B

3

2N7002KDW-2N_SOT363-6

34

2N7002KDW-2N_SOT363-6

12

PD105

1N4148WS-7-F_SOD323-2

5

12

PD104

1N4148WS-7-F_SOD323-2

2010/01/25 2012/07/11

0.022U_0402_16V7K

PR104

1 2

1.5M_0402_5%

0.022U_0402_16V7K

PR105

1 2

1.5M_0402_5%

Compal Secret Data

PC105

12

PC106

12

Deciphered Date

PR106

1 2

PR107

1 2

PU101B

AS393MTR-E1 SO 8P OP

47K_0402_1%

1

47K_0402_1%

7

PU101A AS393MTR-E1 SO 8P OP

AS393MTR-E1 SO 8P OP

8

P

+

O

-

G

4

+5VS

8

P

+

O

-

G

4

2

3

2

5

6

BATT_TEMP

+3VALW

PR108

1 2

10K_0402_1%

12

PR109

1 2

100K_0402_1%

100P_0402_50V8J

100K_0402_1%

Compal Electronics, Inc.

Title

PWR DCIN / RTC Battery

Size Document Number Rev

Custom

LA-9641P

Date: Sheet of

1

ACIN

PC107

48 59Monday, April 22, 2013

1.0

5

4

3

2

1

JBATT1 -15" JBATT2 -14"

@

JBATT1

1 2 3 4 5 6

D D

7 GND GND

@

SUYIN_200082GR007M229ZR

JBATT2

1

2

3

4

5

6

7 GND GND

SUYIN_200082GR007M229ZR

C C

VMB2

1 2 3 4 5 6 7 8 9

EC_SMCA

EC_SMDA

PR201

100_0402_1%

100_0402_1%12PR204

12

100_0402_1%

PR204

100_0402_1%

VL

PR206

1 2

6.49K_0402_1%

1 2

PR207

PR207 10K_0402_5%

10K_0402_5%

PR209

1 2

6.49K_0402_1%

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

21

@PR206

@

VL

12

PC202

PR202

PR202 75K_0402_1%

75K_0402_1%

1 2

BATT_TEMP<43,48,49>

B B

PR213

@PR203

@

PR203

@PR217

@

A A

PR217

12

PC207

1 2

PC207

100K_0402_1%

75K_0402_1%

100K_0402_1%

100P_0402_25V8K

+3V_LDO

@PC209

@

12

PC209

100P_0402_25V8K

PC202

0.01U_0402_25V7K

3

+

2

-

5

6

5

PR210

8

4

+

-

1 2

P

1

O

G

PU201A

AS393MTR-E1 SO 8P OP

VLVMB

@PR212

@

PR212

8

P

7

O

G

PU201B

AS393MTR-E1 SO 8P OP

4

47K_0402_1%

PC208

0.068U_0402_16V7K

PC210

1 2

0.068U_0402_16V7K

47K_0402_1%

12

VMB

+3VALW

+3VLP

12

PD201

1N4148WS-7-F_SOD323-2

@PC210

@

12

@PD203

@

PD203

1N4148WS-7-F_SOD323-2

PL201

SUPPRE_ KC FBCA-K5B-302540-L1-T 1812

1 2

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 <43,50>

EC_SMB_DA1 <43,50>

BATT_TEMP <43,48,49>

PR205

1 2

1.5M_0402_5%

@PR208

@

PR208

1 2

1.5M_0402_5%

4

12

A/D

2

G

BATT+

PC203

0.01U_0402_25V7K

13

D

S

Turbo_V<43>

100K_0402_1%

PROCHOT<43,49>

ADP_65<43>

ADP_90<43>

ADP_135<4 3>

5

PQ209

@

PQ209

@

2N7002KW_SOT323-3

BATT_LEN#<43>

PH201 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

ADP_I<43,50>

@

PR233

1 2

PR230

2

+3VALW

PR214

1 2

PR211

1 2

100K_0402_1%

61

2

34

PQ202B

2N7002KDW-2N_SOT363-6

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

PR230

1 2

25.5K_0402_1%

13

D

G

S

100K_0402_1%

PQ202A

2N7002KDW-2N_SOT363-6

+3VLP

PR220

1 2

100K_0402_1%

Issued Date

PQ206

2N7002KW_SOT323-3

2

G

2

G

3

PR229

1 2

9.31K_0402_1%

13

D

PQ208

S

2N7002KW_SOT323-3

2

G

13

D

PQ205

2N7002KW_SOT323-3

S

ECAGND

2010/01/25 2012/07/11

PR227

PR232

5.9K_0402_1%

1 2

13

D

PQ207

2N7002KW_SOT323-3

S

BATT_OUT <50>

1 2

8.45K_0402_1%

PR225

PR225 100K_0402_1%

100K_0402_1%

1 2

Compal Secret Data

+5VALWP

Deciphered Date

+3VS

@PR215

H_PROCHOT#<43,48,56,6>

PROCHOT<43,49>

B+

@PC211

@

12

+5VALWP

PC211

22U_0603_6.3V6M

2

@

PR215

1 2

13

D

@

2

ADP_OCP_1

G

PQ201

2N7002KW_SOT323-3

S

PR216 0_0402_5%

0_0402_5%

1 2

PJ202

PJ202 JUMP_43X39@

JUMP_43X39@

112

@

PU202

1

IN

OUT

2

GND

SHDN#3BYP

G9191-330T1U_SOT23-5

100K_0402_1%

@PR216

@

2

5

4

12

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

LA-96

Date: of

Date:

Friday, April 19, 2013 Sheet

NTC_V<43>

+VSB

12

PC213

4.7U_0402_4V6M

PC212

@PC212

@

1U_0402_6.3V6K

41P

+3V_LDO

@PC213

@

1

+EC_VCCA

12

PR226

12.7K_0402_1%

12

PH201

12

100K_0402_1%_TSM0B104F4251RZ

PR228

PR228 0_0402_5%

0_0402_5%

ECAGND

49 59

1.0

of

5

PQ301

PQ301 AO4407AL_SO8

AO4407AL_SO8

DTA144EUA_SC70-3

47K_0402_5%

13

2

PQ307A

PQ305

DTC115EUA_SC70-3

PR311

10K_0402_1%

1 2

PQ314

2

G

8 7

5

PQ304

2

1 3

PQ303

DTC115EUA_SC70-3

PR303

47K_0402_1%

1 2

2

ACOFF-1

13

D

S

2N7002KW_SOT323-3

4

VIN

D D

C C

B B

12

PR302

61

2

2N7002KDW -2N_SOT363-6

ACOFF<4 3>

BATT_OUT<49,50>

P2

1 2 36

12

PC302

0.1U_0603_25V7K

P2-1

12

P2-2

34

PQ307B

5

13

1 2 3 6

PR304

200K_0402_1%

12

13

D

PR305

S

150K_0402_1%

2N7002KDW-2N_SOT363-6

PQ302

65W@PQ302

65W@

AO4407AL_SO8

4

5600P_0402_25V7K

PR306

PR306 20K_0402_1%

20K_0402_1%

PQ306

2N7002KW_S OT323-3

2

G

PR308

1 2

64.9K_0402_1%

64.9K_0402_1% PC303

PC303

1 2

0.1U_0402_25V6

EC_SMB_DA1<43,49>

EC_SMB_CK1<43,49>

8 7

5

1 2

PC301

PQ302

90W@

AO4407AL_SO8

BATT_OUT <49,50>

VIN

12

PR309

392K_0402_1%

+3VALW

4

P3

PQ302

135W@

AO4423L_SO8

ADP_I<43, 49>

100P_0402_50V8J

PR315

200K_0402_1%

1 2

100K_0402_1%

1 2

PR316

PC304

PR301

0.01_1206_1%

1

2

ACPRN

6

ACDET

7

IOUT

8

SDA

BQ24737RGRR_VQFN20_ 3P5X3P5

9

SCL

10

12

ILIM

B+

4

3

ACP

0.1U_0402_25V6

5

4

ACOK

CMPIN

PU301

SRN12BM

11

12

PR317

6.8_0402_5%

PC306

0.1U_0402_25V6

PC307

1 2

3

CMPOUT

SRP

13

12

1 2

PC318

10U_0805_25V6K

ACN

PC308

0.1U_0402_25V6

12

1

2

ACP

GND

15

14

PR318

10_0402_5%

3

1 2

PL301

1UH_PCMB061H-1R0M S_7A_20%

1 2

PC310

10U_0805_25V6K

PC311

12

0.1U_0402_25V6

ACN

21

TP

20

19

18

17

16

DH_CHG-1

BST_CHG

12

PC312

PC312 1U_0603_25V6K

1U_0603_25V6K

BQ24737VCC

VCC

PHASE

HIDRV

BTST

REGN

LODRV

1 2

PC313

10U_0805_25V6K@

P2

PR319

10_1206_5%

1 2

PC314

1 2

1U_0603_25V6K

PR326

1 2

0_0603_5%

2.2_0603_5%

PD301

RB751V-40_SOD323-2

1 2

12

BQ24737VDD

DL_CHG

PR320

1 2

PC315

LX_CHG

0.047U_0603_16V7K

10U_0805_25V6K

PC317

2

CHG_B+

PQ312

AO4407AL_SO8

1 2 3 6

4

ACOFF-1

PD302

1SS355_SOD323-2

1 2

PD303

1SS355_SOD323-2

0.01_1206_1%

1

CHG

2

SRP

10U_0805_25V6K

6

578

6

578

123

DISCHG_G

1 2

DISCHG_G-1

13

PQ309

PQ310

MDS1521URH 1N SO8

PR322

200K_0402_1%

1 2

PR321

PR321 47K_0402_1%

47K_0402_1%

PQ311

DTC115EUA_SC70-3

2

MDS1525URH 1N SO8

PL302

1 2

12

PR323

24737_SN

12

PC320

PL302

4.7_1206_5%

680P_0603_50V7K

10UH_PCMB104T-100MS _6A_20%

1 2

PC319

PC316

10U_0805_25V6K

DH_CHGPACIN

12

PC319

4

PC324

PR324

1 2

12

0.1U_0402_25V6

SRN

8 7

5

PR325

PR325 200K_0402_1%

200K_0402_1%

4

3

1

VIN

PQ313

2N7002KW_S OT323-3

13

D

2

PACIN

G

S

12

PC322

10U_0805_25V6K

PC323

12

10U_0805_25V6K

BATT+

12

PC305

0.1U_0402_25V6

BQ24737VDD

PR314

10K_0402_1%

12

PR307

ACPRN

A A

5

12

PR310

PR310 10K_0402_1%

10K_0402_1%

47K_0402_1%

PQ308

13

D

2

G

S

10K_0402_1%

1 2

PACIN

12

PR312

12K_0402_1%

2N7002KW_SOT323-3

4

ACIN <15,24,43,48>

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

3

12

PC309

0.1U_0402_25V6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/07/112010/01/13

2

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER-BQ24737

LA-9641P

50 59Friday, April 19, 2013

1

1.0

A

1 1

B+

PL401

HCB2012KF-121T50_0805

1 2

@PC433

@

@PC403

@

12

PC433

PC403

0.1U_0402_25V6

2 2

B+

PL403

HCB2012KF-121T50_0805

1 2

@PC434

@

12

PC434

PC420

0.1U_0402_25V6

10U_0805_25V6K

3 3

0.1U_0402_25V6

PC416

12

10U_0805_25V6K

3V_VIN

12

PC404

2200P_0402_50V7K

5V_VIN

12

PC417

2200P_0402_50V7K

2.2K_0402_5%

PC405

PR407

12

10U_0805_25V6K

@PC418

@

PC418

0.1U_0402_25V6

12

EC_ON<43>

PR408

MAINPWON<43>

4 4

PR408

0_0402_5%

12

PC406

12

5V_VCC

PC422

12

PR409

1M_0402_1%

12

10U_0805_25V6K

4.7U_0603_6.3V6M

12

7

8

9

PU402

8

IN

9

GND

5

VCC

2

PG

SY8208CQNC_QFN10_3X3

3V5V_EN

PC431

4.7U_0402_6.3V6M

0_0402_5%

PU401

IN

EN1

IN

EN2

BS

OUT

GND

PG2LDO

SY8208BQNC_QFN10_3X3

ENLDO_3V5V_1

EN1

EN2

BS

LX

OUT

LDO

PR415

1

3VALW_EN

3

6

BST_3V

10

LX

4

5

1

3V5V_EN

3

ENLDO_3V5V_1

6

BST_5V

10

4

7

B

12

ENLDO_3V5V

1 2

0_0603_5%

12

PR412

1 2

0_0402_5%

ENLDO_3V5V_1

12

PC430

PR421

+3VLP

PC414

4.7U_0603_6.3V6M

@PR412

@

ENLDO_3V5V

6800P_0402_25V7K

PR422

1 2

0_0603_5%

VL

4.7U_0603_6.3V6M

BST_3V_1

PC419

1 2

BST_5V_1

PR411

@PR411

@

0_0402_5%

PC435

1 2

0.01U_0402_50V7K

PC402

1 2

0.1U_0603_25V7K

LX_3V

PR413

1 2

1K_0402_1%

PC421

0.1U_0603_25V7K

1 2

LX_5V

12

ENLDO_3V5V

PR414

1 2

1K_0402_1%

PL402

1 2

1.5UH_PCMC063T-1R5MN_9A_20%

12

PR404

4.7_1206_5%

3V_SN

12

PC415

680P_0603_50V7K

1 2

1.5UH_PCMB063T-1R5MS_9A_20%

12

PR406

4.7_1206_5%

5V_SN

12

PC429

680P_0603_50V7K

PL404

C

3VALW_EN

12

D

PR410

12

0_0402_5%

@PC432

@

PC432

4.7U_0402_6.3V6M

ENLDO_3V5V

3V5V_EN

PR402

499K_0402_1%

12

PR403

PC407

150K_0402_1%

1U_0603_25V6K

12

E

B+

+3VALWP

12

PC409

PC408

22U_0805_6.3V6M

12

PC423

PC424

22U_0805_6.3V6M

12

@PC410

@

PC410

22U_0805_6.3V6M

12

PC425

22U_0805_6.3V6M

12

PC412

PC411

22U_0805_6.3V6M

PC426

22U_0805_6.3V6M

PC413

22U_0805_6.3V6M

PJ401

@PJ401

@

+5VALWP

12

@PC428

@

PC427

PC428

22U_0805_6.3V6M

+3VALWP +3VALW

+5VALWP

112

JUMP_43X118

PJ402

@PJ402

@

112

JUMP_43X118

2

+5VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/10/03 2014/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PWR- 3VALWP/5VALWP

LA-9641P

Friday, April 19, 2013

E

51Friday, April 19, 2013

51

1.0

61

A

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0

Hi Hi

S3

S4/S5

1 1

HiLo

Lo Lo

On

Off

On

Off (Hi-Z)

Off Off

Note: S3 - sleep ; S5 - power off

+0.675VSP

12

PC504

PC505

10U_0805_25V6K

+VTT_REFP

12

PC506

PR505

0_0402_5%

1 2

PC506

0.033U_0402_16V7K

0.1U_0402_16V7K

2 2

PR502

49.9K_0402_5%

SUSP#

1 2

SYSON<43>

12

PC503

0.1U_0402_16V6K

PC508

PU501

21

PAD

1

VTTGND

2

VTTSNS

3

GND

4

VTTREF

5

VDDQ

12

@PC508

@

PR506

10K_0402_1%

B

+1.35VP

2

@PJ503

@

2

1

PJ503

JUMP_43X39

1

BST_1.35V BST_1.35V-1

18

19

VLDOIN

S3

7

S3_1.35V

17

BOOT

UGATE

S5

TON

8

9

S5_1.35V

PR507

8.2K_0402_1%

20

VTT

RT8207MZQW _WQFN20_3X3

FB

6

12

PR501

2.2_0603_5%

1 2

16

PHASE LGATE

PGND

CS

VDDP

VDD

PGOOD

10

PR509

887K_0402_1%

12

15

14

13

12

11

12

PR511

6.65K_0402_1%

1.35V_B+

UG_1.35V

LX_1.35V

PC510

1U_0603_10V6K

PC512

0.1U_0603_25V7K

1 2

LG_1.35V

12

PC511

1U_0603_10V6K

PR514

5.1_0603_5%

5

MDU1516URH_POW ERDFN56-8-5

4

123

5

4

123

12

+5VALW+1.35VP

PQ501

PQ502

C

1.35V_B+

@PC509

@

@PC520

@

12

PC520

PC501

10U_0805_25V6K

PL501

1UH_PCMB104T-1R0M H_18A_20%

12

@PR515

@

PR515

4.7_1206_5%

1.35V_SN

12

@PC517

@

PC517

MDU1511RH_POWERDFN56-8-5

680P_0603_50V7K

12

PC509

PC513

0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

12

PL502

1 2

HCB2012KF-121T50_0805

D

B+

+1.35VP

1

+

PC522

2

330U_2.5V_M

+1.35VP OCP min 20A OVP min 1.485V

PJ505

2

112

JUMP_43X118@

PJ504

+1.35VP +1.35V

2

112

JUMP_43X118@

PJ506

2

112

JUMP_43X79

@

3 3

4 4

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2010/01/25 2012/07/11

Compal Secret Data

Deciphered Date

C

Title

Size D ocument Number Rev

Custom

Date: Sheet of

@

Compal Electronics, Inc.

+1.35V_DDR

LA-9641P

D

+0.675VS+0.675VSP

52

1.0

61Friday, April 19, 2013

5

PL603

D D

B+

PL603

HCB2012KF-121T50_0805

1 2

+3VS

PC617

12

@PR 604

@

PR604

0_0402_5%

ILMT_1.5V

12

@PR 605

@

PR605

0_0402_5%

C C

PC617

4

PU601

8

12

@PC 603

@

PC603

0.1U_0402_25V6

2200P_0402_50V7K

B+_1.5V

12

PC604

10U_0805_25V6K

+1.5VS_PWRGD<43>

ILMT_1.5V

PR602

12

IN

9

GND

3

ILMT

2

PG

SY8208DQNC_QFN10_3X3

10K_0402_1%

1

PC602

EN

0.1U_0603_25V7K

6

1 2

BST_1.5V

BS

10

LX_1.5V

LX

4

FB

7

BYP

5

LDO

12

PC605

+3VALW

3

PR613

1 2

@ PR603

@

4.7_1206_5%

1 2

1.5UH_PCMB063T-1R5MS_9A_20%

+3VALW

12

PC606

4.7U_0603_6.3V6K

+3VALW

12

1M_0402_1%

PR603

SNB_1.5V

PL601

1 2

PR601

40.2K_0402_1%

PC637

PC637 .1U_0402_16V7K

.1U_0402_16V7K

@ PC 601

@

680P_0603_50V7K

1 2

12

PC601

12

20K_0402_1%

PJ605

1 2

PAD-OPEN 3x3m

PR608

@

PR607

30.1K_0402_1%

SUSP# <43,47,52,54>

12

PC607

330P_0402_50V7K

12

PC626

PC626 22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC608

22U_0805_6.3VAM

+1.8V_VIN

PC625

22P_0402_50V8J

PR625

20K_0402_1%

1 2

2

1

+1.5VSP

12

PC611

22U_0805_6.3VAM

PU603

4

IN

5

PG

FB6EN

SY8032ABC_SOT23-6

12

@PC 612

@

PC612

22U_0805_6.3VAM

3

LX

2

GND

1

PR626

60.4K_0402_1%

1 2

+1.8V_EN

12

PD601

@PD601

PR623

PC619

1 2

47K_0402_1%

0.1U_0402_25V6

@

RB751V-40_SOD323-2

12

+1.5VSP

+1.8VGSP

+0.95VGSP

1UH_PHT32251B-1R0MS_2.34A_20%

+1.8V_LX

DGPU_PWR_EN<15,25,43,53,55>

1 2

12

@PR 614

@

PR614

+1.8V_SNUB

@PC 613

@

12

PC613

PJ602

2

112

JUMP_43X118@

PJ603

2

112

JUMP_43X118@

PJ606

2

112

JUMP_43X118@

PL604

12

PC618

4.7_1206_5%

1000P_0603_50V7K

22U_0805_6.3V6M

+1.5VS

+1.8VGS

+0.95VGS

+1.8VGSP

12

PC620

22U_0805_6.3V6M

12

PC609

PC610

22U_0805_6.3VAM

+1.8V_FB

12

PR624

PR624 10K_0402_1%

10K_0402_1%

1 2

B B

PL606

HCB2012KF-121T50_0805

1 2

B+

+3VS

12

PR618

0_0402_5% @

ILMT_0.95V

12

PR609

0_0402_5% @

A A

0_0402_5% @

5

12

@PC 636

@

PC621

PC636

0.1U_0402_25V6

2200P_0402_50V7K

B+_0.95V

12

PC627

10U_0805_25V6K

4

ILMT_0.95V

PU604

8

IN

9

GND

3

BYP

ILMT

2

PG

LDO

SY8208DQNC_QFN10_3X3

1

EN

6

BST_0.95V

BS

10

LX

4

FB

7

5

PC632

0.1U_0603_25V7K

1 2

LX_0.95V

12

PC630

4.7U_0603_6.3V6K

0.95V_EN

PR616

1 2

1M_0402_1%

@ PR610

@

4.7_1206_5%

1 2

PL605

1.5UH_PCMB063T-1R5MS_9A_20%

1 2

+3VALW

12

PC628

4.7U_0603_6.3V6K

PC638

PC638 .1U_0402_16V7K

.1U_0402_16V7K

1 2

PR610

SNB_0.95V

PR612

12

82.5K_0402_1%

PC634

@ PC634

@

680P_0603_50V7K

1 2

3

DGPU_PWR_EN <15,25,43,53,55>

12

PR611

12

PR615

100K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

12

PC629

PC635

59K_0402_1%

220P_0402_50V7K

12

PC631

PC633

22U_0805_6.3VAM

2010/01/25 2012/07/11

+0.95VGSP

12

PC622

22U_0805_6.3VAM

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

1.5V_VRAM/1.8V/0.95V

Size Document Number Rev

C

LA-9641P

Date: Sheet

Friday, April 19, 2013

1

53Friday, April 19, 2013

53

of

61

1.0

5

D D

PR702

0_0402_ 5%

1.05VS_EN<43>

SUSP#<43,47,52,53>

C C

B B

1 2

PR701

@PR701

@

20K_040 2_1%

1 2

@PR706

@

PR706

PR704

1 2

10.7K_0402_1%

12

PC702

0.1U_0402_25V6

PC704

10.7K_0402_1%

1 2

PR705

12K_0402_1%

1 2

1000P_0402_50V7K

4

12

@PC701

@

1 2

PC701

1M_0402_1%

PC703

0.01UF_0 402_25V7K

PR707

PR707 10_0402 _5%

10_0402 _5%

.1U_0402_16V7K

1

2

3

4

PC706

1 2

0.01UF_0 402_25V7K

1 2

PC705

PC705 1000P_0 402_50V7K

1000P_0 402_50V7K

1 2

1.05V_EN

17

PU701

PAD

VREF

REFIN

TPS5121 9RTER_QFN16_ 3X3

GSNS

VSNS

COMP5TRIP6GND

PR711

PR709

10_0402 _1%

3

PC707

PR713

SW

DH

DL

V5

PR713

2.2_0603 _5%

1 2

12

11

10

9

LX_1.05V SP

DH_1.05V SP

PR712

100K_0402_1%

1 2

16

15EN14

PGOOD

12

45.3K_0402_1%

BST_1.05 VSP

13

MODE

BST

PGND

8

7

PC707

0.1U_060 3_25V7K

1 2

BST_1.05 VSP_1

DL_1.05V SP

12

PC708

1U_0603 _10V6K

4

+5VALW

6

578

6

578

123

2

1.05VSP_ B+

PC711

PQ701

PQ702

MDS1521URH 1N SO8

PC711

2200P_0402_50V7K

MDS1525URH 1N SO8

1 2

3.3UH_PCMB063T-3R3MS_ 6.5A_20%

12

PR714

4.7_1206_5%

@

12

PC709

1000P_0603_50V7K

@

12

PL701

1

PJ701

2

112

JUMP_43 X118@

PL702

HCB2012 KF-121T50_080 5

1 2

@PC715

@

@PC713

@

12

PC713

PC712

10U_0805_25V6K

12

PC715

0.1U_0402_25V6

4.7U_0805_25V6-K

+1.05VS+1.05VSP

B+

+1.05VSP

1

+

PC714

2

+1.05VP

220U_6.3V_M

OCP min 8A OVP min 1.24V

A A

Security Class ification

2010/01/ 25 2012/07/ 11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/ 25 2012/07/ 11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+1.05VS

Size Do cument Number Rev

Custom

LA-9641P

Date: Sheet o f

2

Friday, April 19, 2013

54Friday, April 19, 2013

54

1

1.0

61

A

+3VGS

B

C

D

VGA Boot Up Voltage Setting Sun Pro:0.9V(0110000) Mars XT:0.85V(0110100)

PR817

Mars@PR817

Mars@

2.2_0603_5%

12

PR847

Sun@

7.5K_0402_1%

BOOT1_VGA

UGATE1_VGA

PR852

2.2_0603_5%

PHASE1_VGA

LGATE1_VGA

PQ801

Mars@PQ801

PC806

0.22U_0603_10V7K

1 2

UGATE2_VGA

LGATE2_VGA

Mars@PC806

Mars@

PHASE2_VGA

Mars@

CSD87351Q5D_SON8-7

2

3

4

1

8

+VGA_CORE

12

PC825

PC824

2.2U_0402_6.3V6M

12

PC841

PC840

10U_0603_6.3V6M

PC858

0.22U_0603_10V7K

1 2

12

2.2U_0402_6.3V6M

12

10U_0603_6.3V6M

12

BOOT1_1_VGA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

12

PC826

PC827

2.2U_0402_6.3V6M

12

PC843

PC842

10U_0603_6.3V6M

CSD87351Q5D_SON8-7

2011/06/30 2012/12/31

C

PC829

PC828

2.2U_0402_6.3V6M

12

PC845

PC844

10U_0603_6.3V6M

PQ802

2

3

4

Compal Secret Data

12

PC830

2.2U_0402_6.3V6M

12

PC846

10U_0603_6.3V6M

1

8

Deciphered Date

<24>

12

PR859

11K_0402_1%

1 2

PR807 10K_0402_1%@PR807 10K_0402_1%@

GPU_VID5

GPU_VID1

PC812

PC812 1U_0603_10V6K

1U_0603_10V6K

1 2

PC872

PC872 1U_0603_10V6K

1U_0603_10V6K

PR844 0_0402_5%@PR844 0_0402_5%@

1 2

0.047U_0402_16V7-K

PR853

1 2

PR808 10K_0402_1%@PR808 10K_0402_1%@

GPU_VID4

<24>

GPU_VID0

1 2

Mars@PR847

Mars@

PR847

11K_0402_1%

12

2.61K_0402_1%

NTC_VGA

12

PH802

PH802 10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

Layout Note: Place near Phase1 Choke

B

1 2

PR810 10K_0402_1%Sun@ PR810 10K_0402_1%Sun@

PR809 10K_0402_1%PR809 10K_0402_1%

PR811 10K_0402_1%PR811 10K_0402_1%

GPU_VID3

GPU_VID2

GPU_VID1

<24>

BOOT2_VGA BOOT2_2_VGA

+5VS

GPU_IMON <43>

VSSSENSE_VGA <27,55>

VSUM+_VGA

VSUM-_VGA

1 2

PR812 0_0402_5%PR812 0_0402_5%

GPU_VID0

1 2

PR801 10K_0402_1%PR801 10K_0402_1%

PR802 10K_0402_1%PR802 10K_0402_1%

GPU_VID5

PR814

0_0402_5%

35

VID4

VIN

17

16

VDD_VGA

VIN_VGA

12

PC876

@PR 851

@

PR851

82.5_0402_5%

@PC 864

@

PC864

0.01U_0402_25V7K

PR862

1.1K_0402_1%

1 2

PR862

Sun@

845_0402_1%

IMON18BOOT119UGATE1

1U_0603_10V6K

UGATE2

20

12

PR803 10K_0402_1%@PR803 10K_0402_1%@

GPU_VID3

GPU_VID4

GPU_VID5

VID031VID132VID233VID334VID536VID6

30

BOOT2

29 28

PHASE2

27

VSSP2

26

LGATE2

25

VCCP

24

PWM3

23

LGATE1

22

VSSP1

21

PHASE1

ISL62883CHRTZ-T_TQFN40_5X5

PR845 0_0402_5%PR845 0_0402_5%

1 2

PR848

1_0402_5%

1 2

PC877

0.22U_0603_25V7K

Sun@PC860

Sun@

PC860

.1U_0603_25V7K

Mars@PR862

Mars@

PR813

@PR813

@

147K_0402_1%

1 2

PR820

1 2

0_0402_5%

PC805

1 2

.1U_0402_16V7K

CLK_ENABLE#_VGA

PSI#_VGA

RBIAS_VGA

1 2 3 4 5 6 7 8

FB_VGA

9

10

41

PR864 0_0402_5%

0_0402_5%

1 2

+5VS

12

Mars@PC875

Mars@

Mars@PC850

Mars@

PC875

PC850

0.22U_0402_10V6K

PC859

PC862

PC860

Mars@

0.22U_0603_10V7K

VRON_VGA

@PC805

@

PU801

PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2

AGND

Sun@PR864

Sun@

VSEN_VGA

0.22U_0402_10V6K

12

39

40

CLK_EN#

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

@PC 863

@

12

PC863

330P_0402_50V7K

1 2

GPU_VID6

37

38

VR_ON

DPRSLPVR

RTN_VGA

ISUM-_VGA

12

VSUM_VGA_N001

12

+3VGS

PR832

PR832 0_0402_5%

0_0402_5%

1 2

GPU_GPIO0<24,55>

1K_0402_1%

12

5.9K_0402_1%

PC847

1 2

FB2_VGA

PR843

Sun@

12

PC873

PR846

Mars@PR846

Mars@

1 2

221K_0402_1%

+VGA_CORE

VCCSENSE_VGA<27>

VSSSENSE_VGA<27,55>

DGPU_PWR_EN<15,25, 43,53>

EC_VGA_EN<43>

+3VGS

1000P_0402_50V7K

12

PR831

1.91K_0402_1%

+3VGS

499_0402_1%

1 2

1.4K_0402_1%

1 2

ISEN2_VGA

12

ISEN1_VGA

PR849 30K_0402_1%

30K_0402_1%

PR816

2.2K_0402_1%

1 2

PR818

1 2

0_0402_5%

PR819

1 2

2.2K_0402_1%

2.2K_0402_1% PR830

1.91K_0402_1%

1 2

VW_VGA

PR842

FB1_VGA

PR843

Mars@PR843

Mars@

Sun@PR849

Sun@

1 2

10_0402_1%

1 2

0_0402_5%

1 2

10_0402_1%

A

@PR816

@

@PR818

@

DPRSLPVR_VGA-1

@PR830

@

PR833

2.2K_0402_1%

1 2

PR834

0_0402_5%

PR835

1 2

2.2K_0402_1%

PR836

147K_0402_1%

1 2

PC871

22P_0402_50V8J

PC874

1 2

390P_0402_50V7K

PR863

Sun@PR863

Sun@

0_0402_5%

1 2

PR850

PR854

PR860

1 2

0_0402_5%

PR861

@PR834

@

@PR835

@

12

COMP_VGA

ISEN3_VGA

12

VSUM-_VGA

330P_0402_50V7K

1000P_0402_50V7K

1 1

GPU_GPIO0<24,55>

DGPU_PWROK

2 2

@PR 840

@

PR841

PR840

1 2

249K_0402_1%

33P_0402_50V8J

3 3

4 4

1 2

PC848

150P_0402_50V8J

PR846

Sun@

158K_0402_1%

PR849

Mars@

40.2K_0402_1%

1 2

PR806 10K_0402_1%@PR806 10K_0402_1%@

PR804 10K_0402_1%Mars@ PR804 10K_0402_1%Mars@

PR805 10K_0402_1%@PR805 10K_0402_1%@

GPU_VID2

GPU_VID1

GPU_VID0

<24>

GPU_VID2

GPU_VID3

GPU_VID4

+VGA_B+

PC849

+5VS

Sun@PC861

Sun@

12

PC861

0.047U_0603_25V7K

12

PC866

0.1U_0402_16V7K

+VGA_B+

Mars@PC804

Mars@

Mars@PC803

12

SW2_VGA

PC833

2.2U_0402_6.3V6M

12

0.1U_0402_25V6

12

4.7_1206_5%

SNUB1_VGA

12

680P_0402_50V7K

12

PC853

@PC 802

@

PC802

2200P_0402_50V7K

Mars@PR827

Mars@

PR827

PC834

12

1U_0402_6.3V6K

PC879

2200P_0402_50V7K

SW1_VGA

Mars@

12

PC803

10U_0805_25V6K

12

3.65K_0402_1%

ISEN2_VGA

VSUM+_VGA

12

PC835

2.2U_0402_6.3V6M

12

PC854

1U_0402_6.3V6K

12

PC880

10U_0805_25V6K

12

PR856

3.65K_0402_1%

VSUM+_VGA

12

PC804

10U_0805_25V6K

PL802

0.22UH_PCME064T-R22MS_28A_20%

1

2

Mars@PR828

Mars@

PR828

10K_0402_1%

12

PC837

PC836

2.2U_0402_6.3V6M

12

PC856

PC855

0.1U_0402_10V7K

+VGA_B+

12

PC881

10U_0805_25V6K

0.22UH_PCME064T-R22MS_28A_20%

1

2

LF1_VGA

12

Mars@PR857

Mars@

PR857

10K_0402_1%

ISEN1_VGA

Title

Size Document Number Rev

Date: Sheet of

@PC 801

@

PC801

0.1U_0402_25V6

7 6 5

12

PR826

4.7_1206_5%

SNUB2_VGA

12

PC811

680P_0402_50V7K

12

2.2U_0402_6.3V6M

10U_0603_6.3V6M

12

PC831

PC832

2.2U_0402_6.3V6M

12

PC852

PC851

1U_0402_6.3V6K

@PC 878

@

PC878

7 6 5

Mars@PR855

Mars@

PR855

Mars@PC865

Mars@

PC865

PL801

HCB4532KF-800T90_1812

1 2

Mars@PL802

Mars@

4

3

V2N_VGALF2_VGA

12

PC839

PC838

2.2U_0402_6.3V6M

12

PC857

0.1U_0402_10V7K

PL803

4

3

V1N_VGA

Compal Electronics, Inc.

VGA_COREP

Friday, April 19, 2013

12

Mars@PR829

Mars@

1_0402_1%

PR829

VSUM-_VGA

LA-9641P

D

1

+

2

12

PR858

1_0402_1%

VSUM-_VGA

B+

+VGA_CORE

1

+

PC807

2

330U_D2_2V_Y

1

Mars@

+

PC808

PC809

2

PC810

330U_D2_2V_Y

+VGA_CORE

61

330U_D2_2V_Y

1.0

330U_D2_2V_Y

55Friday, April 19, 2013

55

5

D D

Place close to phase 1 inductir

C C

PC902

330P_0402_50V7K

1 2

PR902

49.9_0402_1%

1 2

PR903

1K_0402_1%

VSSSENSE<10,11>

VCCSENSE<10>

B B

PR945

1 2

0.1U_0402_10V7K

PR946

1 2

0.1U_0402_10V7K

PR947

1 2

0.1U_0402_10V7K

PR948

@

1 2

0_0402_5%

PC989

560P_0402_50V7K

1 2

A A

ALER# pull high at HW side need to confirm HW circuit

@PC989

@

VR_SVID_DAT<10>

VR_SVID_ALRT#<10>

VR_SVID_CLK<10>

PR904

37W@

10K_0402_1%

37W=10K 47W=7.5K

PR904

47W@PR904

47W@

1 2

7.5K_0402_1%

12

PC903

1000P_0402_50V7K

1 2

0_0402_5%

PR905

12

PH901

220K_0402 _5%_ERTJ0EV224J

1K_0402_1%

PC904

10P_0402_25V8K

1 2

+5VS

PR906

130_0402 _1%

1 2

Close VR side

4

PR901

75K_0402_ 1%

1 2

PR907

+VCCIO_OUT

165K_0402_1%

1 2

CPU_B+

IMVP_IMON<43>

1 2

12

PC905

0.01U_040 2_25V7K

1 2

PR909

1K_0402_5%

1 2

PC906

2200P_0402_50V7K

1 2

PR908

2_0603_5%

PR910

54.9_040 2_1%

1 2

PR911

PR913

37W@

10K_0402_1%

24.3K_0402_1%

1 2

470P_0402_50V7K

PC907

1 2

H_PROCHOT#<43,48,49,6>

2.2U_0603 _10V7K

SDIO

ALERT#

SCLK

PR912

PC908

PC901

1 2

1000P_040 2_50V7K

12

VR_ON<43>

1 2

PC910

1 2

820P_0402 _50V7K

1 2

PC909

PC909 .1U_0402_16V7K

.1U_0402_16V7K

CSCOMP

37W=10K 47W=15.4K

PR913

47W@PR913

47W@

15.4K_0402_1%

PR914

0_0402_5%

1 2

PR915

0_0402_5%

1 2

3

PR918

121K +-1% 0603

1 2

PR919 121K +-1% 0603

121K +-1% 0603

1 2

121K +-1% 0603

1 2

PC911

1 2

1000P_040 2_50V7K

CSP3

CSP2

CSP1

CSSUM

PU901

24

25

19

22

21

23

26

CSREF

CSSUM

CSCOMP

EN1VRHOT#2SDIO3ALERT#4ROSC7SCLK

SDIO

ALERT#

0.1U_0402 _25V6K

20

NCP81103MNTWG_QFN36_5X5

BST3

CSP3

CSP1

CSP2

DRON

PWM2/IMAX

PVCC PGND

VR_RDY

TSENSE

INT_SEL

5

6

8

9

TSENSE

SCLK

VR_RDY

PR917

34.8K_0402_1%

1 2

12

PR916

1.91K +-1 % 0402

27

28

ILIM

29

IOUT

30

VRMP

31

COMP

32

FB

33

DIFFOUT

34

VSN

35

VSP

36

VCC

37

GND

@PR914

@

@PR915

@

@PC987

@

12

PC987

47W@PR919

47W@

PR920

PR922

66.5K_0402_1%

1 2

BST_CPU_Phase3

18

HG3

17

SW3

16

LG3

15 14 13

LG1

12

SW1

11

HG1

10

BST1

PR921

45.3K_0402_1%

1 2

PC912

PC912 .1U_0402_16V7K

.1U_0402_16V7K

1 2

SWN3

SWN2

SWN1

CSREF <57>

DRON <57>

47W@PR922

47W@

37W: @ 47W: INSTALL

PR922

37W@

43K_0402_1%

37W=43K 47W=66.5K

81103_PWM <57>

PR924

2.2_0603_5%

1 2

HG3 <57>

LG3 <57>

LG1 <57>

HG1 <57>

PR925

2.2_0603_5%

1 2

BST_CPU_Phase1

TSENSE

1 2

BST_CPU_Phase3-2

@PR923

@

PR923

+3VS

VGATE

<15,43>

Place close to phase 1 MOSFET

0.22U_0402_10V6K

2.2U_0603_10V7K

0.22U_0402_10V6K

BST_CPU_Phase1-1

12

PR942 0_0402_5%

0_0402_5%

@PH902

@

PH902

1 2

61.9K_040 2_1%

2

CSREF

12

CSP3

CSREF

12

CSP2

CSREF

12

CSP1

PC913

1 2

PC914

1 2

PC915

1 2

@PR942

@

VRHOT Assert Thr eshold : 472 mV TSENSE Bias Curr ent : 120 uA PRZ146=61.9K, 11 0C active

100K_0402 _1%_TSM0B104F42 51RZ

@PR926

@

PR926

PC916

20K_0402_ 1%

1 2

0.047U_04 02_16V7K

@PR927

@

47W@PC9 17

47W@

PR927

PC917

20K_0402_ 1%

1 2

0.047U_04 02_16V7K

@PR928

@

PC918

PR928

20K_0402_ 1%

1 2

0.047U_04 02_16V7K

SW3 <57>

+5VS

SW1 <57>

PR929

5.76K_0402_1%

12

37W: @ 47W: INSTALL

PR930

47W@PR930

47W@

5.76K_0402_1%

12

PR931

5.76K_0402_1%

12

CSP2

SWN3 <57>

SWN2 <57>

SWN1 <57>

+5VS

12

37W@PR93 2

37W@

PR932

2K_0402_1 %

37W: INSTALL 47W

: @

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/12/14 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: S heet of

Date: S heet

2

Date: S heet

CPU_CORE1

Friday, April 19, 2013

LA-9641P

1

1.0

of

56Friday, April 19, 2013

56

61

5

4

3

2

1

D D

B+

CPU_B+

5

PQ901

PR935

2K_0402_1%

4

5

PQ902

4

BSTA2 BSTA2_1

47W@PR935

47W@

12

EN_VCORE2

VCC_VCORE2

123

PR936

2.2_0603_5%

1 2

PU902 47W@

PU902 47W@ NCP81151MNTBG_DFN8_2X2

NCP81151MNTBG_DFN8_2X2

1

2

3

4

HG1<56>

SW1<56>

LG1<56>

C C

B B

81103_PWM<56>

DRON<56>

PR933 0_0402_5%

0_0402_5%

47W@PR933

47W@

12

47W@PC919

47W@

PC919

2.2U_0603_10V7K

+5VS

A A

12

PC920

10U_0805_25V6K

MDU1516URH_POWERDFN56-8-5

MDU1511RH_POWERDFN56-8-5

47W@PR936

47W@

9

BST

FLAG

8

PWM

DRVH

7

EN

SW

6

VCC

GND

5

DRVL

12

PC925

10U_0805_25V6K

PL902

0.22UH +-20% PCMB104T-R22MS 35A

1

4

3

12

PR937

SNUB_CPU1

12

PC922

12

47W@PC923

47W@

PC923

HG2

SW2

LG2

2

R22

0.

4.7_1206_5%

680P_0603_50V7K

0.22U_0402_10V6K

82mohm

PQ903

4

PQ904

4

V1N_CPU

PR939

PR939 10_0402_1%

10_0402_1%

47W@

5

MDU1516URH_POWERDFN56-8-5

123

5

MDU1511RH_POWERDFN56-8-5

123

47W@

12

+CPU_CORE

CSREF <56>

SWN1 <56>

12

47W@PR940

47W@

PR940

SNUB_CPU2

47W@PC930

47W@

12

PC930

12

0.22UH +-20% PCMB104T-R22MS 35A

4.7_1206_5%

680P_0603_50V7K

HG3<56>

SW3<56>

LG3<56>

CPU_B+

12

47W@PC933

47W@

47W@PC932

47W@

PC933

PC932

10U_0805_25V6K

47W@PR941

47W@

12

+CPU_CORE

SWN2 <56>

PL903

47W@PL903

47W@

1

4

3

2

PR941 10_0402_1%

10_0402_1%

V2N_CPU CSREF

PL901

FBMA-L11-453215800LMA90T_2P

1 2

1

+

PC986

2

220U_25V_M

5

123

5

123

PC986

MDU1516URH_POWERDFN56-8-5

MDU1511RH_POWERDFN56-8-5

PC985

PQ905

PQ906

4

PR944

10_0402_1%

CPU_B+

+CPU_CORE

12

CSREF

SWN3 <56>

1

+

2

100U_25V_M

12

PC943

PC942

470P_0402_50V7K

560P_0402_50V7K

CPU_B+

12

PC939

10U_0805_25V6K

0.22UH +-20% PCMB104T-R22MS 35A

12

PR943

4.7_1206_5%

SNUB_CPU3

12

PC940

680P_0603_50V7K

12

PC938

12

PC988

560P_0402_50V7K

1

2

PL904

PC988

PC945

560P_0402_50V7K

470P_0402_50V7K

4

3

V3N_CPU

PC944

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/12/14 2012/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU_CORE2

Size Document Number Rev

C

Date: Sheet

Friday, April 19, 2013

LA-9641P

1

57Friday, April 19, 2013

57

of

61

1.0

5

4

3

2

1

+

PC957

2

1

PC958

2

1

PC959

2

2X330u/9m(37W) 34 X 22u/0805

1

12

+

PC960

330U_D2_2.5V_Y

2

@PC961

@

12

PC961

22U_0805_6.3V6M

12

PC962

22U_0805_6.3V6M

@PC966

@

@PC963

@

1

PC966

PC969

PC963

2

22U_0805_6.3V6M

@PC964

@

12

PC964

22U_0805_6.3V6M

12

PC965

22U_0805_6.3V6M

PC969

2

22U_0805_6.3V6M

PC967

22U_0805_6.3V6M

PC968

22U_0805_6.3V6M

2

22U_0805_6.3V6M

12

PC970

22U_0805_6.3V6M

12

PC971

22U_0805_6.3V6M

@PC975

@

1

12

PC975

PC972

2

22U_0805_6.3V6M

12

PC973

PC976

22U_0805_6.3V6M

12

PC974

PC977

22U_0805_6.3V6M

@PC980

@

12

PC982

PC980

PC978

22U_0805_6.3V6M

@PC983

12

PC979

22U_0805_6.3V6M

@

12

PC981

PC983

PC984

22U_0805_6.3V6M

+CPU_CORE

+CPU_CO RE

D D

12

PC946

22U_0805_6.3V6M

C C

12

PC947

22U_0805_6.3V6M

3 X 330u/9m(47W)

X 22u/0805

34

1

@

+

PC951

2

@PC952

@

1

PC952

PC949

2

22U_0805_6.3V6M

1

PC953

PC950

2

22U_0805_6.3V6M

1

+

PC954

330U_D2_2.5V_Y

2

1

PC955

2

22U_0805_6.3V6M

1

PC956

2

22U_0805_6.3V6M

B B

A A

Security Class ification

2012/04/03

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/03

3

Compal Secret Data

Deciphered Date

2014/12/31

2

Compal Electronics, Inc.

Title

PROCESSOR DECOUPLING

Size Do cument Number Rev

LA-9641P

Date: Sheet o f

Friday, April 19, 2013

Date: Sheet o f

Friday, April 19, 2013

Date: Sheet o f

Friday, April 19, 2013

58

1

61

1.0

5

4

3

2

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

1

D D

2

3

4

5

6

7

C C

8

9

10

11

12

13

Adapter ID selection circuit

Delete reserve circuit B+ to VSB 49 Delete PR217,PR218,PR219,PC204,PQ203,PR223,PR224,PC205,PQ204,PC206

Pop Snubber by EMI request 50 PR323,PC320

To reduce Ripple 51 PC411,PC426 and change PL404 to 3.3uH

Reserve enable signal by HW request 51 Add PR410,PC432

Add boost resistor by EMI request 51 Add PR421,PR422

Reserve feedback signal for IC application 51 Add PR413,PC419

Delete reserve circuit

To reduce Ripple 54 Change PL601and PL701 to 3.3uH

Reserve enable signal by HW request Add PR70254

Pop Snubber by EMI request PR826,PC811,PR855,PC86555

Add input MLCC by EMI request 57 Add PC943,PC944,PC945,PC988

4849Add PR103,PR110,PR111,PQ102,PC108,PC109

Add PR227,PR230,PR229,PR232,PR225,PQ206,PQ208,PQ207

53To reduce Ripple Change PL601and PL605 to 1.5uH

Delete PC623,PU602,PC624,PR619,PR620,PR622,PC614,PR627,PL602,PR613,

53

PC612,PC615,PC616

2012.11.28

DVT

B B

14

Reserve battery detective circuit

4950Add PR2003,PR217,PC209,PR212,PC210,PD203,PR208,PQ209,PC211,PU202,PC212,PC213

2013.03.03 PVT

Add PQ314,PR311(Pop)

15

16

17 Reserve 1.5VSP Power Good by HW request 53 Add PR602

Reserve capacitor by EMI request 50 Add PC318,PC319

Reduce Component 51 Delete PD401

2013.03.03 PVT

Reserve bridge resistor by EMI request18 55 Add PR948,PC989

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2009/01/06 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

LA-9641P

Friday, April 19, 2013

59Friday, April 19, 2013

59

1

1.0

61

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 2 for HW

Reason for change PG# Modify List Date PhaseItem

USE singal 8M ROM for BIOS

1

D D

POWER NEW AC Connector

2

Change U8 to SA000039A30 8MB ROM Del U7,R239,R234,R235,R233,R236

U31.21--> ADP_65 U31.68 change from EC_WL_OFF# to ADP_90 U31.85 change from EC_TS_ON#to ADP_135 U31.66 change from BRDID_1 to ADP_ID

12/25

DVT

Change XDP pull down Resistor to R pack

3

Update Lenovo BGA footprint U

4

Move 15" ODD CAP to Small Board ChangeC605 to R401/ChangeC606 to R402/

5

WLAN Control change to PCH

6

POP TL_ENVDD PULL DOWN PO

7

8

Change HDMI LV from 10P8R to 8R4R X2

C C

Update EC GPIO

9

Del R18,R21,R23 / Add RP19

V

1,U4,UV5,UV6,UV7,UV8,UV9,UV10,UV11,UV12

ChangeC618 to R403/ChangeC617 to R404

PCH_GPIO55--> PCH_WL_OFF# PCH_GPIO22-->PCH_BT_ON# PCH_GPIO34-->INTEL_BT_OFF#

P R408

Del RP19 ADD RP5, RP6

NOVO# change form pin 26 to 34 EC_FAN_PWM change form pin 34 to 26 ENBKL change form pin 73 to 76

12/25

DVT

DVT12/25

IMVP_IMON change form pin 76 to 73 DGPU_PWR_EN change form pin 107 to 123

10

11

12

13

B B

14

VGA sequence +1.5VGS : RV41 --> 240K / CV53 --> 0.1U

EC Board ID Change R695 to 15K

Change ODD connector symbol

Update Crystal cap Value by vendor suggestion

JODD1->ALLTO_C18518-11305-L_13P-T

C111/ C112 --> 15p CV36/CV37-->8.2p

Reserve for EMI ADD R411,R412,C411,C412

DVT12/25

15

16

17

18

Change PCIE port and clock connection by SW request

Reserve R301 DVT12/25

Change EC_RST# power rail to +3V_EC

Change EC_SMB_CK1 & EC_SMB_DA1 power rail to +3V_EC

LAN-->Port 3 / WLAN--> Port2

Reserve +3VLP power rail to EC

Using power rail which the same with EC.

12/25

DVT12/25

DVT

19

20

A A

21

22

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2009/01/06 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (HW)

VIWGQ/GS

1

60 61Friday, April 19, 2 013

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 2 of 2 for HW

Reason for change PG# Modify List Date PhaseItem

Add resistor to switch audio power from +3VS

1

to +3VLP and +3VALW.

D D

Reconnect HDD +3VS power rail. Add R-short R552.

2

Modify LED current limiting resistor value.

3

Add parallel resistor to separate BIOS and EC. A

4

Add a Capacitor to connect CHASSIS_GND and GND by EMI request.

5

6

7

8

C C

9

10

Add RA1,RA2

Modify : R623,R765,R303

d

d RP2

Add CL64

02/18

PVT

02/18 PVT

PVT02/18

11

12

13

B B

14

15

16

17

18

19

20

A A

21

22

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2009/01/06 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (HW)

VIWGQ/GS

1

61 61Friday, April 19, 2 013

1.0

Compal LA-9641P, G410, G510 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual