Compal LA-9611P VIUS1, ThinkPad S431 Schematic

1
2
3
4
5
ŽŵƉĂůŽŶĨŝĚĞŶƚŝĂů
DŽĚĞůEĂŵĞs/h^ϭ
A A
&ŝůĞEĂŵĞ>ͲϵϲϭϭW KDWE
B B
ŽŵƉĂůŽŶĨŝĚĞŶƚŝĂů
D^ĐŚĞŵĂƚŝĐƐŽĐƵŵĞŶƚ
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C C
D D
ϮϬϭϮͲϬϮͲϭϴ
ZsϬϰ
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Cover Sheet
Cover Sheet
Cover Sheet
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
153Tuesday, February 26, 2013
153Tuesday, February 26, 2013
153Tuesday, February 26, 2013
0.4
0.4
0.4
A
B
C
D
E
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DŽĚĞůEĂŵĞs/h^ϭ
1 1
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WĂŐĞϮϮΕϮϵ
ĞWŽŶŶĞĐƚŽƌ
2 2
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;ŽĐŬŝŶŐͿ
;^ƵďŽĂƌĚͿ
,D/ŽŶŶĞĐƚŽƌ
ŝƐƉůĂLJWŽƌƚ
ĂƌĚZĞĂĚĞƌ
Realtek RTS5229
>E
Realtek RTL8111F
Z:ϰϱKEE
3 3
WĂŐĞϯϬ
WĂŐĞϯϭ
WĂŐĞϯϯ
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WĂŐĞϯϯ
W/Ͳyϴ DĞŵŽƌLJƵƐ
ĞW
FDI x8 (UMA)
100MHz
2.7GT/s
,D/
W
W/Ͳ
^W/
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'
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ENE KBC9012
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WĂŐĞϱΕϭϭ
DMI x4
100MHz 5GB/s
WĂŐĞϭϯΕϮϭ
dWD
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ƵĚŝŽŽĚĞĐ
Realtek ALC3202
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h^WKZdϯϬ
h^WKZdϯϬ
dŽƵĐŚWĂŶĞů
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W/džƉƌĞƐƐDŝŶŝĐĂƌĚ
WLAN / WiMAX / BT
4 4
ZZZ
ZZZ
LA-9611P
DA_PCB
DA_PCB
DA8000X7000
DA8000X7000
UCPU1
UCPU1
CPU2@
CPU2@
i5-3337U
i5-3337U
SA00006CU20
SA00006CU20
A
UCPU1
UCPU1
CPU3@
CPU3@
i3-3227U
i3-3227U
SA00006ED20
SA00006ED20
WĂŐĞϯϱ
UCPU1
UCPU1
CPU4@
CPU4@
i5-3437U
i5-3437U
SA00006D940
SA00006D940
W/Ͳ;t>EͿ
h^;dͿ
UCPU1
UCPU1
CPU5@
CPU5@
i7-3537U
i7-3537U
SA00006D840
SA00006D840
UCPU1
UCPU1
CPU6@
CPU6@
Ivy Bridgei7-3537U
Ivy Bridgei7-3537U
SA00006DB30
SA00006DB30
B
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dƌĂĐŬWŽŝŶƚ
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WĂŐĞϯϲ
WĂŐĞϯϲ
'Ͳ^ĞŶƐŽƌ
dŚĞƌŵĂů^ĞŶƐŽƌ
Fintek F75303M CPU & RAM
&ŝŶŐĞƌWƌŝŶƚĞƌ
UPEK TCS5DH6C0
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Nuvuton NCT7718 Panel
;^ƵďŽĂƌĚͿ
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
;^ƵďŽĂƌĚͿ
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
E
0.4
0.4
253Tuesday, February 26, 2013
253Tuesday, February 26, 2013
253Tuesday, February 26, 2013
0.4
1
2
3
4
5
Voltage Rails
SIGNAL
STATE
+5VS
power plane
A A
State
S0
S3
S5 S4/AC
S5 S4/ Battery only
B B
S5 S4/AC & Battery don't exist
+5VALW
+B
O
O
O
X
X
+1.5V
+3VALW
O
O
O
O
XX
X
X
XX X
EC SM Bus1 address
Device
Smart Battery
Address Address
0001 011X b
+3VS
+1.5VS
+VCCP
+CPU_CORE
+VGA_CORE
+VCC_GFXCORE_AXG
+1.8VS
+0.75VS
+1.05VS
OO
X
M3 Supported
M3 Supported
M3 Supported
X
EC SM Bus2 address
Device
Thermal Sensor Fintek F75303M
+3VM
+1.05VM
(SBA Only)
O
O
O
1001_101xb
Full ON
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID
0 1 2 3 4 5 6 7
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON ON ON
ON
OFF
OFF
OFF
OFF
OFFLOW LOW LOW LOW
HIGH HIGH HIGH HIGH
LOW LOW
HIGH
LOWLOWLOW
HIGH
HIGH
USB Port TableBOARD ID Table
PCB Revision
0.1
0.2
0.3
EHCI1
USB3.0
EHCI2
USB 2.0 Port
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
10 11 12 13
0
USB 3.0 Port (I/O Board)
1
USB 3.0 Port (MB)
2
USB 3.0 Port (Docking)
3
Camera
4 5 6 7 8
Touch Panel
9
(Test point) Mini Card (WLAN/BT) FPR
OFF
OFF
OFF
3 External USB Port
BOM Structure Table
BTO Item BOM Structure Connector CONN@ Unpop
Intel UMA
TPM TPM@ AOAC AOAC@
@ DIS@AMD UMA@ X76@VRAM Option
PCH SM Bus address
Device Address
DDR DIMM0
DDR DIMM2
C C
1001 000Xb
1001 010Xb
60%86&RQWURO7DEOH
7KHUPDO
;
;
9
96
;
:/$1 ::$1
;
;;
9
96
;
6HQVRU
;
;
;
;;
9
96
2
3&+
;
9
96
;
;
;;;
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Notes List
Notes List
Notes List
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
353Tuesday, February 26, 2013
353Tuesday, February 26, 2013
353Tuesday, February 26, 2013
0.4
0.4
0.4
6285&(
60%B(&B&. 60%B(&B'$ 60%B(&B&. 60%B(&B'$ 60%&/. 60%'$7$ 60/&/. 60/'$7$ 60/&/. 60/'$7$
D D
.%
9$/:
.%
9$/:
3&+
9$/:
3&+
9$/:
3&+
9$/:
9*$ %$77 .( 62',00
;9
;
;
;
9
96
1
9$/:
;
;
;
;
;
;
9
96
1
2
S5G3
3
4
5
S0
RTC
MB Bottom view
RTCRST
EC_111 pin
EC_ON
FD2
FD1
A A
FD1
@
@
1
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FD2
@
@
1
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FD3
FD3
@
@
1
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FD4
FD4
@
@
1
FIDUCIAL_C40M80
FIDUCIAL_C40M80
MAINPWON
+5VALW
+3VALW/VCCDSW
ON/OFF#
EC_RSMRST#
PBTN_OUT#
SLP_S5#
SLP_S4#
SYSON
SYSON
M_PWR_ON
PCH_APWROK
B B
SLP_S3#
SUSP#
+1.5V_CPU_VDDQ
+1.8VS
PCH
+5VS
+3VS
GPU
+1.5VS
+0.75VS
+V1.05VS(VCCP)
+VCCSA
RAM
C C
CPU
SA_PGOOD
VR_ON
99ms
PCH_POK
PCH_CLKOUT
DRAMPWROK
H_CPUPWRGD
CPU_VID
CPU_CORE
VGATE
SYS_PWROK
BUF_PLT_RST#
H1
H1
H_4P2
H_4P2
D D
@
@
1
H_4P2
H_4P2
H4
H4
H2
H2
@
@
1
H_4P2
H_4P2
H3
H3
H5
H5
H_4P2
H_4P2
H_2P7
H_2P7
@
@
@
@
@
1
@
1
1
H_2P3
H_2P3
H7
H7
H6
H6
H_3P3
H_3P3
@
@
@
@
1
1
H_2P3
H_2P3
H9
H9
H8
H8
@
@
1
H_4P0
H_4P0
H10
H10
H_4P0
H_4P0
@
@
@
@
1
1
JLB1
JLB1
SHAPE354X512
SHAPE354X512
@
@
1
SPI
DMI
ME and BIOS activity will continue
Tralning
H_4P0
H_4P0
H13
H13
H12
H12
H_4P0
H_4P0
@
@
@
@
1
1
H_4P0
H_4P0
H15
H15
H14
H14
@
@
1
H_4P0
H_4P0
H16
H16
H_4P0
H_4P0
@
@
@
@
1
1
1
H_4P2
H_4P2
H21
H21
H22
H_2P3
H_2P3
H22
H_2P5
H_2P5
@
@
@
@
1
1
H18
H18
@
@
1
H_2P3
H_2P3
H24
H24
H23
H23
H_2P2X1P8N
H_2P2X1P8N
@
@
@
@
1
1
2
JLB2
JLB2
CLIP_3X15
CLIP_3X15
1
Security Classification
Security Classification
@
@
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Screw Hole
Screw Hole
Screw Hole
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
453Tuesday, February 26, 2013
453Tuesday, February 26, 2013
453Tuesday, February 26, 2013
0.4
0.4
0.4
1
A A
DMI_CRX_PTX_N0[15] DMI_CRX_PTX_N1[15] DMI_CRX_PTX_N2[15] DMI_CRX_PTX_N3[15]
DMI_CRX_PTX_P0[15] DMI_CRX_PTX_P1[15] DMI_CRX_PTX_P2[15] DMI_CRX_PTX_P3[15]
DMI_CTX_PRX_N0[15] DMI_CTX_PRX_N1[15] DMI_CTX_PRX_N2[15] DMI_CTX_PRX_N3[15]
DMI_CTX_PRX_P0[15] DMI_CTX_PRX_P1[15] DMI_CTX_PRX_P2[15] DMI_CTX_PRX_P3[15]
FDI_CTX_PRX_N0[15] FDI_CTX_PRX_N1[15] FDI_CTX_PRX_N2[15]
B B
C C
FDI_CTX_PRX_N3[15] FDI_CTX_PRX_N4[15] FDI_CTX_PRX_N5[15] FDI_CTX_PRX_N6[15] FDI_CTX_PRX_N7[15]
FDI_CTX_PRX_P0[15] FDI_CTX_PRX_P1[15] FDI_CTX_PRX_P2[15] FDI_CTX_PRX_P3[15] FDI_CTX_PRX_P4[15] FDI_CTX_PRX_P5[15] FDI_CTX_PRX_P6[15] FDI_CTX_PRX_P7[15]
FDI_FSYNC0[15] FDI_FSYNC1[15]
FDI_INT[15]
FDI_LSYNC0[15] FDI_LSYNC1[15]
CPU_eDPC_AUXN[30]
CPU_eDPC_AUXP[30]
eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms
2
UCPU1A
UCPU1A
M2
DMI_RX#[0]
P6
DMI_RX#[1]
P1
DMI_RX#[2]
P10
DMI_RX#[3]
N3
DMI_RX[0]
P7
DMI_RX[1]
P3
DMI_RX[2]
P11
DMI_RX[3]
K1
DMI_TX#[0]
M8
DMI_TX#[1]
N4
DMI_TX#[2]
R2
DMI_TX#[3]
K3
DMI_TX[0]
M7
DMI_TX[1]
P4
DMI_TX[2]
T3
DMI_TX[3]
U7
FDI0_TX#[0]
W11
FDI0_TX#[1]
W1
FDI0_TX#[2]
AA6
FDI0_TX#[3]
W6
FDI1_TX#[0]
V4
FDI1_TX#[1]
Y2
FDI1_TX#[2]
AC9
FDI1_TX#[3]
U6
FDI0_TX[0]
W10
FDI0_TX[1]
W3
FDI0_TX[2]
AA7
FDI0_TX[3]
W7
FDI1_TX[0]
T4
FDI1_TX[1]
AA3
FDI1_TX[2]
AC8
FDI1_TX[3]
AA11
FDI0_FSYNC
AC12
FDI1_FSYNC
U11
FDI_INT
AA10
FDI0_LSYNC
AG8
+1.05VS
1 2
24.9_0402_1%
24.9_0402_1%
EDP_COMP
R2
CPU_eDP_HPD#[30]
CPU_eDPC_N0[30] CPU_eDPC_N1[30]
CPU_eDPC_P0[30] CPU_eDPC_P1[30]
R2
FDI1_LSYNC
AF3
eDP_COMP IO
AD2
eDP_ICOMPO
AG11
eDP_HPD#
AG4
eDP_AUX#
AF4
eDP_AUX
AC3
eDP_TX#[0]
AC4
eDP_TX#[1]
AE11
eDP_TX#[2]
AE7
eDP_TX#[3]
AC1
eDP_TX[ 0]
AA4
eDP_TX[ 1]
AE10
eDP_TX[ 2]
AE6
eDP_TX[ 3]
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023 CPU1@
CPU1@
DMI Intel(R) FDI
DMI Intel(R) FDI
eDP
eDP
3
G3 G1 G4
H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7
K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6
G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4
F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4
PEG_COMP
PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P7
PCIE_CTX_GRX_C_N0 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_P0 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P7
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]
PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]
PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]
PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
1 2
R1 24.9_0402_1%R1 24.9_0402_1%
C1 0.1U_0402_10V7KDIS@C1 0.1U_0402_10V7KDIS@ C2 0.1U_0402_10V7KDIS@C2 0.1U_0402_10V7KDIS@ C3 0.1U_0402_10V7KDIS@C3 0.1U_0402_10V7KDIS@ C4 0.1U_0402_10V7KDIS@C4 0.1U_0402_10V7KDIS@ C5 0.1U_0402_10V7KDIS@C5 0.1U_0402_10V7KDIS@ C6 0.1U_0402_10V7KDIS@C6 0.1U_0402_10V7KDIS@ C7 0.1U_0402_10V7KDIS@C7 0.1U_0402_10V7KDIS@ C8 0.1U_0402_10V7KDIS@C8 0.1U_0402_10V7KDIS@
C10 0.1U_0402_10V7KDIS@C10 0.1U_0402_10V7KDIS@ C11 0.1U_0402_10V7KDIS@C11 0.1U_0402_10V7KDIS@ C13 0.1U_0402_10V7KDIS@C13 0.1U_0402_10V7KDIS@ C12 0.1U_0402_10V7KDIS@C12 0.1U_0402_10V7KDIS@ C15 0.1U_0402_10V7KDIS@C15 0.1U_0402_10V7KDIS@ C14 0.1U_0402_10V7KDIS@C14 0.1U_0402_10V7KDIS@ C16 0.1U_0402_10V7KDIS@C16 0.1U_0402_10V7KDIS@ C17 0.1U_0402_10V7KDIS@C17 0.1U_0402_10V7KDIS@
ŚĞĐŬ'WhW/ͲĞh^ƐƉĞĞĚ 'ĞŶϮсϬϭƵ& 'ĞŶϯсϬϮϮƵ&
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
+1.05VS
PCIE_CRX_GTX_N[0..7] [23]
PCIE_CRX_GTX_P[0..7] [23]
4
PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P7
5
PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1: Normal Operation; Lane # definition matches socket pin map definition
*
0:Lane Reversed
PCIE_CTX_GRX_N[0..7] [23]
PCIE_CTX_GRX_P[0..7] [23]
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
553Tuesday, February 26, 2013
553Tuesday, February 26, 2013
553Tuesday, February 26, 2013
0.4
0.4
0.4
1
A A
H_SNB_IVB#[18]
+1.05VS
WƌŽĐĞƐƐŽƌWƵůůƵƉƐ
H_PROCHOT#[38]
B B
12
H_CPUPWRGD[18]
R5
R5 62_0402_5%
62_0402_5%
H_PECI[18,38]
H_THRMTRIP#[18]
H_PM_SYNC[15]
1
C33
C33 220P_0402_50V7K
220P_0402_50V7K
2
@
@
ESD Request
2
1 2
R8 10K_0402_5%@R8 10K_0402_5%@
1 2
R12 56_0402_5%R12 56_0402_5%
1 2
C2215 100P_0402_50V8J
C2215 100P_0402_50V8J
@
@
ESD Request
1 2
R25 130_0402_5%R25 130_0402_5%
3
UCPU1B
UCPU1B
MISC THERMAL PWR MANAGEMENT
F49
PROC_SELECT#
C57
PROC_DETECT#
1
H_CATERR#
T1
TPC12T1TPC12
H_PROCHOT#_R
PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF
BUF_CPU_RST#
C49
CATERR#
A48
PECI
C45
PROCHOT#
D45
THERMTRIP#
C48
PM_SYNC
B46
UNCOREPWRGOOD
BE45
SM_DRAMPWROK
D44
RESET#
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023 CPU1@
CPU1@
MISC THERMAL PWR MANAGEMENT
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
BCLK
BCLK#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
PRDY# PREQ#
TRST#
DBR#
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
J3
CLK_CPU_DMI_R
H2
CLK_CPU_DMI#_R
AG3
CLK_CPU_DP_R
AG1
CLK_CPU_DP#_R
AT30
BF44
SM_RCOMP0
BE43
SM_RCOMP1
BG43
SM_RCOMP2
N53
XDP_PRDY#
N55
XDP_PREQ#
L56
XDP_TCK
TCK
L55
XDP_TMS
TMS
J58
XDP_TRST#
M60
XDP_TDI
TDI
L59
XDP_TDO
TDO
K58
XDP_DBRESET#
G58 E55 E59 G55 G59 H60 J59 J61
4
1 2
R4 0_0402_5%@R4 0_0402_5%@
1 2
R7 0_0402_5%@R7 0_0402_5%@
1 2
R20 0_0402_5%@R20 0_0402_5%@
1 2
R23 0_0402_5%@R23 0_0402_5%@
1 2
R13 140_0402_1%R13 140_0402_1%
1 2
R14 25.5_.402_1%R14 25.5_.402_1%
1 2
R15 200_0402_1%R15 200_0402_1%
ZϯŽŵƉĞŶƐĂƚŝŽŶ^ŝŐŶĂůƐ
WhWĨŽƌ:d'ƐŝŐŶĂůƐ
1 2
R21 51_0402_5%@R21 51_0402_5%@
1 2
R17 51_0402_5%@R17 51_0402_5%@
1 2
R22 51_0402_5%@R22 51_0402_5%@
1 2
R18 51_0402_5%@R18 51_0402_5%@
1 2
R19 51_0402_5%@R19 51_0402_5%@
1
T4
TPC12T4TPC12
CLK_CPU_DMI [14] CLK_CPU_DMI# [14]
CLK_CPU_DP [14] CLK_CPU_DP# [14]
H_DRAMRST# [7]
+1.05VS
5
C C
R35
@R35
@
10K_0402_5%
10K_0402_5%
PM_DRAM_PWRGD[15]
PM_DRAM_PWRGD PM_SYS_PWRGD_BUF
D D
R214 0_0402_5%@R214 0_0402_5%@
1
1 2
1 2
5
1
P
B
2
A
G
3
1
C34
@C34
@
0.1U_0402_10V6K
0.1U_0402_10V6K
2
U1
@U1
@
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
4
O
SUSP[39]
+1.5V_CPU_VDDQ+3VALW+3VS
12
R33
R33 200_0402_5%
200_0402_5%
PM_SYS_PWRGD_BUF
12
R37
R37 39_0402_5%
39_0402_5% @
@
13
D
D
Q1
Q1
2
2N7002K_SOT23-3
2N7002K_SOT23-3 @
@
G
G
S
S
2
Buffered reset to CPU
PCH_PLTRST#[17]
+3VS +1.05VS
1
C35
C35
0.1U_0402_10V6K
0.1U_0402_10V6K
2
5
1
P
NC
4
BUFO_CPU_RST# BUF_CPU_RST#
Y
2
A
G
U2
U2 SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
12
R34
R34 75_0402_5%
75_0402_5%
R36
R36
43_0402_1%
43_0402_1%
1 2
12
R38
R38 0_0402_5%
0_0402_5% @
@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
653Tuesday, February 26, 2013
653Tuesday, February 26, 2013
653Tuesday, February 26, 2013
0.4
0.4
0.4
1
DDR_A_D[0..63][12]
A A
B B
DDR_A_BS0[12] DDR_A_BS1[12] DDR_A_BS2[12]
C C
DDR_A_CAS#[12] DDR_A_RAS#[12] DDR_A_WE#[12]
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
AP11
AJ10
AR11
AT13 AU13
BA13 BB11
AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43
AW48
BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56
BD37 BF36 BA28
BE39 BD39 AT41
2
UCPU1C
UCPU1C
AG6
SA_DQ[0]
AJ6
SA_DQ[1] SA_DQ[2]
AL6
SA_DQ[3] SA_DQ[4]
AJ8
SA_DQ[5]
AL8
SA_DQ[6]
AL7
SA_DQ[7] SA_DQ[8]
AP6
SA_DQ[9]
AU6
SA_DQ[10]
AV9
SA_DQ[11]
AR6
SA_DQ[12]
AP8
SA_DQ[13] SA_DQ[14] SA_DQ[15]
BC7
SA_DQ[16]
BB7
SA_DQ[17] SA_DQ[18] SA_DQ[19]
BA7
SA_DQ[20]
BA9
SA_DQ[21]
BB9
SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
SA_BS[0] SA_BS[1] SA_BS[2]
SA_CAS# SA_RAS# SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CK[0] SA_CK#[0] SA_CKE[0]
SA_CK[1] SA_CK#[1] SA_CKE[1]
SA_CS#[0] SA_CS#[1]
SA_ODT[0] SA_ODT[1]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
AU36 AV36 AY26
AT40 AU40 BB26
BB40 BC41
AY40 BA41
AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55
AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54
BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
3
M_CLK_DDR0 [12] M_CLK_DDR#0 [12] DDR_CKE0_DIMMA [12]
M_CLK_DDR1 [12] M_CLK_DDR#1 [12] DDR_CKE1_DIMMA [12]
DDR_CS0_DIMMA# [12] DDR_CS1_DIMMA# [12]
M_ODT0 [12] M_ODT1 [12]
DDR_A_DQS#[0..7] [12]
DDR_A_DQS[0..7] [12]
DDR_A_MA[0..15] [12]
BD13
BF12
BD10 BD14 BE13
BF16 BE17 BE18 BE21 BE14 BG14 BG18
BF19 BD50
BF48 BD53
BF52 BD49 BE49 BD54 BE53
BF56 BE57 BC59 AY60 BE54 BG54 BA58
AW59 AW58
AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58
AL58 AG58 AG59 AM60
AL59
AF61 AH60
BG39 BD42
AT22
AV43
BF40 BD45
4
UCPU1D
UCPU1D
AL4
SB_DQ[0]
AL1
SB_DQ[1]
AN3
SB_DQ[2]
AR4
SB_DQ[3]
AK4
SB_DQ[4]
AK3
SB_DQ[5]
AN4
SB_DQ[6]
AR1
SB_DQ[7]
AU4
SB_DQ[8]
AT2
SB_DQ[9]
AV4
SB_DQ[10]
BA4
SB_DQ[11]
AU3
SB_DQ[12]
AR3
SB_DQ[13]
AY2
SB_DQ[14]
BA3
SB_DQ[15]
BE9
SB_DQ[16]
BD9
SB_DQ[17] SB_DQ[18] SB_DQ[19]
BF8
SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]
SB_BS[0] SB_BS[1] SB_BS[2]
SB_CAS# SB_RAS# SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CK[0] SB_CK#[0] SB_CKE[0]
SB_CK[1] SB_CK#[1] SB_CKE[1]
SB_CS#[0] SB_CS#[1]
SB_ODT[0] SB_ODT[1]
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
BA34 AY34 AR22
BA36 BB36 BF27
BE41 BE47
AT43 BG47
AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59
AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61
BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22
5
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023
CPU1@
CPU1@
+1.5V
1 2
R39 0_0402_5%@R39 0_0402_5%@
D
S
D
S
13
H_DRAMRST#[6]
D D
DRAMRST_CNTRL_PCH[10,14]
1
R42
R42
4.99K_0402_1%
4.99K_0402_1%
12
Q2
Q2
G
G
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
2
1
C36
C36
0.047U_0402_16V4Z
0.047U_0402_16V4Z
2
DDR3_DRAMRST#_R
DRAMRST_CNTRL
R40
R40
1K_0402_5%
1K_0402_5%
12
R41
R41
1K_0402_5%
1K_0402_5%
1 2
2
DDR3_DRAMRST# [12]
DRAMRST_CNTRL [10,14]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023
CPU1@
CPU1@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
753Tuesday, February 26, 2013
753Tuesday, February 26, 2013
753Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
CFG Straps for Processor
CFG2
12
R45
A A
R45 1K_0402_1%
1K_0402_1% @
@
UCPU1E
UCPU1E
XDP_CFG0
CFG2
CFG4 CFG5 CFG6 CFG7
TPC12T2TPC12
B50
CFG[0]
C51
CFG[1]
B54
CFG[2]
D53
CFG[3]
A51
CFG[4]
C53
CFG[5]
C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53
H43 K43
H45 K45
F48
1
H48 K48
BA19 AV19
AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26
BF23 BE24
P+
CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]
VCC_VAL_SENSE VSS_VAL_SENSE
VAXG_VAL_SENSE VSSAXG_VAL_SENSE
VCC_DIE_SENSE
RSVD6 RSVD7
RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023 CPU1@
CPU1@
RESERVED
RESERVED
DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58
1
T3T3
+VCC_GFXCORE_AXG +CPU_CORE
@
@
1 2
12
R48
R48
49.9_0402_1%
49.9_0402_1%
R179 100_0402_1%@R179 100_0402_1%@
1 2
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE
VCC_VAL_SENSE VSS_VAL_SENSE
VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE
T2
12
R46
R46
49.9_0402_1% @
49.9_0402_1% @
B B
R176 100_0402_1%@R176 100_0402_1%@
1 2
R47 49.9_0402_1%@R47 49.9_0402_1%@
1 2
R49 49.9_0402_1%@R49 49.9_0402_1%@
C C
BCLK_ITP
BCLK_ITP#
RSVD30 RSVD31 RSVD32 RSVD33
RSVD34 RSVD35 RSVD36 RSVD37 RSVD38
RSVD39 RSVD40
RSVD41 RSVD42 RSVD43 RSVD44
RSVD45
DC_TEST_A4 DC_TEST_C4 DC_TEST_D3
DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61
DC_TEST_BG4 DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1 DC_TEST_BD1
N59 N58
N42 L42 L45 L47
M13 M14 U14 W14 P13
AT49 K24
AH2 AG13 AM14 AM15
N50
A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1: Normal Operation; Lane # definition matches socket pin map definition
*
0:Lane Reversed
CFG4
12
R50
R50
1K_0402_1%
1K_0402_1%
Display Port Presence Strap
CFG4
1 : Disabled; No Physical Display Port attached to Embedded Display Port
0 : Enabled; An external Display Port device is connected to the Embedded Display Port
*
CFG5 CFG6
1K_0402_1%
1K_0402_1%
12
12
R51
R52
R51
@R52
@
1K_0402_1%
1K_0402_1%
PCIE Port Bifurcation Straps
CFG[6:5]
— 00 = 1 x8, 2 x4 PCI Express* — 01 = reserved — 10 = 2 x8 PCI Express*
*
— 11 = 1 x16 PCI Express*
CFG7
12
R53
@R53
@ 1K_0402_1%
1K_0402_1%
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7
de assertion
0: PEG Wait for BIOS for training
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
of
853Tuesday, February 26, 2013
853Tuesday, February 26, 2013
853Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
+CPU_CORE +1.05VS
A A
B B
C C
D D
͵͵ ȋȌ
UCPU1F
UCPU1F
A26
VCC[1]
A29
VCC[2]
A31
VCC[3]
A34
VCC[4]
A35
VCC[5]
A38
VCC[6]
A39
VCC[7]
A42
VCC[8]
C26
VCC[9]
C27
VCC[10]
C32
VCC[11]
C34
VCC[12]
C37
VCC[13]
C39
VCC[14]
C42
VCC[15]
D27
VCC[16]
D32
VCC[17]
D34
VCC[18]
D37
VCC[19]
D39
VCC[20]
D42
VCC[21]
E26
VCC[22]
E28
VCC[23]
E32
VCC[24]
E34
VCC[25]
E37
VCC[26]
E38
VCC[27]
F25
VCC[28]
F26
VCC[29]
F28
VCC[30]
F32
VCC[31]
F34
VCC[32]
F37
VCC[33]
F38
VCC[34]
F42
VCC[35]
G42
VCC[36]
H25
VCC[37]
H26
VCC[38]
H28
VCC[39]
H29
VCC[40]
H32
VCC[41]
H34
VCC[42]
H35
VCC[43]
H37
VCC[44]
H38
VCC[45]
H40
VCC[46]
J25
VCC[47]
J26
VCC[48]
J28
VCC[49]
J29
VCC[50]
J32
VCC[51]
J34
VCC[52]
J35
VCC[53]
J37
VCC[54]
J38
VCC[55]
J40
VCC[56]
J42
VCC[57]
K26
VCC[58]
K27
VCC[59]
K29
VCC[60]
K32
VCC[61]
K34
VCC[62]
K35
VCC[63]
K37
VCC[64]
K39
VCC[66]
K42
VCC[67]
L25
VCC[68]
L28
VCC[69]
L33
VCC[70]
L36
VCC[71]
L40
VCC[72]
N26
VCC[73]
N30
VCC[74]
N34
VCC[75]
N38
VCC[76]
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023
CPU1@
CPU1@
POWER
POWER
CORE SUPPLY
CORE SUPPLY
ͺǤͷ
AF46
VCCIO[1]
AG48
VCCIO[3]
AG50
VCCIO[4]
AG51
VCCIO[5]
AJ17
VCCIO[6]
AJ21
VCCIO[7]
AJ25
VCCIO[8]
AJ43
VCCIO[9]
AJ47
VCCIO[10]
AK50
VCCIO[11]
AK51
VCCIO[12]
AL14
VCCIO[13]
AL15
VCCIO[14]
AL16
VCCIO[15]
AL20
VCCIO[16]
AL22
VCCIO[17]
AL26
VCCIO[18]
AL45
VCCIO[19]
AL48
VCCIO[20]
AM16
VCCIO[21]
AM17
VCCIO[22]
AM21
VCCIO[23]
AM43
VCCIO[24]
AM47
VCCIO[25]
AN20
VCCIO[26]
AN42
VCCIO[27]
AN45
VCCIO[28]
AN48
VCCIO[29]
AA14
VCCIO[30]
AA15
VCCIO[31]
AB17
VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]
VCCIO50 VCCIO51
VCCIO_SEL
VCCPQE[1] VCCPQE[2]
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15
W16 W17
BC22
AM25 AN22
A44 B43 C44
F43 G43
AN16 AN17
H_VCCP_SEL
H_CPU_SVIDALRT#
VCCSENSE VSSSENSE
PEG IO AND DDR IO
PEG IO AND DDR IO
RAILS
RAILS
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID QUIET
SENSE LINES SVID QUIET
+1.05VS
Chief-River platforms VCCIO_SEL = pulled high
+1.05VS
12
C161
C161 1U_0402_6.3V6K
1U_0402_6.3V6K
1 2
R174 100_0402_1%@R174 100_0402_1%@
1 2
R64 10_0402_1%R64 10_0402_1%
VCCIO_SENSE VSSIO_SENSE
12
R63
R63
10_0402_1%
10_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.05VS
VCCIO_SENSE [46] VSSIO_SENSE [46]
+3VS
1 2
R78 10K_0402_5%R78 10K_0402_5%
12
1
C37
C37
R54
R54 130_0402_5%
130_0402_5%
2
1 2
R56 43_0402_1%R56 43_0402_1%
Trace Impedance = 27 ~ 33 ohm Trace Length Match < 25 mils
R55
R55
75_0402_5%
75_0402_5%
+1.05VS+1.05VS
12
+CPU_CORE
12
12
Place the PU resistors close to VR
1
C38
C38
0.1U_0402_10V6K
0.1U_0402_10V6K
2
VR_SVID_ALRT# [48] VR_SVID_CLK [48] VR_SVID_DAT [48]
Place the PU
R59
R59
resistors close to CPU
100_0402_1%
100_0402_1%
VCCSENSE [48] VSSSENSE [48]
R62
R62 100_0402_1%
100_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
LA-9611P
LA-9611P
LA-9611P
5
of
953Tuesday, February 26, 2013
953Tuesday, February 26, 2013
953Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
10U_0603_6.3V6M
10U_0603_6.3V6M
C42
10U_0603_6.3V6M
C42
10U_0603_6.3V6M
1
2
+1.5V_CPU_VDDQ
R68
R68
1K_0402_5%
1K_0402_5%
R72
R72
1K_0402_5%
1K_0402_5%
C43
10U_0603_6.3V6M
C43
10U_0603_6.3V6M
1
@
2
H_VCCSA_VID0 [45] H_VCCSA_VID1 [45]
Dϯ^ƵƉƉŽƌƚ
C44
12
12
1
2
10U_0603_6.3V6M@C44
10U_0603_6.3V6M
@
+1.5V_CPU_VDDQ
C45
10U_0603_6.3V6M@C45
10U_0603_6.3V6M
C46
1
2
330U_D2_2V_Y+C46
330U_D2_2V_Y
1
+
2
ΪͳǤͷ
+5VALW
1 2
SUSP#[25,38,39,44,46,47]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
R67 0_0402_5%@R67 0_0402_5%@
+V_DDR_REFA_R
C2327 1U_0402_6.3V6K
C2327 1U_0402_6.3V6K
R203
R203
15K_0402_5%
15K_0402_5%
12
R79
R79
1K_0402_1%
1K_0402_1%
@
@
+1.5V_CPU_VDDQ +1.5V
@
@
1 2
+1.5V
RUN_ON_CPU1.35VS3
1
C65
C65
0.047U_0402_16V4Z
0.047U_0402_16V4Z
2
1 2
Q3
Q3
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
D
S
D
S
13
G
G
2
DRAMRST_CNTRL
1 2
C47 0.1U_0402_10V6KC47 0.1U_0402_10V6K
1 2
C53 0.1U_0402_10V6KC53 0.1U_0402_10V6K
1 2
C54 0.1U_0402_10V6K@ C54 0.1U_0402_10V6K@
1 2
C55 0.1U_0402_10V6K@ C55 0.1U_0402_10V6K@
+1.5V
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
JP1
@JP1
@
PAD-OPEN 4x4m
PAD-OPEN 4x4m
U2409
U2409
6
CT
GND GND
4
VBIAS
2
VIN
VOUT
1
VIN
VOUT
3
ON
TPS22965DSGR_SON8_2X2~D
TPS22965DSGR_SON8_2X2~D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
+VREF_DQ_DIMMA
DRAMRST_CNTRL [14,7]
+1.5V_CPU_VDDQ
12
9 5
8
7
LA-9611P
LA-9611P
LA-9611P
5
+1.5V_CPU_VDDQ
10 53Tuesday, February 26, 2013
10 53Tuesday, February 26, 2013
10 53Tuesday, February 26, 2013
0.4
0.4
0.4
+V_SM_VREF should have 10 mil trace width
POWER
UCPU1G
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
UCPU1G
͵͵ ȋʹȌ
AA46
VAXG[1]
AB47
VAXG[2]
AB50
VAXG[3]
AB51
VAXG[4]
AB52
VAXG[5]
AB53
VAXG[6]
AB55
VAXG[7]
AB56
VAXG[8]
AB58
VAXG[9]
AB59
VAXG[10]
AC61
VAXG[11]
AD47
VAXG[12]
AD48
VAXG[13]
AD50
VAXG[14]
AD51
VAXG[15]
AD52
VAXG[16]
AD53
VAXG[17]
AD55
VAXG[18]
AD56
VAXG[19]
AD58
VAXG[20]
AD59
VAXG[21]
AE46
VAXG[22]
N45
VAXG[23]
P47
VAXG[24]
P48
VAXG[25]
P50
VAXG[26]
P51
VAXG[27]
P52
VAXG[28]
P53
VAXG[29]
P55
VAXG[30]
P56
VAXG[31]
P61
VAXG[32]
T48
VAXG[33]
T58
VAXG[34]
T59
VAXG[35]
T61
VAXG[36]
U46
VAXG[37]
V47
VAXG[38]
V48
VAXG[39]
V50
VAXG[40]
V51
VAXG[41]
V52
VAXG[42]
V53
VAXG[43]
V55
VAXG[44]
V56
VAXG[45]
V58
VAXG[46]
V59
VAXG[47]
W50
VAXG[48]
W51
VAXG[49]
W52
VAXG[50]
W53
VAXG[51]
W55
VAXG[52]
W56
VAXG[53]
W61
VAXG[54]
Y48
VAXG[55]
Y61
VAXG[56]
F45
VAXG_SENSE
G45
VSSAXG_SENSE
ͳǤʹ
BB3
VCCPLL[1]
BC1
VCCPLL[2]
BC4
VCCPLL[3]
͸
L17
VCCSA[1]
L21
VCCSA[2]
N16
VCCSA[3]
N20
VCCSA[4]
N22
VCCSA[5]
P17
VCCSA[6]
P20
VCCSA[7]
R16
VCCSA[8]
R18
VCCSA[9]
R21
VCCSA[10]
U15
VCCSA[11]
V16
VCCSA[12]
V17
VCCSA[13]
V18
VCCSA[14]
V21
VCCSA[15]
W20
VCCSA[16]
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023
CPU1@
CPU1@
+VCC_GFXCORE_AXG
A A
B B
+VCC_GFXCORE_AXG
R65
R65
10_0402_1%
10_0402_1%
VCC_AXG_SENSE[48] VSS_AXG_SENSE[48]
R66
R66
10_0402_1%
10_0402_1%
+1.8VS
C C
D D
Vaxg
Can connect to GND if mother board onlyɄɄɄɄ
supports externa l graphics and if GFX VR is not stuffed in a common mother board design,
VAXG can be left floating in a commonɄɄɄɄ
motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed
R76 0_0805_5%@R76 0_0805_5%@
+VCCSA
1
1 2
12
1 2
C48
C48
R73 100_0402_1%@R73 100_0402_1%@
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
1 2
C56
10U_0603_6.3V6M
C56
10U_0603_6.3V6M
1
2
C49
10U_0603_6.3V6M
C49
10U_0603_6.3V6M
1
2
+1.8VS_VCCPLL
C58
1U_0402_6.3V6K@C58
1U_0402_6.3V6K
C57
1U_0402_6.3V6K
C57
1U_0402_6.3V6K
C59
C59
1
1
1
2
C50
C50
1
2
+
+
@
@
2
2
@
C51
10U_0603_6.3V6M@C51
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C52
C52
1
1
+
+
@
@
@
2
2
POWER
VREF
VREF
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
GRAPHICS
GRAPHICS
SENSE
LINES
SENSE
LINES
1.8V RAIL
1.8V RAIL
SA RAIL
SA RAIL
VCCSA VID
VCCSA VID
2
SM_VREF
SA_DIMM_VREFDQ SB_DIMM_VREFDQ
VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]
VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]
VCCDQ[1] VCCDQ[2]
QUIET RAILS
QUIET RAILS
VDDQ_SENSE
VSS_SENSE_VDDQ
VCCSA_SENSE
SENSE LINES
SENSE LINES
VCCSA_VID[0] VCCSA_VID[1]
lines
lines
AY43
BE7 BG7
ͷ
AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33
AM28 AN26
BC43 BA43
U10
D48 D49
+V_SM_VREF_CNT
+V_DDR_REFA_R +V_DDR_REFB_R
C40
10U_0603_6.3V6M
C40
10U_0603_6.3V6M
C41
C41
1
2
+1.5V_CPU_VDDQ
12
C162
C162 1U_0402_6.3V6K
1U_0402_6.3V6K
1 2
R75 0_0402_5%@R75 0_0402_5%@
1
2
1
A13
AA13 AA50 AA51 AA52 AA53 AA55 AA56
AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46
AD17 AD20
AD61 AE13
AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58
AF59 AG10 AG14 AG18 AG47 AG52 AG61
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61 AM13 AM20 AM22 AM26 AM30 AM34
A17 A21 A25 A28 A33 A37 A40 A45 A49 A53
A9
AA1
AA8
AC6
AD4
AE8 AF1
AG7 AH4
AJ7 AK1
A A
B B
C C
UCPU1H
UCPU1H
VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]
2
VSS
VSS
VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]
VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]
AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13
3
UCPU1I
UCPU1I
BG17
VSS[181]
BG21
VSS[182]
BG24
VSS[183]
BG28
VSS[184]
BG37
VSS[185]
BG41
VSS[186]
BG45
VSS[187]
BG49
VSS[188]
BG53
VSS[189]
BG9
VSS[190]
C29
VSS[191]
C35
VSS[192]
C40
VSS[193]
D10
VSS[194]
D14
VSS[195]
D18
VSS[196]
D22
VSS[197]
D26
VSS[198]
D29
VSS[199]
D35
VSS[200]
D4
VSS[201]
D40
VSS[202]
D43
VSS[203]
D46 D50 D54 D58
D6 E25 E29
E3 E35 E40 F13 F15 F19 F29 F35 F40 F55
G51
G6
G61
H10 H14 H17 H21
H4 H53 H58
J1 J49 J55 K11 K21 K51
K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61
M11 M15
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023 CPU1@
CPU1@
VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249]
VSS
VSS
4
VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8
VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11
NCTF
NCTF
VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14
M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48
A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61
1 1 1
1 1
1
T101 PAD @T101 PAD @ T102 PAD @T102 PAD @ T103 PAD @T103 PAD @
T108 PAD @T108 PAD @ T109 PAD @T109 PAD @
T114 PAD @T114 PAD @
5
IVY-BRIDGE_BG A1023
IVY-BRIDGE_BG A1023
CPU1@
CPU1@
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
11 53Tuesday, February 26, 2013
11 53Tuesday, February 26, 2013
11 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
+1.5V
12
R2001
R2001
1K_0402_1%
1K_0402_1%
+VREF_DQ_DIMMA
A A
All VREF traces should have 10 mil trace width
B B
R2003
R2003 1K_0402_1%
1K_0402_1%
12
DDR_CKE0_DIMMA[7]
DDR_A_BS2[7]
M_CLK_DDR0[7] M_CLK_DDR#0[7]
DDR_A_BS0[7]
DDR_A_WE#[7] DDR_A_CAS#[7]
DDR_CS1_DIMMA#[7]
PN:SP07000LB00
C C
<Address: 00>
DIMM_A H:4.0mm
+3VS
+0.75VS +0.75VS
D D
1
@
C2001
1
2
C2021
@
2
+1.5V
JDIMM1
R2007
R2007 0_0402_5%
0_0402_5% @
@
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1 VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9 VSS925VSS10
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2 DQS247VSS17
49
VSS18
51
DQ18 DQ1953VSS19
55
VSS20
57
DQ24 DQ2559VSS21 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3 A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1 VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4406-0102
LCN_DAN06-K4406-0102 CONN@
CONN@
VSS3
DQS0
VSS6
VSS8 DQ12 DQ13
DQ14 DQ15
DQ20 DQ21
DQ22 DQ23
DQ28 DQ29
DQS3
DQ30 DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
VSS31
DQ38 DQ39
VSS33
DQ44
DQ45 VSS35 DQS#5
DQS5
VSS38
DQ46
DQ47 VSS40
DQ52
DQ53 VSS42
VSS43
DQ54
DQ55 VSS45
DQ60
DQ61 VSS47 DQS#7
DQS7
VSS50
DQ62
DQ63 VSS52
EVENT#
VTT2
DQ4 DQ5
DQ6 DQ7
DM1
DM2
A15 A14
CK1
BA1
S0#
NC2
DM4
DM6
SDA SCL
G2
2.2U_0603_6.3V6K@C2001
2.2U_0603_6.3V6K
C2002
C2002
C2046
0.1U_0402_10V6K@C2021
0.1U_0402_10V6K
1
@
2
2
+VREF_DQ_DIMMA
0.1U_0402_10V6K
0.1U_0402_10V6K DDR_A_D0 DDR_A_D1
1
2
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA9
DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1
M_CLK_DDR0 M_CLK_DDR#0
DDR_A_MA10 DDR_A_BS0
DDR_A_WE# DDR_A_CAS#
DDR_A_MA13 DDR_CS1_DIMMA#
DDR_A_D32 DDR_A_D36 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_D42 DDR_A_D46 DDR_A_D43
DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_D58 DDR_A_D59
0.1U_0402_10V6K@C2046
0.1U_0402_10V6K
C2022
2.2U_0603_6.3V6K@C2022
2.2U_0603_6.3V6K
R2006 0_0402_5%@R2006 0_0402_5%
12
1
2
12
1
@
2
@
3
+1.5V
2 4
DDR_A_D4
6
DDR_A_D5 8 10
DDR_A_DQS#0 12
DDR_A_DQS0 14 16
DDR_A_D6 18
DDR_A_D7 20 22
DDR_A_D12 24
DDR_A_D13 26 28 30
DDR3_DRAMRST# 32 34
DDR_A_D14 36
DDR_A_D15 38 40
DDR_A_D20 42
DDR_A_D21 44 46 48 50
DDR_A_D22 52
DDR_A_D23 54 56
DDR_A_D28 58
DDR_A_D29 60 62
DDR_A_DQS#3 64
DDR_A_DQS3 66 68
DDR_A_D30 70
DDR_A_D31 72
74
DDR_CKE1_DIMMA 76 78
DDR_A_MA15 80
DDR_A_MA14DDR_A_MA14 82 84
DDR_A_MA11DDR_A_MA12 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
+VREF_CA
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
A7
A6 A4
A2 A0
DDR3_DRAMRST# [ 7]
DDR_CKE1_DIMMA [7]
M_CLK_DDR1 [7] M_CLK_DDR#1 [7]
DDR_A_BS1 [7] DDR_A_RAS# [7]
DDR_CS0_DIMMA# [ 7] M_ODT0 [7]
M_ODT1 [7]
C2015
2.2U_0603_6.3V6K@C2015
2.2U_0603_6.3V6K
1
@
2
SMB_DATA_S3 [14,30,35,36] SMB_CLK_S3 [14,30,35,36]
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
C2016
C2016
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
+1.5V
12
12
Compal Secret Data
Compal Secret Data
Compal Secret Data
R2004
R2004 1K_0402_1%
1K_0402_1%
R2005
R2005 1K_0402_1%
1K_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
4
+1.5V
C2005
0.1U_0402_10V6K
C2005
0.1U_0402_10V6K
C2004
0.1U_0402_10V6K
C2004
0.1U_0402_10V6K
C2006
C2003
0.1U_0402_10V6K@C2003
0.1U_0402_10V6K
1
@
2
+1.5V
C2008
C2008
C2007
10U_0603_6.3V6M
C2007
10U_0603_6.3V6M
1
2
+0.75VS
C2017
1U_0402_6.3V6K
C2017
1U_0402_6.3V6K
1
2
4
C2006
1
1
2
1
2
C2018
C2018
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
C2009
10U_0603_6.3V6M@C2009
10U_0603_6.3V6M
C2010
1
1
@
@
2
2
@
C2019
1U_0402_6.3V6K@C2019
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DDRIII DIMMA
DDRIII DIMMA
DDRIII DIMMA
5
DDR_A_DQS#[0..7] [7]
DDR_A_DQS[0..7] [7]
DDR_A_D[0..63] [7]
DDR_A_MA[0..15] [7]
Layout Note: Place near
0.1U_0402_10V6K
0.1U_0402_10V6K
JDIMM1
C2011
10U_0603_6.3V6M
C2011
10U_0603_6.3V6M
10U_0603_6.3V6M@C2010
10U_0603_6.3V6M
C2012
C2012
1
1
2
2
@
Layout Note: Place near
C2020
1U_0402_6.3V6K@C2020
1U_0402_6.3V6K
JDIMM1.203,204
1
2
LA-9611P
LA-9611P
LA-9611P
5
C2013
10U_0603_6.3V6M@C2013
10U_0603_6.3V6M
C2014
330U_D2_2V_Y
C2014
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D2_2V_Y
1
1
+
+
@
2
@
@
2
0.4
0.4
12 53Tuesday, February 26, 2013
12 53Tuesday, February 26, 2013
12 53Tuesday, February 26, 2013
0.4
1
1
C64
C64 18P_0402_50V8J
18P_0402_50V8J
2
PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
HDA_SPKR
HDA_SDOUT
HDA_SYNC
1
C179
C179 1U_0402_6.3V6K
1U_0402_6.3V6K
2
+3VS
1 2
R202 10K_0402_5%R202 10K_0402_5%
12
CLRP1
CLRP1 SHORT PADS
SHORT PADS
1 2
R87 10M_0402_5%R87 10M_0402_5%
Y1
Y1
1 2
32.768KHZ_12.5PF_CM31532768DZFT
32.768KHZ_12.5PF_CM31532768DZFT
1
C63
C63 18P_0402_50V8J
18P_0402_50V8J
2
A A
+RTCVCC
1 2
R90 1M_0402_5%R90 1M_0402_5%
1 2
R91 330K_0402_5%R91 330K_0402_5%
INTVR MEN
H烉烉烉Integrated VRM enable
*
L烉烉烉Integrated VRM disable
(INTVRMEN should always be pull high.)
+3VS
1 2
R93 1K_0402_5%@R93 1K_0402_5%@
HIGH= Enable ( No Reboot ) LOW= Disable (Default)
*
B B
+3V_PCH
1 2
R95 1K_0402_5%@R95 1K_0402_5%@
HDA_SDO
ME debug mode,this signal has a weak i nternal PD Low = Disabled (Default)
*
High = Enabled [Flash Descriptor Security Overide]
+3V_PCH
1 2
R99 1K _0402_5%R99 1K_0402_5%
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when sampled high
*
1.8V when sampled low Needs to be pulled High for Huron River platfrom
C C
EMI
RP9
RP9
1 8
HDA_BITCLK_AUDIO[32] HDA_SYNC_AUDIO[32] HDA_RST_AUDIO#[32] HDA_SDOUT_AUDIO[32]
2 7 3 6 4 5
33_8P4R_5%
33_8P4R_5%
HDA_BIT_CLK HDA_SYNC_R HDA_RST# HDA_SDOUT
Prevent back drive issue.
+5VS
G
G
2
13
D
S
D
S
Q8
Q8
12
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
R303
R303 1M_0402_5%
1M_0402_5%
HDA_SYNC
R106
R106
1K_0402_5%
1K_0402_5%
1 2
W=20milsW=20mils
+RTCBATT+RTCVCC
WLBT_OFF_5#
2
PIN1
PIN2
CLRP1, JCMOS1, JME1 place near the door
C62
+RTCVCC
1 2
R88 20K_0402_5%R88 20K_0402_5%
1 2
R89 20K_0402_5%R89 20K_0402_5%
HDA_SPKR[32]
HDA_SDIN0[ 32]
ME_FLASH[38]
WLBT_OFF_5#[35]
+3V_PCH
C62
1U_0402_6.3V6K
1U_0402_6.3V6K
C66
C66
1U_0402_6.3V6K
1U_0402_6.3V6K
R94 0_0402_5%@R94 0_0402_5%@
R209 10K_0402_5%@R209 10K_0402_5%@
R96 51_0402_5%R96 51_0402_5%
RTC conn
1
12
@
2
1
12
@
2
HDA_SPKR
HDA_SDIN0
1 2
1 2
1 2
CMOS
JCMOS1
SHORT PADS@JCMOS1
SHORT PADS
ME
JME1
SHORT PADS@JME1
SHORT PADS
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDOUT
WLBT_OFF_5#
PCH_GPIO13
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
SPI_CLK_PCH_R
SPI_SB_CS0#
SPI_SI
SPI_SO_R
3
G22
G34
U2408A
U2408A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPI O13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
P-
P-
P-
P-
P-
P-
P-
P-
P+
P+
P-
P+
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
P+ P+
P+
ϴD^W/ZKD&KZϭϱDD ΘEŽŶͲƐŚĂƌĞZKD
4
C38
P+
FWH0 / LAD0
P+
FWH1 / LAD1
P+
FWH2 / LAD2
P+
FWH3 / LAD3
LPC
LPC
FWH4 / LFRA ME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
SATA1RXN SATA1RXP
SATA 6G
SATA 6G
SATA1TXN SATA1TXP
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
SATA3RXN SATA3RXP SATA3TXN SATA3TXP
SATA4RXN SATA4RXP SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
SPI_SB_CS0#
SPI_WP#
KE ϴD^ϬϬϬϬϰϲϰϬϬ^/&>ϲϰDEϮϱYϲϰͲϭϬϰ,/W^KWϴW
LPC_AD0
A38
LPC_AD1
B37
LPC_AD2
C37
LPC_AD3
D36
LPC_FRAME#
E36 K36
V5
SERIRQ
AM3
SATA_DTX_C_PRX_N0
AM1
SATA_DTX_C_PRX_P0
AP7
SATA_PTX_C_DRX_N0
AP5
SATA_PTX_C_DRX_P0
AM10
SATA_DTX_C_PRX_N1
AM8
SATA_DTX_C_PRX_P1
AP11
SATA_PTX_C_DRX_N1
AP10
SATA_PTX_C_DRX_P1
AD7 AD5 AH5 AH4
AB8 AB10 AF3 AF1
Y7 Y5 AD3 AD1
Y3 Y1 AB3 AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
1 2 3 4
SATA_COMP
SATA3_COMP
RBIAS_SATA3
PCH_SATALED#
PCH_GPIO21
PCH_GPIO19
U5 8M
U5
U5
CS#
VCC
DO
HOLD#
WP#
CLK
GND
DI
W25Q32BVSSIG_SO 8
W25Q32BVSSIG_SO 8
+3VS
C191 0.1U_0402_10V6KC191 0.1U_0402_10V6K
8 7
SPI_HOLD#SPI_SO_R
6
SPI_CLK_PCH_R
5
SPI_SI
1 2
LPC_AD0 [37,38] LPC_AD1 [37,38] LPC_AD2 [37,38] LPC_AD3 [37,38]
LPC_FRAME# [37,38]
SERIRQ [37,38]
SATA_DTX_C_PRX_N0 [34] SATA_DTX_C_PRX_P0 [34] SATA_PTX_C_DRX_N0 [34] SATA_PTX_C_DRX_P0 [34]
SATA_DTX_C_PRX_N1 [34] SATA_DTX_C_PRX_P1 [34] SATA_PTX_C_DRX_N1 [34] SATA_PTX_C_DRX_P1 [34]
GATEA20[18,38] CLK_BUF_PCIE_SATA#[14] CLK_BUF_PCIE_SATA[14]
+1.05VS_VCC_SATA
+1.05VS_SATA3
PCH_GPIO49[18]
PCH_GPIO22[18]
KB_RST#[18,38]
SERIRQ GATEA20 CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA
SATA_COMP
SATA3_COMP
RBIAS_SATA3
PCH_SATALED#
PCH_GPIO19
SPI_WP#
SPI_HOLD#
5
HDD
m-SATA
RP5
RP5
1 8 2 7 3 6 4 5
10K_8P4R_5%
10K_8P4R_5%
1 2
R97 37.4_0402_1%R97 37.4_0402_1%
1 2
R98 49.9_0402_1%R98 49.9_0402_1%
1 2
R100 750_0402_1%R100 750_0402_1%
RP3
RP3
1 8
PCH_GPIO21
PCH_GPIO49
2 7 3 6
PCH_GPIO22
4 5
KB_RST#
10K_8P4R_5%
10K_8P4R_5%
1 2
R101 10K_0402_5%R101 10K_0402_5%
1 2
R103 10K_0402_5%R103 10K_0402_5%
1 2
R334 3.3K_0402_5%R334 3.3K_0402_5%
1 2
R335 3.3K_0402_5%R335 3.3K_0402_5%
+3VS
+1.05VS
+3VS
+3VS
+3V_PCH +3V_PCH+3V_PCH
D D
12
R120 200_0402_5%
200_0402_5%
12
R123 100_0402_1%
100_0402_1%
12
@R120
@
@R123
@
R121 200_0402_5%
200_0402_5%
PCH_JTAG_TMSPCH_JTAG_TDO PCH_JTAG_TDI
12
R124 100_0402_1%
100_0402_1%
12
R122
@R122
@R121
@
@R124
@
1
200_0402_5%
200_0402_5%
12
R125 100_0402_1%
100_0402_1%
@
Security Classification
Security Classification
@R125
@
2
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
13 53Tuesday, February 26, 2013
13 53Tuesday, February 26, 2013
13 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
PCIE_PRX_DTX_N1[37]
18 27 36 45
18 27 36 45
LAN_CLKREQ# PCIE_WAKE# RI# EC_SMI#
PCH_GPIO45 PCH_GPIO56 PCH_GPIO44 PCH_GPIO72
PCIE_PRX_DTX_P1[37] PCIE_PTX_C_DRX_N1[37] PCIE_PTX_C_DRX_P1[37]
PCIE_PRX_DTX_N2[35] PCIE_PRX_DTX_P2[35] PCIE_PTX_C_DRX_N2[35] PCIE_PTX_C_DRX_P2[35]
PCIE_PRX_DTX_N4[33] PCIE_PRX_DTX_P4[33] PCIE_PTX_C_DRX_N4[33] PCIE_PTX_C_DRX_P4[33]
CLK_PCIE_CARD#[37] CLK_PCIE_CARD[37]
CARD_CLKREQ#[37]
CLK_PCIE_WLAN1#[35] CLK_PCIE_WLAN1[35]
WLAN_CLKREQ1#[35]
CLK_PCIE_LAN#[33] CLK_PCIE_LAN[33]
LAN_CLKREQ#[33]
WLAN_CLKREQ1#
PCH_GPIO20
CARD_CLKREQ#
PCH_GPIO26
PCH_GPIO46
PCIE_WAKE# [15,33] RI# [15] EC_SMI# [18,38]
PCH_GPIO72 [15]
Card Reader
A A
Wireless LAN
PCIE LAN
B B
Card Reader
Wireless LAN
PCIE LAN
+3VS
1 2
R170 10K_0402_5%R170 10K_0402_5%
1 2
R162 10K_0402_5%@R162 10K_0402_5%@
+3V_PCH
1 2
C C
D D
R177 10K_0402_5%R177 10K_0402_5%
1 2
R181 10K_0402_5%@R181 10K_0402_5%@
1 2
R184 10K_0402_5%@R184 10K_0402_5%@
RP7
RP7
10K_8P4R_5%
10K_8P4R_5%
RP6
@RP6
@
10K_8P4R_5%
10K_8P4R_5%
1 2
C86 0.1U_0402_10V6KC86 0.1U_0402_10V6K
1 2
C79 0.1U_0402_10V6KC79 0.1U_0402_10V6K
1 2
C82 0.1U_0402_10V6KC82 0.1U_0402_10V6K
1 2
C83 0.1U_0402_10V6KC83 0.1U_0402_10V6K
1 2
C80 0.1U_0402_10V6KC80 0.1U_0402_10V6K
1 2
C81 0.1U_0402_10V6KC81 0.1U_0402_10V6K
1 2
R147 0_0402_5%@R147 0_0402_5%@
1 2
R149 0_0402_5%@R149 0_0402_5%@
1 2
R141 0_0402_5%@R141 0_0402_5%@
1 2
R142 0_0402_5%@R142 0_0402_5%@
1 2
R145 0_0402_5%@R145 0_0402_5%@
1 2
R146 0_0402_5%@R146 0_0402_5%@
1
T227T227
1
T226T226
2
PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1
PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4
CLK_CARD# CLK_CARD
CARD_CLKREQ#
CLK_MINI1# CLK_MINI1
WLAN_CLKREQ1#
PCH_GPIO20
CLK_LAN# CLK_LAN
LAN_CLKREQ#
PCH_GPIO26
PCH_GPIO44
PCH_GPIO56
PCH_GPIO45
PCH_GPIO46
CLK_XDP_CLK# CLK_XDP_CLK
U2408B
U2408B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
P+
P+
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
P+/P-
P+/P-
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKOUT_DP_N CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N CLKIN_GND1_P
CLKIN_DOT_96N CLKIN_DOT_96P
CLKIN_SATA_N CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPB ACK
XTAL25_OUT
XCLK_RCOMP
P-
CLKOUTFLEX0 / GPIO64
P-
CLKOUTFLEX1 / GPIO65
P-
CLKOUTFLEX2 / GPIO66
P-
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
3
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
E12
PCH_GPIO11
H14
PCH_SMBCLK
C9
PCH_SMBDATA
A12
DRAMRST_CNTRL_PCH
C8
PCH_SML0CLK
G12
PCH_SML0DATA
C13
PCH_HOT#
E14
PCH_SML1CLK
M16
PCH_SML1DATA
M7
T11
P10
M10
PCH_GPIO47
AB37 AB38
AV22
CLK_CPU_DMI#
AU22
CLK_CPU_DMI
AM12
CLK_CPU_DP#
AM13
CLK_CPU_DP
BF18
CLK_BUF_CPU_DMI#
BE18
CLK_BUF_CPU_DMI
BJ30
CLKIN_DMI2#
BG30
CLKIN_DMI2
G24
CLK_BUF_DREF_96M#
E24
CLK_BUF_DREF_96M
AK7
CLK_BUF_PCIE_SATA#
AK5
CLK_BUF_PCIE_SATA
K45
CLK_BUF_ICH_14M
H45
CLK_PCI_LPBACK
V47
XTAL25_IN
V49
XTAL25_OUT
Y47
XCLK_RCOMP
K43
PCH_GPIO64
F47
PCH_GPIO65
H47
PCH_GPIO66
K49
PCH_GPIO67
DRAMRST_CNTRL_PCH [10,7]
1 2
R139 0_0402_5%@R139 0_0402_5%@
1 2
R144 0_0402_5%@R144 0_0402_5%@
1 2
R151 0_0402_5%@R151 0_0402_5%@
1 2
R148 10K_0402_5%R148 10K_0402_5%
1 2
R150 10K_0402_5%R150 10K_0402_5%
1 2
R152 10K_0402_5%R152 10K_0402_5%
1 2
R153 10K_0402_5%R153 10K_0402_5%
1 2
R154 10K_0402_5%R154 10K_0402_5%
1 2
R155 10K_0402_5%R155 10K_0402_5%
CLK_BUF_PCIE_SATA# [13] CLK_BUF_PCIE_SATA [13]
1 2
R158 10K_0402_5%R158 10K_0402_5%
1 2
R160 90.9_0402_1%R160 90.9_0402_1%
CLK_CPU_DP [6]
+1.05VS
+1.05VS_VCCDIFFCLKN
PCH_GPIO67 [18]
4
PCH_GPIO47 [ 18]
GPU_CLKREQA [24]
CLK_PCIE_VGA# [23] CLK_PCIE_VGA [23]
CLK_CPU_DMI# [6] CLK_CPU_DMI [6]
CLK_CPU_DP# [6]
CLK_PCI_LPBACK [17]
PCH_SMBCLK
PCH_SMBDATA
PCH_SML0CLK
PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
PCH_HOT#
PCH_GPIO11
DRAMRST_CNTRL_PCH
@
@
6 1
PCH_SMBDATA
Q9A 2N7002KDWH_SOT363-6
Q9A 2N7002KDWH_SOT363-6
PCH_SMBCLK
Q9B 2N7002KDWH_SOT363-6
Q9B 2N7002KDWH_SOT363-6
PCH_SMBCLK SMB_CLK_S3
PCH_SML1DATA
PCH_SML1CLK
PLT_RST#[17,23,33,35,37,38]
R163 0_0402_5%@R163 0_0402_5%@ R164 0_0402_5%@R164 0_0402_5%@
@
@
6 1
Q10A 2N7002KDWH_SOT363-6
Q10A 2N7002KDWH_SOT363-6
@
@
Q10B 2N7002KDWH_SOT363-6
Q10B 2N7002KDWH_SOT363-6
PCH_SML1CLK EC_SMB_CK2
XTAL25_IN
XTAL25_OUT
C87
C87 15P_0402_50V8J
15P_0402_50V8J
+3VS
12
R172
R172 10K_0402_5%
10K_0402_5% @
@
PLT_RST#
R128 2.2K_0402_5%@R128 2.2K_0402_5%@
R129 2.2K_0402_5%@R129 2.2K_0402_5%@
R130 2.2K_0402_5%R130 2.2K_0402_5%
R131 2.2K_0402_5%R131 2.2K_0402_5%
R126 2.2K_0402_5%@R126 2.2K_0402_5%@
R132 2.2K_0402_5%@R132 2.2K_0402_5%@
R133 10K_0402_5%R133 10K_0402_5%
R135 10K_0402_5%R135 10K_0402_5%
R127 1K_0402_5%R127 1K_0402_5%
+3VS
3 4
+3VS
R165 0_0402_5%@R165 0_0402_5%@ R166 0_0402_5%@R166 0_0402_5%@
R136 2.2K_0402_5%R136 2.2K_0402_5%
2
SMB_DATA_S3
R137 2.2K_0402_5%R137 2.2K_0402_5%
1 2
5
@
@
SMB_CLK_S3
1 2 1 2
Pull up at EC side.
2
EC_SMB_DA2
5
3 4
EC_SMB_CK2
1 2 1 2
1 2
R161 1M_0402_5%R161 1M_0402_5%
25MHZ 20PF +-20PPM X 3G025000DK1H-X
25MHZ 20PF +-20PPM X 3G025000DK1H-X Y2
Y2
1
1
1
2
U8
U8
1
NC
VCC
2
NC
WP
3
SCL
PROT#
4
SDA
GND
PCA24S08D_SO8
PCA24S08D_SO8 EEPROM SA00004MK00 EEPROM SA00004ML00
GND
5
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
8 7 6 5
GND
SMB_CLK_S3 SMB_DATA_S3
+3VS
SMB_DATA_S3 [12,30,35,36]
+3VS
SMB_CLK_S3 [12,30,35,36]
SMB_DATA_S3PCH_SMBDATA
EC_SMB_DA2 [24,30,36,38]
EC, VGA, Theraml
EC_SMB_CK2 [24,30,36,38]
EC_SMB_DA2PCH_SML1DATA
3
3
4
1
2
+3VS
ROM_WP
+3V_PCH
DDR, WALN
C88
C88 15P_0402_50V8J
15P_0402_50V8J
1
C91
C91
0.1U_0402_10V6K
0.1U_0402_10V6K
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
14 53Tuesday, February 26, 2013
14 53Tuesday, February 26, 2013
14 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
DMI_CTX_PRX_N0[5]
A A
B B
C C
+3VS
+3V_PCH
DMI_CTX_PRX_N1[5] DMI_CTX_PRX_N2[5] DMI_CTX_PRX_N3[5]
DMI_CTX_PRX_P0[5] DMI_CTX_PRX_P1[5] DMI_CTX_PRX_P2[5] DMI_CTX_PRX_P3[5]
DMI_CRX_PTX_N0[5] DMI_CRX_PTX_N1[5] DMI_CRX_PTX_N2[5] DMI_CRX_PTX_N3[5]
DMI_CRX_PTX_P0[5] DMI_CRX_PTX_P1[5] DMI_CRX_PTX_P2[5] DMI_CRX_PTX_P3[5]
PCH_PWROK[38]
PM_DRAM_PWRGD[6]
EC_RSMRST#[38]
PBTN_OUT#[38]
ACIN[38,42]
1 2
R204 200_0402_5%@R204 200_0402_5%@
1 2
R305 200_0402_5%@R305 200_0402_5%@
1 2
R205 10K_0402_5%R205 10K_0402_5%
1 2
R206 200K_0402_5%R206 200K_0402_5%
1 2
R210 10K_0402_5%R210 10K_0402_5%
PCH_PWROK
PM_DRAM_PWRGD
PM_DRAM_PWRGD
SUSWARN#
AC_PRESENT_R
EC_RSMRST#
2
+1.05VS
1 2
R186 49.9_0402_1%R186 49.9_0402_1%
1 2
R188 750_0402_1%R188 750_0402_1%
4mil width and place within 500mil of the PCH
+3VS
1 2
R24 1K _0402_5%R24 1K_0402_5%
1 2
R197 0_0402_5%@R197 0_0402_5%@
1 2
R198 0_0402_5%@R198 0_0402_5%@
1 2
D3
D3
PCH_GPIO72[14]
RI#[14]
1
T8
TPC12T8TPC12
APWROK
RB751V-40_SOD323-2
RB751V-40_SOD323-2
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
DMI_IRCOMP
RBIAS_CPY
SUSACK#_R
SYS_RST#
SYS_PWROK
PCH_POK_R
PM_DRAM_PWRGD
SUSWARN#
AC_PRESENT_R
PCH_GPIO72
RI#
VGATE[48]
U2408C
U2408C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
P+
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/ SUSPWRDNACK/ GPIO30
E20
H20
E10
A10
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
P+
PWRBTN#
ACPRESENT / GPIO31
BATLOW# / GPIO72
RI#
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
PCH_PWROK
3
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6
DMI
FDI
DMI
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
System Power Management
System Power Management
SLP_S3#
SLP_A#
P-
P+
+3VS
U9
U9
1
IN1
2
IN2
5
VCC
OUT
GND
3
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
4
SYS_PWROK
12
R211
R211 100K_0402_5%
100K_0402_5%
BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9
BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
EC_RSMRST#
PCIE_WAKE#
PM_CLKRUN#
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PCH_SLPA#
PM_SLP_SUS#
H_PM_SYNC
PCH_GPIO29
4
1
1
1
1
1
1
FDI_CTX_PRX_N0 [5] FDI_CTX_PRX_N1 [5] FDI_CTX_PRX_N2 [5] FDI_CTX_PRX_N3 [5] FDI_CTX_PRX_N4 [5] FDI_CTX_PRX_N5 [5] FDI_CTX_PRX_N6 [5] FDI_CTX_PRX_N7 [5]
FDI_CTX_PRX_P0 [5] FDI_CTX_PRX_P1 [5] FDI_CTX_PRX_P2 [5] FDI_CTX_PRX_P3 [5] FDI_CTX_PRX_P4 [5] FDI_CTX_PRX_P5 [5] FDI_CTX_PRX_P6 [5] FDI_CTX_PRX_P7 [5]
FDI_INT [5]
FDI_FSYNC0 [5]
FDI_FSYNC1 [5]
FDI_LSYNC0 [5]
FDI_LSYNC1 [5]
PCIE_WAKE# [14,33]
PM_CLKRUN# [18]
SUSCLK [38]
T11T11
PM_SLP_S5# [38]
T12T12
PM_SLP_S4# [38]
T13T13
PM_SLP_S3# [38]
T16T16
T14T14
T15T15
H_PM_SYNC [6]
5
DSWODVREN
DSWODVREN - On Die DSW VR Enable
Enable
H
*
Disable
L
PCH_GPIO29
PM_CLKRUN#
EC team suggestion South Bridge side must have pull-low 10K on this pin(GPIO32) Use CLKRUN# Requires a 8.2- k weak pull-up resistor to Vcc3_3S
Can be left NC when IAMT is not support on the platfrom
1 2
R185 330K_0402_5%R185 330K_0402_5%
1 2
R187 330K_0402_5%@R187 330K_0402_5%@
1 2
R195 10K_0402_5%@R195 10K_0402_5%@
1 2
R199 10K_0402_5%@R199 10K_0402_5%@
+RTCVCC
+3V_PCH
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (3/8) DMI,FDI,PM,
PCH (3/8) DMI,FDI,PM,
PCH (3/8) DMI,FDI,PM,
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
of
15 53Tuesday, February 26, 2013
15 53Tuesday, February 26, 2013
15 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
A A
R253 100K_0402_5%R253 100K_0402_5%
B B
C C
12
ENBKL
2
U2408D
U2408D
ENBKL[38] PCH_ENVDD[30]
PCH_PWM[30]
CRT_IREF
R223
R223
1K_0402_5%
1K_0402_5%
1 2
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
3
P-
SDVO_TVCLKINN
P-
SDVO_TVCLKINP
P-
SDVO_STALLN
P-
P-
LVDS
LVDS
CRT
CRT
SDVO_STALLP
P-
SDVO_INTN
P-
SDVO_INTP
SDVO_CTRLCLK
P-
SDVO_CTRLDATA
DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
DDPC_CTRLCLK
P-
DDPC_CTRLDATA
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
P-
DDPD_CTRLDATA
DDPD_AUXN DDPD_AUXP
DDPD_HPD
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
4
AP43 AP45
AM42 AM40
AP39 AP40
P38
HDMICLK_NB
M39
HDMIDAT_NB
AT49 AT47 AT40
AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49
P46
PCH_DPC_CLK PCH_DPC_CLK
P42
AP47 AP49 AT38
AY47 AY49 AY43 AY45 BA47
PCH_DPC_N2
BA48
PCH_DPC_P2
BB47
PCH_DPC_N3
BB49
PCH_DPC_P3
M43 M36
AT45 AT43 BH41
BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42
ŝŐŝƚĂůŝƐƉůĂLJWŽƌƚƐŶĂďůĞĂŶĚŝƐĂďůĞ'ƵŝĚĞůŝŶĞƐ
WŽƌƚ ^ƚƌĂƉ
>s^
WŽƌƚ
WŽƌƚ
WŽƌƚ
HDMICLK_NB [37] HDMIDAT_NB [37]
PCH_DPB_HPD [37]
PCH_DPB_N0 [37] PCH_DPB_P0 [37] PCH_DPB_N1 [37] PCH_DPB_P1 [37] PCH_DPB_N2 [37] PCH_DPB_P2 [37] PCH_DPB_N3 [37] PCH_DPB_P3 [37]
PCH_DPC_AUXN [31] PCH_DPC_AUXP [31] PCH_DPC_HPD [31]
PCH_DPC_N0 [31] PCH_DPC_P0 [31] PCH_DPC_N1 [31] PCH_DPC_P1 [31]
1 1
T222T222
1
T223T223
1
T224T224 T225T225
>ͺͺd
^sKͺdZ>d
WͺdZ>d
WͺdZ>d
HDMI
DP
,ŽǁƚŽŶĂďůĞ
WƵůůͲŚŝŐŚƚŽϯϯsǁŝƚŚϮϮŬͺϱйKŚŵ
WƵůůͲŚŝŐŚƚŽϯϯsǁŝƚŚϮϮŬͺϱйKŚŵ
WƵůůͲŚŝŐŚƚŽϯϯsǁŝƚŚϮϮŬͺϱйKŚŵ
WƵůůͲŚŝŐŚƚŽϯϯsǁŝƚŚϮϮŬͺϱйKŚŵ
HDMICLK_NB HDMIDAT_NB
PCH_DPC_DATPCH_DPC_DAT
,ŽǁƚŽŝƐĂďůĞ
EŽŽŶŶĞĐƚ
EŽŽŶŶĞĐƚ
EŽŽŶŶĞĐƚ
EŽŽŶŶĞĐƚ
5
+3VS
12
R21482.2K_0402_1% R21482.2K_0402_1%
12
R21432.2K_0402_1% R21432.2K_0402_1%
12
R21462.2K_0402_5% @ R21462. 2K_0402_5% @
12
R21452.2K_0402_5% R21452.2K_0402_5%
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
16 53Tuesday, February 26, 2013
16 53Tuesday, February 26, 2013
16 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
A A
'EdϬη'Edϭη'W/Kϱϭ'EdϮη'W/Kϱϯ'Edϯη'W/Kϱϱ W/'ƌĂŶƚƐdŚĞW,ƐƵƉƉŽƌƚƐƵƉƚŽϰŵĂƐƚĞƌƐŽŶƚŚĞW/ ďƵƐ 'Ed΀ϯϭ΁ηƉŝŶƐĐĂŶŝŶƐƚĞĂĚďĞƵƐĞĚĂƐ'W/K WƵůůͲƵƉƌĞƐŝƐƚŽƌƐĂƌĞŶŽƚƌĞƋƵŝƌĞĚŽŶƚŚĞƐĞƐŝŐŶĂůƐ/ĨƉƵůůͲ ƵƉƐĂƌĞƵƐĞĚƚŚĞLJƐŚŽƵůĚďĞƚŝĞĚƚŽƚŚĞsĐĐϯͺϯƉŽǁĞƌƌĂŝů EKd^ ϭ'Ed΀ϯϭ΁η'W/K΀ϱϱϱϯϱϭ΁ĂƌĞƐĂŵƉůĞĚĂƐĂ ĨƵŶĐƚŝŽŶĂůƐƚƌĂƉ^ĞĞ^ĞĐƚŝŽŶϮϮϳĨŽƌĚĞƚĂŝůƐ
USB3_RX0_N[ 37] USB3_RX1_N[ 35] USB3_RX2_N[ 31]
USB3_RX0_P[37] USB3_RX1_P[35] USB3_RX2_P[31]
USB3_TX0_N[37] USB3_TX1_N[35] USB3_TX2_N[31]
USB3_TX0_P[37] USB3_TX1_P[35] USB3_TX2_P[31]
'W/KϱϬϱϮϱϰĚĞĨĂƵůƚсEĂƚŝǀĞ dŽƵĐŚƉĂŶĞů
DGPU_HOLD_RST#[23] TS_ON[30] DGPU_PWR_EN[25,47,51]
BT_DET#[35]
MSATS_DEVSLP[34]
PCI_PME#[38]
PCH_PLTRST#[6]
CLK_PCI_LPBACK[14] CLK_PCI_EC[38] CLK_PCI_DB[37] CLK_PCI_TPM[37]
PCH_PLTRST#
RP8
+3VS
PCH_GPIO4 PCH_GPIO5 PCH_GPIO2 PCH_GPIO3
+3VS
R239 10K_0402_5%R239 10K_0402_5%
R240 10K_0402_5%@R240 10K_0402_5%@
R235 10K_0402_5%@R235 10K_0402_5%@
R231 10K_0402_5%R231 10K_0402_5%
B B
R236 10K_0402_5%@R236 10K_0402_5%@
R246 10K_0402_5%R246 10K_0402_5%
R244 10K_0402_5%@R244 10K_0402_5%@
R232 10K_0402_5%@R232 10K_0402_5%@
R234 10K_0402_5%@R234 10K_0402_5%@
R190 10K_0402_5%R190 10K_0402_5%
R243 1K_0402_5%@R243 1K_0402_5%@
Boot BIOS Strap bit1 BBS1
C C
R245 1K_0402_5%@R245 1K_0402_5%@
A16 swap overide Strap/Top-Block Swap Override jumper
PCI_GNT3#
D D
RP8
1 2 3 4 5
10K_1206_10P8R_5%
10K_1206_10P8R_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
GPIO19GPIO51
Bit11
Bit10
1
0
0
1
1
1
0
0
1 2
Low=A16 swap override/Top-Block Swap Override enabled High=Default
10 9 8 7 6
Boot BIOS Destination
Reserved
PCI
SPI
*
LPC
PCH_GPIO55
PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQA#
PCH_GPIO51
PCH_GPIO53
PCH_GPIO55
PCH_GPIO50
PCH_GPIO52
PCH_GPIO54
PCH_GPIO54
PCH_GPIO50
PCH_PLTRST#
PCH_GPIO52
PCH_GPIO51
(Default)
*
+3VS
2
R251 0_0402_5%@R251 0_0402_5%@
@
@
TC7SH08FUF_SSOP5
TC7SH08FUF_SSOP5
CLK_PCI_EC
1 2
+3VS
5
1
B
2
A
3
DIS@
DIS@
U11
U11
P
G
1 2
R254 0_0402_5%@R254 0_0402_5%@
1 2
R337 0_0402_5%@R337 0_0402_5%@
1 2
R264 0_0402_5%@R264 0_0402_5%@
1 2
R332 0_0402_5%@R332 0_0402_5%@
1 2
R296 0_0402_5%@R296 0_0402_5%@
1 2
R248 22_0402_5%R248 22_0402_5%
1 2
R249 22_0402_5%R249 22_0402_5%
1 2
R250 22_0402_5%R250 22_0402_5%
1 2
R350 22_0402_5%TPM@ R350 22_0402_5%TPM @
4
Y
12
R255
R255 100K_0402_5%
100K_0402_5%
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
PCH_GPIO50 PCH_GPIO52 PCH_GPIO54
PCH_GPIO51 PCH_GPIO53 PCH_GPIO55
PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5
PCH_PLTRST#
CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3
PLT_RST# [14,23,33,35,37,38]
U2408E
U2408E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3Tp1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
3
AY7
RSVD1
AV7
RSVD2
AU3
RSVD3
BG4
RSVD4
AT10
RSVD5
BC8
RSVD6
AU2
RSVD7
AT4
RSVD8
AT3
RSVD9
AT1
RSVD10
AY3
RSVD11
AT5
RSVD12
AV3
RSVD13
AV1
RSVD14
BB1
RSVD15
BA3
RSVD16
BB5
RSVD17
BB3
RSVD18
BB7
RSVD19
BE8
RSVD20
BD4
RSVD21
BF6
RSVD22
RSVD
RSVD
P-
PCI
PCI
USB
USB
P+ P+ P+
P+
P­P­P­P­P-
RSVD23 RSVD24
RSVD25
RSVD26 RSVD27
RSVD28 RSVD29
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N
USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43
OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14
AV5 AV10
AT8
AY5 BA2
AT12 BF3
C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32
C33
B33
A14 K20 B17 C16 L16 A16 D14 C14
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3
USB20_N8 USB20_P8
1
1 USB20_N10 USB20_P10 USB20_N11 USB20_P11
Within 500 mils
USBRBIAS
R247 22.6_0402_1%R247 22.6_0402_1%
USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4#
4
USB20_N0 [37] USB20_P0 [37] USB20_N1 [35] USB20_P1 [35] USB20_N2 [31] USB20_P2 [31] USB20_N3 [30] USB20_P3 [30]
USB20_N8 [30]
USB20_P8 [30] T26T26 T28T28
USB20_N10 [35]
USB20_P10 [35]
USB20_N11 [37]
USB20_P11 [37]
1 2
USB_OC0# [35,37]
KϬηh^ϯϬ;/KŽĂƌĚͿ;DͿ
h^ϯϬ;/KŽĂƌĚͿ
h^ϯϬ;DͿ
h^ϯϬ;ŽĐŬŝŶŐͿ
DK^ĂŵĞƌĂ;>s^Ϳ
;dĞƐƚWŽŝŶƚĨŽƌ/K^ĞďƵŐͿ
DŝŶŝĂƌĚ;t>EdͿ
&ŝŶŐĞƌWƌŝŶƚ
OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2
USB_OC1# USB_OC0# USB_OC2# USB_OC3#
USB_OC4#
1 8 2 7 3 6 4 5
R180 10K_0402_5%R180 10K_0402_5%
5
R233
R233
10K_8P4R_5%
10K_8P4R_5%
+3V_PCH
12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (5/9) PCI, USB, NVRAM
PCH (5/9) PCI, USB, NVRAM
PCH (5/9) PCI, USB, NVRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
of
17 53Wednesday, February 27, 2013
17 53Wednesday, February 27, 2013
17 53Wednesday, February 27, 2013
0.4
0.4
0.4
GPIO28
On-Die PLL Voltage Regulator This signal has a weak internal pull up
On-Die voltage regulator enable
H
*
L烉On-Die PLL Voltage Regulator disable
1 2
R265 1K_0402_5%@R265 1K_0402_5%@
1 2
A A
B B
C C
R274 1K_0402_5%@R274 1K_0402_5%@
+3VS
R280 10K_0402_5%@R280 10K_0402_5%@ R282 10K_0402_5%R282 10K_0402_5%
+3V_PCH
R288 10K_0402_5%R288 10K_0402_5% R290 10K_0402_5%@R290 10K_0402_5%@
+3VS
R285 10K_0402_5%@R285 10K_0402_5%@ R284 10K_0402_5%R284 10K_0402_5%
+3VS
+3V_PCH
+3VS
R266 10K_0402_5%@R266 10K_0402_5%@
R344 10K_0402_5%@R344 10K_0402_5%@
R275 10K_0402_5%R275 10K_0402_5%
R268 10K_0402_5%R268 10K_0402_5%
R346 10K_0402_5%@R346 10K_0402_5%@
R283 10K_0402_5%@R283 10K_0402_5%@
R287 10K_0402_5%@R287 10K_0402_5%@
R289 10K_0402_5%@R289 10K_0402_5%@
+3V_PCH
R293 100K_0402_5%R293 100K_0402_5%
R271 10K_0402_5%R271 10K_0402_5%
R273 1K_0402_5%R273 1K_0402_5%
R292 10K_0402_5%@R292 10K_0402_5%@
1 2 1 2
1 2 1 2
1 2 1 2
RP4
RP4
1 8 2 7 3 6 4 5
10K_8P4R_5%
10K_8P4R_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCH_GPIO69
1
PCH_GPIO28
EC_SMI#
WLBT_OFF_51#
PCH_GPIO24
PCH_GPIO37
PCH_GPIO0 PM_CLKRUN# PCH_GPIO28 PCH_GPIO47
DOCK_PRSNT#
EC_SCI#
PCH_GPIO16
DGPU_PWROK
PCH_GPIO34
PCH_GPIO35
PCH_GPIO39
PCH_GPIO48
PCH_GPIO27
PCH_GPIO12
PCH_GPIO15
PCH_GPIO57
PCH_GPIO38 PCH_GPIO67
PM_CLKRUN# [15]
PCH_GPIO47 [14]
Function
TS_INT#[30]
DOCK_PRSNT#[31]
EC_SCI#[38]
EC_SMI#[14,38]
EC_WAKE#[38]
DGPU_PWROK[38,47]
PCH_GPIO22[13]
WLBT_OFF_51#[35]
PCH_GPIO49[13]
2
R178 0_0402_5%@R178 0_0402_5%@
1 2
PCH_GPIO0
TS_INT#
DOCK_PRSNT#
EC_SCI#
EC_SMI#
PCH_GPIO12
PCH_GPIO15
PCH_GPIO16
DGPU_PWROK
PCH_GPIO22
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
PCH_GPIO34
PCH_GPIO35
WLBT_OFF_51#
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
PCH_GPIO48
PCH_GPIO49
PCH_GPIO57
T22T22
T24T24
T26
T28
T30T30
T32T32
T34T34
T36
T38T38
T40T40
T42T42
T44T44
T46T46
T48T48
U2408F
U2408F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PW R_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
1
VSS_NCTF_1
A44
1
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
1
VSS_NCTF_5
A6
1
VSS_NCTF_6
B3
1
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
1
VSS_NCTF_9
BD49
1
VSS_NCTF_10
BE1
1
VSS_NCTF_11
BE49
1
VSS_NCTF_12
BF1
1
VSS_NCTF_13
1
BF49
VSS_NCTF_14
PANTHER-POINT_FCBGA 989
PANTHER-POINT_FCBGA 989
3
C40
PECI
RCIN#
NC_1
TS_PRSNC#
B41
PCH_GPIO69
C41
PCH_GPIO70
A40
PCH_GPIO71
P4
AU16
PCH_PECI_R
P5
KB_RST#
AY11
H_CPUPWRGD
AY10
1 2
R278 390_0402_5%R278 390_0402_5%
T14
AY1
DF_TVS
AH8
AK11
AH10
AK10
P37
BG2
1
BG48
1
BH3
1
BH47
1
BJ4
1
BJ44
1
BJ45
1
BJ46
1
BJ5
1
BJ6
1
C2
1
C48
D1
1
D49
E1
1
E49
F1
1
F49
1 2
R267 0_0402_5%@R267 0_0402_5%@
INIT3_3V
This signal has weak internal PU, can't pull low
Intel schematic reviwe recommand.
T18T18
T19T19
T20T20
T21T21
T23T23
T25T25
T27T27
T29T29
T31T31
T33T33
T35T35
T39T39
T43T43
T47T47
P+
GPIO
GPIO
NCTF
NCTF
P+
P+
P+
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
P-
PROCPWRGD
THRMTRIP#
P+
INIT3_3V#
P-
DF_TVS
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
P+
P+
P+
P+
P-
P+
P+
P-
P-
TS_PRSNC# [30]
H_THRMTRIP#
4
GATEA20 [13,38]
H_PECI [38,6]
KB_RST# [13,38]
H_CPUPWRGD [6]
H_THRMTRIP# [6]
5
TS_PRSNC#
PCH_GPIO71 PCH_GPIO70 PCH_GPIO69 TS_INT#
DF_TVS
DMI Termination Voltage
NV_CLE
CLOSE TO THE BRANCHING POINT
1 2
R256 10K_0402_5%R256 10K_0402_5%
RP10
RP10
45 36 27 18
10K_8P4R_5%
10K_8P4R_5%
1 2
R229 1K_0402_5%R229 1K_0402_5%
Set to Vcc when HIGH
Set to Vss when LOW
+1.8VS
12
+3VS
R226
R226
2.2K_0402_5%
2.2K_0402_5%
H_SNB_IVB# [6]
0
0
0
0
12
R259
R259 10K_0402_5%
D D
10K_0402_5% @
@
Connect to RP10
0
0
01
1
0
11
+3VS
12
R330
R330 10K_0402_5%
10K_0402_5% UMA@
UMA@
12
R329
R329 10K_0402_5%
10K_0402_5% DIS@
DIS@
12
R311
R311 10K_0402_5%
10K_0402_5% UMA@
UMA@
12
R286
R286 10K_0402_5%
10K_0402_5% DIS@
DIS@
1
PCH_GPIO69 PCH_GPIO38 PCH_GPIO67
Optimus
Reserved
DIS
UMA
PCH_GPIO67 [14]
(MB_ID_2) (MB_ID_1) (MB_ID_0)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
18 53Tuesday, February 26, 2013
18 53Tuesday, February 26, 2013
18 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
A A
B B
C C
2
+1.05VS
C95
10U_0603_6.3V6M
C95
10U_0603_6.3V6M
C96
1U_0402_6.3V6K
C96
1U_0402_6.3V6K
C97
C97
1
1
1
2
2
2
+1.05VS
1
+VCCAPLLEXP
T50
T50
TPC12
+1.05VS
+3VS
C105
C105
C106
C106
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
1
C112
C112
0.1U_0402_10V6K
0.1U_0402_10V6K
2
TPC12
1U_0402_6.3V6K
1U_0402_6.3V6K
C107
C107
1
2
This pin can be left a s no connect in On-Die VR enabled mode (default).
Place C167 Near BG6 pin
1
C114
@C114
@
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1U_0402_6.3V6K
1U_0402_6.3V6K
C98
C98
1U_0402_6.3V6K
1U_0402_6.3V6K
C108
C108
+1.5VS
+1.05VS
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
C109
1U_0402_6.3V6K
C109
1U_0402_6.3V6K
1
1
2
2
+1.05VS_VCCAPLL_FDI
U2408G
U2408G
AA23
VCCCORE[1]
AC23
VCCCORE[2]
AD21
VCCCORE[3]
AD23
VCCCORE[4]
AF21
VCCCORE[5]
AF23
VCCCORE[6]
AG21
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9]
AG26
VCCCORE[10]
AG27
VCCCORE[11]
AG29
VCCCORE[12]
AJ23
VCCCORE[13]
AJ26
VCCCORE[14]
AJ27
VCCCORE[15]
AJ29
VCCCORE[16]
AJ31
VCCCORE[17]
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VccAFDIPLL
AP17
VCCIO[27]
AU20
VCCDMI[2]
PANTHER-POINT_FCB GA989
PANTHER-POINT_FCB GA989
ϭϳϯ
ϯϳϵϵ
3
POWER
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
ϲϯŵ
CRTLVDS
CRTLVDS
ϭŵ
VCCTX_LVDS[1]
ϰϬŵ
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
ϭϰϳŵ
ϰϳŵ
DMI
DMI
ϳϱŵ
Ϯŵ
DFT / SPI HVCMOS
DFT / SPI HVCMOS
ϭϬŵ
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
VCCSPI
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
+VCCADAC
VCCALVDS
+VCCTX_LVDS
0.1U_0402_10V6K
0.1U_0402_10V6K
12
R215
R215 0_0402_5%
0_0402_5% @
@
C163
C163
C94
1U_0402_16V7K@C94
1U_0402_16V7K
1
@
2
12
1
C104
C104
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1
C111
C111 1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
2
+3VS
1
C115
C115 1U_0402_6.3V6K
1U_0402_6.3V6K
2
4
+3VS
C160
10U_0603_6.3V6M@C160
C99
0.1U_0402_10V6K
C99
0.1U_0402_10V6K
1
2
Disable LVDS VCCTX_LVDS and VCCA_LVD can be connected to ground(DG 471984 P196)
R216
R216 0_0402_5%
0_0402_5% @
@
+3VS
+1.05VS
+1.8VS
1
@
@ C113
C113 1U_0402_6.3V6K
1U_0402_6.3V6K
2
10U_0603_6.3V6M
C100
10U_0603_6.3V6M@C100
10U_0603_6.3V6M
1
1
@
@
2
2
+1.5VS
VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP
+1.05VS
1
C110
C110 1U_0402_6.3V6K
1U_0402_6.3V6K
2
5
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (7/9) PWR
PCH (7/9) PWR
PCH (7/9) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
19 53Tuesday, February 26, 2013
19 53Tuesday, February 26, 2013
19 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
+3VALW
+1.05VS
R307 0_0603_5%@R307 0_0603_5%@
Have internal VRM
1 2
2
+VCCACLK
3
4
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
5
C145
C145
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.5VS
+3V_PCH
1
C158
C158
0.1U_0402_10V6K
0.1U_0402_10V6K
2
Deciphered Date
Deciphered Date
Deciphered Date
+1.05VS
+3V_PCH
+1.05VS
+3V_PCH
+3VS
+1.05VS
1
2
+1.05VS
1
2
4
+1.05VS_VCCAUPLL
+1.05VS_SATA3
C148
C148 1U_0402_6.3V6K
1U_0402_6.3V6K
+3V_PCH
+5VALW
12
D4
D4
R315
RB751V-40_SOD323-2
RB751V-40_SOD323-2
+PCH_V5REF_SUS
C126
C126
0.1U_0402_10V6K
0.1U_0402_10V6K
RB751V-40_SOD323-2
RB751V-40_SOD323-2
+PCH_V5REF_RUN
C135
C135
1U_0402_6.3V6K
1U_0402_6.3V6K
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (8/9) PWR
PCH (8/9) PWR
PCH (8/9) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
1 2
1
2
+3VS +5VS
D5
D5
1 2
1
2
20 53Tuesday, February 26, 2013
20 53Tuesday, February 26, 2013
20 53Tuesday, February 26, 2013
R315 10_0402_5%
10_0402_5%
12
R318
R318 10_0402_5%
10_0402_5%
of
0.4
0.4
0.4
POWER
U2408J
A A
+3VS
C117
1U_0402_6.3V6K@C117
C116
@
B B
C C
D D
1U_0402_6.3V6K
10U_0603_6.3V6M@C116
10U_0603_6.3V6M
1
1
@
2
2
+1.05VS
+1.05VS
ŶƐƵƌĞŝŶĚĞƉĞŶĚĞŶƚƉŽǁĞƌ ƌŽƵƚŝŶŐĨŽƌ^^ĂŶĚ/&&><E
1
If platform does not support Deep S4/S5 then tie to VccSus3_3.
+1.05VS
нsW>>ͺWz
L4
L4
1 2
10UH_LB2012T100MR_20%
10UH_LB2012T100MR_20%
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
1 2
R336 0_0402_5%
R336 0_0402_5%
@
@
+1.05VS_VCCA_A_DPL
C136
C136
+3VS
+1.05VS
C127
C127
1
+
+
2
1
C144
C144 1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C146
C146 1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C149
C149 1U_0402_6.3V6K
1U_0402_6.3V6K
2
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.05VS
C152
C152
1U_0402_6.3V6K
1U_0402_6.3V6K
C128
C128
1
2
C137
C137
1
1U_0402_6.3V6K
1U_0402_6.3V6K
2
C153
C153
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2
1
2
C150
C150
1
2
C121
C123
C124
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C129
C129
1
2
2
1
2
1
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1 2
@C121
@
0.1U_0402_10V6K
0.1U_0402_10V6K
12
@C123
@
10U_0603_6.3V6M
10U_0603_6.3V6M
1 2
@C124
@
1U_0402_6.3V6K
1U_0402_6.3V6K
C130
22U_0805_6.3V6M
C130
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1 2
C143
C143
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.05VS_VCCA_A_DPL
+1.05VS_SSCVCC
1
C151
C151 1U_0402_6.3V6K
1U_0402_6.3V6K
2
@
@
+RTCVCC
C155
C155
C118
C118
+PCH_VCCDSW
+VCCAPLL_CPY_PCH
+VCCSUS1
C131
22U_0805_6.3V6M@C131
22U_0805_6.3V6M
1
@
2
+VCCRTCEXT
+1.5VS
+VCCSST
+1.05VM_VCCSUS
C157
0.1U_0402_10V6K
C157
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
U2408J
AD49
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3[5]
BH23
VCCAPLLDMI2
AL29
VCCIO[14]
AL24
DCPSUS[3]
AA19
VCCASW[1]
AA21
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD29
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
N16
DCPRTC
Y49
VCCVRM[4]
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO[7]
AF33
VCCDIFFCLKN[1]
AF34
VCCDIFFCLKN[2]
AG34
VCCDIFFCLKN[3]
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS[1]
V19
DCPSUS[2]
BJ8
V_PROC_IO
A22
VCCRTC
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
POWER
VCCIO[29]
ϭϭϵŵ
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
ϭϬŵ
HDA
HDA
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCIO[34]
V5REF_SUS
ϭŵ
DCPSUS[4]
VCCSUS3_3[1]
V5REF
ϭŵ
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
ϭϳϴŵ
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12]
VCCIO[13]
VCCIO[6]
VCCAPLLSATA
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
VCCASW[22]
VCCASW[23]
VCCASW[21]
VCCSUSHDA
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
ϭŵ
ϴϬϯŵ
Clock and Miscellaneous
Clock and Miscellaneous
ϳϱŵ
ϳϱŵ
ϱϱŵ
ϵϱŵ
Ϯŵ
CPURTC
CPURTC
N26
P26
P28
T27
T29
T23
T24
V23
V24
P24
T26
M26
+PCH_V5REF_SUS
AN23
+VCCA_USBSUS
AN24
+3V_PCH
P34
+PCH_V5REF_RUN
N20
+3V_PCH
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
Place C199 Near AK1 pin
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
Issued Date
Issued Date
Issued Date
1
C120
C120 1U_0402_6.3V6K
1U_0402_6.3V6K
2
+1.05VS_VCCUSBCORE
1
C122
C122
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1
C125
C125
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1
C132
@C132
@
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C133
C133
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1
C134
C134 1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C140
C140
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1
C142
C142
0.1U_0402_10V6K
0.1U_0402_10V6K
2
+VCCSATAPLL
1
C147
C147 10U_0603_6.3V6M
10U_0603_6.3V6M @
@
2
+1.05VS_VCC_SATA
+1.05VS
Compal Secret Data
Compal Secret Data
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
1
A A
B B
C C
U2408H
U2408H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
2
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
3
U2408I
U2408I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]
4
H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28
5
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCH (9/9) VSS
PCH (9/9) VSS
PCH (9/9) VSS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
21 53Tuesday, February 26, 2013
21 53Tuesday, February 26, 2013
21 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
A A
Power-Up/Down Sequence
1. All the ASIC supplies must reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up dur ation is preferred. The maximum slew rate on all rails is 50 mV/ȝs.
2. The exte rnal pull ups on the DDC/AUX signals (if applic able) should ramp up before or after both VDDC and VDD_CT have ramped up.
3. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC should reach 90% before VDD_CT starts to ramp up (or vice versa).
4. For power down, reversing the ramp-up sequence is recommended.
VDDR3(3.3VGS)
B B
VDDC/VDDCI(GPU_CORE)
PCIE_VDDC(0.95V)
VDDR1(1.5VGS)
W,
'W/KϱϬ
'W/Kϱϰ
d,Ϭ'W/Kϭϳ
PLT_RST#
DGPU_HOLD_RST
DGPU_PWR_EN
DGPU_PWROK
VDD_CT(1.8V)
EKd
E 'd
PLT_RST_VGA#
DGPU_PWR_EN#
WZ^d
'Wh
PERSTb
нϯs^
нϯs^
н
MOS
Regulator
PWM
REFCLK
Straps Reset
C C
Straps Valid
Global ASIC Reset
T4+16clock
ϭ
Ϯ
ϰ
нϯs^ͺs'
нϬϵϱs^ͺs'
нs'ͺKZ
нϭϴs^
нϭϱs^
ϱ
ϯ
нϭϴs^ͺs'
нϭϱs^ͺs'
MOS
MOS
CPU part
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
MARS_Note
MARS_Note
MARS_Note
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
22 53Tuesday, February 26, 2013
22 53Tuesday, February 26, 2013
22 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
A A
PCIE_CTX_GRX_N[0..7][5]
PCIE_CTX_GRX_P[0..7][5]
PCIE_CRX_GTX_N[0..7][5]
PCIE_CRX_GTX_P[0..7][5]
B B
C C
PCIE_CTX_GRX_N[0..7]
PCIE_CTX_GRX_P[0..7]
PCIE_CRX_GTX_N[0..7]
PCIE_CRX_GTX_P[0..7]
CLK_PCIE_VGA[14] CLK_PCIE_VGA#[14]
1 2
R1400 1K_0402_5%DIS@R1400 1K_0402_5%DIS@
PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7
CLK_PCIE_VGA CLK_PCIE_VGA#
PLT_RST_VGA#
2
DIS@
DIS@ U666A
U666A
3
4
5
DIS@
AF30
AE31
AE29 AD28
AD30 AC31
AC29 AB28
AB30 AA31
AA29
AK30 AK32
AL27
Y28
Y30
W31
W29
V28
V30 U31
U29
T28
T30 R31
R29 P28
P30 N31
N29 M28
M30
L31
L29
K30
N10
PCIE_RX0P PCIE_RX0N
PCIE_RX1P PCIE_RX1N
PCIE_RX2P PCIE_RX2N
PCIE_RX3P PCIE_RX3N
PCIE_RX4P PCIE_RX4N
PCIE_RX5P PCIE_RX5N
PCIE_RX6P PCIE_RX6N
PCIE_RX7P PCIE_RX7N
NC#V30 NC#U31
NC#U29 NC#T28
NC#T30 NC#R31
NC#R29 NC#P28
NC#P30 NC#N31
NC#N29 NC#M28
NC#M30 NC#L31
NC#L29 NC#K30
CLOCK
CLOCK
PCIE_REFCLKP PCIE_REFCLKN
TEST_PG
PERSTB
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
CALIBRATION
CALIBRATION
PCIE_CALR_TX
PCIE_CALR_RX
PCIE_TX0P PCIE_TX0N
PCIE_TX1P PCIE_TX1N
PCIE_TX2P PCIE_TX2N
PCIE_TX3P PCIE_TX3N
PCIE_TX4P PCIE_TX4N
PCIE_TX5P PCIE_TX5N
PCIE_TX6P PCIE_TX6N
PCIE_TX7P PCIE_TX7N
NC#W24 NC#W23
NC#V27
NC#U26
NC#U24 NC#U23
NC#T26 NC#T27
NC#T24 NC#T23
NC#P27 NC#P26
NC#P24 NC#P23
NC#M27 NC#N26
AH30
PCIE_CRX_C_GTX_P0
AG31
PCIE_CRX_C_GTX_N0
AG29
PCIE_CRX_C_GTX_P1
AF28
PCIE_CRX_C_GTX_N1
AF27
PCIE_CRX_C_GTX_P2
AF26
PCIE_CRX_C_GTX_N2
AD27
PCIE_CRX_C_GTX_P3
AD26
PCIE_CRX_C_GTX_N3
AC25
PCIE_CRX_C_GTX_P4
AB25
Y23
PCIE_CRX_C_GTX_P5
Y24
PCIE_CRX_C_GTX_N5
AB27
PCIE_CRX_C_GTX_P6
AB26
PCIE_CRX_C_GTX_N6
Y27
PCIE_CRX_C_GTX_P7 PCIE_CRX_GTX_P7
Y26
PCIE_CRX_C_GTX_N7
W24 W23
V27 U26
U24 U23
T26 T27
T24 T23
P27 P26
P24 P23
M27 N26
Y22
AA22
1 2
R5159 1.69K_0402_1%DIS@R5159 1.69K_0402_1%DIS@
1 2
R717 1K_0402_1%DIS@R717 1K_0402_1%DIS@
+0.95VS_VGA
12 12
12 12
12 12
12 12
12 12
12 12
12 12
12 12
C51870.1U_0402_10V7K DIS@ C51870.1U_0402_10V7K DIS@ C51880.1U_0402_10V7K DIS@ C51880.1U_0402_10V7K DIS@
C51890.1U_0402_10V7K DIS@ C51890.1U_0402_10V7K DIS@ C51900.1U_0402_10V7K DIS@ C51900.1U_0402_10V7K DIS@
C51910.1U_0402_10V7K DIS@ C51910.1U_0402_10V7K DIS@ C51920.1U_0402_10V7K DIS@ C51920.1U_0402_10V7K DIS@
C51930.1U_0402_10V7K DIS@ C51930.1U_0402_10V7K DIS@ C51940.1U_0402_10V7K DIS@ C51940.1U_0402_10V7K DIS@
C51950.1U_0402_10V7K DIS@ C51950.1U_0402_10V7K DIS@ C51960.1U_0402_10V7K DIS@ C51960.1U_0402_10V7K DIS@
C51970.1U_0402_10V7K DIS@ C51970.1U_0402_10V7K DIS@ C51980.1U_0402_10V7K DIS@ C51980.1U_0402_10V7K DIS@
C51990.1U_0402_10V7K DIS@ C51990.1U_0402_10V7K DIS@ C52000.1U_0402_10V7K DIS@ C52000.1U_0402_10V7K DIS@
C52010.1U_0402_10V7K DIS@ C52010.1U_0402_10V7K DIS@ C52020.1U_0402_10V7K DIS@ C52020.1U_0402_10V7K DIS@
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4PCIE_CRX_C_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N7
EŽhƐĞ'WhŝƐƉůĂLJWŽƌƚŽƵƚƉƵĚ
DIS@
DIS@ U666F
U666F
AB11
VARY_BL
AB12
DIGON
AL15
TXCAP_DPA3P
TX0P_DPA2P TX0M_DPA2N
TX1P_DPA1P TX1M_DPA1N
TX2P_DPA0P TX2M_DPA0N
TXCBP_DPB3P
TX3P_DPB2P TX3M_DPB2N
TX4P_DPB1P TX4M_DPB1N
TX5P_DPB0P TX5M_DPB0N
AK14
AH16 AJ15
AL17 AK16
AH18 AJ17
AL19 AK18
AH20 AJ19
AL21 AK20
AH22 AJ21
AL23 AK22
AK24 AJ23
TXCAM_DPA3N
NC_TXOUT_L3P NC_TXOUT_L3N
TMDP
TMDP
TXCBM_DPB3N
NC_TXOUT_U3P NC_TXOUT_U3N
216-0842024-A11-MAR_FCBGA631
216-0842024-A11-MAR_FCBGA631
?
?
+3VS_VGA +3VS_VGA
R1437
@R1437
@
1 2
0_0402_5%
0_0402_5%
PLT_RST#[14,17,33,35,37,38]
D D
1
DGPU_HOLD_RST#[17]
PLT_RST#
DGPU_HOLD_RST#
2
5
1
B
2
A
TC7SH08FUF_SSOP5
TC7SH08FUF_SSOP5
3
12
@
@ R1438
R1438 10K_0402_5%
DIS@
DIS@ U1402
U1402
P
G
10K_0402_5%
4
Y
PLT_RST_VGA#
12
DIS@
DIS@ R1441
R1441 10K_0402_5%
10K_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
MARS_PCIE/DP
MARS_PCIE/DP
MARS_PCIE/DP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
23 53Tuesday, February 26, 2013
23 53Tuesday, February 26, 2013
23 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
A A
+3VS_VGA
12
12
DIS@
DIS@
DIS@
DIS@
2
G
G
10K_0402_5%
10K_0402_5%
6 1
S
EC_SMB_DA2[14,30,36,38]
B B
C C
D D
10P_0402_50V8J
10P_0402_50V8J
@
@
C2506
C2506
0.1U_0402_10V6K
0.1U_0402_10V6K
DIS@
DIS@ C341
C341
EC_SMB_CK2[14,30,36,38]
+3VS_VGA
+3VS_VGA
EC_SMB_CK2
ϬϵϮϰ
1 2
R1456 10K_0402_5%@R1456 10K_0402_5%@
RP2
RP2
@
@
1 8 2 7 3 6 4 5
10K_8P4R_5%
10K_8P4R_5%
1 2
R1439 1K_0402_5%DIS@R1439 1K_0402_5%DIS@
1 2
XTALIN XTALOUT
R349
10M_0402_5%
10M_0402_5%
Y6
DIS@
Y6
DIS@
4
NC
OSC
1
OSC
27MHZ 16PF +-30PPM X3G027000FG1H-HX
27MHZ 16PF +-30PPM X3G027000FG1H-HX
2
1
1
2
NC
SJ100009700
SJ100009700
VGA_DPLUS VGA _DMINUS
1
D
D
Q2416A
Q2416A DIS@
DIS@
VGA_AC__BATT
JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS
TESTEN
DIS@R349
DIS@
3
2
C323 1000P_0402_50V7K@C323 1000P_0402_50V7K@
@ U2410
@
1
VDD1
6
ALERT#
4
THERM#
5
GND
SDATA
ADM1032ARMZ_MSOP8
ADM1032ARMZ_MSOP8
S
3 4
D
D
Q2416B
Q2416B DIS@
DIS@
1 2
U2410
D+
D-
SCLK
5
G
G
2
DIS@
DIS@ C350
C350 10P_0402_50V8J
10P_0402_50V8J
1
2
3
8
7
R327
R327
S
S
VGA_DPLUS
VGA_DMINUS
VGA_SMB_CK2_R
VGA_SMB_DA2_R
R328
R328 10K_0402_5%
10K_0402_5%
VGA_SMB_DA2_REC_SMB_DA2
VGA_SMB_CK2_R
R301 0_0402_5%@R301 0_0402_5%@
R304 0_0402_5%@R304 0_0402_5%@
VGA_AC_DET[38,47]
GPU_VID1[47]
GPU_VID2[47] GPU_VID5[47]
GPU_VID4[47] GPU_VID3[47] GPU_CLKREQA[14]
><ZYϬKŚŵƌĞƐĞƌǀĞΛW,ƐŝĚĞ
1 2
1 2
+1.8VS_VGA
2
R321 10K_0402_5%DIS@R321 10K_0402_5%DIS@
+1.8VS_VGA
R331 499_0402_1%DIS@R331 499_0402_1%DIS@
R333 249_0402_1%DIS@R333 249_0402_1%DIS@
C322 0.1U_0402_10V6KDIS@C322 0.1U_0402_10V6KDIS@
1 2
R1442 10K_0402_5%DIS@R1442 10K_0402_5%DIS@
ŶĂďůĞD>W^
L54
DIS@L54
DIS@
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
12
C414 10U_0603_6.3V6MDIS@C414 10U_0603_6.3V6MDIS@
12
C421 1U_0402_6.3V4ZDIS@C421 1U_0402_6.3V4ZDIS@
12
C438 0.1U_0402_10V6KDIS@C438 0.1U_0402_10V6KDIS @
2
VGA_SMB_DA2
VGA_SMB_CK2
1 2
RB751V-40_SOD323-2
RB751V-40_SOD323-2
1 2
12
12
12
ϭϯŵ
D2416
D2416
3
DIS@
DIS@ U666B
U666B
1
N9
T201T201 T202T202 T203T203 T204T204 T205T205 T206T206 T207T207 T208T208 T209T209 T210T210 T211T211 T212T212 T213T213 T214T214 T215T215 T216T216 T217T217
VGA_SMB_DA2 VGA_SMB_CK2 VGA_AC__BATT
GPU_VID1
T221T221
GPU_VID2 GPU_VID5
GPU_VID4 GPU_VID3 GPU_CLKREQA
JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS
1
JTAG_TDO
T64
T64
TESTEN
PAD
PAD
T218T218
+VREFG_GPU
XTALIN XTALOUT
T219T219 T220T220
VGA_DPLUS VGA_DMINUS
GPIO28 +TSVDD
1
1 1 1 1 1 1
AC10 1 1 1 1 1 1 1 1 1 1
AK10
AM10
AF24
AB13
AD10
AC14 1
AB16
AC16
AM28
AK28
1
AC22 1
AB22
AD17
AC17
DBG_DATA16
L9
DBG_DATA15
AE9
DBG_DATA14
Y11
DBG_DATA13
AE8
DBG_DATA12
AD9
DBG_DATA11 DBG_DATA10
AD7
DBG_DATA9
AC8
DBG_DATA8
AC7
DBG_DATA7
AB9
DBG_DATA6
AB8
DBG_DATA5
AB7
DBG_DATA4
AB4
DBG_DATA3
AB2
DBG_DATA2
Y8
DBG_DATA1
Y7
DBG_DATA0
W6
NC#W6
V6
NC#V6
AC6
NC#AC5
AC5
NC#AC6
AA5
NC#AA5
AA6
NC#AA6
U1
NC#U1
W1
NC#W1
U3
NC#U3
Y6
NC#Y6
AA1
NC#AA1
I2C
I2C
R1
SCL
R3
SDA
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
U6
GPIO_0
U10
GPIO_1
T10
GPIO_2
U8
SMBDATA
U7
SMBCLK
T9
GPIO_5_AC_BATT
T8
GPIO_6
T7
GPIO_7_BLON
P10
GPIO_8_ROMSO
P4
GPIO_9_ROMSI
P2
GPIO_10_ROMSCK
N6
GPIO_11
N5
GPIO_12
N3
GPIO_13
Y9
GPIO_14_HPD2
N1
GPIO_15_PWRCNTL_0
M4
GPIO_16
R6
GPIO_17_THERMAL_INT
W10
GPIO_18
M2
GPIO_19_CTF
P8
GPIO_20_PWRCNTL_1
P7
GPIO_21
N8
GPIO_22_ROMCSB GPIO_29 GPIO_30
N7
CLKREQB
L6
JTAG_TRSTB
L5
JTAG_TDI
L3
JTAG_TCK
L1
JTAG_TMS
K4
JTAG_TDO
K7
TESTEN NC#AF24
GENERICA
W8
GENERICB
W9
GENERICC
W7
GENERICD GENERICE
AJ9
NC#AJ9
AL9
NC#AL9
HPD1 PX_EN
DBG_VREFG
PLL/CLOCK
PLL/CLOCK
XTALIN XTALOUT
XO_IN XO_IN2
SEYMOUR/FutureASIC
SEYMOUR/FutureASIC
T4
DPLUS
T2
DMINUS
R5
GPIO28_FDO TSVDD TSVSS
216-0842024-A11-MAR_FCBGA631
216-0842024-A11-MAR_FCBGA631
THERMAL
THERMAL
DVO
DVO
U?
U?
DPA
DPA
DPB
DPB
DPC
DPC
AVSSN#AK26
AVSSN#AJ25
AVSSN#AG25
DAC1
DAC1
FutureASIC/SEYMOUR/PARK
FutureASIC/SEYMOUR/PARK
GENLK_VSYNC
SWAPLOCKA SWAPLOCKB
DDC/AUX
DDC/AUX
DDCVGACLK
DDCVGADATA
?
?
3
NC#AF2 NC#AF4
NC#AG3 NC#AG5
NC#AH3 NC#AH1
NC#AK3 NC#AK1
NC#AK5
NC#AM3
NC#AK6
NC#AM5
NC#AJ7
NC#AH6
NC#AK8 NC#AL7
NC#V4 NC#U5
NC#W3
NC#V2
NC#Y4
NC#W5
NC#AA3
NC#Y2
NC#J8
HSYNC VSYNC
RSET
AVDD
AVSSQ
VDD1DI VSS1DI
CEC_1
RSVD#AK12 RSVD#AL11 RSVD#AJ11
GENLK_CLK
TS_A
DDC1CLK
DDC1DATA
AUX1P AUX1N
DDC2CLK
DDC2DATA
AUX2P AUX2N
NC#AD20 NC#AC20
NC#AE16 NC#AD16
AF2 AF4
AG3 AG5
AH3 AH1
AK3 AK1
AK5 AM3
AK6 AM5
AJ7 AH6
AK8 AL7
V4 U5
W3 V2
Y4 W5
AA3 Y2
J8
AM26
R
AK26
AL25
G
AJ25
AH24
B
AG25
AH26 AJ27
AD22
AG24 AE22
AE23 AD23
AM12
AK12 AL11 AJ11
AL13 AJ13
AG13 AH12
AC19
PS_0
PS_1
PS_2
PS_3
PS_0
AD19
PS_1
AE17
PS_2
AE20
PS_3
AE19
AE6 AE5
AD2 AD4
AC11 AC13
AD13 AD11
AD20 AC20
AE16 AD16
AC1 AC3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONI CS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONI CS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONI CS, INC.
R322 499_0402_1%DIS@R322 499_0402_1%DIS@
+AVDD
1 2
ZĞƐŝƐƚŽƌŝǀŝĚĞƌ>ŽŽŬƵƉ>ĂďůĞ
ZͺƉĚ;ŽŚŵͿ
ZͺƉƵ;ŽŚŵͿ
Zϱϭϲϵ
Zϱϭϳϰ
ϬϰϬϮϭйƌĞƐŝƐƚŽƌƐĂƌĞĞƋƵŝƌĞĚ
ĂƉĂĐŝƚŽƌŝǀŝĚĞƌ>ŽŽŬƵƉ>ĂďůĞ
ĂƉ;Ŷ&Ϳ ϱϮϬϲ
E
ϴϰϱŬ
ϰϱϯŬ
ϲϵϴŬ
ϰϱϯŬ
ϯϮϰŬ
ϯϰŬ
ϰϳϱŬ
ϲϴϬŶ&
ϴϮŶ&
ϭϬŶ& ϭϬ
E
ϰϳϱŬ
ϮŬ
ϮŬ
ϰϵϵŬ
ϰϵϵŬ
ϱϲϮŬ
ϭϬŬ
E
ŝƚĚ΀ϱϰ΁
ϬϬ
Ϭϭ
ϭϭ
ϭϴϳŵ
1
1
1
C43610U_0603_6.3V6M@C43610U_0603_6.3V6M
C4371U_0402_6.3V4Z@C4371U_0402_6.3V4Z
C4131U_0402_6.3V4Z@C4131U_0402_6.3V4Z
2
2
2
@
@
@
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
4
ŝƚĚ΀ϯϭ΁
ϬϬϬ
ϬϬϭ
ϬϭϬ
Ϭϭϭ
ϭϬϬ
ϭϬϭ
ϭϭϬ
ϭϭϭ
ŽŵƉĂůWE
^ϬϬϬϬϬz:ϴϬ
^ϬϳϲϴϮϯ<ϴϬ
^ϬϳϰϭϬϯ<EϬ
+1.8VS_VGA
L50
@L50
@
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
Compal Secret Data
Compal Secret Data
Compal Secret Data
4
5
W^ͺϬ΀ϯϭ΁сϬϬϭ
W^ͺϬ΀ϱϰ΁сϭϭ
0.68U_0402_X6S
0.68U_0402_X6S
W^ͺϭ΀ϯϭ΁сϬϬϭ
W^ͺϭ΀ϱϰ΁сϭϭ
0.68U_0402_X6S
0.68U_0402_X6S
W^ͺϮ΀ϯϭ΁сϬϬϬ
W^ͺϮ΀ϱϰ΁сϬϬ
0.01U_0402_16V7K
0.01U_0402_16V7K
W^ͺϯ΀ϯϭ΁сϬϬϬ
W^ͺϯ΀ϱϰ΁сϭϭ
DĞŵŽƌLJ/
EX: PS_3=11001 (PU=NC, PD=4.75K, C=NC) for Samsung 1GB PS_3=11010 (PU=8.45K ,PD=2K, C=NC) for Micro 1GB
ZZZ1
ZZZ1
Samsung
Samsung
S1G@
S1G@
X7647239L01
X7647239L01
Deciphered Dat e
Deciphered Dat e
Deciphered Dat e
+1.8VS_VGA
12
DIS@
DIS@ R5165
R5165
8.45K_0402_1%
@
@
C5207
C5207
@
@
8.45K_0402_1%
12
1
DIS@
DIS@ R5166
R5166 2K_0402_1%
2K_0402_1%
2
+1.8VS_VGA
12
@
@ R5167
R5167
8.45K_0402_1%
8.45K_0402_1%
12
1
DIS@
DIS@
@
@
R5168
R5168
4.75K_0402_1%
4.75K_0402_1%
2
+1.8VS_VGA
12
@
@ R5175
R5175
4.75K_0402_1%
4.75K_0402_1%
12
1
DIS@
DIS@ R5164
R5164
4.75K_0402_1%
4.75K_0402_1%
2
+1.8VS_VGA
12
X76@
X76@ R5174
R5174
8.45K_0402_1%
8.45K_0402_1%
12
1
DIS@
DIS@ R5169
R5169 2K_0402_1%
2K_0402_1%
2
PS_0
C5208
C5208
PS_1
PS_2
C5203
C5203
PS_3
@
@ C5206
C5206
0.68U_0402_X6S
0.68U_0402_X6S
DĞŵŽƌLJdLJƉĞ
ŐZϯͲϮϭϯϯ
ϭ
^ϬϬϬϬϲϴhϬϬͲ^/ϯϭϮϴDyϭϲ<ϰtϮ'ϭϲϰϲͲϭ&'ϵϲW
ŐZϯͲϮϬϬϬ
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ZZZ2
ZZZ2
Micro
Micro
M1G@
M1G@ X7647239L02
X7647239L02
^ƚƌĂƉEĂŵĞ
W^ͺϬ΀ϭ΁ZKDͺKE&/'΀Ϭ΁
W^ͺϬ΀Ϯ΁ZKDͺKE&/'΀ϭ΁
W^ͺϬ΀ϯ΁ZKDͺKE&/'΀Ϯ΁
W^ͺϬ΀ϰ΁E
W^ͺϬ΀ϱ΁hͺWKZdͺKEEͺW/E^dZW΀Ϭ΁
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W^ͺϭ΀ϯ΁E
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^ƚƌĂƉEĂŵĞ
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W^ͺϮ΀Ϯ΁E
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Title
Title
Title
MARS_MSIC
MARS_MSIC
MARS_MSIC
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-9611P
LA-9611P
LA-9611P
5
Ϯ'ďyϰ ;Ϯϱϲ'yϰͿ
Ϯ'ďyϰ ;Ϯϱϲ'yϰͿ
of
of
of
24 53W ednesday, February 27, 2013
24 53W ednesday, February 27, 2013
24 53W ednesday, February 27, 2013
0.4
0.4
0.4
1
2
3
4
5
нϯs^dKнϯs^ͺs'
12
R297
R297 470K_0402_1%
470K_0402_1%
DIS@
A A
1 2
SUSP#[10,38,39,44,46,47]
DGPU_PWR_EN[17,47,51]
R1477 0_0402_5%@R1477 0_0402_5%@
1 2
R1478 0_0402_5%@R1478 0_0402_5%@
DIS@
R1480
100K_0402_5%
100K_0402_5%
12
@R1480
@
DIS@
DGPU_PWR_EN#
13
D
D
2
Q1406
Q1406 2N7002K_SOT23-3
2N7002K_SOT23-3
G
G
DIS@
DIS@
S
S
нϭϴs^dKнϭϴs^ͺs'
нϭϱsdKнϭϱs^ͺs'
B B
110K
+1.8VS
DIS@
DIS@
DGPU_PWR_EN
C C
D D
1 2
R1482 110K_0402_1%
R1482 110K_0402_1%
C1524
C1524
1
DIS@
DIS@
2
12
+5VS
R143
R143 0_0402_5%
0_0402_5% @
@
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.5V
U2302
U2302
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
DIS@
DIS@
R1475
R1475 DIS@
DIS@
1 2
10K_0402_5%
10K_0402_5%
VOUT1 VOUT1
VOUT2 VOUT2
GPAD
CT1
GND
CT2
+3VS+5VALW +3VS_VGA
J1401
@J1401
@
2
112
JUMP_43X79
JUMP_43X79
Q1405
DIS@
Q1405
DIS@
AO3413_SOT23-3
AO3413_SOT23-3
D
S
D
S
13
G
G
2
C1515
0.1U_0402_10V6K
0.1U_0402_10V6K
DIS@C1515
DIS@
14 13
12
11
10
9 8
15
1
2
2N7002K_SOT23-3
2N7002K_SOT23-3
1.8VSVGA
1.5VSVGA
Q1407
Q1407
@
@
J508
J508
2
JUMP_43X79@
JUMP_43X79@
J509
J509
2
JUMP_43X79@
JUMP_43X79@
12
13
D
D
S
S
112
112
C1514
DIS@C1514
DIS@
R1533
R1533 470_0603_5%
470_0603_5% @
@
2
G
G
C1521
@
+1.8VS_VGA
C1522
@
+1.5VS_VGA
C1516
DIS@C1516
DIS@
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
R1479
1 2
10K_0402_5%
10K_0402_5%
0.1U_0402_10V6K@C1521
0.1U_0402_10V6K
1
2
10U_0603_6.3V6M@C1522
10U_0603_6.3V6M
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
C1632
DIS@C1632
DIS@
C1520
DIS@C1520
DIS@
C1523
DIS@C1523
DIS@
1
2
@R1479
@
1
2
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
C1633
DIS@C1633
DIS@
C1628
10U_0603_6.3V6M
10U_0603_6.3V6M
DIS@C1628
DIS@
DGPU_PWR_EN#
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
+1.8VS_VGA
@
@
1 2
R319 0_0603_5%
R319 0_0603_5%
+0.95VS_VGA
@
@
1 2
R320 0_0603_5%
R320 0_0603_5%
ϯϳϬŵ;,D/Ϳ ϭϴϴŵ;ŝƐƉůĂLJWŽƌƚͿ
+DP_VDDR
1
1
C4461U_0402_6.3V4Z@C4461U_0402_6.3V4Z
C4470.1U_0402_10V6K@C4470.1U_0402_10V6K
2
2
@
@
ϮϴϬŵ
+DP_VDDC
1
1
C4501U_0402_6.3V4Z@C4501U_0402_6.3V4Z
C4510.1U_0402_10V6K@C4510.1U_0402_10V6K
2
2
@
@
EŽhƐĞ'WhŝƐƉůĂLJWŽƌƚŽƵƚƉƵĚ
DIS@
DIS@ U666G
U666G
AG15
DP_VDDR#AG15
AG16
DP_VDDR#AG16
AF16
DP_VDDR#AF16
AG17
DP_VDDR#AG17
AG18
DP_VDDR#AG18
AG19
DP_VDDR#AG19
AF14
DP_VDDR#AF14
AG20
DP_VDDC#AG20
AG21
DP_VDDC#AG21
AF22
DP_VDDC#AF22
AG22
DP_VDDC#AG22
AD14
DP_VDDC#AD14
AG14
DP_VSSR
AH14
DP_VSSR
AM14
DP_VSSR
AM16
DP_VSSR
AM18
DP_VSSR
AF23
DP_VSSR
AG23
DP_VSSR
AM20
DP_VSSR
AM22
DP_VSSR
AM24
DP_VSSR
AF19
DP_VSSR
AF20
DP_VSSR
AE14
DP_VSSR
AF17
DPAB_CALR
216-0842024-A11-MAR_FCBGA631
216-0842024-A11-MAR_FCBGA631
DP POWER
DP POWER
U?
U?
?
?
NC/DP POWER
NC/DP POWER
NC#AE11 NC#AF11 NC#AE13 NC#AF13
NC#AG8
NC#AG10
NC#AF6 NC#AF7 NC#AF8 NC#AF9
NC#AE1 NC#AE3 NC#AG1 NC#AG6 NC#AH5
NC#AF10
NC#AG9 NC#AH8 NC#AM6 NC#AM8 NC#AG7
NC#AG11
NC#AE10
AE11 AF11 AE13 AF13 AG8 AG10
AF6 AF7 AF8 AF9
AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8 AM6 AM8 AG7 AG11
AE10
DIS@
DIS@ U666E
U666E
AA27
GND
AB24
GND
AB32
GND
AC24
GND
AC26
GND
AC27
GND
AD25
GND
AD32
GND
AE27
GND
AF32
GND
AG27
GND
AH32
GND
K28
GND
K32
GND
L27
GND
M32
GND
N25
GND
N27
GND
P25
GND
P32
GND
R27
GND
T25
GND
T32
GND
U25
GND
U27
GND
V32
GND
W25
GND
W26
GND
W27
GND
Y25
GND
Y32
GND
M6
GND
N13
GND
N16
GND
N18
GND
N21
GND
P6
GND
P9
GND
R12
GND
R15
GND
R17
GND
R20
GND
T13
GND
T16
GND
T18
GND
T21
GND
T6
GND
U15
GND
U17
GND
U20
GND
U9
GND
V13
GND
V16
GND
V18
GND
Y10
GND
Y15
GND
Y17
GND
Y20
GND
R11
GND
T11
GND
AA11
GND
M12
GND
N11
GND
V11
GND
216-0842024-A11-MAR_FCBGA631
216-0842024-A11-MAR_FCBGA631
U?
U?
A3
GND
A30
GND
AA13
GND
AA16
GND
AB10
GND
AB15
GND
AB6
GND
AC9
GND
AD6
GND
AD8
GND
AE7
GND
AG12
GND
AH10
GND
AH28
GND
B10
GND
B12
GND
B14
GND
B16
GND
B18
GND
B20
GND
B22
GND
B24
GND
B26
GND
B6
GND
B8
GND
C1
GND
C32
GND
E28
GND
F10
GND
F12
GND
F14
GND
F16
GND
F18
GND
F2
GND
F20
GND
F22
GND
F24
GND
F26
GND
F6
GND
VSS_MECH VSS_MECH VSS_MECH
F8
GND
G10
GND
G27
GND
G31
GND
G8
GND
H14
GND
H17
GND
H2
GND
H20
GND
H6
GND
J27
GND
J31
GND
K11
GND
K2
GND
K22
GND
K6
GND
A32 AM1 AM32
GND
GND
?
?
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
MARS_Power/GND
MARS_Power/GND
MARS_Power/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
25 53Tuesday, February 26, 2013
25 53Tuesday, February 26, 2013
25 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
A A
s
s/
d
ϱ;ϭΛͿ ϭϬ;ϮΛͿ Ϭ
ϯϱ
ϭϯϬ
ϭϬƵ& ϭƵ& ϬϭƵ&нϬϵϱs^ͺs'
W/ͺs
/&ͺs
^W>>ͺs
B B
sZϭ
Ϯϱ
Ϯ;ϭΛͿ ϱ;ϭΛͿ Ϭ
ϭϰ
ϭϬϬŵ
ϭϬƵ& ϭƵ& ϬϭƵ&нϭϱs^ͺs'
ϯϱϱ
ϭϱ
ϭϬƵ&нϭϴs^ͺs' ϬϭƵ&ϭƵ&
W/ͺWs
DW>>ͺWs
^W>>ͺWs
sZϰ
sͺd
ϭϬϬŵ
ϭϯϬŵ
ϳϱŵ
;ϯϬϬŵͿ
ϭϯŵ
ϭϭϭ
нd^s ϭϯŵ ϭ ϭϭ
C C
нWͺsZ
нWͺs
sZϯ
Ϯϱŵ
Ϭ Ϯ;ϭΛͿ ϭ
ϬϭƵ&ϭƵ&ϭϬƵ&нs'ͺKZ
ϬϬϬ
ϭϭϭ
+1.8VS_VGA
ϭϭϭ
ϭϭϭ
ϭϭϭ
ϬϬϬ
+1.8VS_VGA
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
ϬϬϬ
ϬϬϬ
ϬϭƵ&ϭƵ&ϭϬƵ&нϯs^ͺs'
L56
DIS@L56
DIS@
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
L51
DIS@L51
DIS@
1 2
DIS@
DIS@ U666D
+1.5VS_VGA
1
C36510U_0603_6.3V6M
C36510U_0603_6.3V6M
2
DIS@
DIS@
1
1
C36710U_0603_6.3V6M
C36710U_0603_6.3V6M
2
1
C37510U_0603_6.3V6M
C37510U_0603_6.3V6M
2
DIS@
DIS@
1
C3701U_0402_6.3V4Z
C3701U_0402_6.3V4Z
C3711U_0402_6.3V4Z@C3711U_0402_6.3V4Z
2
2
DIS@
DIS@
@
DIS@
DIS@
1
1
1
C3741U_0402_6.3V4Z
C3741U_0402_6.3V4Z
C3721U_0402_6.3V4Z
C3721U_0402_6.3V4Z
C3731U_0402_6.3V4Z
C3731U_0402_6.3V4Z
2
2
2
DIS@
DIS@
DIS@
DIS@
1
1
C3900.1U_0402_10V6K
C3900.1U_0402_10V6K
C3890.1U_0402_10V6K
C3890.1U_0402_10V6K
2
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
ϭϱ
1
1
1
C3910.1U_0402_10V6K
C3910.1U_0402_10V6K
C3920.1U_0402_10V6K@C3920.1U_0402_10V6K
C3810.1U_0402_10V6K
C3810.1U_0402_10V6K
2
2
2
@
DIS@
DIS@
DIS@
DIS@
ϭϯŵ
+VDD_CT
1
1
1
C40410U_0603_6.3V6M
C40410U_0603_6.3V6M
C4220.1U_0402_10V6K
C4220.1U_0402_10V6K
C4051U_0402_6.3V4Z
C4051U_0402_6.3V4Z
2
1
C40610U_0603_6.3V6M
C40610U_0603_6.3V6M
2
+3VS_VGA
2
2
DIS@
DIS@
DIS@
DIS@
1
1
C4330.1U_0402_10V6K
C4330.1U_0402_10V6K
C4071U_0402_6.3V4Z
C4071U_0402_6.3V4Z
2
2
DIS@
DIS@
DIS@
DIS@
L24 0_0402_5%@L24 0_0402_5%@
DIS@
DIS@
ϬŽŚŵWE
+1.8VS_VGA
DIS@
DIS@
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
1 2
L52
DIS@L52
DIS@
1 2
1
1
1
C4101U_0402_6.3V4Z
C4101U_0402_6.3V4Z
C4290.1U_0402_10V6K
C4290.1U_0402_10V6K
C4281U_0402_6.3V4Z@C4281U_0402_6.3V4Z
+1.8VS_VGA
L25
2
ϬŽŚŵWE
DIS@
DIS@
L53
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
DIS@L53
DIS@
2
2
@
DIS@
DIS@
1
1
1
C4091U_0402_6.3V4Z
C4091U_0402_6.3V4Z
C4340.1U_0402_10V6K
C4340.1U_0402_10V6K
C40810U_0603_6.3V6M
C40810U_0603_6.3V6M
2
+0.95VS_VGA
2
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
Ϯϱŵ
+VDDR3
ϯϬϬŵ
@L25
@
+VDDR4
ϭϯϬŵ
+MPLL_PVDD
ϳϱŵ
+SPLL_PVDD
ϭϬϬŵ
+SPLL_VDDC
1
1
1
C41110U_0603_6.3V6M
C41110U_0603_6.3V6M
C4121U_0402_6.3V4Z
C4121U_0402_6.3V4Z
C4350.1U_0402_10V6K
C4350.1U_0402_10V6K
2
2
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
U666D
MEM I/O
MEM I/O
H13
VDDR1
H16
VDDR1
H19
VDDR1
J10
VDDR1
J23
VDDR1
J24
VDDR1
J9
VDDR1
K10
VDDR1
K23
VDDR1
K24
VDDR1
K9
VDDR1
L11
VDDR1
L12
VDDR1
L13
VDDR1
L20
VDDR1
L21
VDDR1
L22
VDDR1
LEVEL
LEVEL TRANSLATION
TRANSLATION
AA20
VDD_CT
AA21
VDD_CT
AB20
VDD_CT
AB21
VDD_CT
AA17
VDDR3
AA18
VDDR3
AB17
VDDR3
AB18
VDDR3
V12
VDDR4
Y12
VDDR4
U12
VDDR4
PLL
PLL
L8
MPLL_PVDD
H7
SPLL_PVDD
H8
SPLL_VDDC
J7
SPLL_PVSS
216-0842024-A11-MAR_FCBGA631
216-0842024-A11-MAR_FCBGA631
I/O
I/O
U?
U?
PCIE
PCIE
PCIE_PVDD
NC#AB23 NC#AC23 NC#AD24 NC#AE24 NC#AE25 NC#AE26 NC#AF25 NC#AG26
PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC
VDDC
CORE
CORE
VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC
POWER
POWER
VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC
BIF_VDDC BIF_VDDC
ISOLATED
ISOLATED CORE I/O
CORE I/O
VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI
?
?
AM30
AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26
L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22
AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11
R21 U21
M13 M15 M16 M17 M18 M20 M21 N20
ϭϬϬŵ
+PCIE_PVDD
1
C38010U_0603_6.3V6M
C38010U_0603_6.3V6M
2
Ϯϱ
1
C38410U_0603_6.3V6M
C38410U_0603_6.3V6M
2
d
1
C42310U_0603_6.3V6M
C42310U_0603_6.3V6M
2
ϭϰ
+BIF_VDDC
ϯϱ;ZϯͿ
1
C46610U_0603_6.3V6M
C46610U_0603_6.3V6M
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1
C3871U_0402_6.3V4Z
C3871U_0402_6.3V4Z
2
DIS@
DIS@
1
C38610U_0603_6.3V6M@C38610U_0603_6.3V6M
2
@
1
1
C42510U_0603_6.3V6M
C42510U_0603_6.3V6M
C42410U_0603_6.3V6M
C42410U_0603_6.3V6M
2
2
DIS@
DIS@
1 2
R398 0_0805_5%@R398 0_0805_5%@
1
C4651U_0402_6.3V4Z
C4651U_0402_6.3V4Z
2
DIS@
DIS@
+1.8VS_VGA
1
C3981U_0402_6.3V4Z
C3981U_0402_6.3V4Z
2
DIS@
DIS@
+VGA_CORE
1
C4601U_0402_6.3V4Z
C4601U_0402_6.3V4Z
2
1
C3940.1U_0402_10V6K
C3940.1U_0402_10V6K
2
DIS@
DIS@
+0.95VS_VGA
1
C3831U_0402_6.3V4Z
C3831U_0402_6.3V4Z
2
DIS@
DIS@
1
C4311U_0402_6.3V4Z
C4311U_0402_6.3V4Z
2
DIS@
DIS@
+0.95VS_VGA
1
1
C3881U_0402_6.3V4Z@C3881U_0402_6.3V4Z
C4031U_0402_6.3V4Z
C4031U_0402_6.3V4Z
2
2
@
DIS@
DIS@
+VGA_CORE
1
C4321U_0402_6.3V4Z
C4321U_0402_6.3V4Z
2
DIS@
DIS@
1
C4191U_0402_6.3V4Z
C4191U_0402_6.3V4Z
C4181U_0402_6.3V4Z
C4181U_0402_6.3V4Z
C4161U_0402_6.3V4Z
C4161U_0402_6.3V4Z
C4151U_0402_6.3V4Z
C4151U_0402_6.3V4Z
C4171U_0402_6.3V4Z
C4171U_0402_6.3V4Z
2
2
2
2
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1
1
1
1
1
1
1
C4481U_0402_6.3V4Z@C4481U_0402_6.3V4Z
C4491U_0402_6.3V4Z@C4491U_0402_6.3V4Z
C4201U_0402_6.3V4Z
C4201U_0402_6.3V4Z
2
2
2
@
@
DIS@
DIS@
1
C3991U_0402_6.3V4Z
C3991U_0402_6.3V4Z
2
DIS@
DIS@
DIS@
DIS@
1
C42610U_0603_6.3V6M
C42610U_0603_6.3V6M
2
DIS@
DIS@
1
C4611U_0402_6.3V4Z
C4611U_0402_6.3V4Z
2
DIS@
DIS@
DIS@
DIS@
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
MARS_Power
MARS_Power
MARS_Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
26 53Tuesday, February 26, 2013
26 53Tuesday, February 26, 2013
26 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
DIS@
DIS@ C469
C469
M_DA[63..0]
M_MA[15..0]
M_DQM[7..0]
M_DQS[7..0]
M_DQS#[7..0]
40.2_0402_1%
40.2_0402_1%
100_0402_1%
100_0402_1%
DIS@
DIS@ R455
R455 10_0402_1%
10_0402_1%
1
2
+1.5VS_VGA+1.5VS_VGA
12
DIS@
DIS@ R365
R365
12
DIS@
DIS@ R457
R457
12
DIS@
DIS@ R5161
R5161
5.1K_0402_1%
5.1K_0402_1%
+MVREFSA
1
DIS@
DIS@ C514
C514 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
DRAM_RST
12
1
DIS@
DIS@ C5186
C5186 68P_0402_50V8J
68P_0402_50V8J
2
R5162 120_0402_1%DIS@R5162 120_0402_1%DIS @
1 2
R460 51.1_0402_1%@R460 51.1_0402_1%@
1 2
R373 51.1_0402_1%@R373 51.1_0402_1%@
ZŽƵƚĞϱϬŽŚŵƐƐŝŶŐůĞͲĞŶĚĞĚϭϬϬŽŚŵĚŝĨĨĂŶĚŬĞĞƉƐŚŽƌƚ ĚĞďƵŐŽŶůLJĨŽƌĐůŽĐŬŽďƐĞƌǀĂƚŝŽŶŝĨŶŽƚŶĞĞĚE/
C515 0.1U_0402_10V6K@C515 0.1U_0402_10V6K@ C517
1 2
1 2 1 2
@C517
@
M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63
+MVREFDA +MVREFSA
DRAM_RST
0.1U_0402_10V6K
0.1U_0402_10V6K
DIS@
DIS@ U666C
U666C
K27
DQA0_0
J29
DQA0_1
H30
DQA0_2
H32
DQA0_3
G29
DQA0_4
F28
DQA0_5
F32
DQA0_6
F30
DQA0_7
C30
DQA0_8
F27
DQA0_9
A28
DQA0_10
C28
DQA0_11
E27
DQA0_12
G26
DQA0_13
D26
DQA0_14
F25
DQA0_15
A25
DQA0_16
C25
DQA0_17
E25
DQA0_18
D24
DQA0_19
E23
DQA0_20
F23
DQA0_21
D22
DQA0_22
F21
DQA0_23
E21
DQA0_24
D20
DQA0_25
F19
DQA0_26
A19
DQA0_27
D18
DQA0_28
F17
DQA0_29
A17
DQA0_30
C17
DQA0_31
E17
DQA1_0
D16
DQA1_1
F15
DQA1_2
A15
DQA1_3
D14
DQA1_4
F13
DQA1_5
A13
DQA1_6
C13
DQA1_7
E11
DQA1_8
A11
DQA1_9
C11
DQA1_10
F11
DQA1_11
A9
DQA1_12
C9
DQA1_13
F9
DQA1_14
D8
DQA1_15
E7
DQA1_16
A7
DQA1_17
C7
DQA1_18
F7
DQA1_19
A5
DQA1_20
E5
DQA1_21
C3
DQA1_22
E1
DQA1_23
G7
DQA1_24
G6
DQA1_25
G1
DQA1_26
G3
DQA1_27
J6
DQA1_28
J1
DQA1_29
J3
DQA1_30
J5
DQA1_31
K26
MVREFDA
J26
MVREFSA
J25
NC#J25
K25
MEM_CALRP 0
L10
DRAM_RST
K8
CLKTESTA
L7
CLKTESTB
216-0842024-A11-MAR_FCBGA631
216-0842024-A11-MAR_FCBGA631
U?
U?
GDDR5/DDR3GDDR5/DDR3
GDDR5/DDR3GDDR5/DDR3
MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6
MAA0_7/MAA_7 MAA0_8/MAA_13 MAA0_9/MAA_15
MAA1_0/MAA_8
MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12
MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1
MAA1_8/MAA_14
MAA1_9/RSVD
WCKA0_0/DQMA0_0
WCKA0B_0/DQMA0_1
WCKA0_1/DQMA0_2
WCKA0B_1/DQMA0_3
WCKA1_0/DQMA1_0
MEMORY INTERFACE
MEMORY INTERFACE
WCKA1B_0/DQMA1_1
WCKA1_1/DQMA1_2
WCKA1B_1/DQMA1_3
EDCA0_0/QSA0_0 EDCA0_1/QSA0_1 EDCA0_2/QSA0_2 EDCA0_3/QSA0_3 EDCA1_0/QSA1_0 EDCA1_1/QSA1_1 EDCA1_2/QSA1_2 EDCA1_3/QSA1_3
DDBIA0_0/QSA0_0B DDBIA0_1/QSA0_1B DDBIA0_2/QSA0_2B DDBIA0_3/QSA0_3B DDBIA1_0/QSA1_0B DDBIA1_1/QSA1_1B DDBIA1_2/QSA1_2B DDBIA1_3/QSA1_3B
ADBIA0/ODTA0
ADBIA1/ODTA1
?
?
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B RASA1B
CASA0B CASA1B
CSA0B_0 CSA0B_1
CSA1B_0 CSA1B_1
CKEA0 CKEA1
WEA0B WEA1B
K17
M_MA0
J20
M_MA1
H23
M_MA2
G23
M_MA3
G24
M_MA4
H24
M_MA5
J19
M_MA6
K19
M_MA7
G20
M_MA13
L17
M_MA15
J14
M_MA8
K14
M_MA9
J11
M_MA10
J13
M_MA11
H11
M_MA12
G11
M_BA2
J16
M_BA0
L15
M_BA1
G14
M_MA14
L16
E32
M_DQM0
E30
M_DQM1
A21
M_DQM2
C21
M_DQM3
E13
M_DQM4
D12
M_DQM5
E3
M_DQM6
F4
M_DQM7
H28
M_DQS0
C27
M_DQS1
A23
M_DQS2
E19
M_DQS3
E15
M_DQS4
D10
M_DQS5
D6
M_DQS6
G5
M_DQS7
H27
M_DQS#0
A27
M_DQS#1
C23
M_DQS#2
C19
M_DQS#3
C15
M_DQS#4
E9
M_DQS#5
C5
M_DQS#6
H4
M_DQS#7
L18
VRAM_ODT0
K16
VRAM_ODT1
H26
M_CLK0
H25
M_CLK#0
G9
M_CLK1
H9
M_CLK#1
G22
M_RAS#0
G17
M_RAS#1
G19
M_CAS#0
G16
M_CAS#1
H22
M_CS#0
J22
G13
M_CS#1
K13
K20
M_CKE0
J17
M_CKE1
G25
M_WE#0
H10
M_WE#1
M_BA2 [28,29] M_BA0 [28,29] M_BA1 [28,29]
VRAM_ODT0 [28] VRAM_ODT1 [29]
M_CLK0 [28] M_CLK#0 [28]
M_CLK1 [29] M_CLK#1 [29]
M_RAS#0 [28] M_RAS#1 [29]
M_CAS#0 [28] M_CAS#1 [29]
M_CS#0 [28]
M_CS#1 [29]
M_CKE0 [28] M_CKE1 [29]
M_WE#0 [28] M_WE#1 [29]
M_DA[63..0][28,29]
M_MA[15..0][28,29]
M_DQM[7..0][28,29]
A A
40.2_0402_1%
40.2_0402_1%
100_0402_1%
100_0402_1%
B B
DRAM_RST#[28,29]
C C
M_DQS[7..0][28,29]
M_DQS#[7..0][28,29]
12
DIS@
DIS@ R363
R363
+MVREFDA
12
1
DIS@
DIS@
DIS@
DIS@
C467
C467
R364
R364
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
DIS@
DIS@ R5160
R5160
49.9_0402_1%
49.9_0402_1%
1 2
120P_0402_50V8J
120P_0402_50V8J
WůĂĐĞĐůŽƐĞƚŽ'Wh;ǁŝƚŚŝŶϮϱŵŵͿ ĂŶĚƉůĂĐĞĐŽŵƉŽŶŵĞŶƚĐůŽƐĞƚŽĞĂĐŚŽƚŚĞƌ ;ĚĂŝƐLJĐŚĂŝŶ㕡⺷崘⇘⚃柮sZDͿ
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
MARS_MEM
MARS_MEM
MARS_MEM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
27 53Tuesday, February 26, 2013
27 53Tuesday, February 26, 2013
27 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
Memory Partition A - Lower 32 bits
M_DA[63..0][27,29]
M_MA[15..0][27,29]
M_DQM[7..0][27,29]
M_DQS[7..0][27,29]
M_DQS#[7..0][27,29]
A A
B B
C C
R5171
R5171
40.2_0402_1%
40.2_0402_1% DIS@
DIS@
12
1
2
M_CLK0 M_CLK#0
12
R5170
R5170
40.2_0402_1%
40.2_0402_1% DIS@
DIS@
DIS@
DIS@ C506
C506
0.01U_0402_16V7K
0.01U_0402_16V7K
M_DA[63..0]
M_MA[15..0]
M_DQM[7..0]
M_DQS[7..0]
M_DQS#[7..0]
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
+1.5VS_VGA
DIS@
DIS@ R452
R452
DIS@
DIS@ R453
R453
12
12
+FBA_VREF0
1
DIS@
DIS@ C472
C472
0.1U_0402_10V6K
0.1U_0402_10V6K
2
M_BA0[27,29] M_BA1[27,29] M_BA2[27,29]
M_CLK0[27] M_CLK#0[27] M_CKE0[27]
VRAM_ODT0[27] M_CS#0[27] M_RAS#0[27] M_CAS#0[27] M_WE#0[27]
DRAM_RST#[27,29]
243_0402_1%
243_0402_1%
1
C49110U_0603_6.3V6M
C49110U_0603_6.3V6M
2
DIS@
DIS@
+1.5VS_VGA
12
DIS@
DIS@ R463
R463
4.99K_0402_1%
U1406
U1406
M8
VREFCA
H1
VREFDQ
N3
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15
M_BA0 M_BA1 M_BA2
M_CLK0 M_CLK#0 M_CKE0
VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0
M_DQS2 M_DQS0
M_DQM2 M_DQM0
M_DQS#2 M_DQS#0
12
DIS@
DIS@ R454
R454
1
1
C5111U_0402_6.3V4Z
C5111U_0402_6.3V4Z
C5121U_0402_6.3V4Z
C5121U_0402_6.3V4Z
2
2
DIS@
DIS@
DIS@
DIS@
1
C5191U_0402_6.3V4Z@C5191U_0402_6.3V4Z
2
@
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4W1G1646E-HC12_FBGA96
K4W1G1646E-HC12_FBGA96 X76@
X76@
1
1
C5101U_0402_6.3V4Z
C5101U_0402_6.3V4Z
C5211U_0402_6.3V4Z
C5211U_0402_6.3V4Z
2
2
DIS@
DIS@
DIS@
DIS@
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
1
C5321U_0402_6.3V4Z
C5321U_0402_6.3V4Z
2
DIS@
DIS@
E3
M_DA17
DQL0
F7
M_DA23
DQL1
F2
M_DA21
DQL2
F8
M_DA22
DQL3
H3
M_DA18
DQL4
H8
M_DA19
DQL5
G2
M_DA16
DQL6
H7
M_DA20
DQL7
D7
M_DA3
DQU0
C3
M_DA2
DQU1
C8
M_DA5
DQU2
C2
M_DA1
DQU3
A7
M_DA7
DQU4
A2
M_DA0
DQU5
B8
M_DA6
DQU6
A3
M_DA4
DQU7
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
hϭϰϬϲƐŝĚĞ
1
1
1
C4800.1U_0402_10V6K
C4800.1U_0402_10V6K
C4810.1U_0402_10V6K
C4810.1U_0402_10V6K
C5201U_0402_6.3V4Z@C5201U_0402_6.3V4Z
2
2
2
@
DIS@
DIS@
+1.5VS_VGA
B2 D9 G7 K2 K8 N1 N9 R1 R9
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
+1.5VS_VGA
1
1
C4820.1U_0402_10V6K
C4820.1U_0402_10V6K
2
DIS@
DIS@
DIS@
DIS@
1
1
1
C4850.1U_0402_10V6K
C4850.1U_0402_10V6K
C5310.1U_0402_10V6K
C5310.1U_0402_10V6K
C4860.1U_0402_10V6K@C4860.1U_0402_10V6K
C4830.1U_0402_10V6K@C4830.1U_0402_10V6K
2
2
2
2
@
@
DIS@
DIS@
DIS@
DIS@
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
DIS@
DIS@ R464
R464
12
+FBA_VREF1
1
DIS@
DIS@ C540
C540
0.1U_0402_10V6K
0.1U_0402_10V6K
2
243_0402_1%
243_0402_1%
1
C49010U_0603_6.3V6M
C49010U_0603_6.3V6M
2
U1407
U1407
M8
VREFCA
H1
VREFDQ
N3
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15
M_BA0 M_BA1 M_BA2
M_CLK0 M_CLK#0 M_CKE0
VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0
M_DQS3 M_DQS1
M_DQM3 M_DQM1
M_DQS#3 M_DQS#1
DRAM_RST#
12
DIS@
DIS@ R456
R456
1
1
C4961U_0402_6.3V4Z
C4961U_0402_6.3V4Z
C4971U_0402_6.3V4Z
C4971U_0402_6.3V4Z
2
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1
C4991U_0402_6.3V4Z
C4991U_0402_6.3V4Z
C4981U_0402_6.3V4Z@C4981U_0402_6.3V4Z
2
@
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
K4W1G1646E-HC12_FBGA96 X76@
X76@
1
1
1
C5181U_0402_6.3V4Z
C5181U_0402_6.3V4Z
C5331U_0402_6.3V4Z
C5331U_0402_6.3V4Z
2
2
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
E3
M_DA30
DQL0
F7
M_DA27
DQL1
F2
M_DA31
DQL2
F8
M_DA24
DQL3
H3
M_DA29
DQL4
H8
M_DA26
DQL5
G2
M_DA28
DQL6
H7
M_DA25
DQL7
D7
M_DA8
DQU0
C3
M_DA14
DQU1
C8
M_DA9
DQU2
C2
M_DA12
DQU3
A7
M_DA10
DQU4
A2
M_DA15
DQU5
B8
M_DA11
DQU6
A3
M_DA13
DQU7
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
1
1
C4740.1U_0402_10V6K
C4740.1U_0402_10V6K
C5161U_0402_6.3V4Z@C5161U_0402_6.3V4Z
2
2
@
DIS@
DIS@
B2 D9 G7 K2 K8 N1 N9 R1 R9
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
hϭϰϬϳƐŝĚĞ
1
1
C4760.1U_0402_10V6K
C4760.1U_0402_10V6K
C4750.1U_0402_10V6K
C4750.1U_0402_10V6K
2
2
DIS@
DIS@
DIS@
DIS@
+1.5VS_VGA
+1.5VS_VGA+1.5VS_VGA
1
C4770.1U_0402_10V6K
C4770.1U_0402_10V6K
2
DIS@
DIS@
+1.5VS_VGA
1
1
1
C4790.1U_0402_10V6K@C4790.1U_0402_10V6K
C5340.1U_0402_10V6K@C5340.1U_0402_10V6K
C4780.1U_0402_10V6K
C4780.1U_0402_10V6K
2
2
2
@
@
DIS@
DIS@
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
MARS_VRAM A Lower
MARS_VRAM A Lower
MARS_VRAM A Lower
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
28 53Tuesday, February 26, 2013
28 53Tuesday, February 26, 2013
28 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
Memory Partition A - Upper 32 bits
3
4
5
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
+1.5VS_VGA
DIS@
DIS@ R461
R461
DIS@
DIS@ R462
R462
12
12
1
DIS@
DIS@ C539
C539
0.1U_0402_10V6K
0.1U_0402_10V6K
2
243_0402_1%
243_0402_1%
DIS@
DIS@ R444
R444
+FBA_VREF3+FBA_VREF3
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15
M_BA0 M_BA1 M_BA2
M_CLK1 M_CLK#1 M_CKE1
VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1
M_DQS6 M_DQS7
M_DQM6 M_DQM7
M_DQS#6 M_DQS#7
DRAM_RST#
12
U1409
U1409
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
K4W1G1646E-HC12_FBGA96 X76@
X76@
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
E3
M_DA49
F7
M_DA53
F2
M_DA51
F8
M_DA54
H3
M_DA50
H8
M_DA55
G2
M_DA48
H7
M_DA52
D7
M_DA60
C3
M_DA63
C8
M_DA57
C2
M_DA56
A7
M_DA62
A2
M_DA58
B8
M_DA61
A3
M_DA59
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1 B9 D1 D8 E2 E8 F9 G1 G9
+1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA
12
DIS@
DIS@ R458
R458
4.99K_0402_1%
A A
B B
40.2_0402_1%
40.2_0402_1%
C C
R5173
R5173
DIS@
DIS@
M_DA[63..0][27,28]
M_MA[15..0][27,28]
M_DQM[7..0][27,28]
M_DQS[7..0][27,28]
M_DQS#[7..0][27,28]
12
12
R5172
R5172
40.2_0402_1%
40.2_0402_1% DIS@
DIS@
1
DIS@
DIS@ C507
C507
0.01U_0402_16V7K
0.01U_0402_16V7K
2
M_CLK1 M_CLK#1
M_DA[63..0]
M_MA[15..0]
M_DQM[7..0]
M_DQS[7..0]
M_DQS#[7..0]
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
DIS@
DIS@ R459
R459
12
1
DIS@
DIS@ C473
C473
0.1U_0402_10V6K
0.1U_0402_10V6K
2
M_BA0[27,28] M_BA1[27,28] M_BA2[27,28]
M_CLK1[27] M_CLK#1[27] M_CKE1[27]
VRAM_ODT1[27] M_CS#1[27] M_RAS#1[27] M_CAS#1[27] M_WE#1[27]
DRAM_RST#[27,28]
243_0402_1%
243_0402_1%
DIS@
DIS@ R410
R410
+FBA_VREF2
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13 M_MA14 M_MA15
M_BA0 M_BA1 M_BA2
M_CLK1 M_CLK#1 M_CKE1
VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1
M_DQS4 M_DQS5
M_DQM4 M_DQM5
M_DQS#4 M_DQS#5
DRAM_RST#
12
U1408
U1408
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
K4W1G1646E-HC12_FBGA96 X76@
X76@
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
E3
M_DA38
F7
M_DA36
F2
M_DA37
F8
M_DA35
H3
M_DA39
H8
M_DA32
G2
M_DA34
H7
M_DA33
D7
M_DA41
C3
M_DA44
C8
M_DA43
C2
M_DA45
A7
M_DA42
A2
M_DA46
B8
M_DA40
A3
M_DA47
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1 B9 D1 D8 E2 E8 F9 G1 G9
+1.5VS_VGA
+1.5VS_VGA
hϭϰϬϴƐŝĚĞ hϭϰϬϵƐŝĚĞ
1
1
1
C49510U_0603_6.3V6M
C49510U_0603_6.3V6M
2
DIS@
DIS@
D D
1
C5261U_0402_6.3V4Z
C5261U_0402_6.3V4Z
C5241U_0402_6.3V4Z@C5241U_0402_6.3V4Z
C5251U_0402_6.3V4Z
C5251U_0402_6.3V4Z
2
2
2
@
DIS@
DIS@
DIS@
DIS@
2
1
1
1
1
1
C5271U_0402_6.3V4Z
C5271U_0402_6.3V4Z
C5281U_0402_6.3V4Z@C5281U_0402_6.3V4Z
C5361U_0402_6.3V4Z
C5361U_0402_6.3V4Z
C5131U_0402_6.3V4Z
C5131U_0402_6.3V4Z
2
2
2
2
DIS@
DIS@
@
DIS@
DIS@
DIS@
DIS@
1
1
1
C5050.1U_0402_10V6K
C5050.1U_0402_10V6K
C5090.1U_0402_10V6K
C5090.1U_0402_10V6K
C5080.1U_0402_10V6K
C5080.1U_0402_10V6K
C5040.1U_0402_10V6K
C5040.1U_0402_10V6K
2
2
2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
+1.5VS_VGA +1.5VS_VGA
1
1
1
1
C5290.1U_0402_10V6K@C5290.1U_0402_10V6K
C5350.1U_0402_10V6K
C5350.1U_0402_10V6K
C5300.1U_0402_10V6K@C5300.1U_0402_10V6K
2
2
2
2
@
DIS@
DIS@
@
DIS@
DIS@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
1
1
1
C5011U_0402_6.3V4Z
C5011U_0402_6.3V4Z
C5031U_0402_6.3V4Z@C5031U_0402_6.3V4Z
C5021U_0402_6.3V4Z
C5021U_0402_6.3V4Z
C49210U_0603_6.3V6M
C49210U_0603_6.3V6M
2
2
2
2
DIS@
DIS@
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
@
DIS@
DIS@
DIS@
DIS@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1
1
1
C5381U_0402_6.3V4Z@C5381U_0402_6.3V4Z
C5231U_0402_6.3V4Z
C5231U_0402_6.3V4Z
C5001U_0402_6.3V4Z
C5001U_0402_6.3V4Z
2
2
2
@
DIS@
DIS@
DIS@
DIS@
4
1
1
1
C4840.1U_0402_10V6K
C4840.1U_0402_10V6K
C4870.1U_0402_10V6K
C4870.1U_0402_10V6K
C5221U_0402_6.3V4Z@C5221U_0402_6.3V4Z
2
2
2
@
DIS@
DIS@
DIS@
DIS@
1
1
1
1
C4890.1U_0402_10V6K
C4890.1U_0402_10V6K
C4880.1U_0402_10V6K
C4880.1U_0402_10V6K
2
2
DIS@
DIS@
DIS@
DIS@
1
C4930.1U_0402_10V6K
C4930.1U_0402_10V6K
C5370.1U_0402_10V6K
C5370.1U_0402_10V6K
C4940.1U_0402_10V6K@C4940.1U_0402_10V6K
2
2
2
@
DIS@
DIS@
DIS@
DIS@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
MARS_VRAM A Upper
MARS_VRAM A Upper
MARS_VRAM A Upper
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
29 53Tuesday, February 26, 2013
29 53Tuesday, February 26, 2013
29 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
LCD PANEL Conn.
1 2
A A
BKOFF#[38]
R2114 0_0402_5%@R2114 0_0402_5%@
12
R2115
R2115 10K_0402_5%
10K_0402_5%
R2116
R2116 10K_0402_5%
10K_0402_5% @
@
For power on screen flash issue
R2153
R2153 10K_0402_5%@
10K_0402_5%@
12
13
D
D
S
S
12
R104
R104 1K_0402_5%
1K_0402_5%
2
G
G
100K_0402_5%
100K_0402_5%
R677
R677
PCH_PWM[16]
B B
R2107 0_0402_5%@R2107 0_0402_5%@
12
+1.05VS
HPD Inversion for eDP
C C
CPU_eDP_HPD#[5]
Q11
Q11
2N7002K_SOT23-3
2N7002K_SOT23-3
R2137
R2137 10K_0402_5%
10K_0402_5% @
@
EMB_HPD
12
12
DISPOFF#
+3VS
12
12
R2118
R2118 10K_0402_5%
10K_0402_5%
INVPWM
modify
Touch Panel
+3VS
Place closed to JLVDS1
1
C2103
C2103
0.1U_0402_10V6K
0.1U_0402_10V6K
2
DMIC_DATA[32] DMIC_CLK[32]
USB20_P3[17] USB20_N3[17] +3VS +3VS_CMOS +3VS
Thermal Sensor
A LOGO RED LIGHT
+3VS
12
R674
R674
100K_0402_5%
100K_0402_5%
1 2
CPU_eDPC_AUXN[5]
CPU_eDPC_AUXP[5]
C553 0.1U_0402_10V6KC553 0.1U_0402_10V6K
1 2
C552 0.1U_0402_10V6KC552 0.1U_0402_10V6K
100K_0402_5%
100K_0402_5%
R673
R673
CPU_eDP_AUXN
CPU_eDP_AUXP
12
LCD Panel
EC_SMB_DA2[14,24,36,38] EC_SMB_CK2[14,24,36,38]
LOGO_LED#[37,38] +3VALW
CPU_eDPC_N1[5] CPU_eDPC_P1[5] CPU_eDPC_N0[5] CPU_eDPC_P0[5]
TS_ON[17]
USB20_N8[17] USB20_P8[17]
SMB_CLK_S3[12,14,35,36] SMB_DATA_S3[12,14,35,36]
TS_INT#[18] TS_PRSNC#[18]
B+
+LCDVDD_CONN
PIN1PIN10
PIN31 PIN32
Panel 30+10 PIN
+3VS
+5VS
JLVDS2
@C2113
@
JLVDS1
JLVDS1
STARC_107K30-000001-G2
STARC_107K30-000001-G2
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
CONN@
CONN@
JLVDS2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
E&T_4260K-F10N-00L
E&T_4260K-F10N-00L CONN@
CONN@
GND6 GND5 GND4 GND3 GND2 GND1
R2113 0_0402_5%@R2113 0_0402_5%@ R2109 0_0402_5%@R2109 0_0402_5%@
R2110 0_0402_5%@R2110 0_0402_5%@ R2112 0_0402_5%@R2112 0_0402_5%@
R2108 0_0805_5%@R2108 0_0805_5%@
R1237 750_0402_5%R1237 750_0402_5%
C555 0.1U_0402_10V6K@C555 0.1U_0402_10V6K@ C554 0.1U_0402_10V6K@C554 0.1U_0402_10V6K@ C557 0.1U_0402_10V6KC557 0.1U_0402_10V6K C556 0.1U_0402_10V6KC556 0.1U_0402_10V6K
12
1 2
R2486 0_0603_5%R2486 0_0603_5%
CPU_eDP_AUXN CPU_eDP_AUXP
1 2
1 2 1 2 1 2 1 2
1 2 1 2
1 2 1 2
C2113
4.7U_0805_25V6-K
4.7U_0805_25V6-K
INVPWM DISPOFF# EMB_HPD
+3VALW_LOGO
CPU_eDP_N1 CPU_eDP_P1 CPU_eDP_N0 CPU_eDP_P0
+LEDVDD
1
2
(20 MIL)
PIN1 PIN30
PIN35 PIN33 PIN34 PIN36
36 35 34 33 32 31
>WKtZ/Zh/d
+3VS
W=60mils
1
C2101
C2101
0.1U_0402_10V6K
D D
0.1U_0402_10V6K
PCH_ENVDD[16]
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K @
@
R2111 0_0402_5%
R2111 0_0402_5%
1
C2110
C2110 @
@
2
12
U2412
U2412
5
VIN
4
SS
APL3512ABI-TRG_SOT 23-5
APL3512ABI-TRG_SOT 23-5
PCH_ENVDD_R
+LCDVDD +LCDVDD_CONN
VOUT
1
2
GND
3
EN
1 2
FBMA-L11-201209-221LMA 30T_0805
FBMA-L11-201209-221LMA 30T_0805
L2102
L2102
Css Tss
0.1uF
10nF
1nF
Open or tied to VIN
W=60mils
0.1U_0402_10V6K
0.1U_0402_10V6K
100mS
10mS
1mS
1mS
2
C2109
C2109
1
2
SS table
1
C2124
C2124
0.1U_0402_10V6K
0.1U_0402_10V6K
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
DK^ĂŵĞƌĂŽŶŶ
+3VS
R314 0_0603_5%
R314 0_0603_5%
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
@
@
(20 MIL)
1 2
0.1U_0402_10V6K
0.1U_0402_10V6K
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
LVDS Connector
LVDS Connector
LVDS Connector
LA-9611P
LA-9611P
LA-9611P
(20 MIL)
CMOS SUSPEND 2.4mA
1
@
@
C2114
C2114
2
5
1
@
@ C2115
C2115 10U_0603_6.3V6M
10U_0603_6.3V6M
2
30 53Wednesday, February 27, 2013
30 53Wednesday, February 27, 2013
30 53Wednesday, February 27, 2013
+3VS_CMOS
0.4
0.4
0.4
1
2
3
4
5
Docking (USB3.0)
USB20_P2
A A
USB3_TX2_P[17]
USB3_TX2_N[17]
USB3_RX2_P[17]
USB3_RX2_N[17]
USB20_P2[17]
USB20_N2[17]
USB3_TX2_P
USB3_TX2_N
USB3_RX2_P
USB3_RX2_N
USB20_P2
USB20_N2
USB3_TX2_N USB3_TX2_N
USB3_TX2_P USB3_TX2_P
USB3_RX2_N USB3_RX2_N
USB3_RX2_P USB3_RX2_P
D2403
D2403
1
I/O1
2
GND
3
I/O2
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
4
I/O3
5
VDD
6
I/O4
PN: SC300001G00
D2415
D2415
1
2
4
5
3
8
8
YSCLAMP0524P_SLP 2510P8-10-9
YSCLAMP0524P_SLP 2510P8-10-9
9


8


7


6


+5VALW
USB20_N2
DPA_AUX_P DPA_AUX_P
DPA_AUX_N DPA_AUX_N
mDP_HPD mDP_HPD
PCH_DPC_P0_C PCH_DPC_P0_C
PCH_DPC_N0_C
PCH_DPC_N1_C PCH_DPC_N1_C
D44
D44
1
2
4
5
3
8
8
YSCLAMP0524P_SLP 2510P8-10-9
YSCLAMP0524P_SLP 2510P8-10-9
D43
D43
1
2
4
5
3
8
8
YSCLAMP0524P_SLP 2510P8-10-9
YSCLAMP0524P_SLP 2510P8-10-9
9


8


7


6


9


8


7


6


PCH_DPC_N0_C
PCH_DPC_P1_CPCH_DPC_P1_C
ESD
Docking (Display Port)
B B
Docking Connector
1 2
@R338
@
F1
F1
1.1A_6V_SMD1812P110TF
1.1A_6V_SMD1812P110TF
R928
R928 0_0402_5%
0_0402_5%
Q2404
AP2301GN-HF_SOT23-3
AP2301GN-HF_SOT23-3
3 1
12
2
DK_DETECT#
R678 100K_0402_5%R678 100K_0402_5%
ON/OFFBTN# DK_DETECT#
R338
0_0402_5%
+5VALW
USB20_P2 USB20_N2
USB3_RX2_P
USB3_TX2_NDOCK_CONSUMP
Adap+
12
0_0402_5%
1 2
+5VALW
JDOCK1
JDOCK1
1 2
PCH_DPC_P0[16]
LANE0
PCH_DPC_N0[16]
PCH_DPC_P1[16]
LANE1
PCH_DPC_N1[16]
DOCK_CONSUMP[42]
+3VS
12
R5137
R5137 100K_0402_5%
DPA_AUX_N
DPA_AUX_P
12
1 2
R105 1M_0402_5%@R105 1M _0402_5%@
1 2
R110 1M_0402_5%@R110 1M _0402_5%@
100K_0402_5%
R5158
R5158 100K_0402_5%
100K_0402_5%
C C
1 2
PCH_DPC_AUXN[16]
PCH_DPC_AUXP[16]
C5184 0.1U_0402_10V6KC5184 0.1U_0402_10V6K
1 2
C5185 0.1U_0402_10V6KC5185 0.1U_0402_10V6K
SB00000EO10==>for Lenovo 2nd source SB00000VL00
+5VS
12
R112
R112
1M_0402_5%
1M_0402_5%
@
@
PCH_DPC_HPD[ 16]
D D
check pull up
G
G
2
S
S
Q12
Q12 BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
13
D
D
12
100K_0402_5%
100K_0402_5%
R5140
R5140
mDP_HPD
C242 0.1U_0402_10V6KC242 0. 1U_0402_10V6K
1 2
C243 0.1U_0402_10V6KC243 0. 1U_0402_10V6K
1 2
C545 0.1U_0402_10V6KC545 0. 1U_0402_10V6K
1 2
C544 0.1U_0402_10V6KC544 0. 1U_0402_10V6K
ADP_ID_Dok[40]
Footprint:DRAPH_PJSS0296-MB11H_24P-T
PA_CFG1_LSEO0
DOCK_CONSUMP
PCH_DPC_P0_C PCH_DPC_N0_C
PCH_DPC_P1_C PCH_DPC_N1_C
DPA_AUX_P USB3_RX2_N DPA_AUX_N PA_CFG1_LSEO0 USB3_TX2_P
mDP_HPD
GND1POWER BUTTON ML_LANE0(P)3RETURN ML_LANE0(N)5VBUS(500mA)
7
GND ML_LANE1(P)9USB2.0(N) ML_LANE1(N)11GND
13
GND
15
AUX_CH(P)
17
AUX_CH(N)
19
CONFIG1 CONFIG221USB3.0_TX(N)
23
HOT PLUG DETECT
GROUND25POWER1 DETECT27POWER2 GROUND29GROUND
DRAPH_PJSS0296-M B11H
DRAPH_PJSS0296-M B11H
+5VALW_DOCK_ON[38]
USB2.0(P)
USB3.0_RX(P) USB3.0_RX(N)
USB3.0_TX(P)
150K_0402_5%
150K_0402_5%
2 4 6 8 10 12 14 16 18
GND
20 22 24
GND
26 28 30
R2412
R2412
ON/OFFBTN# [37] DOCK_PRSNT# [18]
+5VALW_DOCK
12
<BOM Structure>Q2404
<BOM Structure>
+3VS
+5VALW_DOCK
C1145
C1145
+5VALW
1000P_0402_50V7K
1000P_0402_50V7K
12
ESD
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Docking
Docking
Docking
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
31 53Tuesday, February 26, 2013
31 53Tuesday, February 26, 2013
31 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
A A
D/
R108 33_0402_5% @R108 33_0402_5% @
12
C651 22P_0402_50V8J@ C651 22P_0402_50V8J@
HDA_RST_AUDIO#[13]
B B
WĞĞƉ
C C
ĞĞƉ
W,ĞĞƉ
1 2
+3VS
R5071
R5071
4.7K_0402_5%
4.7K_0402_5% @
@
1 2
12
R5065
R5065
4.7K_0402_5%
4.7K_0402_5% @
@
BEEP#[38]
HDA_SPKR[13]
C1138
C1138
0.1U_0402_10V6K
0.1U_0402_10V6K 1 2
C1140
C1140
0.1U_0402_10V6K
0.1U_0402_10V6K 1 2
HDA_BITCLK_AUDIO
Power down (PD#) power stage for save power 0V: Power down power stage
3.3V: Power up power stage
EC_MUTE#[38] HDA_SDOUT_AUDIO[13] HDA_BITCLK_AUDIO[13] HDA_SDIN0[13]
HDA_SYNC_AUDIO[13]
PLUG_IN[37]
GNDA
R1124
R1124 33_0402_5%
33_0402_5%
1 2
+5VS +5VS_PVDD
change to short pad
R938 22_0402_5%R938 22_0402_5%
1 2
R942 20K_0402_1%R942 20K_0402_1%
1 2
R940 39.2K_0402_1%R940 39.2K _0402_1%
D/^ĞŶƐĞZϵϰϬƉůĂĐĞŶĞĂƌƉŝŶϭϯ
1 2
C666 2.2U_0603_6.3V6KC666 2.2U_0603_6.3V6K
1 2
C5099 2.2U_0603_6.3V 6KC5099 2.2U_0603_6.3V6K
1 2
C5100 4.7U_0603_6.3V 6KC5100 4.7U_0603_6.3V6K
+MIC1_VREFO_L
PC_BEEP_CPC_BEEP_C_R
12
@
@
R1131
R1131
10K_0402_5%
10K_0402_5%
R943 0_0603_5%
0_0603_5%
1 2
EMI
R929 0_0603_5%
0_0603_5%
1 2
EMI
12
12
@
@ C1141
C1141 1000P_0402_50V7K
1000P_0402_50V7K
@R943
@
WůĂĐĞŶĞĂƌWŝŶϮϱ
@R929
@
C5102
C5102
1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
2
C5094
C5094
C5096
C5096
MIC_JD EC_MUTE# HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO SDATA_IN
HDA_RST_AUDIO# PC_BEEP
JDREF
SENSEA
CBN CBP
+5VDDA_CODEC+5VS
2
1
2
1
PC_BEEP
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C646
C646
C657
C657
1
2
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
WůĂĐĞŶĞĂƌWŝŶϯϴ
+5VS_PVDD
1
C656
C656
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
U900
U900
47
EAPD/COMB-JACK
4
PD#
5
SDATA-OUT
6
BIT-CLK
8
SDATA-IN
10
SYNC
11
RESET#
12
PCBEEP
19
JDREF
20
MONO-OUT(PORT-H)
13
SENSE A
18
SENSE B
35
CBN
36
CBP
34
CPVEE
28
LDO-CAP
29
MIC2-VREFO
30
MIC1-VREFO-R
31
MIC1-VREFO-L
42
PVSS1
43
PVSS2
7
DVSS
>ϯϮϬϮsϯ
^ϬϬϬϬϱϴϯϭϬ
C5095
C5095
3
EMI
+3VS
@R1355
@
+3VDD_CODEC
1
2
C648
C648
2
1
0.1U_0402_10V6K
0.1U_0402_10V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C5110
C5110
1
2
R1355 0_0603_5%
0_0603_5%
1 2
C693
C693
1
change to short padchange to short pad
1U_0402_6.3V6K
1U_0402_6.3V6K
2
0.1U_0402_10V6K
0.1U_0402_10V6K
WůĂĐĞŶĞĂƌWŝŶϭ
+IOVDD_CODEC
1
C654
C654
@
@
2
0.1U_0402_10V6K
0.1U_0402_10V6K
WůĂĐĞŶĞĂƌWŝŶϵ
sĞŶĚŽƌZĞĐŽŵŵĂŶĚĂĚĚϭϬh&
1
39
PVDD1
38
46
25
PVDD2
AVDD1
AVDD2
9
DVDD
DVDD-IO
LINE1-R(PORT-C-R) LINE1-L(PORT-C-L)
MIC1-R(PORT-B-R)
MIC1-L(PORT-B-L)
MIC2-R(PORT-F-R)
MIC2-L(PORT-F-L)
LINE2-R(PORT-E-R)
LINE2-L(PORT-E-L)
SPK-OUT-L+
SPK-OUT-L-
SPK-OUT-R-
SPK-OUT-R+
HPOUT-R(PORT-A-R)
HPOUT-L(PORT-A-L)
SPDIF-OUT
GPIO1/DMIC-CLK
GPIO0/DMIC-DATA
AVSS1 AVSS2
THERMAL PAD
ALC3202-GR_MQFN48_6X6
ALC3202-GR_MQFN48_6X6
VREF
24 23 22 21 17 16 15 14
40 41 44 45
33 32 48
3
2
27 26 37
49
1 2
1
@
@
change to short pad
C655
C655 10U_0603_6.3V6M
10U_0603_6.3V6M
2
MIC_EXT_C
SPK_L2+ SPK_L1­SPK_R1­SPK_R2+
DMIC_CLK_R
DMIC_DATA
R927
R927 0_0402_5%
0_0402_5%
@
@
EMI
sĞŶĚŽƌƌĞĐŽŵŵĞŶĚϮϮƵ
C5097
C5097
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K 12
Internal Speaker
L2407
L2407
1 2
SBY100505T-301Y-N
SBY100505T-301Y-N
EMI
C5101
C5101
1
1U_0402_6.3V6K
1U_0402_6.3V6K
2
WůĂĐĞŶĞdžƚƚŽƉŝŶϮϳ
Pin Assignment
SPK-OUT (Pin40/41/44/45)
Capless HP-OUT (Pin32/33)
Internal
External
4
+MIC1_VREFO_L
R933
R933 1K_0402_5%
1K_0402_5%
12
HP_OUTR [37] HP_OUTL [37]
DMIC_CLK [30]
DMIC_DATA [30]
1
C659
C659
2
0.1U_0402_10V6K
0.1U_0402_10V6K
FunctionLocation
Int Speaker
Headphone out
Mic inExternalMIC1(Pin21/22)
2.2K_0402_5%
2.2K_0402_5%
1 2
R931
R931 470K_0402_5%
470K_0402_5%
1 2
R930
R930
external MIC
EXT_MIC [37]
Headphone
5
D/
GND GNDA
@
@
1 2
C1143 0.1U_0402_10V6K
C1143 0.1U_0402_10V6K
1 2
C1144 0.1U_0402_10V6KC1144 0.1U_0402_10V6K
1 2
C1147 0.1U_0402_10V6KC1147 0.1U_0402_10V6K
1 2
C1148 0.1U_0402_10V6KC1148 0.1U_0402_10V6K
2 1
J112MM@J112MM
@
ŽŵďŽ:ĂĐŬĚĞƚĞĐƚ;ŶŽƌŵĂůŽƉĞŶͿ
R1123 47K_0402_5%R1123 47K_0402_5%
C1134
C1134
1 2
2
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
EXT_MIC
EMI
MIC_JD
Vendor Recommand connect to GNDA
/ŶƚĞƌŶĂů^ƉĞĂŬĞƌ
SPK_R1-
SPK_R2+ SPK_R2+_CONN
SPK_L1-
D D
Width 20 mil
Rdc < 0.05 ohms Rated Current > 2A
1 2
R1356 0_0603_5% @R1356 0_0603_5% @
1 2
R1357 0_0603_5% @R1357 0_0603_5% @
1 2
R1358 0_0603_5% @R1358 0_0603_5% @
1 2
R1359 0_0603_5% @R1359 0_0603_5% @
EMI
1
ǁŝĚĞϮϱD/>
D/
SPK_R1-_CONN
SPK_L1-_CONN
SPK_L2+_CONNSPK_L2+
@
@
12
C1135
C1135
PN:SP02000TS00
@
@
@
@
@
@
C1136
C1136
12
12
C1139
C1139
C1137
C1137
12
JSPK1
JSPK1
1
1
2
2
3
3
4
4
5
GND1
6
GND2
ACES_50271-0040N-001
ACES_50271-0040N-001 ME@
ME@
PIN1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
SPK_R1-_CONN
SPK_R2+_CONN
ZĞƐĞƌǀĞĨŽƌ^ƌĞƋƵĞƐƚ
PIN4
2
D2402
@D2402
@
1
I/O1
2
GND
3
I/O2
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
4
5
6
SPK_L1-_CONN
SPK_L2+_CONN
I/O3
VDD
I/O4
ESD request 0830
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Audio Codec ALC3202
Audio Codec ALC3202
Audio Codec ALC3202
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
32 53Tuesday, February 26, 2013
32 53Tuesday, February 26, 2013
32 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
+3V_LAN
1.5A
C1251
0.1U_0402_10V6K
C1251
0.1U_0402_10V6K
C1250
0.1U_0402_10V6K
C1250
0.1U_0402_10V6K
C1247
0.1U_0402_10V6K
C1247
0.1U_0402_10V6K
C1243
1
2
A A
нϯͺ>EZŝƐŝŶŐƚŝŵĞ;ϭϬйΕϵϬйͿхϭŵ^ĂŶĚфϭϬϬŵ^
R1236
R1236 0_0402_5%
0_0402_5%
@
@
+3V_LAN
370mA
XTLI
XTLO
+3VALW
W=60mils
B B
C1239
C1239 15P_0402_50V8J
15P_0402_50V8J
1 2
C1237
C1237 15P_0402_50V8J
15P_0402_50V8J
1 2
XTLI_R
2
4
JUMP_43X39
JUMP_43X39
GND
GND
J1203
@J1203
@
2
112
1 2
1
Y1201
Y1201
1
25MHZ_12PF_7V25000012
25MHZ_12PF_7V25000012
3
3
dŚĞƐĞĐĂƉƐĐůŽƐĞƚŽhϭϮϬϭWŝŶϭϮϮϳϯϵϰϮϰϳϰϴ
+3V_LAN
1 2
R1239 0_0603_5%
R1239 0_0603_5%
EMI EMI EMI
PCIE_PRX_DTX_P4[14]
PCIE_PRX_DTX_N4[14]
PCIE_PTX_C_DRX_P4[14] PCIE_PTX_C_DRX_N4[14]
LAN_CLKREQ#[14]
PLT_RST#[14,17,23,35,37,38]
CLK_PCIE_LAN[14] CLK_PCIE_LAN#[14]
LAN_WAKE#[38] PCIE_WAKE#[14,15]
C1243
1
1
2
2
@
@
R1232 1K_0402_5%R1232 1K_0402_5%
15K_0402_5%
15K_0402_5%
C1259
C1259
C1241
0.1U_0402_10V6K
C1241
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
1
2
2
2
C1249
4.7U_0603_6.3V6K
C1249
4.7U_0603_6.3V6K
1
2
PCIE_PRX_DTX_N4
1 2
12
R1233
R1233
3.3V : Enable switching regulator 0V : Disable switching regulator
0.1U_0402_10V6K
0.1U_0402_10V6K
C1260
0.1U_0402_10V6K
C1260
0.1U_0402_10V6K
1
2
dŚĞƐĞĐĂƉƐĐůŽƐĞƚŽhϭϮϬϭ
1 2
C1238 0.1U_0402_10V6KC1238 0.1U_0402_10V6K
1 2
C1236 0.1U_0402_10V6KC1236 0.1U_0402_10V6K
1 2
R1235 0_0402_5%@R1235 0_0402_5%@
+3V_LAN
+3V_LAN
8111F-VB support X'tal free
C C
TS1202
TS1202
+V_DAC
LAN_MDI0-
LAN_MDI0+
LAN_MDI1-
LAN_MDI1+
LAN_MDI2-
LAN_MDI2+
LAN_MDI3-
LAN_MDI3+
1
C1288
C1288
0.01U_0402_16V7K
0.01U_0402_16V7K
2
D D
1
2
3
4
5
6
7
8
9
10
11
1
TCT1
TD1+
TD1-
TCT2
TD2
TD2-
TCT3
TD3+
TD3-
TCT4
TD4+
TD4-12MX4-
350UH_IH-160
350UH_IH-160
MCT1
MX1+
MCT2
MX2+
MCT3
MX3+
MCT4
MX4+
MX1-
MX2-
MX3-
24
MCT1
23
RJ45_MDO0-
22
RJ45_MDO0+
21
MCT2
20
RJ45_MDO1-
19
RJ45_MDO1+
18
MCT3
17
RJ45_MDO2-
16
RJ45_MDO2+
15
MCT4
14
RJ45_MDO3-
13
RJ45_MDO3+
@
@
1 2
C1262 0.01U_0402_16V7K
C1262 0.01U_0402_16V7K
1 2
C1261 0.1U_0402_10V6KC1261 0.1U_0402_10V6K
EMI
RP1
RP1
1 8 2 7 3 6 4 5
75_0804_8P4R_1%
75_0804_8P4R_1%
10P_1206_2KV8J
10P_1206_2KV8J
EMI
RJ45_GND
C1287
C1287
LAN_MDI0-
LAN_MDI0+
1
2
2
LAN_MDI2-
LAN_MDI2+
D1027 D1028 2nd :SC300001G00 3nd :SC300001100
+LAN_VDD
C1258
0.1U_0402_10V6K
C1258
0.1U_0402_10V6K
C1256
C1256
1
1
2
2
dŚĞƐĞĐĂƉƐĐůŽƐĞƚŽhϭϮϬϭWŝŶϯϲϵϭϯϮϵϰϭϰϱ
+LAN_VDD
@
@
1 2
R1240 0_0603_5%
R1240 0_0603_5%
PCIE_PRX_C_DTX_P4PCIE_PRX_DTX_P4
PCIE_PRX_C_DTX_N4
PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4
LAN_CLKREQ#
PLT_RST#
CLK_PCIE_LAN CLK_PCIE_LAN#
XTLO
XTLI
LAN_WAKE#PCIE_WAKE#
ISOLATEB
1 2
R1228 10K_0402_5%@R1228 10K_0402_5%@
1 2
R1231 1K_0402_5%@R1231 1K_0402_5%@
@
@
1 2
R1234 0_0402_5%
R1234 0_0402_5%
+LAN_VDDREG
1 2
R1227 2.49K_0402_1%R1227 2.49K_0402_1%
D1207
D1207
6
I/O4
5
VDD
4
I/O3
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
D1208
D1208
6
I/O4
5
VDD
4
I/O3
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
dŚĞZŶĞĞĚĐŚĞĐĐŬнϯsͺ>Eн>EͺsĂƉĂĐŝƚŽƌƉůĂĐĞŵĞŶƚ
C1257
0.1U_0402_10V6K
C1257
0.1U_0402_10V6K
C1253
0.1U_0402_10V6K
C1253
C1254
0.1U_0402_10V6K
C1254
0.1U_0402_10V6K
C1255
0.1U_0402_10V6K
C1255
0.1U_0402_10V6K
0.1U_0402_10V6K
I/O2
GND
I/O1
I/O2
GND
I/O1
0.1U_0402_10V6K
1
1
2
2
C1246
0.1U_0402_10V6K
C1246
0.1U_0402_10V6K
1
2
3
LAN_MDI1+
2
1
LAN_MDI1-
3
LAN_MDI3+
2
1
LAN_MDI3-
0.1U_0402_10V6K
C1252
0.1U_0402_10V6K
C1252
0.1U_0402_10V6K
1
1
2
2
C1242
1U_0402_6.3V6K
C1242
1U_0402_6.3V6K
1
2
U1201
U1201
22
HSOP
23
HSON
17
HSIP
18
HSIN
16
CLKREQB
25
PERSTB
19
REFCLK_P
20
REFCLK_N
43
CKXTAL1
44
CKXTAL2
28
LANWAKEB
26
ISOLATEB
14
NC/SMBCLK
15
NC/SMBDATA
38
GPO/SMBALERT
33
ENSWREG
34
VDDREG
35
VDDREG
46
RSET
24
GND
49
PGND
RTL8111F-CGT_QFN48_6x6
RTL8111F-CGT_QFN48_6x6
MCT1
MCT2
MCT3
MCT4
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
1
2
+LAN_SROUT1.05+LAN_EVDD10+LAN_VDDREG
LED3/EEDO LED1/EESK
NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
W=60mils W=60mils
dŚĞƐĞĐŽŵƉŽŶĞŶƚƐĐůŽƐĞƚŽhϭϮϬϭWŝŶϯϲ
;^ŚŽƵůĚďĞƉůĂĐĞǁŝƚŚŝŶϮϬϬŵŝůƐͿ
31 37 40
LED0
30
R1230 10K_0402_5%@R1230 10K_0402_5%@
EECS
32
R1229 10K_0402_5%@R1229 10K_0402_5%@
EEDI
1
MDIP0
2
MDIN0
4
MDIP1
5
MDIN1
7 8 10 11
13
DVDD10
29
DVDD10
41
DVDD10
27
DVDD33
39
DVDD33
12
AVDD33
42
AVDD33
47
AVDD33
48
AVDD33
21
EVDD10
AVDD10 AVDD10 AVDD10 AVDD10
REGOUT
D1209
D1209
D1210
D1210
D1211
D1211
D1212
D1212
+LAN_EVDD10
3 6 9 45
36
+LAN_SROUT1.05
@
@
12
@
@
12
@
@
12
@
@
12
EMI
Reserve for Surge
L1201
L1201
1 2
2.2UH_NLC252018T-2R2J-N_5%
2.2UH_NLC252018T-2R2J-N_5%
LANLINK_STATUS# LAN_ACTIVITY#
1 2 1 2
LAN_MDI0+ LAN_MDI0­LAN_MDI1+ LAN_MDI1­LAN_MDI2+ LAN_MDI2­LAN_MDI3+ LAN_MDI3-
+LAN_VDD
+3V_LAN+3VS
+LAN_VDD
NEW(referDC234005L00 MB TO TOP 4.95 move up 1.35)
NEW(refer 130452-D MB TO TOP 4.95 move up 1.35)
+LAN_VDD
C1248
4.7U_0603_6.3V6K
C1248
4.7U_0603_6.3V6K
C1245
0.1U_0402_10V6K
C1245
0.1U_0402_10V6K
1
1
2
2
ŽŶŶĞĐƚŽƌd
PN:XXXXXXXXXX
R1241
R1241
LAN_ACTIVITY# LANLED_ACT#
拵湹捛
拵湹捛
510_0402_5%
510_0402_5%
EMI
)
)
R1246
R1246
510_0402_5%
510_0402_5%
12
+3V_LAN
RJ45_MDO0+
RJ45_MDO0-
RJ45_MDO1+
RJ45_MDO2+
RJ45_MDO2-
RJ45_MDO1-
RJ45_MDO3+
RJ45_MDO3-
12
LANLED_LINK#LANLINK_STATUS#
+3V_LAN
A1
A2
B2
yellow
1
2
3
4
5
6
7
8
B1
Green
RJ-45 Conn. 㕘㕘㕘㕘㕁㕁㕁㕁嘇嘇嘇嘇&footprint check
JRJ45
JRJ45
9
Yellow LED-
10
Yellow LED+
1
PR1+
2
PR1-
3
PR2+
4
PR3+
5
PR3-
6
PR2-
7
PR4+
8
PR4-
11
Green LED -
12
Green LED +
SANTA_130452-D
SANTA_130452-D
CONN@
CONN@
14
G2
13
G1
ESD
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
LAN RTL8111F
LAN RTL8111F
LAN RTL8111F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
33 53Wednesday, February 27, 2013
33 53Wednesday, February 27, 2013
33 53Wednesday, February 27, 2013
0.4
0.4
0.4
1
SATA HDD BTB CONN.
+3VS
12
R713
R713
@
@
10K_0402_5%
10K_0402_5%
1 2
A A
SATA_PTX_C_DRX_P0[13] SATA_PTX_C_DRX_N0[13]
SATA_DTX_C_PRX_P0[13] SATA_DTX_C_PRX_N0[13]
+3VS +3VS +3VS +3VS
12
R707
R707
@
@
10K_0402_5%
10K_0402_5%
A_PRE0_HDD A_PRE1_HDD B_PRE0_HDD
12
R708
R708
10K_0402_5%
B B
10K_0402_5%
C68 0.01U_0402_16V7KC68 0.01U_0402_16V7K
1 2
C67 0.01U_0402_16V7KC67 0.01U_0402_16V7K
1 2
C2401 0.01U_0402_16V 7KC2401 0. 01U_0402_16V7K
1 2
C2402 0.01U_0402_16V 7KC2402 0. 01U_0402_16V7K
R703
R703
+3VS
12
R709
R709
10K_0402_5%
10K_0402_5%
12
R710
R710
@
@
10K_0402_5%
10K_0402_5%
@
@
SATA_PTX_DRX_P0 SATA_PTX_DRX_N0
SATA_DTX_PRX_P0 SATA_DTX_PRX_N0
A_PRE1_HDD B_PRE1_HDD
10K_0402_5%
10K_0402_5%
12
@
@
12
R711
R711 10K_0402_5%
10K_0402_5%
12
R712
R712 10K_0402_5%
10K_0402_5%
U702
U702
7
EN
1
A_INp
2
A_INn
5
B_OUTp
4
B_OUTn
19
A_PRE1
17
B_PRE1
18
TEST
3
GND
13
GND
21
EPAD
PS8520CTQFN20GTR2-A_TQ FN20_4X4
PS8520CTQFN20GTR2-A_TQ FN20_4X4
B_PRE1_HDD
(PIN17)(PIN8)(PIN19)(PIN9)
@
@
VDD VDD
A_PRE0 B_PRE0
A_OUTp A_OUTn
B_INp B_INn
12
R715
R715
10K_0402_5%
10K_0402_5%
12
R716
R716
10K_0402_5%
10K_0402_5%
2
+3VS
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C705
C705
C706
C706
12
10 20
6
NC
16
NC
9 8
15 14
11 12
2
@
@
R704
R704
1 2
4.99K_0402_1%
A_PRE0_HDD B_PRE0_HDD
SATA_PTX_DRX_P0_R SATA_P TX_DRX_P0_C
EŽƌŵĂůŽƉĞƌĂƚŝŽŶ ;ĚĞĨĂƵůƚͿ
ŽŵƉůŝĂŶĐĞƚĞƐƚŝŶŐ ŵŽĚĞĞŶĂďůĞ
4.99K_0402_1%
12
C710 0.01U_0402_16V7KC710 0.01U_0402_16V7K
12
C709 0.01U_0402_16V7KC709 0.01U_0402_16V7K
12
C711 0.01U_0402_16V7KC711 0.01U_0402_16V7K
12
C712 0.01U_0402_16V7KC712 0.01U_0402_16V7K
d^d
;/ŶƚĞƌŶĂůƉƵůů>ŽǁͿ
Low
High
ͺWZϭͺWZϭ ;/ŶƚĞƌŶĂůƉƵůů>ŽǁͿ ;/ŶƚĞƌŶĂůƉƵůů>ŽǁͿ
ϬĚŶŽƉƌĞͲĞŵƉŚĂƐŝƐ
ϭϱĚƉƌĞͲĞŵƉŚĂƐŝƐŝƐƐĞůĞĐƚĞĚ
ϮϱĚƉƌĞͲĞŵƉŚĂƐŝƐŝƐƐĞůĞĐƚĞĚ
ϯϱĚƉƌĞͲĞŵƉŚĂƐŝƐŝƐƐĞůĞĐƚĞĚ
Low
Low
3
4
5
SATA HDD CONN.
PN:XXXXXXXXXX
JHDD1
JHDD1
1
GND
SATA_PTX_DRX_P0_C SATA_PTX_DRX_N0_C
J2401@
J2401@
112
SATA_DTX_PRX_N0_C SATA_DTX_PRX_P0_C
2
5VS_HDD
+3VS
SATA_PTX_DRX_N0_CSATA_PTX_DRX_N0_R
SATA_DTX_PRX_P0_CSATA_DTX_PRX_P0_R SATA_DTX_PRX_N0_CSATA_DTX_PRX_N0_R
+5VS
HDD_DETECT#[38]
JUMP_43X79
JUMP_43X79
WŝŶϭϴƚŽ'EĨŽƌ'ĞŶϯ
ͺWZϬͺWZϬ
Low
High
LowHigh
HighHigh
+5VS
@
C2403
C2406
10U_0603_6.3V6M
C2406
10U_0603_6.3V6M
C2405
1U_0402_6.3V6K@C2405
1U_0402_6.3V6K
1000P_0402_50V7K@C2403
1000P_0402_50V7K
1
1
1
@
2
2
2
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
V33
9
V33
10
V33
11
GND
12
GND
13
GND
14
V5
15
V5
16
V5
17
GND
18
Reserved
19
GND
20
V12
21
V12
22
V12
SANTA_191901-1
SANTA_191901-1
23
NC
24
NC
PIN1PIN15
Ņ ņ
Ņ IJ
ņ
ĩ ĩ
ij
ł
Ń ń
ĩ
Š
Š
ŏ
ʼn
ń
ő
ő
ń
IJ
ĩ
ʼn
œ
œ Ī
ij
ť
ņ
ņ İ
Ī
ı
Ŧ
ı Š
Š
ŧ
ʼn
ʼn
Ţ
Ņ
Ņ
Ŷ
Ņ
Ņ
ŭ
İ
Ī
ŵ
C C
Ī
D D
ń ʼn
Ņ IJ
Ŧ
ť İ
Į
Ń ń
ņ
ĩ ʼn
Ů
Ł
Į
ij
ű
ķ
ķ
ũ
ň Ţ
ţ
ı
Ŵ
ű Ū
Ŵ
IJĮ
Ŵ
Ĵ
APS G-Sensor mSATA CONN.
GS_SELFTEST[38] GS_VOUTX [38]
+3VS +3VS_GS
@
@
1 2
R2405 0_0603_5%
R2405 0_0603_5%
ņ Œ
ņ IJ
Œ
ĩ ĩ
ij
Ń
ł ń
ĩ
Š
Š
ŏ
ʼn
ń
ő
ő
ń
IJ
ĩ
ʼn
œ
œ Ī
ij
ť
ņ
ņ Ī
IJ
Ŧ
IJ
ı
ı
Š
Š
ŧ
ʼn
ʼn
Ţ
IJIJ
Ņ
Ņ
Ŷ
Ņ
Ņ
ŭ
İ
Ī
ŵ Ī
C2413
10U_0603_6.3V6M
C2413
10U_0603_6.3V6M
1
2
1
12
R2402
R2402 100K_0402_5%
100K_0402_5%
C2410
C2410
1
2
APS_GND
0.1U_0402_10V6K
0.1U_0402_10V6K
ń ʼn
ņ IJ
Ų
ť İ
Ŷ
Ń ń
Ţ
ġ ʼn
ŭ
ĩ
ı
ij
Ū
Ł Ż
ķ Ţ
ň
ĸ
ŵ
ţ Ū
ű Ű
Ŵ
ĵ
ů
Ī
U2401
U2401
2
ST
14
Vs
15
Vs
3
COM
5
COM
6
COM
7
COM
LIS34ALTR_LGA16_4X4
LIS34ALTR_LGA16_4X4
@ J2402
@
GS_ON#[38]
Ņ ņ
Ņ Ř
ņ IJ
Ř ĩ
ij ń
ĩ ʼn
ń IJ
ʼn
ġ
Ī
ij
ġ
ĩ
Ī
ġ
ť ġ
Ŧ ġ
ŧ ġ
Ţ IJ
Ŷ ŭ ŵ Ī
J2402
21
2MM
2MM
Xout Yout Zout
NC NC NC NC NC NC
ı
APS_GND
GS_ON#
Ņ Ŧ Ņ
ŷ Ŧ
Ū
ĩ Į
Ť
ų
Ű ņ
Ŧ
Ŧ
ű Ņ
Ů
ġ
Ť
Ŧ Ŧ
ű
ĩ
Ň
Ű
ų Į
ũ
ų
Ŷ
Ů
Ű
Ţ ņ
Ţ
Ŧ
ů
Ů
ű
ŵ Ů
Ŵ
Ť
Ť
Ŧ
Ŧ
Ŧ ű
Ū
Ű
ŵ
ů
ų
Ŵ ũ
Ŵ
Ů
Ū
ť
Ţ
ġ Ţ
ġ
Ů
Ű
Ŧ
ŵ
Ţ Ŵ
ő
Ŧ
ů
ť
Ŧ
ŵ Ū
Ŷ
ů
Į
ġ
Ŵ
ġ Ŵ
ŭ
ť
Į
Ŵ
ġ
12
VOUTX
Ŕ ġ
10
VOUTY
Ŵ
Ŧ
Į
Ŧ
Ţ
ł
8
ő
Ŧ
ť
Ŀ
ŵ
ŵ
ŕ Ŷ
C2411
C2411
ġ
ġ
ġ
ŵ
ġ
ł ŭ
Ř
Ŵ
Ņ
Ū
Ŕ
ġ
1
Ŵ
Ū
Ŧ
ņ
ů
ł
4
IJ Ŧ
ť
9
ŵ
ġ
Ũ
ŕ
į
11
ġ
ŵ
ŵ
Ř
ġ
ł
13
Ķ Ř
16
ũ
Ū
Ū
Ÿ
ġ
İ Ū
ġ
ů
ť
APS_GND
ũ
IJ
Ĵ ť
Ŕ
Ũ
ŵ
Ŧ
į
į ŵ
ũ
ġ
ũ
ů
Ķ
ı ũ
Ű
Ÿ
ġ
ġ
İ
İ ġ
ų
ũ
ŧ
ŭ
Ĵ
ķ ō
ŵ
Ŧ
Ű
Ū
į
į Ű
ů
ų
ů
ı
ı ů
ġ
ġ
Ŭ
ġ
ġ Ũ
ŭ
ń
ġ
ň
ň Ū
ʼn
ţ
ţ ů
IJ
ű
R2138
@ R2138
@
ű Ŭ
İ
150K_0402_5%
150K_0402_5%
Ŵ
Ŵ ġ
ń
ġ
Ī ʼn
Ŵ
R2410
R2410
ij
1 2
ű
150K_0402_5%
150K_0402_5%
Ŧ Ŧ
@
@
ť ġ Ű ů ŭ
1 2
R2403 56K_0402_5%R2403 56K_0402_5%
1 2
R2404 56K_0402_5%R2404 56K_0402_5%
C2414
0.1U_0402_10V6K
C2414
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
2
2
+3VS
12
1
2
2
Q2402
AP2301GN-HF_SOT23-3
AP2301GN-HF_SOT23-3
3 1
2
C2426
C2426
0.01U_0402_16V7K
0.01U_0402_16V7K @
@
1
@
@ C2418
C2418
0.01U_0402_16V7K
0.01U_0402_16V7K
2
@Q 2402
@
C2412
0.1U_0402_10V6K
C2412
0.1U_0402_10V6K
1
2
1
@
@
C2417
C2417
0.1U_0402_10V6K
0.1U_0402_10V6K
2
C2415
C2415
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
E
Ϭ
ϭ
GS_VOUTY [38]
+3VS_GS
1
@
@ C2420
C2420
10U_0603_6.3V6M
10U_0603_6.3V6M
2
ĞǀŝĐĞ&ƵŶĐƚŝŽŶͲх ^ƚĂŶĚLJDŽĚĞ
Ņ Ŧ ŷ
Ņ Ū
Ŧ
ĩ Ť
ŷ
ť Ŧ
Ū
Ŧ ġ
Ť
ŧ Ņ
Ŧ
Ţ Ū
ġ
Ŷ Ŵ
ņ
ŭ Ţ
ů
ŵ ţ
Ţ
Ī ŭ
ţ Ŧ
ŭ ť
Ŧ ť ġ
3
SATA_PTX_C_DRX_N1[13] SATA_PTX_C_DRX_P1[13]
SATA_DTX_C_PRX_N1[13] SATA_DTX_C_PRX_P1[13]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
C69 0.01U_0402_16V7KC69 0.01U_0402_16V7K
1 2
C70 0.01U_0402_16V7KC70 0.01U_0402_16V7K
1 2
C2408 0.01U_0402_16V 7KC2408 0. 01U_0402_16V7K
1 2
C2409 0.01U_0402_16V 7KC2409 0. 01U_0402_16V7K
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Deciphered Date
4
SATA_PTX_DRX_N1 SATA_PTX_DRX_P1
SATA_DTX_PRX_N1 SATA_DTX_PRX_P1
JMSTA1
JMSTA1
2
112
4
334
6
556
8
778
10
9910
12
111112
14
131314
ACES_50169-01441-001
ACES_50169-01441-001
CONN@
CONN@
+3VS
J2404 @
J2404 @
2
112
JUMP_43X79
JUMP_43X79
mSATA_DETEC# [38]
MSATS_DEVSLP [17]
PIN1PIN13
PIN14
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
HDD/mSATA/G-Sensor
HDD/mSATA/G-Sensor
HDD/mSATA/G-Sensor
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
PIN2
34 53Wednesday, February 27, 2013
34 53Wednesday, February 27, 2013
34 53Wednesday, February 27, 2013
0.4
0.4
0.4
1
USB 3.0 Charger & Conn.
C9
C9
0.1U_0402_10V6K
0.1U_0402_10V6K
1 2
R16 0_0402_5%@R16 0_0402_5%@
12
A A
B B
USB_OC0#[17,37]
USB20_N1[17] USB20_P1[17]
AOU_EN[38]
AOU_CTL2[38] AOU_CTL3[38]
U2004
U2004
1
IN
13
FAULT#
2
DM_OUT
DM_IN
3
DP_OUT
DP_IN
4
ILIM_SEL
5
EN/DSC
6
CTL1
7
CTL2
8
CTL3
GPAD
TPS2541ARTER_QFN16_3X3
TPS2541ARTER_QFN16_3X3
ILIM1 ILIM0
GND
+5V_CHGUSB+5VALW
12
OUT
9
NC
11 10
15 16
R11 19. 1K_0402_1%R11 19.1K_0402_1%
14 17
2
1 2
USB20_N1_C USB20_P1_C
3
Superworld’s common mode choke(SM070001V00) has quality issue for USB 3.0
L2401
L2401
WCM-2012-900T_4P
WCM-2012-900T_4P
USB20_N1_C USB20_N1_C_R
USB20_P1_C
USB3_RX1_N[17]
USB3_RX1_P[17]
USB3_TX1_N[17]
USB3_TX1_P[17]
USB3_RX1_N USB3_RX1_C_N
USB3_RX1_P
1 2
USB3TXDN1
C24440.1U_0402_10V6K C24440.1U_0402_10V6K
1 2
USB3TXDP1
C24450.1U_0402_10V6K C24450.1U_0402_10V6K
3
3
2
2
L2405
L2405
WCM-2012HS-900T
WCM-2012HS-900T
2
2
3
3
L2404
L2404
WCM-2012HS-900T
WCM-2012HS-900T
2
2
3
3
4
4
1
1
1
1
4
4
1
1
4
4
EMI
USB20_P1_C_R
D2401
D2401
1
2
3
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
I/O3
I/O1
VDD
GND
I/O4
I/O2
4
5
6
+5V_CHGUSB
USB20_N1_C_R
USB3_TX1_C_P
USB3_TX1_C_N
USB3_RX1_C_P
USB3_RX1_C_N USB3_RX1_C_N
1
2
4
5
3
TVWDF1004AD0_DFN9
TVWDF1004AD0_DFN9
USB20_P1_C_R
USB3_RX1_C_P
USB3_TX1_C_N
USB3_TX1_C_P
D2410
D2410
4
+5V_CHGUSB
C2434
150U_B2_6.3VM_R35M+C2434
150U_B2_6.3VM_R35M
C1146
C1146
1
12
+
9
USB3_TX1_C_P
8
USB3_TX1_C_N
7
USB3_RX1_C_P
6
2
JUSB1
JUSB1
1
VBUS
2
D-
3
D+
4
GND
5
STDA_SSRX-
6
STDA_SSRX+
7
GND
8
STDA_SSTX-
9
STDA_SSTX+
10
GND
11
GND
12
GND
13
GND
SINGA_2UB4039-200011F
SINGA_2UB4039-200011F
CONN@
CONN@
ESD
1000P_0402_50V7K
1000P_0402_50V7K
ESD
PIN1 VBUS PIN2 D­PIN3 D+ PIN4 GND PIN5 RX­PIN6 RX+ PIN7 GND PIN8 TX­PIN9 TX+
5
5
1
6
2
7
3
8
4
9
Mini-Express Card for WLAN/WiMAX(Half)
Mini-Express Card(WLAN/WiMAX)
C2452
C2452
+1.5VS+3VS_AOAC
C2455
0.1U_0402_10V6K
C2455
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
For AOAC assessment
AOAC_WLAN#[38]
11/17
AOAC_WLAN#
+3VALW +3VS_AOAC
R2411
R2411
1 2
150K_0402_5%
150K_0402_5%
J2406
J2406
112
JUMP_43X79
JUMP_43X79
Q2403
AP2301GN-HF_SOT23-3
AP2301GN-HF_SOT23-3
3 1
AOAC@
AOAC@
@
@
2
AOAC@Q2403
AOAC@
2
1
C2422
0.01U_0402_16V7K
0.01U_0402_16V7K
2
AOAC@C2422
AOAC@
1
C2419
0.1U_0402_10V6K
0.1U_0402_10V6K
2
AOAC@C2419
AOAC@
PIN1PIN51
PIN53PIN54
+3VS_AOAC
12
R2243
R2243 10K_0402_5%
10K_0402_5% @
@
WLAN_WAKE#[38]
WLBT_OFF_5#[13] WLAN_CLKREQ1#[14]
C C
CLK_PCIE_WLAN1#[14] CLK_PCIE_WLAN1[14]
BT_DET#[17]
PCIE_PRX_DTX_N2[14] PCIE_PRX_DTX_P2[14]
PCIE_PTX_C_DRX_N2[14] PCIE_PTX_C_DRX_P2[14]
EC_TX_P80_DATA[37,38] EC_RX_P80_CLK[37,38]
WLBT_OFF_51#[18]
WLAN_WAKE#
WLBT_OFF_5# WLAN_CLKREQ1#
R2427 1K_0402_5%R2427 1K _0402_5%
+3VS_AOAC
EC_TX_P80_DATA EC_RX_P80_CLK
1 2
1 2
1 2 1 2
R2470
R2470
1K_0402_5%
1K_0402_5%
&ŽƌƚŽĚĞƚĞĐƚ ĚĞďƵŐĐĂƌĚ ŝŶƐĞƌƚ
R2432
R2432
R2433
R2433
R2435
R2435
100K_0402_5%
100K_0402_5%
CLK_PCI_DB_R
100_0402_1%
100_0402_1% 100_0402_1%
100_0402_1%
12
JMINI1
JMINI1 CONN@
CONN@
CONCR_159SBBA32010NNN
CONCR_159SBBA32010NNN
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
G254G1
53
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
J2403
J2403
JUMP_43X79
JUMP_43X79
@
@
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1
1
2
2
RF_OFF# PLT_RST#
SMB_CLK_S3 SMB_DATA_S3
+1.5VS+3VS_AOAC+3VS
RF_OFF# [38] PLT_RST# [14,17,23,33,37,38]
SMB_CLK_S3 [12,14,30,36] SMB_DATA_S3 [12,14,30,36]
USB20_N10 [17] USB20_P10 [17]
D D
EĞĞĚĐŚĞĐŬt>EdŵŽĚƵůĞK&&ƉŝŶ
1
NEW(apply compal PN) 159SBBA32010NNN
2
PIN52 PIN2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
USB 3.0 Connector & WLAN
USB 3.0 Connector & WLAN
USB 3.0 Connector & WLAN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
35 53Tuesday, February 26, 2013
35 53Tuesday, February 26, 2013
35 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
INT_KBD Conn.
KSI[0..7]
KSO[0..17]
A A
Vcc 3V for LEDs KB_LED1 for Fn KB_LED2 for F1 KB_LED3 for F4 Fn (S9)
D17 (GND)
B B
KB_LED1_FN[38] KB_LED2_F1[38] KB_LED3_F4[38]
FN(S9)
KSI[0..7] [38]
KSO[0..17] [38]
KSI8[38]
+3VS
KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
JKB1
JKB1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
GND1
32
GND2
JAE_FL10F032HA2
JAE_FL10F032HA2
33 34
2
<ƉŝŶŶĞĞĚĐŽŶĨŝƌŵ
JAE_FL10F032HA2
nwe footprint
Pin 1
Cable
Pin32 Pin1
JAE_FL10S032HA1
old footprint
3
4
5
Track point
PN:SP01001CH00
+5VS
Pin32Pin1
Pin 32
3
1
TP_DATA2
TP_CLK2
2
D2409
D2409
@
@
PJDLC05_SOT23-3
PJDLC05_SOT23-3
ESD
+5VS
KB_LED_DET#[38]
KB_LED_PWM[38]
change footprint & PN check PIN1
R2226
R2226
10K_0402_5%
10K_0402_5%
+5VS
1
C2508
C2508
0.1U_0402_10V6K
0.1U_0402_10V6K
2
JTP1
JTP1
TP_DATA2
1 2
TP_RESET
TP_CLK2
KB_LED_PWM
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
CONN@
CONN@ JAE_FL10F012HA1
JAE_FL10F012HA1
GND1 GND2
13 14
PIN1 PIN12
Pin 1
Pin 12
Cable
Fintek thermal sensor placed near CPU Core
+3VS +3VS
12
R2448
R2448 10K_0402_5%
10K_0402_5% @
GND
@ C2500
@
@ C2505
@
@
10
EC_SMB_CK2
9
EC_SMB_DA2
8
7
6
C2500
1 2
R2450
R2450
0_0402_5%
0_0402_5%
12
1
C
C
2
B
B
E
E
3
Q2407 near PCH Q2408 near DIMM
12
1
C
C
2
C2505
B
B
E
E
3
@
@
Q2407
Q2407 MMST3904-7-F_SOT323-3
MMST3904-7-F_SOT323-3
Q2408
Q2408
MMST3904-7-F_SOT323-3
MMST3904-7-F_SOT323-3
EC_SMB_CK2 [14,24,30,38]
EC_SMB_DA2 [14,24,30,38]
MAINPWON [38,43]
ZDKdϭϮ;нͲͿ dƌĂĐĞǁŝĚƚŚƐƉĂĐĞϭϬϭϬŵŝů dƌĂĐĞůĞŶŐƚŚфϴΗ
2
U2407
C C
REMOTE1+
1
2
C2502
C2502
C2504
C2504
1
2
1
2
REMOTE1-
REMOTE2+
REMOTE2-
REMOTE1+
REMOTE1-
REMOTE2+
REMOTE2-
C2498
C2498
0.1U_0402_10V6K
0.1U_0402_10V6K
ůŽƐĞhϮϰϬϳ
D D
2200P_0402_25V7K
2200P_0402_25V7K
2200P_0402_25V7K
2200P_0402_25V7K
U2407
1
VDD
2
DP1
3
DN1
4
DP2/DN3
5
DN2/DP3
F75303M_MSOP10
F75303M_MSOP10
ĚĚƌĞƐƐϭϬϬϭͺϭϬϭdžď ϮŶĚƐŽƵƌĐĞ ^ϬϬϬϬϮϵϮϭϬͲͲхDϭϰϬϯͲϮͲ/>ͲdZ
1
SMCLK
SMDATA
ALERT#
THERM#
REMOTE1+
2200P_0402_25V7K
2200P_0402_25V7K
REMOTE1-
REMOTE2+
2200P_0402_25V7K
2200P_0402_25V7K
REMOTE2-
Click pad
PIN1 PIN12
to EC
to EC to EC
SMB_CLK_S3[12,14,30,35]
SMB_DATA_S3[12,14,30,35]
CP_RESET#[38] TP_CLK[38] TP_DATA[38] TP_RESET[38] BYPASS[38]
+5VS
1 2
R2443 4.7K_0402_5%@R2443 4.7K_0402_5%@
1 2
R2444 4.7K_0402_5%
@
R2444 4.7K_0402_5%
@
1 2
R2447 100K_0402_1%R2447 100K_0402_1%
TP_CLK2
TP_DATA2
CP_RESET#
+5VS
check rest voltage
TP_CLK
TP_DATA
2
3
D2408
D2408 PJDLC05_SOT23-3
PJDLC05_SOT23-3 @
@
1
ESD
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
PN:XXXXXXXX
JCP1
JCP1
1
1 2
R2469 0_0402_5%@R2469 0_0402_5%@
R2479 0_0402_5%@R2479 0_0402_5%@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
TP_DATA2 TP_CLK2
1 2
CP_RESET# TP_CLK TP_DATA TP_RESET BYPASS
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
KB/CP/TP/FP/Thermal Sensor
KB/CP/TP/FP/Thermal Sensor
KB/CP/TP/FP/Thermal Sensor
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
ACES_51522-01201-001
ACES_51522-01201-001 CONN@
CONN@
LA-9611P
LA-9611P
LA-9611P
5
13
GND
14
GND
36 53Tuesday, February 26, 2013
36 53Tuesday, February 26, 2013
36 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
2
3
4
5
Power Button
+3VLP
12
R2453
R2453
100K_0402_5%
100K_0402_5%
D2412
D2412
R2478
R2478 0_0603_5%
0_0603_5%
EC_FAN_ID[38]
EC_TACH[38]
EC_FAN_PWM[38]
ON/OFFBTN#
10K_0402_5%
10K_0402_5%
1000P_0402_50V7K
1000P_0402_50V7K
A A
B B
ON/OFFBTN#[31]
+5VS +3VS
12
R2449
R2449
C2503
C2503
1 2
RB751V-40_SOD323-2
RB751V-40_SOD323-2
J2405
J2405 SHORT PADS
SHORT PADS
1 2
40mil
12
+5VS_FAN
1
1
C2499
C2499
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
2
2
@
@
JFAN1
JFAN1
1
1
2
2
3
3
4
4
5
5
6
GND1
7
GND2
ACES_50281-00501-001
ACES_50281-00501-001 CONN@
CONN@
ON/OFF [38]
FAN PWM
PIN1 PIN5
I/O Board CONN.
+3VS
HP_OUTL[32,37] HP_OUTR[32,37] EXT_MIC[32,37] PLUG_IN[32,37]
PCH_DPB_HPD[16, 37] HDMICLK_NB[16,37] HDMIDAT_NB[16,37]
PCH_DPB_P0[16,37] PCH_DPB_N0[16,37]
PCH_DPB_P1[16,37] PCH_DPB_N1[16,37]
PCH_DPB_P2[16,37] PCH_DPB_N2[16,37]
PCH_DPB_P3[16,37] PCH_DPB_N3[16,37]
JBTB2
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
GND_1
GND_2
64
GND_3
GND_4
ACES_51015-06001-002
ACES_51015-06001-002
Connector: 0.3A / pin
JBTB1
JBTB1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
GND_2 GND_4
GND_1 GND_3
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
ON/OFFBTN#
27
29
29
31
31
33
N38433539
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61 63
1
+5VALW
+5VS
+3VLP
LID_SW# [ 37,38]
T9T9
USB_ON# [37,38] USB_OC0# [17,35,37]
USB3_TX0_P [17,37] USB3_TX0_N [17,37]
USB3_RX0_P [17,37] USB3_RX0_N [17,37]
USB20_P0 [17,37] USB20_N0 [17,37]
ON/OFFBTN#
Power Button
Lid Switch & LED
USB3.0
D2417
D2417
2
3
L30ESD24VC3-2_SOT23-3
L30ESD24VC3-2_SOT23-3 @
@
to EC
1
+3VS
HP_OUTL[32,37] HP_OUTR[32,37]
Audio combo Jack
CONN@JBTB2
CONN@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
ON/OFFBTN#
27
29
29
31
31
33
N38433539
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61 63
+5VALW
+5VS
+3VLP
LID_SW# [ 37,38]
USB_ON# [37,38] USB_OC0# [17,35,37]
USB3_TX0_P [17,37] USB3_TX0_N [17,37]
USB3_RX0_P [17,37] USB3_RX0_N [17,37]
USB20_P0 [17,37] USB20_N0 [17,37]
HDMI
EXT_MIC[32,37] PLUG_IN[32,37]
PCH_DPB_HPD[16, 37] HDMICLK_NB[16,37] HDMIDAT_NB[16,37]
PCH_DPB_P0[16,37] PCH_DPB_N0[16,37]
PCH_DPB_P1[16,37] PCH_DPB_N1[16,37]
PCH_DPB_P2[16,37] PCH_DPB_N2[16,37]
PCH_DPB_P3[16,37] PCH_DPB_N3[16,37]
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
62 64
PANAS_AXK8L60114B G
PANAS_AXK8L60114B G
ESD request 0827
PIN5 PIN1
C C
U10
U10
1
NC
2
NC
3
NC
7
LPCPD#
PP
SERIRQ
6
NC
9
VNC
LFRAME#
4
GND
11
GND
18
GND
5
NC
8
VNC
12
NC
13
NC
14
LRESET#
NC
ST33ZP24AR28PVSP _TSSOP28
ST33ZP24AR28PVSP _TSSOP28
TPM@
TPM@
D D
RF 11/17
1
VPS VPS
LAD0 LAD1
LAD2 LAD3
NC
LCLK
NC NC
CLK_PCI_TPM
+3VS
CHECK
24
C589 10U_0603_6.3V6M
C589 10U_0603_6.3V6M
10
C645 0.1U_0402_10V6K
C645 0.1U_0402_10V6K
28 27
SERIRQ
26
LPC_AD0
23
LPC_AD1
22
LPC_FRAME#
20
LPC_AD2
17
LPC_AD3
25 21
CLK_PCI_TPM 19 15
16
PLT_RST#
1 2
R317
R317
10_0402_5%
10_0402_5%
@
@
@
@
1 2 1 2
TPM@
TPM@
TPM@
TPM@
12
R680 0_0402_5%
R680 0_0402_5%
C159
C159
22P_0402_50V8J
22P_0402_50V8J
SERIRQ [13,38] LPC_AD0 [13,37,38] LPC_AD1 [13,37,38] LPC_FRAME# [13,37,38] LPC_AD2 [13,37,38] LPC_AD3 [13,37,38]
CLK_PCI_TPM [17]
PLT_RST# [14,17,23,33,35,37,38]
1 2
@
@
+3VS
Debug Conn.
2
+3VALW+3VS
JDB3
JDB3
1
1
2
2
3
3 LPC_FRAME#[13,37, 38] LPC_AD3[13, 37,38] LPC_AD2[13, 37,38] LPC_AD1[13, 37,38] LPC_AD0[13, 37,38] PLT_RST#[14,17,23,33,35,37,38] CLK_PCI_DB[17] EC_TX_P80_DATA[35,38] EC_RX_P80_CLK[35,38]
LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 PLT_RST#
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
13
11
GND
12
14
12
GND
ACES_85201-1205N
ACES_85201-1205N
CONN@
CONN@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Card Reader CONN.TPM
Card Reader
LOGO LED
FP
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
JCARD1
JCARD1
+3VS
PCIE_PRX_DTX_P1[14] PCIE_PRX_DTX_N1[14]
CLK_PCIE_CARD[14] CLK_PCIE_CARD#[14]
PCIE_PTX_C_DRX_P1[14] PCIE_PTX_C_DRX_N1[14] CARD_CLKREQ#[14] PLT_RST#[14,17,23,33,35,37,38]
+3VALW
LOGO_LED#[30,38] LID_SW1#[38]
+3VLP
USB20_N11[17] USB20_P11[17]
䡢娵
LID 妲嘇,暨18PIN CONN
4
USB20_N11 USB20_P11
Title
Title
Title
PBTN/FAN/TPM/RTC/IO Board
PBTN/FAN/TPM/RTC/IO Board
PBTN/FAN/TPM/RTC/IO Board
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
G1
20
G2
ACES_50208-0180N-P01
ACES_50208-0180N-P01
CONN@
CONN@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-9611P
LA-9611P
LA-9611P
5
37 53Tuesday, February 26, 2013
37 53Tuesday, February 26, 2013
37 53Tuesday, February 26, 2013
0.4
0.4
0.4
1
+3VALW_EC
1 2
L2201 0_0603_5%
L2201 0_0603_5%
1 2
L2202 0_0603_5%
L2202 0_0603_5%
@
@
0.1U_0402_10V6K
0.1U_0402_10V6K
@
@
C2201
C2201
1
2
ECAGND
+EC_AVCC
1
C2202
C2202 1000P_0402_50V7K
1000P_0402_50V7K
@
@
2
EMI
Can't internal pull up
A A
B B
C C
D D
GPIO44 GPIO45 GPIO46 GPIO47 GPIO4A GPIO4B GPIO4E GPIO4F GPIO50 GPIO5B
C2209
C2209 22P_0402_50V8J
22P_0402_50V8J
1 2
+3VALW
1 2
R2225 47K_0402_5%R2225 47K_0402_5%
1 2
R2227 47K_0402_5%R2227 47K_0402_5%
1 2
R2231 2.2K_0402_5%
@
R2231 2.2K_0402_5%
@
1 2
R2232 2.2K_0402_5%
@
R2232 2.2K_0402_5%
@
+3VLP
1 2
R2454 10K_0402_5%R2454 10K_0402_5%
1 2
R2228 2.2K_0402_5%R2228 2.2K_0402_5%
1 2
R2230 2.2K_0402_5%R2230 2.2K_0402_5%
+3VS
1 2
R2452 10K_0402_5%
@
R2452 10K_0402_5%
@
1 2
R2451 10K_0402_5%R2451 10K_0402_5%
1 2
R2236 2.2K_0402_5%R2236 2.2K_0402_5%
1 2
R2237 2.2K_0402_5%R2237 2.2K_0402_5%
1 2
C2220 100P_0402_50V8J@C2220 100P_0402_50V8J@
1 2
C2221 100P_0402_50V8J@C2221 100P_0402_50V8J@
1 2
R2239 10K_0402_5%R2239 10K_0402_5%
1 2
R2229 10M_0402_5%
@
R2229 10M_0402_5%
@
@
@
Y2202
Y2202
1 2
32.768KHZ_12.5PF_CM31532768DZFT
32.768KHZ_12.5PF_CM31532768DZFT
1
C2218
C2218 18P_0402_50V8J
18P_0402_50V8J @
@
2
+3VALW_EC
1 2
R2205 330K_0402_5%R2205 330K_0402_5%
R2201
R2201 10_0402_5%
10_0402_5%
1 2
RF EMI
KSO1
KSO2
EC_SMB_CK1
EC_SMB_DA1
KSI8
EC_SMB_CK1
EC_SMB_DA1
EC_FAN_PWM
EC_TACH
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA2
PCH_PWROK
EC_RTCX1
SUSCLK_R
11/14
1
C2219
C2219 18P_0402_50V8J
18P_0402_50V8J @
@
2
1
CLK_PCI_EC
C2210
C2210
0.1U_0402_10V6K
0.1U_0402_10V6K
for 5 button
+VSB_EN
BOTTOM SIDE
SN111005800 by ME drawing
PWR_RESET[43]
1
2
KSO[0..17][36]
KSI[0..7][36]
SUSCLK[15]
GATEA20[13,18] KB_RST#[13,18] SERIRQ[13,37] LPC_FRAME#[13,37] LPC_AD3[13,37] LPC_AD2[13,37] LPC_AD1[13,37] LPC_AD0[13,37]
CLK_PCI_EC[17] PLT_RST#[14,17,23,33,35,37]
EC_SCI#[18] ADP_65W[41]
KSO[0..17]
KSI[0..7]
+5VALW_DOCK_ON[31]
EC_SMB_CK1[41,42] EC_SMB_DA1[41,42] EC_SMB_CK2[14,24,30,36] EC_SMB_DA2[14,24,30,36]
PM_SLP_S3#[15] PM_SLP_S5#[15] EC_SMI#[14,18]
TP_RESET[36] GS_ON#[34] RF_OFF#[35] KB_LED_PWM[36] EC_TACH[37]
EC_TX_P80_DATA[35,37] EC_RX_P80_CLK[35,37] PCH_PWROK[15] EC_FAN_PWM[37] GS_SELFTEST[34]
1 2
R2221 0_0402_5%@R2221 0_0402_5%@
change 0 ohm
PWR_RESET
C2203
C2203
T6
TPC12T6TPC12
R2223
R2223
100K_0402_5%
100K_0402_5%
2
SW4
SW4
4
SKRBAAE010_4P
SKRBAAE010_4P
2
R310 0_0603_5%@R310 0_0603_5%@
R313 0_0603_5%@R313 0_0603_5%@
C2204
C2204
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
EC_RST# EC_SCI#
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
1
KSO16
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
EC_SMI# KB_LED3
EC_TACH EC_PME# EC_TX_P80_DATA EC_RX_P80_CLK PCH_PWROK EC_FAN_PWM
EC_RTCX1 SUSCLK_R
12
@
@
1
3
2
1 2
1 2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
GND
+3VALW_EC
C2205
1
@
2
1
C2213
C2213 20P_0402_50V8
20P_0402_50V8
@
@
2
EMI
EMI
0.1U_0402_10V6K@C2205
0.1U_0402_10V6K
C2206
0.1U_0402_10V6K@C2206
0.1U_0402_10V6K
C2208
1000P_0402_50V7K@C2208
1000P_0402_50V7K
1
1
@
@
2
2
1
GATEA20/GPIO00
2
KBRST#/GPIO01
3
SERIRQ
4
LPC_FRAME#
5
LPC_AD3
7
LPC_AD2
8
LPC_AD1
10
LPC & MISC
LPC & MISC
LPC_AD0
12
CLK_PCI_EC
13
PCIRST#/GPIO05
37
EC_RST#
20
EC_SCII#/GPIO0E
38
GPIO1D
55
KSI0/GPIO30
56
KSI1/GPIO31
57
KSI2/GPIO32
58
KSI3/GPIO33
59
KSI4/GPIO34
60
KSI5/GPIO35
61
KSI6/GPIO36
62
KSI7/GPIO37
39
KSO0/GPIO20
40
KSO1/GPIO21
41
KSO2/GPIO22
42
KSO3/GPIO23
43
KSO4/GPIO24
44
KSO5/GPIO25
45
KSO6/GPIO26
46
KSO7/GPIO27
47
KSO8/GPIO28
48
KSO9/GPIO29
49
KSO10/GPIO2A
50
KSO11/GPIO2B
51
KSO12/GPIO2C
52
KSO13/GPIO2D
53
KSO14/GPIO2E
54
KSO15/GPIO2F
81
KSO16/GPIO48
82
KSO17/GPIO49
77
EC_SMB_CK1/GPIO44
78
EC_SMB_DA1/GPIO45
79
EC_SMB_CK2/GPIO46
80
EC_SMB_DA2/GPIO47
6
PM_SLP_S3#/GPIO04
14
PM_SLP_S5#/GPIO07
15
EC_SMI#/GPIO08
16
GPIO0A
17
GPIO0B
18
GPIO0C
19
GPIO0D
25
EC_INVT_PWM/GPIO11
28
FAN_SPEED1/GPIO14
29
EC_PME#/GPIO15
30
EC_TX/GPIO16
31
EC_RX/GPIO17
32
PCH_PWROK/ GPIO18
34
SUSP_LED#/GPIO19
36
NUM_LED#/GPIO1A
122
XCLKI/GPIO5D
123
XCLKO/GPIO5E
KB9012QF A4 LQFP 128P_14X 14
KB9012QF A4 LQFP 128P_14X 14
H_PROCHOT#_EC[41]
+3VALW_EC
C2207
1000P_0402_50V7K@C2207
1000P_0402_50V7K
1
2
Int. K/B
Int. K/B Matrix
Matrix
@
9
22
33
EC_VDD/VCC
EC_VDD/VCC
PWM Output
PWM Output
DA Output
DA Output
PS2 Interface
PS2 Interface
SPI Device Interface
SPI Device Interface
SM Bus
SM Bus
GPIO
GPIO
GND/GND
11
24
VR_HOT#
EC_VDD/VCC
GND/GND
+EC_AVCC+3VALW+3VLP
SD034120280 S RES 1/16W 12K +-1% 0402
SD034150280 S RES 1/16W 15K +-1% 0402
SD034200280 S RES 1/16W 20K +-1% 0402
SD034270280 S RES 1/16W 27K +-1% 0402
SD034330280 S RES 1/16W 33K +-1% 0402
67
96
111
125
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
BEEP#/GPIO10
EC_VDD/AVCC
ACOFF/GPIO13
BATT_TEMP/GPIO38
AD Input
AD Input
DAC_BRIG/GPI O3C
EN_DFAN1/GPIO3D
CHGVADJ/GPIO 3F
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
TP_CLK/GPIO4E
TP_DATA/GPIO4F
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA 01 HDA_SDO/GPXIO A02 VCIN0_PH/GPXIOD00
SPI Flash ROM
SPI Flash ROM
GPIO
GPIO
GND/GND
35
94
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GP IO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPI O55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXI OA06
VCOUT0_PH/GPXIOA07
GPO
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
GPI
LID_SW#/GPXI OD04
SUSP#/GPXIOD05
PECI_KB9012/GPXIOD07
AGND/AGND
GND/GND
GND0
69
113
ECAGND
@
@
1 2
R2233 0_0402_5%
R2233 0_0402_5%
2
G
G
U2201
U2201
GPIO0F
GPIO12
GPIO39
ADP_I/GPIO3A
GPIO3B GPIO42
IMON/GPIO43
IREF/GPIO3E
EAPD/GPIO4D
SPIDI/GPIO5B
GPXIOD06
V18R
13
D
D
Q2202
Q2202 2N7002K_SOT23-3
2N7002K_SOT23-3
S
S
3
100K_0402_1%
100K_0402_1%
BRDID
20K_0402_1%
20K_0402_1%
EC
天㯪枰㓡䁢
21 23
BEEP# 26 27
ACOFF
63
BATT_TEMP 64 65 66 75
BRDID 76
68 70 71 72
83
EC_MUTE# 84
USB_ON# NTC_V 85 86 87
TP_CLK 88
TP_DATA
97 98 99 109
NTC_V
119 120
LID_SW# 126
BYPASS 128
KB_LED2
73 74 89 90 91 92 93 95
SYSON 121 127
100 101
EC_WAKE# 102 103
H_PROCHOT#_EC 104
MAINPW ON_R 105
BKOFF# 106
PBTN_OUT# 107 108
SA_PGOOD
110
ACIN 112 114
ON/OFF 115 116
SUSP# 117
KB_LED1 118
EC_PECI
124
+V18R
C2214
C2214
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
ECAGND [41]
LOGO_LED# [30,37] BEEP# [32] WLAN_WAKE# [35] ACOFF [42]
BATT_TEMP [41] GS_VOUTX [34] ADP_I [41,42] GS_VOUTY [34]
IMVP_IMON [48]
AOU_CTL2 [35] EC_FAN_ID [37] AOU_CTL3 [35] AOAC_WLAN# [35]
EC_MUTE# [32] USB_ON# [37] KB_LED_DET# [36] DGPU_PWROK [18,47] TP_CLK [36] TP_DATA [36]
PTC_PROTECT [41] VGA_AC_DET [24,47] ME_FLASH [13] NTC_V [41]
mSATA_DETEC# [34] LID_SW# [37]
BYPASS [36]
ENBKL [16] ADP_ID [40] KSI8 [36] AOU_EN [35] ADP_90W [41] HDD_DETECT# [34] CP_RESET# [36] SYSON [44] VR_ON [48] PM_SLP_S4# [15]
EC_RSMRST# [15] EC_WAKE# [18] Turbo_V [41]
BKOFF# [30] PBTN_OUT# [15] EN_5V [43] SA_PGOOD [45]
ACIN [15,42] EN_3V [43] ON/OFF [37] LID_SW1# [37] SUSP# [10,25,39,44,46,47]
1
2
1%
For LCD thermal
for 5 button
R2215 0_0402_5%@R2215 0_0402_5%@
LCD on/off
R2245 43_0402_1%R2245 43_0402_1%
+3VALW
R2210
R2210
R2213
R2213
1 2
1 2
4
12
12
Vcc R2210
Board ID
0 1 2 3 4 5
3.3V +/- 5%
100K +/- 1%
R2213
0K +/- 5%
12K +/- 5%
15K +/- 5%
20K +/- 5%
27K +/- 5%
33K +/- 5%
MAINPWON [36,43]
H_PECI [18,6]
add resister
Deciphered Date
Deciphered Date
Deciphered Date
4
12 12 12
KB_LED1_FN [36] KB_LED2_F1 [36] KB_LED3_F4 [36]
KB_LED1
R2234 100_0402_1%R2234 100_0402_1%
KB_LED2
R2235 150_0402_1%R2235 150_0402_1%
KB_LED3
H_PROCHOT# [6]VR_HOT#[48]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
R2238 100_0402_1%R2238 100_0402_1%
Compal Secret Data
Compal Secret Data
Compal Secret Data
5
min
VV
AD_BID
0 V
0.423 V 0.430 V
0.541 V
0.691 V 0.702 V 0.713 V
0.807 V
LCD for thermal
LID_SW#
LID_SW1#
LED on/off
Turbo_V
NTC_V
BATT_TEMP
Turbo_V
ADP_65W
ADP_90W
EC_MUTE#
HDD_DETECT#
mSATA_DETEC#
HDD_DETECT#
mSATA_DETEC#
USB_ON#
TP_CLK
TP_DATA
TP_CLK
TP_DATA
+3VALW
EC_PME#
2N7002K_SOT23-3
2N7002K_SOT23-3
Title
Title
Title
EC ENE-KB9012
EC ENE-KB9012
EC ENE-KB9012
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
typ
V
AD_BID
0 V 0 V
0.354 V
0.550 V
0.819 V
R2203 100K_0402_5%R2203 100K_0402_5%
R2208 100K_0402_5%R2208 100K_0402_5%
R2218 10K_0402_5%
R2218 10K_0402_5%
R2219 10K_0402_5%
R2219 10K_0402_5%
R2240 10K_0402_5%
R2240 10K_0402_5%
R2217 47K_0402_5%
R2217 47K_0402_5%
R2206 10K_0402_5%
R2206 10K_0402_5%
R2207 10K_0402_5%R2207 10K_0402_5%
R2214 10K_0402_5%R2214 10K_0402_5%
R2202 10K_0402_5%R2202 10K_0402_5%
R2204 100K_0402_5%R2204 100K_0402_5%
R2242 10K_0402_5%R2242 10K_0402_5%
R2246 100K_0402_5%
R2246 100K_0402_5%
R2244 10K_0402_5%
R2244 10K_0402_5%
R2209 10K_0402_5%
R2209 10K_0402_5%
R2211 4.7K_0402_5%R2211 4.7K_0402_5%
R2212 4.7K_0402_5%R2212 4.7K_0402_5%
R2216 4.7K_0402_5%
R2216 4.7K_0402_5%
R2241 4.7K_0402_5%
R2241 4.7K_0402_5%
12
R2220
R2220 10K_0402_5%
10K_0402_5%
1 2
R2222 0_0402_5%
R2222 0_0402_5%
1 2
R2224 0_0402_5%
R2224 0_0402_5%
1 3
Q2203
Q2203
@
@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
AD_BID
0.360 V0.347 V
0.438 V
0.559 V
0.831 V
1 2
1 2
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
1 2
1 2
1 2
1 2
1 2
@
@
1 2
@
@
1 2
@
@
1 2
1 2
1 2
@
@
1 2
@
@
@
@
@
@
D
S
D
S
+3VALW
G
G
2
LA-9611P
LA-9611P
LA-9611P
5
+3VALW_EC
+3VLP
+3VALW
+3VALW_EC
+5VALW
+5VS
+3VS
(EC_PME#)
LAN_WAKE# [33]
PCI_PME# [17]
38 53Tuesday, February 26, 2013
38 53Tuesday, February 26, 2013
38 53Tuesday, February 26, 2013
Phasemax SDV FVT SIT SVT
0.4
0.4
0.4
1
нϱs>tdKнϱs^ нϯs>tdKнϯs^
R2313
R2313
1 2
200K_0402_5%
SUSP#[10,25,38,39,44,46,47]
A A
10mil
R2318
R2318
1 2
C2322
C2322
0.01U_0402_16V7K
0.01U_0402_16V7K
200K_0402_5%
470K_0402_5%
470K_0402_5%
1
2
+5VALW
U2301
U2301
1
VIN1
2
VIN1
C2316
C2316
1
2
+5VALW
10U_0603_6.3V6M
10U_0603_6.3V6M
+3VALW
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
C2318
10U_0603_6.3V6M@C2318
10U_0603_6.3V6M
1
@
2
C2306
C2306
1
2
5VS_GATE
3VS_GATE
1
+3VALW
C2309
C2309
0.01U_0402_16V7K
0.01U_0402_16V7K
2
нϭϱsƚŽнϭϱs^
B B
U2303
U2303
AP2301GN-HF_SOT23-3
AP2301GN-HF_SOT23-3
3 1
C2317
0.1U_0402_10V6K
C2317
0.1U_0402_10V6K
C2315
10U_0603_6.3V6M
C2315
10U_0603_6.3V6M
1
+3VALW
1 2
R2312 100K_0402_5%R2312 100K_0402_5%
20mil
SUSP#[10,25, 38,39,44,46,47]
SUSP#
Q2306
Q2306 2N7002K_SOT23-3
2N7002K_SOT23-3
12
2
2
G
G
13
D
D
S
S
R2322
R2322
1 2
@
@
0_0402_5%
0_0402_5%
2
1.5VS_GATE
10mil
C2321
C2321
12
2
J510
J510
2
5VS
JUMP_43X79@
14
VOUT1
13
VOUT1
12
CT1
11
GND
10
CT2
9
VOUT2
8
VOUT2
15
GPAD
+5VALW
C2305
10U_0603_6.3V6M@C2305
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
@
2
+1.5VS+1.5V
C2320
1U_0402_6.3V6K
C2320
1U_0402_6.3V6K
C2319
10U_0603_6.3V6M
C2319
10U_0603_6.3V6M
1
1
2
2
JUMP_43X79@
10U_0603_6.3V6M
10U_0603_6.3V6M
C2325
3VS
@
J511
J511
2
JUMP_43X79@
JUMP_43X79@
12
R2311
R2311 470_0603_5%
470_0603_5% @
@
+5VS
112
C2307
C2307
C2326
1U_0402_6.3V6K@C2325
1U_0402_6.3V6K
@
1
1
2
2
112
C2308
10U_0603_6.3V6M
C2308
10U_0603_6.3V6M
1
+3VS
@
2
C2324
1
2
C2323
10U_0603_6.3V6M
C2323
10U_0603_6.3V6M
10U_0603_6.3V6M@C2324
10U_0603_6.3V6M
1
1
2
2
@
@
1U_0402_6.3V6K@C2326
1U_0402_6.3V6K
3
4
5
PU502
+1.8VS
PU1202
+0.95VS_VGA
PU501
+0.75VS
B+
PU401
+3VALW
+5VALW
PU501
+1.5VP
PU701
+1.05VS
U2301
+3VS
+5VS
U2303
+1.5VS
PU601
+VCCSA
PU901
0.1U_0402_10V6K
0.1U_0402_10V6K
13
D
D
G
G
S
S
2N7002K_SOT23-3
2N7002K_SOT23-3 @
@
2
SUSP
Q2311
Q2311
+CPU_CORE
+GPU_CORE
C C
+5VALW
VL
нϯs>tdKнϯs>t;W,hyWŽǁĞƌͿ
Short J2301 for PCH VCCSUS3.3
+3V_PCH+3VALW
40mil40mil
@ R2308
@
100K_0402_5%
100K_0402_5%
H
SUSP
R2306
R2306 10K_0402_5%
10K_0402_5%
SUSP[6]
SUSP#[10,25,38,39,44,46,47]
R2308
12
12
R2303
R2303 100K_0402_5%
100K_0402_5%
L
13
D
D
2
Q2302
Q2302 2N7002K_SOT23-3
2N7002K_SOT23-3
G
G
S
S
12
PU801
+VGA_CORE
&Žƌ/ŶƚĞů^ϯWŽǁĞƌZĞĚƵĐƚŝŽŶ
+1.8VS+0.75VS +1.05VS
D D
12
13
D
D
S
S
R2314
R2314 22_0603_5%
22_0603_5% @
@
2
G
G
Q2307
Q2307 2N7002K_SOT23-3
2N7002K_SOT23-3 @
@
1
12
13
D
D
S
S
R2315
R2315 470_0603_5%
470_0603_5% @
@
2
G
G
Q2308
Q2308 2N7002K_SOT23-3
2N7002K_SOT23-3 @
@
12
13
D
D
S
S
R2316
R2316 470_0603_5%
470_0603_5% @
@
2
G
G
Q2309
Q2309 2N7002K_SOT23-3
2N7002K_SOT23-3 @
@
+5VS
12
R2317
R2317 470_0603_5%
470_0603_5%
13
D
D
SUSPSUSP SUSP
S
S
2
2
G
G
Q2310
Q2310 2N7002K_SOT23-3
2N7002K_SOT23-3
+3VS
12
R2319
R2319 470_0603_5%
470_0603_5%
13
D
D
SUSP SUSP
S
S
2
G
G
Q2312
Q2312 2N7002K_SOT23-3
2N7002K_SOT23-3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DC Interface
DC Interface
DC Interface
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9611P
LA-9611P
LA-9611P
5
39 53Tuesday, February 26, 2013
39 53Tuesday, February 26, 2013
39 53Tuesday, February 26, 2013
0.4
0.4
0.4
5
4
3
2
1
VIN
21
Adap+
ADP_I D_Dok[31]
D D
PR106
PR106
750_0402_1%
750_0402_1%
+3VALW
1 2
APDIN1
PF101
PF101
7A_24VDC_429007.WRML
7A_24VDC_429007.WRML
PR101
PR101
1 2
0_0402_5%
0_0402_5%
12
1 2
PL101
PL101
12
SMB3025500YA_2P
SMB3025500YA_2P
PC102
PC102
PC101
PC101
100P_0603_50V8
100P_0603_50V8
1000P_0603_50V7
1000P_0603_50V7
12
12
PC107
PC107
@
@
@
@
.1U_0402_16V7K
.1U_0402_16V7K
A/D
PC108
PC108
680P_0603_50V7K
680P_0603_50V7K
ADP_ID [38]
12
12
PC103
PC103
PC104
PC104
100P_0603_50V8
100P_0603_50V8
1000P_0603_50V7
1000P_0603_50V7
ADP_ID
AC Adapter 45W 65W 90W 135W
R(ohm) 118 287 549 1000 ADP_ID(V) 0.449 0.913 1.395 1.886
Detection <=0.663, <=1.134, <=1.618, <=2.109,
-Voltage(V) >0.234 >0.693 >1.172 >1.663
+CHGRTC
@
PR111
PR111
1K_0603_5%
1K_0603_5% 1 2
PR112 0_0603_5%
PD103
PD103
C C
+RTCBATT
2
1
3
S SCH DIO BAS40CW SOT-323
S SCH DIO BAS40CW SOT-323
1 2
1K_0402_5%
1K_0402_5%
PR113
PR113
PR112 0_0603_5%
JRTC1
JRTC1
1
1
2
2
3
GND
4
GND
ACES_50271-0020N-001
ACES_50271-0020N-001
@
@
@
1 2
+3VLP
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/01/25 2010/12/31
2010/01/25 2010/12/31
2010/01/25 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
PWR DCIN
PWR DCIN
PWR DCIN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
VIUS1
Date: Sheet
Date: Sheet
2
Date: Sheet
1
40 53Tuesday, February 26, 2013
40 53Tuesday, February 26, 2013
40 53Tuesday, February 26, 2013
0.4
0.4
0.4
of
of
of
5
4
3
2
1
Rsistance between Turbo_V and ECAGND:
JBATT1
JBATT1
D D
GND GND
ACES_51202-00901-001
ACES_51202-00901-001
@
@
VMB2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11
EC_SMCA EC_SMDA
12
PR201
PR201
12
100_0402_1%
100_0402_1%
PR202
PR202
100_0402_1%
100_0402_1%
PF201
PF201 12A_65V_451012MRL
12A_65V_451012MRL
21
VMB
12
PL201
PL201
SMB3025500YA_2P
SMB3025500YA_2P
1 2
PC201
PC201
1000P_0603_50V7
1000P_0603_50V7
45 W: 10K (Default)
BATT+
12
PC202
PC202
0.01U_0603_25V7K
0.01U_0603_25V7K
65 W: 4.4K (ADP_65W to High,ADP_90W to Low) 90 W: 2.27K (ADP_90W to High,ADP_65W to Low)
Trigger Power:
45 W ĺ 55 W ĺ ADP_I:1.65 65 W ĺ 74 W ĺ ADP_I:2.22 90 W ĺ 106 W ĺ ADP_I:3.18
PH201 under CPU botten side :
EC_SMB_CK1 [38,42]
EC_SMB_DA1 [38,42]
1 2
PR203
PR203
6.49K_0402_1%
6.49K_0402_1%
1 2
PR205
PR205 10K_0402_5%
10K_0402_5%
C C
VMB2
PR214
PR214 768K_0402_1%
768K_0402_1%
1000P_0402_25V8J
1000P_0402_25V8J
B B
1 2
TMSNS1
@
@
1
12
PC205
PC205
PR217
2
@
@
PR217
90.9K_0402_1%
90.9K_0402_1%
@
@
PR212
PR212 100K_0402_1%
100K_0402_1%
1 2
@
@
2N7002KW_SOT323-3
2N7002KW_SOT323-3
@
@
12
+3VALW+3VLP
@
@
1 2
PQ201
PQ201
13
D
D
2
OT1
G
G
S
S
@
@
PC206
PC206
0.1U_0603_25V7K
0.1U_0603_25V7K
PR213
PR213 100K_0402_1%
100K_0402_1%
+3VALW
BATT_TEMP [38]
12
A/D
BATT_OUT [42]
PC204
PC204
@
@
0.1U_0603_25V7K
0.1U_0603_25V7K
VL
1 2
PC207
PC207
.1U_0603_25V7K
.1U_0603_25V7K
1 2
PR221
PR221 0_0402_5%
0_0402_5%
PTC_PROTECT[38]
PU201
PU201
1
VCC
TMSNS1
2
GND
RHYST1
3
OT1
TMSNS2
4
RHYST2
OT2
G718TM1U_SOT23-8
G718TM1U_SOT23-8
8
7
6
5
ADP_I[38,42]
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
TMSNS1
TMSNS2OT1
PQ204A
PQ204A
12
PR206
PR206
3.74K_0402_1%
3.74K_0402_1%
ADP_90W[38]
PR209
PR209
2.94K_0402_1%
2.94K_0402_1%
2
12
61
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
12
ADP_65W[38]
PR208
PR208
7.87K_0402_1%
7.87K_0402_1%
34
PQ204B
PQ204B
5
PR210
PR210
PR211
PR211
1 2
1 2
@
@
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
H_PROCHOT#_EC [38]
ECAGND[38,41]
PH201:
Temp. Rman. Rnor. Rmin. (Kohm)
93 7.3419 7.0792 6.8253
CPU thermal protection at 100 degree C
+EC_AVCC
Turbo_V [38]
12
PR207
PR207
12
PH201
PH201
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
ECAGND[38,41]
10K_0402_1%
10K_0402_1%
NTC_V [38]
Posestor
+3VLP
PR1209
PR1205
PR1203
1 2
1K_0402_50%
1K_0402_50%
PR1208
A A
PR1208
1 2
1K_0402_50%
1K_0402_50%
1 2
1K_0402_50%
1K_0402_50%
1 2
PR1210
PR1210
1 2
1K_0402_50%
1K_0402_50%
5
1K_0402_50%
1K_0402_50%
PR1211
PR1211
1 2
1K_0402_50%
1K_0402_50%
1 2
PR1205
PR1204
PR1204
PR1203
PR1206
PR1206
1K_0402_50%
1K_0402_50%
PR1207
PR1207
1 2
1K_0402_50%
1K_0402_50%
TMSNS2
PR1209
1 2
316K_0402_1%
316K_0402_1%
VL
4
12
PR1202
PR1202
100K_0402_1%
100K_0402_1%
PQ203
PQ203
2N7002KW_SOT323-3
2N7002KW_SOT323-3
PTC_PROTECT
2
G
G
PR1201
PR1201 100K_0402_1%
100K_0402_1%
1 2
13
D
D
S
S
MOS_OTP [43]
MOS_OTP: Default:High Active :Low
PTC_PROTECT: Default:Low Active :High
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/01/25 2010/12/31
2010/01/25 2010/12/31
2010/01/25 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Title
Title
Title
PWR-BATTERY CONN/OTP
PWR-BATTERY CONN/OTP
PWR-BATTERY CONN/OTP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
VIUS1
of
41 53Tuesday, Febr uary 26, 2013
of
41 53Tuesday, Febr uary 26, 2013
of
41 53Tuesday, Febr uary 26, 2013
1
0.4
0.4
0.4
5
DCR
㎃㎃㎃㎃ㆸㆸㆸㆸ
15m ohm,CP,Throttling....need redefine with EC
PQ301
PQ301 AO4407A_SO8
AO4407A_SO8
VIN
D D
C C
B B
A A
12
PR301
PR301
V1
61
2
ACOFF[38]
VIN
8 7
5
PQ306
PQ306
DTA144EUA_SC70-3
DTA144EUA_SC70-3
47K_0402_5%
47K_0402_5%
2
13
2
PQ310A
PQ310A
2N7002KDW-2N_S OT363-6
2N7002KDW-2N_S OT363-6
PD301
PD301
1SS355_SOD323-2
1SS355_SOD323-2
PD303
PD303
DTC115EUA_SC70-3
DTC115EUA_SC70-3
47K_0402_1%
47K_0402_1%
1 2
PACIN
PQ318
PQ318
DTC115EUA_SC70-3
DTC115EUA_SC70-3
12
1 2
S DIO GLZ22B LL-34
S DIO GLZ22B LL-34
PQ307
PQ307
PR320
PR320
1 3
PACIN_2
2
ACOFF-1
ACOFF-1
P2
1 2 36
4
12
12
PR305
PR305
PC301
PC301
0.1U_0603_25V7K
0.1U_0603_25V7K
P2-1
12
P2-2
34
PQ310B
PQ310B
5
13
AO4423L SO8
AO4423L SO8 1 2 3 6
200K_0402_1%
200K_0402_1%
PR313
PR313
150K_0402_1%
150K_0402_1%
PR318
PR318
1 2
59K_0402_1%
59K_0402_1%
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
PQ304
PQ304
4
5600P_0402_25V7K
5600P_0402_25V7K
PR316
PR316
EC_SMB_DA1[38,41]
EC_SMB_CK1[38,41]
8 7
5
1 2
PC304
PC304
VIN
12
392K_0402_1%
392K_0402_1%
12
PC314
PC314
0.1U_0603_25V7K
0.1U_0603_25V7K
4
P3
1UH_PCMB061H-1R0MS_7A_20%
1UH_PCMB061H-1R0MS_7A_20%
1 2
1 2
PC305
PC305
10U_0805_25V6K
10U_0805_25V6K
ADP_I[38,41]
PR325
PR325 1 2 316K_0402_1%
316K_0402_1%
+3VALW
118K_0402_1%
118K_0402_1%
0.015_1206_1%
PL301
PL301
@
@
0.015_1206_1%
1
2
1 2
PC302
PC302
10U_0805_25V6K
10U_0805_25V6K
PR315
PR315
1 2
Lenovo request
ACPRN
6
ACDET
PC316
PC316
1 2
7
PR330
PR330
IOUT
8
SDA
BQ24737RGRR_VQFN20_3P5X3P5
BQ24737RGRR_VQFN20_3P5X3P5
9
SCL
10
12
ILIM
12
PQ316
PQ316
2
G
G
BQ24727VDD
100P_0603_50V8
100P_0603_50V8
PR326
PR326
47K_0402_1%
47K_0402_1%
ACPRN
SH00000AA00
PR302
PR302
4
3
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
PR314
PR314
1 2
ACP
PC310
PC310
1 2
0.1U_0402_25V6
0.1U_0402_25V6
3
5
4
ACOK
CMPIN
CMPOUT
PU301
PU301
SA000051W00
SRN
BM
SRP
12
13
11
12
12
PR328
PR328
PR327
PR327
10_0402_5%
10_0402_5%
6.8_0402_5%
6.8_0402_5%
PC322
PC322
1 2
0.1U_0402_25V6
0.1U_0402_25V6
12
PC323
PC323
0.1U_0402_25V6
0.1U_0402_25V6
12
PR331
PR331 10K_0402_1%
10K_0402_1%
13
D
D
S
S
ACN
1 2
0.1U_0402_25V6
0.1U_0402_25V6
2
ACP
GND
14
PR332
PR332
10K_0402_1%
10K_0402_1%
1 2
PACIN
12
PR334
PR334
12K_0402_1%
12K_0402_1%
3
PR329
1 2
10_0402_1%
10_0402_1%
1 2
PC312
PC312
1
ACN
TP
VCC
PHASE
HIDRV
BTST
REGN
LODRV
15
B+
1 2
PC306
PC306
@P R329
@
PC311
PC311
0.1U_0402_25V6
0.1U_0402_25V6
21
20
19
18
17
16
12
PC324
PC324
@
@
0.1U_0402_25V6
0.1U_0402_25V6
1 2
PC307
PC307
10U_0805_25V6K
10U_0805_25V6K
BST_CHG
PD302
PD302
2 1
RB751V40_SC76-2
RB751V40_SC76-2
12
PC321
PC321 1U_0603_16V6K
1U_0603_16V6K
ACIN [15,38]
PC309
PC309
1 2
1 2
10U_0805_25V6K
10U_0805_25V6K
PC308
PC308
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@
@
DOCK_CONSUMP [31]
P2
PR319
PR319
10_1206_5%
10_1206_5%
1 2
PC315
PC315
1 2
1U_0603_25V6K
1U_0603_25V6K
DH_CHG
PR323
PR323
2.2_0603_5%
2.2_0603_5% 1 2
DL_CHG
2200P_0402_50V7K
2200P_0402_50V7K
LX_CHG
0.047U_0603_16V7K
0.047U_0603_16V7K
BQ24727VDD
PQ309
PQ309
DTC115EUA_SC70-3
DTC115EUA_SC70-3
1 2
0_0603_5%
0_0603_5%
PC317
PC317
12
PR335
PR335
2
PR308
PR308
1 2
13
1 2 3 6
PR311
PR311
200K_0402_1%
200K_0402_1%
47K_0402_5%
47K_0402_5%
2
6
578
4
6
578
4
PQ302
PQ302
AO4407A_SO8
AO4407A_SO8
12
123
123
8 7
5
4
VIN
PC313
PC313
PQ313
PQ313
AO4466L_SO8
AO4466L_SO8
10UH +-20% PCMB104T-100MS 6A
10UH +-20% PCMB104T-100MS 6A
12
@
@
PQ314
PQ314
AO4466L_SO8
AO4466L_SO8
6251_SN 12
@
@
V1
D
D
12
S
S
0.1U_0603_25V7K
0.1U_0603_25V7K
PL302
PL302
1 2
PR324
PR324
4.7_1206_5%
4.7_1206_5%
PC319
PC319
680P_0603_50V7K
680P_0603_50V7K
PR310
PR310 200K_0402_1%
200K_0402_1%
1 2
PQ311
PQ311
13
G
G
2
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
PJ301
PJ301
2
JUMP_43X118@
JUMP_43X118@
AO4423L SO8
AO4423L SO8 8 7
5
PC303
PC303
12
@
@
2200P_0402_50V7K
2200P_0402_50V7K
PACIN_2 2N7002KDW-2N_S OT363-6
2N7002KDW-2N_S OT363-6
2N7002KDW-2N_S OT363-6
2N7002KDW-2N_S OT363-6
PR321
PR321
0.01_1206_1%
0.01_1206_1%
CHGCHG
1
2
SRP
4
3
SRN
1
PQ303
PQ303
PQ312A
PQ312A
112
4
12
@
@
@
@
1 2 36
@
@
@
@
1 2
PR309
PR309
100K_0402_1%
100K_0402_1%
61
PQ312B
PQ312B
BATT_OUT[41]
12
PC318
PC318
10U_0805_25V6K
10U_0805_25V6K
BATT+
PR306
PR306 100K_0402_1%
100K_0402_1%
PR312
PR312
1 2
@
@
2
34
@
@
BA+
12
PC320
PC320
10U_0805_25V6K
10U_0805_25V6K
100K_0402_1%
100K_0402_1%
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
5
4
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2013/10/122011/ 10/12
2013/10/122011/ 10/12
2013/10/122011/ 10/12
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
CHARGER
VIUS1
42 53Tuesday, February 26, 2013
42 53Tuesday, February 26, 2013
42 53Tuesday, February 26, 2013
1
0.4
0.4
0.4
of
of
of
A
B
C
D
E
PC403
PC403
@
1 1
RT8243_B+
PL400
PL400
B+
1 2
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
12
PC423
PC423
68P_0402_50V8J
68P_0402_50V8J
@
@
2 2
PQ405A
3 3
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
PQ405A
61
PC401
PC401
0.1U_0402_25V6
0.1U_0402_25V6 @
@
12
PC404
PC404
10U_0805_25V6K
10U_0805_25V6K
+3VALWP
2
12
12
12
PC422
PC422
PC405
PC405
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
2200P_0402_50V7K
4.7UH_PCMB063T-4R7MS_5.5A_20%
4.7UH_PCMB063T-4R7MS_5.5A_20%
1
+
+
2
1 2
PC412
PC412
150U_B2_6.3VM_R45M
150U_B2_6.3VM_R45M
PL401
PL401
5
AO4466L_SO8
AO4466L_SO8
ENTRIP2-1ENTRIP1-1
34
6
578
PQ401
PQ401
123
12
578
PQ403
3 6
241
PQ403 AO4712L_SO8
AO4712L_SO8
PR401 @ PR401
@
4.7_1206_5%
4.7_1206_5%
12
PC414
PC414
@
@
680P_0603_25V8J
680P_0603_25V8J
PQ405B
PQ405B 2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
4
RT8243_B+
1 2
BST_3V_1
PC408
PC408
0.1U_0603_50V_X7R
0.1U_0603_50V_X7R
1 2
PWR_RESET[38]
@
100P_0402_50V8J
100P_0402_50V8J
1 2
PR403
PR403
14K_0402_1%
14K_0402_1%
1 2
PR405
PR405
21.5K_0402_1%
21.5K_0402_1% 1 2
PR410
PR410
1 2
BST_3V
2.2_0603_5%
2.2_0603_5%
UG_3V
LX_3V
10
LG_3V
PC415
PC415
0.1U_0603_50V_X7R
0.1U_0603_50V_X7R
EN Rising=1.2-1.6- 2V Falling0.9-0.95- 1V
PR413
PR413
499K_0402_1%
499K_0402_1%
PR415
PR415
0_0402_5%
0_0402_5%
12
RT8243_B+
12
12
PU401
PU401
6
7
8
9
FB_3V
PGOOD
BOOT2
UGATE2
PHASE2
LGATE2
PR418
PR418
100K_0402_1%
100K_0402_1%
12
PR402
PR402
71.5K_0402_1%
71.5K_0402_1%
3V5V_TON
12
PR407
PR407
124K_0402_1%
124K_0402_1%
ENTRIP2 ENTRIP2-1
3
5
4
FB2
TON
ENTRIP2
RT8243AZQW_WQFN20_3X3
RT8243AZQW_WQFN20_3X3
VIN11ENLDO12ENM13LDO514LDO3
ENABLE
3V5V_ENLDO
12
PC419
PC419
12
1U_0402_16V6K
1U_0402_16V6K
PR416
PR416
@
@
ENTRIP1-1
PR408
PR408
1 2
ENTRIP1
1
2
ENTRIP1
15
12
PC417
PC417
0_0402_5%
0_0402_5%
PC402
PC402
@
@
100P_0402_50V8J
100P_0402_50V8J
1 2
FB_5V
PR404
PR404
30K_0402_1%
30K_0402_1%
1 2
20K_0402_1%
20K_0402_1% 1 2
64.9K_0402_1%
64.9K_0402_1%
FB1
PAD
BYP1
BOOT1
UGATE1
PHASE1
LGATE1
+3VLP
1 2
VL
Typ: 175mA
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PR420
PR420
0_0402_5%
0_0402_5%
PR406
PR406
21
20
2.2_0603_5%
2.2_0603_5%
1 2
19
BST_5V
18
UG_5V
17
LX_5V
16
LG_5V
Typ: 175mA
PC416
PC416
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0_0402_5%
0_0402_5%
PR417
PR417
12
12
RT8243_B+
12
12
PC407
PC407
PC406
PC406
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PR411
PR411
PC411
PC411
0.1U_0603_50V_X7R
0.1U_0603_50V_X7R
1 2
BST_5V_1
MAINPWON [36,38]
MOS_OTP [41]
12
PC409
PC409
2200P_0402_50V7K
2200P_0402_50V7K
@
@
12
12
PC410
PC410
PC424
PC424
0.1U_0402_25V6
0.1U_0402_25V6
68P_0402_50V8J
68P_0402_50V8J
@
@
@
@
PQ404
PQ404
SI4634DY-T1-GE3_SO8
SI4634DY-T1-GE3_SO8
678
PQ402
PQ402
SI4172DY-T1-GE3_SO8
SI4172DY-T1-GE3_SO8
35241
578
3 6
241
TON (1)SMPS1=305KHZ (+5VALWP) (2)SMPS2=357KHZ(+3VALWP)
PL402
PL402
4.7UH_PCMB063T-4R7MS_5.5A_20%
4.7UH_PCMB063T-4R7MS_5.5A_20% 1 2
LX_5V
12
@
@
PR412
PR412
4.7_1206_5%
4.7_1206_5%
SNUB_5V
12
PC418
PC418
@
@
680P_0603_25V8J
680P_0603_25V8J
1
+
+
2
+5VALWP
PC413
PC413 150U_B2_6.3VM_R45M
150U_B2_6.3VM_R45M
+3.3VALWP Ipeak=6.4A ; 1.2Ipeak=6.72A; Imax=3.92A f=375KHz, L=4.7UH Rdson=13.5~16.5m ohm 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=1.48/2=0.74A
PD401
PD401
1 2
S SCH DIO RB751V40 SC76
S SCH DIO RB751V40 SC76
PR419
EN_5V[38]
4 4
PR419
2.2K_0402_5%
2.2K_0402_5%
12
12
12
PC421
PC421
402K_0402_1%
402K_0402_1%
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M @
@
@
@
A
12
PR422
PR422
PR423
PR423
402K_0402_1%
402K_0402_1%
@
@
2012/10/19 check the EN circuit
PD402
PD402
1 2
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
@
@
12
PR421
PR421
2.2K_0402_5%
2.2K_0402_5%
S SCH DIO RB751V40 SC76
S SCH DIO RB751V40 SC76
12
PC425
PC425
B
Vlimit=10*10^-6*150Kohm/10=0.15V Ilimit=0.15/(16m*1.2)~0.15/(13m)=7.82A~11.53A Iocp=7.7A (8.536A>8.4A -> ok)
EN_3V [38]
+5VALWP Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A f=300KHz, L=1UH,Rentrip=64.9k ohm Rdson=4.1~5.2m ohm 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*1UH)=6A Vlimit=10*10^-6*64.9Kohm/10=0.0649V Ilimit=0.0649/(5.2m*1.2)~0.0649/(4.1m)=10~13A Iocp=16~19A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
2011/10/03 2014/12/31
2011/10/03 2014/12/31
2011/10/03 2014/12/31
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
+3VALWP
+5VALWP
Custom
Custom
Custom
@
@
PJ402
PJ402
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m PJ403
PJ403
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
@
@
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PWR- 3VALWP/5VALWP
PWR- 3VALWP/5VALWP
PWR- 3VALWP/5VALWP
VIUS1
+3VALW
+5VALW
E
of
43 53Tuesday, Febr uary 26, 2013
of
43 53Tuesday, Febr uary 26, 2013
of
43 53Tuesday, Febr uary 26, 2013
0.4
0.4
0.4
A
B
C
D
PJ502
PJ502
2
220P_0402_50V8J
220P_0402_50V8J
1 2
PR505
PR505
5.9K_0402_1%
5.9K_0402_1% 1 2
PR508
PR508
5.76K_0402_1%
5.76K_0402_1%
+1.5VP
PC512
PC512
VTTREF_1.5V
+1.5VP
@
@
20
PU501
PU501
VTT
VTTGND
VTTSNS
GND
VTTREF
VDDQ
FB
6
PAD
1.5V_FB
112
JUMP_43X39
JUMP_43X39 @
@
21
1
2
3
4
5
12
PL500
B+
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 1
+1.5VP
2 2
1.5VP TDC A Peak Current 11.027 A OCP current 13.36~18.27 A TYP MAX H/S Rds(on) :11.7mohm , 14.5mohm L/S Rds(on) :2.6mohm ,3.2mohm
PL500
1 2
PC501
PC501 330U_D2_2.5VY_R15M
330U_D2_2.5VY_R15M
12
12
PC524
PC524
68P_0402_50V8J
68P_0402_50V8J
@
@
1UH_PCMB063T-1R0MS_12A_20%
1UH_PCMB063T-1R0MS_12A_20%
PL501
PL501
1 2
@
@
1
12
+
+
PC510
PC510
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1.5V_B+
PC503
PC503
PR502
PR502
1 2
2.2_0603_5%
2.2_0603_5%
12
PC504
PC504
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7_1206_5%
4.7_1206_5%
680P_0603_50V7K
680P_0603_50V7K
12
12
PC505
PC505
0.1U_0402_25V6
0.1U_0402_25V6
@
@
SI4172DY-T1-GE3_SO8
SI4172DY-T1-GE3_SO8
12
PR501
PR501
@
@
SNUB_1.5V
12
@
@
PC513
PC513
SYSON[38]
PC506
PC506
2200P_0402_50V7K
2200P_0402_50V7K
PQ501
PQ501
PR507
PR507
1 2
0_0402_5%
0_0402_5%
678
35241
578
SI4634DY-T1-GE3_SO8
SI4634DY-T1-GE3_SO8
3 6
241
12
PC516
PC516
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
PQ502
PQ502
PC502
PC502
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
+5VALW
+5VALW
SUSP#[10,25,38,39,44,46,47]
PR504
PR504
5.1_0603_5%
5.1_0603_5%
1 2
PR509 change for HW power sequence 10/17/2012
12
PC514
PC514 1U_0603_10V6K
1U_0603_10V6K
1 2
PR509
PR509
30K_0402_5%
30K_0402_5%
1 2
BOOT_1.5V
DH_1.5V
SW_1.5V
DL_1.5V
PR503
PR503
7.87K_0402_1%
7.87K_0402_1% 1 2
VDD_1.5V
PC511
PC511 1U_0603_10V6K
1U_0603_10V6K
16
PHASE
15
LGATE
14
PGND
13
CS_1.5V
CS
RT8207MZQW_W QFN20_3X3
RT8207MZQW_W QFN20_3X3
12
VDDP
11
VDD
PGOOD
10
PR506
PR506
1M_0402_1%
1M_0402_1%
1.5V_B+
S5_1.5V
S3_1.5V
12
PC517
PC517
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
17
9
UGATE
TON
18
8
BOOT
S5
VLDOIN_1.5V
19
VLDOIN
S3
7
STATE S3 S5 VDDQ VTTREF VTT S0 Hi Hi On On On S3 Lo Hi On On Off (Hi-Z) S4/S5 Lo Lo Off Off Off
3 3
2011_0801 JP504 form 43x118 change to 43x79
PJ506
PJ506
+3VALW
2
112
JUMP_43X79@
JUMP_43X79@
SUSP#25,38,39,44,46,47]
4 4
12
PR512
PR512
1 2
0_0402_5%
0_0402_5%
1.8VSP_VIN
PC518
PC518 22U_0805_6.3VAM
22U_0805_6.3VAM
EN_1.8VSP
1M_0402_5%
1M_0402_5%
PR513
PR513
1 2
PU502
PU502
4
10
12
PC523
PC523
0.1U_0402_10V7K
0.1U_0402_10V7K
PVIN
9
PVIN
8
SVIN
5
EN
TP
11
LX
PG
LX
FB
NC
NC
7
1
SY8033BDBC_DFN10_3X3
SY8033BDBC_DFN10_3X3
(Discharge) (Discharge) (Discharge)
PL502
PL502
1UH_PH041H-1R0MS_3.8A_20%
1UH_PH041H-1R0MS_3.8A_20%
2
3
6
1.8VSP_LX
FB=0.6Volt
1 2
PR511
PR511
PR514
PR514
12
12
PC519
PC519
12
68P_0402_50V8J
68P_0402_50V8J
12
12
PC520
PC520
22U_0805_6.3V6M
22U_0805_6.3V6M
12
@
@
@
@
20K_0402_1%
20K_0402_1%
PR510
PR510
4.7_1206_5%
4.7_1206_5%
12
PC522
PC522
680P_0603_50V7K
680P_0603_50V7K
1.8VSP_FB
10K_0402_1%
10K_0402_1%
+1.8VSP
PC521
PC521
22U_0805_6.3V6M
22U_0805_6.3V6M
2011_0801 JP505 form 43x118 change to 43x79
PJ507
PJ507
2
112
JUMP_43X79@
JUMP_43X79@
1.8VSP max current=4A
+1.8VS+1.8VSP
0.75Volt +/- 5% TDC A Peak Current 1A OCP Current A
12
12
PC507
PC507
10U_0805_6.3V6M
10U_0805_6.3V6M
12
PC515
PC515 .1U_0402_16V7K
.1U_0402_16V7K
@
@
+1.5VP
+1.5VP
PC508
PC508
10U_0805_6.3V6M
10U_0805_6.3V6M
12
PC509
PC509
0.033U_0402_16V7K
0.033U_0402_16V7K
PJ503
PJ503
2
JUMP_43X79@
JUMP_43X79@
PJ504
PJ504
2
JUMP_43X79@
JUMP_43X79@
PJ505
PJ505
112
JUMP_43X39
JUMP_43X39 @
@
+1.5VP OCP(min)=12.6A
+0.75VSP
112
112
2
+1.5V
+0.75VS+0.75VSP
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010/01/25 2010/12/31
2010/01/25 2010/12/31
2010/01/25 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Title
Title
Title
PWR-+1.5VP/+1.8VSP
PWR-+1.5VP/+1.8VSP
PWR-+1.5VP/+1.8VSP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
VIUS1
D
of
44 53Tuesday, February 26, 2013
of
44 53Tuesday, February 26, 2013
of
44 53Tuesday, February 26, 2013
0.4
0.4
0.4
5
4
3
2
1
VID [0] VID[1] VCCSA Vout 0 0 0.9V 0 1 0.85V 1 0 0.775V
D D
C C
1 1 0.75V
output voltage adjustable network
+3VS
PR610
PR610
100K_0402_5%
100K_0402_5%
SA_PGOOD[38]
1.05VS_VCCP_PWRGOOD[46]
1 2
+1.05VS
PJ602
PJ602
2
JUMP_43X79@
JUMP_43X79@
PR612
PR612
1 2
0_0402_5%
0_0402_5%
12
12
PC628
PC628
PC626
PC626
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.05VS_VIN
112
22U_0805_6.3V6M
+5VALW
PC624
PC624
PR611
PR611
1 2
1 2
1M_0402_1%
1M_0402_1%
1U_0603_6.3V6M
1U_0603_6.3V6M
PU601
PU601
9
GND
5
VIN
6
VPP
7
POK
8
VEN/MODE
PC629
PC629
1 2
1U_0603_6.3V6M
1U_0603_6.3V6M
G978F11U_SO8
G978F11U_SO8
4
Vo
3
Vo
2
D1
1
D0
PR622
PR622
0_0402_5%
0_0402_5%
PR621
PR621
12
12
0_0402_5%
0_0402_5%
@
@
@
@
H_VCCSA_VID1 [10]
H_VCCSA_VID0 [10]
PC613
PC613
PC615
PC615
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
+VCC_SAP TDC 2.9A Peak Current 4A OCP current 5.4A
The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stabili ty.
+VCCSA+VCCSAP
PJ601
PJ601
2
112
JUMP_43X79@
JUMP_43X79@
PC618
PC618
PC616
PC616
22U_0805_6.3V6M
22U_0805_6.3V6M
1 2
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
1 2
+VCCSAP
0.9V
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONI CS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONI CS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONI CS, INC.
3
2010/01/25 2010/12/31
2010/01/25 2010/12/31
2010/01/25 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Title
Title
Title
PWR +VCCSAP
PWR +VCCSAP
PWR +VCCSAP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
VIUS1
45 53Wednesday, February 27, 2013
45 53Wednesday, February 27, 2013
45 53Wednesday, February 27, 2013
of
of
1
of
0.4
0.4
0.4
5
D D
4
3
2
1
2011_0801 del PJ705 and "+V1.05S_VCCP"
Ivy Bridge CPU ES2 Using
C C
+1.05VS_VCCPP OCP(min)=15.76A
PL700
PL700
2011_0801 mount
+3VS
PR704, PR706
PR702
PR702 100K_0402_5%
1 2
PR708
PR708
1 2
470K_0402_1%
470K_0402_1%
100K_0402_5%
PU701
PU701
1
2
3
4
5
VBST
PGOOD
TRIP
DRVH
EN
SW
V5IN
VFB
DRVL
RF
TPS51212DSCR_SON10_3X3
TPS51212DSCR_SON10_3X3
TP
VFB=0.7V
10
9
8
7
6
11
BST_1.05VS_VCCP
DH_1.05VS_VCCP
LX_1.05VS_VCCP
DL_1.05VS_VCCP
0_0402_5%
0_0402_5%
PR703
PR703
TRIP_1.05VS_VCCP
12
PR707
PR707
54.9K_0402_1%
54.9K_0402_1%
12
1.05VS_VCCP_PWRGOOD[45]
PR701
PR701
60.4K_0402_1%
B B
SUSP#[10,25,38,39,44,47]
60.4K_0402_1%
1 2
PR706
PR706
12
PC701
PC701
10K_0402_1%@
10K_0402_1%@
1 2
.1U_0402_16V7K
.1U_0402_16V7K
SIR472DP-T1-GE3_POWERPAK8-5
SIR472DP-T1-GE3_POWERPAK8-5
PR704
PR704
2.2_0603_5%
2.2_0603_5%
1 2
PC707
PC707
0.22U_0603_16V7K
0.22U_0603_16V7K
1 2
+5VALW
12
PC710
PC710
1U_0603_10V6K
1U_0603_10V6K
PQ701
PQ701
1.05VS_B+
5
4
123
5
PQ702
PQ702
4
123
12
PC703
PC703
PC704
PC704
0.1U_0402_25V6
0.1U_0402_25V6
@
@
PL701
PL701
1 2
PR705
PR705
4.7_1206_5%
4.7_1206_5%
PC711
PC711
1000P_0603_50V7K
1000P_0603_50V7K
12
PC705
PC705
2200P_0402_50V7K
2200P_0402_50V7K
12
PC702
PC702
68P_0402_50V8J
68P_0402_50V8J
@
@
1UH_PCMB063T-1R0MS_12A_20%
1UH_PCMB063T-1R0MS_12A_20%
12
@
@
12
@
@
SIRA10DP-T1-GE3_POWERPAK8-5
SIRA10DP-T1-GE3_POWERPAK8-5
4.7U_0805_25V6-K
4.7U_0805_25V6-K
12
12
PC706
PC706
PR710
PR710 0_0402_5%
0_0402_5%
1 2
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
12
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
+
+
PC709
PC709
2
330U_D2_2V_Y
330U_D2_2V_Y
B+
2011_0815 PC1166, PC1167 PC1168 change place
1
form"+1.05VS"
+
+
to"+1.05VS_VCCPP"
PC712
PC712
2
330U_D2_2V_Y
330U_D2_2V_Y PR709
@PR709
@
10_0402_5%
10_0402_5%
12
+1.05VS
VSSIO_SENSE [9]
1 2
PR711
PR711
12
4.99K_0402_1%
4.99K_0402_1%
PR712
PR712
10K_0402_1%
10K_0402_1%
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010/01/25 2010/12/31
2010/01/25 2010/12/31
2010/01/25 2010/12/31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
PR713
10_0402_5%
10_0402_5%
@PR713
@
12
VCCIO_SENSE [9]
Compal Electronics, Inc.
Title
Title
Title
PWR +1.05VS_VCCPP
PWR +1.05VS_VCCPP
PWR +1.05VS_VCCPP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
VIUS1
1
0.4
0.4
46 53Tuesday, February 26, 2013
46 53Tuesday, February 26, 2013
46 53Tuesday, February 26, 2013
0.4
A
FM GN FN EI
FE
H G F E 
I
EENNN
NEE EN
NEEEN
E
1 1
2 2
3 3
4 4
N
E
E
N
E
NN
E
E
NE
E
NE
E
NENE
E
E
E
E
E
E
E
E
E
E
+3VS_VGA
0_0402_5%
0_0402_5%
@
@
PR832
PR832
DGPU_PWROK[18,38]
PR837
PR837
1 2
4.02K_0402_1%
4.02K_0402_1%
@
@
@PR838
@
PR838
1 2
249K_0402_1%
249K_0402_1%
150P_0402_50V8J
150P_0402_50V8J
PC822
PC822
12
VGA_AC_DET[24,38]
470K_0402_5%_TSM0B474J4702RE
470K_0402_5%_TSM0B474J4702RE
1 2
PH801
PH801
@
@
12
12
PC816
PC816
PR839
PR839
8.06K_0402_1%
8.06K_0402_1%
PC821
PC821
33P_0402_50V8J
33P_0402_50V8J
1 2
1 2
1 2
FB2_VGA
PR844
PR844
267K_0402_1%
267K_0402_1%
+VGA_CORE
N
N
N
N
N
E
N
EE
N ETNNN
E
N
E
E
NNN
N
N
N
E
N
E
E
N
DGPU_PWR_EN[17,25,51]
SUSP#[10,25,38,39,44,46]
PR819
PR819
1 2
10K_0402_1%
10K_0402_1%
12
@
@
PR831
PR831
1.91K_0402_1%
1.91K_0402_1%
1 2
+3VS_VGA
147K_0402_1%
147K_0402_1%
PR835
PR835
100K_0402_5%@
100K_0402_5%@
1 2
+3VS_VGA
1 2
PR836
0_0402_5%
0_0402_5%
VW_VGA
1 2
22P_0402_50V8J
22P_0402_50V8J
PR840
PR840
499_0402_1%
499_0402_1%
1 2
FB1_VGA
1000P_0402_50V7K
1000P_0402_50V7K
PR842
PR842
1.69K_0402_1%
1.69K_0402_1%
1 2
ISEN2_VGA
ISEN1_VGA
12
PR847
PR847 56K_0402_1%
56K_0402_1%
PR848
PR848
0_0402_5%
0_0402_5%
PR859
PR859
0_0402_5%
0_0402_5%
A
N
E
N
E
N
E
N
E
N
PC801 .1U_0402_16V7KPC801 .1U_0402_16V7K
DPRSLPVR_VGA-1
PR833
PR833
100K_0402_5%
100K_0402_5%
PR834
PR834
12
@PR836
@
COMP_VGA
FB_VGA
ISEN3_V GA
PC814
PC814
PC817
PC817
1 2
390P_0402_50V7K
390P_0402_50V7K
12
VSUM-_VGA
12
330P_0402_50V7K
330P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
12
PR816
PR816 91K_0402_1%
91K_0402_1%
1 2
0_0402_5%
0_0402_5%
1 2
1 2
PSI#_VGA
RBIAS_VGA
PC824
PC824
0.22U_0402_10V6K
0.22U_0402_10V6K
PR818
PC833
PC833
PC838
PC838
ETFNN
ETEKI
ETEIN
ETEFINEE EE
ETENN
ETNKI
ETNINN
ETNFI
NTMKI
NTMIN
NTMFI
NTMNN
NTLKI
NTLIN
NTLFI
NTLNN
12
10
41
@PR818
@
1 2 3 4 5 6 7 8 9
PC825
PC825
PU801
PU801
PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2
AGND
VSEN_VGA
0.22U_0402_10V6K
0.22U_0402_10V6K
12
12
'(#7.6
39
40
CLK_EN#
ISEN111VSEN12RTN13ISUM-14ISUM+15VDD
@PC839
@
12
PC839
330P_0402_50V7K
330P_0402_50V7K
VRON_VGA
38
DPRSLPVR
RTN_VGA
0_0402_5%
0_0402_5%
12
GPU_VID6
37
VR_ON
ISUM-_VGA
@
@
PR820
PR820
35
16
VDD_VGA
12
12
VSUM_VGA_N001
12
0_0402_5%
0_0402_5%
PR815
PR815
12
GPU_VID5
PR821
PR821
12
0_0402_5%
0_0402_5%
VID031VID132VID233VID334VID536VID6
VID4
BOOT2 UGATE2 PHASE2
VSSP2 LGATE2
VCCP
PWM3
LGATE1
VSSP1 PHASE1
VIN
IMON18BOOT119UGATE1
ISL62883CHRTZ-T_TQFN40_5X5
ISL62883CHRTZ-T_TQFN40_5X5
17
20
VIN_VGA
1 2
12
PC826
PC826
PC827
PC827
1U_0603_10V6K
1U_0603_10V6K
0.22U_0603_25V7K
0.22U_0603_25V7K
@PR849
@
PR849
82.5_0402_5%
82.5_0402_5%
@PC840
@
PC840
0.01U_0402_25V7K
0.01U_0402_25V7K
PR860
PR860
1.47K_0402_1%
1.47K_0402_1%
1 2
B
PR801 10K_0402_1%PR801 10K_0402_1%
1 2
10K_0402_5%
10K_0402_5%
GPU_VID4
PR822
PR822
12
0_0402_5%
0_0402_5%
30 29 28 27 26 25 24 23 22 21
PR843
PR843
PR846
PR846
1_0402_5%
1_0402_5%
PC834
PC834
0.22U_0603_10V7K
0.22U_0603_10V7K
B
1 2
GPU_VID5
PR813
PR813
@
@
12
PR802 10K_0402_1%PR802 10K_0402_1%
[24]
+3VS_VGA
1 2
GPU_VID4
2
@
@
GPU_VID3
PR823
PR823
12
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
12
+VGA_B+
PC835
PC835
1 2
PR803 10K_0402_1%@PR803 10K_0402_1%
GPU_VID3
@
61
+5VS
12
0.01U_0603_25V7K
0.01U_0603_25V7K
12
1 2
1 2
PR804 10K_0402_1%@PR804 10K_0402_1%
PR805 10K_0402_1%@PR805 10K_0402_1%
GPU_VID2
GPU_VID1
@
@
+3VS_VGA+3VALW
PQ802A
PQ802A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
[24]
[24]
GPU_VID2
12
PR824
PR824
0_0402_5%
0_0402_5%
PC811
PC811 1U_0603_10V6K
1U_0603_10V6K
12
12
PC823
PC823
.047U_0402_16V7K
.047U_0402_16V7K
12
PR857
PR857
11K_0402_1%
11K_0402_1%
PC842
PC842
.1U_0402_16V7K
.1U_0402_16V7K
1 2
PR806 10K_0402_1%@PR806 10K_0402_1%
GPU_VID0
@
PR814
PR814
1 2
10K_0402_5%
10K_0402_5%
@
@
5
@
@
[24]
GPU_VID0
GPU_VID1
PR826
PR826
12
12
PR825
PR825
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1 2
PC815
PC815 1U_0603_10V6K
1U_0603_10V6K
PR841 0_0402_5%@PR841 0_0402_5%@
1 2
PR845
PR845
11K_0402_1%
11K_0402_1%
1 2
VSUM+_VGA
12
PR851
PR851
2.61K_0402_1%~N
2.61K_0402_1%~N
NTC_VGA
12
PH802
PH802 10K_0402_1%_TSM0A103F34D1RZ
10K_0402_1%_TSM0A103F34D1RZ
1 2
PR807 10K_0402_1%@PR807 10K_0402_1%
GPU_VID5
@
34
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
[24]
+5VS
VGA_IMVP_IMON
VSUM-_VGA
PR811 10K_0402_1%PR811 10K_0402_1%
PR808 10K_0402_1%@PR808 10K_0402_1%
GPU_VID4
@
PQ802B
PQ802B
BOOT2_VGA BOOT2_2_VGA
+5VS
PR809 10K_0402_1%PR809 10K_0402_1%
GPU_VID3
PR810 10K_0402_1%PR810 10K_0402_1%
GPU_VID2
BOOT1_VGA
PR812 10K_0402_1%PR812 10K_0402_1%
GPU_VID1
PR817
PR817
2.2_0603_5%
2.2_0603_5%
UGATE1_VGA
PHASE1_VGA
LGATE1_VGA
1 2
1 2
1 2
1 2
C
1 2
GPU_VID0
SIR472DP-T1-GE3_POWERPAK8-5
SIR472DP-T1-GE3_POWERPAK8-5
PR863
PR863
UGATE2_VGA
12
LGATE2_VGA
+VGA_CORE
1
2
12
PC818
PC818
10U_0603_6.3V6M
10U_0603_6.3V6M
PR850
PR850
2.2_0603_5%
2.2_0603_5%
12
BOOT1_1_VGA
Layout Note: Place near Phase1 Choke
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
1 2
0_0603_5%
0_0603_5%
PC806
PC806
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
Near VGA Core
1
PC813
PC813
PC812
PC812
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
12
PC819
PC819
PC820
PC820
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
SIR472DP-T1-GE3_POWERPAK8-5
SIR472DP-T1-GE3_POWERPAK8-5
PC832
PC832
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
PQ801
PQ801
PR864
PR864
1 2
0_0603_5%
0_0603_5%
2012/07/03 2013/07/03
2012/07/03 2013/07/03
2012/07/03 2013/07/03
D
5
4
123
PHASE2_VGA
5
PQ803
PQ803
4
123
5
PQ804
PQ804
4
123
5
PQ805
PQ805
4
123
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
+VGA_B+
12
PC843
PC843
68P_0402_50V8J
68P_0402_50V8J
@
@
@PR827
@
PR827
SIRA10DP-T1-GE3_POWERPAK8-5
SIRA10DP-T1-GE3_POWERPAK8-5
@
@
12
PC844
PC844
68P_0402_50V8J
68P_0402_50V8J
@
@
SIRA10DP-T1-GE3_POWERPAK8-5
SIRA10DP-T1-GE3_POWERPAK8-5
PC802
PC802
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
4.7_1206_5%
4.7_1206_5%
SNUB2_VGA
12
PC828
PC828
@
@
@PR853
@
PR853
12
VSUM+_VGA
PC810
PC810
680P_0603_50V7K
680P_0603_50V7K
12
0.1U_0402_25V6
0.1U_0402_25V6
12
4.7_1206_5%
4.7_1206_5%
SNUB1_VGA
12
PC803
PC803
PC829
PC829
PC841
PC841
12
2200P_0402_50V7K
2200P_0402_50V7K
PR828
PR828
3.65K_0402_1%
3.65K_0402_1%
12
2200P_0402_50V7K@
2200P_0402_50V7K@
VSUM+_VGA
@
@
680P_0603_50V7K
680P_0603_50V7K
PC804
PC804
10U_0805_25V6K
10U_0805_25V6K
12
12
ISEN2_VGA
PC830
PC830
10U_0805_25V6K
10U_0805_25V6K
12
PR854
PR854
3.65K_0402_1%
3.65K_0402_1%
E
PL800
PL800
1 2
FBMA-L11-453215800LMA90T_2P
FBMA-L11-453215800LMA90T_2P
12
12
PC805
PC805
10U_0805_25V6K
10U_0805_25V6K
PL802
PL802
0.36UH 20% PDME064T-R36MS1R405 24A
0.36UH 20% PDME064T-R36MS1R405 24A
1 2
12
12
PR830
PR830 1_0402_1%
1_0402_1%
@
@
PR861
PR829
PR829
10K_0402_1%
10K_0402_1%
ISEN1_VGA
+VGA_B+
12
12
PC831
PC831
10U_0805_25V6K
10U_0805_25V6K
0.36UH 20% PDME064T-R36MS1R405 24A
0.36UH 20% PDME064T-R36MS1R405 24A
12
PR855
PR855
10K_0402_1%
10K_0402_1%
ISEN1_VGA
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PR861
10K_0402_1%
10K_0402_1%
VSUM-_VGA
ISEN1_VGA
㗗⏎天≈
PL803
PL803
1 2
12
PR856
PR856
PR862
PR862
10K_0402_1%
10K_0402_1%
@
@
VSUM-_VGA
ISEN2_VGA
ISEN2_VGA
㗗⏎天≈
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
VGA_COREP
VGA_COREP
VGA_COREP
VIUS1
12
E
PC807
PC807
330U_D2_2V_Y
330U_D2_2V_Y
1_0402_1%
1_0402_1%
330U_D2_2V_Y
330U_D2_2V_Y
B+
+VGA_CORE
1
1
+
+
+
+
PC808
PC808
2
2
330U_D2_2V_Y
330U_D2_2V_Y
@
@
+VGA_CORE
1
1
+
+
+
+
PC836
PC836
PC837
PC837
2
2
330U_D2_2V_Y
330U_D2_2V_Y
of
47 53Tuesday, February 26, 2013
of
47 53Tuesday, February 26, 2013
of
47 53Tuesday, February 26, 2013
0.4
0.4
0.4
5
4
3
2
1
PC902
1 2
PR904
PR904
1 2
26.7K_0402_1%
26.7K_0402_1%
PC908
PC908 10P_0402_50V8J
10P_0402_50V8J
1 2
COMPA1
2200P_0402_50V7K
2200P_0402_50V7K
1 2
60
61
PU901
PU901
PAD
VSNA
1
VCC
2
VDDBP
3
VRDYA
4
EN
5
SDIO
6
ALERT#
7
SCLK
8
VBOOT
9
ROSC VRMP VRHOT# VRDY VSN VSP DIFF
TRBST#
16
TRBST#
12
PC925
PC925 2200P_0402_50V7K
2200P_0402_50V7K
27K_0402_1%
27K_0402_1%
PR946
PR946
1 2
PUT COLSE TO VCORE Phase 1 Inductor
PC902
.1U_0402_16V7K
.1U_0402_16V7K
1 2
PC909
PC909
DIFFA
59
58
VSPA
NCP6132AMNR2G_QFN60_7X7
NCP6132AMNR2G_QFN60_7X7
FB
18
17
FB_CPU
COMP_CPU
12
CSSUMA
CSCOMPA
12
1 2
PR915
PR915
+5VS
16.9K_0402_1%
16.9K_0402_1%
FBA
DROOPA
ILIMA
COMPA
TRBSTA#
IMONAIMONA
51
53
49
52
56
54
57
50
55
FBA
ILIMA
DIFFA
IOUTA
COMPA
CSSUMA
DROOPA
TRBSTA#
CSCOMPA
CSCOMP22CSP325CSREF24CSSUM
COMP
DROOP
IOUT
CSP2
ILIM
23
21
20
ILIM_CPU
1 2
DROOP
13K_0402_1%
13K_0402_1%
PR936
PR936
CSCOMPCSCOMPCSCOMPCSCOMPCSCOMPCSCOMP
27
26
PC927
PC927 1000P_0402_50V7K
1000P_0402_50V7K
1 2
19
IMVP_IMON
1 2
1 2
PC931
PC931
1 2
.1U_0402_16V7K
.1U_0402_16V7K
PR948
PR948 75K_0402_1%
75K_0402_1%
220K_0402_5%_ERTJ0EV224J
220K_0402_5%_ERTJ0EV224J
PC903
PC903
1 2
1200P_0402_50V7K
1200P_0402_50V7K
PR911
PR911
1 2
53.6K_0603_1%
53.6K_0603_1%
PC911
PC911 1000P_0402_50V7K
1000P_0402_50V7K
1 2
CSP1A
TSENSEA
46
48
47
CSP2A
CSP1A
TSNSA
CSREFA
PWMA
BSTA
HGA SWA
LGA
BST2
HG2
SW2
LG2
PVCC
PGND
LG1
SW1
HG1
BST1
CSP1
DRVEN
TSNS
PWM
29
28
30
TSENSETSENSE
1 2
CSP1
+5VS
CSSUM
PC932
PC932
1000P_0402_50V7K
1000P_0402_50V7K NTC_PH201
12
PH904
PH904
PC904
PC904
1000P_0402_50V7K
1000P_0402_50V7K
12
PR908
PR908
165K_0402_1%
165K_0402_1%
SWN1A
PC913
PC913
.1U_0402_16V7K
.1U_0402_16V7K
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
PR934
PR934
26.1K_0402_1%
26.1K_0402_1%
1 2
PC922
PC922
.1U_0402_16V7K
.1U_0402_16V7K
PC930
PC930 1200P_0402_50V7K
1200P_0402_50V7K
12
1 2
PR949
PR949
165K_0402_1%
165K_0402_1%
1 2
NTC_PH203
CSREFA [49]
BST1
CSREF [49]
PR905
PR905
75K_0402_1%
75K_0402_1%
1 2
BSTA1
12
PR919
PR919
26.1K_0402_1%
26.1K_0402_1%
PUT COLSE TO GT
PH901
PH901
Inductor
220K_0402_5%_ERTJ0EV224J
220K_0402_5%_ERTJ0EV224J
CSREFA
PC910
PC910
12
0.068U_0402_16V7K
0.068U_0402_16V7K
PR921
PR921
2.2_0603_5%
2.2_0603_5%
1 2
1 2
PR930
PR930
2.2_0603_5%
2.2_0603_5%
CSREF
PR947
PR947
1 2
71.5K_0603_1%
71.5K_0603_1%
1 2
6.49K_0402_1%
6.49K_0402_1%
CSP1
BSTA1_1
BST1_1
CSP1A
HG1A [49]
LG1A [49]
6132P_VCCP
LG1 [49]
HG1 [49]
PR913
PR913
PC915
PC915
0.1U_0603_50V_X7R
0.1U_0603_50V_X7R
1 2
1 2
PR929 0_0402_5%PR929 0_0402_5%
12
1 2
PC920
PC920
0.1U_0603_50V_X7R
0.1U_0603_50V_X7R
PR941
PR941
1 2
12
6.49K_0402_1%
6.49K_0402_1%
PC928
PC928
0.068U_0402_16V7K
0.068U_0402_16V7K
SWN1
PC918
PC918
2.2U_0603_10V7K
2.2U_0603_10V7K
PR901
PR901
10_0402_1%
10_0402_1%
1 2
D D
TRBSTA#
1 2
PR902
PR902
10K_0402_1%
10K_0402_1%
VCC_AXG_SENSE[10]
VSS_AXG_SENSE[10]
+1.05VS
PC916
C C
PC916
12
PR922
PR922
.1U_0402_16V7K
.1U_0402_16V7K
130_0402_1%
130_0402_1%
VR_SVID_DAT[9]
VR_SVID_ALRT#[9]
VR_SVID_CLK[9]
1 2
+1.05VS
12
1
PC934
PC934
47P_0402_50V8J
47P_0402_50V8J
@
VR_HOT#[38]
B B
A A
@
VSSSENSE[9]
VCCSENSE[9]
PR931
PR931 75_0402_1%
75_0402_1%
@
@
2
VGATE[15]
TRBST#
1 2
FBA3
PC905
PC905
0.033U_0402_16V7K
0.033U_0402_16V7K
PC917
PC917
12
PR924
PR924
54.9_0402_1%
54.9_0402_1%
1 2
PR942
PR942 10_0402_1%
10_0402_1%
1 2
PC901
PC901
0.033U_0402_16V7K
0.033U_0402_16V7K
FBA1
1 2
@
@
.1U_0402_16V7K
.1U_0402_16V7K
+3VS
12
PR932
PR932 10K_0402_5%
10K_0402_5%
FB_CPU3
1 2
PR944
PR944
10K_0402_1%
10K_0402_1%
0.033U_0402_16V7K
0.033U_0402_16V7K
PR950
PR950
910_0402_1%
910_0402_1%
1 2
1 2
PR903
PR903
1K_0402_1%
1K_0402_1%
VR_ON[38]
CPU_B+
PR927
PR927 1K_0402_1%
1K_0402_1%
PR933
PR933
0_0402_5%
0_0402_5%
12
PR935
PR935
0_0402_5%
0_0402_5%
12
PC926
PC926
0.033U_0402_16V7K
0.033U_0402_16V7K
12
FB_CPU2
PC929
PC929
DROOP
PR907
PR907
10_0402_1%
10_0402_1%
1 2
1 2
PR909
PR909
1K_0402_1%
1K_0402_1%
PR928
PR928
95.3K_0402_1%
95.3K_0402_1%
1 2
1 2
12
PR939
PR939
10_0402_1%
10_0402_1%
1 2
1 2
PC933
PC933
1000P_0402_50V7K
1000P_0402_50V7K
1 2
FBA2
PR914 0_0402_5%PR914 0_0402_5%
12
12
PR917 0_0402_5%PR917 0_0402_5%
PR920
PR920 2_0603_5%
2_0603_5%
1 2
+5VS
PC914
PC914
1 2
2.2U_0603_10V7K
2.2U_0603_10V7K PR923 0_0402_5%PR923 0_0402_5%
1 2
12
PC919
PC919
0.01U_0402_25V7K
0.01U_0402_25V7K
VSN
PC921
PC921 1000P_0402_50V7K
1000P_0402_50V7K
VSP
PR938
PR938
1K_0402_1%
1K_0402_1%
1 2
PC924
PC924 680P_0402_50V7K
680P_0402_50V7K
1 2
FB_CPU1
1 2
PR945
PR945 866_0402_1%
866_0402_1%
CSREFCS COMP
IMVP_IMON[38]
PC907
PC907 470P_0402_50V7K
470P_0402_50V7K
1 2
12
VR_ON_CPU
PR926
PR926 10K_0402_1%
10K_0402_1%
PR910
PR910
6.04K_0402_1%
6.04K_0402_1%
PC912
PC912
1000P_0402_50V7K
1000P_0402_50V7K
6132_VCC
VR_SVID_DAT VR_SVID_ALRT# VR_SVID_CLK
VBOOT
ROSC_CPU VRMP VR_HOT# VGATE
DIFF_CPU
PR940
PR940
6.04K_0402_1%
6.04K_0402_1%
1 2
12
10 11 12 13 14 15
PC923
PC923
10P_0402_50V8J
10P_0402_50V8J
12
COMP_CPU1
806 ohm
PR906
PR906 806_0402_1%
806_0402_1%
1 2
SWN1A [49]
SW1A [49]
+5VS
SW1 [49]
SWN1 [49]
䡢娵㗗⏎天ᶲ 㰺ᶲ䲬
100
PC906
PC906 1000P_0402_50V7K
1000P_0402_50V7K
1 2
TSENSEA
12
8.25K_0402_1%@
8.25K_0402_1%@
PR916
PR916
PUT COLSE TO V_GT HOT SPOT
TSENSE
12
PR943
PR943
8.25K_0402_1%@
8.25K_0402_1%@
⹎枪⇘
PUT COLSE TO VCORE HOT SPOT
1 2
1 2
1 2
1 2
CSREFACSCOMPA DROOPA
0_0402_5%
0_0402_5% PR912
PR912
PH902
PH902
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
0_0402_5%
0_0402_5% PR937
PR937
PH903
PH903
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
PWR-CPU_CORE
PWR-CPU_CORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
PWR-CPU_CORE
VIUS1
1
0.4
0.4
48 53Tuesday, February 26, 2013
48 53Tuesday, February 26, 2013
48 53Tuesday, February 26, 2013
0.4
of
of
of
5
4
3
2
1
CPU_B+
SIR472DP-T1-GE3_POWERPAK8-5
SIR472DP-T1-GE3_POWERPAK8-5
PR1003
PR1003
HG1[48]
D D
SW1[48]
LG1[48]
C C
1 2
0_0603_5%
0_0603_5%
5
PQ1002
PQ1002
4
123
@
@
SIRA10DP-T1-GE3_POWERPAK8-5
SIRA10DP-T1-GE3_POWERPAK8-5
PQ1001
PQ1001
5
4
123
5
PQ1003
PQ1003
4
123
SIRA10DP-T1-GE3_POWERPAK8-5
SIRA10DP-T1-GE3_POWERPAK8-5
12
12
12
12
PC1001
PC1001
PC1002
PC1002
PC1003
PC1003
PC1004
PC1004
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
68P_0402_50V8J
68P_0402_50V8J
@
@
0.1U_0402_25V6 @
@
Choke PN:SH00000L400
DCR=0.779~0.861m ohm
PR1001
PR1001
4.7_1206_5%
4.7_1206_5%
PC1011
PC1011
680P_0603_50V7K
680P_0603_50V7K
4
3
PL1001
PL1001
0.36UH_PDME104T-R36MS0R825_37A_20%
0.36UH_PDME104T-R36MS0R825_37A_20%
12
@
@
SNUB_CPU1 12
@
@
12
PC1005
PC1005
2200P_0402_25V7K
2200P_0402_25V7K
1
2
B+
+CPU_CORE
1
+
+
PC1006
PC1006
2
33U_25V_M
33U_25V_M
CSREF [48]
SWN1 [48]
1
+
+
PC1008
PC1008
2
33U_25V_M
33U_25V_M
FBMA-L11-453215800LMA90T_2P
FBMA-L11-453215800LMA90T_2P
PL1003
PL1003
1 2
ULV 17W CPU VID1=0.9V IccMax=33A Icc_Dyn=28A Icc_TDC=16A R_LL=2.9m ohm
33U_25V_M
33U_25V_M
CPU_B+
1
1
+
+
+
+
PC1009
PC1009
PC1010
PC1010
2
2
33U_25V_M
33U_25V_M
CPU_B+
12
12
12
SIR472DP-T1-GE3_POWERPAK8-5
B B
A A
SIR472DP-T1-GE3_POWERPAK8-5
HG1A[48]
SW1A[48]
LG1A[48]
PQ1004
PQ1004
PR1004
PR1004
1 2
0_0603_5%
0_0603_5%
5
4
5
4
5
12
PC1013
PC1013
PC1014
PC1014
PC1012
PC1012
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6 @
@
Choke PN:SH00000L400
123
PQ1005
PQ1005
123
SIRA10DP-T1-GE3_POWERPAK8-5
SIRA10DP-T1-GE3_POWERPAK8-5
DCR=0.779~0.861m ohm
12
PR1002
PR1002
4.7_1206_5%
4.7_1206_5%
@
@
SNUB_GFX1
12
PC1017
PC1017
680P_0603_50V7K
680P_0603_50V7K
@
@
12
PC1015
PC1015
PC1016
PC1016
68P_0402_50V8J
68P_0402_50V8J
@
@
@
@
2200P_0402_25V7K
2200P_0402_25V7K
4
3
PL1002
PL1002
0.36UH_PDME104T-R36MS0R825_37A_20%
0.36UH_PDME104T-R36MS0R825_37A_20%
+VCC_GFXCORE_AXG
1
2
CSREFA [48]
SWN1A [48]
4
ULV GT2 VID1=1.23V IccMax=33A Icc_Dyn=20.2A Icc_TDC=21.5A R_LL=3.9m ohm
3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Title
Title
Title
PWR-CPU_CORE
PWR-CPU_CORE
PWR-CPU_CORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
VIUS1
49 53Tuesday, February 26, 2013
49 53Tuesday, February 26, 2013
49 53Tuesday, February 26, 2013
of
of
1
of
0.4
0.4
0.4
5
4
3
2
1
+CPU_CORE
12
PC1101
12
@
@
12
@
@
PC1101
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
PC1106
PC1106
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1125
PC1125
D D
C C
12
PC1102
PC1102
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
PC1107
PC1107
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
12
PC1126
PC1126
12
PC1103
PC1103
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
PC1108
PC1108
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
12
PC1130
PC1130
@
@
+CPU_CORE
1
PC1150
PC1150 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC1164
PC1164 22U_0805_6.3V6M
22U_0805_6.3V6M
2
@
@
B B
1
PC1171
PC1171 22U_0805_6.3V6M
22U_0805_6.3V6M
2
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1177
PC1177
12
1
PC1151
PC1151 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC1167
PC1167 22U_0805_6.3V6M
22U_0805_6.3V6M
2
@
@
1
PC1172
PC1172 22U_0805_6.3V6M
22U_0805_6.3V6M
2
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1178
PC1178
12
1
PC1152
PC1152 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC1165
PC1165 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC1173
PC1173 22U_0805_6.3V6M
22U_0805_6.3V6M
2
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1179
PC1179
12
+CPU_CORE +VCC_GFXCORE_AXG
12
PC1104
PC1104
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1131
PC1131
12
1
PC1153
PC1153 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC1168
PC1168 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC1174
PC1174 22U_0805_6.3V6M
22U_0805_6.3V6M
2
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
12
PC1180
PC1180
12
PC1105
PC1105
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1132
PC1132
12
1
PC1154
PC1154 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC1169
PC1169 22U_0805_6.3V6M
22U_0805_6.3V6M
2
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1175
PC1175
12
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1133
PC1133
12
1
2
1
2
12
PC1155
PC1155 22U_0805_6.3V6M
22U_0805_6.3V6M
PC1170
PC1170 22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1176
PC1176
+VCC_GFXCORE_AXG
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1109
PC1109
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1116
PC1116
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1135
PC1135
12
1
+
+
PC1148
PC1148
2
330U_D2_2V_Y
330U_D2_2V_Y
PC1111
PC1111
PC1110
PC1110
1
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
12
PC1117
PC1117
PC1136
PC1136
1
+
+
2
1
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1118
PC1118
1
12
2
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1137
PC1137
12
12
PC1149
PC1149
330U_D2_2V_Y
330U_D2_2V_Y
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1112
PC1112
PC1119
PC1119
PC1138
PC1138
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1113
PC1113
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1120
PC1120
12
@
@
22U_0805_6.3V6M
PC1114
PC1114
PC1115
PC1115
1
1
2
2
2011_0808 place power name change form +V1.05S_VCCP to +1.05VS
+1.05VS
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
PC1121
PC1121
PC1122
PC1122
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1140
PC1140
PC1139
PC1139
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1156
PC1156
12
2011_0815 PC714 change place form "+1.05VS_VCCPP" to "+1.05VS"
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PC1123
PC1123
2
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1141
PC1141
12
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1157
PC1157
12
10U_0603_6.3V6M
10U_0603_6.3V6M
1
12
PC1124
PC1124
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1142
PC1142
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1158
PC1158
12
12
PC1127
PC1127
PC1143
PC1143
PC1159
PC1159
12
12
12
+1.05VS
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1128
PC1128
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1144
PC1144
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1160
PC1160
10U_0603_6.3V6M
10U_0603_6.3V6M
PC1129
PC1129
PC1134
PC1134
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1145
PC1145
12
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1161
PC1161
12
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1147
PC1147
PC1146
PC1146
12
12
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1163
PC1163
PC1162
PC1162
12
12
1
+
+
PC1166
PC1166
2
330U_V_2.5VM_R6M
330U_V_2.5VM_R6M
@
@
@
@
+CPU_CORE
1
+
+
PC1181
PC1181
330U_D2_2VM_R9M
330U_D2_2VM_R9M
2
A A
5
1
+
+
330U_D2_2VM_R9M
330U_D2_2VM_R9M
2
PC1182
PC1182
@
@
1
+
+
PC1183
PC1183
330U_D2_2VM_R9M
330U_D2_2VM_R9M
2
@
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/09/15 2009/09/15
2008/09/15 2009/09/15
2008/09/15 2009/09/15
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
PWR - PROCESSOR DECOUPLING
PWR - PROCESSOR DECOUPLING
PWR - PROCESSOR DECOUPLING
VIUS1
1
of
50 53Tuesday, February 26, 2013
of
50 53Tuesday, February 26, 2013
of
50 53Tuesday, February 26, 2013
0.4
0.4
0.4
5
D D
4
3
2
1
PR1230,PD1201 add for HW power sequence required 10/31/2012
PR1230
PR1230
82K_0402_1%
82K_0402_1%
PD1201
PD1201
1 2
S SCH DIO RB751V40 SC76
S SCH DIO RB751V40 SC76
DGPU_PWR_EN[17,25,47]
PJ1202
C C
+3VALW
B B
PJ1202
2
JUMP_43X79
JUMP_43X79 @
@
112
12
PR1222
PR1222
130K_0402_1%
130K_0402_1%
1 2
PC1204
PC1204
0.1U_0402_10V7K
0.1U_0402_10V7K
12
PC1206
PC1206
@
@
0.1U_0402_10V7K
0.1U_0402_10V7K
EN_0.95V
12
PR1223
PR1223 100K_0402_1%
100K_0402_1%
@
@
1 2
12
12
PC1207
PC1207
PC1208
PC1208
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
VIN
2
VIN
3
GND
4
GND
17
PWRPD
16
15
EN
VIN
PU1202
PU1202
TPS54618RTER_QFN16_3X3
TPS54618RTER_QFN16_3X3
AGND5VSENSE6COMP7RT/CLK
PR1227
PR1227
18K_0402_1%
18K_0402_1%
14
PWRGD
1 2 12
PC1216
PC1216
0_0402_5%
0_0402_5%
13
BOOT
SS/TR
8
3300P_0402_50V7K
3300P_0402_50V7K
PR1224
PR1224
1 2
12
PH
11
PH
10
PH
9
12
PR1229
PR1229
182K_0402_1%
182K_0402_1%
0.22U_0603_10V7K
0.22U_0603_10V7K
12
PC1215
PC1215
2200P_0402_50V7K
2200P_0402_50V7K
PC1205
PC1205
1 2
LX_0.95V
1UH_PCMB042T-1R0MS_4.5A_20%
1UH_PCMB042T-1R0MS_4.5A_20%
12
PR1225
PR1225
SNUB_0.95V
4.7_0402_1%
4.7_0402_1%
@
@
12
@
@
PC1214
PC1214
680P_0402_50V7K
680P_0402_50V7K
PL1201
PL1201
1 2
100K_0402_1%
100K_0402_1%
Ϭϴs
PR1228
PR1228
PR1226
PR1226
19.1K_0402_1%
19.1K_0402_1%
+VGA_PCIEP
12
12
PC1213
PC1213
1 2
22P_0402_50V8J
22P_0402_50V8J
1 2
PC1209
PC1209
12
12
22U_0805_6.3VAM
22U_0805_6.3VAM
PC1210
PC1210
12
PC1211
PC1211
PC1212
PC1212
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
+VGA_PCIEP
PJ1203
PJ1203
2
JUMP_43X79
JUMP_43X79 @
@
112
+0.95VS_VGA
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/07/01 2012/07/01
2011/07/01 2012/07/01
2011/07/01 2012/07/01
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
PWR-PROSESTOR
PWR-PROSESTOR
PWR-PROSESTOR
VIUS1
1
of
51 53Tuesday, February 26, 2013
of
51 53Tuesday, February 26, 2013
of
51 53Tuesday, February 26, 2013
0.4
0.4
0.4
5
4
3
2
9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRI
IRU3:5
5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH,WHP
1
D D
2012/06/05
2012/06/08
2012/06/08
2012/06/08
C C





B B



A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/01/06 2009/01/06
2009/01/06 2009/01/06
2009/01/06 2009/01/06
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
PIR (PWR)
PIR (PWR)
PIR (PWR)
VIUS1
52 53Tuesday, February 26, 2013
52 53Tuesday, February 26, 2013
52 53Tuesday, February 26, 2013
1
0.4
0.4
0.4
of
of
of
1
2
3
4
5
9HUVLRQ&KDQJH/LVW3,5/LVW
Phase
2011/09/13
A A
B B
No1 Add C2325,C2326,C2327,C2328,C2329,R2319,R2324,Q2312
Sch Layout
V
DescriptionNo. BOMDate
V
function
Add SBA function (+3VM) power
C C
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONI CS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONI CS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONI CS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PIR (EE)
PIR (EE)
PIR (EE)
LA-8133P
5
53 53Tuesday, February 26, 2013
53 53Tuesday, February 26, 2013
53 53Tuesday, February 26, 2013
0.4
0.4
0.4
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