Compal LA-9611P VIUS1, ThinkPad S431 Schematic

1

2

3

4

5

ŽŵƉĂůŽŶĨŝĚĞŶƚŝĂů

DŽĚĞůEĂŵĞs/h^ϭ

A A

&ŝůĞEĂŵĞ>ͲϵϲϭϭW KDWE

B B

ŽŵƉĂůŽŶĨŝĚĞŶƚŝĂů

D^ĐŚĞŵĂƚŝĐƐŽĐƵŵĞŶƚ

/ŶƚĞů/ǀǇƌŝĚŐĞWƌŽĐĞƐƐŽƌǁŝƚŚZ///нWĂŶƚŚĞƌWŽŝŶƚW,

'WhD

C C

D D

ϮϬϭϮͲϬϮͲϭϴ

ZsϬϰ

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Cover Sheet

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

153Tuesday, February 26, 2013

0.4

A

B

C

D

E

ŽŵƉĂůŽŶĨŝĚĞŶƚŝĂů

DŽĚĞůEĂŵĞs/h^ϭ

1 1

&ŝůĞEĂŵĞ>ͲϵϲϭϭW KDWE

D^ƵŶyd

ϮϯŵŵΎϮϯŵŵ ZϯΎϰ

sZDϭϮϴDΎϭϲ

WĂŐĞϮϮΕϮϵ

ĞWŽŶŶĞĐƚŽƌ

2 2

;^ƵďŽĂƌĚͿ

;ŽĐŬŝŶŐͿ

;^ƵďŽĂƌĚͿ

,D/ŽŶŶĞĐƚŽƌ

ŝƐƉůĂǇWŽƌƚ

ĂƌĚZĞĂĚĞƌ

Realtek RTS5229

>E

Realtek RTL8111F

Z:ϰϱKEE

3 3

WĂŐĞϯϬ

WĂŐĞϯϭ

WĂŐĞϯϯ

^W/ZKD /K^ϴD

WĂŐĞϯϯ

W/Ͳyϴ DĞŵŽƌǇƵƐ

ĞW

FDI x8 (UMA)

100MHz

2.7GT/s

,D/

W

W/Ͳ

^W/

WĂŐĞϭϯ

/ŶƚĞů /ǀǇƌŝĚŐĞ

h>s;ϭϳtͿ

'

/ŶƚĞů WĂŶƚŚĞƌWŽŝŶƚ

,Dϳϲ

&'ϵϴϵ

ϮϱŵŵΎϮϱŵŵ

>Wh^



ENE KBC9012

WĂŐĞϯϴ

WĂŐĞϱΕϭϭ

DMI x4

100MHz 5GB/s

WĂŐĞϭϯΕϮϭ

dWD

Zϯ>ϭϲϬϬD,ǌ;ϭϱsͿ

,ƵĚŝŽ

h^ϯϬ

h^ϮϬ

^d

WĂŐĞϯϳ

ZϯͲ^KͲ/DDyϭ

ƵĚŝŽŽĚĞĐ

Realtek ALC3202

h^WKZdϯϬ

dŽƵĐŚWĂŶĞů

DK^ĂŵĞƌĂ

WĂŐĞϯϮ

WĂŐĞϭϮ

ϮŚĂŶŶĞů^ƉĞĂŬĞƌ

ŝŐŝƚĂůD/

ƵĚŝŽĐŽŵďŽ:ĂĐŬ

;^ƵďŽĂƌĚͿ

;ŽĐŬŝŶŐͿ

W/ǆƉƌĞƐƐDŝŶŝĐĂƌĚ

WLAN / WiMAX / BT

4 4

ZZZ

LA-9611P

DA_PCB

DA8000X7000

UCPU1

CPU2@

i5-3337U

SA00006CU20

A

UCPU1

CPU3@

i3-3227U

SA00006ED20

WĂŐĞϯϱ

UCPU1

CPU4@

i5-3437U

SA00006D940

W/Ͳ;t>EͿ

h^;dͿ

UCPU1

CPU5@

i7-3537U

SA00006D840

UCPU1

CPU6@

Ivy Bridgei7-3537U

SA00006DB30

B

/Ŷƚ<

ůŝĐŬWĂĚ

dƌĂĐŬWŽŝŶƚ

WĂŐĞϯϲ

'Ͳ^ĞŶƐŽƌ

dŚĞƌŵĂů^ĞŶƐŽƌ

Fintek F75303M CPU & RAM

&ŝŶŐĞƌWƌŝŶƚĞƌ

UPEK TCS5DH6C0

^dϯϬ,KEE

E'&&^^ ;^ƵďŽĂƌĚͿ

dŚĞƌŵĂů^ĞŶƐŽƌ

Nuvuton NCT7718 Panel

;^ƵďŽĂƌĚͿ

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

D

;^ƵďŽĂƌĚͿ

Compal Electronics, Inc.

Title

Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

E

0.4

253Tuesday, February 26, 2013

0.4

1

2

3

4

5

Voltage Rails

SIGNAL

STATE

+5VS

power plane

A A

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

B B

S5 S4/AC & Battery don't exist

+5VALW

+B

O

X

+1.5V

+3VALW

O

XX

X

XX X

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

+3VS

+1.5VS

+VCCP

+CPU_CORE

+VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS

+1.05VS

OO

X

M3 Supported

X

EC SM Bus2 address

Device

Thermal Sensor Fintek F75303M

+3VM

+1.05VM

(SBA Only)

O

1001_101xb

Full ON

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID

0 1 2 3 4 5 6 7

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON ON ON

ON

OFF

OFFLOW LOW LOW LOW

HIGH HIGH HIGH HIGH

LOW LOW

HIGH

LOWLOWLOW

HIGH

USB Port TableBOARD ID Table

PCB Revision

0.1

0.2

0.3

EHCI1

USB3.0

EHCI2

USB 2.0 Port

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

10 11 12 13

0

USB 3.0 Port (I/O Board)

1

USB 3.0 Port (MB)

2

USB 3.0 Port (Docking)

3

Camera

4 5 6 7 8

Touch Panel

9

(Test point) Mini Card (WLAN/BT) FPR

OFF

3 External USB Port

BOM Structure Table

BTO Item BOM Structure Connector CONN@ Unpop

Intel UMA

TPM TPM@ AOAC AOAC@

@ DIS@AMD UMA@ X76@VRAM Option

PCH SM Bus address

Device Address

DDR DIMM0

DDR DIMM2

C C

1001 000Xb

1001 010Xb

60%86&RQWURO7DEOH

7KHUPDO

;

9

96

;

:/$1 ::$1

;

;;

9

96

;

6HQVRU

;

;;

9

96

2

3&+

;

9

96

;

;;;

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

353Tuesday, February 26, 2013

0.4

6285&(

60%B(&B&. 60%B(&B'$ 60%B(&B&. 60%B(&B'$ 60%&/. 60%'$7$ 60/&/. 60/'$7$ 60/&/. 60/'$7$

D D

.%

9$/:

.%

9$/:

3&+

9$/:

3&+

9$/:

3&+

9$/:

9*$ %$77 .( 62',00

;9

;

9

96

1

9$/:

;

9

96

1

2

S5G3

3

4

5

S0

RTC

MB Bottom view

RTCRST

EC_111 pin

EC_ON

FD2

FD1

A A

FD1

@

1

FIDUCIAL_C40M80

FD2

@

1

FIDUCIAL_C40M80

FD3

@

1

FIDUCIAL_C40M80

FD4

@

1

FIDUCIAL_C40M80

MAINPWON

+5VALW

+3VALW/VCCDSW

ON/OFF#

EC_RSMRST#

PBTN_OUT#

SLP_S5#

SLP_S4#

SYSON

M_PWR_ON

PCH_APWROK

B B

SLP_S3#

SUSP#

+1.5V_CPU_VDDQ

+1.8VS

PCH

+5VS

+3VS

GPU

+1.5VS

+0.75VS

+V1.05VS(VCCP)

+VCCSA

RAM

C C

CPU

SA_PGOOD

VR_ON

99ms

PCH_POK

PCH_CLKOUT

DRAMPWROK

H_CPUPWRGD

CPU_VID

CPU_CORE

VGATE

SYS_PWROK

BUF_PLT_RST#

H1

H_4P2

D D

@

1

H_4P2

H4

H2

@

1

H_4P2

H3

H5

H_4P2

H_2P7

@

1

@

1

H_2P3

H7

H6

H_3P3

@

1

H_2P3

H9

H8

@

1

H_4P0

H10

H_4P0

@

1

JLB1

SHAPE354X512

@

1

SPI

DMI

ME and BIOS activity will continue

Tralning

H_4P0

H13

H12

H_4P0

@

1

H_4P0

H15

H14

@

1

H_4P0

H16

H_4P0

@

1

H_4P2

H21

H22

H_2P3

H22

H_2P5

@

1

H18

@

1

H_2P3

H24

H23

H_2P2X1P8N

@

1

2

JLB2

CLIP_3X15

1

Security Classification

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

Screw Hole

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

453Tuesday, February 26, 2013

0.4

1

A A

DMI_CRX_PTX_N0[15] DMI_CRX_PTX_N1[15] DMI_CRX_PTX_N2[15] DMI_CRX_PTX_N3[15]

DMI_CRX_PTX_P0[15] DMI_CRX_PTX_P1[15] DMI_CRX_PTX_P2[15] DMI_CRX_PTX_P3[15]

DMI_CTX_PRX_N0[15] DMI_CTX_PRX_N1[15] DMI_CTX_PRX_N2[15] DMI_CTX_PRX_N3[15]

DMI_CTX_PRX_P0[15] DMI_CTX_PRX_P1[15] DMI_CTX_PRX_P2[15] DMI_CTX_PRX_P3[15]

FDI_CTX_PRX_N0[15] FDI_CTX_PRX_N1[15] FDI_CTX_PRX_N2[15]

B B

C C

FDI_CTX_PRX_N3[15] FDI_CTX_PRX_N4[15] FDI_CTX_PRX_N5[15] FDI_CTX_PRX_N6[15] FDI_CTX_PRX_N7[15]

FDI_CTX_PRX_P0[15] FDI_CTX_PRX_P1[15] FDI_CTX_PRX_P2[15] FDI_CTX_PRX_P3[15] FDI_CTX_PRX_P4[15] FDI_CTX_PRX_P5[15] FDI_CTX_PRX_P6[15] FDI_CTX_PRX_P7[15]

FDI_FSYNC0[15] FDI_FSYNC1[15]

FDI_INT[15]

FDI_LSYNC0[15] FDI_LSYNC1[15]

CPU_eDPC_AUXN[30]

CPU_eDPC_AUXP[30]

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

2

UCPU1A

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

+1.05VS

1 2

24.9_0402_1%

EDP_COMP

R2

CPU_eDP_HPD#[30]

CPU_eDPC_N0[30] CPU_eDPC_N1[30]

CPU_eDPC_P0[30] CPU_eDPC_P1[30]

R2

FDI1_LSYNC

AF3

eDP_COMP IO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[ 0]

AA4

eDP_TX[ 1]

AE10

eDP_TX[ 2]

AE6

eDP_TX[ 3]

IVY-BRIDGE_BG A1023

IVY-BRIDGE_BG A1023 CPU1@

CPU1@

DMI Intel(R) FDI

eDP

3

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_COMP

PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N7

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P7

PCIE_CTX_GRX_C_N0 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N7

PCIE_CTX_GRX_C_P0 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P7

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

1 2

R1 24.9_0402_1%R1 24.9_0402_1%

C1 0.1U_0402_10V7KDIS@C1 0.1U_0402_10V7KDIS@ C2 0.1U_0402_10V7KDIS@C2 0.1U_0402_10V7KDIS@ C3 0.1U_0402_10V7KDIS@C3 0.1U_0402_10V7KDIS@ C4 0.1U_0402_10V7KDIS@C4 0.1U_0402_10V7KDIS@ C5 0.1U_0402_10V7KDIS@C5 0.1U_0402_10V7KDIS@ C6 0.1U_0402_10V7KDIS@C6 0.1U_0402_10V7KDIS@ C7 0.1U_0402_10V7KDIS@C7 0.1U_0402_10V7KDIS@ C8 0.1U_0402_10V7KDIS@C8 0.1U_0402_10V7KDIS@

C10 0.1U_0402_10V7KDIS@C10 0.1U_0402_10V7KDIS@ C11 0.1U_0402_10V7KDIS@C11 0.1U_0402_10V7KDIS@ C13 0.1U_0402_10V7KDIS@C13 0.1U_0402_10V7KDIS@ C12 0.1U_0402_10V7KDIS@C12 0.1U_0402_10V7KDIS@ C15 0.1U_0402_10V7KDIS@C15 0.1U_0402_10V7KDIS@ C14 0.1U_0402_10V7KDIS@C14 0.1U_0402_10V7KDIS@ C16 0.1U_0402_10V7KDIS@C16 0.1U_0402_10V7KDIS@ C17 0.1U_0402_10V7KDIS@C17 0.1U_0402_10V7KDIS@

ŚĞĐŬ'WhW/ͲĞh^ƐƉĞĞĚ 'ĞŶϮсϬϭƵ& 'ĞŶϯсϬϮϮƵ&

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

+1.05VS

PCIE_CRX_GTX_N[0..7] [23]

PCIE_CRX_GTX_P[0..7] [23]

4

PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P7

5

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

*

0:Lane Reversed

PCIE_CTX_GRX_N[0..7] [23]

PCIE_CTX_GRX_P[0..7] [23]

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

553Tuesday, February 26, 2013

0.4

1

A A

H_SNB_IVB#[18]

+1.05VS

WƌŽĐĞƐƐŽƌWƵůůƵƉƐ

H_PROCHOT#[38]

B B

12

H_CPUPWRGD[18]

R5

R5 62_0402_5%

62_0402_5%

H_PECI[18,38]

H_THRMTRIP#[18]

H_PM_SYNC[15]

1

C33

C33 220P_0402_50V7K

220P_0402_50V7K

2

@

ESD Request

2

1 2

R8 10K_0402_5%@R8 10K_0402_5%@

1 2

R12 56_0402_5%R12 56_0402_5%

1 2

C2215 100P_0402_50V8J

@

ESD Request

1 2

R25 130_0402_5%R25 130_0402_5%

3

UCPU1B

MISC THERMAL PWR MANAGEMENT

F49

PROC_SELECT#

C57

PROC_DETECT#

1

H_CATERR#

T1

TPC12T1TPC12

H_PROCHOT#_R

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-BRIDGE_BG A1023

IVY-BRIDGE_BG A1023 CPU1@

CPU1@

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK

BCLK#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY# PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

J3

CLK_CPU_DMI_R

H2

CLK_CPU_DMI#_R

AG3

CLK_CPU_DP_R

AG1

CLK_CPU_DP#_R

AT30

BF44

SM_RCOMP0

BE43

SM_RCOMP1

BG43

SM_RCOMP2

N53

XDP_PRDY#

N55

XDP_PREQ#

L56

XDP_TCK

TCK

L55

XDP_TMS

TMS

J58

XDP_TRST#

M60

XDP_TDI

TDI

L59

XDP_TDO

TDO

K58

XDP_DBRESET#

G58 E55 E59 G55 G59 H60 J59 J61

4

1 2

R4 0_0402_5%@R4 0_0402_5%@

1 2

R7 0_0402_5%@R7 0_0402_5%@

1 2

R20 0_0402_5%@R20 0_0402_5%@

1 2

R23 0_0402_5%@R23 0_0402_5%@

1 2

R13 140_0402_1%R13 140_0402_1%

1 2

R14 25.5_.402_1%R14 25.5_.402_1%

1 2

R15 200_0402_1%R15 200_0402_1%

ZϯŽŵƉĞŶƐĂƚŝŽŶ^ŝŐŶĂůƐ

WhWĨŽƌ:d'ƐŝŐŶĂůƐ

1 2

R21 51_0402_5%@R21 51_0402_5%@

1 2

R17 51_0402_5%@R17 51_0402_5%@

1 2

R22 51_0402_5%@R22 51_0402_5%@

1 2

R18 51_0402_5%@R18 51_0402_5%@

1 2

R19 51_0402_5%@R19 51_0402_5%@

1

T4

TPC12T4TPC12

CLK_CPU_DMI [14] CLK_CPU_DMI# [14]

CLK_CPU_DP [14] CLK_CPU_DP# [14]

H_DRAMRST# [7]

+1.05VS

5

C C

R35

@R35

@

10K_0402_5%

PM_DRAM_PWRGD[15]

PM_DRAM_PWRGD PM_SYS_PWRGD_BUF

D D

R214 0_0402_5%@R214 0_0402_5%@

1

1 2

5

1

P

B

2

A

G

3

1

C34

@C34

@

0.1U_0402_10V6K

2

U1

@U1

@

74AHC1G09GW_TSSOP5

4

O

SUSP[39]

+1.5V_CPU_VDDQ+3VALW+3VS

12

R33

R33 200_0402_5%

200_0402_5%

PM_SYS_PWRGD_BUF

12

R37

R37 39_0402_5%

39_0402_5% @

@

13

D

Q1

2

2N7002K_SOT23-3

2N7002K_SOT23-3 @

@

G

S

2

Buffered reset to CPU

PCH_PLTRST#[17]

+3VS +1.05VS

1

C35

0.1U_0402_10V6K

2

5

1

P

NC

4

BUFO_CPU_RST# BUF_CPU_RST#

Y

2

A

G

U2

U2 SN74LVC1G07DCKR_SC70-5

SN74LVC1G07DCKR_SC70-5

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

R34

R34 75_0402_5%

75_0402_5%

R36

43_0402_1%

1 2

12

R38

R38 0_0402_5%

0_0402_5% @

@

Compal Secret Data

Deciphered Date

2011/07/12 2012/07/01

Deciphered Date

4

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

653Tuesday, February 26, 2013

0.4

1

DDR_A_D[0..63][12]

A A

B B

DDR_A_BS0[12] DDR_A_BS1[12] DDR_A_BS2[12]

C C

DDR_A_CAS#[12] DDR_A_RAS#[12] DDR_A_WE#[12]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AP11

AJ10

AR11

AT13 AU13

BA13 BB11

AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

2

UCPU1C

AG6

SA_DQ[0]

AJ6

SA_DQ[1] SA_DQ[2]

AL6

SA_DQ[3] SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7] SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13] SA_DQ[14] SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17] SA_DQ[18] SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

3

M_CLK_DDR0 [12] M_CLK_DDR#0 [12] DDR_CKE0_DIMMA [12]

M_CLK_DDR1 [12] M_CLK_DDR#1 [12] DDR_CKE1_DIMMA [12]

DDR_CS0_DIMMA# [12] DDR_CS1_DIMMA# [12]

M_ODT0 [12] M_ODT1 [12]

DDR_A_DQS#[0..7] [12]

DDR_A_DQS[0..7] [12]

DDR_A_MA[0..15] [12]

BD13

BF12

BD10 BD14 BE13

BF16 BE17 BE18 BE21 BE14 BG14 BG18

BF19 BD50

BF48 BD53

BF52 BD49 BE49 BD54 BE53

BF56 BE57 BC59 AY60 BE54 BG54 BA58

AW59 AW58

AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58

AL58 AG58 AG59 AM60

AL59

AF61 AH60

BG39 BD42

AT22

AV43

BF40 BD45

4

UCPU1D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17] SB_DQ[18] SB_DQ[19]

BF8

SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

5

IVY-BRIDGE_BG A1023

CPU1@

+1.5V

1 2

R39 0_0402_5%@R39 0_0402_5%@

D

S

D

S

13

H_DRAMRST#[6]

D D

DRAMRST_CNTRL_PCH[10,14]

1

R42

4.99K_0402_1%

12

Q2

G

BSS138_NL_SOT23-3

2

1

C36

0.047U_0402_16V4Z

2

DDR3_DRAMRST#_R

DRAMRST_CNTRL

R40

1K_0402_5%

12

R41

1K_0402_5%

1 2

2

DDR3_DRAMRST# [12]

DRAMRST_CNTRL [10,14]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

IVY-BRIDGE_BG A1023

CPU1@

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

753Tuesday, February 26, 2013

0.4

1

2

3

4

5

CFG Straps for Processor

CFG2

12

R45

A A

R45 1K_0402_1%

1K_0402_1% @

@

UCPU1E

XDP_CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

TPC12T2TPC12

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53

H43 K43

H45 K45

F48

1

H48 K48

BA19 AV19

AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26

BF23 BE24

P+

CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]

VCC_VAL_SENSE VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

VCC_DIE_SENSE

RSVD6 RSVD7

RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

IVY-BRIDGE_BG A1023

IVY-BRIDGE_BG A1023 CPU1@

CPU1@

RESERVED

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

1

T3T3

+VCC_GFXCORE_AXG +CPU_CORE

@

1 2

12

R48

49.9_0402_1%

R179 100_0402_1%@R179 100_0402_1%@

1 2

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

VCC_VAL_SENSE VSS_VAL_SENSE

VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE

T2

12

R46

49.9_0402_1% @

B B

R176 100_0402_1%@R176 100_0402_1%@

1 2

R47 49.9_0402_1%@R47 49.9_0402_1%@

1 2

R49 49.9_0402_1%@R49 49.9_0402_1%@

C C

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BG4 DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1 DC_TEST_BD1

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

*

0:Lane Reversed

CFG4

12

R50

1K_0402_1%

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

*

CFG5 CFG6

1K_0402_1%

12

R51

R52

R51

@R52

@

1K_0402_1%

PCIE Port Bifurcation Straps

CFG[6:5]

— 00 = 1 x8, 2 x4 PCI Express* — 01 = reserved — 10 = 2 x8 PCI Express*

*

— 11 = 1 x16 PCI Express*

CFG7

12

R53

@R53

@ 1K_0402_1%

1K_0402_1%

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

0: PEG Wait for BIOS for training

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PROCESSOR(4/7) RSVD,CFG

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

LA-9611P

5

of

853Tuesday, February 26, 2013

0.4

1

2

3

4

5

+CPU_CORE +1.05VS

A A

B B

C C

D D

͵͵ ȋȌ

UCPU1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BG A1023

CPU1@

POWER

CORE SUPPLY

ͺǤͷ

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

H_VCCP_SEL

H_CPU_SVIDALRT#

VCCSENSE VSSSENSE

PEG IO AND DDR IO

RAILS

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

+1.05VS

Chief-River platforms VCCIO_SEL = pulled high

+1.05VS

12

C161

C161 1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

R174 100_0402_1%@R174 100_0402_1%@

1 2

R64 10_0402_1%R64 10_0402_1%

VCCIO_SENSE VSSIO_SENSE

12

R63

10_0402_1%

0.1U_0402_10V6K

+1.05VS

VCCIO_SENSE [46] VSSIO_SENSE [46]

+3VS

1 2

R78 10K_0402_5%R78 10K_0402_5%

12

1

C37

R54

R54 130_0402_5%

130_0402_5%

2

1 2

R56 43_0402_1%R56 43_0402_1%

Trace Impedance = 27 ~ 33 ohm Trace Length Match < 25 mils

R55

75_0402_5%

+1.05VS+1.05VS

12

+CPU_CORE

12

Place the PU resistors close to VR

1

C38

0.1U_0402_10V6K

2

VR_SVID_ALRT# [48] VR_SVID_CLK [48] VR_SVID_DAT [48]

Place the PU

R59

resistors close to CPU

100_0402_1%

VCCSENSE [48] VSSSENSE [48]

R62

R62 100_0402_1%

100_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

LA-9611P

5

of

953Tuesday, February 26, 2013

0.4

1

2

3

4

5

10U_0603_6.3V6M

C42

10U_0603_6.3V6M

C42

10U_0603_6.3V6M

1

2

+1.5V_CPU_VDDQ

R68

1K_0402_5%

R72

1K_0402_5%

C43

10U_0603_6.3V6M

C43

10U_0603_6.3V6M

1

@

2

H_VCCSA_VID0 [45] H_VCCSA_VID1 [45]

Dϯ^ƵƉƉŽƌƚ

C44

12

1

2

10U_0603_6.3V6M@C44

10U_0603_6.3V6M

@

+1.5V_CPU_VDDQ

C45

10U_0603_6.3V6M@C45

10U_0603_6.3V6M

C46

1

2

330U_D2_2V_Y+C46

330U_D2_2V_Y

1

+

2

ΪͳǤͷ

+5VALW

1 2

SUSP#[25,38,39,44,46,47]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

R67 0_0402_5%@R67 0_0402_5%@

+V_DDR_REFA_R

C2327 1U_0402_6.3V6K

R203

15K_0402_5%

12

R79

1K_0402_1%

@

+1.5V_CPU_VDDQ +1.5V

@

1 2

+1.5V

RUN_ON_CPU1.35VS3

1

C65

0.047U_0402_16V4Z

2

1 2

Q3

BSS138_NL_SOT23-3

D

S

D

S

13

G

2

DRAMRST_CNTRL

1 2

C47 0.1U_0402_10V6KC47 0.1U_0402_10V6K

1 2

C53 0.1U_0402_10V6KC53 0.1U_0402_10V6K

1 2

C54 0.1U_0402_10V6K@ C54 0.1U_0402_10V6K@

1 2

C55 0.1U_0402_10V6K@ C55 0.1U_0402_10V6K@

+1.5V

Title

Size Document Number Rev

Custom

Date: Sheet of

JP1

@JP1

@

PAD-OPEN 4x4m

U2409

6

CT

GND GND

4

VBIAS

2

VIN

VOUT

1

VIN

VOUT

3

ON

TPS22965DSGR_SON8_2X2~D

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

+VREF_DQ_DIMMA

DRAMRST_CNTRL [14,7]

+1.5V_CPU_VDDQ

12

9 5

8

7

LA-9611P

5

+1.5V_CPU_VDDQ

10 53Tuesday, February 26, 2013

0.4

+V_SM_VREF should have 10 mil trace width

POWER

UCPU1G

330U_D2_2V_Y

UCPU1G

͵͵ ȋʹȌ

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

ͳǤʹ

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

͸

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BG A1023

CPU1@

+VCC_GFXCORE_AXG

A A

B B

+VCC_GFXCORE_AXG

R65

10_0402_1%

VCC_AXG_SENSE[48] VSS_AXG_SENSE[48]

R66

10_0402_1%

+1.8VS

C C

D D

Vaxg

Can connect to GND if mother board onlyɄɄɄɄ

supports externa l graphics and if GFX VR is not stuffed in a common mother board design,

VAXG can be left floating in a commonɄɄɄɄ

motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed

R76 0_0805_5%@R76 0_0805_5%@

+VCCSA

1

1 2

12

1 2

C48

R73 100_0402_1%@R73 100_0402_1%@

10U_0603_6.3V6M

1

2

1 2

C56

10U_0603_6.3V6M

C56

10U_0603_6.3V6M

1

2

C49

10U_0603_6.3V6M

C49

10U_0603_6.3V6M

1

2

+1.8VS_VCCPLL

C58

1U_0402_6.3V6K@C58

1U_0402_6.3V6K

C57

1U_0402_6.3V6K

C57

1U_0402_6.3V6K

C59

1

2

C50

1

2

+

@

2

@

C51

10U_0603_6.3V6M@C51

10U_0603_6.3V6M

C52

1

+

@

2

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

2

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0] VCCSA_VID[1]

lines

AY43

BE7 BG7

ͷ

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+V_SM_VREF_CNT

+V_DDR_REFA_R +V_DDR_REFB_R

C40

10U_0603_6.3V6M

C40

10U_0603_6.3V6M

C41

1

2

+1.5V_CPU_VDDQ

12

C162

C162 1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

R75 0_0402_5%@R75 0_0402_5%@

1

2

1

A13

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AD17 AD20

AD61 AE13

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58

AF59 AG10 AG14 AG18 AG47 AG52 AG61

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

A17 A21 A25 A28 A33 A37 A40 A45 A49 A53

A9

AA1

AA8

AC6

AD4

AE8 AF1

AG7 AH4

AJ7 AK1

A A

B B

C C

UCPU1H

VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

2

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

3

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46 D50 D54 D58

D6 E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55

G51

G6

G61

H10 H14 H17 H21

H4 H53 H58

J1 J49 J55 K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

IVY-BRIDGE_BG A1023

IVY-BRIDGE_BG A1023 CPU1@

CPU1@

VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249]

VSS

4

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11

NCTF

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

1 1 1

1 1

1

T101 PAD @T101 PAD @ T102 PAD @T102 PAD @ T103 PAD @T103 PAD @

T108 PAD @T108 PAD @ T109 PAD @T109 PAD @

T114 PAD @T114 PAD @

5

IVY-BRIDGE_BG A1023

CPU1@

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

11 53Tuesday, February 26, 2013

0.4

1

+1.5V

12

R2001

1K_0402_1%

+VREF_DQ_DIMMA

A A

All VREF traces should have 10 mil trace width

B B

R2003

R2003 1K_0402_1%

1K_0402_1%

12

DDR_CKE0_DIMMA[7]

DDR_A_BS2[7]

M_CLK_DDR0[7] M_CLK_DDR#0[7]

DDR_A_BS0[7]

DDR_A_WE#[7] DDR_A_CAS#[7]

DDR_CS1_DIMMA#[7]

PN:SP07000LB00

C C

<Address: 00>

DIMM_A H:4.0mm

+3VS

+0.75VS +0.75VS

D D

1

@

C2001

1

2

C2021

@

2

+1.5V

JDIMM1

R2007

R2007 0_0402_5%

0_0402_5% @

@

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9 VSS925VSS10

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18 DQ1953VSS19

55

VSS20

57

DQ24 DQ2559VSS21 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

LCN_DAN06-K4406-0102 CONN@

CONN@

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3

DQ30 DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

G2

2.2U_0603_6.3V6K@C2001

2.2U_0603_6.3V6K

C2002

C2046

0.1U_0402_10V6K@C2021

0.1U_0402_10V6K

1

@

2

+VREF_DQ_DIMMA

0.1U_0402_10V6K

0.1U_0402_10V6K DDR_A_D0 DDR_A_D1

1

2

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D36 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D46 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

0.1U_0402_10V6K@C2046

0.1U_0402_10V6K

C2022

2.2U_0603_6.3V6K@C2022

2.2U_0603_6.3V6K

R2006 0_0402_5%@R2006 0_0402_5%

12

1

2

12

1

@

2

@

3

+1.5V

2 4

DDR_A_D4

6

DDR_A_D5 8 10

DDR_A_DQS#0 12

DDR_A_DQS0 14 16

DDR_A_D6 18

DDR_A_D7 20 22

DDR_A_D12 24

DDR_A_D13 26 28 30

DDR3_DRAMRST# 32 34

DDR_A_D14 36

DDR_A_D15 38 40

DDR_A_D20 42

DDR_A_D21 44 46 48 50

DDR_A_D22 52

DDR_A_D23 54 56

DDR_A_D28 58

DDR_A_D29 60 62

DDR_A_DQS#3 64

DDR_A_DQS3 66 68

DDR_A_D30 70

DDR_A_D31 72

74

DDR_CKE1_DIMMA 76 78

DDR_A_MA15 80

DDR_A_MA14DDR_A_MA14 82 84

DDR_A_MA11DDR_A_MA12 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA7

DDR_A_MA6

DDR_A_MA4

DDR_A_MA2

DDR_A_MA0

M_CLK_DDR1

M_CLK_DDR#1

DDR_A_BS1

DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT0

M_ODT1

+VREF_CA

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D45

DDR_A_DQS#5

DDR_A_DQS5

DDR_A_D47

DDR_A_D52

DDR_A_D53

DDR_A_D54

DDR_A_D55

DDR_A_D60

DDR_A_D61

DDR_A_DQS#7

DDR_A_DQS7

DDR_A_D62

DDR_A_D63

SMB_DATA_S3

SMB_CLK_S3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

A7

A6 A4

A2 A0

DDR3_DRAMRST# [ 7]

DDR_CKE1_DIMMA [7]

M_CLK_DDR1 [7] M_CLK_DDR#1 [7]

DDR_A_BS1 [7] DDR_A_RAS# [7]

DDR_CS0_DIMMA# [ 7] M_ODT0 [7]

M_ODT1 [7]

C2015

2.2U_0603_6.3V6K@C2015

2.2U_0603_6.3V6K

1

@

2

SMB_DATA_S3 [14,30,35,36] SMB_CLK_S3 [14,30,35,36]

2011/07/12 2012/07/01

C2016

0.1U_0402_10V6K

1

2

+1.5V

12

Compal Secret Data

R2004

R2004 1K_0402_1%

1K_0402_1%

R2005

R2005 1K_0402_1%

1K_0402_1%

Deciphered Date

4

+1.5V

C2005

0.1U_0402_10V6K

C2005

0.1U_0402_10V6K

C2004

0.1U_0402_10V6K

C2004

0.1U_0402_10V6K

C2006

C2003

0.1U_0402_10V6K@C2003

0.1U_0402_10V6K

1

@

2

+1.5V

C2008

C2007

10U_0603_6.3V6M

C2007

10U_0603_6.3V6M

1

2

+0.75VS

C2017

1U_0402_6.3V6K

C2017

1U_0402_6.3V6K

1

2

4

C2006

1

2

1

2

C2018

Size Document Number Rev

Custom

Date: Sheet of

1

2

10U_0603_6.3V6M

C2009

10U_0603_6.3V6M@C2009

10U_0603_6.3V6M

C2010

1

@

2

@

C2019

1U_0402_6.3V6K@C2019

1U_0402_6.3V6K

1

2

Compal Electronics, Inc.

Title

DDRIII DIMMA

5

DDR_A_DQS#[0..7] [7]

DDR_A_DQS[0..7] [7]

DDR_A_D[0..63] [7]

DDR_A_MA[0..15] [7]

Layout Note: Place near

0.1U_0402_10V6K

JDIMM1

C2011

10U_0603_6.3V6M

C2011

10U_0603_6.3V6M

10U_0603_6.3V6M@C2010

10U_0603_6.3V6M

C2012

1

2

@

Layout Note: Place near

C2020

1U_0402_6.3V6K@C2020

1U_0402_6.3V6K

JDIMM1.203,204

1

2

LA-9611P

5

C2013

10U_0603_6.3V6M@C2013

10U_0603_6.3V6M

C2014

330U_D2_2V_Y

C2014

10U_0603_6.3V6M

330U_D2_2V_Y

1

+

@

2

@

2

0.4

12 53Tuesday, February 26, 2013

0.4

1

C64

C64 18P_0402_50V8J

18P_0402_50V8J

2

PCH_RTCX1

PCH_RTCX2

SM_INTRUDER#

PCH_INTVRMEN

HDA_SPKR

HDA_SDOUT

HDA_SYNC

1

C179

C179 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+3VS

1 2

R202 10K_0402_5%R202 10K_0402_5%

12

CLRP1

CLRP1 SHORT PADS

SHORT PADS

1 2

R87 10M_0402_5%R87 10M_0402_5%

Y1

1 2

32.768KHZ_12.5PF_CM31532768DZFT

1

C63

C63 18P_0402_50V8J

18P_0402_50V8J

2

A A

+RTCVCC

1 2

R90 1M_0402_5%R90 1M_0402_5%

1 2

R91 330K_0402_5%R91 330K_0402_5%

INTVR MEN

H烉烉烉烉Integrated VRM enable

*

L烉烉烉烉Integrated VRM disable

(INTVRMEN should always be pull high.)

+3VS

1 2

R93 1K_0402_5%@R93 1K_0402_5%@

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

B B

+3V_PCH

1 2

R95 1K_0402_5%@R95 1K_0402_5%@

HDA_SDO

ME debug mode,this signal has a weak i nternal PD Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

1 2

R99 1K _0402_5%R99 1K_0402_5%

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when sampled high

*

1.8V when sampled low Needs to be pulled High for Huron River platfrom

C C

EMI

RP9

1 8

HDA_BITCLK_AUDIO[32] HDA_SYNC_AUDIO[32] HDA_RST_AUDIO#[32] HDA_SDOUT_AUDIO[32]

2 7 3 6 4 5

33_8P4R_5%

HDA_BIT_CLK HDA_SYNC_R HDA_RST# HDA_SDOUT

Prevent back drive issue.

+5VS

G

2

13

D

S

D

S

Q8

12

BSS138_NL_SOT23-3

R303

R303 1M_0402_5%

1M_0402_5%

HDA_SYNC

R106

1K_0402_5%

1 2

W=20milsW=20mils

+RTCBATT+RTCVCC

WLBT_OFF_5#

2

PIN1

PIN2

CLRP1, JCMOS1, JME1 place near the door

C62

+RTCVCC

1 2

R88 20K_0402_5%R88 20K_0402_5%

1 2

R89 20K_0402_5%R89 20K_0402_5%

HDA_SPKR[32]

HDA_SDIN0[ 32]

ME_FLASH[38]

WLBT_OFF_5#[35]

+3V_PCH

C62

1U_0402_6.3V6K

C66

1U_0402_6.3V6K

R94 0_0402_5%@R94 0_0402_5%@

R209 10K_0402_5%@R209 10K_0402_5%@

R96 51_0402_5%R96 51_0402_5%

RTC conn

1

12

@

2

1

12

@

2

HDA_SPKR

HDA_SDIN0

1 2

CMOS

JCMOS1

SHORT PADS@JCMOS1

SHORT PADS

ME

JME1

SHORT PADS@JME1

SHORT PADS

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_RST#

HDA_SDOUT

WLBT_OFF_5#

PCH_GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH_R

SPI_SB_CS0#

SPI_SI

SPI_SO_R

3

G22

G34

U2408A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPI O13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

P-

P+

P-

P+

RTCIHDA

JTAG

SPI

P+ P+

P+

ϴD^W/ZKD&KZϭϱDD ΘEŽŶͲƐŚĂƌĞZKD

4

C38

P+

FWH0 / LAD0

P+

FWH1 / LAD1

P+

FWH2 / LAD2

P+

FWH3 / LAD3

LPC

FWH4 / LFRA ME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI_SB_CS0#

SPI_WP#

KE ϴD^ϬϬϬϬϰϲϰϬϬ^/&>ϲϰDEϮϱYϲϰͲϭϬϰ,/W^KWϴW

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36 K36

V5

SERIRQ

AM3

SATA_DTX_C_PRX_N0

AM1

SATA_DTX_C_PRX_P0

AP7

SATA_PTX_C_DRX_N0

AP5

SATA_PTX_C_DRX_P0

AM10

SATA_DTX_C_PRX_N1

AM8

SATA_DTX_C_PRX_P1

AP11

SATA_PTX_C_DRX_N1

AP10

SATA_PTX_C_DRX_P1

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

1 2 3 4

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

PCH_GPIO21

PCH_GPIO19

U5 8M

U5

CS#

VCC

DO

HOLD#

WP#

CLK

GND

DI

W25Q32BVSSIG_SO 8

+3VS

C191 0.1U_0402_10V6KC191 0.1U_0402_10V6K

8 7

SPI_HOLD#SPI_SO_R

6

SPI_CLK_PCH_R

5

SPI_SI

1 2

LPC_AD0 [37,38] LPC_AD1 [37,38] LPC_AD2 [37,38] LPC_AD3 [37,38]

LPC_FRAME# [37,38]

SERIRQ [37,38]

SATA_DTX_C_PRX_N0 [34] SATA_DTX_C_PRX_P0 [34] SATA_PTX_C_DRX_N0 [34] SATA_PTX_C_DRX_P0 [34]

SATA_DTX_C_PRX_N1 [34] SATA_DTX_C_PRX_P1 [34] SATA_PTX_C_DRX_N1 [34] SATA_PTX_C_DRX_P1 [34]

GATEA20[18,38] CLK_BUF_PCIE_SATA#[14] CLK_BUF_PCIE_SATA[14]

+1.05VS_VCC_SATA

+1.05VS_SATA3

PCH_GPIO49[18]

PCH_GPIO22[18]

KB_RST#[18,38]

SERIRQ GATEA20 CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

PCH_GPIO19

SPI_WP#

SPI_HOLD#

5

HDD

m-SATA

RP5

1 8 2 7 3 6 4 5

10K_8P4R_5%

1 2

R97 37.4_0402_1%R97 37.4_0402_1%

1 2

R98 49.9_0402_1%R98 49.9_0402_1%

1 2

R100 750_0402_1%R100 750_0402_1%

RP3

1 8

PCH_GPIO21

PCH_GPIO49

2 7 3 6

PCH_GPIO22

4 5

KB_RST#

10K_8P4R_5%

1 2

R101 10K_0402_5%R101 10K_0402_5%

1 2

R103 10K_0402_5%R103 10K_0402_5%

1 2

R334 3.3K_0402_5%R334 3.3K_0402_5%

1 2

R335 3.3K_0402_5%R335 3.3K_0402_5%

+3VS

+1.05VS

+3VS

+3V_PCH +3V_PCH+3V_PCH

D D

12

R120 200_0402_5%

200_0402_5%

12

R123 100_0402_1%

100_0402_1%

12

@R120

@

@R123

@

R121 200_0402_5%

200_0402_5%

PCH_JTAG_TMSPCH_JTAG_TDO PCH_JTAG_TDI

12

R124 100_0402_1%

100_0402_1%

12

R122

@R122

@R121

@

@R124

@

1

200_0402_5%

12

R125 100_0402_1%

100_0402_1%

@

Security Classification

@R125

@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PCH (1/9) SATA,HDA,SPI, LPC

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

13 53Tuesday, February 26, 2013

0.4

1

PCIE_PRX_DTX_N1[37]

18 27 36 45

LAN_CLKREQ# PCIE_WAKE# RI# EC_SMI#

PCH_GPIO45 PCH_GPIO56 PCH_GPIO44 PCH_GPIO72

PCIE_PRX_DTX_P1[37] PCIE_PTX_C_DRX_N1[37] PCIE_PTX_C_DRX_P1[37]

PCIE_PRX_DTX_N2[35] PCIE_PRX_DTX_P2[35] PCIE_PTX_C_DRX_N2[35] PCIE_PTX_C_DRX_P2[35]

PCIE_PRX_DTX_N4[33] PCIE_PRX_DTX_P4[33] PCIE_PTX_C_DRX_N4[33] PCIE_PTX_C_DRX_P4[33]

CLK_PCIE_CARD#[37] CLK_PCIE_CARD[37]

CARD_CLKREQ#[37]

CLK_PCIE_WLAN1#[35] CLK_PCIE_WLAN1[35]

WLAN_CLKREQ1#[35]

CLK_PCIE_LAN#[33] CLK_PCIE_LAN[33]

LAN_CLKREQ#[33]

WLAN_CLKREQ1#

PCH_GPIO20

CARD_CLKREQ#

PCH_GPIO26

PCH_GPIO46

PCIE_WAKE# [15,33] RI# [15] EC_SMI# [18,38]

PCH_GPIO72 [15]

Card Reader

A A

Wireless LAN

PCIE LAN

B B

Card Reader

Wireless LAN

PCIE LAN

+3VS

1 2

R170 10K_0402_5%R170 10K_0402_5%

1 2

R162 10K_0402_5%@R162 10K_0402_5%@

+3V_PCH

1 2

C C

D D

R177 10K_0402_5%R177 10K_0402_5%

1 2

R181 10K_0402_5%@R181 10K_0402_5%@

1 2

R184 10K_0402_5%@R184 10K_0402_5%@

RP7

10K_8P4R_5%

RP6

@RP6

@

10K_8P4R_5%

1 2

C86 0.1U_0402_10V6KC86 0.1U_0402_10V6K

1 2

C79 0.1U_0402_10V6KC79 0.1U_0402_10V6K

1 2

C82 0.1U_0402_10V6KC82 0.1U_0402_10V6K

1 2

C83 0.1U_0402_10V6KC83 0.1U_0402_10V6K

1 2

C80 0.1U_0402_10V6KC80 0.1U_0402_10V6K

1 2

C81 0.1U_0402_10V6KC81 0.1U_0402_10V6K

1 2

R147 0_0402_5%@R147 0_0402_5%@

1 2

R149 0_0402_5%@R149 0_0402_5%@

1 2

R141 0_0402_5%@R141 0_0402_5%@

1 2

R142 0_0402_5%@R142 0_0402_5%@

1 2

R145 0_0402_5%@R145 0_0402_5%@

1 2

R146 0_0402_5%@R146 0_0402_5%@

1

T227T227

1

T226T226

2

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

CLK_CARD# CLK_CARD

CARD_CLKREQ#

CLK_MINI1# CLK_MINI1

WLAN_CLKREQ1#

PCH_GPIO20

CLK_LAN# CLK_LAN

LAN_CLKREQ#

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

CLK_XDP_CLK# CLK_XDP_CLK

U2408B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

P+

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

P+/P-

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPB ACK

XTAL25_OUT

XCLK_RCOMP

P-

CLKOUTFLEX0 / GPIO64

P-

CLKOUTFLEX1 / GPIO65

P-

CLKOUTFLEX2 / GPIO66

P-

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

3

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12

PCH_GPIO11

H14

PCH_SMBCLK

C9

PCH_SMBDATA

A12

DRAMRST_CNTRL_PCH

C8

PCH_SML0CLK

G12

PCH_SML0DATA

C13

PCH_HOT#

E14

PCH_SML1CLK

M16

PCH_SML1DATA

M7

T11

P10

M10

PCH_GPIO47

AB37 AB38

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12

CLK_CPU_DP#

AM13

CLK_CPU_DP

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_DMI2#

BG30

CLKIN_DMI2

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

PCH_GPIO64

F47

PCH_GPIO65

H47

PCH_GPIO66

K49

PCH_GPIO67

DRAMRST_CNTRL_PCH [10,7]

1 2

R139 0_0402_5%@R139 0_0402_5%@

1 2

R144 0_0402_5%@R144 0_0402_5%@

1 2

R151 0_0402_5%@R151 0_0402_5%@

1 2

R148 10K_0402_5%R148 10K_0402_5%

1 2

R150 10K_0402_5%R150 10K_0402_5%

1 2

R152 10K_0402_5%R152 10K_0402_5%

1 2

R153 10K_0402_5%R153 10K_0402_5%

1 2

R154 10K_0402_5%R154 10K_0402_5%

1 2

R155 10K_0402_5%R155 10K_0402_5%

CLK_BUF_PCIE_SATA# [13] CLK_BUF_PCIE_SATA [13]

1 2

R158 10K_0402_5%R158 10K_0402_5%

1 2

R160 90.9_0402_1%R160 90.9_0402_1%

CLK_CPU_DP [6]

+1.05VS

+1.05VS_VCCDIFFCLKN

PCH_GPIO67 [18]

4

PCH_GPIO47 [ 18]

GPU_CLKREQA [24]

CLK_PCIE_VGA# [23] CLK_PCIE_VGA [23]

CLK_CPU_DMI# [6] CLK_CPU_DMI [6]

CLK_CPU_DP# [6]

CLK_PCI_LPBACK [17]

PCH_SMBCLK

PCH_SMBDATA

PCH_SML0CLK

PCH_SML0DATA

PCH_SML1CLK

PCH_SML1DATA

PCH_HOT#

PCH_GPIO11

DRAMRST_CNTRL_PCH

@

6 1

PCH_SMBDATA

Q9A 2N7002KDWH_SOT363-6

PCH_SMBCLK

Q9B 2N7002KDWH_SOT363-6

PCH_SMBCLK SMB_CLK_S3

PCH_SML1DATA

PCH_SML1CLK

PLT_RST#[17,23,33,35,37,38]

R163 0_0402_5%@R163 0_0402_5%@ R164 0_0402_5%@R164 0_0402_5%@

@

6 1

Q10A 2N7002KDWH_SOT363-6

@

Q10B 2N7002KDWH_SOT363-6

PCH_SML1CLK EC_SMB_CK2

XTAL25_IN

XTAL25_OUT

C87

C87 15P_0402_50V8J

15P_0402_50V8J

+3VS

12

R172

R172 10K_0402_5%

10K_0402_5% @

@

PLT_RST#

R128 2.2K_0402_5%@R128 2.2K_0402_5%@

R129 2.2K_0402_5%@R129 2.2K_0402_5%@

R130 2.2K_0402_5%R130 2.2K_0402_5%

R131 2.2K_0402_5%R131 2.2K_0402_5%

R126 2.2K_0402_5%@R126 2.2K_0402_5%@

R132 2.2K_0402_5%@R132 2.2K_0402_5%@

R133 10K_0402_5%R133 10K_0402_5%

R135 10K_0402_5%R135 10K_0402_5%

R127 1K_0402_5%R127 1K_0402_5%

+3VS

3 4

+3VS

R165 0_0402_5%@R165 0_0402_5%@ R166 0_0402_5%@R166 0_0402_5%@

R136 2.2K_0402_5%R136 2.2K_0402_5%

2

SMB_DATA_S3

R137 2.2K_0402_5%R137 2.2K_0402_5%

1 2

5

@

SMB_CLK_S3

1 2 1 2

Pull up at EC side.

2

EC_SMB_DA2

5

3 4

EC_SMB_CK2

1 2 1 2

1 2

R161 1M_0402_5%R161 1M_0402_5%

25MHZ 20PF +-20PPM X 3G025000DK1H-X

25MHZ 20PF +-20PPM X 3G025000DK1H-X Y2

Y2

1

2

U8

1

NC

VCC

2

NC

WP

3

SCL

PROT#

4

SDA

GND

PCA24S08D_SO8

PCA24S08D_SO8 EEPROM SA00004MK00 EEPROM SA00004ML00

GND

5

1 2

2

8 7 6 5

GND

SMB_CLK_S3 SMB_DATA_S3

+3VS

SMB_DATA_S3 [12,30,35,36]

+3VS

SMB_CLK_S3 [12,30,35,36]

SMB_DATA_S3PCH_SMBDATA

EC_SMB_DA2 [24,30,36,38]

EC, VGA, Theraml

EC_SMB_CK2 [24,30,36,38]

EC_SMB_DA2PCH_SML1DATA

3

4

1

2

+3VS

ROM_WP

+3V_PCH

DDR, WALN

C88

C88 15P_0402_50V8J

15P_0402_50V8J

1

C91

0.1U_0402_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PCH (2/8) PCIE, SMBUS, CLK

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

14 53Tuesday, February 26, 2013

0.4

1

DMI_CTX_PRX_N0[5]

A A

B B

C C

+3VS

+3V_PCH

DMI_CTX_PRX_N1[5] DMI_CTX_PRX_N2[5] DMI_CTX_PRX_N3[5]

DMI_CTX_PRX_P0[5] DMI_CTX_PRX_P1[5] DMI_CTX_PRX_P2[5] DMI_CTX_PRX_P3[5]

DMI_CRX_PTX_N0[5] DMI_CRX_PTX_N1[5] DMI_CRX_PTX_N2[5] DMI_CRX_PTX_N3[5]

DMI_CRX_PTX_P0[5] DMI_CRX_PTX_P1[5] DMI_CRX_PTX_P2[5] DMI_CRX_PTX_P3[5]

PCH_PWROK[38]

PM_DRAM_PWRGD[6]

EC_RSMRST#[38]

PBTN_OUT#[38]

ACIN[38,42]

1 2

R204 200_0402_5%@R204 200_0402_5%@

1 2

R305 200_0402_5%@R305 200_0402_5%@

1 2

R205 10K_0402_5%R205 10K_0402_5%

1 2

R206 200K_0402_5%R206 200K_0402_5%

1 2

R210 10K_0402_5%R210 10K_0402_5%

PCH_PWROK

PM_DRAM_PWRGD

SUSWARN#

AC_PRESENT_R

EC_RSMRST#

2

+1.05VS

1 2

R186 49.9_0402_1%R186 49.9_0402_1%

1 2

R188 750_0402_1%R188 750_0402_1%

4mil width and place within 500mil of the PCH

+3VS

1 2

R24 1K _0402_5%R24 1K_0402_5%

1 2

R197 0_0402_5%@R197 0_0402_5%@

1 2

R198 0_0402_5%@R198 0_0402_5%@

1 2

D3

PCH_GPIO72[14]

RI#[14]

1

T8

TPC12T8TPC12

APWROK

RB751V-40_SOD323-2

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

SUSACK#_R

SYS_RST#

SYS_PWROK

PCH_POK_R

PM_DRAM_PWRGD

SUSWARN#

AC_PRESENT_R

PCH_GPIO72

RI#

VGATE[48]

U2408C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

P+

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/ SUSPWRDNACK/ GPIO30

E20

H20

E10

A10

MC74VHC1G08DFT2G_SC70-5

P+

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

RI#

PANTHER-POINT_FCBGA989

PCH_PWROK

3

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

DMI

FDI

DMI

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

System Power Management

SLP_S3#

SLP_A#

P-

P+

+3VS

U9

1

IN1

2

IN2

5

VCC

OUT

GND

3

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

4

SYS_PWROK

12

R211

R211 100K_0402_5%

100K_0402_5%

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

EC_RSMRST#

PCIE_WAKE#

PM_CLKRUN#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PCH_SLPA#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

4

1

FDI_CTX_PRX_N0 [5] FDI_CTX_PRX_N1 [5] FDI_CTX_PRX_N2 [5] FDI_CTX_PRX_N3 [5] FDI_CTX_PRX_N4 [5] FDI_CTX_PRX_N5 [5] FDI_CTX_PRX_N6 [5] FDI_CTX_PRX_N7 [5]

FDI_CTX_PRX_P0 [5] FDI_CTX_PRX_P1 [5] FDI_CTX_PRX_P2 [5] FDI_CTX_PRX_P3 [5] FDI_CTX_PRX_P4 [5] FDI_CTX_PRX_P5 [5] FDI_CTX_PRX_P6 [5] FDI_CTX_PRX_P7 [5]

FDI_INT [5]

FDI_FSYNC0 [5]

FDI_FSYNC1 [5]

FDI_LSYNC0 [5]

FDI_LSYNC1 [5]

PCIE_WAKE# [14,33]

PM_CLKRUN# [18]

SUSCLK [38]

T11T11

PM_SLP_S5# [38]

T12T12

PM_SLP_S4# [38]

T13T13

PM_SLP_S3# [38]

T16T16

T14T14

T15T15

H_PM_SYNC [6]

5

DSWODVREN

DSWODVREN - On Die DSW VR Enable

烉

Enable

H

*

烉

Disable

L

PCH_GPIO29

PM_CLKRUN#

EC team suggestion South Bridge side must have pull-low 10K on this pin(GPIO32) Use CLKRUN# Requires a 8.2- k weak pull-up resistor to Vcc3_3S

Can be left NC when IAMT is not support on the platfrom

1 2

R185 330K_0402_5%R185 330K_0402_5%

1 2

R187 330K_0402_5%@R187 330K_0402_5%@

1 2

R195 10K_0402_5%@R195 10K_0402_5%@

1 2

R199 10K_0402_5%@R199 10K_0402_5%@

+RTCVCC

+3V_PCH

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PCH (3/8) DMI,FDI,PM,

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

LA-9611P

5

of

15 53Tuesday, February 26, 2013

0.4

1

A A

R253 100K_0402_5%R253 100K_0402_5%

B B

C C

12

ENBKL

2

U2408D

ENBKL[38] PCH_ENVDD[30]

PCH_PWM[30]

CRT_IREF

R223

1K_0402_5%

1 2

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

3

P-

SDVO_TVCLKINN

P-

SDVO_TVCLKINP

P-

SDVO_STALLN

P-

LVDS

CRT

SDVO_STALLP

P-

SDVO_INTN

P-

SDVO_INTP

SDVO_CTRLCLK

P-

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

P-

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

Digital Display Interface

DDPD_CTRLCLK

P-

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

4

AP43 AP45

AM42 AM40

AP39 AP40

P38

HDMICLK_NB

M39

HDMIDAT_NB

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46

PCH_DPC_CLK PCH_DPC_CLK

P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47

PCH_DPC_N2

BA48

PCH_DPC_P2

BB47

PCH_DPC_N3

BB49

PCH_DPC_P3

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

ŝŐŝƚĂůŝƐƉůĂǇWŽƌƚƐŶĂďůĞĂŶĚŝƐĂďůĞ'ƵŝĚĞůŝŶĞƐ

WŽƌƚ ^ƚƌĂƉ

>s^

WŽƌƚ

WŽƌƚ

WŽƌƚ

HDMICLK_NB [37] HDMIDAT_NB [37]

PCH_DPB_HPD [37]

PCH_DPB_N0 [37] PCH_DPB_P0 [37] PCH_DPB_N1 [37] PCH_DPB_P1 [37] PCH_DPB_N2 [37] PCH_DPB_P2 [37] PCH_DPB_N3 [37] PCH_DPB_P3 [37]

PCH_DPC_AUXN [31] PCH_DPC_AUXP [31] PCH_DPC_HPD [31]

PCH_DPC_N0 [31] PCH_DPC_P0 [31] PCH_DPC_N1 [31] PCH_DPC_P1 [31]

1 1

T222T222

1

T223T223

1

T224T224 T225T225

>ͺͺd

^sKͺdZ>d

WͺdZ>d

WͺdZ>d

HDMI

DP

,ŽǁƚŽŶĂďůĞ

WƵůůͲŚŝŐŚƚŽϯϯsǁŝƚŚϮϮŬͺϱйKŚŵ

HDMICLK_NB HDMIDAT_NB

PCH_DPC_DATPCH_DPC_DAT

,ŽǁƚŽŝƐĂďůĞ

EŽŽŶŶĞĐƚ

5

+3VS

12

R21482.2K_0402_1% R21482.2K_0402_1%

12

R21432.2K_0402_1% R21432.2K_0402_1%

12

R21462.2K_0402_5% @ R21462. 2K_0402_5% @

12

R21452.2K_0402_5% R21452.2K_0402_5%

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Rev

Custom

Date: Sheet of

LA-9611P

5

16 53Tuesday, February 26, 2013

0.4

1

A A

'EdϬη'Edϭη'W/Kϱϭ'EdϮη'W/Kϱϯ'Edϯη'W/Kϱϱ W/'ƌĂŶƚƐdŚĞW,ƐƵƉƉŽƌƚƐƵƉƚŽϰŵĂƐƚĞƌƐŽŶƚŚĞW/ ďƵƐ 'Ed΀ϯϭ΁ηƉŝŶƐĐĂŶŝŶƐƚĞĂĚďĞƵƐĞĚĂƐ'W/K WƵůůͲƵƉƌĞƐŝƐƚŽƌƐĂƌĞŶŽƚƌĞƋƵŝƌĞĚŽŶƚŚĞƐĞƐŝŐŶĂůƐ/ĨƉƵůůͲ ƵƉƐĂƌĞƵƐĞĚƚŚĞǇƐŚŽƵůĚďĞƚŝĞĚƚŽƚŚĞsĐĐϯͺϯƉŽǁĞƌƌĂŝů EKd^ ϭ'Ed΀ϯϭ΁η'W/K΀ϱϱϱϯϱϭ΁ĂƌĞƐĂŵƉůĞĚĂƐĂ ĨƵŶĐƚŝŽŶĂůƐƚƌĂƉ^ĞĞ^ĞĐƚŝŽŶϮϮϳĨŽƌĚĞƚĂŝůƐ

USB3_RX0_N[ 37] USB3_RX1_N[ 35] USB3_RX2_N[ 31]

USB3_RX0_P[37] USB3_RX1_P[35] USB3_RX2_P[31]

USB3_TX0_N[37] USB3_TX1_N[35] USB3_TX2_N[31]

USB3_TX0_P[37] USB3_TX1_P[35] USB3_TX2_P[31]

'W/KϱϬϱϮϱϰĚĞĨĂƵůƚсEĂƚŝǀĞ dŽƵĐŚƉĂŶĞů

DGPU_HOLD_RST#[23] TS_ON[30] DGPU_PWR_EN[25,47,51]

BT_DET#[35]

MSATS_DEVSLP[34]

PCI_PME#[38]

PCH_PLTRST#[6]

CLK_PCI_LPBACK[14] CLK_PCI_EC[38] CLK_PCI_DB[37] CLK_PCI_TPM[37]

PCH_PLTRST#

RP8

+3VS

PCH_GPIO4 PCH_GPIO5 PCH_GPIO2 PCH_GPIO3

+3VS

R239 10K_0402_5%R239 10K_0402_5%

R240 10K_0402_5%@R240 10K_0402_5%@

R235 10K_0402_5%@R235 10K_0402_5%@

R231 10K_0402_5%R231 10K_0402_5%

B B

R236 10K_0402_5%@R236 10K_0402_5%@

R246 10K_0402_5%R246 10K_0402_5%

R244 10K_0402_5%@R244 10K_0402_5%@

R232 10K_0402_5%@R232 10K_0402_5%@

R234 10K_0402_5%@R234 10K_0402_5%@

R190 10K_0402_5%R190 10K_0402_5%

R243 1K_0402_5%@R243 1K_0402_5%@

Boot BIOS Strap bit1 BBS1

C C

R245 1K_0402_5%@R245 1K_0402_5%@

A16 swap overide Strap/Top-Block Swap Override jumper

PCI_GNT3#

D D

RP8

1 2 3 4 5

10K_1206_10P8R_5%

1 2

GPIO19GPIO51

Bit11

Bit10

1

0

1

0

1 2

Low=A16 swap override/Top-Block Swap Override enabled High=Default

10 9 8 7 6

Boot BIOS Destination

Reserved

PCI

SPI

*

LPC

PCH_GPIO55

PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQA#

PCH_GPIO51

PCH_GPIO53

PCH_GPIO55

PCH_GPIO50

PCH_GPIO52

PCH_GPIO54

PCH_GPIO50

PCH_PLTRST#

PCH_GPIO52

PCH_GPIO51

(Default)

*

+3VS

2

R251 0_0402_5%@R251 0_0402_5%@

@

TC7SH08FUF_SSOP5

CLK_PCI_EC

1 2

+3VS

5

1

B

2

A

3

DIS@

U11

P

G

1 2

R254 0_0402_5%@R254 0_0402_5%@

1 2

R337 0_0402_5%@R337 0_0402_5%@

1 2

R264 0_0402_5%@R264 0_0402_5%@

1 2

R332 0_0402_5%@R332 0_0402_5%@

1 2

R296 0_0402_5%@R296 0_0402_5%@

1 2

R248 22_0402_5%R248 22_0402_5%

1 2

R249 22_0402_5%R249 22_0402_5%

1 2

R250 22_0402_5%R250 22_0402_5%

1 2

R350 22_0402_5%TPM@ R350 22_0402_5%TPM @

4

Y

12

R255

R255 100K_0402_5%

100K_0402_5%

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

PCH_GPIO51 PCH_GPIO53 PCH_GPIO55

PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5

PCH_PLTRST#

CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3

PLT_RST# [14,23,33,35,37,38]

U2408E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

RSVD

P-

PCI

USB

P+ P+ P+

P+

PPPPP-

RSVD23 RSVD24

RSVD25

RSVD26 RSVD27

RSVD28 RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

AV5 AV10

AT8

AY5 BA2

AT12 BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB20_N8 USB20_P8

1

1 USB20_N10 USB20_P10 USB20_N11 USB20_P11

Within 500 mils

USBRBIAS

R247 22.6_0402_1%R247 22.6_0402_1%

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4#

4

USB20_N0 [37] USB20_P0 [37] USB20_N1 [35] USB20_P1 [35] USB20_N2 [31] USB20_P2 [31] USB20_N3 [30] USB20_P3 [30]

USB20_N8 [30]

USB20_P8 [30] T26T26 T28T28

USB20_N10 [35]

USB20_P10 [35]

USB20_N11 [37]

USB20_P11 [37]

1 2

USB_OC0# [35,37]

KϬηh^ϯϬ;/KŽĂƌĚͿ;DͿ

h^ϯϬ;/KŽĂƌĚͿ

h^ϯϬ;DͿ

h^ϯϬ;ŽĐŬŝŶŐͿ

DK^ĂŵĞƌĂ;>s^Ϳ

;dĞƐƚWŽŝŶƚĨŽƌ/K^ĞďƵŐͿ

DŝŶŝĂƌĚ;t>EdͿ

&ŝŶŐĞƌWƌŝŶƚ

OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2

USB_OC1# USB_OC0# USB_OC2# USB_OC3#

USB_OC4#

1 8 2 7 3 6 4 5

R180 10K_0402_5%R180 10K_0402_5%

5

R233

10K_8P4R_5%

+3V_PCH

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

PCH (5/9) PCI, USB, NVRAM

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

LA-9611P

5

of

17 53Wednesday, February 27, 2013

0.4

Compal LA-9611P VIUS1, ThinkPad S431 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual