Compal LA-8241P QCL00, Inspiron N7520, Inspiron N5520, Vostro 3560, LA-8241P QCL20 Schematic

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-8241P

4619GP31L21
4619GQ31L21
4619GP31L01
4619GQ31L01

QCL00_QCL20

Inspiron DIS
Inspiron UMA
Vostro DIS
Vostro UMA

Dell / Compal Confidential

Schematic Document

2 2

Inspron A5 & Vostro 3560 (Intel Chief River)
Ivy Bridge(rPGA) + Panther Point(mainstream)

Discrete AMD Thames-XT

3 3

46@ : for 46 level

@ : Nopop Component

2012-02-01

Rev: 1.0

CONN@ : Connector Component
KB930@ : ENE KB930 Implemented

ConfigBOM P/NMB Type

KB9012@ : ENE KB9012 Implemented

EXP@ : Express Card Implemented

FFS@ : Only for Free Fall Sensor

VOS@ : Only for Vostro

4 4

INS@ : Only for Inspiron
UMA@ : Only for UMA

GCLK@ : Green CLK implemented
AMP@ : External Amplifier implemented

KBBL@ : Keyboard Back Light implemented

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

D

X76@ : VRAM Group

CH@ : Chelsea M2

SE@ : Seymour M2
TH@ : Thames-XT

DIS@ : Only for Discrete

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-8241P

E

1 56Wednesday, February 01, 2012

1.0

A

B

C

D

E

Compal Confidential

Fan Control

Project Code : QCL00 / QCL20
File Name : LA-8241P

1 1

64M*16

VRAM * 4
DDR3

CRT Conn.

2 2

LVDS Conn.

HDMI Conn.

Port 3 Port 1

Mini Card-1
WLAN / BT4.0

Half

3 3

P.32 P.32

Daughter board

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

4 4

A

P.27

41

P.

P.22

P.22

P.

23

Port 11

Express Card

34mm Slot

Daughter board

P.13

P.25

64bit

Port 2

P.28

64M*16

VRAM * 4
DDR3

AMD
Thames-XT /
Chelsea Pro
24-26 W

P.40

64bit

P.34~39

Ethernet
RTL8105E (10/100)

RTL8111F (10/100/1000)

RJ45

Daughter board

SPI ROM

4MB

SPI ROM

2MB

B

PEG 3.0 x16

CRT

LVDS

HDMI

USB2.0

PCI-E x1

P.13

P.13

Int.KBD

page 25

Intel
Ivy Bridge
Processor

35W QC
35W DC

100MHz 100MHz

2.7GT/s

rPGA 988
rPGA 988

Intel

Panther Point

PCH HM77

BGA 989 Balls

SPI

LPC Bus

SPI

PS/2

Touch Pad

33MHz

ENE KBC
KB9012 /
KB930

page 25

page 24

Dashboard

Button x3

Memory Bus (DDR3)

Dual Channel

1.5V DDR3 1333 MHz

P.5~10

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

DMI x4FDI x8

5GB/s

SATA3.0

USB 3.0

USB2.0

HD Audio

P13~20

Port 0

Port 1

Port 5

Port 2

Port 1,2

Port 0,1

Port 3,4

Port 2,3

Port 12

Port 4

Port 10

Port 8

SATA HDD Conn.

Mini Card-2 (mSATA)

( Full )

SATA ODD Conn.

USB 3.0 Conn. 1
USB 3.0 Conn. 2 -( USB Charger )

USB 3.0 Conn. 3
USB 3.0 Conn. 4

Digital Camera

Mini Card-1 (WLAN)

( Half )

Card Reader
RTS5139

Finger Print

Digital Mic.

Audio Codec
CX20672

SPI

SPI ROM

page 32

C

128K

page 26

reserved for KB930

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2012/01/17 2013/01/16

Amplifier
TPA3113D2

Compal Secret Data

Deciphered Date

P.25

8GB Max

P.30

P.31

D

CPU XDP
Conn.

page 11,12

P.29

P.32

Daughter board

P.29

P.33

P.32

Daughter board

P.22

P.32

Daughter board

P.32

P.32

P.6

FFS

P.29

3 in 1 Socket

Daughter board

Headphone Jack

Mic. Jack

Int. Speaker R/L

Size Document Number Rev

Date: Sheet of

only for Vostro 3560

Title

Compal Electronics, Inc.

Block Diagram

LA-8241P

E

2 56Wednesday, February 01, 2012

1.0

A

B

C

D

E

Compal Confidential

Project Code : QCL00 / QCL20

le Name : LA-8241P

Fi

1 1

8

Led1

LS-8245P (Ins)
LS-8255P (Vos)

SW1

Led2

4 pin-Hot Bar

LED/B

pin-Hot Bar

Led1 Led2 Led3

SW1 SW2 SW3

LS-8241P (Ins) LED/B
LS-8251P (Vos)

8 pin

FFC

8 pin

JFC

Lid (Vostro)

LS-8242P (Ins) IO/B
LS-8252P (Vos)

FFC

4 pin

Touch Pad

L R

FFC

4 pin

JPWR

2 2

Lid (Inspiron)

4 pin

LA-8241P M/B

JLVDS
40 pin

80 pin
JBTB1

JFP
6 pin

(Vostro)

JCR2
4 pin

ostro)

(V

JCR1JLED
4 pin

(Inspiron)

Camera

FFC

4 pin

4 pin-Hot Bar

26

1

Card Reader/B

LS-8243P (Ins)
LS

-8253P (Vos)

40 pin

Wire

LCD Panel

JTP

4 pin

TP Led (Vos)

TP Led (Ins)

3 3

10 pin

JEXP
26 pin

FFC

10 pi

n

LS-8244P (Ins)
LS-8254P (Vos)

10 pin-Hot Bar

Led1

Led2 Led3 Led4

4 4

LED/B

Express Card

Top Side

Bottom Side

4 pin-Hot Bar

Finger Print/B
LS-8256P (Vos)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

E

3 56Wednesday, February 01, 2012

1.0

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

MEM_SMBCLK
MEM_SMBDATA

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%

100K +/- 5%
200K +/- 5%

NC

SOURCE

KB9012

KB9012

PCH

PCH

AD_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V

2.433 V

MINI2

MINI1 BATT SODIMM

V V

V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

2.200 V

3.300 V

Express
Card

V

V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

Thermal
Sensor

max

FFS VGA

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

VGA Thermal
Sensor

V

V

BOARD ID Table

Board ID

XDP

Charger

V

V

V

A

USB PORT#

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

1.0

QCL00 QCL20

0.1

0.2

0.3

1.0

Link

0.2

0.3

1.0

QCL01

PCH

0

1

2

3

4

5

6

7

8

9

10

11

USB conn.1

USB conn.2 - Power Share

USB conn.3

USB conn.4

MI

NI CARD-1 (WLAN)

NC

NC

NC

Finger Print

NC

Card Reader

Express Card

DESTINATION

12

CLKOUT

1 1

PCI0

PCI1

PCI2

PCI3

PCI4

CLK

DESTINATION

PCH_LOOPBACK

EC LPC

None

None

None

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7 None

CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

10/100/1G LAN

MINI CARD-1 WLAN

Express Card

None

None

None

None

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

None

None

None

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

DESTINATION

HDD

SSD

ODD

None

None

None

Symbol Note :

: means Digital Ground

: means Analog Ground

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

PCI EXPRESS

13

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

Camera

NC

DESTINATION

10/100/1G LAN

MINI CARD-1 (WLAN)

Express Card

None

None

None

None

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-8241P

4 56Wednesday, February 01, 2012

1.0

5

D D

DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>

C C

B B

FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15>
FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>
FDI_LSYNC1<15>

+VCCP

1 2

RC36 24.9_0402_1%

RC158 10K_0402_5%

@

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

+EDP_COM

12

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

CONN@

DMI

Intel(R) FDI

eDP

4

+VCCP

12

RC2

24.9_0402_1%

PEG_COMP

PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

CC9 220nF_0402_16V7KDIS@

1 2

CC10 220nF_0402_16V7KDIS@

1 2

CC11 220nF_0402_16V7KDIS@

1 2

CC12 220nF_0402_16V7KDIS@

1 2

CC13 220nF_0402_16V7KDIS@

1 2

CC14 220nF_0402_16V7KDIS@

1 2

CC15 220nF_0402_16V7KDIS@

1 2

CC16 220nF_0402_16V7KDIS@

1 2

CC25 220nF_0402_16V7KDIS@

1 2

CC26 220nF_0402_16V7KDIS@

1 2

CC27 220nF_0402_16V7KDIS@

1 2

CC28 220nF_0402_16V7KDIS@

1 2

CC29 220nF_0402_16V7KDIS@

1 2

CC30 220nF_0402_16V7KDIS@

1 2

CC31 220nF_0402_16V7KDIS@

1 2

CC32 220nF_0402_16V7KDIS@

1 2

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

3

PEG_ICOMPI and R COMPO signals s hould be shorted and routed
with - max lengt h = 500 mils - typical impedanc e = 43 mohms
PEG_ICOMPO signa ls should be ro uted with - max length = 500 mils

- typical impeda nce = 14.5 mohm s

PEG_GTX_C_HRX_N7 <34>
PEG_GTX_C_HRX_N6 <34>
PEG_GTX_C_HRX_N5 <34>
PEG_GTX_C_HRX_N4 <34>
PEG_GTX_C_HRX_N3 <34>
PEG_GTX_C_HRX_N2 <34>
PEG_GTX_C_HRX_N1 <34>
PEG_GTX_C_HRX_N0 <34>

PEG_GTX_C_HRX_P7 <34>
PEG_GTX_C_HRX_P6 <34>
PEG_GTX_C_HRX_P5 <34>
PEG_GTX_C_HRX_P4 <34>
PEG_GTX_C_HRX_P3 <34>
PEG_GTX_C_HRX_P2 <34>
PEG_GTX_C_HRX_P1 <34>
PEG_GTX_C_HRX_P0 <34>

PEG_HTX_C_GRX_N7 <34>
PEG_HTX_C_GRX_N6 <34>
PEG_HTX_C_GRX_N5 <34>
PEG_HTX_C_GRX_N4 <34>
PEG_HTX_C_GRX_N3 <34>
PEG_HTX_C_GRX_N2 <34>
PEG_HTX_C_GRX_N1 <34>
PEG_HTX_C_GRX_N0 <34>

PEG_HTX_C_GRX_P7 <34>
PEG_HTX_C_GRX_P6 <34>
PEG_HTX_C_GRX_P5 <34>
PEG_HTX_C_GRX_P4 <34>
PEG_HTX_C_GRX_P3 <34>
PEG_HTX_C_GRX_P2 <34>
PEG_HTX_C_GRX_P1 <34>
PEG_HTX_C_GRX_P0 <34>

2

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

1

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267

B19

VSS268

B17

VSS269

B15

VSS270

B13

VSS271

B11

VSS272

B9

VSS273

B8

VSS274

B7

VSS275

B5

VSS276

B3

VSS277

B2

VSS278

A35

VSS279

A32

VSS280

A29

VSS281

A26

VSS282

A23

VSS283

A20

VSS284

A3

VSS285

Sandy Bridge_rPGA_Rev1p0

CONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-8241P

1

of

5 56Wednesday, February 01, 2012

1.0

5

XDP_PREQ#_R
XDP_PRDY#_R

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2
XDP_BPM#3

CFG10_R

RC130_0402_5% @

1 2
1 2

1 2
1 2

1 2

+VCCP

1 2

12
12

CFG11_R

RC150_0402_5% @

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

H_CPUPWRGD_XD P

RC221K_0402_5% @

CFD_PWRBTN#_X DP

RC230_0402_5% @

XDP_HOOK2

RC241K_0402_5% @

SYS_PWROK_XDP

RC260_0402_1% @

XDP_TCK1

RC30

XDP_TCK_R

H_THERMTRIP#<17>

H_PM_SYNC<15>

H_CPUPWRGD<17>

D D

C C

B B

A A

CFG10<8>
CFG11<8>

H_CPUPWRGD

CFG0<8>

VGATE<15,50>

PCH_JTAG_TCK<13>

The resistor
for HOOK2 should be
placed such that the
stub is very sma ll
on CFG0 net

H_PROCHOT#<24,44>

PCH_SMBDATA<11,12,14,28,29,32>
PCH_SMBCLK<11,12,14,28,29,32>

0_0402_5% @

RC43

62_0402_5%

+VCCP +VCCP

+3VALW

12

@

RC27
1K_0402_5%

SYS_PWROK_XDP

H_SNB_IVB#<17>

T1PAD~D @

H_PECI<17,24>

1 2

56_0402_1%

1 2

1 2

VDDPWRGOOD

CC64

1 2

@

10P_0402_50V8J

1 2

130_0402_1%~D

H_CPUPWRGD_R

4

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

CONN@

H_CATERR#

RC41

H_PROCHOT#_R

H_THERMTRIP#

@

H_PM_SYNC_R

RC49
0_0402_1%

@

H_CPUPWRGD_R

RC53
0_0402_1%

RC57

VDDPWRGOOD_R

BUF_CPU_RST#

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

JCPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

Sandy Bridge_rPGA_Rev1p0

CONN@

3

PM_DRAM_PWR GD<15>

PCH_PWROK<15,24>

SYS_PWROK<15>

+3V_PCH

1 2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

CLK_CPU_ITP

40

CLK_CPU_ITP#

42
44

XDP_RST#_R

46

XDP_DBRESET#

48
50

XDP_TDO

52

TD0

TDI

XDP_TRST#_R

54

XDP_TDI

56

XDP_TMS_R

58
60

+VCCP

@

1 2

RC25 1K_0402_5%

RC28 0_0402_5%@

1 2

RC31 0_0402_5%@

1 2

RC29 0_0402_5%@

1 2

0.1U_0402_16V7K

1

CC35

2

0.1U_0402_16V7K

1

CC36

2

CLK_CPU_ITP <14>
CLK_CPU_ITP# <14>PBTN_OUT#<15,24>

PLT_RST#

PCH_JTAG_TDO <13>

PCH_JTAG_TDI <13>
PCH_JTAG_TMS <13>

Place near JXDP1

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

PRDY#

PREQ#

TCK
TMS

TRST#

TDI

TDO

DBR#

BPM#[0]

JTAG & BPM

BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

CLK_CPU_DMI_R

A28

CLK_CPU_DMI#_R

A27

CLK_CPU_DPLL_R

A16

CLK_CPU_DPLL#_R

A15

Remove DPLL Ref clock (for eDP only)

H_DRAMRST#

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

DDR3 Compe nsation Si gnals

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCK

AR26

XDP_TMS

AR27

XDP_TRST#

AP30

XDP_TDI_R

AR28

XDP_TDO_R

AP26

XDP_DBRESET#_R

AL35

XDP_BPM#0_R

AT28

XDP_BPM#1_R

AR29

XDP_BPM#2_R

AR30

XDP_BPM#3_R

AT30

XDP_BPM#4_R

AP32

XDP_BPM#5_R

AR31

XDP_BPM#6_R

AT31

XDP_BPM#7_R

AR32

XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

RC37 0_0402_1%@

1 2

RC38 0_0402_1%@

1 2

RC39 1K_0402_1%

1 2

RC40 1K_0402_1%

1 2

H_DRAMRST# <7>

1 2
1 2
1 2

RC121 0_0402_5%@

1 2

RC122 0_0402_5%@

1 2

RC123 0_0402_1%@

1 2

RC124 0_0402_1%@

1 2

RC125 0_0402_1%@

1 2

RC50 0_0402_1%@

1 2

RC51 0_0402_1%@

1 2

1 2

RC56

RC59 0_0402_5%@

1 2

RC61 0_0402_5%@

1 2

RC62 0_0402_5%@

1 2

RC63 0_0402_5%@

1 2

RC64 0_0402_5%@

1 2

RC65 0_0402_5%@

1 2

RC66 0_0402_5%@

1 2

RC67 0_0402_5%@

1 2

RC68 0_0402_5%@

1 2

RC69 0_0402_5%@

1 2

RC70 0_0402_5%@

1 2

RC71 0_0402_5%@

1 2

0_0402_1%@

0_0402_1%

RC4

200_0402_1%

RC55140_0402_1%
RC5825.5_0402_1%
RC60200_0402_1%

XDP_TDI
XDP_TDO

XDP_DBRESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

2

RC128

RC127

@

1 2

1 2

RC11 0_0402_1%

RUN_ON_CPU1.5VS3#<10,27>

PLT_RST#<16,24,28,32>

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

CFG12 < 8>
CFG13 < 8>
CFG14 < 8>
CFG15 < 8>

+3VS

12

@

@

RC6

10K_0402_5%

1 2

0_0402_5%

D_PWG

@

CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>

+VCCP

XDP_DBRESET# <15>

UC1

1
2

5

B

VCC

A

4

GND3Y

74AHC1G09GW TSSOP 5P

RUN_ON_CPU1.5VS3#

UC2

1

NC

VCC

2

A
GND3Y

SN74LVC1G07DCKR_SC70-5~D

+3V_PCH

0.1U_0402_16V7K

+1.5V_CPU_VDDQ

CC33

1

2

RC19

@

39_0402_1%

1 2

13

D

QC1

2

G

SSM3K7002F_SC59-3

S

@

+3VALW

0.1U_0402_16V7K

1

CC34

2

5

BUFO_CPU_RST#

4

PU/PD for JTAG signa ls

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

XDP_DBRESET#

H_CPUPWRGD_R

1

12

RC8
200_0402_1%

VDDPWRGOOD

RC8
CRB 1.1K
CHECK LIST 0.7 - -> 4.75K
INTEL recommand 1.1K
PDG 0.71 rev --> 200

+VCCP

12

RC32
75_0402_5%

RC33

1 2

43_0402_1%

1

2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

BUF_CPU_RST#

0.1U_0402_16V7K

12

CC63

RC4551_0402_5%

RC4651_0402_5%

RC4751_0402_5% @

RC4851_0402_5%

RC5251_0402_5%

RC5451_0402_5%

+3VS

RC421K_0402_5%

RC4410K_0402_5%

@

RC34
0_0402_5%

+VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

LA-8241P

1

6 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

JCPU1C

M_CLK_DDR0

DDR_A_D[0..63]<11>

D D

C C

B B

A A

DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>

DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>

H_DRAMRST#<6>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

H_DRAMRST#

4.99K_0402_1%

RC77

AP11
AN11

AL12
AM12
AM11

AL11

AP12

AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10

AF10

C5
D5
D3
D2
D6
C6
C2
C3

F10

F8

G10

G9
F9
F7
G8
G7
K4
K5
K1

J1
J5
J4

J2
K2
M8

N10

N8
N7

M10

M9
N9
M7

AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8

V6

AE8
AD9
AF9

12

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

Sandy Bridge_rPGA_Rev1p0

CONN@

@

1 2

RC74 0_0402_5%

QC2

BSS138_SOT23

S

G

2

DDR SYSTEM MEMORY A

D

DDR3_DRAMRST#_R

13

DRAMRST_CNTRL

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

+1.5V

12

RC75
1K_0402_5%

1 2

RC76 1K_0402_5%

M_CLK_DDR#0
DDR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0
M_ODT1

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

@

1 2

RC72 0_0402_1%

M_CLK_DDR0 <11>
M_CLK_DDR#0 <11>
DDR_CKE0_DIMMA <11>

M_CLK_DDR1 <11>
M_CLK_DDR#1 <11>
DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA# <11>
DDR_CS1_DIMMA# <11>

M_ODT0 <11>
M_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR3_DRAMRST# <11,12>

DRAMRST_CNTRL_PCH <14>

DRAMRST_CNTRL <11>

DDR_B_D[0..63]<12>

DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>

DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_WE#<12>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

JCPU1D

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

Sandy Bridge_rPGA_Rev1p0

CONN@

M_CLK_DDR2

AE2

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_CLK_DDR#2
DDR_CKE2_DIMMB

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT2
M_ODT3

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <12>
M_CLK_DDR#2 <12>
DDR_CKE2_DIMMB <12>

M_CLK_DDR3 <12>
M_CLK_DDR#3 <12>
DDR_CKE3_DIMMB <12>

DDR_CS2_DIMMB# <12>
DDR_CS3_DIMMB# <12>

M_ODT2 <12>
M_ODT3 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

1

CC37
.047U_0402_16V7K

2

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

LA-8241P

1

7 56W ednesday, February 01, 2012

1.0

5

4

3

2

1

CFG Straps for Processor

D D

JCPU1E

L7

RSVD28

AG7

CFG0<6>

T85PAD~D @

T86PAD~D @

T87PAD~D @
T88PAD~D @

T89PAD~D @
T90PAD~D @

RC159

12

10K_0402_5%

CFG10<6>
CFG11<6>
CFG12<6>
CFG13<6>
CFG14<6>
CFG15<6>

1 2

+VCC_GFXCORE_AXG

@

RC79
50_0402_1%

1 2

12

@

RC84

1K_0402_1%

VCC_AXG_VAL_SENSE

VCC_VAL_SENSE

+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ

12

@

RC85
1K_0402_1%

+3VS

+VCC_CORE

@

RC80
50_0402_1%

C C

+SA_DIMM_VREFDQ

+SB_DIMM_VREFDQ

B B

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

T19PAD~D @

T25PAD~D @
T26PAD~D @
T27PAD~D @
T28PAD~D @
T30PAD~D @
T32PAD~D @
T33PAD~D @
T34PAD~D @
T35PAD~D @ T36 PAD~D@
T37PAD~D @
T38PAD~D @
T39PAD~D @
T40PAD~D @
T41PAD~D @
T42PAD~D @
T43PAD~D @

T44PAD~D @
T45PAD~D @

H_VCCP_SEL

T49PAD~D @

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

Sandy Bridge_rPGA_Rev1p0

CONN@

RESERVED

RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

KEY

T2 PAD~D@
T3 PAD~D@
T4 PAD~D@
T5 PAD~D@
T6 PAD~D@

T7 PAD~D@
T8 PAD~D@
T9 PAD~D@

T10 PAD~D@
T11 PAD~D@
T12 PAD~D@
T13 PAD~D@

T14 PAD~D@
T15 PAD~D@
T16 PAD~D@
T17 PAD~D@
T18 PAD~D@

PEG Static Lane Reversal - CFG2 is for the 16x

Display Port Presence Strap

T20 PAD~D@
T21 PAD~D@
T22 PAD~D@
T23 PAD~D@
T24 PAD~D@

T29 PAD~D@
T31 PAD~D@

CLK_RES_ITP <14>
CLK_RES_ITP# <14>

T46 PAD~D@
T47 PAD~D@
T48 PAD~D@

T50 PAD~D@

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

12

RC78
1K_0402_1%

1:(Default) Norm al Operation; L ane #

CFG2

definition match es socket pin m ap definition

0:Lane Reversed

*

CFG4

12

RC81

@

1K_0402_1%

1 : Disabled; No Physical Displ ay Port

*

CFG4

attached to Embe dded Display Po rt

0 : Enabled; An external Displa y Port device is
connected to the Embedded Displ ay Port

CFG6

CFG5

1K_0402_1%

RC87

12

12

RC86

@

1K_0402_1%

11: (Default) x1 6 - Device 1 fu nctions 1 and 2 disabled

10: x8, x8 - Dev ice 1 function 1 enabled ; func tion 2

*

disabled
01: Reserved - ( Device 1 functi on 1 disabled ; functi
2 enabled)
00: x8,x4,x4 - D evice 1 functio ns 1 and 2 enabl ed

CFG7

12

RC89

@

1K_0402_1%

on

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

@

RC90

50_0402_1%

A A

INTEL 12/28 reco mmand

add RC120, RC12 1, RC122, RC123

to

Please place as close as JCPU1

5

@

RC91
50_0402_1%

1 2

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

PEG DEFER TRAINING

1: (Default) PEG Train immediat ely

*

CFG7

following xxRESE TB de assertion

0: PEG Wait for BIOS for traini ng

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

LA-8241P

8 56W ednesday, February 01, 2012

1

of

1.0

5

4

3

2

1

QC=94A
DC=53A

POWER

PEG AND DDR

CORE SUPPLY

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

8.5A

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

B10
A10

RC111

10_0402_1%

+VCCP

130_0402_1%~D

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

12

12

RC95

RC95 close to CPU

RC94 43_0402_1%
RC92 0_0402_1%@
RC96 0_0402_1%@

RC98 0_0402_1%@

1 2

RC99 0_0402_1%@

1 2

RC108

12

10_0402_1%

1 2
1 2
1 2

+VCCP

VCCIO_SENSE <47>

+VCCP

12

+VCC_CORE

12

12

RC93
75_0402_5%

RC97
100_0402_1%

RC100
100_0402_1%

Place the PU
resistors close to CPU

VR_SVID_ALRT# <50>
VR_SVID_CLK <50>
VR_SVID_DAT <50>

VCCSENSE <50>
VSSSENSE <50>

JCPU1F

+VCC_CORE

AG35

D D

C C

B B

A A

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev1p0

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

LA-8241P

9 56W ednesday, February 01, 2012

1

1.0

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

B+_BIAS+3VALW

12

RC102
100K_0402_5%

2

1

@

CC40

0.1U_0402_10V7K~D

2

+VCC_GFXCORE_AXG

10U_0805_4VAM~D

10U_0805_4VAM~D

@

1

1

CC61

2

2

RUN_ON_CPU1.5VS3#

61

QC5A
2N7002DW-7-F_SOT363-6

33A

AT24
AT23
AT21
AT20
AT18

AT17
AR24
AR23
AR21
AR20
AR18
AR17

AP24

AP23

AP21

AP20

AP18

AP17

AN24

AN23

AN21

AN20

AN18

AN17
AM24
AM23
AM21
AM20
AM18
AM17

AL24

AL23

AL21

AL20

AL18

AL17

AK24

AK23

AK21

AK20

AK18

AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17

AH24

AH23

AH21

AH20

AH18

AH17

@

CC62

330U_D2_2.5VM_R6M~D

1

CC57

+

2

JCPU1G

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

1.2A

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev1p0

CONN@

D D

RC104

@

SUSP#<24,27,28,46,47,48>

CPU1.5V_S3_GATE<24>

C C

B B

+1.8VS

RC109 0_0805_1%@

1 2

1 2

0_0402_5%

RC107

1 2

0_0402_5%

+1.8VS_VCCPLL

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_4VAM~D

1

1

1

2

CC56

CC55

CC54

2

2

12

RC101
100K_0402_5%

RUN_ON_CPU1.5VS3

3

QC5B

5

2N7002DW-7-F_SOT363-6

4

RUN_ON_CPU1.5VS3# <6,27>

POWER

VSSAXG_SENSE

SENSE

LINES

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

1.8V RAIL

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

FC_C22

VCCSA_VID1

QC3

AO4728L_SO8~D

8
7
6
5

1
2

12

3

1

4

CC38

2

RC103

10U_0805_10V6K

+VCC_GFXCORE_AXG

1 2

@

RC114

1 2

10_0402_1%

1K_0402_5%

20K_0402_5%

RC126

1 2

RC129 1K_0402_5%

1 2

RC106 0_0402_5%@

3

12

2

0.1U_0603_50V_X7R

12

1

CC39

2

RC105

330K_0402_1%

RC113

1 2

10_0402_1%

VCC_AXG_SENSE

RC157 100_0402_1%

VSS_AXG_SENSE

AK35
AK34

+V_SM_VREF should
have 10 mil trace width

+V_SM_VREF_CNT +V_SM_VREF

AL1

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

6A

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

10U_0805_4VAM~D

1

1

CC41

2

2

10U_0805_4VAM~D

1

CC49

2

VCCSA_VID0 <49>
VCCSA_VID1 <49>

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

CC43

CC44

CC42

2

2

10U_0805_4VAM~D

10U_0603_6.3V6M

10U_0805_4VAM~D

1

2

@

1

1

CC51

CC52

CC50

2

2

VCC_AXG_SENSE <50>

VSS_AXG_SENSE <50>

+1.5V_CPU_VDDQ

1

@

QC4

NTR4503NT1G_SOT23-3~D

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

1

CC45

CC46

+

2

2

2

1

+

CC48
330U_D2_2VM_R6M~D

2

VCCSA_SENSE <49>

12

RC110

@

0_0402_5%

CC47
330U_D2_2VM_R6M~D

+VCCSA

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

+1.5V

12

@

1K_0402_5%
RC112

12

1K_0402_5%

@

RC116

@

JP10

1 2

PAD-OPEN 4x4m

J8 OPEN

+1.5V_CPU_VDDQ +1.5V

add CC181 , CC182, 4 caps ar e all pop.
fo

+1.5V

CC53 0.1U_0402_10V7K~D

12

CC58 0.1U_0402_10V7K~D

12

CC59 0.1U_0402_10V7K~D

12

CC60 0.1U_0402_10V7K~D

12

llow checklist 1.0 5/24

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

Sandy Bridge_rPGA_Rev1p0

CONN@

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(6/6) PWR,VSS

Size Document Number Rev

LA-8241P

Date: Sheet of

1

10 56Wednesday, February 01, 2012

1.0

5

+V_DDR_REFA

330U_SX_2VY~D

1

CD13

+

2

+V_DDR_REFA

CD14

DDR_A_DQS#[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_MA[0..15]<7>

D D

Layout Note:
Place near JDIMM1

+1.5V

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C C

+1.5V

10U_0603_6.3V6M

B B

+0.75VS

A A

CD4

CD3

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD7

CD8

1

1

2

2

Layout Note:
Place near JDIMM1.203,204

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD17

2

2

1U_0402_6.3V6K

CD5

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD10

CD9

1

1

2

2

1U_0402_6.3V6K

1

1

CD19

CD18

2

2

+1.5V

12

12

All VREF traces should
have 10 mil trace width

CD6

10U_0603_6.3V6M

10U_0603_6.3V6M

CD12

CD11

1

1

2

2

1U_0402_6.3V6K

CD20

RD1
1K_0402_1%

RD3
1K_0402_1%

@

1

2

4

+1.5V

1

CD2

2

2.2U_0603_6.3V6K

CD22

1

2

+V_DDR_REFA

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

1 2

RD6 10K_0 402_5%

1 2

RD7 10K_0 402_5%

+0.75VS

0.1U_0402_16V7K

2.2U_0603_6.3V6K

1

CD1

2

DDR_CKE0_DIMMA<7> DDR_CKE1_DIMMA <7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

0.1U_0402_16V7K

CD21

1

2

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

BELLW_80001-5021
CO

NN@

DQ4
DQ5

VSS3

DQS#0

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1
CK1#

VDD12

BA1
RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

A15
A14

A11

S0#

A7

A6
A4

A2
A0

G2

3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

+1.5V

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#
M_ODT0

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

PCH_SMBDATA <6,12,14,28,29,32>
PCH_SMBCLK <6,12,14,28,29,32>

+VREF_CA

2.2U_0603_6.3V6K

2

DDR3_DRAMRST# <7,12>

+1.5V

12

RD4
1K_0402_1%

0.1U_0402_16V7K

1

1

CD15

2

2

12

RD5
1K_0402_1%

CD16

RD8 0_0402_5%@

RD9 0_0402_5%@

1 2

S

G

1 2

S

G

DRAMRST_CNTRL<7>

M3

+SA_DIMM_VREFDQ

DRAMRST_CNTRL

+SB_DIMM_VREFDQ

DRAMRST_CNTRL

QD1

D

BSS138_NL_SOT23-3

13

2

QD2

D

BSS138_NL_SOT23-3

13

2

1

+V_DDR_REFA

+V_DDR_REFB

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

LA-8241P

1

11 56Wednesday, February 01, 2012

1.0

5

+1.5V

12

D D

C C

B B

A A

DDR_B_DQS#[0..7]<7>

DDR_B_DQS[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_MA[0..15]<7>

+1.5V

1U_0402_6.3V6K

1U_0402_6.3V6K

CD28

1

1

2

2

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD32

CD33

1

2

Layout Note:
Place near JDIMMB.203,204

+0.75VS

1

1

2

2

1U_0402_6.3V6K

1

1

CD42

2

2

Layout Note:
Place near JDIMMB

1U_0402_6.3V6K

1U_0402_6.3V6K

CD29

CD30

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD34

CD35

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD44

CD43

2

12

CD31

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD37

CD36

1

2

1U_0402_6.3V6K

1

CD45

2

@

330U_SX_2VY~D

@

1

CD39

CD38

1

+

2

2

RD15
1K_0402_1%

RD16
1K_0402_1%

4

+V_DDR_REFB

+V_DDR_REFB

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

All VREF traces should
have 10 mil trace width

+3VS

10K_0402_5%

2.2U_0603_6.3V6K

RD19

3

+1.5V

1

2

CD26

12

+V_DDR_REFB

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

0.1U_0402_16V7K

CD46

1

2

2.2U_0603_6.3V6K

+0.75VS

1

2

CD47

0.1U_0402_16V7K

1

CD27

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

12

10K_0402_5%

RD20

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

BELLW_80001-1021

CONN@

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1
CK1#

VDD

BA1

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84

A11

86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114

S0#

116
118
120
122

NC

124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

+1.5V

2

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31DDR_B_D27

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2

M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

DDR3_DRAMRST# <7,11>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

2.2U_0603_6.3V6K

1

2

PCH_SMBDATA <6,11,14,28,29,32>
PCH_SMBCLK <6,11,14,28,29,32>

RD17
1K_0402_1%

0.1U_0402_16V7K

1

CD40

CD41

2

+1.5V

12

12

RD18
1K_0402_1%

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

LA-8241P

1

12 56Wednesday, February 01, 2012

1.0

5

PCH_RTCX1

ME_EN<24>

12

RH19

@

200_0402_5%

12

RH25
100_0402_1%

PCH_RTCX2

1

CH4
18P_0402_50V8J

2

1 2

RH5 33_0402_5%

1 2

RH6 33_0402_5%

1 2

RH7 33_0402_5%

1 2

RH8 1M_0402_5%

12

12

PCH_RTCX1_R<31>

+RTCVCC

+RTCVCC

1U_0603_10V6K

1 2

RH3 20K_0402_5%

1 2

RH4 20K_0402_5%

1U_0603_10V6K

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R SATA_PTX_DRX_P1

1 2

RH11 1K_0402_1%

1 2

RH15 33_0402_5%

RH20

@

200_0402_5%

RH26

100_0402_1%

RH30 0_0402_5%

RH2

1 2

1

CH5

2

1

CH6

2

+5VS

G

2

13

D

S

QH1BSS138_SOT23

@

1 2

RH9 0_0402_5%

HDA_SDOUT

HDA_SDOUT

12

SHORT PADS

12

SHORT PADS

CLP1 & CLP2 place near DIMM

HDA_SYNC

close to YH1

1 2

GCLK@

1M_0402_5%

CMOS

CLRP1

CLRP2

ME CMOS

HDA_SPKR<30>

HDA_SDIN0<30>

PCH_JTAG_TCK<6>

PCH_JTAG_TMS<6>

PCH_JTAG_TDI<6>

PCH_JTAG_TDO<6>

PCH_RTCX1

SM_INTRUDER#

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_CS1#

PCH_SPI_SI

PCH_SPI_SO

1 2

RH1 10M_0402_5%

YH1

1 2

32.768KHZ_12.5PF_9H03200019

18P_0402_50V8J

1

CH3

2

D D

keep away hot s pot

HDA_BITCLK_AUDIO<30>

HDA_RST_AUDIO#<30>

HDA_SYNC_AUDIO<30>

C C

HDA_SDOUT_AUDIO<30>

+3V_PCH +3V_PCH+3V_PCH

12

RH18

@

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

RH24

100_0402_1%

B B

4

@

HDA_SDOUT

12

CH1 10P_0402_50V8J

@

HDA_BIT_CLK

12

CH2 10P_0402_50V8J

Reserve for RF please close t o UH1

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

BD82HM77 QPRG C1 BGA 989P PCH

SA00005AG1L

RTCIHDA

JTAG

SPI

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA

SATA0GP / GPIO21

SATA1GP / GPIO19

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN

SATA 6G

SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

UH1

BD82HM77 QPRG C1 BGA 989P PCH

SA00005AG1L

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36

E36
K36

SERIRQ

V5

AM3
AM1

SATA_PTX_DRX_N0

AP7

SATA_PTX_DRX_P0

AP5

AM10
AM8

SATA_PTX_DRX_N1

AP11
AP10

AD7
AD5

SATA_PTX_DRX_N2

AH5

SATA_PTX_DRX_P2

AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

SATA_COMP

Y10

AB12

SATA3_COMP

AB13

RBIAS_SATA3

AH1

PCH_SATALED#

P3

HDD_DET#_R

V14

BBS_BIT0_R

P1

3

@

LPC_AD0 <24>
LPC_AD1 <24>
LPC_AD2 <24>
LPC_AD3 <24>

LPC_FRAME# <24>

SERIRQ <24>

CH7 0.01U_0402_16V7K

1 2

CH8 0.01U_0402_16V7K

1 2

CH18 0.01U_0402_16V7K

1 2

CH17 0.01U_0402_16V7K

1 2

CH9 0.01U_0402_16V7K

1 2

CH10 0.01U_0402_16V7K

1 2

1 2

RH21 37.4_0402_1%

1 2

RH22 49.9_0402_1%

1 2

RH28 750_0402_1%~D

RH268 0_0402_5%

1 2

RH29

+1.05VS_VCC_SATA

+1.05VS_SATA3

PCH_SATALED# <32>

10K_0402_5%

12

HDD_DET#

+3VS

SATA_PRX_DTX_N0 <29>
SATA_PRX_DTX_P0 <29>
SATA_PTX_DRX_N0_C <29>
SATA_PTX_DRX_P0_C <29>

SATA_PRX_DTX_N1 <32>
SATA_PRX_DTX_P1 <32>
SATA_PTX_DRX_N1_C <32>
SATA_PTX_DRX_P1_C <32>

SATA_PRX_DTX_N2 <29>
SATA_PRX_DTX_P2 <29>
SATA_PTX_DRX_N2_C <29>
SATA_PTX_DRX_P2_C <29>

HDD_DET# <29>

2

330K_0402_5%

PCH_INTVRMEN

RH13

RH16

@

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

HDA_SDO

ME debug mode , this signal has a weak internal PD

L

>security measures defined in the Flash

=

Descriptor will be in effect (default)

330K_0402_5%

+RTCVCC

12

12

H=>Flash Descriptor Security will be overridden

HDA_SYNC

HDD

mSATA

This signal has a weak intern al pull-down
On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low
Needs to be pul led High for H uron River plat from

ODD

JP12

2

+CHGRTC

112

JUMP_43X39

HDA_SYNC

+3VLP

SERIRQ

HDD_DET#

PCH_SATALED#PCH_INTVRMEN

HDA_SPKR

HDA_SDOUT

RH32 1K_0402_5%

W=20mils

1

RH10 10K_0402_5%

RH12 10K_0402_5%

RH14 10K_0402_5%

RH17 1K_0402_5%@

LOW=Default
HIGH=No Reboot

*

RH23 1K_0402_5%@

Low = Disabled

*

High = Enabled

12

+3V_PCH

12

RTC Battery

+RTCBATT

3

1 2

W=20mils

2

1

1

CH12
1U_0603_10V6K

2

RH34
1K_0402_5%

DH1
BAT54CW_SOT323-3

+CHGRTC

W=20mils

12

12

12

12

+3VS

+3VS

+3V_PCH

+RTCVCC

HOLD#

SCLK

+3V_PCH

0.1U_0402_16V7K

1

CH11

2

8

VCC

PCH_SPI_HOLD#PCH_SPI_SO_R

SI

7
6
5

PCH_SPI_CLK_R
PCH_SPI_SI_R

RH27 33_0402_5%
RH39 33_0402_5%

1

CH99

@

10P_0402_50V8J

2

PCH_SPI_CLK

12

PCH_SPI_SI

12

3

PCH_SPI_CS0#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RH264 0_0402_5%

1 2

RH265 33_0402_5%

+3V_PCH

SPI ROM FOR ME

MByte )

@

RH263

3.3K_0402_5%

12

2012/01/17 2013/01/16

( 4

PCH_SPI_CS0#_R

1 2

PCH_SPI_SO_LPCH_SPI_SO

Compal Secret Data

Deciphered Date

2

UH6

1

CS#

2
3
4

VCC

SO/SIO1

HOLD#

WP#

SCLK

GND

SI/SIO0

EN25Q32B-104HIP_SO8

EON EN25Q32B-104HIP_SO8

PCH_JTAG_TCK

+3V_PCH

1 2

RH38 3.3K_0402_5%

1 2

RH40 3.3K_0402_5%

1 2

RH35 51_0402_5%

PCH_SPI_WP#

PCH_SPI_HOLD#

NEC flash issue .

+3V_PCH

RH262

3.3K_0402_5%

PCH_SPI_SO

@

1 2

RH36 0_0402_5%

1 2

RH37 33_0402_5%

@

RH33

3.3K_0402_5%

12

+3V_PCH

SPI ROM FOR WIN8( 2MByte )

1 2

PCH_SPI_CS1#_RPCH_SPI_CS1#

PCH_SPI_WP#

UH2

1

CS#

2

SO

3

WP#

4

GND

EN25QH16-104HIP_SO8

EON EN25QH16-104HIP_SO8

A A

5

4

+3V_PCH

0.1U_0402_16V7K

1

CH98

2

8

PCH_SPI_HOLD#

7

PCH_SPI_CLK_L

6

PCH_SPI_SI_L PCH_SPI_SI

5

RH266 33_0402_5%

12
12

RH267 33_0402_5%

Title

PCH (1/8) SATA,HDA,SPI, LPC

Size Document Number Rev

LA-8241P

Date: Sheet of

PCH_SPI_CLKPCH_SPI_WP#

Compal Electronics, Inc.

1

13 56Wednesday, February 01, 2012

1.0

5

PCIE_PRX_LANTX_N1<32>

10/100/1G LAN --->

WLAN (Mini Card 1)--->

D D

Express Card --->

C C

10/100/1G LAN --->

WLAN (Mini Card 1)--->

Express Card --->

PCIE_PRX_LANTX_P1<32>
PCIE_PTX_LANRX_N1<32>
PCIE_PTX_LANRX_P1<32>

PCIE_PRX_WLANTX_N2<32>

PCIE_PRX_WLANTX_P2<32>
PCIE_PTX_WLANRX_N2<32>
PCIE_PTX_WLANRX_P2<32>

PCIE_PRX_EXPTX_N3<28>

PCIE_PRX_EXPTX_P3<28>
PCIE_PTX_EXPRX_N3<28>
PCIE_PTX_EXPRX_P3<28>

CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>

LAN_CLKREQ#<32>

CLK_PCIE_WLAN#<32>
CLK_PCIE_WLAN<32>

WLAN_CLKREQ#<32>

CLK_PCIE_EXP#<28>
CLK_PCIE_EXP<28>

EXPCLK_REQ#<28>

CH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~D

1 2

CH21 0.1U_0402_10V7K~D

1 2

CH22 0.1U_0402_10V7K~D

1 2

CH15 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~D

1 2

RH67 0_0402_5%
RH68 0_0402_5%

RH69 10K_0402_5%

+3V_PCH

RH75 0_0402_5%
RH76 0_0402_5%
RH77 10K_0402_5%

+3VS

RH79 0_0402_5%
RH80 0_0402_5%
RH81 10K_0402_5%

+3VS

+3V_PCH

RH74 10K_0402_5%

*PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2

B B

XTAL25_IN

CH28

XTAL25_OUT

CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>

27P_0402_50V8J

1

2

5

CLK_RES_ITP#<8>
CLK_RES_ITP<8>

PCH_X1<31>

12

RH891M_0402_5%

3

27P_0402_50V8J

1

CH27

A A

OSC1OSC

2

GND2GND

YH2

4

25MHZ_20PF_FSX3M-25.M20FDO

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

CLK_CPU_ITP#
CLK_CPU_ITP

RH41 0_0402_5%

RH66 10K_0402_5%

RH83 10K_0402_5%

RH84 10K_0402_5%

RH88 10K_0402_5%

RH90 10K_0402_5%

RH91 0_0402_5%
RH92 0_0402_5%

RH93 0_0402_5%@
RH94 0_0402_5%@

close to YH2

1 2

GCLK@

XTAL25_IN

1 2
1 2

1 2

1 2

1 2

1 2

1 2

12

12
12
12

12
12
12

12

12
12

12
12

4

PCIE_PRX_LANTX_N1
PCIE_PRX_LANTX_P1
PCIE_PTX_LANRX_N1_C
PCIE_PTX_LANRX_P1_C

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2_C
PCIE_PTX_WLANRX_P2_C

PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3_C
PCIE_PTX_EXPRX_P3_C

4

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PCIE_LAN#
PCIE_LAN

LAN_CLKREQ#

PCIE_WLAN#
PCIE_WLAN

WLAN_CLKREQ#

PCIE_EXP#
PCIE_EXP

EXPCLK_REQ#

GPIO25

GPIO26

GPIO44

GPIO56

GPIO45

GPIO46

CLK_BCLK_ITP#
CLK_BCLK_ITP

CLK_BCLK_ITP

CLK_PCH_14M

CLK_PCI_LPBACK

Reserve for EMI please close t o
UH1

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82HM77 QPRG C1 BGA 989P PCH

@

RH63

12

33_0402_5%

@

RH65

12

33_0402_5%

@

CH25

1 2

22P_0402_50V8J~D

@

CH26

1 2

22P_0402_50V8J~D

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

SMBALERT#

E12

SMBCLK

H14

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

PCH_HOT#

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

No support iAMT

P10

PEG_A_CLKRQ#

M10

CLK_PEG_VGA#

AB37

CLK_PEG_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12
AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

CLK_FLEX0

K43

CLK_14M_R

F47

CLK_LAN_25M_R

H47

DGPU_PRSNT#

K49

Total device

RH125

1 2

22_0402_5%

RH270 22_0402_5%

RH269 10K_0402_5%

RH261
10K_0402_5%DIS@

1 2

MEMORY

DRAMRST_CNTRL_PCH <7>

PCH_HOT# <24>

+3V_PCH

RH64
10K_0402_5%

1 2

CLK_PEG_VGA# <34>
CLK_PEG_VGA <34>

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

CLK_PCI_LPBACK <16>

1 2

RH85 90.9_0402_1%

@

12

12

UMA@

2

20090512
add double mosfet prevent
ATI M92 electric leakage

PEG_A_CLKRQ# <35>

+3VS

SMBCLK

SMBDATA

+1.05VS_VCCDIFFCLKN

T53 PAD~D@

T54 PAD~D@

CLK_LAN_25M <32>

6 1

DMN66D0LDW-7_SOT363-6

1 2

0_0402_5%

close to RH270

LAN_X1<31>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

RH31 0_0402_5%

Deciphered Date

2

1 2

CLK_LAN_25M

GCLK@

2

QH2A
RH78

@

3

DMN66D0LDW-7_SOT363-6

QH2B
RH82

@

1 2

0_0402_5%

SML1CLK

SML1DATA

1

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

SMBALERT#

PCH_HOT#

DRAMRST_CNTRL_PCH

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

If use extenal CLK gen, pleas e place close to CLK gen
else, please p lace close to P CH

+3VS

+3VS

RH71

2.2K_0402_5%

5

1 2

4

+3V_PCH

2

61

DMN66D0LDW-7_SOT363-6

QH3A

4

DMN66D0LDW-7_SOT363-6

QH3B

Title

PCH (2/8) PCIE, SMBUS, CLK

Size Document Number Rev

LA-8241P

Date: Sheet of

1 2

RH45 2.2K_0402_5%

1 2

RH46 2.2K_0402_5%

1 2

RH47 2.2K_0402_5%

1 2

RH49 2.2K_0402_5%

1 2

RH50 2.2K_0402_5%

1 2

RH51 2.2K_0402_5%

1 2

RH52 10K_0402_5%

1 2

RH86 10K_0402_5%

1 2

RH53 1K_0402_5%

RH54 10K_0402_5%

1 2

RH55 10K_0402_5%

1 2

RH56 10K_0402_5%

1 2

RH57 10K_0402_5%

1 2

RH58 10K_0402_5%

1 2

RH59 10K_0402_5%

1 2

RH60 10K_0402_5%

1 2

RH61 10K_0402_5%

1 2

RH62 10K_0402_5%

1 2

RH72

2.2K_0402_5%

1 2

PCH_SMBCLK <6,11,12,28,29,32>

PCH_SMBDATA <6,11,12,28,29,32>

5

3

Compal Electronics, Inc.

1

+3V_PCH

PCH_SMLCLK <24>

PCH_SMLDATA <24>

1.0

14 56Wednesday, February 01, 2012

5

Compal Electronics, Inc.

UH1C

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>

D D

XDP_DBRESET#<6>

C C

PM_DRAM_PWRGD<6>

GPIO72

B B

RI#

PCIE_WAKE#

AC_PRESENT_R

SUSWARN#

WAKE#

EC_RSMRST#

A A

DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

+1.05VS

SYS_PWROK

PCH_PWROK<6,24>

EC_RSMRST#<24>

PBTN_OUT#< 6,24>

ACIN<24,35, 43,44>

RH116 10K_0402_5%

1 2

RH117 10K_0402_5%

1 2

RH118 10K_0402_5%@

1 2

RH121 200K_0402_5%

1 2

RH124 10K_0402_5%

1 2

RH126 10K_0402_5%

1 2

RH127 10K_0402_5%

1 2

PCH_PWROK<6,24>

VGATE<6,50>

RH99 49.9_0402_1%

RH100 750_0 402_1%~D

4mil width and place
within 500mil of the PCH

T57PAD~D

PCH_PWROK

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

1 2

1 2

RH104 0_0402_5%

RH105 0_0402_5%

RH106 0_0402_5%

RH108 0_040 2_5%

RH110 0_040 2_5%

DMI_IRCOMP

RBIAS_CPY

XDP_DBRESET#

1 2

1 2

1 2

PM_DRAM_PWRGD

PCH_RSMRST#_R

1 2

1 2

DH4

1 2

RB751V-40_SOD323-2

GPIO72

+3V_PCH

+3VS

1

CH30

0.1U_0402_16V7K

2

1

IN1

2

IN2

SYS_PWROK_R

SUSWARN#

AC_PRESENT_R

RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82HM77 QPRG C1 BGA 989P PCH

DSWODVREN

DSWODVREN

DSWODVREN - On Die DSW VR Enable

*

5

UH3

VCC

SYS_PWROK

4

OUT

GND

MC74VHC1G08DFT2G_SC70-5

3

RH119 330K_0402_5%

RH122 330K_0402_5%@

H：Enable
L：Disable

SYS_PWROK <6>

4

FDI_CTX_PRX_N0

BJ14

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

12

12

+RTCVCC

AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

DSWODVREN

WAKE#

PM_CLKRUN#

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

1 2

RH107 0_0402_5%

FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 < 5>
FDI_CTX_PRX_P1 < 5>
FDI_CTX_PRX_P2 < 5>
FDI_CTX_PRX_P3 < 5>
FDI_CTX_PRX_P4 < 5>
FDI_CTX_PRX_P5 < 5>
FDI_CTX_PRX_P6 < 5>
FDI_CTX_PRX_P7 < 5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

RH128 0_0402_5%

1 2

@

RH103 0_0402_5%

12

If not using integrated
LAN,signal may be left as NC.

PCH_RSMRST#_RPCH_DPWROK

PCIE_WAKE# <24,28,32>

T58 PAD~D

SUSCLK_R <24>

PM_SLP_S5# <24>

PM_SLP_S4# <24>

PM_SLP_S3# <24,28>

T59 PAD~D

H_PM_SYNC <6>

SUSCLK

Reserve for RF please close to UH1

3

PCH_ENVDD<22>

VGA_PWM<22>

LVDS_DDC_CLK<2 2>

LVDS_DDC_DATA<22>

LVDS_ACLK-< 22>
LVDS_ACLK+<22>

LVDS_A0-<22>
LVDS_A1-<22>
LVDS_A2-<22>

LVDS_A0+<22>
LVDS_A1+<22>
LVDS_A2+<22>

LVDS_BCLK-< 22>
LVDS_BCLK+<22>

LVDS_B0-<22>
LVDS_B1-<22>
LVDS_B2-<22>

LVDS_B0+<22>
LVDS_B1+<22>
LVDS_B2+<22>

CRT_B<21>
CRT_G<21>
CRT_R<21>

CRT_DDC_CLK<21>
CRT_DDC_DATA<21>

CRT_HSYNC< 21>
CRT_VSYNC<21>

Can be left NC when IAMT is
not support on the platfrom

CH29

12

@

10P_0402_50V8J

+3VS

1 2

RH133 2.2K_0402_5%

1 2

RH135 2.2K_0402_5%

1 2

RH136 8.2K_0402_5%@

1 2

RH137 2.2K_0402_5%

1 2

RH138 2.2K_0402_5%

1 2

RH233 2.2K_0402_5%

1 2

RH234 2.2K_0402_5%

@

1 2

RH238 2.2K_0402_5%

@

1 2

RH239 2.2K_0402_5%

ENBKL<24>

T56PAD~D

RH230 33_0402_5%

RH202 33_0402_5%

1K_0402_0.5%

ENBKL
PCH_ENVDD

LVDS_DDC_CLK
LVDS_DDC_DATA

CTRL_CLK
CTRL_DATA

LVDS_IBG

LVDS_ACLK­LVDS_ACLK+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

LVDS_BCLK­LVDS_BCLK+

LVDS_B0­LVDS_B1­LVDS_B2-

LVDS_B0+
LVDS_B1+
LVDS_B2+

CRT_B
CRT_G
CRT_R

CRT_DDC_CLK
CRT_DDC_DATA

1 2
1 2

12

RH115

CTRL_CLK

CTRL_DATA

PM_CLKRUN#

LVDS_DDC_CLK

LVDS_DDC_DATA

PCH_SDVO_CTRLCLK

PCH_SDVO_CTRLDATA

CRT_DDC_CLK

CRT_DDC_DATA

HSYNC
VSYNC

CRT_IREF

2

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82HM77 QPRG C1 BGA 989P PCH

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN

mDP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DMC

AP43
AP45

AM42
AM40

AP39

SDVO_INTN

AP40

SDVO_INTP

P38
M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

AT40

DDPB_HPD

AV42

DDPB_0N

AV40

DDPB_0P

AV45

DDPB_1N

AV46

DDPB_1P

AU48

DDPB_2N

AU47

DDPB_2P

AV47

DDPB_3N

AV49

DDPB_3P

P46
P42

AP47
AP49

DDPC_AUXP

AT38

DDPC_HPD

AY47

DDPC_0N

AY49

DDPC_0P

AY43

DDPC_1N

AY45

DDPC_1P

BA47

DDPC_2N

BA48

DDPC_2P

BB47

DDPC_3N

BB49

DDPC_3P

M43
M36

AT45
AT43

DDPD_AUXP

BH41

DDPD_HPD

BB43

DDPD_0N

BB45

DDPD_0P

BF44

DDPD_1N

BE44

DDPD_1P

BF42

DDPD_2N

BE42

DDPD_2P

BJ42

DDPD_3N

BG42

DDPD_3P

1 2

RH120 10K_0402_5%

1 2

RH123 2.37K_0402_1 %

1 2

RH132 100K_0402_5 %

1 2

RH134 100K_0402_5 %

1 2

RH235 150_0402_1 %

1 2

RH236 150_0402_1 %

1 2

RH237 150_0402_1 %

HDMI_DET

HDMI_A2N_VGA
HDMI_A2P_VGA
HDMI_A1N_VGA
HDMI_A1P_VGA
HDMI_A0N_VGA
HDMI_A0P_VGA
HDMI_A3N_VGA
HDMI_A3P_VGA

1

PCH_SDVO_CTRLCLK <23>

PCH_SDVO_CTRLDATA <23>

HDMI_DET < 23>

HDMI_A2N_VGA <23>

HDMI_A2P_VGA <23>

HDMI_A1N_VGA <23>

HDMI_A1P_VGA <23>

HDMI_A0N_VGA <23>

HDMI_A0P_VGA <23>

HDMI_A3N_VGA <23>

HDMI_A3P_VGA <23>

PM_CLKRUN#

LVDS_IBG

PCH_ENVDD

ENBKL

CRT_B

CRT_G

CRT_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-8241P

1

15 56Wednesday, February 01, 2012

1.0

5

+3VS

D D

C C

CH31

CLK_PCI1

12

@

10P_0402_50V8J

RPH1

8.2K_0804_8P4R_5%

RPH2

8.2K_0804_8P4R_5%

RPH3

8.2K_0804_8P4R_5%

RH14010K_0402_5%

WL_OFF#

18

PCI_PIRQB#

27

PCI_PIRQD#

36

PCI_PIRQC#

45

GPIO51

18

GPIO52

27

PXS_PWREN

36

FFS_INT1

45

GPIO5

18

PCI_PIRQA#

27

GPIO4

36

ODD_DA#

45

DGPU_HOLD_RST#

12

Reserve for RF p lease close to PCH

B B

CLK_PCI_LPBACK<14>

CLK_PCI_LPC<24>

CLK_PCI_LPBACK
CLK_PCI_LPC

4

USB3RN1<33>
USB3RN2<33>
USB3RN3<32>
USB3RN4<32>
USB3RP1<33>
USB3RP2<33>
USB3RP3<32>
USB3RP4<32>
USB3TN1<3 3>
USB3TN2<3 3>
USB3TN3<3 2>
USB3TN4<3 2>
USB3TP1<33>
USB3TP2<33>
USB3TP3<32>
USB3TP4<32>

DGPU_HOLD_RST#<34>

PXS_PWREN<36,52>

WL_OFF#<32>

FFS_INT1<29>

ODD_DA#<29>

T60PAD~D @

PCH_PLTRST#<34>

RH144 22_0402_5%
RH145 22_0402_5%

1 2

12

T61PAD~D @
T62PAD~D @
T63PAD~D @

USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#
GPIO52
PXS_PWREN

GPIO51

WL_OFF#

FFS_INT1
ODD_DA#
GPIO4
GPIO5

PCH_PLTRST#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

UH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82HM77 QPRG C1 BGA 989P PCH

RSVD

PCI

USB

3

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC6# / GPIO10
OC7# / GPIO14

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC5# / GPIO9

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8

AY5
BA2

AT12
BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

USB20_N8
USB20_P8

USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12

USBRBIAS

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

RH139 1K_0402_5%@

USB20_N0 <33>
USB20_P0 <33>
USB20_N1 <33>
USB20_P1 <33>
USB20_N2 <32>
USB20_P2 <32>
USB20_N3 <32>
USB20_P3 <32>
USB20_N4 <32>
USB20_P4 <32>
USB20_N5 <32>
USB20_P5 <32>

USB20_N8 <32>
USB20_P8 <32>

USB20_N10 <32>
USB20_P10 <32>
USB20_N11 <28>
USB20_P11 <28>
USB20_N12 <22>
USB20_P12 <22>

Within 500 mils

1 2

RH143 22.6_0402_ 1%

2

1 2

USB Conn 1

USB Conn 2 (with PWR Share)

USB Conn 3

USB Conn 4

Mini Card-1 (WLAN)

Mini Card-2 (mSATA)

Finger Print

Card Reader

Express Card

Camera

*

+1.8VS

USB_OC0# <33>
USB_OC1# <33>
USB_OC2# <32>
USB_OC3# <32>

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

RPH4

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RPH5

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

1

+3V_PCH

+3VS

@

RH150

10K_0402_5%

PLT_RST#<6,24,28,32>

A A

5

1 2

12

RH155
100K_0402_5%

@

1 2

RH149 0_0402_5%

+3VS

5

UH5

1

P

IN1

4

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

4

@

1 2

PCH_PLTRST#

RH157
10K_0402_5%

1 2

CH101

0.1U_0402_25V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Date: Sheet of

Title

Size Document Number Rev

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

LA-8241P

1

16 56Wednesday, February 01, 2012

1.0

5

+3V_PCH

1K_0402_5%

D D

10K_0402_5%

High: CRT Plugged

CRT_DET#<21>

+3VS

C C

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H：On-Die voltage r egulator enable

*

L：On-Die PLL Volta ge Regulator di sable

PCH_GPIO37

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx ter minated

*

to same voltage
(DC Coupling Mod e)

+3VS

B B

A A

RH168 1K_0402_5%@

RH169

PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16

Please refer to Huron River Debug Board DG 0.5

1 2

RH165 1K_0402_5%@

1 2

1 2

RH173 10K_0402_5%@

12

10K_0402_5%

2

G

QH4

SSM3K7002F_SC59-3

RH16410K_0402_5%

PCH_GPIO28

PCH_GPIO37

PCH_GPIO37

PCH_GPIO27

5

PCH_LID_SW_IN#

12

RH240

PCH_GPIO28

12

RH241

+3VS

RH160
10K_0402_5%

1 2

CRT_DET

13

D

S

GPIO1 PCH_GPIO37

12

EC_LID_OUT#<24>

4

UH1F

CRT_DET

GPIO1

GPIO6

1 2

EC_SCI#

EC_SMI#

PCH_LID_SW_IN#EC_LID_OUT#

RH730_0402_5%

GPIO16

VGA_PWRGD

PCH_GPIO22

KB_DET#

PCH_GPIO27

PCH_GPIO28

BT_ON#

GPIO35

ODD_DETECT#

PCH_GPIO38

PCH_GPIO39

FFS_INT2

GPIO49

HDD_DETECT#

EC_SCI#< 24>

EC_SMI#<24>

VGA_PWRGD<36,52>

KB_DET#<26>

BT_ON#<32>

ODD_DETECT#<29>

FFS_INT2<29>

HDD_DETECT#<32>

4

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82HM77 QPRG C1 BGA 989P PCH

3

ODD_EN#

GPIO69

PCH_PECI_R

KB_RST#

H_THERMTRIP#_C

INIT3_3V#

NV_CLE

ODD_EN#

HDD_DETECT#

EC_SMI#

Compal Secret Data

Deciphered Date

A20GATE

PECI

RCIN#

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

PROCPWRGD

GPIO

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

NCTF

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

2

ODD_EN# <29>

T64 PAD~D@

@

1 2

RH1610_0402_5%

KB_RST# <24>

H_CPUPWRGD <6>

1 2

RH162390_0402_5%

Weak internal
PU,Do not pull l ow

NV_CLE

1 2

RH178

1 2

RH179

1 2

RH183

2

+3VS

RH159
10K_0402_5%

1 2

H_PECI <6,24>

H_THERMTRIP#

12

@

RH163
10K_0402_5%

INIT3_3V

This signal has weak internal
PU, can't pull low

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

+1.8VS

12

12

RH1671K_0402 _5%

CLOSE TO THE BRANCHING POINT

RH161 and RH162
Follow CRB FAB2 setting

+3V_PCH

10K_0402_5%

10K_0402_5%

10K_0402_5%

Date: Sheet

1

GATEA20 <24>

H_THERMTRIP# <6>

RH166

2.2K_0402_5%

H_SNB_IVB# <6>

+3VS

CRT_DET#

ODD_DETECT#

GPIO16

BT_ON#

KB_RST#

VGA_PWRGD

PCH_GPIO22

GPIO35

GPIO49

PCH_GPIO38

PCH_GPIO39

GPIO6

Title

Size Document Number Rev

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

LA-8241P

1 2

RH170

1 2

RH171

1 2

RH172

1 2

RH174

1 2

RH175

1 2

RH242

1 2

RH176

1 2

RH177

1 2

RH180

1 2

RH181

1 2

RH182

1 2

RH184

1

10K_0402_5%@

200K_0402_5%

10K_0402_5%

8.2K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

17 56Wednesday, February 01, 2012

of

1.0

5

4

3

2

1

D D

C C

B B

+1.05VS

+1.05VS

+1.05VS

RH187 0_0603_5%

RH189

0_0805_5%

+3VS

12

RH192
0_0805_5%

1

CH51

0.1U_0402_10V7K~D

2

RH194 0_0603_5%

@

JP1

12

PAD-OPEN 4x4m

+1.05VS

+VCCAPLLEXP_R

@

12

1

2

RH186 0_0603_5%

1 2

1UH_LB2012T1R0M_20%~D

Place CH40 Near BJ22 pin

+1.05VS

12

1

1

CH45

2

2

10U_0805_4VAM~D

+3VS_VCCA3GBG

Place CH53 Near BG6 pin

@

12

1

CH53

2

@

1

CH36

CH35

2

10U_0805_4VAM~D

12

LH3

@

+1.05VS_VCC_EXP

1

CH47

CH46

2

1U_0402_6.3V6K

+1.05VS

1U_0402_6.3V6K

+1.05VS_VCCCORE

1

CH37

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

@

1

1

CH48

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

RH195

1 2

0_0805_5%

+VCCP_VCCDMI

1

CH38

2

1U_0402_6.3V6K

+1.05VS_VCCDPLLEXP

+VCCAPLLEXP

CH42

10U_0805_4VAM~D

CH49

1U_0402_6.3V6K

+VCCAFDI_VRM

+1.05VS_VCCAPLL_FDI

+1.05VS_VCCDPLL_FDI

UH1G

1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

AP21

AP23

AP24

AP26

AT24

AN33

AN34

BH29

AP16

BG6

AP17

AU20

2925mA

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCC3_3[3]

VCCVRM[2]

VccAFDIPLL

VCCIO[27]

VCCDMI[2]

BD82HM77 QPRG C1 BGA 989P PCH

POWER

VCC CORE

VCCIO

FDI

1mA

CRTLVDS

1mA

VCCTX_LVDS[1]

VCCTX_LVDS[2]

60mA

VCCTX_LVDS[3]

VCCTX_LVDS[4]

DMI

20mA

VCCDFTERM[1]

VCCDFTERM[2]

190mA

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

20mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

+VCCADAC

U48

U47

+VCCA_LVDS

AK36

AK37

AM37

AM38

AP36

AP37

+3VS_VCC3_3_6

V33

V34

+VCCAFDI_VRM

AT16

+VCCP_VCCDMI

AT20

+1.05VS_VCC_DMI_CCI

AB36

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

V1

1

2

+VCCTX_LVDS

CH39

0.01U_0402_16V7K

1

CH43

0.1U_0402_10V7K~D

2

1

2

1

2

1

CH33

CH32

2

0.01U_0402_16V7K

Near AP43

1

2

RH188

1 2

0_0805_5%

1

CH50
1U_0402_6.3V6K

2

+VCCPNAND

CH52

0.1U_0402_10V7K~D

CH54
1U_0402_6.3V6K

4.7UH_LQM18FN4R7M00D_20%

1

CH34
10U_0805_4VAM~D

2

RH185 0_0805_5%

0.1U_0402_10V7K~D

CH40

0.01U_0402_16V7K

+VCCP_VCCDMI

RH191

1 2

0_0805_5%

RH196

1 2

0_0805_5%

RH243

0_0603_5%

1 2

1

2

+3VS

1 2

RH193 0_0805_5%

12

@

LH1

12

CH41

1

22U_0805_6.3V6M

2

+1.05VS

+1.8VS

+3V_PCH

+3VS

+3VS

LH2

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

RH190

1 2

1

0_0805_5%

CH44

2

1U_0402_6.3V6K

+3VS

12

+VCCP

+1.8VS

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Iccmax
Current (A)

0.001

5

5

0.001

0.001

0.266

0.001

0.08

0.08

1.3

0.042

1.05VccIO 2.925

1.05VccASW 1.01

3.3VccS PI 0.02

3.3VccD SW 0.003

1.8 0.19VccpNAND

3.3VccR TC 6 uA

3.3VccS us3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

0.02

VccSSC 1.05 0 .095

cDIFFCLKN 1.05 0.055

Vc

VccALVDS 3.3

0.001

1.8VccT X_LVDS 0.06

+1.5VS +VCCAFDI_VRM

RH197

+VCCAFDI_VRM

12

A A

5

4

0_0603_5%

1

CH100
1U_0402_6.3V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8) PWR

LA-8241P

1

18 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

+1.05VS

+3V_PCH

1 2

RH199 0_0603_5%

D D

+1.05VS

C C

B B

A A

+1.05VS

@

1 2

0_0805_5%

+1.05VS

RH219 0_0603_5%

+1.05VS

+1.05VS

+1.05VS

1 2

RH232

0_0805_5%

RH204

+VCCAPLL_CPY +3VS_VCC_CLKF33

+3VS

@

12

RH220 0_0603_5%

12

+VCCP

+VCCA_DPLL_L

5

LH4

@

10UH_LBR2012T100M_20%

1 2

+1.05VS

1 2

LH5

10UH_LBR2012T100M_20%

1 2

@

+1.05VM_VCCSUS

1

CH80

1U_0402_6.3V6K

2

RH223 0_0603_5%

RH224 0_0603_5%

1 2

RH227 0_0603_5%

10UH_LBR2012T100M_20%

10UH_LBR2012T100M_20%

12

12

LH7

1 2

1 2

LH8

10U_0805_10V6K

@

1

CH59

2

1 2

RH211 0_0805_5%

RH2150_0805_5%

1

2

1

CH84
1U_0402_6.3V6K

2

1

4.7U_0603_6.3V6K

2

+1.05VS

+3VS_VCC_CLKF33

1

1

CH74

2

2

10U_0805_10V6K

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

CH82
1U_0402_6.3V6K

+V_CPU_IO

CH87

1

+

CH94

2

220U_B2_2.5VM_R35M~D

1

CH55

0.1U_0402_10V7K~D

2

0.1U_0402_10V7K~D

1 2

RH207 0_0603_5%

CH75

1U_0402_6.3V6K

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

1

CH85

0.1U_0402_10V7K~D

2

1

2

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

1

CH96

2

1U_0402_6.3V6K

@

RH198 0_0603_5%

CH58

@

1

CH65

2

22U_0805_6.3V6M

1

CH68

2

1U_0402_6.3V6K

1

CH79

0.1U_0402_10V7K~D

2

1

CH88

CH89

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

+

CH95

2

2

220U_B2_2.5VM_R35M~D

12

1

2

1

CH66

2

22U_0805_6.3V6M

1

CH69

2

1U_0402_6.3V6K

+VCCRTCEXT

1

@

CH86
1U_0402_6.3V6K

2

+RTCVCC

CH97

1U_0402_6.3V6K

4

+VCCACLK

+VCCPDSW

+PCH_VCCDSW

+VCCAPLL_CPY_PCH

+VCCDPLL_CPY

+VCCSUS1

1

@

CH62
1U_0402_6.3V6K

2

+1.05VM_VCCASW

1

CH70

2

1U_0402_6.3V6K

+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCSST

+1.05VM_VCCSUS

1

1

CH90

2

CH91

2

0.1U_0402_10V7K~D

UH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

1

2

0.1U_0402_10V7K~D

BD82HM77 QPRG C1 BGA 989P PCH

CH92

1U_0402_6.3V6K

POWER

N26

VCCIO[29]

P26

119mA

PCI/GPIO/LPCMISC

SATA USB

10mA

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

1mA

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

1mA

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

V5REF

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

3m

A

1010mA

Clock and Miscellaneous

80mA

80mA

55mA

95mA

1mA

CPURTC

HDA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

+1.05VS_VCCUSBCORE

1

CH56
1U_0402_6.3V6K

2

+3V_VCCPUSB

1

CH60

2

+1.05VS_VCCAUPLL

+PCH_V5REF_SUS

+VCCA_USBSUS

+3V_VCCPSUS_1

+PCH_V5REF_RUN

+3V_VCCPSUS

1

CH71
1U_0402_6.3V6K

2

+3VS_VCCPPCI

+VCC3_3_2

+VCCAFDI_VRM

+VCCAFDI_VRM

+1.05VS_VCC_SATA

+VCCSUSHDA

1

CH930.1U_0402_10V7K ~D

2

Compal Secret Data

+3V_VCCAUBG

1

2

0.1U_0402_10V7K~D

RH209 0_0603_5%

+3VS_VCCPCORE

RH217

1

2

+1.05VS_VCC_SATA

12

0_0603_5%

CH77

0.1U_0402_10V7K~D

+1.05VS_SATA3

+VCCSATAPLL

@

150_0402_1%

RH231

Deciphered Date

12

RH200 0_0603_5%

RH205 0_0603_5%

RH206 0_0603_5%

CH61

0.1U_0402_10V7K~D

12

RH210 0_0603_5%

1

CH67

2

0.1U_0402_10V7K~D
RH213
0_0603_5%

RH214 0_0805_5%

1

CH73

0.1U_0402_10V7K~D

2

1

+3VS

2

+1.05VS_SATA3

RH222

0_0805_5%

1

CH83

2

+1.05VS

1U_0402_6.3V6K

RH229 0_0603_5%

12

2

+1.05VS

12

+3V_PCH

12

+1.05VS

12

12

+3V_PCH

12

RH216 0_0603_5%

CH76

0.1U_0402_10V7K~D

RH218

1

0_0805_5%
CH78
1U_0402_6.3V6K

2

12

+1.05VS

12

VCC3_3 = 2 66mA detal waiting f or newest spec

CDMI = 42m A detal wa iting for newest sp ec

VC

QH5
AO3419L_SOT23-3

D

S

12

100_0402_1%

100_0402_1%

G

2

RH208

RH212

13

12

12

@

RH221

0_0805_5%

1

2

+3V_PCH+5V_PCH

+3VS+5VS

12

Compal Electronics, Inc.

1

+3V_PCH

+VCCA_USBSUS

+3V_PCH

+3VS

+3VS

12

12

@

10UH_LBR2012T100M_20%

1 2

1

CH81

@

10U_0805_10V6K

2

+3V_PCH

RH201

0_0603_5%

PCH_PWR_EN#<27>

1

CH63

2

@

1U_0402_6.3V6K

+1.05VS

LH6

+VCCSATAPLL_R

If it support 3. 3V audio signal s
POP:RH244
Depop RH245 / RH 246

If it support 1. 5V audio signal s
POP:RH245 / RH24 6
Depop R244

Title

PCH (7/8) PWR

Size Document Number Rev

LA-8241P

Date: Sheet of

+5V_PCH+5VALW

12

RH203

CH57

20K_0402_5%

0.1U_0402_10V7K~D

21

DH2
RB751S40T1_SOD523-2~D

+PCH_V5REF_SUS

1

CH64

0.1U_0603_25V7K

2

21

DH3
RB751S40T1_SOD523-2~D

+PCH_V5REF_RUN

1

CH72
1U_0603_10V6K

2

+1.05VS

19 56Wednesday, February 01, 2012

1.0

5

D D

C C

B B

A A

5

UH1H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

BD82HM77 QPRG C1 BGA 989P PCH

4

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

4

3

UH1I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

BD82HM77 QPRG C1 BGA 989P PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

2

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

2

Date: Sheet of

1

Title

Size Document Number Rev

Compal Electronics, Inc.

PCH (8/8) VSS

LA-8241P

1

20 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

C R T

From VGA

D D

CRT_R<15 >

CRT_G<15>

C C

CRT_B<15>

VGA_CRT_R<35>
VGA_CRT_G<35>

VGA_CRT_B<35>
VGA_CRT_HSYNC<35>
VGA_CRT_VSYNC<35>

VGA_CRT_CLK<35>

VGA_CRT_DATA<35>

LV1 0_0603

LV3 0_0603

LV5 0_0603

CV6

150_0402_1%

CV7

150_0402_1%

CV8

12

150_0402_1%

12

12

VGA_CRT_VSYNC

1 2

1 2

1 2

For EMI

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_CRT_CLK
VGA_CRT_DATA

for debug CRT

RV223 0_0402_5%@

1 2

RV224 0_0402_5%@

1 2

RV225 0_0402_5%@

1 2

RV226 0_0402_5%@

1 2

RV227 0_0402_5%@

1 2

RV228 0_0402_5%@

1 2

RV229 0_0402_5%@

1 2

CRT_R_C

CRT_G_C

CRT_B_C

RV4

150_0402_1%

RV5

150_0402_1%

RV3

150_0402_1%

12

12

12

@

@

@

22P_0402_50V8J

12

CRT_R
CRT_G
CRT_B
CRT_HSYNCVGA_CRT_HSYNC
CRT_VSYNC
CRT_DDC_CLK
CRT_DDC_DATA

CV3

22P_0402_50V8J

12

LV2 LQW18AN47NG00D _0603

1 2

LV4 LQW18AN47NG00D _0603

1 2

LV6 LQW18AN47NG00D _0603

CV4

1 2

CV5

22P_0402_50V8J

12

CRT_R_L

CRT_G_L

CRT_B_L

For EMI

+5VS

DV4

2 1
3

W=40mils

BAT1000-7-F_SOT23-3~D

DV1

2

3

PESD5V0U2BT_SOT23-3
DV2

CV11

10P_0402_50V8J

CV10

10P_0402_50V8J

CV9

10P_0402_50V8J

12

12

12

2

3

PESD5V0U2BT_SOT23-3

@

1

@

1

NC

CRT_DET#<17>

FV2

1.1A_6VDC_FUSE

RV2

CRT_R_L

CRT_DDC_DATA_C
CRT_G_L

HSYNC_L
CRT_B_L

VSYNC_L

CRT_DDC_CLK_C

21

0_1206_5%

12

@

T65PAD~D @

W=40mils

RV1

100K_0402_5%

CV12

100P_0402_50V8J

1

2

+CRT_VCC+R_CRT_VCC

12

1

2

CV1

0.1U_0402_16V7K

JCRT

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070546HR015M22BZR

CONN@

16

G

17

G

B B

CRT_DDC_DATA<15>

CRT_DDC_CLK<15>

A A

+3VS +CRT_VCC+3VS +CR T_VCC+3VS

2.2K_0402_5%
RV7

RV6

2.2K_0402_5%

1 2

1 2

G

S

G

2

2N7002BKW_SOT323-3

13

D

S

QV2

2N7002BKW_SOT323-3

2.2K_0402_5%

RV8

2.2K_0402_5%

RV9

1 2

2

13

D

QV1

1 2

CRT_DDC_DATA_C

CRT_DDC_CLK_C

CRT_HSYNC<15>

CRT_VSYNC<15>

0.1U_0402_16V7K

0.1U_0402_16V7K

1 2

CRT_VSYNC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

CV13

1 2

CV16

3

+CRT_VCC

5

1

P

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

+CRT_VCC

5

1

P

OE#

A2Y

G

3

4

UV26

RV12

10K_0402_5%

1 2

4

UV27
74AHCT1G125GW_SOT353-5

2012/01/17 2013/01/16

D_CRT_HSYNC H SYNC_LCRT_HSYNC

D_CRT_VSYNC

Compal Secret Data

Deciphered Date

RV10

1 2

RV11

1 2

0_0603_5%

0_0603_5%

2

VSYNC_L

12

10P_0402_50V8J

CV15

10P_0402_50V8J

CV14

12

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

VGA / LVDS /camera conn.

LA-8241P

1

21 56Wednesday, February 01, 2012

1.0

of

5

+LCDVDD +5VALW

RV14
100_0402_1%

1 2

1

D

QV3

S

10K_0402_5%

13

RV18

D D

PCH_ENVDD<15>

EC_ENVDD<24>

PCH_ENVDD

EC_ENVDD

SSM3K7002FU_SC70-3~D

DV7

2

3

BAT54C-7-F_SOT23-3

RV15
47K_0402_5%

1 2

RV17

2

G

13

D

QV5
BSS138_SOT23~D

S

56K_0402_5%

2

G

12

LCD backlight PWR CTRL

C C

mil

60

B+

CV25

1000P_0402_50V7K

1

2

RV28
0_0402_5%

+LCDVDD_R

EN_INVPWR<24>

+LCDVDD

B B

RV31
0_0402_5%

@

12

12

2

G

4 5

RV25

100K_0402_5%

12

PWR_SRC_ON

12

RV26
100K_0402_5%

13

D

QV7
SSM3K7002FU_SC70-3~D

S

QV6
SI3457CDV-T1-E3_TSOP6~D

+INV_PWR_SRC_R

D

6

S

2
1

G

1

3

2

B+ +INV_PWR_SRC

4

12

CV19

0.1U_0402_16V7K

1

2

60mil

CV26

0.1U_0603_50V_X7R

@

RV27 0_0805_5%

1 2

LCD PWR CTRL

+3VS

W

60mils

=

S

AO3419L_SOT23-3

G

QV4

2

+LCDVDD

4.14

D

1 3

+LCDVDD

1

CV20

4.7U_0805_10V4Z

2

RV24 0_0805_5%

1 2

W=60mils

1

CV21

0.1U_0402_16V7K

2

+INV_PWR_SRC

BKOFF#<24>

USB20_P12<16>

USB20_N12< 16>

3

BKOFF#

2 1

CH751H-40PT_SOD323-2~D

VGA_PWM<15>

@

DV5

CH751H-40PT_SOD323-2~D

DV6

DLW21SN900HQ2L_0805_4P~D

1

1

4

4

LV24

1 2

RV210 0_0402_5%

1 2

RV208 0_0402_5%

RV29

0_0402_5%

100K_0402_5%

+3VS

@

21

5P_0402_50V8C

5P_0402_50V8C

12

RV230

12

RV13

4.7K_0402_5%

DISPOFF#

2

2

3

3

@

1 2

1 2

CV27

CV28

12

@

@

INV_PWM

LVDS_BCLK-

LVDS_BCLK+

@

12

10K_0402_5%
RV16

USB20_P12_R

USB20_N12_R

LVDS_DDC_CLK<15>
LVDS_DDC_DATA<15>

1

CV30
680P_0402_50V7K~D

2

MIC_DATA<30>

W=60mils

2

EDID_CLK_LCD

EDID_DATA_LCD

CV23

1

2

LVDS_A0­LVDS_A0+

LVDS_A1­LVDS_A1+

LVDS_A2­LVDS_A2+

LVDS_ACLK­LVDS_ACLK+

LVDS_B0­LVDS_B0+

LVDS_B1­LVDS_B1+

LVDS_B2­LVDS_B2+

LVDS_BCLK­LVDS_BCLK+

LCD_TEST

0.1U_0402_16V7K

CV24

1

2

5P_0402_50V8C

5P_0402_50V8C @

W=60mils

+INV_PWR_SRC

INV_PWM
DISPOFF#
USB20_P12_R
USB20_N12_R

+3VS_CAM

MIC_CLK_R

MIC_DATA

+LCDVDD

+3VS

CV17

@

1 2

CV18

1 2

LVDS_A0-<15>
LVDS_A0+<15>

LVDS_A1-<15>
LVDS_A1+<15>

LVDS_A2-<15>
LVDS_A2+<15>

LVDS_ACLK-<15>
LVDS_ACLK+<15>

LVDS_B0-<15>
LVDS_B0+<15>

LVDS_B1-<15>
LVDS_B1+<15>

LVDS_B2-<15>
LVDS_B2+<15>

LVDS_BCLK-<15>
LVDS_BCLK+<15>
LCD_TEST<24>

@
@

RV19 0_0402_1%
RV20 0_0402_1%

0.1U_0402_16V7K

CV22

12
12

* Reserved for EMI/ESD/RF
need to close to JLVDS

DV8

6

V I/O

MIC_CLK

5

V BUS

4

V I/O

IP4223CZ6_SO6-6

0_0402_5%

+5VS

MIC_CLK<30>

RV30

Ground

V I/O

V I/O

1

2

3

12

1

2

USB20_P12_RMIC_CLK_R

USB20_N12_RMIC_DATA

MIC_CLK_R

CV29

@

470P_0402_50V7K~D

1

LVDS Conn.

JLVDS

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

10U_0805_10V6K

39
40

1

2

STARC_107K40-000001-G2

CONN@

1

41

2

G1

42

3

G2

43

4

G3

44

5

G4

45

6

G5

46

7

G6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Wedcam PWR CTRL

+INV_PWR_SRC

+5VALW

+3VS_CAM+3VS +3VS

SI2301CDS-T1-GE3_SOT23-3

12

RV34

100K_0402_5%

A A

CMOS_ON#<24>

5

CV319

@

RV209

@

12

47K_0402_5%

0.1U_0402_16V7K @

QV8

S

D

13

1000P_0402_50V7K

1

2

@

CV31

@

G

2

2

1

12

RV231 0_0603_5%

4

+LCDVDD_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/01/17 2013/01/16

RV33

100K_0402_5%

@

@

QV9A

2

Compal Secret Data

Deciphered Date

2

12

@

12

61

RV32
820_0805_1%

3

@

QV9B

5

4

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

* Reserved for LCD

quence tuning

se

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

LVDS /camera conn.

LA-8241P

1

22 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

W=40mils

Place close to JHDMI1

RV35 0_0402_5%@

1 2

D D

C C

B B

HDMI_A3N_VGA< 15>
HDMI_A3P_VGA<15>

HDMI_A0N_VGA< 15>
HDMI_A0P_VGA<15>

HDMI_A1N_VGA< 15>
HDMI_A1P_VGA<15>

HDMI_A2N_VGA< 15>
HDMI_A2P_VGA<15>

CV32 0.1U_0402_10V7K~D

12

CV33 0.1U_0402_10V7K~D

12

CV36 0.1U_0402_10V7K~D

12

CV37 0.1U_0402_10V7K~D

12

CV38 0.1U_0402_10V7K~D

12

CV39 0.1U_0402_10V7K~D

12

CV40 0.1U_0402_10V7K~D

12

CV41 0.1U_0402_10V7K~D

12

TMDS_TXCN
TMDS_TXCP

TMDS_TX0N
TMDS_TX0P

TMDS_TX1N
TMDS_TX1P

TMDS_TX2N
TMDS_TX2P

RV44 680_0402_1%

12

1 2

RV51

100K_0402_5%

RV45 680_0402_1%

12

12

0_0402_1%

@

RV53

RV46 680_0402_1%

RV47 680_0402_1%

12

12

TMDS_TXCN

TMDS_TXCP

TMDS_TX0N

TMDS_TX0P

TMDS_TX1N

TMDS_TX1P

TMDS_TX2N

TMDS_TX2P

RV49 680_0402_1%

RV48 680_0402_1%

12

12

13

D

QV11

2

G

S

2N7002_SOT23

CV358 100P_0402_50 V8J@

1 2

CV360 100P_0402_50 V8J@

1 2

CV362 100P_0402_50 V8J@

1 2

CV363 100P_0402_50 V8J@

1 2

CV359 100P_0402_50 V8J@

1 2

CV357 100P_0402_50 V8J@

1 2

CV361 100P_0402_50 V8J@

1 2

CV364 100P_0402_50 V8J@

1 2

RV43 680_0402_1%

RV42 680_0402_1%

12

12

+3VS

TMDS_TXCN

TMDS_TXCP

TMDS_TX0N TMDS_L_TX0N

TMDS_TX0P

TMDS_TX1N

TMDS_TX1P

TMDS_TX2N

TMDS_TX2P

LV7

1

1

4

4

WCM-2012HS-900T_4P

RV37 0_0402_5%@

1 2

RV38 0_0402_5%@

1 2

LV8

1

1

4

4

WCM-2012HS-900T_4P

@

RV40 0_0402_5%

1 2

RV41 0_0402_5%@

1 2

LV9

1

1

4

4

WCM-2012HS-900T_4P

RV50 0_0402_5%@

1 2

RV52 0_0402_5%@

1 2

LV10

1

1

4

4

WCM-2012HS-900T_4P

RV54 0_0402_5%@

1 2

TMDS_L_TXCN

2

2

TMDS_L_TXCP

3

3

2

2

TMDS_L_TX0P

3

3

TMDS_L_TX1N

2

2

TMDS_L_TX1P

3

3

TMDS_L_TX2N

2

2

TMDS_L_TX2P

3

3

TMDS_L_TXCN

TMDS_L_TXCP

TMDS_L_TX0N

TMDS_L_TX0P

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TX2N

TMDS_L_TX2P

RV36 0_1206_5%

12

DV9

+5VS

2 1
3

NC

BAT1000-7-F_SOT23-3~D

CV349 3.3P_040 2_50V8C~D

CV350 3.3P_040 2_50V8C~D

CV351 3.3P_040 2_50V8C~D

CV352 3.3P_040 2_50V8C~D

CV353 3.3P_040 2_50V8C~D

CV354 3.3P_040 2_50V8C~D

CV355 3.3P_040 2_50V8C~D

CV356 3.3P_040 2_50V8C~D

@

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

FV1

1.5A_6V_1206L150PR~D

12

HDMI_HPLUG

DDC_DAT_HDMI
DDC_CLK_HDMI

TMDS_L_TXCN

TMDS_L_TXCP
TMDS_L_TX0N

TMDS_L_TX0P
TMDS_L_TX1N

TMDS_L_TX1P
TMDS_L_TX2N

TMDS_L_TX2P

Part Number Description

RO0000002HM

CV34

1

2

+3VS

0.1U_0402_10V7K~D

12

RV39
10K_0402_5%

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMR2U-AK120C

CONN@

ROYALTY HDMI W/LOGO46@

HDMI W/Logo:RO0000002HM

+VDISPLAY_VCC

1

CV35

2

10U_0603_6.3V6M

20

GND

21

GND

22

GND

23

GND

20110805 EMI ADD20111024 EMI ADD

+3VS

+5VS

+3VS

QV12A

2

DMN66D0LDW-7_SOT363-6

DDC_CLK_HDMI +5V_HDMI_DDC

A A

PCH_SDVO_CTRLCLK<15>

PCH_SDVO_CTRLDATA<15>

DMN66D0LDW-7_SOT363-6

5

5

4

QV12B

61

DDC_DAT_HDMI

3

RB751V-40GTE-17_SOD323-2~D

1 2

RV58 2.2K_0402_5%

1 2

RV60 2.2K_04 02_5%

4

21

12

@

DV10

@

0_0402_1%
RV56

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

HDMI_DET<15>

Deciphered Date

MMBT3904_NL_SOT23-3

2

QV13

C

E

3 1

12

RV55
100K_0402_5%

RV57

2

1 2

B

150K_0402_5%

@

RV59

200K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HDMI

LA-8241P

1

2

3

+3VS

1

DV11
BAV99-7-F_SOT23-3

@

1 2

HDMI_HPLUG

1

CV42
220P_0402_50V8J

2

23 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

+3VALW

1 2

RE1
0_0805_5%

D D

CE10

22P_0402_50V8J@

RE8 47K_0402_5%

+3VALW

CE11 0.1U_0402_16V7K

+3VALW

RE11 2.2K_0402_5%

RE13 2.2K_0402_5%

RE62 47K_0402_5%@

C C

RE63 47K_0402_5%@

RE71 10K_0402_5%@

RE70 10K_0402_5%

RE77 100K_0402_5%

RE78 100K_0402_5%

RE16 1K_0402_1%

RE21 10K_0402_5%

RE24 2.2K_0402_5%

RE25 2.2K_0402_5%

+3VS

B B

VCOUT0 PCH_PWROK

A A

EC_SMB_CK1_R

1 2

EC_SMB_DA1_R

1 2

1 2

1 2

1 2

1 2

1 2

1 2

@

1 2

1 2

1 2

1 2

RE32 10K_0402_5%

RE35 10K_0402_5%

PCIE_WAKE#<15,28,32>

USB_DET#_DELAY<28>

H_PROCHOT#<6,44>

KSO1

KSO2

USB_DET#_DELAY

WLAN_WAK E#

DASH_SW3

DASH_SW1

EC_SMI#

EC_PME#

EC_SMB_CK2

EC_SMB_DA2

@

1 2

@

1 2

RE38 0_0402_5%

KB930@

12

RE1810K_0402_5%

VR_HOT#<50>

SN74LVC1G06DCKR_SC70-5

CE19

47P_0402_50V8J

12

EC_SCI#

PCH_HOT#

PCH_PWROK

RE61 0_0402_5%

USB_DET#_DELAY

VR_HOT#

5

12

1 2

RE44 0_0402_5%

12

1

2

RE6 33_0402_5%@

CLK_PCI_LPC<16>

12

12

KSI[0..7]<25>

KSO[0..16]<25>

EC_SMB_CK2 <35>

EC_SMB_DA2 <35>

EC_SMB_CK1<43,44>
EC_SMB_DA1<43,44>

PCH_PWROK<6,15>

EC_PME#

1 2

RE72 0_0402_5%

+3VS

5

UE2

P

Y4A

G3NC

1

12

KSI[0..7]

KSO[0..16]

EC_SMB_CK1 EC_SMB_CK1_R

PCH_SMLCLK<14>
PCH_SMLDATA<14>

PM_SLP_S3#<15,28>
PM_SLP_S5#<15> EC_LID_OUT# <17>

DASH_SW1<32>

CMOS_ON#

0.1U_0402_16V7K

CE15

1

2

VCOUT1_PHH_PROCHOT#

2

RE47
100K_0402_5%

1 2

1

CE1

2

0.1U_0402_16V7K

LPC_FRAME#<13>

PLT_RST#<6,16,28,32>

PWRSHARE_EN _EC#<33>

1 2
1 2

RE28 0_0402_5%

1 2

RE29 0_0402_5%

1 2

RE31 0_0402_5%

1 2

RE33 0_0402_5%

1 2

EC_SMI#<17>

TOUCH_LED#<25>

CMOS_ON#<22>
130W/90W#<43>

DASH_LED_PWM<32>

FAN_SPEED1<25>

PCH_PWROK

SUSCLK_R<15>

0.1U_0402_16V7K

1

2

GATEA20<17>
KB_RST#<17>

SERIRQ<13>

LPC_AD3<13>
LPC_AD2<13>
LPC_AD1<13>
LPC_AD0<13>

EC_SCI#<17>

AOAC_ON<32>

RE26 0_0402_5%
RE27 0_0402_5%

PS_ID<43>

KB9012@

DASH_SW3<32>

22P_0402_50V8J

0.1U_0402_16V7K

1

1

CE2

0.1U_0402_16V7K

EC_TX<32>
EC_RX<32>

RE40

RE45 100K_0402_5%

1 2

CE17 20P_0402_50V8

@

CE12

CE4

CE3

2

2

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

EC_RST#
EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

EC_SMB_DA1_REC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#_R
PM_SLP_S5#_R

EC_SMI#

TOUCH_LED#

DASH_LED_PWM
FAN_SPEED1
EC_PME#

EC_TX

EC_RX

0_0402_5%

12

EC_CRY1
EC_CRY2

12

EC_CRY1

1

1

2

2

@

YE1

32.768KHZ_12.5PF_Q13MC14610002

4

2

1

1000P_0402_50V7K

EC_CRY2

OSC4OSC

NC3NC

2

CE6

CE5

1000P_0402_50V7K

1

UE1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

@

1

CE13

22P_0402_50V8J

2

+3VALW_EC

LPC & MISC

LE1
FBMA-L11-160808-800LMT_0603

1 2

9

22

33

96

EC_VDD/VCC

EC_VDD/VCC

EC_VDD/VCC

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

Int. K/B
Matrix

SPI Device Interface

SPI Flash ROM

SM Bus

GPIO

GND/GND

GND/GND

GND/GND

11

24

35

+EC_VCCA

1

RE2
0_0402_5%

KB930@

1 2

125

111

67

EC_VDD0

EC_VDD/VCC

AD Input

CPU1.5V_S3_GATE/GPXIOA00

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

EC_RSMRST#/GPXIOA03

EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

GPO

PCH_APWROK/GPXIOA10

GPI

PECI_KB9012/GPXIOD07

GND/GND

GND0

69

94

113

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V7K
CE7

ECAGND

2

KB9012@

RE4
0_0402_5%

Reserved for KB9012

EC_VDD/AVCC

BATT_TEMP/GPIO38

EC_MUTE#/GPIO4A

WOL_EN/GPXIOA01

VCIN0_PH/GPXIOD00

PECI_KB930/GPIO41

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

PM_SLP_S4#/GPIO59

VCOUT0_PH/GPXIOA07

PBTN_OUT#/GPXIOA09

SA_PGOOD/GPXIOA11

LID_SW#/GPXIOD04

AGND/AGND

KB9012QF-A3_LQFP128_14X14KB9012@

20mil

ECAGND

FBMA-L11-160808-800LMT_0603

12

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

GPIO39

ADP_I/GPIO3A

GPIO3B
GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

ME_EN/GPXIOA02

SPIDI/GPIO5B

SPIDO/GPIO5C

SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/GPIO40

FSTCHG/GPIO50

SYSON/GPIO56
VR_ON/GPIO57

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

SUSP#/GPXIOD05

GPXIOD06

V18R

LE2

3

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

12

+3VLP

KB_LED_PWM
BEEP#

ACOFF

BATT_TEMP

ADP_I
AD_BID0

PCH_HOT#_R PCH_HOT#

EN_DFAN1

EC_MUTE_R
USB_EN#

TP_CLK
TP_DATA

CPU1.5V_S3_GATE
WOL_EN#

ME_EN

RE15
0_0402_5% KB9012@

FRD#
FWR#
SPI_CLK
FSEL#

RE22 0_0402_5%

1 2

PECI_KB930

RE23 43_0402_1%KB930@

BATT_CHG_LED#

CAPS_LED

PWR_PWM _LED#

BATT_LOW_LED#

SYSON

VR_ON

PM_SLP_S4#_R

EC_RSMRST#

EC_LID_OUT#

RE340_0402_5% KB9012@

VCOUT0

BKOFF#

PBTN_OUT#

HDD_S3.5

SA_PGOOD

ACIN_D

EC_ON_R

ON/OFF_R

LID_SW#

SUSP#

PECI_KB9012

+V18R

1

CE16

4.7U_0805_10V4Z

2

2012/01/17 2013/01/16

KB_LED_PWM <26>

RE3643_0402_1%

BEEP# <30>

12

ACOFF <44>

RE17
0_0402_5% @

RE7 0_0402_5%

RE12 0_0402_5%

12

1 2

12

RE14 0_0402_5%
RE41 0_0402_5%

1 2

RE42 0_0402_5%

1 2

RE43

1 2

12

CE9 100P_0402_50V8J

VCIN0_PHVCIN0_PH_R

12

@

12

EN_INVPWR <2 2>
EN_DFAN1 <25>

EC_ENVDD <22>

LCD_TEST <22>

12

USB_EN# <32,33>

PWRSHARE_OE# <33>

EAPD <30,31>
TP_CLK < 25>
TP_DATA <25>

CPU1.5V_S3_GATE <10>

WOL_EN# <32>

ME_EN <13>
VCIN0_PH <43>

FRD# <26>
FWR# <26>
SPI_CLK <26>
FSEL# <26 >

PX_MODE <36,52,53>
BATT_CHG_LED# <32>

CAPS_LED <25>

PWR_PWM _LED# <32>

BATT_LOW_LED# <32>

SYSON <27,28,48>
VR_ON <50>

EC_RSMRST# <15>

VCOUT1_PH

RE37 0_0402_5%KB9012@

12

BKOFF# <22>
PBTN_OUT# <6,15>

HDD_S3.5 <29>
SA_PGOOD <49>

12

LID_SW# <26,32>
SUSP# < 10,27,28,46,47,48>

65W/90W# <43>

43_0402_1%KB9012@

Co-lay KB930/KB9012 PECI

KB930

KB9012

Compal Secret Data

Deciphered Date

PCH_PWR_EN

ECAGND

ADP_I <43,44>

EC_MUTE#

ENBKL

Stuff

R4930

R4944

PCH_PWR_EN <2 7>

BATT_TEMP <43,44>

PCH_HOT# <14>
IMVP_IMON <5 0>

EC_MUTE# <30>

ENBKL <15>
H_PECI <6,17>

+3VLP

reserve for KB90 12 Rev.A2

12

RE30
47K_0402_5%@

VCIN1_PH <43>

VCOUT0_PH <45>

ACIN <15,35,43,44>

EC_ON <25,28>

ON/OFF <25>

H_PECI

2

TP_CLK

TP_DATA

FRD#

FWR#

SPI_CLK

FSEL#

SA_PGOOD

EC_MUTE#

ACIN

RE5

100K_0402_5%

RE64 0_0402_5%

RE65 0_0402_5%

RE66 0_0402_5%

RE67 0_0402_5%

HDD_S3.5

1 2

CE18 100P_0402_50V8J

Board ID

VOS@

VCIN0_PH_R

PCH_HOT#_R

1 2

1 2

1 2

1 2

PECI_KB930

RE39 0_0402_5%

RE80 0_0402_5%

CE14

1 2

RE46 10K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

+3VALW

RE3
100K_0402_5%

Ra

1 2

AD_BID0

1

2

0.1U_0402_16V7K

12

12

DASH_LED1# <32>

DASH_LED2# <32>

DASH_LED3# <32>

WL_BT_LED# <32>

CE8

VCIN0_PH2 <25>

3S_ON <25>

WLAN_WAK E# <32>

PM_SLP_S4# <15>

ACIN_65W <35>

RE5
56K_0402_5%

Rb

INS@

1 2

Analog Board ID definition,
Please see page 4.

RE19

0_0402_5%

RE76
0_0402_5%

+5VS

12

RE94.7K_0402_5%

12

RE104.7K_0402_5%

DASH_LED1#

DASH_LED2#

DASH_LED3#

WL_BT_LED#

1 2

RE69 0_0402_5%

1 2

0.1U_0402_16V7K

12

PM_SLP_S4#PM_SLP_S4#_R

1 2

Compal Electronics, Inc.

EC ENE-KB930/Co-lay 9012

LA-8241P

1

of

24 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

+FAN_POWER

40mil

Power ON Circuit

ON/OFF switch

D D

C C

TOP Side

SMT1-05-A_4P

1

2

6

@

Bottom Side

SMT1-05-A_4P

1

2

6

@

Pop only for
SSI debug

SW1

5

SW2

5

3

4

3

4

DASH_SW2<32>

ON/OFFBTN#

1

CE20

0.1U_0402_25V6K

2

RE20

0_0402_5%

VOS@

DE2

1

BAV70W_SOT323-3

2

3

12

100K_0402_5%

1

RE75

+3VALW

RE48

100K_0402_5%

KB930@

DE1

2

3

BAV70W_SOT323-3

EC_ON<24,28>

KB930@

10K_0402_5%

+3VALW

1 2

RE51

1 2

+3VLP

1 2

2

G

1 2

3S_ON <24>

RE49
100K_0402_5%

KB9012@

13

D

QE1

KB930@

SSM3K7002F_SC59-3

S

ON/OFF <24>

51_ON# <43>

1

1

2

2.2U_0603_6.3V6K

EN_DFAN1<24>

FAN_SPEED1<24>

CE22

2

1000P_0402_50V7K

EN_DFAN1

CE23

+5VS

+3VS

1
2
3
4

12

RE50
10K_0402_5%

1

CE24

0.01U_0402_16V7K

2

CE25

2.2U_0603_6.3V6K

1 2

UE3

VEN

GND

VIN

GND
GND

VO

GND

VSET

APE8873M SOP 8P

+FAN_POWER

40mil

8
7
6
5

JFAN

1
2
3

4
5

ACES_85204-0300N

CONN@

To POWER/B

+5VALW

RE73

390_0402_5%

1 2

PWR_LED#<32>

B B

PWR_LED#
ON/OFFBTN#

2

3

DE5
PESD24VS2UT_SOT23-3~D

1

JPWR

1

1

2

2

5

3

G1

3

6

4

G2

4

ACES_50504-0040N-001

CONN@

Touch pad

Touch Pad LED

12

390_0402_5%
R6

+TPLED

21

A A

C191KSKT-5A

D2

VOS@

A

21

D1
C191KSKT-5A

INS@

A

TP_CLK<24>

TP_DATA<24>

TP_CLK
TP_DATA

2

3

1

+3VS

DE3

PESD5V0U2BT_SOT23-3

JTP

1

1

2

2

5

3

G1

3

6

4

G2

4

ACES_50504-0040N-001

CONN@

CAPS_LED<24>

FAN Control circuit

VCIN0_PH2<24>

1
2
3

GND
GND

2

G

RE60

1 2

240_0402_1%

13

D

S

KSI[0..7]

KSO[0..16]

QE3
SSM3K7002FU_SC70-3~D

KSI[0..7]<24>

KSO[0..16]<24>

+5VS+5VS

HE1 place around FAN area.

+3VLP

+3VALW

RE79

13.7K_0402_1%

100K_0402_1%_TSM0B104F4251RZ

RE74

13.7K_0402_1%@

1 2

1 2

12

VOS@

HE1

INT_KBD Conn.

JKB

1

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
KB_CAPS_PWR

KB_CAPS_PWR-

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

GND

30

30

GND

ACES_51510-03041-001

CONN@

31
32

TOUCH_LED#<24>

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SW/TP/SCREW

LA-8241P

1

1.0

of

25 56Wednesday, February 01, 2012

5

4

3

2

1

D D

SPI ROM 128KB

+3VALW

20mils

1

CE52

0.1U_0402_16V7K

KB930@

2

RE52 0_0402_5%KB930@

FSEL#<24>

FRD#<24>

1 2

FRD# SPI_SO

RE53 0_0402_5%KB930@

12

SPI_FSEL#

UE4

1

CS#

2
3
4

VCC

SO

HOLD#

WP#

SCLK

GND

SI

MX25L1005AMC-12G_SO8

SA00002C100

8
7
6
5

KB930@

SPI_CLK_R
SPI_FWR#

RE540_0402_5% KB930@

12
12

RE550_0402_5% KB930@

SPI_CLK <24>

FWR# <24>

Reserve for EMI please close to U15

1 2

12

22P_0402_50V8J

@

CE53

@

C C

SPI_CLK_R

RE56

33_0402_5%

+5VS +5VS_KBL

1U_0603_10V6K

20mil

CE56

1

KBBL@

2

@

FE1

0.75A_24V_1812L075-24DR~OK

1 2

RE59

0_0805_5%

KBBL@

Keyboard back light

KB_DET#<17>

12

KBBL@

10U_0603_6.3V6M

1

CE57

2

QE4

SSM3K7002FU_SC70-3~D

KBBL@

KB_LED_PWM<24>

13

D

S

RE68

@

1 2

10K_0402_5%

2

G

12

+3VS

RE58
100K_0402_5%

KBBL@

1

G

3

+5VS_KBL

KB_BL_PWM

20mil

6

2

D

QE2
SI3456BDV-T1-E3 1N TSOP6 W/D

S

KBBL@

4 5

JKBL

1

1

2

2

3

3

4

4

5

GND

6

GND

ACES_50519-00401-001

CONN@

Screw Hole

B B

H1

1

H2

1

H3

1

H5

1

H11

1

H_3P3X4P3N

@

H_3P3N

@

H_3P5

@

H_3P7

@

H_2P8

@

Lid Switch

ZZZ1

H4

H_3P5

@

1

H6

H_3P7

@

1

H12

H_2P8

@

1

H8

H7

1

H13

1

H_3P7

@

H_2P8

@

H_3P7

@

1

H15

H_2P8

@

1

H10

H9

H_3P7

@

1

H16

H_2P8

@

1

H14

H_3P7

H_3P7

@

H_2P8

@

@

1

H19

H_2P8

@

1

H21

H20

1

H_2P8

@

1

H_2P8

@

1

H17

1

H22

1

DA80000R900

H_2P8

@

0.1U_0402_16V7K

INS@

H23

H24

H_2P8

H_2P8

@

1

@

1

S-5712ACDL1-M3T1U_SOT23-3

PCB-MB

+3VALW

CE54

1

2

UE5

VDD

2

OUTPUT

GND

INS@

1

12

RE57
10K_0402_5%

1

CE55

0.1U_0402_16V7K

INS@

2

LID_SW#

LID_SW# <24,32>

3

A A

FD1

FD2

FD3

FIDUCAL@

FIDUCIAL@

1

1

5

FD4

FIDUCAL@

FIDUCIAL@

1

1

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Date: Sheet

Title

Size Document Number Rev

Compal Electronics, Inc.

CONN & LID

LA-8241P

1

of

26 56Wednesday, February 01, 2012

1.0

A

B

C

D

E

+5VALW to +5VS

+5VALW

1

CZ1
10U_0805_10V6K

2

1 1

B+_BIAS

DMN66D0LDW-7_SOT363-6

1

2

1 2

RZ4
470K_0402_5%

SUSP

CZ2
10U_0805_10V6K

5

3

QZ2B

4

8
7
6
5

0_0402_5%

QZ1
SI4128DY-T1-GE3_SO8

4

RZ5

0.1U_0603_50V_X7R

1

CZ9

2

+5VS

1
2
3

1

CZ3

2

RZ6

1 2

1.5M_0402_5%~D

1U_0603_10V6K

10U_0805_10V6K

1

CZ4

2

RZ1
470_0603_5%

1 2

+5VS_D

61

QZ2A

DMN66D0LDW-7_SOT363-6

1

CZ5
10U_0805_10V6K

SUSP

2

2

B+_BIAS

PCH_PWR_EN#

+3VALW to +3VS

+3VALW

1

2 2

CZ11
10U_0805_10V6K

2

B+_BIAS

1

2

1 2

RZ13
470K_0402_5%

SUSP

CZ12
10U_0805_10V6K

2

G

QZ7
SI4128DY-T1-GE3_SO8

8
7
6
5

RZ14

39.2K_0402_1%

13

D

QZ9
SSM3K7002F_SC59-3

S

4

0.1U_0603_50V_X7R

1

CZ15

2

RZ15

+3VS

1
2
3

1 2

1

2

1.5M_0402_5%~D

CZ13
10U_0805_10V6K

1

CZ14
1U_0603_10V6K

2

SUSP#<10,24,28,46,47,48>

RZ16
100K_0402_5%

SUSP

2

G

0.1U_0603_50V_X7R

12

1

@

CZ16

2

+3VALW to +3V_PCH

+3VALW

1

CZ6
10U_0805_10V6K

2

1 2

RZ7
470K_0402_5%

+5VALW

12

RZ10
100K_0402_5%

13

D

S

QZ8
SSM3K7002F_SC59-3

2

G

0_0402_5%

13

D

QZ4
SSM3K7002F_SC59-3

S

JP2

112

JUMP_43X79
QZ3
SI4128DY-T1-GE3_SO8

8
7
6
5

4

RZ8

1

2

@

2

+3V_PCH

1
2
3

0.1U_0603_50V_X7R

CZ10

RZ9

1 2

PCH_PWR_EN<24>

1

2

1.5M_0402_5%~D

10K_0402_5%

40mil

CZ7
10U_0805_10V6K

RZ11

1 2

1

CZ8
1U_0603_10V6K

2

PCH_PWR_EN#<19>

@

RZ17
100K_0402_5%

RUN_ON_CPU1.5VS3#<6,10>

PCH_PWR_EN#

2

G

0.1U_0603_50V_X7R

12

1

@

CZ17

2

+5VALW+3VALW

12

13

D

S

RZ12
100K_0402_5%

QZ10
SSM3K7002F_SC59-3

12

RZ3
220_0402_5%

+1.5V_CPU_VDDQ_CHG

13

D

2

G

S

+0.75VS+1.5V_CPU_VDDQ

12

RZ2
22_0603_5%~D

+DDR_CHG

SSM3K7002FU_SC70-3~D

QZ5

SSM3K7002FU_SC70-3~D

13

D

QZ6

2

G

S

+1.5V To +1.5VS

B+_BIAS

12

3 3

13

SUSP

D

2

G

S

+1.5V +1.5VS

RZ18
100K_0402_5%

RZ20

0_0402_5%

QZ11

SSM3K7002FU_SC70-3

UZ1

SI4634DY-T1-E3_SO8~D

8
7
6
5

4

0.1U_0603_50V_X7R

12

1

CZ20

2

2M_0402_5%~D

RZ21

+5VALW

1
2
3

10U_0805_10V6K

1

2

0.1U_0402_16V7K

CZ19

1

2

470_0402_5%

RZ23

+1.5VS

12

RZ19

SYSON#

SYSON<24,28,48>

+3V_PCH

12

+1.5VS_D

RZ24

470_0402_5%

12

+VCCP_D

RZ25

470_0402_5%

12

+3V_D

+3VS+VCCP

12

+3VS_D

RZ26

470_0402_5%

+1.5V

RZ27

470_0402_5%

RZ22
100K_0402_5%

12

+1.5V_D

1

12

2

100K_0402_5%

13

D

QZ12

2

0.1U_0603_50V_X7R

G

SSM3K7002F_SC59-3

S

@

CZ21

CZ18

61

QZ13A

SUSP SUSP

2

4 4

A

SUSP

2N7002DW-7-F_SOT363-6

B

QZ13B

5

3

4

2N7002DW-7-F_SOT363-6

PCH_PWR_EN#

QZ14A

2

61

2N7002DW-7-F_SOT363-6

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

QZ14B

5

Issued Date

3

4

2N7002DW-7-F_SOT363-6

SYSON#

2012/01/17 2013/01/16

C

13

D

2

G

QZ15

SSM3K7002FU_SC70-3

S

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DC/DC Interface

LA-8241P

E

27 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

USB Detected for PWR Share

Express Card

+RTCVCC +RT CVCC +RT CVCC +RTC VCC +RTCVCC +CHGR TC

1 2

D D

C C

R778
100K_0402_5%

12

C4

2.2U_0603_6.3V6K

USB_DETECT# USB_DET#_DELAY

220K_0402_5%

12

R779

12

USB_DETECT# <3 3>

SDMK0340L-7-F

D3

2 1

U1

TC7SZ14FU_SSOP5~D

SDMK0340L-7-F

1

C13

0.1U_0402_16V7K

2

5

1

P

NC

2

A

G

3

2 1

D4

1

C3

0.1U_0402_16V7K

2

CLOSE TO U1

4

Y

R780

1M_0402_5%

EC_ON<24,25>

12

1 2

R781 0_ 0402_5%

Express Card PWR S/W

+1.5VS

+3VS +3.3V_CARD

500mA

0.1U_0402_25V6K

B B

A A

SYSON<24,27,48>

SUSP#<10,24,27,46,47,48>

PM_SLP_S3#<15,24>

5

1

CX3

2

EXP@

1 2

RX8 0_0402_5%

1 2

RX6 0_0402_5%@

1 2

RX7 0_0402_5%

PLT_RST#<6,16,24,32>

+3VS
+3.3V_CARD
+1.5V_CARD

+1.5VS

1

2

EXP@

+3VALW

1A 1A

SYSON_R

0.1U_0402_25V6K

1

2

EXP@

SYSON_R
STBY#_R
PLT_RST#

STBY#_R

CX5

UX1

17

AUXIN

3.3VIN23.3VOUT

12

1.5VIN

20

SHDN#

1

STBY#

6

SYSRST#

19

OC#

4

NC

5

NC

13

NC

14

NC

16

NC

TPS2231MRGPR-2_QFN20_4 X4~D

EXP@

4

0.1U_0402_25V6K

CX4

R787 0_ 0402_5%

@

PCH_SMBCLK<6,11,12,14,29,32>

D5

2

3

1

2

1

BAV70W-7-F_SOT323- 3

C14

0.1U_0402_16V7K

EC_ON_35V <45>

USB_DET#_DELAY <24 >

+3.3V_CARDAUX

PCIE_PRX_EXPTX_N3<14>
PCIE_PRX_EXPTX_P3<14>

+1.5V_CARD

+3.3V_CARDAUX

+3.3V_CARD

USB20_N11<16>

USB20_P11<16>

PCH_SMBDATA<6,11,12,14,29,32>

EXPCLK_REQ#<14>

CLK_PCIE_EXP#<14>
CLK_PCIE_EXP<14>

CX12 0.1U_0402_ 10V7K~DEXP@

1 2

CX13 0.1U_0402_ 10V7K~DEXP@

1 2

PCIE_PTX_EXPRX_N3<14>
PCIE_PTX_EXPRX_P3<14>

USB20_N11

USB20_P11

PCIE_WAKE#<15,24,32>

275mA275mA

3

0.1U_0402_25V6K

EXP@

1

CX8

2

Compal Secret Data

10U_0603_6.3V6M

1

2

500mA

EXP@

1

2

EXP@

CX9

+1.5V_CARD

10U_0603_6.3V6M

0.1U_0402_25V6K

EXP@

1

CX11

CX10

2

Deciphered Date

+3.3V_CARD +3.3V_CARDAUX

0.1U_0402_25V6K

1

2

EXP@

CX1

CX2

2

0.1U_0402_25V6K

10U_0603_6.3V6M

AUXOUT

1.5VOUT

PERST#

CPPE#

CPUSB#

RCLKEN

GND

PAD

15
3
11

8
10
9

18

7
21

EXP@

1

2

CARD_RESET#
EXPRCRD_CPPE#
CPUSB#

EXP@

1

CX6

CX7

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/01/17 2013/01/16

0.1U_0402_25V6K

EXP_USBP11_D­EXP_USBP11_D+
CPUSB#

PCH_SMBCLK
PCH_SMBDATA

PCIE_WAKE#

CARD_RESET#

EXPCLK_REQ#
EXPRCRD_CPPE#
CLK_PCIE_EXP#
CLK_PCIE_EXP

PCIE_PRX_EXPTX_N3_C
PCIE_PRX_EXPTX_P3_C

PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

LX1

1

4

DLW21SN900SQ2_08 05~D

1

EXP@

2

Title

Size Doc ument Numb er Rev

Date: Sheet of

EXP@

1

4

1 2

RX2 0_0402_5%@

1 2

RX3 0_0402_5%@

2

2

3

3

+3VS +3VS

EXP@

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-8241P

JEXP

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

GND

28

GND

TYCO_2-2041070-6~D

CONN@

EXP_USBP11_D-

EXP_USBP11_D+

RX4

2.2K_0402_5%

1 2

1

2.2K_0402_5%
RX5

EXP@

1 2

PCH_SMBCLK

PCH_SMBDATA

28 56Wednesday, February 01, 2012

1.0

+3VS

1 1

FFS_INT2

2 2

A

JP6

1 2

PAD-OPEN1x1m

@

+3VS

2

FFS@

CN1

FFS_INT1<16>
FFS_INT2<17>

PCH_SMBDATA<6,11,12,14,28,32>

PCH_SMBCLK<6,11,12,14,28,32>

12

FFS@

RN2
100K_0402_5%

DMN66D0LDW-7_SOT363-6

61

QN1A

FFS@

10U_0603_6.3V6M

1

2

5

+3.3V_RUN_FFS

1

FFS@

CN2

2

+5V_HDD

12

RN1

@

100K_0402_5%

DMN66D0LDW-7_SOT363-6

3

QN1B

FFS@

4

0.1U_0402_25V6K

FFS_INT2_Q

B

UN1

LNG3DM

1

VDD_IO

14

VDD

11

INT 1

9

INT 2

7

SDO/SA0

6

SDA / SDI / SDO

4

SCL/SPC

8

CS

LNG3DMTR_LGA16_3X3~D

FFS@

+3VS

RN3 10K_0402_5%

RN4 10K_0402_5%

RN5 100K_0402_5 %

10

RES

13

RES

15

RES

16

RES

5

GND

12

GND

2

NC

3

NC

FFS@

1 2

FFS@

1 2

FFS@

1 2

PCH_SMBDATA

PCH_SMBCLK

FFS_INT1

C

D

E

F

G

H

SATA HDD Conn.

JHDD

1

SATA_PTX_DRX_P0_C<13>
SATA_PTX_DRX_N0_C<13>

CN3 0.01U_0402_16V7K

SATA_PRX_DTX_N0<13>

SATA_PRX_DTX_P0<13>

1 2

CN4 0.01U_0402_16V7K

1 2

SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C

SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C

+5V_HDD Source

+3VS

B+_BIAS

+3VALW

12

RN10

100K_0402_5%@

DMN66D0LDW-7_SOT363-6

61

@

HDD_S3.5<24>

100K_0402_5%

2

12

RN12

@

12

100K_0402_5%@

HDD_EN_5V

3

5

4

@

QN5A

+5VALW

RN9

DMN66D0LDW-7_SOT363-6

QN5B

1

@

2

@

6

2

1

D

G

3

0.1U_0603_50V_X7R

CN17

QN4

SI3456DDV-T1-GE3_TSOP6~D

S

+5V_HDD

4 5

10U_0805_10V6K

1

12

@

CN18

RN11

@

2

100K_0402_5%

JP13

@

2

112

JUMP_43X79

SHORT DEFAULT

HDD_DET#<13>

+5V_HDD

+5VS

HDD_DET#

CN8

FFS_INT2_Q

0.1U_0402_25V6K

1

CN9

2

0.1U_0402_25V6K

1

2

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

RESERVED

19

GND

20

VCC12

21

VCC12

22

VCC12

SUYIN_127043FB022G208ZR_RV

CONN@

+5V_HDD+3VS

1000P_0402_50V7K

1

CN6

CN5

2

0.1U_0402_25V6K

CN7

10U_0805_10V6K

1

2

1

2

SATA ODD Conn.

ODD Power Control

3 3

+5VS

1

CN13

RN6
470K_0402_5%

1 2

13

D

QN3
SSM3K7002FU_SC70-3

S

2

ODD_EN

1U_0402_6.3V6K

B+_BIAS

ODD_EN#<17>

4 4

A

2

G

B

JP7

@

112

JUMP_43X79

QN2

D

6

2
1

RN7

G

2

CN16

+5VS_ODD

1

2

S

45

SI3456BDV-T1-E3 1N TSOP6

3

1 2

1.5M_0402_5%~D

C

SATA_PTX_DRX_P2_C<13>

SATA_PTX_DRX_N2_C<13>

SATA_PRX_DTX_N2<13>
SATA_PRX_DTX_P2< 13>

0.1U_0402_25V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

D

2012/01/17 2013/01/16

E

Compal Secret Data

12

CN14 0.01U_0402_16V7K

12

CN15 0.01U_0402_16V7K

ODD_DETECT#<17>

ODD_DA#<16>

Deciphered Date

SATA_PTX_DRX_P2_C
SATA_PTX_DRX_N2_C

SATA_PRX_DTX_N2_C
SATA_PRX_DTX_P2_C

1 2

RN8 0_0402_1%

F

@

+5VS_ODD

ODD_DA#_R

Pleace near ODD CONN

1000P_0402_50V7K

1

1

CN10

2

2

JODD

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

TYCO_2-1759838-8~D

CONN@

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

G

10U_0805_10V6K

0.1U_0402_25V6K

1

CN11

CN12

2

14

GND1

15

GND2

HDD/ODD/FAN

LA-8241P

29 56Wednesday, February 01, 2012

H

1.0

5

4

3

2

1

RA3

RA4

+MICBIASB

3.3K_0402_5%

3.3K_0402_5%

12

12

RA1

RA2

MIC1_L_R

MIC1_R_RMIC1_R

PESD5V0U2BT_SOT23-3

2

3

1

1

CA18

@

CA17

@

LA1

LA2

@

GNDA GNDA

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

220P_0402_50V8J

220P_0402_50V8J

2

2

GNDAGNDA

1

1

CA22

CA23

10P_0402_50V8J

10P_0402_50V8J

@

2

2

close to Codec

1

CA29

2

1000P_0402_50V7K

HDA_BITCLK_AUDIO

RA18
10_0402_1%

@

1 2

2

CA36
10P_0402_50V8J

1

@

1

HPR

1

CA30

CA31

2

1000P_0402_50V7K

2

3

DA1

1

2

3

1

1

1

CA32

2

2

1000P_0402_50V7K

1000P_0402_50V7K

@

@

MIC JACK

JMIC

1

2

6

3

GNDA

4

5

SINGA_2SJ3013-010311F

CONN@

PESD5V0U2BT_SOT23-3

DA2

HeadPhone JACK

JHP

1

2

6

3

GNDA

3

2

1

4

5

SINGA_2SJ3013-010311F

CONN@

PESD5V0U2BT_SOT23-3

2

3

DA5

@

1

PESD5V0U2BT_SOT23-3

DA6

@

PESD5V0U2BT_SOT23-3

DA3

HDA_SYNC_AUDIO

1

CA34
10P_0402_50V8J

2

HDA_SDOUT_AUDIO HDA_RST_AU DIO#

1

CA38
10P_0402_50V8J

2

7

G

8

G

9

G

7

G

8

G

9

G

JSPK

1

1

2

2

3

3

GND

4

4

GND

ACES_87213-0400G

CONN@

+5VS

12

RA17

4.7K_0402_5%@

1

CA37

0.1U_0402_16V7K@

2

GNDA

GNDA

5
6

for EMI

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-8241P

1

30 56Wednesday, February 01, 2012

1.0

+FILT_1.65V

CA4

4.7U_0603_6.3V6K

B_BIAS

C_BIAS

AVEE
FLY_P
FLY_N

1

2

0.1U_0402_16V7K

1

CA12

2

0.1U_0402_16V7K

12
15
17

36

35
34
33

32
31
30

23
22

24

NC

25

NC

21
19
20

AVDD_3.3 pinis output of
internal LDO. NOT connect
to external supply.

AMP_RIGHT
AMP_LEFT

CA26 1U_0 603_10V6K

1

1

CA2

1

CA16

2

4.7U_0603_6.3V6K

SPK_L2+
SPK_L1-

SPK_R2+
SPK_R1-

2

3

BAT54C-7-F_SOT23-3

CA1

+FILT_1.8V

0.1U_0402_16V7K

DA7

2

10

39

38
37

40

11
13

16
14

2

1U_0603_10V6K

UA1

9

RESET#

5

BIT_CLK

8

SYNC

6

SDATA_IN

4

SDATA_OUT

PC_BEEP

SPDIF

GPIO0/EAPD#
GPIO1/SPK_MUTE#

DMIC_CLK

1

DMIC_1/2

LEFT+
LEFT-

RIGHT+
RIGHT-

41

1

12

CA39

1 2

0.1U_0402_16V7K
CA40

1 2

0.1U_0402_16V7K

0.1U_0402_16V7K

3

2

7

18

VDD_IO

FILT_1.8

VAUX_3.3

DVDD_3.3

Vendor
recommend
VDD_IO is
the same
with HDA

GND

CA41

1 2

0.1U_0402_16V7K

RA19
10K_0402_5%

@

@

@

RA22 0_0402_5%

1

CA9

2

HDA_RST_AUDIO#<13>

HDA_BITCLK_AUDIO<13>

HDA_SYNC_AUDIO<13>

HDA_SDOUT_AUDIO<13>

Reserve for EMI

1 2

1 2

4.7U_0603_6.3V6K

HDA_SDIN0<13>

EC_MUTE#<24>

CA10

EAPD<24,31>

RA23 0_0402_5%

1

1

2

CA11

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1 2

1 2

1 2

RA15 33_0402_5%

1 2

RA14 0_0402_5%

1 2

Beep

EC

ICH Beep

+VDD_IO

1

CA13

1

2

CA15

0.1U_0402_16V7K

2

HDA_RST_AUDIO#

RA7 0_0402_5%

HDA_SYNC_AUDIO

RA5 33_0402_5%

HDA_SDOUT_AUDIO

PC_BEEP

@

RA10 0_0402_5%

12

RA11 0_0402_5%

CA25 15P_0402_50V8J@

CA24 15P_0402_50V8J@

1

1

Internal SPEAKER

2

2

BEEP#<24>

HDA_SPKR<13>

+3V_PCH

D D

+3VS

C C

MIC_CLK<22>

MIC_DATA<22>

B B

PC Beep

A A

1

CA3

2

26

29

27

28

FILT_1.65

AVDD_3.3

AVDD_HP

CLASS-D_REF

CX20672-21Z_QFN40_6X6

PC_BEEP

LPWR_5. 0

RPWR_5 .0

AVDD_5V

SENSE_A

PORTB_R

PORTB_L

PORTC_R

PORTC_L

PORTA_R

PORTA_L

GND GNDA

5

4

+LDO_OUT_3.3V

1

CA6

0.1U_0402_16V7K

MIC1_R
MIC1_L

1

2

1

2

0.1U_0402_16V7K

+MICBIASB

4.7U_0603_6.3V6K

CA7

1

CA8

2

2

10U_0603_6.3V6M

+3VS

HP_PLUG

OUTPUT 1Vrms

SPK_L2+_CONN<31>

SPK_L1-_CONN<31>

SPK_R2+_CONN<31>

SPK_R1-_CONN<31>

1

+5VS

SENSE_A MIC1_PLUG

CA20 4.7U_0603_6.3V6K

1 2

CA19 4.7U_0603_6.3V6K

1 2

1 2

CA21 1000P_0402 _50V7K

@

RA12 39.2_0402_1%

1 2

RA13 39.2_0402_1%

1 2

1 2

CA5

2

1

CA14

Please bypass caps very close to device.

2

0.1U_0402_16V7K

RA6 5.11K_0402_1%

1 2

RA8 20K_0402_1%

1 2

RA9 39.2K_0402_1%

1 2

AMP_RIGHT <31>
AMP_LEFT <31>

HP_R
HP_L

1

CA27

CA28

@

2

0.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

+5VS

MIC1_L

10U_0603_6.3V6M

MIC1_PLUG

HP_L HPL

HP_R

HP_PLUG

SPK_R1­SPK_R2+
SPK_L1­SPK_L2+

1 2

100_0402_1%

1 2

100_0402_1%

1 2

FBMA-L10-160808-800LMT_2P

1 2

FBMA-L10-160808-800LMT_2P

Close to UA1
Pi

n11,13,14,16

LA3 0_0603_5%

1 2

LA4 0_0603_5%

1 2

LA5 0_0603_5%

1 2

LA6 0_0603_5%

1 2

wide 30MIL

SPK_L2+_CONN

SPK_L1-_CONN

SPK_R2+_CONN

SPK_R1-_CONN

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

5

LA9
FBMA-L11-160808-121LMA30T_0805

1

2

1 2

1

AMP@

CA43

0.1U_0402_16V7K

2

AMP@

AMP_LEFT<30>

AMP_RIGHT<30>

12

AMP@

B+

CA42

10U_1206_25V6M

AMP@

D D

Close to LA9

Need final turn R/C

+PVDD

12

12

CA47

CA44

1U_0603_25V6K

1U_0603_25V6K

Close to UA2
Pin7,15,16,27,28

AMP@

AMP@

AMP_LEFT

1 2

240K_0402_1%

AMP_RIGHT

1 2

240K_0402_1%

1U_0603_25V6K

AMP@

AMP@

CA48

AMP@

RA37

RA39

12

10/24

TPA3113 for Speaker

+5VS

@

C C

RA33
100K_0402_1%

1 2

RA34
100K_0402_1%

1 2

AMP@

@

RA35
100K_0402_1%

1 2

GIN1GIN0

RA36
100K_0402_1%

1 2

AMP@

GAIN1 GAIN0

0

0

1 0

1 1

AV(inv)

0

1

40mil

12

CA45

1U_0603_25V6K

AMP@

12

12

20dB

26dB

32dB

36dB

4

CA46

1U_0603_25V6K

RA38
10K_0402_5%

@

RA40
10K_0402_5%

@

+3VALW

EAPD<24,30>

INPUT
IMPEDANCE

60Kohm

30Kohm

15Kohm

9Kohm

CA49

1 2

AMP@

CA51

1 2

AMP@

1 2

1 2

0.027U_0402_16V6K

0.027U_0402_16V6K

RA24
100K_0402_5%

@

RA25
0_0402_5%

AMP@

3

+PVDD SPK_L2+_CONN

AMP_LEFT_C

1 2

0.027U_0402_16V6K

CA50

AMP@

AMP_RIGHT_C

1 2

0.027U_0402_16V6K

CA52

AMP@

GIN0

GIN1

EAPD_R

12

RA26
100K_0402_5%

AMP@

UA2

7

AVCC

15

PVCCR

16

PVCCR

27

PVCCL

28

PVCCL

3

LINP

4

LINN

12

RINP

11

RINN

5

GAIN0

6

GAIN1

1

SD#

2

FAULT#

13

NC

29

GND

TPA3113D2PWPR_H TSSOP28

AMP@

BSPL

OUTPL

OUTNL

BSNL

BSPR

OUTPR

OUTNR

BSNR

PBTL

PLIMIT

GVDD

PGND
PGND
AGND

26

25

23

22

17

18

20

21

14

10

9

24
19
8

BSPL

BSNL

BSPR

BSNR

PLIMIT

+GVDD

CA53

0.22U_0603_25V7K

1 2

AMP@

1 2

AMP@

1 2

AMP@

1 2

CA56

0.22U_0603_25V7K

AMP@

+GVDD

1U_0603_25V6K

CA58

12

AMP@

OUTPL

OUTNL

CA54

0.22U_0603_25V7K

CA55

0.22U_0603_25V7K

OUTPR

OUTNR

+GVDD

12

1U_0603_25V6K

12

CA57

12

AMP@

AMP@

RA27

28.7K_0402_1%

AMP@

RA28
10K_0402_1%

2

OUTPL

OUTNL

OUTPR

OUTNR

Close to LA6

LA7
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

AMP@

Close to LA5

LA8
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

AMP@

Close to LA4

LA10
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

AMP@

Close to LA3

LA11
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

AMP@

SPK_L1-_CONN

SPK_R2+_CONN

SPK_R1-_CONN

1

SPK_L2+_CONN <30>

SPK_L1-_CONN <30>

SPK_R2+_CONN <30>

SPK_R1-_CONN <30>

+RTCBATT +RTCVCC

C5

1 2

GCLK@

22U_0805_6.3V6M

CLK_X1
CLK_X2

SLG3NB274VTR_TQFN16_2X3

U2

10

VBAT

15

2

8

3

1

16

VDD_RTC_OUT

+V3.3A

VDD

VDDIO_27M1127MHz

VDDIO_25M_A

VDDIO_25M_B

XTAL_IN
XTAL_OUT

GCLK@

GND1

4

25MHz_A

25MHz_B

GND2

7

UMA only

U2

SLG3NB244VTR_TQFN 16_2X3

@

4

2.2U_0603_6.3V6K

1

C10

14

9

32kHz

VGA_X1_R

12

LAN_X1_R

6

PCH_X1_R

5

GND3

GND4

13

17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

GCLK@

2

PCH_RTCX1_R <13>

GCLK@

R785

1 2

33_0402_5%

R782

GCLK@

1 2

33_0402_5%

R783

1 2

0_0402_5%

GCLK@

LAN_X1_R

reserved for swi ng level adjust ment
(close to U2)

VGA_X1 <35>

LAN_X1 <14>

PCH_X1 <14>

R784
0_0402_5%

1 2

@

2012/01/17 2013/01/16

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

AMP

LA-8241P

1

31

1.0

56Wednesday, February 01, 2012

0.1U_0402_16V7K

1

2

GCLK@

C8

+3VLP

1

2

0.1U_0402_16V7K

1

C12
33P_0402_50V8K

GCLK@

2

GCLK@

C9

+3VLP

+1.8VGS

+3VALW

+VCCP

1

2

GCLK@

C7

GND

4

3

GCLK@

+3VALW+VCCP

3

+1.8VGS

B B

A A

Depop if GCLK
with UMA

GCLK@

1

C6

2

0.1U_0402_16V7K

CLK_X1 CLK_X2

1

C11
33P_0402_50V8K

GCLK@

2

5

0.1U_0402_16V7K

Y1
25MHZ_20PF_7V25000016

1

1

GND

2

5

4

3

2

1

0_0402_1%@

USB3RP3_R

R771

USB3RP3<16>
USB3RN3<16>

USB3TP3<16>

USB3TN3<16>

USB3RP4<16>
USB3RN4<16>

D D

C C

USB3TP4<16>

USB3TN4<16>

USB20_P2<16>
USB20_N2<16>

USB20_P3<16>
USB20_N3<16>

USB20_P4<16>
USB20_N4<16>

USB20_P5<16>
USB20_N5<16>

SATA_PRX_DTX_P1< 13>
SATA_PRX_DTX_N1<13>

SATA_PTX_DRX_P1_C<13>

SATA_PTX_DRX_N1_C<13>

WLAN_WAK E#<24>

1 2

R772

1 2

0_0402_1%@

0_0402_1%@
R775

1 2

R776

1 2

0_0402_1%@

+3VS

SATA_PRX_DTX_P1
SATA_PRX_DTX_N1

SATA_PTX_DRX_P1_C
SATA_PTX_DRX_N1_C

+1.5VS

+3VS

+5VALW

USB3RN3_R

USB3RP4_R
USB3RN4_R

To Finger Print

2

C1

0.1U_0402_25V6K

1

JFP

1

USB20_P8<16>

B B

USB20_N8<16>

PESD5V0U2BT_SOT23-3

2

3

D6

@

1

2
3
4
5
6

ACES_51524-0060N-001

CONN@

1
2
3
4
5
6

+3VS

G1
G2

JBTB1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

GND

ACES_88079-0800A1

CONN@

7
8

GND

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

DASH_SW1<24>
DASH_SW2<25>
DASH_SW3<24>

DASH_LED1#<24>
DASH_LED2#<24>
DASH_LED3#<24>

+5VS

R777

10K_0402_5%

0.1U_0402_16V7K

USB_OC2# <16>

USB_OC3# <16>

BT_ON# <17>
WL_OFF# <16>
USB_EN# <24,33>

PCIE_WAKE# <15,24,28>
WLAN_CLKREQ# <14>
PLT_RST# <6,16,24,28>
LAN_CLKREQ# <14>
WOL_EN# <24>
AOAC_ON <24>

EC_TX <24>

EC_RX <24>

PCH_SMBCLK <6,11,12,14,28,29>
PCH_SMBDATA <6,11,12,14,28,29>

HDD_DETECT# <17>

B+_BIAS
+3VALW

PCIE_PRX_WLANTX_ P2 <14>

PCIE_PRX_WLANTX_ N2 <14>

PCIE_PTX_WLANRX_ P2 <14>
PCIE_PTX_WLANRX_ N2 <14>

CLK_PCIE_WLAN <14>

CLK_PCIE_WLAN# <14>

PCIE_PTX_LANRX_P1 <14>

PCIE_PTX_LANRX_N1 <14>

PCIE_PRX_LANTX_P1 <14>

PCIE_PRX_LANTX_N1 <14>

CLK_PCIE_LAN <14>

CLK_PCIE_LAN# <14>

LID_SW# <24,26>

CLK_LAN_25M <14>

Function/B

TO

1
2

13

D

2

G

S

3
4
5
6
7
8

Q3
SSM3K7002FU_SC70-3~D

+DAS_PWR

Q2
AP2301GN-HF_SOT23-3

3 1

2

12

1

C2

2

<---WLAN (Mini Card 1)

<---10/100/1G LAN

JFC

1
2
3
4
5

9

6

G1

10

7

G2

8

ACES_51524-0080N-001

CONN@

DASH_LED_PWM <24>

To CardReader/B

* Inspiron only

USB20_N10<16>

USB20_P10<16>

USB20_N10

USB20_P10

To CardReader/B

* Vostro only

USB20_N10_R

USB20_P10_R

DLW21SN900SQ2_0805~D

1

1

4

4

L1

R1 0_ 0402_5%@

R2 0_ 0402_5%@

R9 0_ 0402_5%VOS@

R10 0_0402_5%VOS@

USB10N_R

USB10P_R

+3VS

INS@

1 2

1 2

1 2

1 2

+3VS

JCR1

1

1

2

2

3

3

4

4

ACES_50504-0040N-001

CONN@

2

2

3

3

JCR2

1

1

2

2

3

3

4

4

ACES_50504-0040N-001

CONN@

5

G1

6

G2

USB20_N10_R

USB20_P10_R

USB10N

USB10P

5

G1

6

G2

To LED/B

+5VALW

10mils, All pins

PWR_LED#<25>

A A

PWR_PWM _LED#<24>

R786
100K_0402_5%

PWR_LED#

13

D

2

G

S

12

5

Q1

2N7002_SOT23

PCH_SATALED#<13>
BATT_CHG_LED#<24>
BATT_LOW_LED#<24>
WL_BT_LED#<24>

+5VS

JLED

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

ACES_51524-0080N-001

CONN@

4

9

G1

10

G2

+5VS

PWR_LED#
PCH_SATALED#
BATT_CHG_LED#
BATT_LOW_LED#
WL_BT_LED#

+5VALW

JLED2

1

1

2

2

3

3

4

4

5

5

6

9

6

G1

7

10

7

G2

8

8

ACES_51524-0080N-001

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

USB10N

USB10P

L2

VOS@

1

1

4

4

DLW21SN900SQ2_0805~D

1 2

R8 0_ 0402_5%@

1 2

R7 0_ 0402_5%@

Title

PROCESSOR(1/6) DMI,FDI,PEG

Size Document Number Rev

LA-8241P

Date: Sheet of

USB10N_R

2

2

USB10P_R

3

3

Compal Electronics, Inc.

1

32 56Wednesday, February 01, 2012

1.0

5

USB3RN1<16>

USB3RP1<16>

D D

USB3TN1<16>

USB3TP1<16>

C C

USB3RN1

USB3RP1

USB3TN1

CI3 0.01U_0402_16V7K

USB3TP1

CI4 0.01U_0402_16V7K

12

USB3TP1_C U SB3TP1_R

12

1

4

RI1 0_0402_5%@

RI2 0_0402_5%@

USB20_P0<16>

USB20_N0<16>

LI1

1

4

DLW21SN900HQ2L_0805_4P~D

1 2

1 2

2

2

3

3

LI3

1

1

4

4

DLW21SN900HQ2L_0805_4P~D

1 2

RI4 0_0402_5%@

1 2

RI6 0_0402_5%@

USB20_P0

USB20_N0

USB3RN1_R

USB3RP1_R

2

2

3

3

LI2

1

1

4

4

DLW21SN900SQ2L_0805_4P~D

1 2

RI3 0_0402_5%@

1 2

RI5 0_0402_5%@

4

+5VALW

1

1

2

USB_EN#

CI14

0.1U_0402_16V7K

2

1

CI13

0.1U_0402_16V7K

2

CI12

4.7U_0805_10V4Z

USB_EN#<24,32> USB_OC0# <16>

USB3TN1_RUSB3TN1_C

USB20_P0_R

2

2

USB20_N0_R

3

3

UI3

1

GND

2

VIN
VIN3VOUT

4

EN

USB3RP1_R

USB3RN1_R

USB3TP1_R

USB3TN1_R

2.0A

3

+5V_USB_PWR1

8

VOUT

7

VOUT

6
5

FLG

EPAD

9

AP2301MPG-13_MSOP8

DI1

1

2

4

5

3

8

IP4292CZ10-TB_XSON10U10~D

80mil

1 2

RI19

0_0402_1%

@

10

9

7

6

USB3RP1_R

USB3RN1_R

USB3TP1_R

USB3TN1_R

1

CI15

0.1U_0402_16V7K

2

+5VALW

+5V_USB_PWR1

CI1

220U_6.3V_M

2

1

USB conn.1

0.1U_0402_25V6K

1

1

+

2

CI2

3

2

USB3TP1_R

USB3TN1_R
USB20_P0_R

USB20_N0_R
USB3RP1_R

2

DI2

PESD5V0U2BT_SOT23-3

USB3RN1_R

1

JUSB1

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND
D-2GND

6

SSRX+

4

GND

5

SSRX-

TAITW_PUBAU1-09FNLSC NN4H0

CONN@

GND
GND
GND

10
11
12
13

+5VALW

USB3RN2_R

USB3RP2_R

USB3TN2_R

USB3TP2_R

100K_0402_5%

4.7U_0805_10V4Z

RI11

1 2

SSM3K7002FU_SC70-3~D

13

D

2

G

QI1

S

DI4

1

2

4

5

3

8

IP4292CZ10-TB_XSON10U10~D

2012/01/17 2013/01/16

UI1

RI7 0_0402_5%

PWRSHARE_OE#<24>

B B

USB3RN2<16>

USB3RP2<16>

USB3TN2<16>

USB3TP2<16>

A A

USB3RN2

USB3RP2

USB3TN2

USB3TP2

1 2

USB20_N1<16>
USB20_P1<16>

1

4

RI13 0_0402_5%@

RI14 0_0402_5%@

12

CI10 0.01U_0402 _16V7K

USB3TP2_C U SB3TP2_R

12

CI11 0.01U_0402 _16V7K

SB#

8

CB

7

TDM

6

TDP

5

+5VALW

1

2

LI4

1

4

DLW21SN900HQ2L_0805_4P~D

1 2

1 2

VDD

SLG55584AVTR_TDFN8_2X2

CI5

0.1U_0402_25V6K

2

2

3

3

LI6

1

1

4

4

DLW21SN900HQ2L_0805_4P~D

1 2

RI17 0_0402_5%@

1 2

RI18 0_0402_5%@

CEN

SELCDP

Thermal Pad

2

2

3

3

1
2

DM

3

DP

4
9

USB3RN2_R

USB3RP2_R

USB20_N1_SW
USB20_P1_SW

USB3TN2_RUSB3TN2_C

PWRSHARE_EN

SEL

RI10

1 2

@

RI12
10K_0402_5%

1 2

10K_0402_5%

+5VALW

USB20_P1_SW

USB20_N1_SW

SDMK0340L-7-F_SOD323-2~D

PWRSHARE_EN _EC#<24>

LI5

4

4

1

1

DLW21SN900SQ2L_0805_4P~D

1 2

RI15 0_0402_5%@

1 2

RI16 0_0402_5%@

PWRSHARE_EN

DI3

3

2

+3VALW

3

2

12

RI8
10K_0402_5%

1 2

USB20_P1_R

USB20_N1_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

1

CI6

2

PWRSHARE_EN #

USB3RN2_R

10

USB3RP2_R

9

USB3TN2_R

7

USB3TP2_R

6

Compal Secret Data

1

CI7

0.1U_0402_16V7K

2

Deciphered Date

+5V_USB_PWR2

CI8

220U_6.3V_M

1
2

4

1

+

2

2

2.0A

UI2

GND

VOUT
VOUT

VIN
VIN3VOUT
EN

EPAD

9

AP2301MPG-13_MSOP8

1

2

+5V_USB_PWR2

8

80mil

7
6
5

FLG

RI20

0_0402_1%

1 2

@

1

CI17

0.1U_0402_16V7K

2

USB_OC1# <16>

USB conn.2

USB_DETECT#<28>

0.1U_0402_25V6K

CI9

3

@

USB3TP2_R

USB3TN2_R
USB20_P1_R

USB20_N1_R
USB3RP2_R

2

DI5

PESD5V0U2BT_SOT23-3

USB3RN2_R

1

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-8241P

JUSB2

9

D1-DP

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6
4
5

GND
GND

SSRX+
GND

GND

SSRX-

GND

TAITW_USB011-107BRL-TW

CONN@

1

33 56Wednesday, February 01, 2012

10

11
12
13
14

1.0

of

5

4

3

2

1

GFX PCIE LANE REVERSAL

PEG_HTX_C_GRX_P[7..0]<5>

PEG_HTX_C_GRX_N[7..0]<5>

PEG_HTX_C_GRX_P[7..0]

PEG_HTX_C_GRX_N[7..0]

UV1A

PEG_GTX_C_HRX_P[7..0]

PEG_GTX_C_HRX_N[7..0]

PEG_GTX_C_HRX_P[7..0] <5>

PEG_GTX_C_HRX_N[7..0] <5>

D D

C C

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7

12/8 Remove RX8~15

B B

CLK_PEG_VGA<14>
CLK_PEG_VGA#<14>

A A

CLK_PEG_VGA
CLK_PEG_VGA#

RV64

1 2

1K_0402_5%

GPU_RST#

DIS@

12

DIS@

RV66
100K_0402_5%

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

PWRGOOD

AA30

PERSTB

THAMES XT M2 TH@

UV1

CLOCK

CH@

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

PCIE_TX8P

PCIE_TX8N

PCIE_TX9P

PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

PCIE_CRX_C_GTX_P0

Y33

PCIE_CRX_C_GTX_N0

Y32

PCIE_CRX_C_GTX_P1

W33

PCIE_CRX_C_GTX_N1 PEG_GTX_C_HRX_N1

W32

PCIE_CRX_C_GTX_P2

U33

PCIE_CRX_C_GTX_N2

U32

PCIE_CRX_C_GTX_P3

U30

PCIE_CRX_C_GTX_N3 PEG_GTX_C_HRX_N3

U29

PCIE_CRX_C_GTX_P4

T33

PCIE_CRX_C_GTX_N4 PEG_GTX_C_HRX_N4

T32

PCIE_CRX_C_GTX_P5

T30

PCIE_CRX_C_GTX_N5 PEG_GTX_C_HRX_N5

T29

PCIE_CRX_C_GTX_P6

P33

PCIE_CRX_C_GTX_N6

P32

PCIE_CRX_C_GTX_P7

P30

PCIE_CRX_C_GTX_N7 PEG_GTX_C_HRX_N7

P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

12/8 Remove CV59~CV74 TX8~15

CV43220nF_0402_16V7K DIS@

12

CV44220nF_0402_16V7K DIS@

12

CV45220nF_0402_16V7K DIS@

12

CV46220nF_0402_16V7K DIS@

12

CV47220nF_0402_16V7K DIS@

12

CV48220nF_0402_16V7K DIS@

12

CV49220nF_0402_16V7K DIS@

12

CV50220nF_0402_16V7K DIS@

12

CV51220nF_0402_16V7K DIS@

12

CV52220nF_0402_16V7K DIS@

12

CV53220nF_0402_16V7K DIS@

12

CV54220nF_0402_16V7K DIS@

12

CV55220nF_0402_16V7K DIS@

12

CV56220nF_0402_16V7K DIS@

12

CV57220nF_0402_16V7K DIS@

12

CV58220nF_0402_16V7K DIS@

12

Chelsea Only

1 2

RV198 1.69K_0402_1%~DCH@

+1.0VGS

Thames/seymour Only

Y30

Y29

1 2

1 2
1 2

Install 2K for Thames/Seymour

RV631.27K_0402_1% DIS@

RV652K_0402_1% DIS@

+1.0VGS

RV2031K_0402_1% CH@

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P1

PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P3

PEG_GTX_C_HRX_P4

PEG_GTX_C_HRX_P5

PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P7

DGPU_HOLD_RST#<16>

PCH_PLTRST#<16>

0.1U_0402_25V6K

LVDS Interface

UV1G

LVDS CONTROL

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P

TXOUT_U0N_D PF2N

TXOUT_U1P_DPF1P

TXOUT_U1N_D PF1N

TXOUT_U2P_DPF0P

TXOUT_U2N_D PF0N

LVTMDP

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

THAMES XT M2 @

RV61 0_0402_5%@

+3VGS

5

2

P

B

1

A

G

DIS@

3

MC74VHC1G08DFT2G SC70 5P

CV326

DIS@

2

1

VARY_BL

DIGON

TXOUT_U3P
TXOUT_U3N

TXOUT_L3P
TXOUT_L3N

12

UV13

4

Y

AK27
AJ27

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35
AG36

AP34
AR34

AW37
AU35

AR37
AU39

AP35
AR35

AN36
AP37

GPU_RST#

Security Classification

Chelsea Pro

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/01/17 2013/01/16

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

ATI_SeymourXT_M2_PCIE/LVDS

LA-8241P

34 56Wednesday, February 01, 2012

1

1.0

5

+1.8VGS

RV67 10K_0402_5%X76@

1 2

RV68 10K_0402_5%X76@

1 2

RV69 10K_0402_5%X76@

1 2

RV70 10K_0402_5%X76@

1 2

RV71 10K_0402_5%X76@

1 2

RV72 10K_0402_5%X76@

1 2

D D

VRAM_ID0

VRAM_ID1

VRAM_ID2

Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2

H5TQ1G63DFR-11C

64MX16 (1G)

Hynix 1GB

*

PN:SA000041S3L

K4W1G1646G-BC11

64MX16 (1G)

Samsung 1GB

*

PN:SA00004GS1L

H5TQ2G63BFR-11C

128M16 (2G)

Hynix 2GB
PN:SA00003YO1L

K4W2G1646C-HC11

128M16 (2G)

Samsung 2GB
PN:SA000047Q1L

MT41J64M16JT-107G

64MX16 (1G)

Micron 1GB

*

PN:SA00004Y20L

+3VGS

LV14

LV15

DIS@

12

(Thames 125mA)

DIS@

0.935V@Chelsea

12

3

27MHZ_16PF_7V2700001 1

STRAPS

(Thames 75mA)

1

CV82

2

DIS@

10U_0603_6.3V6M

1

CV86

2

DIS@

10U_0603_6.3V6M

DIS@

1M_0402_5%

3

GND

4

PEG_A_CLKRQ#<14 >

C C

+3VGS

+1.8VGS

BLM15BD121SN1D_0402

B B

+1.0VGS

BLM15BD121SN1D_0402

DIS@

CV94

18P_0402_50V8J

A A

1 2
1 2
1 2

1 2

1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2

1U_0402_6.3V6K

1U_0402_6.3V6K

RV97

GND

DIS@

1

CV83

2

DIS@

1

CV87

2

DIS@

XTALINXTALOUT

YV1

1

2

5

RV67

RV70

1 0

RV69

RV68

0 0

1

RV67

RV70

0

1 1

RV68

RV69

0

1 1

RV67 RV69 RV71

1 1 1

RV7510K_0402_5% DIS@

GPU_GPIO0

RV7610K_0402_5% DIS@

GPU_GPIO1

RV7710K_0402_5% @

GPU_GPIO2

RV7810K_0402_5% @

AC_BATT

RV7910K_0402_5% @

GPU_GPIO8

RV8010K_0402_5% @

GPU_GPIO9

RV8110K_0402_5% DIS@

GPU_GPIO11

RV8210K_0402_5% @

GPU_GPIO12

RV8310K_0402_5% @

GPU_GPIO13

RV8510K_04 02_5% @

GPIO24_TRSTB

RV8610K_04 02_5% @

GPIO25_TDI

RV8710K_04 02_5% @

GPIO27_TMS

RV8810K_04 02_5% @

GPIO26_TCK

+DPLL_PVDD

1

CV84

2

DIS@

0.1U_0402_16V7K

+DPLL_VDDC

1

CV88

2

DIS@

0.1U_0402_16V7K

DIS@

CV95

18P_0402_50V8J

+1.8VGS

+3VGS

1 3

2N7002_SOT23-3

0_0402_5%

1

+3VGS

12

RV235
10K_0402_5%

@

12

RV236
10K_0402_5%

CH@

Add 12/6 for MLPS

(Thames 5mA)

BLM15BD121SN1D_0402

2

G

D

S

@

QV28

RV200

12

@

RV72

0

RV72

RV71

RV71

+1.8VGS

DIS@

RV93 499 _0402_1%

DIS@

RV95 249 _0402_1%

CV81 0.1U_0402_16V7K

DIS@

TS_FDO

DIS@

LV16

1 2

+3VGS

PT

PT

PT

VDDCI_VID<53>

GPU_VID0<52>
GPU_VID2<52>

RV89 10K_040 2_5%@

1 2

GPU_VID1<52>

T78

T79

0.60 V level, Please
VREFG Divider ans
cap close to ASIC

12

12

12

0_0402_5%

1 2

TH@

XTALIN
Voltage Swing: 1.8 V

(1.8V@20mA TSVDD)

1

CV91

2

DIS@

12

RV199

2.2K_0402_5%

@

VGA_CLKREQ#_R

VGA_CLKREQ#_R

RV248

GPU_THERMAL_D+

GPU_THERMAL_D-

10U_0603_6.3V6M

VRAM_ID0
VRAM_ID1
VRAM_ID2

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
VGA_SMB_DA2
VGA_SMB_CK2
AC_BATT
VDDCI_VID

GPU_GPIO8
GPU_GPIO9

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

GPU_VID0
GPU_VID2
THM_ALERT#

GPU_VID1

GPIO21_BBEN

GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS

GPIO28_TDO

+VREFG_GPU

+VREFG_GPU

+DPLL_PVDD
DPLL_PVSS

+DPLL_VDDC

TS_FDO

+TSVDD

1

CV92

2
DIS@

1U_0402_6.3V6K

R02

20mil

20mil

20mil

XTALIN
XTALOUT

10mil

1

CV93

2

DIS@

0.1U_0402_16V7K

4

AR10
AW10
AU10
AP10

AR12
AW12
AU12
AP12

AK21

AK26

AH20
AH18
AN16
AH23

AH17

AK17

AH15

AK16

AM16
AM14
AM13
AK14
AG30
AN14
AM17

AK13
AN13
AM23
AN23
AK23

AM24

AK19

AK20

AH26
AH24

AK24

AH13

AM32
AN32

AN31

AU34

AW34

AW35

AG29

AK32

4

UV1B

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

AJ21

SWAPLOCKA
SWAPLOCKB

SCL

AJ26

SDA

GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA

AJ23

GPIO_4_SMBCLK
GPIO_5_AC_BATT

AJ17

GPIO_6
GPIO_7_BLON

AJ13

GPIO_8_ROMSO
GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK
GPIO_11

AL16

GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK

AL24

JTAG_TMS
JTAG_TDO

AJ19

GENERICA
GENERICB

AJ20

GENERICC
GENERICD

AJ24

GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

HPD1

VREFG

DPLL_PVDD
DPLL_PVSS

DPLL_VDDC

AV33

XTALIN
XTALOUT

XO_IN

XO_IN2

AF29

DPLUS
DMINUS

TS_FDO

AL31

TS_A/NC

AJ32

TSVDD

AJ33

TSVSS

THAMES XT M2

@

VGA_X1<31>

MUTI GFX

I2C

PLL/CLOCK

THERMAL

RV232 0_0402_5%

DPA

DPB

DPC

DPD

DAC1

DAC2

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

DDC/AUX

close to YV1

1 2

GCLK@

TXCAP_DPA3P
TXCAM_DPA3N

TX0P_DPA2P
TX0M_DPA2N

TX1P_DPA1P
TX1M_DPA1N

TX2P_DPA0P
TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

TXCCP_DPC3P

TXCCM_DPC3N

TX0P_DPC2P

TX0M_DPC2N

TX1P_DPC1P

TX1M_DPC1N

TX2P_DPC0P

TX2M_DPC0N

TXCDP_DPD3P

TXCDM_DPD3N

TX3P_DPD2P

TX3M_DPD2N

TX4P_DPD1P

TX4M_DPD1N

TX5P_DPD0P

TX5M_DPD0N

HSYNC
VSYNC

RSET

AVDD

AVSSQ

VDD1DI
VSS1DI

R2/NC

R2B/NC

G2/NC

G2B/NC

B2/NC

B2B/NC

COMP/NC

VDD2DI/NC
VSS2DI/NC

A2VDD/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

R2SET/NC

DDC1CLK

DDC1DATA

AUX1P
AUX1N

DDC2CLK

DDC2DATA

AUX2P
AUX2N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

DDCCLK_AUX7P

DDCDATA_AUX7N

XTALIN

3

AU24
AV23

AT25
AR24

AU26
AV25

AT27
AR26

AR30
AT29

AV31
AU30

AR32
AT31

AT33
AU32

AU14
AV13

AT15
AR14

AU16
AV15

ACIN<15,24,43,44>

AT17
AR16

AU20
AT19

ACIN_65W<24>

AT21
AR20

AU22
AV21

AT23
AR22

Not share via for other GND

AD39

R

AD37

RB

AE36

G

AD35

GB

AF37

B

AE38

BB

AC36
AC38

AB34

AD34
AE34

AC33
AC34

AC30
AC31

AD30
AD31

AF30
AF31

AC32

C/NC

AD32

Y/NC

AF32

AD29
AC29

AG31
AG32

AG33

AD33

AF33

AA29

AM26
AN26

AM27
AL27

AM19
AL19

AN20
AM20

AL30
AM30

AL29
AM29

AN21
AM21

AJ30
AJ31

AK30
AK29

VGA_CRT_R <21>

VGA_CRT_G <21>

VGA_CRT_B <21>

VGA_CRT_HSYNC <21>
VGA_CRT_VSYNC <2 1>

RV84 499_04 02_1%DIS@

1 2

10mil

+AVDD

(1.8V@65mA AVDD)

10mil

+VDD1DI

(1.8V@100mA VDD1DI)

1

1

CV79

CV78

2

2

PS_1

1U_0402_6.3V6K

DIS@

DIS@

0.1U_0402_16V7K

RV246

+DPLL_PVDD

1 2

0_0402_5%@

RV247

DPLL_PVSS

1 2

0_0402_5%@

GENLK_CLK
GENLK_VSYNC

PS_2

PS_3

T80
T81

NC_TSVSSQ should be tied to GND on Thames/Seymour

Reserved test pad of CRT Signals for debug

VGA_CRT_CLK
VGA_CRT_DATA

VGA_CRT_CLK <21>
VGA_CRT_DATA <21>

+3VGS

DIS@

RV250

1 2

2

0_0402_5%@

RV251

1 2

0_0402_5%DIS@

Reserved test pad of CRT Signals for debug

100mA

1 2

LV13

DIS@

BLM15BD121SN1D_0402

1

CV80

2

DIS@

10U_0603_6.3V6M

Add 12/8

RV207

1 2

0_0402_5%DIS@

for debug CRT

RV216 10K_0402_5%@

VGA_CRT_VSYNC
VGA_CRT_HSYNC
VGA_CRT_CLK
VGA_CRT_DATA

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

1 2

RV217 10K_0402_5%@

1 2

RV218 10K_0402_5%@

1 2

RV219 10K_0402_5%@

1 2

RV220 150_0402_1%@

1 2

RV221 150_0402_1%@

1 2

RV222 150_0402_1%@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VGS

12

RV73

DIS@

PACIN#

3

5

4

1

CV75

2

DIS@

0.1U_0402_16V7K

10K_0402_5%

AC_BATT

DIS@

QV14B
2N7002DW-7-F_SOT363-6

1

CV76

2

1U_0402_6.3V6K

DIS@

12

RV74

4.7K_0402_5%DIS@

61

QV14A
2N7002DW-7-F_SOT363-6

+1.8VGS

CRT

+3VGS

2012/01/17 2013/01/16

2

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

1

CV77

2

DIS@

10U_0603_6.3V6M

65mA

1 2

STRAPS

RSVD

RSVD

RSVD

BIOS_ROM_EN

VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS

RSVD

RSVD

AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET

GPIO21 GPIO2

+1.8VGS

LV12

DIS@

BLM15BD121SN1D_0402

GPIO0 PCIE FULL TX OUTPUT SWINGTX_PWRS_ENB

GPIO1TX_DEEMPH_EN PCIE TRANSMITTER DE-EMPHASIS

GPIO2

GPIO8

GPIO9 VGA ENABLEDBIF_VGA DIS

GPIO21

GPIO_22_ROMCSB

GPIO[13:11]ROMIDCFG(2:0)

H2SYNC

GENERICC

HSYNCAUD[1]

VSYNCAUD[0]

H2SYNC GENERICC

PS_1 PS_2 PS_3

CV329

@

0.68U_0402_10V

TX_PWRS_ENB G PIO0

+3VGS

12

12

DIS@

RV90

10K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

VGA Thermal Sensor ADM1032ARMZ

Closed to GPU

0.1U_0402_16V7K

GPU_THERMAL_D+ VGA_SMB_DA2

GPU_THERMAL_D-

Compal Secret Data

Deciphered Date

2

CV89

1 2

CH@

2200P_0402_50V7K

+3VGS

1 2

RV98 4.7K_0 402_5%

CH@

DESCRIPTION OF DEFAULT SETTINGSPIN

Advertises PCIE speed
when compliance test

RESERVED

RESERVED

ENABLE EXTERNAL BIOS ROM

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

GPIO8

+1.8VGS

12

RV237

8.45K_0402_1%

@

12

RV238

1

4.75K_0402_1%

CH@

2

+1.8VGS +1.8VGS

1

CV331

2

CH@

0.68U_0402_10V

Add 12/6 for MLPS

Transmitter Power Saving Enable
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

PCI Express Transmitter De-emphasis Enable

GPIO1TX_DEEMPH_EN

0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

Internal VGA Thermal Sensor

+3VGS
DIS@

RV91
10K_0402_5%

2

61

QV15A

DMN66D0LDW-7_SOT363-6

CV85

12/8 Add external thermal sensor BOM

TH@

354

QV15B

TH@

DMN66D0LDW-7_SOT363-6

RV92 0_0 402_5%@

1 2

RV94 0_0 402_5%@

1 2

+3VGS

CH@

2

1

UV14

1

VDD

SCLK

2

D+

SDATA

3

ALERT#

D-

THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

CH@

Address:100_1101

Compal Electronics, Inc.

Title

ATI_SeymourXT_M2_Main_MSIC

Size Docume nt Number Rev

Custom

Date: Sheet of

12

RV239
10K_0402_5%

@

12

RV240

4.75K_0402_1%

CH@

CH@

8

7

6

5

1

EC_SMB_CK2 <24>

EC_SMB_DA2 <24>

+3VGS

RV96

4.7K_0402_5%

1 2

LA-8241P

1

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

0: 50% swing
1: Full swing

0: disable
1: enable

0: 2.5GT/s
1: 5GT/s

0: disable
1: enable

CV333

@

VGA_SMB_CK2

THM_ALERT#

1

CV90
10P_0402_50V8J

2

@

1

2

0.68U_0402_10V

RECOMMENDED
SETTINGS

X

X

0

0

0

0

X

XXX

0

0

0

11

12

RV241
10K_0402_5%

@

12

RV242

4.75K_0402_1%

CH@

35 56Wednesday, February 01, 201 2

1.0

5

4

3

2

1

+3VGS

RV101
10K_0402_5%

DIS@

2

G

DIS@

RV105

20K_0402_5%

21

1U_0603_10V6K

CV100

@

1 2

13

D

QV21
2N7002K_SOT23-3

DIS@

S

+3VGS

12

1

2

D D

for PX4.0

PX_EN<37>

5.11K_0402_1%

for PX4.0 and PX5.0

C C

Note:

PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON

PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF

PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF

12

RV104

DIS@

@

DV12
RB751V_SOD323

1 2

RV233 0_0402_5%

DIS@

Circuits to support BACO

VGA_PWRGD<17,52>

+3VGS

CV99

@

0.1U_0402_16V7K

1 2

UV16

5

2

P

B

4

Y

1

A

G

@

3

MC74VHC1G08DFT2G SC70 5P

RUNPWROK

RV102

DIS@

1 2

0_0402_5%

for PX5.0

PX_MODE

PX_MODEPXS_PWREN

+3VGS

1

CV96

@

2

0.1U_0402_16V7K

5

UV15

@

2

P

B

4

Y

1

A

G

3

MC74VHC1G08DFT2G SC70 5P

1

CV98

0.1U_0402_16V7K

2

@

PX_MODE <24,52,53>

PX_MODE=1 for Normal Operation

PX

_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

PXS_PWREN<16,52>

RV100

10K_0402_5%

CH@

5

12

34

@

QV18B
DMN66D0LDW-7_SOT363-6

100K_0402_5%

PXS_PWREN

RV109

2

G

+3VALW

DIS@

12

13

D

S

+1.5VS TO +1.5VGS

10U_0603_6.3V6M

CV104

DIS@

B+_BIAS

6

2

1

+1.5V

1

2

RV112

DIS@

20K_0402_5%

RV113

DIS@

1 2

300K_0402_5%

DIS@

QV27A

DMN66D0LDW-7_SOT363-6

UV17

AO4304L_SO8

8
7
6
5

JP9

@

2 1

2MM

DIS@

4

RV115
0_0402_5%

@

1 2

Power Seguence of Thames and Chelsea

+3VGS

B B

A A

+VGA_CORE

+VDDCI

+1.5VGS

+1.0VGS

+1.8VGS

<20ms

PX_MODE

DIS@

100K_0402_5%

100K_0402_5%

RV117

+3VALW

12

DIS@

RV114

PX_MODE#

34

DIS@

QV27B

5

DMN66D0LDW-7_SOT363-6

12

10K_0402_5%

PXS_PWREN#

DIS@

QV25
2N7002_SOT23

+1.5VGS

1
2
3

1

CV107

0.1U_0603_25V7K

2

+5VS+5VS

RV99

@

2

10U_0603_6.3V6M

1

CV105

DIS@

2

DIS@

Switch circuits in BACO desingns for Thanes/Seymour o

12

VDDC_ON#

6

@

QV18A
DMN66D0LDW-7_SOT363-6

1

1.0V_ON#

+1.0VGS

1.0V_ON#

+VGA_CORE

VDDC_ON#

RV249

1 2

QV16

CH@

AO3416_SOT23-3

D

S

13

G

2

QV19

@

AO3416_SOT23-3

D

S

13

G

2

0_0805_5%@

60mil

60mil

QV17

CH@

AO3416_SOT23-3

D

S

13

G

2

QV20

@

AO3416_SOT23-3

D

S

13

G

2

55mA@1.0V, in BACO mode

60mil

RV103

1 2

0_0805_5%CH@

+1.8VS TO +1.8VGS

1

CV106
1U_0603_10V6K

2

PX_MODE#

DIS@

PXS_PWREN#

12

RV111
470_0603_5%

13

D

2

G

QV26

S

2N7002K_SOT23-3

@

RV116 0_0402_5%

1 2

PXS_PWREN

+1.8VS

@

2 1

DMN3030LSS-13_SOP8L-8

8
7

5

DIS@

B+_BIAS

12

330K_0402_5%
RV128

DIS@

RV211

1 2

470K_0402_5%DIS@

13

D

2

QV10

G

S

2N7002H_SOT23-3

DIS@

@

@

+5VALW

DIS@

RV107

20K_0402_5%

2

G

1 2

13

D

S

2N7002H_SOT23-3

+1.8VGS

J92MM

UV35

1
2
36

1

CV320

4

RV212
0_0402_5%

@

10U_0805_10V6K

2

DIS@

1

CV2

0.1U_0603_25V7K

DIS@

2

+3.3VS TO +3.3VGS

+3VS +3VGS

JP8

@

2 1

2MM

3 1

QV22

DIS@

AP2301GN-HF_SOT23-3

2

DIS@

RV108

1K_0402_5%

DIS@

1

CV103

0.1U_0603_25V7K

DIS@

QV24

2

1

CV321
1U_0603_10V6K

2

DIS@

2N7002H_SOT23-3

PXS_PWREN#

10U_0603_6.3V6M

1

CV101

DIS@

2

PXS_PWREN#

QV29

@

RV214

1 2

1U_0603_10V6K

1

CV102

DIS@

2

12

13

D

S

1 2

+BIF_VDDC

RV213
470_0603_5%

@

2

G

0_0402_5%@

12

RV106
470_0603_5%

@

13

D

G

QV23

S

2N7002K_SOT23-3

@

RV110

0_0402_5%@

for PX5.0

1

CV97

22U_0805_6.3V6MDIS@

2

2

60mil

RV234

1 2

0_0603_5%TH @

nly

+VGA_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

ATI_SeymourXT_M2_BACO POWER

LA-8241P

1

of

36 56Wednesday, February 01, 2012

1.0

5

D D

+1.8VGS

+1.0VGS

C C

+1.0VGS

B B

RV201

CH@

2K_0402_1%

A A

(Thames 220mA)

1.0V@220mA DPCD_VDD10)

0.935V@Chelsea

RV121

1 2

0_0402_5%

DIS@

CV117

@

(Thames 220mA)

1.0V@240mA DPEF_VDD10)

0.935V@Chelsea

RV126

1 2

0_0402_5%

DIS@

+1.8VGS

12

RV243

8.45K_0402_1%

CH@

12

RV201
0_0402_5%

TH@

1

2

10U_0603_6.3V6M

+1.8VGS

CV123

@

(Thames 330mA)

1.8V@300mA DPCD_VDD18)

RV119

1 2

0_0402_5%

DIS@

+DPCD_VDD10

+DPCD_VDD10

1

1

CV118

CV119

@

@

2

2

1U_0402_6.3V6K

0.1U_0402_16V7K

(Thames 330mA)

RV124

1 2

0_0402_5%

DIS@

+DPEF_VDD10

+DPEF_VDD10

1

1

CV124

CV125

@

@

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

0.1U_0402_16V7K

PS_0

1

CV335

2

@

0.68U_0402_10V

PS_0 Should be tied to GND on Thames/Seymour

1

1

CV111

@

2

10U_0603_6.3V6M

1.8V@300mA DPEF_VDD18)

CV120

@

1

2

Do not install for Heathrow/Chelsea

1

CV112

CV113

@

@

2

2

1U_0402_6.3V6K

0.1U_0402_16V7K

+DPEF_VDD18

1

1

CV121

CV122

@

@

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

0.1U_0402_16V7K

+DPEF_VDD18

+DPEF_VDD10

Thames/Seymour Only

+DPCD_VDD18

+DPCD_VDD10

+DPCD_VDD18

+DPCD_VDD10

+DPEF_VDD18

+DPEF_VDD10

1

2

20mil

20mil

PS_0

150_0402_1%

20mil

+DPCD_VDD18

20mil

20mil

20mil

RV122150_0402_1% DIS@

12

20mil

20mil

RV127

DIS@

12

AP20
AP21

AP13
AT13

AN17
AP16

AP17
AW14
AW16

AP22

AP23

AP14

AP15

AN19

AP18

AP19
AW20
AW22

AW18

AH34

AM33

AN34

AP39

AR39

AU37

AF34

AG34

AK33

AK34

AF39

AH39

AK39

AM34

AM39

AJ34

AL33

AL34

THAMES XT M2

@

4

UV1H

DP C/D POWER

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP E/F POWER

DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

DPEF_CALR

DP A/B POWER

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

DP PLL POWER

DPAB_VDD18/DPA_PVDD

DP_VSSR/DPA_PVSS

DPAB_VDD18/DPB_PVDD

DP_VSSR/DPB_PVSS

DPCD_VDD18/DPC_PVDD

DP_VSSR/DPC_PVSS

DPCD_VDD18/DPD_PVDD

DP_VSSR/DPD_PVSS

DPEF_VDD18/DPE_PVDD

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPF_PVDD

DP_VSSR/DPF_PVSS

20mil

130mA

AN24
AP24

20mil

110mA

AP31
AP32

AN27
AP27
AP28
AW24
AW26

20mil

AP25
AP26

20mil

AN33
AP33

AN29
AP29
AP30
AW30
AW32

AW28

20mA

AU28
AV27

20mA

AV29
AR28

+DPCD_VDD18

20mA

AU18
AV17

20mA

AV19
AR18

20mA

AM37
AN38

20mA

AL38
AM35

MLPS Bit

PS0:

PS1:

PS2:

PS3:

1.8V@300mA DPAB_VDD18)

+DPAB_VDD18

1

CV109

CV108

2

@

@

1U_0402_6.3V6K

0.1U_0402_16V7K

(1

.0V@220mA DPAB_VDD10)

0.935V@Chelsea

+DPAB_VDD10

1

CV114

@

@

2

1U_0402_6.3V6K

0.1U_0402_16V7K

+DPAB_VDD18

130mA

+DPAB_VDD10

110mA

RV123 150_0402_1%D IS@

1 2

+DPAB_VDD18

10mil

+DPAB_VDD18

10mil

10mil

+DPCD_VDD18

10mil

+DPEF_VDD18

10mil

+DPEF_VDD18

10mil

11001

11000

00000

11000

3

(Thames 330mA)

+DPAB_VDD18

RV118

1

CV110

2

@

10U_0603_6.3V6M

1

CV115

@

2

10U_0603_6.3V6M

AMD recommended setting

R_PU R_PD Cstrap

RV243=8.45K

RV237=NC

RV239=NC

RV241=NC

1 2

1

2

CV116

0_0402_5%

DIS@

(Thames 330mA)

+DPAB_VDD10

RV120

1 2

0_0402_5%

1

2

DIS@

RV201=2K CV335=NC

RV238=4.75K CV329=NC

RV240=4.75K CV331=0.68u

RV242=4.75K CV333=NC

+1.8VGS

+1.0VGS

2

AB39

E39
F34
F39
G33
G34
H31
H34
H39

J31

J34
K31
K34
K39

L31

L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39

W31
W34

Y34
Y39

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33

F7
F9
G2
G6
H9

J27

K14

K7
L11
L17

L22
L24

M17
M22
M24
N16
N18

N2

N21
N23
N26

N6

R15
R17

R2

R20
R22
R24
R27

R6

T11
T13
T16
T18
T21
T23
T26
U15
U17

U2

U20
U22
U24
U27

U6

V11
V16
V18
V21
V23
V26

W2
W6

Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

UV1F

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114

J2

GND#115
GND#116

J6

GND#117

J8

GND#118
GND#119
GND#120
GND#121
GND#122

L2

GND#123
GND#124
GND#125

L6

GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

THAMES XT M2

@

GND

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8

GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60

GND/PX_EN#61

GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

A39
AW1
AW39

MECH#1
MECH#2
MECH#3

12

RV125

4.7K_0402_5%

DIS@

T82 PAD
T83 PAD
T84 PAD

1

PX_EN <36>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ATI_SetmourXT_M2_PWR_GND

LA-8241P

1

37 56Wednesday, February 01, 2012

1.0

5

+1.5VGS

(Thames 1.7)A

D D

C C

+1.8VGS

B B

(Thames 100mA)

+1.0VGS

MCK1608471YZF 0603

1

1

1

+

CV135

CV136

@

220U_B2_2.5VM_R35

+3VGS

(Thames 60mA)

1

1

CV187

CV188

2

2

1U_0402_6.3V6K

DIS@

DIS@

10U_0603_6.3V6M

(Thames 50mA)

LV22

DIS@

1 2

BLM15BD121SN1D_0402

0.935V@Chelsea

LV23

DIS@

1 2

CV137

2

2

2

DIS@

DIS@

10U_0603_6.3V6M

10U_0603_6.3V6M

+1.8VGS +VDDC_CT

(Thames 250mA)

LV19

DIS@

1 2

BLM15BD121SN1D_0402

1

1

CV189

CV190

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

+1.8VGS

(1.8V@75mA SPV18)

1

1

CV200

CV201

2

2

1U_0402_6.3V6K

DIS@

DIS@

10U_0603_6.3V6M

1

1

CV216

CV215

2

2

1U_0402_6.3V6K

DIS@

DIS@

0.1U_0402_16V7K

10U_0603_6.3V6M

VCCSENSE_VGA<52>

VSSSENSE_VGA<52>

4

For DDR3 MVDDQ = 1.5V

1

1

1

CV138

CV140

CV139

2

2

2

DIS@

DIS@

DIS@

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

+1.5VGS

(1.8V@110mA VDD_CT)

1

1

CV170

CV171

2

2

1U_0402_6.3V6K

DIS@

DIS@

10U_0603_6.3V6M

+1.8VGS

(Thames 150mA)

(M97, Broadway and Madison: 1.8V@150mA MPV18)

MCK1608471YZF 0603

0.1U_0402_16V7K

DIS@

1 2

BLM15BD121SN1D_0402

LV21

DIS@

1 2

1

CV202

2

DIS@

LV20

(120mA SPV10)

1

CV217

2

DIS@

VDDCI_SEN<53>

1

CV141

2

1U_0402_6.3V6K

DIS@

1

CV152

2

DIS@

0.1U_0402_16V7K

1

CV172

2

1U_0402_6.3V6K

DIS@

10U_0603_6.3V6M

10_0402_1%

1

1

1

CV143

CV145

CV144

CV142

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

DIS@

1

1

1

CV153

2

DIS@

0.1U_0402_16V7K

1

CV173

2

1U_0402_6.3V6K

DIS@

1

CV193

2

1U_0402_6.3V6K

DIS@

1

1

CV198

CV197

2

2

1U_0402_6.3V6K

DIS@

DIS@

+VDDCI

RV215

DIS@

CV154

DIS@

0.1U_0402_16V7K

CV174

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

12

CV155

2

DIS@

0.1U_0402_16V7K

1

2

1

CV194

2

DIS@

0.1U_0402_16V7K

1

CV199

2

DIS@

10mil
20mil

+VGA_CORE

VGA_CORE_SEN

VSSSENSE_VGA

2

0.1U_0402_16V7K

12

RV202
10_0402_1%

DIS@

VDDCI_SEN

12

10_0402_1%DI S@

CV156

DIS@

1

2

1

2

20mil

+VDDR4

20mil

+MPV18

+SPV18

+SPV10

RV204

20mil

10mil

10mil

10mil

AD11

AG10

AF26

AF27
AG26
AG27

AF23

AF24
AG23
AG24

AF13

AF15
AG13
AG15

AD12

AF11

AF12
AG11

AM10

AN10

AF28

AG28

AH29

AC7

AF7

AJ7

AK8

AL9
G11
G14
G17
G20
G23
G26
G29
H10

K11

K13

L12

L16

L21

L23

L26

M11
N11

R11
U11

U7

Y11

M20
M21

V12
U12

H7
H8

AN9

UV1E

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15

J7

VDDR1#16

J9

VDDR1#17
VDDR1#18
VDDR1#19

K8

VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25

L7

VDDR1#26
VDDR1#27
VDDR1#28

P7

VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33

Y7

VDDR1#34

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

NC_VDDRHA
NC_VSSRHA

NC_VDDRHB
NC_VSSRHB

MPV18#1
MPV18#2

SPV18

SPV10

SPVSS

FB_VDDC

FB_VDDCI

FB_GND

THAMES XT M2

@

MEM I/O

LEVEL
TRANSLATION

I/O

PLL

VOLTAGE
SENESE

3

PCIE

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

PCIE_VDDR/PCIE_PVDD

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8

PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

VDDC#1

CORE

VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8

VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15

POWER

VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32

VDDC/BIF_VDDC#33

VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41

VDDC/BIF_VDDC#42

VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
VDDCI#15

ISOLATED

VDDCI#16

CORE I/O

VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

(Thames 440mA)

(1.8V@504mA PCIE_VDDR)

+PCIE_VDDR

1

1

CV126

CV127

2

2

DIS@

DIS@

0.1U_0402_16V7K

40mil

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

0.1U_0402_16V7K

RV244

1 2

0_0402_5%TH @

RV245

1 2

1

CV157

2

DIS@

1

CV175

2

DIS@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

55mA

CV195

1U_0402_6.3V6K

DIS@

1

CV203

2

DIS@

0_0402_5%@

1

1

CV158

CV159

2

2

1U_0402_6.3V6K

DIS@

DIS@

1

1

CV177

CV176

2

2

1U_0402_6.3V6K

DIS@

DIS@

+BIF_VDDC

1

1

CV196

2

2

1U_0402_6.3V6K

DIS@

1

1

CV204

CV205

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

+PCIE_PVDD

1U_0402_6.3V6K

1U_0402_6.3V6K

(GDDR3/DDR3 1.12V@4A VDDCI)

(GDDR5 1.12V@16A VDDCI)

1

1

1

CV130

CV129

CV128

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

10U_0603_6.3V6M

Add 12/8

+PCIE_VDDR

+BIF_VDDC

1

1

1

CV147

CV146

CV148

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

1

1

1

CV161

CV160

CV162

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

CV178

1U_0402_6.3V6K

DIS@

For non-BACO designs, connect BIF_VDDC to VDDC.
For BACO designs - see BACO reference schematics

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

1

1

1

CV180

CV179

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

+VGA_CORE

1

1

CV192

CV191

2

2

DIS@

DIS@

22U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

CV206

CV208

CV207

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

2

+1.8VGS

LV17

DIS@

12

MBK1608121YZF_0603

1

CV131

2

DIS@

(1.8V@40mA PCIE_PVDD)

1

CV132

2

1U_0402_6.3V6K

DIS@

0.1U_0402_16V7K

+1.0VGS

(Thames 1.1A)

1

1

1

CV150

CV151

CV149

2

DIS@

2

2

1U_0402_6.3V6K

DIS@

DIS@

10U_0603_6.3V6M

(1.0V@1920mA PCIE_VDDC)

(Chelsea)

(0.935V@2.5A PCIE_VDDC)

(Thames 20.5A)

1

1

CV163

2

DIS@

1

CV181

2

DIS@

1

CV209

2

1U_0402_6.3V6K

DIS@

1

1

CV164

CV166

CV165

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

1

1

1

CV182

CV183

CV184

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

1

1

CV211

CV210

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

1

CV133

2

DIS@

4A

1

CV212

2

DIS@

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CV167

2

1U_0402_6.3V6K

DIS@

+VGA_CORE

1

CV185

2

1U_0402_6.3V6K

DIS@

10U_0603_6.3V6M

1

CV325

2

DIS@

40mA

DIS@

MBK1608121YZF_0603

1

CV134

2

DIS@

+VGA_CORE

1

1

CV168

CV169

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

1

CV186

2

1U_0402_6.3V6K

DIS@

+VDDCI

1

1

CV214

CV213

2

2

DIS@

DIS@

22U_0603_6.3V6M

1

1

CV322

CV324

2

2

DIS@

DIS@

10U_0603_6.3V6M

10U_0603_6.3V6M

LV18

1

+

DIS@

2

1

CV323

2

DIS@

10U_0603_6.3V6M

+1.8VGS

12

330U_D2_2VM_R6M~D

CV327

LV25

1 2

BLM15BD121SN1D_0402

LV26

1 2

BLM15BD121SN1D_0402

@

@

+VGA_CORE

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

ATI_SeymourXT_M2_Power

LA-8241P

1

of

38 56Wednesday, February 01, 2012

1.0

5

UV1C

DDR2
GDDR3/GDDR5

AG12

AH12

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13

J13
H11
G10

G8

K9

K10

G9

A8

C8

E8
A6

C6

E6
A5

L18

L20

L27
N12

M12
M27

DDR3

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

MVREFDA
MVREFSA

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11

D D

C C

+1.5VGS

RV129 240_0402_1%D IS@

1 2

RV130 240_0402_1%SE@

1 2

RV131 240_0402_1%D IS@

1 2

RV132 240_0402_1%SE@

1 2

RV134 240_0402_1%D IS@

1 2

RV135 240_0402_1%D IS@

1 2

RV206 120_0402_5%C H@

1 2

RV205 120_0402_5%C H@

1 2

MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

+VDD_MEM15_REFDA
+VDD_MEM15_REFSA

DDR2
GDDR5/GDDR3
DDR3

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9

ADBIA0/ODTA0
ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B

MAA0_8
MAA1_8

GDDR5

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

A32
C32
D23
E22
C14
A14
E10
D9

C34
D29
D25
E20
E16
E12
J10
D7

A34
E30
E26
C20
C16
C12
J11
F8

J21
G19

H27
G27

J14
H14

K23
K19

K20
K17

K24
K27

M13
K16

K21
J20

K26
L15

H23
J19

MAA1_2/MAA_10
MAA1_3/MAA_11

MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0

MAA1_7/MAA_A15_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

GDDR5/DDR2/GDDR3

MEMORY INTERFACE A

EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0
DDBIA0_1/QSA_1B/WDQSA_1
DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

ODTA0
ODTA1

CLKA0
CLKA0#

CLKA1
CLKA1#

RASA0#
RASA1#

CASA0#
CASA1#

CSA0#_0

CSA1#_0

CKEA0
CKEA1

WEA0#
WEA1#

MAA13
MAA14

4

MDA[0..63]<40> MDB[0..63]<41>

ODTA0 <40>
ODTA1 <40>

CLKA0 <40>
CLKA0# <40>

CLKA1 <40>
CLKA1# <40>

RASA0# <40>
RASA1# <40>

CASA0# <40>
CASA1# <40>

CSA0#_0 <40>

CSA1#_0 <40>

CKEA0 <40>
CKEA1 <40>

WEA0# <40>
WEA1# <40>

MAA13 <40>
MAA14 <40> MAB14 <41>

MDA[0..63] MDB[0..63]

MAA[12..0] MAB[12..0]

A_BA[2..0] B_BA[2..0]

DQMA#[7..0] <40>

QSA[7..0] <40>

QSA#[7..0] <40>

MAA[12..0] <40>

A_BA[2..0] <40>

3

+VDD_MEM15_REFDB
+VDD_MEM15_REFSB

DIS@

1 2

5.11K_0402_1%

TESTEN

RV133

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

AA12

AD28

AK10
AL10

2

C5
C3

E3
E1
F1
F3

F5
G4
H5
H6

J4

K6

K5

L4
M6
M1
M3
M5
N4

P6

P5
R4

T6

T1
U4

V6

V1

V3

Y6

Y1

Y3

Y5

AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

Y12

UV1D

DDR2
GDDR3/GDDR5
DDR3

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

MVREFDB
MVREFSB

TESTEN

CLKTESTA
CLKTESTB

DDR2
GDDR5/GDDR3
DDR3

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8

MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12

MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

GDDR5/DDR2/GDDR3

EDCB0_0/QSB_0/RDQSB_0

MEMORY INTERFACE B

EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

ADBIB0/ODTB0
ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B
RASB1B

CASB0B
CASB1B

CSB0B_0
CSB0B_1

CSB1B_0
CSB1B_1

CKEB0
CKEB1

WEB0B
WEB1B

MAB0_8
MAB1_8

DRAM_RST

GDDR5

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

H3
H1
T3
T5
AE4
AF5
AK6
AK5

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

T7
W7

L9
L8

AD8
AD7

T10
Y10

W10
AA10

P10
L10

AD10
AC10

U10
AA11

N10
AB11

T8
W8

AH11

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

ODTB0
ODTB1

CLKB0
CLKB0#

CLKB1
CLKB1#

RASB0#
RASB1#

CASB0#
CASB1#

CSB0#_0

CSB1#_0

CKEB0
CKEB1

WEB0#
WEB1#

MAB13
MAB14

DRAM_RST#_R

1

ODTB0 <41>
ODTB1 <41>

CLKB0 <41>
CLKB0# <41>

CLKB1 <41>
CLKB1# <41>

RASB0# <41>
RASB1# <41>

CASB0# <41>
CASB1# <41>

CSB0#_0 <41>

CSB1#_0 <41>

CKEB0 <41>
CKEB1 <41>

WEB0# <41>
WEB1# <41>

MAB13 <41>

DQMB#[7..0] <41>

QSB[7..0] <41>

QSB#[7..0] <41>

MAB[12..0] <41>

B_BA[2..0] <41>

Co-lay Thames/Seymour/Chelsea

RV129

B B

RV130

RV131

RV132

RV134

RV135

RV206

40.2_0402_1%

100_0402_1%

A A

Thames M2@Seymour M2@Chelsea M2

POP

@

PO

POP

POP

@

@

+1.5VGS +1.5VGS

12

RV139

DIS@

+VDD_MEM15_REFDA

12

12

RV146

DIS@

P

CV220

0.1U_0402_16V7K

DIS@

5

THAMES XT M2

@

POP

@

POP

@

@

@

@

40.2_0402_1%

100_0402_1%

RV140

DIS@

RV147

DIS@

POP

POPRV205

12

12

@

@

@

@

@

@

+VDD_MEM15_REFSA

12

CV221

0.1U_0402_16V7K

DIS@

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

+1.5VGS

12

RV138

4.7K_0402_5%

@

RV143

DRAM_RST#<40,41>

4

1 2

51.1_0402_1%

DIS@

DIS@

CV222

120P_0402_50V9

12

12

@

CV218

0.1U_0402_16V7K

12

@

RV136

51.1_0402_1%

+1.5VGS +1.5VGS

12

RV141

DRAM_RST#_R

RV144

1 2

10_0402_1%

DIS@

DIS@

RV145

4.99K_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

40.2_0402_1%

DIS@

12

RV148

100_0402_1%

DIS@

2012/01/17 2013/01/16

Compal Secret Data

12

@

CV219

0.1U_0402_16V7K

12

@

RV137

51.1_0402_1%

+VDD_MEM15_REFDB

12

CV223

0.1U_0402_16V7K

DIS@

Deciphered Date

2

THAMES XT M2

@

route 50ohms single-ended/100ohms diff
and keep short
Debug only, for clock observation, if not needed, DNI
5mil 5mil

12

RV142

40.2_0402_1%

DIS@

+VDD_MEM15_REFSB

12

12

CV224

RV149

100_0402_1%

DIS@

0.1U_0402_16V7K

DIS@

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ATI_SeymourXT_M2_MEM IF

LA-8241P

1

39 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

CHANNEL A: 256MB/512MB DDR3

VREFC_A1
VREFD_Q1

D D

MDA[0..63]<39>

MAA[14..0]<39>

DQMA#[7..0]<39>

QSA[7..0]<39>

QSA#[7..0]<39>

C C

CLKA0

RV154 56_0402_1%

CLKA0#

RV155 56_0402_1%

B B

CLKA1

1 2

RV164 56_0402_1%

CLKA1#

1 2

RV165 56_0402_1%

DIS@

1 2

DIS@

1 2

DIS@

DIS@

MDA[0..63]

MAA[14..0]

DQMA#[7..0]

QSA[7..0]

QSA#[7..0]

12

CV225

0.01U_0402_16V7K

DIS@

12

CV234

0.01U_0402_16V7K

DIS@

A_BA0<39>
A_BA1<39>
A_BA2<39>

CLKA0<39>
CLKA0#<39>
CKEA0<39>

ODTA0<39>
CSA0#_0<39>
RASA0#<39>
CASA0#<39>
WEA0#<39>

DRAM_RST#<39,41>

RV150

240_0402_1%

DIS@

QSA3
QSA0

DQMA#3
DQMA#0

QSA#3
QSA#0

UV18

M8

VREFCA

H1

VREFDQ

MAA0

N3

A0

MAA1

P7

A1

MAA2

P3

A2

MAA3

N2

A3

MAA4

P8

A4

MAA5

P2

A5

MAA6

R8

A6

MAA7

R2

A7

MAA8

T8

A8

MAA9

R3

A9

MAA10

L7

A10/AP

MAA11

R7

A11

MAA12

N7

A12

MAA13

T3

A13

MAA14

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

12

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4W1G1646G-BC11

+1.5VGS +1.5VGS+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1. 5VGS +1.5VGS

12

RV156

4.99K_0402_1%

DIS@

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

12

DIS@

12

CV226

RV166

4.99K_0402_1%

DIS@

MDA29

E3

DQL0

MDA27

F7

DQL1

MDA30

F2

DQL2

MDA26

F8

DQL3

MDA28

H3

DQL4

MDA24

H8

DQL5

MDA31

G2

DQL6

MDA25

H7

DQL7

MDA0

D7

DQU0

MDA5

C3

DQU1

MDA1

C8

DQU2

MDA6

C2

DQU3

MDA3

A7

DQU4

MDA4

A2

DQU5

MDA2

B8

DQU6

MDA7

A3

DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VREFD_Q1 VREFD_Q2

0.1U_0402_16V7K

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

X76@

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

4.99K_0402_1%

4.99K_0402_1%

+1.5VGS

RV157

DIS@

RV167

DIS@

+1.5VGS

12

12

VREFC_A2
VREFD_Q2

A_BA0 A_BA0 A_BA0
A_BA1 A_BA1 A_BA1
A_BA2 A_BA2 A_BA2

CLKA0
CLKA0#
CKEA0 CKEA1

ODTA0 ODTA1
CSA0#_0 CSA1#_0
RASA0# RASA1#
CASA0# CASA1#
WEA0# WEA1#

QSA2 QSA4
QSA1

DQMA#2 DQMA#4
DQMA#1

QSA#2 QSA#4
QSA#1

DRAM_RST# DRAM_RST# DRAM_RST#

12

RV151

240_0402_1%

DIS@

VREFC_A1 VREFC_A2

0.1U_0402_16V7K

12

CV227

DIS@

UV19

M8

VREFCA

H1

VREFDQ

MAA0 MAA0 MAA0

N3

A0

MAA1 MAA1 MAA1

P7

A1

MAA2 MAA2 MAA2

P3

A2

MAA3 MAA3 MAA3

N2

A3

MAA4 MAA4 MAA4

P8

A4

MAA5 MAA5 MAA5

P2

A5

MAA6 MAA6 MAA6

R8

A6

MAA7 MAA7 MAA7

R2

A7

MAA8 MAA8 MAA8

T8

A8

MAA9 MAA9 MAA9

R3

A9

MAA10 MAA10 MAA10

L7

A10/AP

MAA11 MAA11 MAA11

R7

A11

MAA12 MAA12 MAA12

N7

A12

MAA13 MAA13 MAA13

T3

A13

MAA14 MAA14 MAA14

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4W1G1646G-BC11

12

RV158

4.99K_0402_1%

DIS@

12

RV168

4.99K_0402_1%

DIS@

DIS@

CV228

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

12

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

X76@

0.1U_0402_16V7K

MDA17

E3

MDA23

F7

MDA16

F2

MDA19

F8

MDA18

H3

MDA21

H8

MDA20

G2

MDA22

H7

MDA15

D7

MDA10

C3

MDA14

C8

MDA11

C2

MDA13

A7

MDA9

A2

MDA12

B8

MDA8

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

4.99K_0402_1%

4.99K_0402_1%

DIS@

RV159

DIS@

RV169

+1.5VGS

+1.5VGS

12

12

240_0402_1%

CV229

DIS@

VREFC_A3
VREFD_Q3

CLKA1<39>
CLKA1#<39>
CKEA1<39>

ODTA1<39>
CSA1#_0<39>
RASA1#<39>
CASA1#<39>
WEA1#<39>

QSA5

DQMA#5

QSA#5

12

RV152

DIS@

0.1U_0402_16V7K

12

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3

R7
N7
T3
T7
M7

M2
N8
M3

K7
K9

K1

K3

F3
C7

E7
D3

G3
B7

T2

RV160

4.99K_0402_1%

DIS@

RV170

4.99K_0402_1%

DIS@

UV20

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

L7

A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

J7

CK
CK
CKE/CKE0

ODT/ODT0

L2

CS/CS0

J3

RAS
CAS

L3

WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4W1G1646G-BC11

12

12

DIS@

CV230

12

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

X76@

VREFC_A3

0.1U_0402_16V7K

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

RV161

4.99K_0402_1%

DIS@

RV171

4.99K_0402_1%

DIS@

MDA38
MDA36
MDA39
MDA34
MDA35
MDA33
MDA37
MDA32

MDA42
MDA44
MDA40
MDA46
MDA43
MDA45
MDA41
MDA47

12

12

+1.5VGS

+1.5VGS

240_0402_1%

DIS@

CV231

RV153

DIS@

VREFD_Q3

0.1U_0402_16V7K

12

VREFC_A4
VREFD_Q4

CLKA1
CLKA1#

QSA6
QSA7

DQMA#6
DQMA#7

QSA#6
QSA#7

12

M8

H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

M7

M2

N8

M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3

B7

T2

L8

J1
L1
J9
L9

RV162

4.99K_0402_1%

DIS@

RV172

4.99K_0402_1%

DIS@

UV21

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3

K4W1G1646G-BC11

12

12

DIS@

CV232

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VREFC_A4

12

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

X76@

0.1U_0402_16V7K

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

RV163

4.99K_0402_1%

DIS@

RV173

4.99K_0402_1%

DIS@

MDA55
MDA51
MDA48
MDA52
MDA50
MDA53
MDA49
MDA54

MDA60
MDA57
MDA63
MDA56
MDA61
MDA59
MDA62
MDA58

+1.5VGS

+1.5VGS

12

12

DIS@

CV233

VREFD_Q4

12

0.1U_0402_16V7K

+1.5VGS

1

1

1

CV235

CV236

2

2

DIS@

DIS@

0.1U_0402_16V7K

A A

0.1U_0402_16V7K

1

1

CV238

CV237

2

2

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

5

1

1

CV239

2

DIS@

0.1U_0402_16V7K

1

CV240

CV241

2

2

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

CV242

2

DIS@

0.1U_0402_16V7K

CV244

CV243

2

DIS@

0.1U_0402_16V7K

CV245

2

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

1

CV247

CV246

2

2

2

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

4

+1.5VGS

CV248

DIS@

10U_0603_6.3V6M

+1.5VGS +1.5VGS

1

1

CV249

2

2

DIS@

10U_0603_6.3V6M

1

1

CV251

CV250

2

2

DIS@

DIS@

10U_0603_6.3V6M

10U_0603_6.3V6M

3

1

CV252

2

1U_0402_6.3V6K

DIS@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

1

CV253

2

1U_0402_6.3V6K

DIS@

1

CV254

CV255

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

1

1

CV257

CV256

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

2012/01/17 2013/01/16

1

1

CV259

CV258

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

Compal Secret Data

DIS@

Deciphered Date

1U_0402_6.3V6K

DIS@

2

1

1

1

1

CV260

CV261

2

2

1U_0402_6.3V6K

DIS@

DIS@

1

CV262

CV263

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

1

1

CV265

CV264

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

Title

Size Document Number Rev

C 1.0

Date: Sheet of

1

1

CV266

CV267

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

1

CV268

CV269

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

Compal Electronics, Inc.

ATI_SeymourXT_M2_VRAM_A

LA-8241P

1

1

1

CV271

CV270

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

40 56Wednesday, February 01, 2012

5

4

3

2

1

CHANNEL B: 256MB/512MB DDR3

VREFC_A1_B
VREFD_Q1_B

D D

MDB[0..63]<39>

MAB[14..0]<39>

DQMB#[7..0]<39>

QSB[7..0]<39>

QSB#[7..0]<39>

C C

CLKB0

1 2

RV174 56_0402_1%

CLKB0#

1 2

RV175 56_0402_1%

CLKB1

1 2

RV180 56_0402_1%

CLKB1#

1 2

RV181 56_0402_1%

DIS@

DIS@

DIS@

DIS@

MDB[0..63]

MAB[14..0]

DQMB#[7..0]

QSB[7..0]

QSB#[7..0]

12

12

CV272

0.01U_0402_16V7K

DIS@

CV273

0.01U_0402_16V7K

DIS@

B_BA0<39>
B_BA1<39>
B_BA2<39>

CLKB0<39>
CLKB0#<39>
CKEB0<39>

ODTB0<39>
CSB0#_0<39>
RASB0#<39>
CASB0#<39>
WEB0#<39>

QSB3 QSB2 QSB4
QSB0 QSB1

DQMB#3 DQMB#2 DQMB#4
DQMB#0 DQMB#1

QSB#3 QSB#2 QSB#4
QSB#0 QSB#1

DRAM_RST#<39,40>

12

RV176

240_0402_1%

DIS@

UV22

M8

VREFCA

H1

VREFDQ

MAB0 MAB0 MAB0 MAB0

N3

A0

MAB1 MAB1 MAB1 MAB1

P7

A1

MAB2 MAB2 MAB2 MAB2

P3

A2

MAB3 MAB3 MAB3 MAB3

N2

A3

MAB4 MAB4 MAB4 MAB4

P8

A4

MAB5 MAB5 MAB5 MAB5

P2

A5

MAB6 MAB6 MAB6 MAB6

R8

A6

MAB7 MAB7 MAB7 MAB7

R2

A7

MAB8 MAB8 MAB8 MAB8

T8

A8

MAB9 MAB9 MAB9 MAB9

R3

A9

MAB10 MAB10 MAB10 MAB10

L7

A10/AP

MAB11 MAB11 MAB11 MAB11

R7

A11

MAB12 MAB12 MAB12 MAB12

N7

A12

MAB13 MAB13 MAB13 MAB13

T3

A13

MAB14 MAB14 MAB14 MAB14

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4W1G1646G-BC11

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

X76@

MDB29

E3

MDB26

F7

MDB30

F2

MDB27

F8

MDB31

H3

MDB25

H8

MDB28

G2

MDB24

H7

MDB0

D7

MDB4

C3

MDB1

C8

MDB6

C2

MDB3

A7

MDB7

A2

MDB2

B8

MDB5

A3

+1.5VGS

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240_0402_1%

RV177

DIS@

VREFC_A2_B
VREFD_Q2_B

12

UV23

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

B_BA0 B_BA0 B_BA0
B_BA1 B_BA1 B_BA1
B_BA2 B_BA2 B_BA2

CLKB0
CLKB0#
CKEB0 CKEB1

ODTB0 ODTB1
CSB0#_0 CSB1#_0
RASB0# RASB1#
CASB0# CASB1#
WEB0# WEB1#

DRAM_RST# DRAM_RST# DRAM_RST#

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4W1G1646G-BC11

96-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

MDB16

E3

MDB19

F7

MDB20

F2

MDB22

F8

MDB17

H3

MDB21

H8

MDB18

G2

MDB23

H7

MDB15

D7

MDB10

C3

MDB14

C8

MDB11

C2

MDB12

A7

MDB9

A2

MDB13

B8

MDB8

A3

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

X76@

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

RV178

240_0402_1%

DIS@

CLKB1<39>
CLKB1#<39>
CKEB1<39>

ODTB1<39>
CSB1#_0<39>
RASB1#<39>
CASB1#<39>
WEB1#<39>

VREFC_A3_B
VREFD_Q3_B

QSB5

DQMB#5

QSB#5

12

UV24

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4W1G1646G-BC11

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

MDB33

E3

MDB37

F7

MDB35

F2

MDB39

F8

MDB32

H3

MDB36

H8

MDB34

G2

MDB38

H7

MDB44

D7

MDB41

C3

MDB47

C8

MDB43

C2

MDB45

A7

MDB40

A2

MDB46

B8

MDB42

A3

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

X76@

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

RV179

240_0402_1%

DIS@

VREFC_A4_B
VREFD_Q4_B

CLKB1
CLKB1#

QSB6
QSB7

DQMB#6
DQMB#7

QSB#6
QSB#7

12

UV25

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4W1G1646G-BC11

96-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

MDB55

E3

MDB50

F7

MDB54

F2

MDB51

F8

MDB53

H3

MDB49

H8

MDB52

G2

MDB48

H7

MDB56

D7

MDB59

C3

MDB63

C8

MDB62

C2

MDB57

A7

MDB61

A2

MDB58

B8

MDB60

A3

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

X76@

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

B B

+1.5VGS

1

CV282

A A

2

DIS@

0.1U_0402_16V7K

1

1

CV284

CV283

2

2

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

5

1

1

1

CV286

CV285

2

2

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

1

CV287

CV288

2

2

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

+1.5VGS +1.5VGS +1.5VGS +1. 5VGS +1.5VGS +1.5VGS +1. 5VGS +1.5VGS

4.99K_0402_1%

4.99K_0402_1%

1

CV289

2

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

12

RV182

DIS@

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

VREFD_Q1_B VREFD_Q2_B

12

1

RV190

DIS@

CV274

2

DIS@

0.1U_0402_16V7K

1

1

CV290

CV291

2

2

DIS@

DIS@

0.1U_0402_16V7K

1

1

CV293

CV292

2

2

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

4

RV183

4.99K_0402_1%

DIS@

RV191

4.99K_0402_1%

DIS@

1

CV294

2

DIS@

0.1U_0402_16V7K

12

12

VREFC_A1_B

1

CV275

2

DIS@

0.1U_0402_16V7K

RV184

4.99K_0402_1%

DIS@

RV192

4.99K_0402_1%

DIS@

+1.5VGS

1

CV295

2

DIS@

10U_0603_6.3V6M

12

VREFC_A2_B

12

1

CV296

2

DIS@

10U_0603_6.3V6M

1

CV276

2

DIS@

0.1U_0402_16V7K

1

1

CV298

CV297

2

2

DIS@

DIS@

10U_0603_6.3V6M

10U_0603_6.3V6M

RV185

4.99K_0402_1%

DIS@

RV193

4.99K_0402_1%

DIS@

3

12

12

1

CV277

2

DIS@

0.1U_0402_16V7K

+1.5VGS +1.5VGS

1

1

CV300

CV299

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

RV186

4.99K_0402_1%

DIS@

VREFC_A3_B

12

1

RV194

4.99K_0402_1%

DIS@

1

CV301

2

1U_0402_6.3V6K

DIS@

CV278

2

DIS@

0.1U_0402_16V7K

1

CV303

2

1U_0402_6.3V6K

DIS@

1

CV304

2

1U_0402_6.3V6K

DIS@

Compal Secret Data

1

CV302

2

1U_0402_6.3V6K

DIS@

2012/01/17 2013/01/16

RV187

4.99K_0402_1%

DIS@

RV195

4.99K_0402_1%

DIS@

1

CV305

2

1U_0402_6.3V6K

DIS@

Deciphered Date

12

VREFD_Q3_B

12

1

CV279

2

DIS@

0.1U_0402_16V7K

1

1

CV306

2

1U_0402_6.3V6K

DIS@

1

CV307

CV308

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

2

RV188

4.99K_0402_1%

DIS@

RV196

4.99K_0402_1%

DIS@

1

CV309

2

1U_0402_6.3V6K

DIS@

12

12

0.1U_0402_16V7K

1

1

CV311

CV310

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

12

RV189

4.99K_0402_1%

DIS@

VREFC_A4_B

1

CV280

2

DIS@

Date: Sheet of

RV197

4.99K_0402_1%

DIS@

1

1

CV312

CV313

2

2

1U_0402_6.3V6K

Title

Size Document Number Rev

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

Compal Electronics, Inc.

ATI_SeymourXT_M2_VRAM_B

C 1.0

VREFD_Q4_B

12

1

CV281

2

DIS@

0.1U_0402_16V7K

1

1

CV314

CV315

2

2

1U_0402_6.3V6K

DIS@

DIS@

1

CV316

2

1U_0402_6.3V6K

DIS@

LA-8241P

1

1

1

CV317

CV318

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

41 56Wednesday, February 01, 2012

5

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Request

Request

Page# Title

Item

Item Issue Description

Page#Page#

ItemItem

1

D D

C C

08,11,12 DIMM

2

18,19 PCH VCCDMI, V_PROC_IO change to +VCCP from +1.05VS

3

09,10 CPU

10 CPU

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Title

TitleTitle

Date

DateDate

11/07/28

11/07/28

11/07/28

11/07/28

RequestRequest
Owner

Owner

OwnerOwner

COMPAL

COMPAL

COMPAL

COMPAL

4

Issue DescriptionDate

Issue DescriptionIssue Description

The M3 traces are routed to the Sandy Bridge Processor reserved pins for DDR3
VREF

remove decoupling cap for +VCC_CORE, +VCCP, +VCC_GFXCORE_AXG, owner change to
PWR

VCCSA_SELECT[0:1] which should be connected to VID[1:0] of the System Agent
(SA) VR controller.

3

Page 1

Page 1

Page 1Page 1

Intel CHKLST Rev1.5 required

Intel CHKLST Rev1.5 required

Intel CHKLST Rev1.5 required

Intel CHKLST Rev1.5 required

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

Rev.Page#

Rev.Rev.

0.1

0.1

0.1

0.1

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

HW-PIR

1

42 56Wednesday, February 01, 2012

1.0

A

PL901

ADPIN

PJPDC9

@

1

1

2

2

3

3

4

4

5

5

GND
GND

6
7

1 1

ACES_50299-00501-003

12

PC901

PSID

SMB3025500YA_2P

12

PC902

1000P_0402_50V7K

PL902

BLM18BD102SN1D_0603~D

1 2

100P_0402_50V8J

12

VIN

12

12

PC903

1000P_0402_50V7K

BATT++BATT+

PL900

SMB3025500YA_2P

BATT+

1 2

12

12

PC905

100P_0402_50V8J

PBATT9

GND
GND

PC906

0.01U_0402_25V7K

@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10
11

2 2

ALLTO_C144FE-109A7-L

PBATT1 battery connector (Follow E3)

3 3

SMART

SMART

SMARTSMART
Battery:

Battery:

Battery:Battery:

01.BATT1+

01.BATT1+

01.BATT1+01.BATT1+

02.BATT2+

02.BATT2+

02.BATT2+02.BATT2+

03.CLK_SMB

03.CLK_SMB

03.CLK_SMB03.CLK_SMB

04.DAT_SMB

04.DAT_SMB

04.DAT_SMB04.DAT_SMB

05.BATT_PRS

05.BATT_PRS

05.BATT_PRS05.BATT_PRS

06.SYS_PRES

06.SYS_PRES

06.SYS_PRES06.SYS_PRES

07.BAT_ALERT

07.BAT_ALERT

07.BAT_ALERT07.BAT_ALERT

08.GND1

08.GND1

08.GND108.GND1

09.GND2

09.GND2

09.GND209.GND2

4 4

+3VLP

CLK_SMB
DAT_SMB
BATT_PRS
SYS_PRES

@930

BATT++

12

BATT+

51_ON#<25>

PR924

0_0603_5%

1 2

A

12

PC907

PC900

1000P_0402_50V7K

100P_0402_50V8J

@930

@930

+CHGRTC

1

2

PD907

LL4148_LL34-2

PR922

@930

100K_0402_1%

1 2

PR923

22K_0402_1%

@930

PD904

@

PESD24VS2UT_SOT23-3

3

12

12

12

G920AT24U_SOT89-3

3

12

PC913

4.7U_0603_6.3V6K~D

PR919

1 2

N1

PC911

0.22U_0603_25V7K

OUT

1

PD903

2

3

PESD24VS2UT_SOT23-3

100_0402_5%

1 2

0_0402_5%

PQ905

@930

TP0610K-T1-E3_SOT23- 3

@930

VS_N_002

@930

PU900

2

IN

GND

1

@

PR910

PR914

100_0402_5%

1 2

PR913

100_0402_5%

1 2

2

@930

13

12

PC914

B

PC904

Erp lot6 Circuit

100P_0402_50V8J

ACIN <15,24,35,44>

PR928

200K_0402_1%

PC916

0.1U_0402_25V6

2

-

SUYIN_060003FA002G202NL

PR911

10K_0402_1%

1 2

EC_SMB_CK1 <24 ,44>

EC_SMB_DA1 <24 ,44>

VIN

PD906

@930

LL4148_LL34-2

1 2

VS_N_001

12

@930

PR925

200_0805_5%

B

12

PR921
68_1206_5%

PR920

@930

68_1206_5%

12

PC912

0.1U_0402_25V6

@930

1 2

1U_0603_25V6K

C

PR901
0_0402_5%@

1 2

D

2

G

PC910

.1U_0402_16V7K

1 3

2

B

E

PR908

22K_0402_1%

1 2

VSB_N_003

13

D

PQ903
2N7002KW_S OT323-3

S

@

D

PQ906

S

2N7002KW_SOT323-3

65W 90W 130W

High

VIN

12

PR929

1M_0402_1%

12

2

12

1 2

61

PR930

PQ907A

1M_0402_1%

1 2

SSM6N7002FU-2N_SOT363-6

JRTC9

@

1

+

PR931

3

1.2K_1206_5%~D

5

PQ907B

4

@

PD905

RB751V-40_SOD323-2

1 2

2

1

SSM6N7002FU-2N_SOT363-6

3

@

PD902
SM24_SOT23

+RTCBATT

+3VLP

PR904

1 2

100K_0402_1%

PSID-1

PR900

15K_0402_1%

1 2

B+

+5VALW

BATT_TEMP <24,44>

+3VALW

@930

VS

VCIN1_PH<24>

PR917

499K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/01/17 2013/01/16

PR909

100K_0402_1%

1 2

PC915

@

.1U_0402_16V7K

1 2

1 2

POK<45>

ADP_I <24,44>

PR915
332K_0402_1%

1 2

1 2

Compal Secret Data

Deciphered Date

PR912
0_0402_5%

D

PQ904

S

2N7002KW_SOT323-3

C

VSB_N_002

12

PR918

90.9K_0402_1%

1 2
13

2

G

65W/90W # <24>

65W/90W#

130W/90W#

D

+3VALW+5VALW

2

3

PD901

BAV99W-7-F_SOT-323-3~D

PR903

33_0402_5%

S

PSID-3

1 2

PQ901
FDV301N_NL_SOT23-3~D

G

2

PSID-2

C

PQ900
MMST3904-7-F_SOT3 23~D

3 1

12

PR907

100K_0402_1%

12

PC908

VSB_N_001

0.22U_0603_25V7K

1

+5VALW

12

2

TP0610K-T1-E3_SOT23- 3

PR905

10K_0402_1%

PR906

1 2

10K_0402_1%

PQ902

2.2K_0402_5%

PR902

1 2

+5VALW

3

PD900

@

DA204U_SOT323~D

PSID-5

13

12

PC909

PH901 under CPU botten side :

CPU thermal protection at 90 degree C

PR926

@

6.81K_0402_1%

1 2
13

2

G

Low

Low

130W/90W # <24>

High

Title

Size D ocument Number Rev

Date: Sheet of

VCIN0_PH<24 >

100K_0402_1%_TSM0B104F4251RZ

PWR-DCIN / BATT CONN / OTP

LA-8241P

+3VALW

PR927

13K_0402_1%

1 2

PH900

Compal Electronics, Inc.

D

2

1

B+_BIAS

0.1U_0402_25V6

+3VLP

PR916
13K_0402_1%

1 2

12

PS_ID <24>

@

1.0

43 56Wednesday, February 01, 2012

A

VIN

1 1

PR100

PR104

PC100

2.2U_0805_25V6K

2 2

ACOFF <24>

BATT_TEMP

3 3

BATT_TEMP

For DT Mode

12

3.3_1210_5%

12

3.3_1210_5%

1 2

2

ACIN

PR131

1 2

10K_0402_5%

8
7

5

12

V1

61

H_PROCHOT#<6,24>

PQ100
AO4407AL_SO8

PR103

200K_0402_1%

PQ105A

SSM6N7002FU-2N_SOT363-6

PR118
47K_0402_5%

1 2

2

1
2
36

4

PDTA144EU PNP_SOT 323

2

1U_0603_25V6K

PQ103

2

13

13

2

61

PQ112A

SSM6N7002FU-2N_SOT363-6

12

PC127

@

13

D

2

G

S

P2

12

PC101

1 3

PQ104

12

PR105
150K_0402_1%

3

DDTC115EUA-7-F_SOT323

5

ACIN <15,24,35,43>

PQ109

DDTC115EUA-7-F_SOT323

BATT_TEMP<24,43>

PQ105B
SSM6N7002FU-2N_SOT 363-6

4

VDDP_LDO

12

731@

PR112

100K_0402_1%

ACIN

100_0402_1%

731@

PR125

12

PR117

158K_0402_1%

ADP_I<24,43 >

731@

PC131

.1U_0402_16V7K

PQ111

@

SSM3K7002FU_SC70-3

PU100

747@

12

0.1U_0603_25V7K

MAX8731_REF

12

PR133

100K_0402_1%

PC116

PR126

4.7K_0402_5%

1 2

1 2

PC132

731@

0.01U_0402_25V7K

PR113

PQ101

AO4409L_SO8

1
2
3 6

4

PR101

200K_0402_1%

1000P_0402_50V7K

747@

+5VALW

12

0.1U_0402_10V7K

1 2

PR122

747@

200K_0402_5%

12

PC123

747@

1 2

120P_0402_50VNPO~D

MAX8731_REF

PR134

0_0402_5%

@

1 2

12

PC133

PR135

0_0402_5%

@

@

1 2

PC131

747@

5

12

@

0.1U_0402_10V7K
PC113

1 2

1 2

EC_SMB_CK1<24,43>

EC_SMB_DA1<24,43>

12

0.01U_0402_25V7K

747@

8
7

5

PC102

3

4

PC109

PR116

49.9K_0402_1%

PC124

1 2

747@

12

PC134

731@

0.01U_0402_25V7K

Iada=0~4.62A(90W)

P3

ADP_I = 19.9*Iadapter*Rsense

1 2

5600P_0402_25V7K~D

PQ106B

@

SSM6N7002FU-2N_SOT363-6

VIN

731@

1 2

747@

2200P_0402_50V7K

747@

56P_0402_50V8~D

12

1U_0603_10V6K

PC126

747@

VIN

12

4 4

ACOFF <24>

PR136

1.2K_1206_5%~D

3

5

PQ112B

4

SSM6N7002FU-2N_SOT363-6

A

BQ24747

309K/0402

BATT_TEMP<24,43>

0.1U/0402

V1

61

2

PQ106A

@

SSM6N7002FU-2N_SOT363-6

0.1U/0603

PR107

0/0402

747@

1

2

VIN

PR109

10_1206_1%

1 2

PC111

1U_0603_25V6K

PR113

210K_0402_1%

PR119

0_0402_5%

1 2

PR120

0_0402_5%

1 2

PC117

12

MAX8731_REF

PR129

1 2

10K_0402_5%

PC125

747@

PR127

0/0402

PC112

0.1U/0603

PR106

0/0402

B

PR102

0.01_1206_1%

12

PR123

1 2

7.5K_0402_5%

PC128

@

0.1U_0402_10V7K

747@

747@

747@

B

4

3

DCIN

ACSETIN

747@

12

PU100

PR133

PR112

PR117

PR113

PC131

PC132

C

D

CC = 3.52A (Normal)

CV = 13.3V

VIN

V1

5

61

2

PQ113A

SSM6N7002FU-2N_SOT 363-6

4

3

12

0_0402_5%

PR128

PC130

@

1 2

0.1U_0603_25V7K

CSIN

CSIP

12

PR106

10_0402_5%

731@

0.1U_0603_25V7K

1 2

PC107

0.047U_0603_25V7M

731@

1

28

PU100

22

DCIN

CSSP

ICREF

2

ACIN

13

ACOK

11

VDDSMB

10

SCL

9

SDA

14

NC

8

VICM

6

FBO

5

EAI

4

EAO

3

VREF

7

CE

12

GND

29

TP

ISL88731CHRTZ-T_QFN28_5X 5~D

731@

PC112

1 2

27

CSSN

UGATE

PHASE

LGATE

ICOUT

BOOT

VDDP

PGND
CSOP

CSON

VFB

B+

1UH_NRS4018T1R0NDGJ _3.2A_30%

12

PR107

10_0402_5%

731@

PC108

1 2

731@

26

BST

25

VDDP_LDO

21

DH_CHG

24

LX_CHG

23

20

19
18

17

VFB

1 2

15

16

NC

PL101

1 2

PC110

0.1U_0603_25V7K

1U_0603_10V6K

1 2

PR111

731@

4.7_0603_5%

12

PR114

0_0603_5%

1 2

BAT54HT1G_SOD323-2~D

PR130

100_0402_5%

731@

BST_CHGA

PD101

1 2

BATT+

PC103

12

4.7U_0805_25V6-K

747@

12

PC104

PC106

4.7U_0805_25V6-K

PC135

0.1U_0603_25V7K

1 2

PC115

1 2

1U_0603_10V6K

DL_CHG

PQ102

AO4407AL_SO8

1
2
3 6

CHG_B+

12

12

0.1U_0603_25V7K

PC105

2200P_0402_25V7K~D

5

PQ108

4

5

PQ110

4

PR110

47K_0402_1%

PQ107

DDTC115EUA-7-F_SOT323

786

AO4466L_SO8~D

123

10UH_PCMB063T-100MS _4A_20%

786

123

AO4712L_SO8~D

1 2

12

PR124

@

12

PC121

@

PC129

747@

0.1U_0603_25V7K

1 2

4

1 2

13

PL100

4.7_1206_5%

680P_0402_50V7K

200K_0402_1%

2

VDDP_LDO

12

10_0402_5%731@

PR127

8
7

5

1 2

PR108

100K_0402_1%

PR115

1 2

PR132

1 2

10K_0402_5%

ACOFF<24>

PR121

0.01_1206_1%

CHG

1

2

PC126

731@

1 2

0.22U_0603_25V7K

ISL88731C BQ24747 BQ24747ISL88731C BQ24747ISL88731C BQ24747ISL88731C

ISL88731C BQ24747

@ 100k

100k @

158k @

210k 309k

0.1u 220p

0.01u @

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

PR122

PR123

PR129

PC117

PC124

PC123

PC125

2012/01/17 2013/01/16

@ 200k

@

@

@

@

@

@

Compal Secret Data

Deciphered Date

C

7.5k

10k

2200p

56p

120p

1u

PC134

PC129

PC126

PR127

PR111

PC110

PD101

@0.01u

@ 0.1u

0.1u0.22u

10 0

4.7 @

@1u

@

BAT54HT1G

Title

PWR-Charger

Size D ocument Number Rev

LA-8241P

Date: Sheet of

PC108

PR106

PR107

PC112

731@ for ISL88731C

747@ for BQ24747

Compal Electronics, Inc.

D

3

PQ113B

4

SSM6N7002FU-2N_SOT363-6

12

12

PC122

10U_0805_25V5K~D

PC119

PC118

10U_0805_25V5K~D

10U_0805_25V5K~D

0.1u @

10 0

0.047u 0.1u

44 56Wednesday, February 01, 2012

BATT+

12

PC120

@

010

12

10U_0805_25V5K~D

1.0

A

B

C

D

E

2VREF_6182

1U_0603_16V6K

12

PC202

1 2

PR201

1 2

PR203

1 2

PR205

1 2

PU200

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

PC201

@

FB_3V

ENTRIP2

6

ENTRIP2

EN

13

B++

PJP202

1 2

PAD-OPEN 4x4m
PJP204

1 2

PAD-OPEN 4x4m

0.1U_0402_25V6

PC200

@

1 2

PR202

30.9K_0402_1%

1 2

PR204
20K_0402_1%

FB_5V

1 2

PR206
110K_0402_1%

ENTRIP1

1 2

1

2

5

4

3

FB1

FB2

REF

TONSEL

ENTRIP1

24

VO1

23

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

SKIPSEL

14

NC18VREG5

VIN16GND

17

15

BST_5V

22

21

20

19

RT8205LZQW(2) WQFN 24P PW M

UG_5V

LX_5V

LG_5V

2.2_0603_5%

VL

12

PC216

4.7U_0805_10V6K

12

PC218

0.1U_0402_25V6

PR208

1 2

B++

12

PC207

PC208

0.1U_0402_25V6

0.22U_0603_10V7K

POK <43>

BST1_5VBST1_3V

2200P_0402_50V7K

12

PC211

12

PC209

4.7U_0805_25V6-K

12

AON7702A_DFN8-5

4

PQ205

PQ203
AON7408L_DFN8-5

3 5

241

5

123

PL201

3.3UH_PCMC063T-3R3MS_6A_20 %

1 2

12

@

PR210

4.7_1206_5%

SNUB_5V

12

@

PC215

680P_0603_50V7K

1

+

2

+5VALWP

PC213
330U_6.3V_M

5VALWP
TDC 5.6A
Peak Current 8A
OCP current 9.6A
TYP MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :11mohm , 14mohm

+5VALW

+3VALWP

PJP203

1 2

PAD-OPEN 4x4m
PJP200

1 2

PAD-OPEN 4x4m

+3VALW

1 1

0.1U_0402_25V6

13.7K_0402_1%

PC203

EC_ON_35V<28>

VCOUT0_PH< 24>

12

0.1U_0402_25V6

1 2

PR216
150K_0402_1%

@930

B++

12

12

PC204

2200P_0402_50V7K

SSM6N7002FU-2N_SOT363-6

PR213 2.2K_0402_5%

PR215 0_0402_5%

PC205

4.7U_0805_25V6-K

3.3UH_PCMC063T-3R3MS_6A_20 %

1 2

1

+

PC212
330U_6.3V_M

2

PQ200A

1 2

1 2

12

PR217

40.2K_0402_1%

@930

PL200

ENTRIP1ENT RIP1

61

3/5V_EN-2

12

PR209

2

PC219

4.7_1206_5%

SNUB_3V

@

N_3_5V_001

2

4.7U_0603_10V6K

12

12

@

PC214

680P_0603_50V7K

3 5

241

5

123

5

1 2

13

100K_0402_5%

PQ201

DTC115EUA_SC70-3

PQ202
AON7408L_DFN8-5

10U_0805_6.3V6M

0.22U_0603_10V7K

B++

4

BZV55-B5V1_SOD80C2

VCOUT0_PH<24>

PQ204
AON7702A_DFN8-5

ENTRIP2

34

PQ200B

SSM6N7002FU-2N_SOT363-6

PR214

PC206

PC210

LX_3V

VL

20K_0402_1%

+3VLP

110K_0402_1%

12

PR207

12

2.2_0603_5%

PD200@

@

21

1 2

0_0402_5%@

1 2

1 2

LG_3V

PR200

499K_0402_1%

PR211

@

PR212

200K_0402_1%

12

BST_3V

UG_3V

PC217

@

12

1U_0603_10V6K

2VREF_6182

+5VALWP

B+

PL202

1UH_PCMB061H-1R0MS_7A _20%

1 2

2 2

+3VALWP

3.3VALWP
TDC 5.4A
Peak Current 7.7A
OCP current 9.2A
TYP MAX
H/S Rds(on) :27mohm , 34mohm

3 3

L/S Rds(on) :11mohm , 14mohm

VS

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

PWR-3VALWP/5VALWP

LA-8241P

E

45 56Wednesday, February 01, 2012

1.0

A

B

C

D

1 1

PU400

PJP400

+3VALW

SUSP#<10,24,27,28,47,48>

2 2

1 2

PAD-OPEN 3x3m

@

12

1 2

PR402 100K_0402_5%

PC403
22U_0805_6.3VAM

EN_1.8VSP

47K_0402_5%

1.8VSP_VIN

PR401

@

12

12

PC405

4

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

NC

7

11

SY8033BDBC_DFN10_3X3

0.22U_0402_16V7K

1.8VSP_LX

2

LX

3

LX

1.8VSP_FB

6

FB

NC

1

PL400

1UH_NRS4018T1R0NDGJ _3.2A_30%

1 2

12

20K_0402_1%

PR404

4.7_1206_5%

SNUB_1.8VSP

12

10K_0402_1%

PC401

680P_0603_50V7K

12

PR403

12

PR400

12

PC402

12

12

22P_0402_50V8J

PC400

22U_0805_6.3V6M

+1.8VSP

<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR401/PR404)=0.6*(1+20K/10K)=1.8V

+1.8VSP

+1.8VSP
TDC 2.6A
Peak Current 3.8A
OCP current 4.5A

PC404

22U_0805_6.3V6M

PJP401

@

1 2

PAD-OPEN 3x3m

+1.8VS

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

C

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-1.8VSP

LA-8241P

D

46 56Wednesday, February 01, 2012

1.0

5

4

3

+V1.05S_ VCCPP_B+

2

PJP500

@

2

112

JUMP_43 X118

1

B+

+3VS

12

D D

+V1.05S_VCCP_PW RGOOD<49>

PR502

1 2

PR503

150K_04 02_5%

SUSP#<10,24,27,28,46,48>

C C

1 2

0.22U_04 02_16V7K

47.5K_04 02_1%

12

PC506

TRIP_+V1.0 5S_VCCPP

EN_+V1.0 5S_VCCPP

FB_+V1.0 5S_VCCPP

RF_+V1.0 5S_VCCPP

12

PR504

470K_04 02_1%

PR501
100K_04 02_5%

1 2

PU500

1

2

3

4

5

TPS5121 2DSCR_SON10_ 3X3

PR507

4.99K_04 02_1%

PGOOD

TRIP

EN

VFB

TST

PC509

1000P_0 402_50V7K@

12

PC505

VBST

DRVH

SW

V5IN

DRVL

TP

12

9

8

7

6

11

UG_+V1.0 5S_VCCPP

SW_+ V1.05S_VCCPP

+V1.05S_ VCCPP_5V

LG_+V1.0 5S_VCCPP

12

PR506

1.2K_040 2_1%@

BST_+V1 .05S_VCCPP

10

PR500

1 2

2.2_0603 _5%

1 2

+VCCP

.1U_0603 _25V7K

PC500
1U_0603 _10V6K

12

+5VALW

5

PQ500

4

SIR472DP-T1-GE3_POWERPAK8-5~D

123

1UH_PCM C063T-1R0MN_1 1A_20%

5

PQ501

4

213

12

PR505

4.7_1206 _5%@

12

PC508

1000P_0 402_50V7K

@

SIR818DP-T1-GE3_POWERPAK8-5~D

PC501

PC502

0.1U_0402_25V6

PL500

1 2

12

12

2200P_0402_50V7K

12

PC503

PC504

4.7U_0805_25V6-K

4.7U_0805_25V6-K

+VCCP

@

1 2

PC507

0.1U_0402_10V7K

PR508

0_0402_ 5%

12

VCCIO_SENSE < 9>

PR509
10K_040 2_1%

1 2

PJP501

B B

+VCCP +1.05VS

@

1 2

PAD-OPEN 4x4m

+V1.05S_VCCP
TDC 11A
Peak Current 16A
OCP current 19A
TYP MAX
H/S Rds(on) 10mohm , 14.5mohm
L/S Rds(on) :3mohm , 3.6mohm

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/01/ 17 2013/01/ 16

3

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PWR-V1.05S_VCCPP

LA-8241P

1

1.0

47 56Wednesd ay, February 01, 2012

5

4

3

2

1

20

PU300

VTT

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

PJP301

PAD-OPEN 1x1m

21

1

2

3

4

5

1.5V_FB

+1.5V

12

PC314 220P_04 02_50V8J~D

1 2

PR305

10K_040 2_1%

PR307
10K_040 2_1%

1 2

VTTREF_ 1.5V

+1.5V

12

VLDOIN_1.5 V

PJP302

B+

D D

+1.5V

C C

@

2

112

JUMP_43 X118

0.68UH_P CMC063T-R68MN _15.5A_20%

1 2

1

+

PC308
330U_2.5 V_M

2

12

PL300

1.5V_B+

PC301

PR301

1 2

2.2_0603 _5%

12

12

12

PC305

PC303

PC302

4.7U_0805_25V6-K

SYSON<24,27,28>

0.1U_0402_25V6

4.7U_0805_25V6-K

12

@

PR303

4.7_1206_5%

SNUB_1.5V

@

12

PC312

680P_0603_50V7K

2200P_0402_50V7K

@

5

PQ302

4

213

SIR818DP-T1-GE3_POWERPAK8-5~D

PR306

200K_04 02_5%

1 2

5

PQ300

SIR472DP-T1-GE3_POWERPAK8-5~D

123

5

PQ301

213

SIR818DP-T1-GE3_POWERPAK8-5~D

12

PC304

0.22U_06 03_10V7K

1 2

4

+5VALW

4

PC300

1U_0402 _6.3VX5R

PR304

5.1_0603 _5%

1 2

0_0402_ 5%

SUSP#<10,24,27,28,46,47>

1 2

PR302

7.15K_04 02_1%

1 2

12

PC311
1U_0603 _10V6K

PR308

BOOT_1.5 V

DH_1.5V

SW_1 .5V

DL_1.5V

1 2

VDD_1.5V

CS_1.5V

PC309
1U_0603 _10V6K

+5VALW

1.5V_B+

S5_1.5V

S3_1.5V

15

LGATE

14

PGND

13

CS

RT8207M ZQW_W QFN20_3X3

12

VDDP

11

VDD

PR300

1M_0402 _1%

1 2

17

16

PHASE

PGOOD

10

19

18

BOOT

UGATE

TON

9

VLDOIN

S5

S3

8

7

0.75Volt +/- 5%
TDC 0.7A
Peak Current 1A
OCP Current 1.2A

12

12

PC306

10U_0805_6.3V6M

12

PC313
.1U_0402 _16V7K

@

PC307

10U_0805_6.3V6M

PC310

0.033U_0 402_16V7~D

+0.75VSP

1.5VP
TDC 14A
Peak Current 20A

+1.5V

OCP current 24A
TYP MAX
H/S Rds(on) :10mohm , 14.5mohm

B B

L/S Rds(on) :3mohm , 3.6mohm

+0.75VSP

@

PJP300

1 2

PAD-OPEN 3x3m

+0.75VS

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/01/ 17 2013/01/ 16

3

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PWR-1.5V/0.75VSP

LA-8241P

1.0

48 56Wednesd ay, February 01, 2012

1

5

4

3

2

1

D D

VID [0] VID[1] VCCSA Vout
0 0 0.9V
0 1 0.8V
1 0 0.725V
1 1 0.675V

output voltage adjustable network

PC600
680P_0402_50V7K

1 2

SNUB_+1.5VP

PR600

PR605

100K_0402_5%

1 2

12

PC601

@

0.1U_0402_10V7K

4.7_1206_5%

1 2

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

12

+3VS

0_0402_5%

PR601

+V1.05S_VCCP_PWRGOOD<47>

VCCSA_VID0 <10>

VCCSA_VID1 <10>

PL600

1 2

SA_PGOOD <24>

PC604

PC607

PC606

1 2

22U_0805_6.3VAM

1 2

1 2

22U_0805_6.3VAM

22U_0805_6.3VAM

PL601

C C

HCB1608KF-121T30_0603

+3VALW +VCCSAP

1 2

PC605

2200P_0402_50V7K

+VCCSA_PWR_SRC +VCCSA_PHASE

2

1

PC603

0.1U_0603_25V7K

12

12

12

68P_0402_50V8J

PC612

PC611

+VCCSAP_FB

10U_0805_6.3V6M

10U_0805_6.3V6M

PC610

SY8037BDCC_DFN12_3X3

12

PR603

1 2

1K_0402_5%

PU600

12

PVIN

11

PVIN

10

SVIN

9

FB

8

VOUT

7

VID1

1

LX

2

LX

3

LX

4

PG

+VCCSA_EN

5

EN

6

VID0

GND

13

PR604

1 2

1K_0402_5%

PC609

1 2

22U_0805_6.3VAM

+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

PR606

100_0402_5%

12

PR602

0_0402_5%

12

VCCSA_SENSE <10>

B B

A A

5

4

The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

@

PJP601

+VCCSAP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

1 2

PAD-OPEN 4x4m

+VCCSA

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-VCC_SAP

LA-8241P

1

49 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

PR700

10_0402_1%

D D

TRBSTA#

C C

PC716

VR_SVID_DAT<9>

VR_SVID_ALRT#<9>

VR_SVID_CLK<9>

1 2

PR702

1 2

8.06K_0402_1%

VCC_AXG_SENSE<10>

VSS_AXG_SENSE<10>

+VCCP

12

PR721

.1U_0402_16V7K

130_0402_1%

1 2

+VCCP

12

PR731
75_0402_1%

VR_HOT#<24>

VSSSENSE<9>

VCCSENSE<9>

B B

A A

VGATE<6,15>

TRBST#

0.033U_0603_16V7

FBA3

PC717

PR722

54.9_0402_1%

1 2

PR725

1 2

PC700

1 2

PC704

0.033U_0603_16V7

VR_RDYA

12

.1U_0402_16V7K

0_0402_5%

VR_SVID_DAT1

PR743

1 2

10_0402_1%

8.06K_0402_1%

FBA1

12

+3VS

12

FB_CPU3

PR746

1 2

PR754

1 2

1K_0402_1%

PR703

1 2

806_0402_1%

+3VS

CPU_B+

PR732
10K_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

PC729

1 2

0.033U_0603_16V7

DROOP

PR707

1 2

10_0402_1%

1 2

0_0402_5%

1 2

0_0402_5%

12

PR716
10K_0402_1%

VR_ON<24>

95.3K_0402_1%

1 2

PR727 1K_0402_1%

PR735

PR737

PR741

1 2

49.9_0402_1%

FB_CPU2

12

PC732

1000P_0402_50V7K

PR708

1 2

1K_0402_1%

PR753

PR765

@

+5VS

PR726

1 2

VSN

12

PC722
1000P_0402_50V7K

VSP

FB_CPU1

1 2

806_0402_1%

0.033U_0603_16V7

PC736

1 2

FBA2

560P_0402_50V7K

1 2

2_0603_5%

PC714

1 2

2.2U_0603_10V7K

1 2

0_0402_5%

1 2

12

PC720

PR739

1 2

1K_0402_1%

PC727

1 2

560P_0402_50V7K

PR747

CSREFCSCOMP

PC706

1 2

+5VS

PC753

1 2

2.2U_0603_10V7K
PR718

PR720

VR_ON_CPU

PR724

10K_0402_1%

0.01U_0402_25V7K

IMVP_IMON<24>

PR709

1 2

5.11K_0402_1%

1000P_0402_50V7K

6132_VDDBP

6132_VCC

6132_VDDBP

VR_RDYA

VR_SVID_DAT1
VR_SVID_ALRT#
VR_SVID_CLK

VBOOT

ROSC_CPU
VRMP
VR_HOT#
VGATE

DIFF_CPU

PR742

6.34K_0402_1%

PR736

@

0_0402_5%

10P_0402_50V8J

PC707

1 2

COMPA1

PC711

1 2

PU700

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

PC725

10P_0402_50V8J

COMP_CPU1

12

1 2

PC701

1 2

.1U_0402_16V7K

PR701

1 2

24.9K_0402_1%

PC708

1 2

1500P_0402_50V7K

DIFFA

59

60

61

58

PAD

VSPA

VSNA

DIFFA

VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT

NCP6132BMNR2G_QFN60_7X7

ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF

COMP

TRBST#

18

17

16

FB_CPU

TRBST#

COMP_CPU

12

PC728

12

1800P_0402_50V7K

PC734

PR749

1 2

24.9K_0402_1%

PUT COLSE
TO VCORE
Phase 1
Inductor

PUT COLSE

12

TO GT

PH700

1 2

1 2

PC703

PC702

1200P_0402_50V7K

PR711

1 2

69.8K_0603_1%

PC710
1000P_0402_50V7K

1 2

CSCOMPA

PR713

1 2

15.8K_0402_1%

CSSUMA

DROOPA

ILIMA

51

53

50

54

52

49

ILIMA

IOUTA

CSSUMA

DROOPA

CSCOMPA

CSCOMP22CSP325CSREF24CSSUM

CSP2

23

27

26

PC730
1000P_0402_50V7K

1 2

1 2

PR751

1 2

75K_0402_1%

PH703

220K_0402_5%_ERTJ0EV224J

CSP1A

TSENSEA

48

47

46

CSP2A

CSP1A

TSNSA

CSREFA

PWMA

CSP1

DRVEN

TSNS

PWM

29

28

30

TSENSETSENSE CSP2A

1 2

CSP1
CSP2
CSP3

CSSUM

PC733

1500P_0402_50V7K

1 2

NTC_PH201

12

FBA

COMPA

TRBSTA#

IMONAIMONA

56

55

57

FBA

COMPA

TRBSTA#

DROOP21FB

IOUT

ILIM

19

20

DROOP

ILIM_CPU

1 2

PR738 12.7K_ 0402_1%

CSCOMPCSCOMPCSCOMPCSCOMPCSCOMPCSCOMP

1 2

.1U_0402_16V7K

680P_0402_50V7K

PR706

165K_0402_1%

SWN1A

PC713

1 2

.1U_0402_16V7K

45
44

BSTA

43

HGA

42

SWA

41

LGA

40

BST2

39

HG2

38

SW2

37

LG2

36

PVCC

35

PGND

34

LG1

33

SW1

32

HG1

31

BST1

PC723

.1U_0402_16V7K

PC735
560P_0402_50V7K

PR704

1 2

NTC_PH203

12

BST2

6132P_VCCP

BST1

PR733

1 2

43.2K_0402_1%

CSREF <51>

PR752

1 2

165K_0402_1%

75K_0402_1%

CSREFA <51>

1 2

28K_0402_1%

DRVEN <51>

Inductor

220K_0402_5%_ERTJ0EV224J

CSREFA

PC709

0.047U_0402_16V7K

1 2

CSP1A

PR717

PR723

1 2

2.2_0603_5%

HG2 <51>

LG2 <51>

LG1 <51>

HG1 <51>

PR730

1 2

2.2_0603_5%

CSP2

CSREF

CSP1

CSREF

PR748

1 2

130K_0603_1%

PR750

1 2

130K_0603_1%

PR712 6.98K_0402_1%

1 2

6132_PWMA <51>

PC718

BST2_1

12

0.22U_0603_10V7K

PC719 2.2U_0603_10V7K

12

PR728

1 2

0_0402_5%

BST1_1

12

PC721

0.22U_0603_10V7K

PR740

1 2

6.98K_0402_1%

12

PC726

PR766

1 2

13.3K_0402_1%

0.047U_0402_16V7K

PC731

0.047U_0402_16V7K

PR744

1 2

6.98K_0402_1%

12

PR767

@

1 2

13.3K_0402_1%

SWN1

SWN2

SWN1A <51>

+5VS

1 2

1K_0402_1%

<BOM Structure>

SW2 <51>

SW1 <51>

SWN2 <51>

SWN1 <51>

PR705

PR714

Option for
1 phase GFX

Option for
2 phase CPU

PC705

1 2

1000P_0402_50V7K

TSENSEA

12

8.25K_0402_1%

PUT COLSE
TO V_GT
HOT SPOT

+5VS

CSP2A

+5VS

CSP3

TSENSE

12

PR745

8.25K_0402_1%

PUT COLSE
TO VCORE
HOT SPOT

1 2

1 2

CSREFACSCOMPA DROOPA

PH701

100K_0402_1%_TSM0B104F4251RZ

PH702

100K_0402_1%_TSM0B104F4251RZ

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

CPU Core

LA-8241P

1

50 56W ednesday, February 01, 2012

1.0

5

D D

B+

PJP700

@

2

JUMP_43X118

112

1

+

PC712

2

CPU_B+

1

+

PC724

2

100U_25V_M~D

100U_25V_M~D

4

3

2

VCC_core
TDC 32A
Peak Current 53A
OCP current 65
Load line -1.9mV/A
FSW=300kHz
DCR 1.1mohm +/-5%
TYP MAX
H/S Rds(on) :10mohm , 14.5mohm
L/S Rds(on) :3mohm , 3.6mohm

1

CPU_B+ CPU_B+

12

12

12

PC741

PC740

PQ707

@

GFX_BST_1

SIR818DP-T1-GE3_POWERPAK8-5~D

GFX_HG

PC739

4.7U_0805_25V6-K

12

PR755

4.7_1206_5%

SNUB_CPU1

12

PC745

680P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PL701

0.36UH_FDU1040J-H-R36M=P3_33A_20%

4

3

@

@

PC750

0.22U_0603_10V7K

1 2

GFX_SW

GFX_LG

+VCC_CORE

HG2<50>

1

2

PR757

V1N_CPU

10_0402_1%

12

CSREF <50>

SWN1 <50>

12

12

PC747

5

PQ704

4

SIR472DP-T1-GE3_POWERPAK8-5~D

123

5

PQ705

4

4

213

SIR818DP-T1-GE3_POWERPAK8-5~D

PC749

PC748

4.7U_0805_25V6-K

5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

12

PR762

PQ706

213

SNUB_GFX1

12

PC752

SIR818DP-T1-GE3_POWERPAK8-5~D

SW2<50>

LG2<50>

112

PL704

B+

1

2

PJP701

@

2

JUMP_43X118

12

0.36UH_FDU1040J-H-R36M=P3_33A_20%

4

3

4.7_1206_5%@

680P_0402_50V7K@

5

PQ700

EN_GFX

12

12

PC751

2.2U_0603_10V7K

4

5

4

213

GFX_BST

PU701

1

BST

2

PWM

3

EN

4

VCC

NCP5911MNTBG_DFN8_2X2

123

FLAG

DRVH

GND

DRVL

SW

SIR472DP-T1-GE3_POWERPAK8-5~D

PQ702

SIR818DP-T1-GE3_POWERPAK8-5~D

5

4

PR759

1 2

2.2_0603_5%

9

8

7

6

5

213

HG1<50>

C C

B B

A A

+5VS

6132_PWMA<50>

SW1<50>

LG1<50>

QC-SV 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=32A
R_LL=1.9m ohm
OCP~65A

DRVEN<50>

DRVEN

2K_0402_1%

PR761
0_0402_5%

VCC_GFX

12

PR760

5

4

123

5

4

213

+VCC_GFXCORE_AXG

PR764

12

10_0402_1%

PQ701

SIR472DP-T1-GE3_POWERPAK8-5~D

PQ703

4

SIR818DP-T1-GE3_POWERPAK8-5~D

CSREFA <50>

SWN1A <50>

5

PQ708

@

213

SIR818DP-T1-GE3_POWERPAK8-5~D

PC742

12

PR756

4.7_1206_5%

SNUB_CPU2

12

PC746

680P_0402_50V7K

12

12

12

PC743

PC744

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

+VCC_CORE

PL702

0.36UH_FDU1040J-H-R36M=P3_33A_20%

1

4

3

@

@

2

PR758

10_0402_1%

V2N_CPU

+VCC_GFXCORE_AXG
TDC 21.5A
Peak Current 33A
OCP current 40A
Load line -3.9mV/A
FSW=300kHz
DCR 1.1mohm +/-5%
TYP MAX
H/S Rds(on) :10mohm , 14.5mohm
L/S Rds(on) :3mohm , 3.6mohm

CSREF

12

SWN2 <50>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-VCC_SAP

LA-8241P

1

51 56Wednesday, February 01, 2012

1.0

5

VGA@

VGA@

10P_0402_50V8J

PC828

12

VGA@

PR811

VGA@

PR833

VGA@

PR800

1 2

5.11K_0402_1%

1 2

1 2

12

105K_0402_1%

10P_0402_50V8J

VGA@

PR813

VGA@

PR810

PQ804

1 3

VGA@

1 2

5.11K_0402_1%

1

2

3

4

5.11K_0402_1%

5

PR834

VGA@

2.49K_0402_1%

1 2

SI2301CDS-T1-GE3_SOT 23-3

S

D

G

2

+3VS

12

VGA@

PR801

10K_0402_1%

PR835

VGA@

0_0402_5%

VSSSENSE_VGA<38>

D D

PR814

VGA@

2.49K_0402_1%

VGA@

PQ803

2N7002KW_S OT323-3

S

G

2

C C

PR803

VGA@

GPU_VID0GPU_VID1

10K_0402_1%

1 2

VGA_PW RGD<17,36>

PR804

2.2K_0402_5%

1 2

1 2

PC806

.1U_0402_16V7K

GPU_VID2

VGA@

VGA@

GPU_VID2<35>

PX_MODE<24, 36,53>

B B

Chelsea Pro

0 0 0

0 0 1

0 01

0 1 1

1 0 0

1 10

A A

11

1

0

11

1 2

12

PR815

VGA@

76.8K_0402_1%

D

13

EN_VGA_CORE

Core Voltage Level

0.95V

0.925V

0.9V

0.875V

0.85V

0.825V

0.8V

0.775V

0_0402_5%

1 2

4

VCCSENSE_VGA<38>

12

PC829

12

VGA@

20

21

PU801

PAD

GSNS

V3

V2

TPS51518RUKR_QFN20_3X3

V1

V0

VREF

6

12

PC830

0.1U_0402_10V7K

VGA@

PR836

1 2

1K_0402_5%

VGA@

3

VGA@

PR830

0_0402_5%

PR807

VGA@

43K_0402_1%

1 2

1 2

PC814

18

19

4700P_0402_25V7K

TRIP

VSNS

SLEW

VID08PGOOD

7

VID19EN

16

17

GND

MODE

V5IN

DRVL

DRVH

SW

BST

10

15

LG_VGA_CORE

14

UG_VGA_CORE

13

SW_VGA _CORE

12

BST_VGA_CORE

11

VGA_CORE_5V

1U_0603_10V6K

1 2

PR802

VGA@

2.2_0603_5%

PC807

12

VGA@

+5VALW

1 2

PC805

VGA@

0.1U_0603_25V7K

5

PQ800

4

4

VGA@

123

SIR472DP-T1-GE3_POWERPAK8-5~D

5

213

5

PQ801

4

VGA@

SIR818DP-T1-GE3_POWERPAK8-5~D

2

VGA_CORE_B+

VGA@

VGA@

12

PC801

PC802

0.1U_0402_25V6
2200P_0402_50V7K

PL800

VGA@

0.36UH_FDU1040J-H -R36M=P3_33A_20%

1 2

12

PR808

PQ802

VGA@

213

SIR818DP-T1-GE3_POWERPAK8-5~D

@

4.7_1206_5%

12

PC813

@

1000P_0603_50V7K

PJP800

@

2

112

JUMP_43X118

VGA@

VGA@

12

12

12

PC803

PC804

4.7U_0805_25V6-K

4.7U_0805_25V6-K

1

1

+

VGA@

PC800

470U_D2_2VM_R4.5M

+

VGA@

2 3

2 3

PC809

470U_D2_2VM_R4.5M

1

B+

+VGA_CORE

VGA@

12

12

PC810

10U_0805_6.3V6M

VGA@

VGA@

12

PC812

PC811

10U_0805_6.3V6M

10U_0805_6.3V6M

+VGA_CORE
TD

PR838

@

0_0402_5%~D

PR839

@

0_0402_5%~D

1 2

1 2

C 22A
Peak Current 30A
OCP current 36A
FSW=350kHz
DCR 1.1mohm +/-5%
TYP MAX
H/S Rds(on) :10mohm , 14.5mohm
L/S Rds(on) :3mohm , 3.6mohm

+VGA_PCIE
TD

C 3.6A

Peak Current 5.2A

@

+3VALW

PR837

1 2

1K_0402_5%

VGA@

<35>

<35>

GPU_VID1

GPU_VID0

PJP805

2

112

JUMP_43X79

PR826

PXS_PWREN<16,36>

+VGA_PCIEP +1.0VGS

VGA@

1 2

200K_0402_5%

47K_0402_5%

2

EN_PCIE

PR828

@

PJP804

112

JUMP_43X79

PCIE_B+

VGA@

12

PC819
22U_0805_6.3VAM

12

@

VGA@

4

PU800

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

SS

7

VGA@

12

11

12

PC823

0.1U_0402_10V7K

LX_PCIE

2

LX

3

LX

FB_PCIE

6

FB

LX

SY8036LDBC_DFN10_3x3

1

PC822

VGA@

0.1U_0402_10V7K

PR827

VGA@

10K_0402_1%

PR825

VGA@

5.9K_0402_1%

12

PC825

VGA@

12

12

22P_0402_50V8J

PL801

VGA@

0.47UH_FDVE0630-H- R47M=P3_17.7A_20%

1 2

12

PR829

4.7_1206_5%

VGA@

SNUB_PCIE

12

PC826

VGA@

680P_0603_50V7K

+VGA_PCIEP

PR825 6.81K

OCP current 6A

12

12

PC821

PC820

22U_0805_6.3VAM

VGA@

22U_0805_6.3VAM

VGA@

Thames XT Chelsea Pro

1.0VVGA_PCIE

+VGA_PCIEP

12

12

PC824

PC818

22U_0805_6.3VAM

0.95V

5.9K

22U_0805_6.3VAM

VGA@

VGA@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/01/17 2013/01/16

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

VGA_COREP

LA-8241P

1

52 56Wednesday, February 01, 2012

1.0

A

B

C

D

1 1

+VDDCI
TDC 2.8A
Peak Current 4A

PL1000

1 2

4.7_1206_5%

680P_0603_50V7K

VGA@

10K_0402_1%

VGA@

PC1000

22P_0402_50V8J

VGA@

PR1000

12

1 2

VGA@

4.99K_0402_1%

12

PR1003

D

S

PR1006

VGA@

10_0402_5%

1 2

12

VGA@

PR1007

29.4K_0402_1%

13

2

G

PQ1000

VGA@

2N7002W- T/R7_SOT323-3

PR1004

0_0402_5%

VGA@

12

12

12

PC1003

22U_0805_6.3V6M

VGA@

PR1009

VGA@

10K_0402_5%

PC1006

@

4700P_0402_25V7K

12

12

PC1005

22U_0805_6.3V6M

VGA@

+3VGS

12

PR1008
10K_0402_5%

12

PR1010
100K_0402_5%

VGA@

@

VGA@

0.1U_0402_10V7K

4

PU1000

VGA@

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

SS

7

11

12

LX_VDDCIP

2

LX

3

LX

FB_VDDCIP

6

FB

LX

SY8036LDBC_DFN10_3x3

1

PC827

VGA@

0.1U_0402_10V7K

0.47UH_FDVE0630-H- R47M=P3_17.7A_20%

12

VGA@

PR1001

FB=0.6Volt

12

PC1002

VGA@

PJ1000

@

+3VALW

PX_MODE<24, 36,52>

2 2

112

JUMP_43X79

2

12

1 2

PR1002 10K_0402_5%

VGA@

PC1001

VGA@

22U_0805_6.3V6M

1M_0402_5%

PR1005

@

EN_VDDCIP

12

PC1004

1 2

OCP current 6A

+VDDCIP

VDDCI_SEN <38>

VDDCI_VID <35>

VDDCI_VID

1VHigh

Low 0.9V

3 3

+VDDCIP

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

C

@

PJ1001

1 2

PAD-OPEN 4x4m

+VDDCI

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

+VDDCIP

LA-8241P

D

53 56Wednesday, February 01, 2012

1.0

5

4

3

2

1

+VCC_CORE

1

PC1201
10U_080 5_6.3VAM

2

D D

1

PC1206
10U_080 5_6.3VAM

2

1

PC1202
10U_080 5_6.3VAM

2

1

PC1207
10U_080 5_6.3VAM

2

1

PC1203
10U_080 5_6.3VAM

2

1

PC1208
10U_080 5_6.3VAM

2

1

PC1204
10U_080 5_6.3VAM

2

1

PC1209
10U_080 5_6.3VAM

2

+VCC_CORE +VCC_GFXCORE_AXG

1

PC1205
10U_080 5_6.3VAM

2

1

PC1210
10U_080 5_6.3VAM

2

+VCC_GFXCORE_AXG

22U_0805_6.3V6M

22U_0805_6.3V6M

PC1212

PC1211

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

PC1213

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

PC1215

PC1214

1

2

PC1216

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

PC1218

PC1217

1

1

2

2

+VCC_CORE

1

PC1219
22U_080 5_6.3V6M

2

1

PC1238
22U_080 5_6.3V6M

2

C C

1

PC1249
22U_080 5_6.3V6M

2

1

PC1256
22U_080 5_6.3V6M

2

1

PC1220
22U_080 5_6.3V6M

2

1

PC1239
22U_080 5_6.3V6M

2

1

PC1250
22U_080 5_6.3V6M

2

1

PC1221
22U_080 5_6.3V6M

2

1

PC1240
22U_080 5_6.3V6M

2

1

PC1251
22U_080 5_6.3V6M

2

1

PC1222
22U_080 5_6.3V6M

2

1

PC1241
22U_080 5_6.3V6M

2

1

PC1252
22U_080 5_6.3V6M

2

1

PC1223
22U_080 5_6.3V6M

2

1

PC1242
22U_080 5_6.3V6M

2

1

PC1253
22U_080 5_6.3V6M

2

PC1246

330U_D2 _2V_Y

22U_0805_6.3V6M

1

2

PC1235

1

2

1

+

PC1247
330U_D2 _2V_Y

2

22U_0805_6.3V6M

22U_0805_6.3V6M

PC1236

PC1237

1

2

22U_0805_6.3V6M

PC1234

1

2

1

+

2

Below is 458544_CRV_PDDG_0.5 Table 5-8.

5 x 22 µF (0805)

Socket Bottom

5 x (0805) no-stuff
sites

7 x 22 µF (0805)

Socket Top

2 x (0805) no-stuff
sites

+VCCP

+VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

2

PC1225

PC1224

2

22U_0805_6.3V6M

1

1

PC1226

PC1227

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

PC1228

PC1229

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

2

22U_0805_6.3V6M

1

2

330U_D2_2VM_R9M

1

+

2

1

PC1231

PC1230

2

2

22U_0805_6.3V6M

1

PC1244

PC1243

2

330U_D2_2VM_R9M

1

PC1200

PC1254

+

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

PC1233

PC1232

2

22U_0805_6.3V6M

1

PC1245

2

330U_D2_2VM_R9M

1

PC1255

+

2

+VCC_CORE

1

+

PC1257

B B

A A

330U_D2 _2VM_R9M

2 3

1

+

PC1261
330U_D2 _2V_Y

2

1

+

PC1258
330U_D2 _2V_Y

2

1

+

@

5

PC1262
330U_D2 _2V_Y

2

1

+

PC1259

330U_D2 _2VM_R9M

2 3

@

1

+

PC1260
330U_D2 _2V_Y

2

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/01/ 17 2013/01/ 16

3

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

LA-8241P

54 56Wednesd ay, February 01, 2012

1

1.0

5

4

3

2

1

Power block

CPU OTP

D D

B+

+3VALWP: TDC:5.4A
+5VALWP: TDC:5.6A

DC IN

Input
Switch

Page 44

RT8205LZQW(2) WQFN

Page 43

Turn Off

Always

Page 45

CHARGER
CC:0A~3.52A
CV:13.3V(6cell)
ISL88731CHRTZ-T

Page 44

C C

Battery

+1.8VSP: TDC:2.6A
SY8033BDBC

Page 46

+VCCP: TDC:11A
TP

S51212DSCR

Page 47

+1.5V/+0.75VSP: TDC:14A/0.7A

SUSP#

SUSP#

SYSON

RT8207MZQW

Page 48

+VCCSAP: TDC:4.2A
SY

8037DCC

PX_MODE

B B

+VGA_CORE
TDC:23.4A
TPS51518RUKR

Page 52

+VGA_PCIEP: TDC:3.5A
SY8036LDBC

Page 49

Page 52

+V1.05S_VCCP_PWRGOOD

PXS_PWREN

VR_ON

A A

VR_ON

5

+VCC_CORE
TDC: 32A
NCP6132BMNR2G

+VCC_GFXCORE_AXG
TDC: 21.5A
NCP6132BMNR2G

Page 50/51

Page 50/51

4

+VDDCIP: TDC:2.8A
SY8036LDBC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/1/17 2013/1/16

Compal Secret Data

Deciphered Date

Page 53

2

PX_MODE

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

LA-8241P

55 56Wednesday, February 01, 2012

1

0.2

5

Request

Request

Item

Item Issue Description

ItemItem

D D

Page# Title

Page#Page#

1 Frank44 Charge r. 11 /12/08 Change PR113 fro m 316k to 309k for Charger IC B Q24747RHDR.

2 45 3.3VALWP/5VA LWP 11/12/08 Frank

Title

TitleTitle

Date

DateDate

RequestRequest
Owner

Owner

OwnerOwner

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

Change PR113 for temperature a nd voltage test.

Design change.

3

2

Page 1

Page 1

Page 1Page 1

Remove PR132.

Change PC219 fro m 1uF to 4.7uF.

1

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

Rev.Page#

Rev.Rev.

X00

X00

+VDDCIP533 11/12/08 F rank Change PR1002 fr om 100k to 0ohm .

C C

B B

Fine tune time s equence.

Remove PR1005 an d PC1004.

X00

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PWR-PIR

LA-8241P

1

56 56Wednesday, February 01, 2012

1.0