COMPAL LA-8241P Schematics
A
www.qdzbwx.com
B
C
D
E
MODEL NAME :
PCB NO :
BOM P/N :
1 1
LA-8241P
4619GP31L21
4619GQ31L21
4619GP31L01
4619GQ31L01
QCL00_QCL20
Inspiron DIS
Inspiron UMA
Vostro DIS
Vostro UMA
www.qdzbwx.com
Dell / Compal Confidential
Schematic Document
2 2
Inspron A5 & Vostro 3560 (Intel Chief River)
Ivy Bridge(rPGA) + Panther Point(mainstream)
Discrete AMD Thames-XT
3 3
46@ : for 46 level
@ : Nopop Component
2012-02-01
Rev: 1.0
CONN@ : Connector Component
KB930@ : ENE KB930 Implemented
ConfigBOM P/NMB Type
KB9012@ : ENE KB9012 Implemented
EXP@ : Express Card Implemented
FFS@ : Only for Free Fall Sensor
VOS@ : Only for Vostro
4 4
INS@ : Only for Inspiron
UMA@ : Only for UMA
GCLK@ : Green CLK implemented
AMP@ : External Amplifier implemented
KBBL@ : Keyboard Back Light implemented
A
B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
D
X76@ : VRAM Group
CH@ : Chelsea M2
SE@ : Seymour M2
TH@ : Thames-XT
DIS@ : Only for Discrete
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Cover Page
LA-8241P
E
1 56Wednesday, February 01, 2012
1.0
A
www.qdzbwx.com
B
C
D
E
Compal Confidential
Project Code : QCL00 / QCL20
File Name : LA-8241P
1 1
64M*16
VRAM * 4
DDR3
CRT Conn.
2 2
LVDS Conn.
HDMI Conn.
Port 3 Port 1
Mini Card-1
WLAN / BT4.0
Half
3 3
P.32 P.32
Daughter board
RTC CKT.
Power On/Off CKT.
DC/DC Interface CKT.
4 4
A
P.41
P.22
P.22
P.23
Port 11
Express Card
34mm Slot
Daughter board
P.13
P.25
P.27
64bit
Port 2
P.28
64M*16
VRAM * 4
DDR3
AMD
Thames-XT /
Chelsea Pro
24-26 W
40
P.
64bit
P.34~39
Ethernet
RTL8105E (10/100)
RTL8111F (10/100/1000)
RJ45
Daughter board
SPI ROM
4MB
SPI ROM
2MB
B
PEG 3.0 x16
CRT
LVDS
HDMI
USB2.0
PCI-E x1
P.13
P.13
Int.KBD
page 25
Intel
Ivy Bridge
Processor
35W QC
35W DC
100MHz 100MHz
2.7GT/s
rPGA 988
rPGA 988
Intel
Panther Point
PCH HM77
BGA 989 Balls
SPI
LPC Bus
SPI
PS/2
Touch Pad
33MHz
ENE KBC
KB9012 /
KB930
page 25
page 24
Dashboard
Button x3
Memory Bus (DDR3)
Dual Channel
1.5V DDR3 1333 MHz
P.5~10
DMI x4FDI x8
5GB/s
SATA3.0
USB 3.0
USB2.0
Port 0
Port 1
Port 5
Port 2
Port 1,2
Port 0,1
Port 3,4
Port 2,3
Port 12
Port 4
Port 10
Port 8
HD Audio
P13~
20
Audio Codec
CX20672
SPI
Amplifier
TPA3113D2
SPI ROM
page 32
C
128K
page 26
reserved for KB930
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
2012/01/17 2013/01/16
www.qdzbwx.com
Fan Control
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
P.25
CPU XDP
Conn.
page 11,12
P.6
8GB Max
SATA HDD Conn.
Mini Card-2 (mSATA)
( Full )
SATA ODD Conn.
USB 3.0 Conn. 1
USB 3.0 Conn. 2 -( USB Charger )
USB 3.0 Conn. 3
USB 3.0 Conn. 4
Digital Camera
Mini Card-1 (WLAN)
( Half )
Card Reader
RTS5139
Finger Print
P.29
P.32
P.29
P.33
P.32
P.22
P.32
P.32
P.32
FFS
Daughter board
Daughter board
Daughter board
3 in 1 Socket
Daughter board
P.29
Digital Mic.
Headphone Jack
P.30
P.31
Mic. Jack
Int. Speaker R/L
only for Vostro 3560
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
LA-8241P
E
2 56Wednesday, February 01, 2012
1.0
A
www.qdzbwx.com
B
C
D
E
Compal Confidential
www.qdzbwx.com
Project Code : QCL00 / QCL20
Name : LA-8241P
File
1 1
8 pi
n-Hot Bar
Led1
Led2
LS-8245P (Ins)
LS-8255P (Vos)
2 2
3 3
FFC
4 pin
Lid (Inspiron)
SW1
4 pin-Hot Bar
LED/B
JPWR
4 pin
10 pin
LA-8241P M/B
JTP
4 pin
TP Led (Vos)
TP Led (Ins)
JEXP
26 pin
(Vostro)
JLVDS
40 pin
JFP
6 pin
JCR2
4 pin
(Vos
JCR1JLED
4 pin
(Inspiron)
tro)
80 pin
JBT
26
1
Led1 Led2 Led3
FFC
8 pin
JFC
8 pin
B1
SW1 SW2 SW3
LS-8241P (Ins) LED/B
LS-8251P (Vos)
Lid (Vostro)
LS-8242P (Ins) IO/B
LS-8252P (Vos)
FFC
4 pin
4 pin-Hot Bar
Card Reader/B
LS-8243P (Ins)
LS-8253P (V
os)
40 pin
Wire
FFC
4 pin
Touch Pad
L R
Camera
LCD Panel
FFC
10 pin
LS-8244P (Ins)
LS-8254P (Vos)
10 pin-Hot Bar
Led1
Led2 Led3 Led4
4 4
A
LED/B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
Express Card
Top Side
Bottom Side
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
D
4 pin-Hot Bar
Finger Print/B
LS-8256P (Vos)
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
E
3 56Wednesday, February 01, 2012
1.0
A
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Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7
SMBUS Control Table
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PCH_SML0CLK PCH
PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
MEM_SMBCLK
MEM_SMBDATA
CLKOUT
1 1
PCI0
100K +/- 5%Ra
Rb V min
0 0 V
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
SOURCE
KB9012
KB9012
PCH
PCH
AD_BID
0.168 V
0.375 V 0.503 V
0.634 V
0.958 V
1.372 V
1.851 V
2.433 V
MINI2
MINI1 BATT SODIMM
V V
DESTINATION
PCH_LOOPBACK
V
V typ
AD_BID
0 V 0.155 V
0.250 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
Express
Card
V
V
V
AD_BID
0.362 V
0.621 V
0.945 V
1.359 V
1.838 V
2.420 V
3.300 V
Thermal
Sensor
max
FFS VGA
EC AD3
0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF
VGA Thermal
Sensor
V
V
BOARD ID Table
Board ID
XDP
Charger
V
V
V
0
1
2
3
4
5
6
7
PCB Revision
0.1
0.2
0.3
1.0
QCL00 QCL20
0.1
0.2
0.3
1.0
Link
0.2
0.3
1.0
QCL01
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PCH
USB PORT#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
USB conn.1
USB conn.2 - Power Share
USB conn.3
USB conn.4
MINI
NC
NC
NC
Finger Print
NC
Card Reader
Express Card
Camera
NC
DESTINATION
CARD-1 (WLAN)
PCI1
PCI2
PCI3
PCI4
EC LPC
None
SATA
DESTINATION
PCI EXPRESS
DESTINATION
None
SATA0
HDD
Lane 1
10/100/1G LAN
None
SATA1
SATA2
DESTINATIONDIFFERENTIAL
FLEX CLOCKS DESTINATION
SATA3
CLKOUT_PCIE0
10/100/1G LAN
CLKOUTFLEX0
None
SATA4
CLKOUT_PCIE1
MINI CARD-1 WLAN
CLKOUTFLEX1
None
SATA5
CLK
CLKOUT_PCIE2
CLKOUT_PCIE3
CLKOUT_PCIE4
CLKOUT_PCIE5
CLKOUT_PCIE6
Express Card
None
None
None
None
CLKOUT_PCIE7 None
CLKOUT_PEG_B
None
CLKOUTFLEX2
CLKOUTFLEX3
None
None
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
A
Symbol Note :
: means Digital Ground
: means Analog Ground
2012/01/17 2013/01/16
SSD
ODD
None
None
None
Compal Secret Data
Deciphered Date
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8 None
MINI CARD-1 (WLAN)
Express Card
None
None
None
None
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Notes List
LA-8241P
4 56Wednesday, February 01, 2012
1.0
5
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4
3
2
1
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+VCCP
12
RC2
24.9_0402_1%
D D
DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>
DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>
DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>
DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>
FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>
C C
B B
FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>
FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>
FDI_FSYNC0<15>
FDI_FSYNC1<15>
FDI_INT<15>
FDI_LSYNC0<15>
FDI_LSYNC1<15>
+VCCP
1 2
RC36 24.9_0402_1%
RC158 10K_0402_5%
@
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
+EDP_COM
12
JCPU1A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_Rev1p0
CONN@
PEG_COMP
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
Intel(R) FDI
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
eDP
CC9 220nF_0402_16V7KDIS@
1 2
CC10 220nF_0402_16V7KDIS@
1 2
CC11 220nF_0402_16V7KDIS@
1 2
CC12 220nF_0402_16V7KDIS@
1 2
CC13 220nF_0402_16V7KDIS@
1 2
CC14 220nF_0402_16V7KDIS@
1 2
CC15 220nF_0402_16V7KDIS@
1 2
CC16 220nF_0402_16V7KDIS@
1 2
CC25 220nF_0402_16V7KDIS@
1 2
CC26 220nF_0402_16V7KDIS@
1 2
CC27 220nF_0402_16V7KDIS@
1 2
CC28 220nF_0402_16V7KDIS@
1 2
CC29 220nF_0402_16V7KDIS@
1 2
CC30 220nF_0402_16V7KDIS@
1 2
CC31 220nF_0402_16V7KDIS@
1 2
CC32 220nF_0402_16V7KDIS@
1 2
PEG_ICOMPI and R COMPO signals s hould be shorted and routed
with - max lengt h = 500 mils - typical impedanc e = 43 mohms
PEG_ICOMPO signa ls should be ro uted with - max length = 500 mils
- typical impeda nce = 14.5 mohm s
PEG_GTX_C_HRX_N7 <34>
PEG_GTX_C_HRX_N6 <34>
PEG_GTX_C_HRX_N5 <34>
PEG_GTX_C_HRX_N4 <34>
PEG_GTX_C_HRX_N3 <34>
PEG_GTX_C_HRX_N2 <34>
PEG_GTX_C_HRX_N1 <34>
PEG_GTX_C_HRX_N0 <34>
PEG_GTX_C_HRX_P7 <34>
PEG_GTX_C_HRX_P6 <34>
PEG_GTX_C_HRX_P5 <34>
PEG_GTX_C_HRX_P4 <34>
PEG_GTX_C_HRX_P3 <34>
PEG_GTX_C_HRX_P2 <34>
PEG_GTX_C_HRX_P1 <34>
PEG_GTX_C_HRX_P0 <34>
PEG_HTX_C_GRX_N7 <34>
PEG_HTX_C_GRX_N6 <34>
PEG_HTX_C_GRX_N5 <34>
PEG_HTX_C_GRX_N4 <34>
PEG_HTX_C_GRX_N3 <34>
PEG_HTX_C_GRX_N2 <34>
PEG_HTX_C_GRX_N1 <34>
PEG_HTX_C_GRX_N0 <34>
PEG_HTX_C_GRX_P7 <34>
PEG_HTX_C_GRX_P6 <34>
PEG_HTX_C_GRX_P5 <34>
PEG_HTX_C_GRX_P4 <34>
PEG_HTX_C_GRX_P3 <34>
PEG_HTX_C_GRX_P2 <34>
PEG_HTX_C_GRX_P1 <34>
PEG_HTX_C_GRX_P0 <34>
M34
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
Sandy Bridge_rPGA_Rev1p0
CONN@
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(1/6) DMI,FDI,PEG
LA-8241P
1
of
5 56Wednesday, February 01, 2012
1.0
5
www.qdzbwx.com
XDP_PREQ#_R
XDP_PRDY#_R
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
CFG10_R
RC130_0402_5% @
1 2
1 2
1 2
1 2
1 2
+VCCP
1 2
12
12
CFG11_R
RC150_0402_5% @
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
H_CPUPWRGD_XD P
RC221K_0402_5% @
CFD_PWRBTN#_X DP
RC230_0402_5% @
XDP_HOOK2
RC241K_0402_5% @
SYS_PWROK_XDP
RC260_0402_1% @
XDP_TCK1
RC30
XDP_TCK_R
H_THERMTRIP#<17>
H_PM_SYNC<15>
H_CPUPWRGD<17>
D D
C C
B B
A A
CFG10<8>
CFG11<8>
H_CPUPWRGD
CFG0<8>
VGATE<15,50>
PCH_JTAG_TCK<13>
The resistor
for HOOK2 should be
placed such that the
stub is very sma ll
on CFG0 net
H_PROCHOT#<24,44>
PCH_SMBDATA<11,12,14,28,29,32>
PCH_SMBCLK<11,12,14,28,29,32>
0_0402_5% @
RC43
62_0402_5%
+VCCP +VCCP
+3VALW
12
@
RC27
1K_0402_5%
SYS_PWROK_XDP
H_SNB_IVB#<17>
T1PAD~D @
H_PECI<17,24>
1 2
56_0402_1%
1 2
1 2
VDDPWRGOOD
CC64
1 2
@
10P_0402_50V8J
1 2
130_0402_1%~D
H_CPUPWRGD_R
4
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A
CONN@
H_CATERR#
RC41
H_PROCHOT#_R
H_THERMTRIP#
@
H_PM_SYNC_R
RC49
0_0402_1%
@
H_CPUPWRGD_R
RC53
0_0402_1%
RC57
VDDPWRGOOD_R
BUF_CPU_RST#
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
TMS
GND17
JCPU1B
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWR OK
AR33
RESET#
Sandy Bridge_rPGA_Rev1p0
CONN@
3
PM_DRAM_PWR GD<15>
PCH_PWROK<15,24>
SYS_PWROK<15>
+3V_PCH
1 2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
CLK_CPU_ITP
40
CLK_CPU_ITP#
42
44
XDP_RST#_R
46
XDP_DBRESET#
48
50
XDP_TDO
52
TD0
TDI
XDP_TRST#_R
54
XDP_TDI
56
XDP_TMS_R
58
60
+VCCP
@
1 2
RC25 1K_0402_5%
RC28 0_0402_5%@
1 2
RC31 0_0402_5%@
1 2
RC29 0_0402_5%@
1 2
0.1U_0402_16V7K
1
CC35
2
0.1U_0402_16V7K
1
CC36
2
CLK_CPU_ITP <14>
CLK_CPU_ITP# <14>PBTN_OUT#<15,24>
PLT_RST#
PCH_JTAG_TDO <13>
PCH_JTAG_TDI <13>
PCH_JTAG_TMS <13>
Place near JXDP1
BCLK
BCLK#
MISCTHERMALPWR MANAGEMENT
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
JTAG & BPM
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
CLK_CPU_DMI_R
A28
CLK_CPU_DMI#_R
A27
CLK_CPU_DPLL_R
A16
CLK_CPU_DPLL#_R
A15
Remove DPLL Ref clock (for eDP only)
H_DRAMRST#
R8
SM_RCOMP0
AK1
SM_RCOMP1
A5
SM_RCOMP2
A4
DDR3 Compe nsation Si gnals
XDP_PRDY#
AP29
XDP_PREQ#
AP27
XDP_TCK
AR26
XDP_TMS
AR27
XDP_TRST#
AP30
XDP_TDI_R
AR28
XDP_TDO_R
AP26
XDP_DBRESET#_R
AL35
XDP_BPM#0_R
AT28
XDP_BPM#1_R
AR29
XDP_BPM#2_R
AR30
XDP_BPM#3_R
AT30
XDP_BPM#4_R
AP32
XDP_BPM#5_R
AR31
XDP_BPM#6_R
AT31
XDP_BPM#7_R
AR32
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
RC37 0_0402_1%@
1 2
RC38 0_0402_1%@
1 2
RC39 1K_0402_1%
1 2
RC40 1K_0402_1%
1 2
H_DRAMRST# <7>
1 2
1 2
1 2
RC121 0_0402_5%@
1 2
RC122 0_0402_5%@
1 2
RC123 0_0402_1%@
1 2
RC124 0_0402_1%@
1 2
RC125 0_0402_1%@
1 2
RC50 0_0402_1%@
1 2
RC51 0_0402_1%@
1 2
1 2
RC56
RC59 0_0402_5%@
1 2
RC61 0_0402_5%@
1 2
RC62 0_0402_5%@
1 2
RC63 0_0402_5%@
1 2
RC64 0_0402_5%@
1 2
RC65 0_0402_5%@
1 2
RC66 0_0402_5%@
1 2
RC67 0_0402_5%@
1 2
RC68 0_0402_5%@
1 2
RC69 0_0402_5%@
1 2
RC70 0_0402_5%@
1 2
RC71 0_0402_5%@
1 2
0_0402_1%@
2
www.qdzbwx.com
RC127
0_0402_1%
@
RC11 0_0402_1%
RC4
200_0402_1%
RUN_ON_CPU1.5VS3#<10,27>
PLT_RST#<16,24,28,32>
RC55140_0402_1%
RC5825.5_0402_1%
RC60200_0402_1%
XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI
XDP_TDO
XDP_DBRESET#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
RC128
1 2
0_0402_5%
@
1 2
CFG12 < 8>
CFG13 < 8>
CFG14 < 8>
CFG15 < 8>
+3VS
12
@
@
RC6
10K_0402_5%
1 2
CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>
UC1
1
B
D_PWG
2
A
GND3Y
74AHC1G09GW TSSOP 5P
RUN_ON_CPU1.5VS3#
+VCCP
XDP_DBRESET# <15>
+3V_PCH
1
2
5
VCC
4
@
2
G
@
+3VALW
UC2
1
2
5
NC
VCC
A
4
GND3Y
SN74LVC1G07DCKR_SC70-5~D
0.1U_0402_16V7K
+1.5V_CPU_VDDQ
CC33
RC19
39_0402_1%
1 2
13
D
QC1
SSM3K7002F_SC59-3
S
0.1U_0402_16V7K
1
CC34
2
BUFO_CPU_RST#
PU/PD for JTAG signa ls
XDP_TMS_R
XDP_TDI_R
XDP_PREQ#
XDP_TDO
XDP_TCK_R
XDP_TRST#_R
XDP_DBRESET#
H_CPUPWRGD_R
1
12
RC8
200_0402_1%
VDDPWRGOOD
RC8
CRB 1.1K
CHECK LIST 0.7 - -> 4.75K
INTEL recommand 1.1K
PDG 0.71 rev --> 200
+VCCP
12
RC32
75_0402_5%
RC33
1 2
43_0402_1%
BUF_CPU_RST#
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
0.1U_0402_16V7K
12
@
RC34
CC63
0_0402_5%
+VCCP
RC4551_0402_5%
RC4651_0402_5%
RC4751_0402_5% @
RC4851_0402_5%
RC5251_0402_5%
RC5451_0402_5%
+3VS
RC421K_0402_5%
RC4410K_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(2/6) PM,XDP,CLK
LA-8241P
1
6 56Wednesday, February 01, 2012
1.0
5
www.qdzbwx.com
4
3
2
1
www.qdzbwx.com
JCPU1C
M_CLK_DDR0
DDR_A_D[0..63]<11>
D D
C C
B B
A A
DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>
DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>
H_DRAMRST#<6>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
H_DRAMRST#
4.99K_0402_1%
RC77
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
V6
AE8
AD9
AF9
12
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
Sandy Bridge_rPGA_Rev1p0
CONN@
@
1 2
RC74 0_0402_5%
QC2
BSS138_SOT23
S
G
2
DDR SYSTEM MEMORY A
D
DDR3_DRAMRST#_R
13
DRAMRST_CNTRL
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
+1.5V
12
RC75
1K_0402_5%
1 2
RC76 1K_0402_5%
M_CLK_DDR#0
DDR_CKE0_DIMMA
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_ODT0
M_ODT1
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
@
1 2
RC72 0_0402_1%
M_CLK_DDR0 <11>
M_CLK_DDR#0 <11>
DDR_CKE0_DIMMA <11>
M_CLK_DDR1 <11>
M_CLK_DDR#1 <11>
DDR_CKE1_DIMMA <11>
DDR_CS0_DIMMA# <11>
DDR_CS1_DIMMA# <11>
M_ODT0 <11>
M_ODT1 <11>
DDR_A_DQS#[0..7] <11>
DDR_A_DQS[0..7] <11>
DDR_A_MA[0..15] <11>
DDR3_DRAMRST# <11,12>
DRAMRST_CNTRL_PCH <14>
DRAMRST_CNTRL <11>
DDR_B_D[0..63]<12>
DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>
DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_WE#<12>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
JCPU1D
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
AM5
SB_DQ[32]
AM6
SB_DQ[33]
AR3
SB_DQ[34]
AP3
SB_DQ[35]
AN3
SB_DQ[36]
AN2
SB_DQ[37]
AN1
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
AN9
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
AN8
SB_DQ[45]
AR6
SB_DQ[46]
AR5
SB_DQ[47]
AR9
SB_DQ[48]
AJ11
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
AH11
SB_DQ[52]
AR8
SB_DQ[53]
AJ12
SB_DQ[54]
AH12
SB_DQ[55]
AT11
SB_DQ[56]
AN14
SB_DQ[57]
AR14
SB_DQ[58]
AT14
SB_DQ[59]
AT12
SB_DQ[60]
AN15
SB_DQ[61]
AR15
SB_DQ[62]
AT15
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
AA10
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
Sandy Bridge_rPGA_Rev1p0
CONN@
M_CLK_DDR2
AE2
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
DDR SYSTEM MEMORY B
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_CLK_DDR#2
DDR_CKE2_DIMMB
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT2
M_ODT3
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
M_CLK_DDR2 <12>
M_CLK_DDR#2 <12>
DDR_CKE2_DIMMB <12>
M_CLK_DDR3 <12>
M_CLK_DDR#3 <12>
DDR_CKE3_DIMMB <12>
DDR_CS2_DIMMB# <12>
DDR_CS3_DIMMB# <12>
M_ODT2 <12>
M_ODT3 <12>
DDR_B_DQS#[0..7] <12>
DDR_B_DQS[0..7] <12>
DDR_B_MA[0..15] <12>
1
CC37
.047U_0402_16V7K
2
5
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/6) DDRIII
LA-8241P
1
7 56W ednesday, February 01, 2012
1.0
5
www.qdzbwx.com
4
3
2
1
www.qdzbwx.com
CFG Straps for Processor
D D
JCPU1E
L7
RSVD28
AG7
CFG0<6>
T85PAD~D @
T86PAD~D @
T87PAD~D @
T88PAD~D @
T89PAD~D @
T90PAD~D @
RC159
12
10K_0402_5%
CFG10<6>
CFG11<6>
CFG12<6>
CFG13<6>
CFG14<6>
CFG15<6>
1 2
+VCC_GFXCORE_AXG
@
RC79
50_0402_1%
1 2
12
@
RC84
1K_0402_1%
VCC_AXG_VAL_SENSE
VCC_VAL_SENSE
+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ
12
@
RC85
1K_0402_1%
+3VS
+VCC_CORE
@
RC80
50_0402_1%
C C
+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ
B B
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE
T19PAD~D @
T25PAD~D @
T26PAD~D @
T27PAD~D @
T28PAD~D @
T30PAD~D @
T32PAD~D @
T33PAD~D @
T34PAD~D @
T35PAD~D @ T36 PAD~D@
T37PAD~D @
T38PAD~D @
T39PAD~D @
T40PAD~D @
T41PAD~D @
T42PAD~D @
T43PAD~D @
T44PAD~D @
T45PAD~D @
H_VCCP_SEL
T49PAD~D @
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
Sandy Bridge_rPGA_Rev1p0
CONN@
RESERVED
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
VCC_DIE_SENSE
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
B1
KEY
T2 PAD~D@
T3 PAD~D@
T4 PAD~D@
T5 PAD~D@
T6 PAD~D@
T7 PAD~D@
T8 PAD~D@
T9 PAD~D@
T10 PAD~D@
T11 PAD~D@
T12 PAD~D@
T13 PAD~D@
T14 PAD~D@
T15 PAD~D@
T16 PAD~D@
T17 PAD~D@
T18 PAD~D@
PEG Static Lane Reversal - CFG2 is for the 16x
Display Port Presence Strap
T20 PAD~D@
T21 PAD~D@
T22 PAD~D@
T23 PAD~D@
T24 PAD~D@
T29 PAD~D@
T31 PAD~D@
CLK_RES_ITP <14>
CLK_RES_ITP# <14>
T46 PAD~D@
T47 PAD~D@
T48 PAD~D@
T50 PAD~D@
PCIE Port Bifurcation Straps
CFG[6:5]
CFG2
12
RC78
1K_0402_1%
1:(Default) Norm al Operation; L ane #
CFG2
definition match es socket pin m ap definition
0:Lane Reversed
*
CFG4
12
RC81
@
1K_0402_1%
1 : Disabled; No Physical Displ ay Port
*
CFG4
attached to Embe dded Display Po rt
0 : Enabled; An external Displa y Port device is
connected to the Embedded Displ ay Port
CFG6
CFG5
1K_0402_1%
RC87
12
12
RC86
@
1K_0402_1%
11: (Default) x1 6 - Device 1 fu nctions 1 and 2 disabled
10: x8, x8 - Dev ice 1 function 1 enabled ; func tion 2
*
disabled
01: Reserved - ( Device 1 functi on 1 disabled ; function
2 enabled)
00: x8,x4,x4 - D evice 1 functio ns 1 and 2 enabl ed
CFG7
12
RC89
@
1K_0402_1%
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE
@
RC90
50_0402_1%
A A
INTEL 12/28 reco mmand
dd RC120, RC121, RC122, RC123
to a
Please place as close as JCPU1
5
@
RC91
50_0402_1%
1 2
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
PEG DEFER TRAINING
1: (Default) PEG Train immediat ely
*
CFG7
following xxRESE TB de assertion
0: PEG Wait for BIOS for traini ng
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(4/6) RSVD,CFG
LA-8241P
8 56W ednesday, February 01, 2012
1
of
1.0
5
www.qdzbwx.com
4
3
2
1
www.qdzbwx.com
QC=94A
DC=53A
POWER
PEG AND DDR
CORE SUPPLY
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
8.5A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
VCCSENSE_R
AJ35
VSSSENSE_R
AJ34
B10
A10
RC111
10_0402_1%
+VCCP
130_0402_1%~D
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
12
12
RC95
RC95 close to CPU
RC94 43_0402_1%
RC92 0_0402_1%@
RC96 0_0402_1%@
RC98 0_0402_1%@
1 2
RC99 0_0402_1%@
1 2
RC108
12
10_0402_1%
1 2
1 2
1 2
+VCCP
VCCIO_SENSE <47>
+VCCP
12
+VCC_CORE
12
12
RC93
75_0402_5%
RC97
100_0402_1%
RC100
100_0402_1%
Place the PU
resistors close to CPU
VR_SVID_ALRT# <50>
VR_SVID_CLK <50>
VR_SVID_DAT <50>
VCCSENSE <50>
VSSSENSE <50>
JCPU1F
+VCC_CORE
AG35
D D
C C
B B
A A
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
Sandy Bridge_rPGA_Rev1p0
CONN@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(5/6) PWR,BYPASS
LA-8241P
9 56W ednesday, February 01, 2012
1
1.0
5
www.qdzbwx.com
4
3
2
1
+1.5V_CPU_VDDQ Source
+1.5V +1.5V_CPU_VDDQ
B+_BIAS+3VALW
12
RC102
100K_0402_5%
2
1
@
CC40
0.1U_0402_10V7K~D
2
+VCC_GFXCORE_AXG
10U_0805_4VAM~D
10U_0805_4VAM~D
@
1
1
CC61
2
2
RUN_ON_CPU1.5VS3#
61
QC5A
2N7002DW-7-F_SOT363-6
33A
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
@
CC62
330U_D2_2.5VM_R6M~D
1
CC57
+
2
JCPU1G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
1.2A
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
Sandy Bridge_rPGA_Rev1p0
CONN@
D D
RC104
@
SUSP#<24,27,28,46,47,48>
CPU1.5V_S3_GATE<24>
C C
B B
+1.8VS
RC109 0_0805_1%@
1 2
1 2
0_0402_5%
RC107
1 2
0_0402_5%
+1.8VS_VCCPLL
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_4VAM~D
1
1
1
2
CC56
CC55
CC54
2
2
12
RC101
100K_0402_5%
RUN_ON_CPU1.5VS3
3
QC5B
5
2N7002DW-7-F_SOT363-6
4
RUN_ON_CPU1.5VS3# <6,27>
POWER
VSSAXG_SENSE
SENSE
LINES
VREFMISC
GRAPHICS
DDR3 -1.5V RAILS
SA RAIL
1.8V RAIL
VAXG_SENSE
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
FC_C22
VCCSA_VID1
QC3
AO4728L_SO8~D
8
7
6
5
1
2
12
3
1
4
CC38
2
RC103
10U_0805_10V6K
+VCC_GFXCORE_AXG
1 2
@
RC114
1 2
10_0402_1%
1K_0402_5%
20K_0402_5%
RC126
1 2
RC129 1K_0402_5%
1 2
RC106 0_0402_5%@
3
12
2
0.1U_0603_50V_X7R
12
1
CC39
2
RC105
330K_0402_1%
RC113
1 2
10_0402_1%
VCC_AXG_SENSE
RC157 100_0402_1%
VSS_AXG_SENSE
AK35
AK34
+V_SM_VREF should
have 10 mil trace width
+V_SM_VREF_CNT +V_SM_VREF
AL1
5A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
10U_0805_4VAM~D
1
1
CC41
2
2
10U_0805_4VAM~D
1
CC49
2
VCCSA_VID0 <49>
VCCSA_VID1 <49>
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
CC43
CC44
CC42
2
2
10U_0805_4VAM~D
10U_0603_6.3V6M
10U_0805_4VAM~D
1
2
@
1
1
CC51
CC52
CC50
2
2
VCC_AXG_SENSE <50>
VSS_AXG_SENSE <50>
+1.5V_CPU_VDDQ
1
@
QC4
NTR4503NT1G_SOT23-3~D
RUN_ON_CPU1.5VS3
+1.5V_CPU_VDDQ
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
1
CC45
CC46
+
2
2
2
1
+
CC48
330U_D2_2VM_R6M~D
2
VCCSA_SENSE <49>
12
RC110
@
0_0402_5%
CC47
330U_D2_2VM_R6M~D
+VCCSA
+1.5V
12
@
1K_0402_5%
RC112
12
1K_0402_5%
@
RC116
@
JP10
1 2
PAD-OPEN 4x4m
J8 OPEN
+1.5V_CPU_VDDQ +1.5V
add CC181 , CC182, 4 caps ar e all pop.
foll
+1.5V
CC53 0.1U_0402_10V7K~D
12
CC58 0.1U_0402_10V7K~D
12
CC59 0.1U_0402_10V7K~D
12
CC60 0.1U_0402_10V7K~D
12
ow checklist 1.0 5/24
www.qdzbwx.com
JCPU1H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
Sandy Bridge_rPGA_Rev1p0
CONN@
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
2
Compal Electronics, Inc.
Title
PROCESSOR(6/6) PWR,VSS
Size Document Number Rev
LA-8241P
Date: Sheet of
1
10 56Wednesday, February 01, 2012
1.0
5
www.qdzbwx.com
+V_DDR_REFA
330U_SX_2VY~D
1
CD13
+
2
+V_DDR_REFA
CD14
DDR_A_DQS#[0..7]<7>
DDR_A_DQS[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_MA[0..15]<7>
D D
Layout Note:
Place near JDIMM1
+1.5V
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C C
+1.5V
10U_0603_6.3V6M
B B
+0.75VS
A A
CD4
CD3
1
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD7
CD8
1
1
2
2
Layout Note:
Place near JDIMM1.203,204
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD17
2
2
1U_0402_6.3V6K
CD5
1
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD10
CD9
1
1
2
2
1U_0402_6.3V6K
1
1
CD19
CD18
2
2
+1.5V
12
12
All VREF traces should
have 10 mil trace width
CD6
10U_0603_6.3V6M
10U_0603_6.3V6M
CD12
CD11
1
1
2
2
1U_0402_6.3V6K
CD20
RD1
1K_0402_1%
RD3
1K_0402_1%
@
1
2
4
+1.5V
1
CD2
2
2.2U_0603_6.3V6K
CD22
1
2
+V_DDR_REFA
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
1 2
RD6 10K_0 402_5%
1 2
RD7 10K_0 402_5%
+0.75VS
0.1U_0402_16V7K
2.2U_0603_6.3V6K
1
CD1
2
DDR_CKE0_DIMMA<7> DDR_CKE1_DIMMA <7>
DDR_A_BS2<7>
M_CLK_DDR0<7>
M_CLK_DDR#0<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1_DIMMA#<7>
+3VS
0.1U_0402_16V7K
CD21
1
2
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
BELLW_80001-5021
CONN
@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
A15
A14
A11
S0#
A7
A6
A4
A2
A0
G2
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
+1.5V
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PCH_SMBDATA
PCH_SMBCLK
+0.75VS
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
M_ODT0 <7>
M_ODT1 <7>
PCH_SMBDATA <6,12,14,28,29,32>
PCH_SMBCLK <6,12,14,28,29,32>
+VREF_CA
2.2U_0603_6.3V6K
2
www.qdzbwx.com
DDR3_DRAMRST# <7,12>
+1.5V
12
RD4
1K_0402_1%
0.1U_0402_16V7K
1
1
CD15
2
2
12
RD5
1K_0402_1%
CD16
RD8 0_0402_5%@
M3
+SA_DIMM_VREFDQ
DRAMRST_CNTRL<7>
DRAMRST_CNTRL
RD9 0_0402_5%@
+SB_DIMM_VREFDQ
DRAMRST_CNTRL
1 2
S
G
2
1 2
S
G
2
1
QD1
D
BSS138_NL_SOT23-3
13
QD2
D
BSS138_NL_SOT23-3
13
+V_DDR_REFA
+V_DDR_REFB
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
DDRIII DIMMA
LA-8241P
1
11 56Wednesday, February 01, 2012
1.0
5
www.qdzbwx.com
+1.5V
12
D D
C C
B B
A A
DDR_B_DQS#[0..7]<7>
DDR_B_DQS[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_MA[0..15]<7>
+1.5V
1U_0402_6.3V6K
1U_0402_6.3V6K
CD28
1
1
2
2
+1.5V
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD32
CD33
1
2
Layout Note:
Place near JDIMMB.203,204
+0.75VS
1
1
2
2
1U_0402_6.3V6K
1
1
CD42
2
2
Layout Note:
Place near JDIMMB
1U_0402_6.3V6K
1U_0402_6.3V6K
CD29
CD30
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD34
CD35
1
1
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD44
CD43
2
12
CD31
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD37
CD36
1
2
1U_0402_6.3V6K
1
CD45
2
@
330U_SX_2VY~D
@
1
CD39
CD38
1
+
2
2
RD15
1K_0402_1%
RD16
1K_0402_1%
4
+V_DDR_REFB
+V_DDR_REFB
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
All VREF traces should
have 10 mil trace width
+3VS
10K_0402_5%
2.2U_0603_6.3V6K
RD19
3
+1.5V
1
2
CD26
12
+V_DDR_REFB
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
0.1U_0402_16V7K
CD46
1
2
2.2U_0603_6.3V6K
+0.75VS
1
2
CD47
0.1U_0402_16V7K
1
CD27
2
DDR_CKE2_DIMMB<7>
DDR_B_BS2<7>
M_CLK_DDR2<7>
M_CLK_DDR#2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<7>
+3VS
12
10K_0402_5%
RD20
JDIMM2
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
BELLW_80001-1021
CONN@
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
S0#
116
118
120
122
NC
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
2
+1.5V
www.qdzbwx.com
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31DDR_B_D27
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PCH_SMBDATA
PCH_SMBCLK
+0.75VS
DDR3_DRAMRST# <7,11>
DDR_CKE3_DIMMB <7>
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <7>
M_ODT2 <7>
M_ODT3 <7>
+VREF_CB
2.2U_0603_6.3V6K
1
2
PCH_SMBDATA <6,11,14,28,29,32>
PCH_SMBCLK <6,11,14,28,29,32>
RD17
1K_0402_1%
0.1U_0402_16V7K
1
CD40
CD41
2
+1.5V
12
12
RD18
1K_0402_1%
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
DDRIII DIMMB
LA-8241P
1
12 56Wednesday, February 01, 2012
1.0
5
www.qdzbwx.com
PCH_RTCX1
ME_EN<24>
12
RH19
@
200_0402_5%
12
RH25
100_0402_1%
PCH_RTCX2
1
CH4
18P_0402_50V8J
2
1 2
RH5 33_0402_5%
1 2
RH6 33_0402_5%
1 2
RH7 33_0402_5%
1 2
RH8 1M_0402_5%
12
12
PCH_RTCX1_R<31>
+RTCVCC
+RTCVCC
1U_0603_10V6K
1 2
RH3 20K_0402_5%
1 2
RH4 20K_0402_5%
1U_0603_10V6K
HDA_BIT_CLK
HDA_RST#
HDA_SYNC_R SATA_PTX_DRX_P1
1 2
RH11 1K_0402_1%
1 2
RH15 33_0402_5%
RH20
@
200_0402_5%
RH26
100_0402_1%
RH30 0_0402_5%
RH2
1 2
1
CH5
2
1
CH6
2
+5VS
G
2
13
D
S
QH1BSS138_SOT23
@
1 2
RH9 0_0402_5%
HDA_SDOUT
HDA_SDOUT
12
SHORT PADS
12
SHORT PADS
CLP1 & CLP2 place near DIMM
HDA_SYNC
close to YH1
1 2
GCLK@
1M_0402_5%
CMOS
CLRP1
CLRP2
ME CMOS
HDA_SPKR<30>
HDA_SDIN0<30>
PCH_JTAG_TCK<6>
PCH_JTAG_TMS<6>
PCH_JTAG_TDI<6>
PCH_JTAG_TDO<6>
PCH_RTCX1
SM_INTRUDER#
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDIN0
HDA_SDOUT
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_SI
PCH_SPI_SO
1 2
RH1 10M_0402_5%
YH1
1 2
32.768KHZ_12.5PF_9H03200019
18P_0402_50V8J
1
CH3
2
D D
keep away hot s pot
HDA_BITCLK_AUDIO<30>
HDA_RST_AUDIO#<30>
HDA_SYNC_AUDIO<30>
C C
HDA_SDOUT_AUDIO<30>
+3V_PCH +3V_PCH+3V_PCH
12
RH18
@
200_0402_5%
PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS
12
RH24
100_0402_1%
B B
4
@
HDA_SDOUT
12
CH1 10P_0402_50V8J
@
HDA_BIT_CLK
12
CH2 10P_0402_50V8J
Reserve for RF please close t o UH1
UH1A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST # / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
BD82HM77 QPRG C1 BGA 989P PCH
SA00005AG1L
RTCIHDA
JTAG
SPI
LPC
FWH4 / LFRAME#
LDRQ1# / GPIO23
SATA
SATA0GP / GPIO21
SATA1GP / GPIO19
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
UH1
BD82HM77 QPRG C1 BGA 989P PCH
SA00005AG1L
LPC_AD0
C38
LPC_AD1
A38
LPC_AD2
B37
LPC_AD3
C37
LPC_FRAME#
D36
E36
K36
SERIRQ
V5
AM3
AM1
SATA_PTX_DRX_N0
AP7
SATA_PTX_DRX_P0
AP5
AM10
AM8
SATA_PTX_DRX_N1
AP11
AP10
AD7
AD5
SATA_PTX_DRX_N2
AH5
SATA_PTX_DRX_P2
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
SATA_COMP
Y10
AB12
SATA3_COMP
AB13
RBIAS_SATA3
AH1
PCH_SATALED#
P3
HDD_DET#_R
V14
BBS_BIT0_R
P1
3
@
LPC_AD0 <24>
LPC_AD1 <24>
LPC_AD2 <24>
LPC_AD3 <24>
LPC_FRAME# <24>
SERIRQ <24>
CH7 0.01U_0402_16V7K
1 2
CH8 0.01U_0402_16V7K
1 2
CH18 0.01U_0402_16V7K
1 2
CH17 0.01U_0402_16V7K
1 2
CH9 0.01U_0402_16V7K
1 2
CH10 0.01U_0402_16V7K
1 2
1 2
RH21 37.4_0402_1%
1 2
RH22 49.9_0402_1%
1 2
RH28 750_0402_1%~D
RH268 0_0402_5%
1 2
RH29
+1.05VS_VCC_SATA
+1.05VS_SATA3
PCH_SATALED# <32>
10K_0402_5%
12
HDD_DET#
+3VS
SATA_PRX_DTX_N0 <29>
SATA_PRX_DTX_P0 <29>
SATA_PTX_DRX_N0_C <29>
SATA_PTX_DRX_P0_C <29>
SATA_PRX_DTX_N1 <32>
SATA_PRX_DTX_P1 <32>
SATA_PTX_DRX_N1_C <32>
SATA_PTX_DRX_P1_C <32>
SATA_PRX_DTX_N2 <29>
SATA_PRX_DTX_P2 <29>
SATA_PTX_DRX_N2_C <29>
SATA_PTX_DRX_P2_C <29>
HDD_DET# <29>
2
www.qdzbwx.com
HDA_SYNC
+3VLP
SERIRQ
HDD_DET#
PCH_SATALED#PCH_INTVRMEN
HDA_SPKR
HDA_SDOUT
RH32 1K_0402_5%
W=20mils
RH23 1K_0402_5%@
*
RTC Battery
+CHGRTC
W=20mils
330K_0402_5%
PCH_INTVRMEN
RH13
RH16
@
INTVRMEN
H：Integrated VRM enable
*
L：Integrated VRM disable
HDA_SDO
ME debug mode , this signal has a weak internal PD
L=>
s
Descriptor will be in effect (default)
330K_0402_5%
ecurity measures defined in the Flash
+RTCVCC
12
12
H=>Flash Descriptor Security will be overridden
HDA_SYNC
HDD
mSATA
This signal has a weak intern al pull-down
On Die PLL VR is supplied by
1.5V when smapl ed high
1.8V when sampl ed low
Needs to be pul led High for H uron River plat from
ODD
JP12
2
+CHGRTC
112
JUMP_43X39
1
RH10 10K_0402_5%
RH12 10K_0402_5%
RH14 10K_0402_5%
RH17 1K_0402_5%@
*
Low = Disabled
High = Enabled
12
12
12
12
12
LOW=Default
HIGH=No Reboot
12
+3V_PCH
+3V_PCH
+RTCBATT
RH34
1K_0402_5%
1 2
W=20mils
2
3
DH1
BAT54CW_SOT323-3
1
1
CH12
1U_0603_10V6K
2
+RTCVCC
+3VS
+3VS
HOLD#
SCLK
+3V_PCH
0.1U_0402_16V7K
1
CH11
2
8
VCC
PCH_SPI_HOLD#PCH_SPI_SO_R
SI
7
6
5
PCH_SPI_CLK_R
PCH_SPI_SI_R
RH27 33_0402_5%
RH39 33_0402_5%
1
CH99
@
10P_0402_50V8J
2
PCH_SPI_CLK
12
PCH_SPI_SI
12
3
PCH_SPI_CS0#
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
RH264 0_0402_5%
1 2
RH265 33_0402_5%
+3V_PCH
SPI ROM FOR ME
yte )
@
RH263
3.3K_0402_5%
12
2012/01/17 2013/01/16
( 4MB
PCH_SPI_CS0#_R
1 2
PCH_SPI_SO_LPCH_SPI_SO
Compal Secret Data
Deciphered Date
2
UH6
1
CS#
2
3
4
VCC
SO/SIO1
HOLD#
WP#
SCLK
GND
SI/SIO0
EN25Q32B-104HIP_SO8
EON EN25Q32B-104HIP_SO8
PCH_JTAG_TCK
+3V_PCH
1 2
RH38 3.3K_0402_5%
1 2
RH40 3.3K_0402_5%
1 2
RH35 51_0402_5%
PCH_SPI_WP#
PCH_SPI_HOLD#
NEC flash issue .
+3V_PCH
RH262
3.3K_0402_5%
PCH_SPI_SO
@
1 2
RH36 0_0402_5%
1 2
RH37 33_0402_5%
@
RH33
3.3K_0402_5%
12
+3V_PCH
SPI ROM FOR WIN8( 2MByte )
1 2
PCH_SPI_CS1#_RPCH_SPI_CS1#
PCH_SPI_WP#
UH2
1
CS#
2
SO
3
WP#
4
GND
EN25QH16-104HIP_SO8
EON EN25QH16-104HIP_SO8
A A
5
4
+3V_PCH
0.1U_0402_16V7K
1
CH98
2
8
PCH_SPI_HOLD#
7
PCH_SPI_CLK_L
6
PCH_SPI_SI_L PCH_SPI_SI
5
RH266 33_0402_5%
12
12
RH267 33_0402_5%
Title
PCH (1/8) SATA,HDA,SPI, LPC
Size Document Number Rev
LA-8241P
Date: Sheet of
PCH_SPI_CLKPCH_SPI_WP#
Compal Electronics, Inc.
1
13 56Wednesday, February 01, 2012
1.0
5
www.qdzbwx.com
PCIE_PRX_LANTX_N1<32>
10/100/1G LAN --->
WLAN (Mini Card 1)--->
D D
Express Card --->
C C
10/100/1G LAN --->
WLAN (Mini Card 1)--->
Express Card --->
PCIE_PRX_LANTX_P1<32>
PCIE_PTX_LANRX_N1<32>
PCIE_PTX_LANRX_P1<32>
PCIE_PRX_WLANTX_N2<32>
PCIE_PRX_WLANTX_P2<32>
PCIE_PTX_WLANRX_N2<32>
PCIE_PTX_WLANRX_P2<32>
PCIE_PRX_EXPTX_N3<28>
PCIE_PRX_EXPTX_P3<28>
PCIE_PTX_EXPRX_N3<28>
PCIE_PTX_EXPRX_P3<28>
CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>
LAN_CLKREQ#<32>
CLK_PCIE_WLAN#<32>
CLK_PCIE_WLAN<32>
WLAN_CLKREQ#<32>
CLK_PCIE_EXP#<28>
CLK_PCIE_EXP<28>
EXPCLK_REQ#<28>
CH19 0.1U_0402_10V7K~D
1 2
CH20 0.1U_0402_10V7K~D
1 2
CH21 0.1U_0402_10V7K~D
1 2
CH22 0.1U_0402_10V7K~D
1 2
CH15 0.1U_0402_10V7K~D
1 2
CH16 0.1U_0402_10V7K~D
1 2
RH67 0_0402_5%
RH68 0_0402_5%
RH69 10K_0402_5%
+3V_PCH
RH75 0_0402_5%
RH76 0_0402_5%
RH77 10K_0402_5%
+3VS
RH79 0_0402_5%
RH80 0_0402_5%
RH81 10K_0402_5%
+3VS
+3V_PCH
RH74 10K_0402_5%
*PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2
B B
XTAL25_IN
CH28
XTAL25_OUT
CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>
27P_0402_50V8J
1
2
5
CLK_RES_ITP#<8>
CLK_RES_ITP<8>
PCH_X1<31>
12
RH891M_0402_5%
3
27P_0402_50V8J
1
CH27
A A
OSC1OSC
2
GND2GND
YH2
4
25MHZ_20PF_FSX3M-25.M20FDO
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
CLK_CPU_ITP#
CLK_CPU_ITP
RH41 0_0402_5%
RH66 10K_0402_5%
RH83 10K_0402_5%
RH84 10K_0402_5%
RH88 10K_0402_5%
RH90 10K_0402_5%
RH91 0_0402_5%
RH92 0_0402_5%
RH93 0_0402_5%@
RH94 0_0402_5%@
close to YH2
1 2
GCLK@
XTAL25_IN
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
12
12
12
12
12
12
12
12
12
4
PCIE_PRX_LANTX_N1
PCIE_PRX_LANTX_P1
PCIE_PTX_LANRX_N1_C
PCIE_PTX_LANRX_P1_C
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2_C
PCIE_PTX_WLANRX_P2_C
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3_C
PCIE_PTX_EXPRX_P3_C
4
UH1B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PCIE_LAN#
PCIE_LAN
LAN_CLKREQ#
PCIE_WLAN#
PCIE_WLAN
WLAN_CLKREQ#
PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#
GPIO25
GPIO26
GPIO44
GPIO56
GPIO45
GPIO46
CLK_BCLK_ITP#
CLK_BCLK_ITP
CLK_BCLK_ITP
CLK_PCH_14M
CLK_PCI_LPBACK
Reserve for EMI please close t o
UH1
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
BD82HM77 QPRG C1 BGA 989P PCH
@
RH63
12
33_0402_5%
@
RH65
12
33_0402_5%
@
CH25
1 2
22P_0402_50V8J~D
@
CH26
1 2
22P_0402_50V8J~D
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
CLOCKS
3
2
www.qdzbwx.com
SMBALERT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
CLKIN_DMI_N
CLKIN_DMI_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
Issued Date
E12
SMBCLK
H14
SMBDATA
C9
DRAMRST_CNTRL_PCH
A12
SML0CLK
C8
SML0DATA
G12
PCH_HOT#
C13
SML1CLK
E14
SML1DATA
M16
M7
T11
No support iAMT
P10
PEG_A_CLKRQ#
M10
CLK_PEG_VGA#
AB37
CLK_PEG_VGA
AB38
CLK_CPU_DMI#
AV22
CLK_CPU_DMI
AU22
AM12
AM13
CLKIN_DMI#
BF18
CLKIN_DMI
BE18
CLKIN_DMI2#
BJ30
CLKIN_DMI2
BG30
CLKIN_DOT96#
G24
CLKIN_DOT96
E24
CLKIN_SATA#
AK7
CLKIN_SATA
AK5
CLK_PCH_14M
K45
CLK_PCI_LPBACK
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
CLK_FLEX0
K43
CLK_14M_R
F47
CLK_LAN_25M_R
H47
DGPU_PRSNT#
K49
MEMORY
DRAMRST_CNTRL_PCH <7>
PCH_HOT# <24>
Total device
RH125
1 2
22_0402_5%
RH270 22_0402_5%
RH269 10K_0402_5%
RH261
10K_0402_5%DIS@
1 2
2012/01/17 2013/01/16
20090512
add double mosfet prevent
ATI M92 electric leakage
+3V_PCH
RH64
10K_0402_5%
1 2
CLK_PEG_VGA# <34>
CLK_PEG_VGA <34>
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
CLK_PCI_LPBACK <16>
1 2
RH85 90.9_0402_1%
T53 PAD~D@
T54 PAD~D@
@
12
12
+3VS
UMA@
LAN_X1<31>
Compal Secret Data
Deciphered Date
PEG_A_CLKRQ# <35>
SMBCLK
DMN66D0LDW-7_SOT363-6
SMBDATA
+1.05VS_VCCDIFFCLKN
CLK_LAN_25M <32>
close to RH270
1 2
RH31 0_0402_5%
GCLK@
2
6 1
1 2
0_0402_5%
CLK_LAN_25M
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
CLKIN_PCILOOPBACK
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
QH2A
RH78
@
3
DMN66D0LDW-7_SOT363-6
QH2B
RH82
@
1 2
0_0402_5%
SML1CLK
SML1DATA
1
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
SMBALERT#
PCH_HOT#
DRAMRST_CNTRL_PCH
CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M
If use extenal CLK gen, pleas e place close to CLK gen
else, please p lace close to P CH
+3VS
+3VS
RH71
2.2K_0402_5%
5
1 2
4
+3V_PCH
2
61
DMN66D0LDW-7_SOT363-6
QH3A
4
DMN66D0LDW-7_SOT363-6
QH3B
Title
PCH (2/8) PCIE, SMBUS, CLK
Size Document Number Rev
LA-8241P
Date: Sheet of
1 2
RH45 2.2K_0402_5%
1 2
RH46 2.2K_0402_5%
1 2
RH47 2.2K_0402_5%
1 2
RH49 2.2K_0402_5%
1 2
RH50 2.2K_0402_5%
1 2
RH51 2.2K_0402_5%
1 2
RH52 10K_0402_5%
1 2
RH86 10K_0402_5%
1 2
RH53 1K_0402_5%
RH54 10K_0402_5%
1 2
RH55 10K_0402_5%
1 2
RH56 10K_0402_5%
1 2
RH57 10K_0402_5%
1 2
RH58 10K_0402_5%
1 2
RH59 10K_0402_5%
1 2
RH60 10K_0402_5%
1 2
RH61 10K_0402_5%
1 2
RH62 10K_0402_5%
1 2
RH72
2.2K_0402_5%
1 2
PCH_SMBCLK <6,11,12,28,29,32>
PCH_SMBDATA <6,11,12,28,29,32>
5
3
Compal Electronics, Inc.
1
+3V_PCH
PCH_SMLCLK <24>
PCH_SMLDATA <24>
1.0
14 56Wednesday, February 01, 2012
5
Compal Electronics, Inc.
www.qdzbwx.com
UH1C
DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>
DMI_CRX_PTX_N0<5>
D D
XDP_DBRESET#<6>
C C
PM_DRAM_PWRGD<6>
GPIO72
B B
RI#
PCIE_WAKE#
AC_PRESENT_R
SUSWARN#
WAKE#
EC_RSMRST#
A A
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
+1.05VS
SYS_PWROK
PCH_PWROK<6,24>
EC_RSMRST#<24>
PBTN_OUT#< 6,24>
ACIN<24,35, 43,44>
RH116 10K_0402_5%
1 2
RH117 10K_0402_5%
1 2
RH118 10K_0402_5%@
1 2
RH121 200K_0402_5%
1 2
RH124 10K_0402_5%
1 2
RH126 10K_0402_5%
1 2
RH127 10K_0402_5%
1 2
PCH_PWROK<6,24>
VGATE<6,50>
RH99 49.9_0402_1%
RH100 750_0 402_1%~D
4mil width and place
within 500mil of the PCH
T57PAD~D
PCH_PWROK
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
1 2
1 2
RH104 0_0402_5%
RH105 0_0402_5%
RH106 0_0402_5%
RH108 0_040 2_5%
RH110 0_040 2_5%
DMI_IRCOMP
RBIAS_CPY
XDP_DBRESET#
1 2
1 2
1 2
PM_DRAM_PWRGD
PCH_RSMRST#_R
1 2
1 2
DH4
1 2
RB751V-40_SOD323-2
GPIO72
+3V_PCH
+3VS
1
CH30
0.1U_0402_16V7K
2
1
IN1
2
IN2
SYS_PWROK_R
SUSWARN#
AC_PRESENT_R
RI#
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPW RDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
BD82HM77 QPRG C1 BGA 989P PCH
DSWODVREN
DSWODVREN
DSWODVREN - On Die DSW VR Enable
*
5
UH3
VCC
SYS_PWROK
4
OUT
GND
MC74VHC1G08DFT2G_SC70-5
3
RH119 330K_0402_5%
RH122 330K_0402_5%@
H：Enable
L：Disable
SYS_PWROK <6>
4
FDI_CTX_PRX_N0
BJ14
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
DMI
System Power Management
FDI_RXP6
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
Check EC for S3 S4 LED
12
12
+RTCVCC
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
DSWODVREN
WAKE#
PM_CLKRUN#
SUS_STAT#
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PM_SLP_SUS#
H_PM_SYNC
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
1 2
RH107 0_0402_5%
FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>
FDI_CTX_PRX_P0 < 5>
FDI_CTX_PRX_P1 < 5>
FDI_CTX_PRX_P2 < 5>
FDI_CTX_PRX_P3 < 5>
FDI_CTX_PRX_P4 < 5>
FDI_CTX_PRX_P5 < 5>
FDI_CTX_PRX_P6 < 5>
FDI_CTX_PRX_P7 < 5>
FDI_INT <5>
FDI_FSYNC0 <5>
FDI_FSYNC1 <5>
FDI_LSYNC0 <5>
FDI_LSYNC1 <5>
RH128 0_0402_5%
1 2
@
RH103 0_0402_5%
12
If not using integrated
LAN,signal may be left as NC.
PCH_RSMRST#_RPCH_DPWROK
PCIE_WAKE# <24,28,32>
T58 PAD~D
SUSCLK_R <24>
PM_SLP_S5# <24>
PM_SLP_S4# <24>
PM_SLP_S3# <24,28>
T59 PAD~D
H_PM_SYNC <6>
SUSCLK
Reserve for RF please close to UH1
3
PCH_ENVDD<22>
VGA_PWM<22>
LVDS_DDC_CLK<2 2>
LVDS_DDC_DATA<22>
LVDS_ACLK-< 22>
LVDS_ACLK+<22>
LVDS_A0-<22>
LVDS_A1-<22>
LVDS_A2-<22>
LVDS_A0+<22>
LVDS_A1+<22>
LVDS_A2+<22>
LVDS_BCLK-< 22>
LVDS_BCLK+<22>
LVDS_B0-<22>
LVDS_B1-<22>
LVDS_B2-<22>
LVDS_B0+<22>
LVDS_B1+<22>
LVDS_B2+<22>
CRT_B<21>
CRT_G<21>
CRT_R<21>
CRT_DDC_CLK<21>
CRT_DDC_DATA<21>
CRT_HSYNC< 21>
CRT_VSYNC<21>
Can be left NC when IAMT is
not support on the platfrom
CH29
12
@
10P_0402_50V8J
+3VS
1 2
RH133 2.2K_0402_5%
1 2
RH135 2.2K_0402_5%
1 2
RH136 8.2K_0402_5%@
1 2
RH137 2.2K_0402_5%
1 2
RH138 2.2K_0402_5%
1 2
RH233 2.2K_0402_5%
1 2
RH234 2.2K_0402_5%
@
1 2
RH238 2.2K_0402_5%
@
1 2
RH239 2.2K_0402_5%
ENBKL<24>
T56PAD~D
RH230 33_0402_5%
RH202 33_0402_5%
1K_0402_0.5%
ENBKL
PCH_ENVDD
LVDS_DDC_CLK
LVDS_DDC_DATA
CTRL_CLK
CTRL_DATA
LVDS_IBG
LVDS_ACLKLVDS_ACLK+
LVDS_A0LVDS_A1LVDS_A2-
LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_BCLKLVDS_BCLK+
LVDS_B0LVDS_B1LVDS_B2-
LVDS_B0+
LVDS_B1+
LVDS_B2+
CRT_B
CRT_G
CRT_R
CRT_DDC_CLK
CRT_DDC_DATA
1 2
1 2
12
RH115
CTRL_CLK
CTRL_DATA
PM_CLKRUN#
LVDS_DDC_CLK
LVDS_DDC_DATA
PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA
CRT_DDC_CLK
CRT_DDC_DATA
2
www.qdzbwx.com
UH1D
HSYNC
VSYNC
CRT_IREF
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
BD82HM77 QPRG C1 BGA 989P PCH
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
HDMI
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
mDP
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
CRT
DMC
AP43
AP45
AM42
AM40
AP39
SDVO_INTN
AP40
SDVO_INTP
P38
M39
AT49
DDPB_AUXN
AT47
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
1 2
RH120 10K_0402_5%
1 2
RH123 2.37K_0402_1 %
1 2
RH132 100K_0402_5 %
1 2
RH134 100K_0402_5 %
1 2
RH235 150_0402_1 %
1 2
RH236 150_0402_1 %
1 2
RH237 150_0402_1 %
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
HDMI_DET
HDMI_A2N_VGA
HDMI_A2P_VGA
HDMI_A1N_VGA
HDMI_A1P_VGA
HDMI_A0N_VGA
HDMI_A0P_VGA
HDMI_A3N_VGA
HDMI_A3P_VGA
PM_CLKRUN#
LVDS_IBG
PCH_ENVDD
ENBKL
CRT_B
CRT_G
CRT_R
1
PCH_SDVO_CTRLCLK <23>
PCH_SDVO_CTRLDATA <23>
HDMI_DET < 23>
HDMI_A2N_VGA <23>
HDMI_A2P_VGA <23>
HDMI_A1N_VGA <23>
HDMI_A1P_VGA <23>
HDMI_A0N_VGA <23>
HDMI_A0P_VGA <23>
HDMI_A3N_VGA <23>
HDMI_A3P_VGA <23>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet of
Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM,GFX,DP
LA-8241P
1
15 56Wednesday, February 01, 2012
1.0
5
www.qdzbwx.com
+3VS
D D
C C
CH31
CLK_PCI1
12
@
10P_0402_50V8J
RPH1
8.2K_0804_8P4R_5%
RPH2
8.2K_0804_8P4R_5%
RPH3
8.2K_0804_8P4R_5%
RH14010K_0402_5%
WL_OFF#
18
PCI_PIRQB#
27
PCI_PIRQD#
36
PCI_PIRQC#
45
GPIO51
18
GPIO52
27
PXS_PWREN
36
FFS_INT1
45
GPIO5
18
PCI_PIRQA#
27
GPIO4
36
ODD_DA#
45
DGPU_HOLD_RST#
12
Reserve for RF p lease close to PCH
B B
CLK_PCI_LPBACK<14>
CLK_PCI_LPC<24>
CLK_PCI_LPBACK
CLK_PCI_LPC
4
USB3RN1<33>
USB3RN2<33>
USB3RN3<32>
USB3RN4<32>
USB3RP1<33>
USB3RP2<33>
USB3RP3<32>
USB3RP4<32>
USB3TN1<3 3>
USB3TN2<3 3>
USB3TN3<3 2>
USB3TN4<3 2>
USB3TP1<33>
USB3TP2<33>
USB3TP3<32>
USB3TP4<32>
DGPU_HOLD_RST#<34>
PXS_PWREN<36,52>
WL_OFF#<32>
FFS_INT1<29>
ODD_DA#<29>
T60PAD~D @
PCH_PLTRST#<34>
RH144 22_0402_5%
RH145 22_0402_5%
1 2
12
T61PAD~D @
T62PAD~D @
T63PAD~D @
USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
DGPU_HOLD_RST#
GPIO52
PXS_PWREN
GPIO51
WL_OFF#
FFS_INT1
ODD_DA#
GPIO4
GPIO5
PCH_PLTRST#
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4
UH1E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ32
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG32
TP32
AV26
TP33
BB26
TP34
AU28
TP35
AY30
TP36
AU26
TP37
AY26
TP38
AV28
TP39
AW30
TP40
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
BD82HM77 QPRG C1 BGA 989P PCH
RSVD
PCI
USB
3
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC6# / GPIO10
OC7# / GPIO14
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC5# / GPIO9
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
Intel Anti-Theft Techonlogy
High=Endabled
NV_ALE
Low=Disable(floating)
NV_ALE
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N8
USB20_P8
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
RH139 1K_0402_5%@
USB20_N0 <33>
USB20_P0 <33>
USB20_N1 <33>
USB20_P1 <33>
USB20_N2 <32>
USB20_P2 <32>
USB20_N3 <32>
USB20_P3 <32>
USB20_N4 <32>
USB20_P4 <32>
USB20_N5 <32>
USB20_P5 <32>
USB20_N8 <32>
USB20_P8 <32>
USB20_N10 <32>
USB20_P10 <32>
USB20_N11 <28>
USB20_P11 <28>
USB20_N12 <22>
USB20_P12 <22>
Within 500 mils
1 2
RH143 22.6_0402_ 1%
2
www.qdzbwx.com
*
+1.8VS
1 2
USB Conn 1
USB Conn 2 (with PWR Share)
USB Conn 3
USB Conn 4
Mini Card-1 (WLAN)
Mini Card-2 (mSATA)
Finger Print
Card Reader
Express Card
Camera
RPH4
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%
RPH5
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%
USB_OC0# <33>
USB_OC1# <33>
USB_OC2# <32>
USB_OC3# <32>
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
1
+3V_PCH
+3VS
@
RH150
10K_0402_5%
PLT_RST#<6,24,28,32>
A A
5
1 2
12
RH155
100K_0402_5%
@
1 2
RH149 0_0402_5%
+3VS
5
UH5
1
P
IN1
4
O
2
IN2
G
SN74AHC1G08DCKR_SC70-5
3
4
@
1 2
PCH_PLTRST#
RH157
10K_0402_5%
1 2
CH101
0.1U_0402_25V6K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2012/01/17 2013/01/16
Compal Secret Data
Deciphered Date
2
Date: Sheet of
Title
Size Document Number Rev
Compal Electronics, Inc.
PCH (4/8) PCI, USB, NVRAM
LA-8241P
1
16 56Wednesday, February 01, 2012
1.0
5
www.qdzbwx.com
4
3
2
1
www.qdzbwx.com
UH1F
+3V_PCH
1K_0402_5%
D D
10K_0402_5%
High: CRT Plugged
CRT_DET#<21>
+3VS
C C
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
H：On-Die voltage r egulator enable
*
L：On-Die PLL Volta ge Regulator di sable
PCH_GPIO37
FDI TERMINATION VOLTAGE OVERRIDE
LOW - Tx, Rx ter minated
*
to same voltage
(DC Coupling Mod e)
+3VS
B B
A A
RH168 1K_0402_5%@
RH169
PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16
Please refer to Huron River Debug Board DG 0.5
1 2
RH165 1K_0402_5%@
1 2
1 2
RH173 10K_0402_5%@
12
10K_0402_5%
2
G
QH4
SSM3K7002F_SC59-3
RH16410K_0402_5%
PCH_GPIO28
PCH_GPIO37
PCH_GPIO37
PCH_GPIO27
5
PCH_LID_SW_IN#
12
RH240
PCH_GPIO28
12
RH241
+3VS
RH160
10K_0402_5%
1 2
CRT_DET
13
D
S
GPIO1 PCH_GPIO37
12
EC_LID_OUT#<24>
EC_SCI#< 24>
EC_SMI#<24>
VGA_PWRGD<36,52>
KB_DET#<26>
BT_ON#<32>
ODD_DETECT#<29>
FFS_INT2<29>
HDD_DETECT#<32>
4
1 2
CRT_DET
GPIO1
GPIO6
EC_SCI#
EC_SMI#
PCH_LID_SW_IN#EC_LID_OUT#
RH730_0402_5%
GPIO16
VGA_PWRGD
PCH_GPIO22
KB_DET#
PCH_GPIO27
PCH_GPIO28
BT_ON#
GPIO35
ODD_DETECT#
PCH_GPIO38
PCH_GPIO39
FFS_INT2
GPIO49
HDD_DETECT#
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
BD82HM77 QPRG C1 BGA 989P PCH
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
PROCPWRGD
GPIO
CPU/MISC
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
NCTF
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
2012/01/17 2013/01/16
A20GATE
PECI
RCIN#
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
ODD_EN#
GPIO69
PCH_PECI_R
KB_RST#
H_THERMTRIP#_C
INIT3_3V#
NV_CLE
ODD_EN#
HDD_DETECT#
EC_SMI#
1 2
KB_RST# <24>
H_CPUPWRGD <6>
1 2
Compal Secret Data
Deciphered Date
ODD_EN# <29>
T64 PAD~D@
@
RH1610_0402_5%
RH162390_0402_5%
Weak internal
PU,Do not pull l ow
NV_CLE
1 2
RH178
1 2
RH179
1 2
RH183
2
H_PECI <6,24>
H_THERMTRIP#
12
@
RH163
10K_0402_5%
DMI Termination Voltage
NV_CLE
CLOSE TO THE BRANCHING POINT
RH161 and RH162
Follow CRB FAB2 setting
10K_0402_5%
10K_0402_5%
10K_0402_5%
+3VS
RH159
10K_0402_5%
1 2
GATEA20 <24>
H_THERMTRIP# <6>
INIT3_3V
This signal has weak internal
PU, can't pull low
Set to Vcc when HIGH
Set to Vss when LOW
+1.8VS
12
RH166
2.2K_0402_5%
12
RH1671K_0402 _5%
+3V_PCH
H_SNB_IVB# <6>
CRT_DET#
ODD_DETECT#
GPIO16
BT_ON#
KB_RST#
VGA_PWRGD
PCH_GPIO22
GPIO35
GPIO49
PCH_GPIO38
PCH_GPIO39
GPIO6
Title
PCH (5/8) GPIO, CPU, MISC
Size Document Number Rev
LA-8241P
Date: Sheet
10K_0402_5%@
1 2
RH170
200K_0402_5%
1 2
RH171
10K_0402_5%
1 2
RH172
8.2K_0402_5%
1 2
RH174
10K_0402_5%
1 2
RH175
10K_0402_5%
1 2
RH242
10K_0402_5%
1 2
RH176
10K_0402_5%
1 2
RH177
10K_0402_5%
1 2
RH180
10K_0402_5%
1 2
RH181
10K_0402_5%
1 2
RH182
10K_0402_5%
1 2
RH184
Compal Electronics, Inc.
1
17 56Wednesday, February 01, 2012
+3VS
1.0
of
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