COMPAL LA-8133P Schematics
1
2
3
4
5
Compal Confidential
Model Name : QILE1 & QILE2
File Name : LA-8131P, LA-8133P
BOM P/N:
QILE1:
A A
4319GG39L01 : SMT MB A8131 QILE1 DIS-N13P
4319GG39L02 : SMT MB A8131 QILE1 DIS GPU-N13M
4319GG39L03 : SMT MB A8131 QILE1 UMA
QILE2:
4319GJ39L01 : SMT MB A8133 QILE2 DIS-N13P
4319GJ39L02 : SMT MB A8133 QILE2 DIS GPU-N13M
4319GJ39L03 : SMT MB A8133 QILE2 UMA
Compal Confidential
B B
M/B Schematics Document
Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
GPU nVIDIA N13M-GE1 / N13P-GL
C C
2012-01-11
REV:1.0
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-8133P
LA-8133P
LA-8133P
5
1 58Friday, January 13, 2012
1 58Friday, January 13, 2012
1 58Friday, January 13, 2012
1.0
1.0
1.0
ZZZ
ZZZ
LA8131P
DA_PCB
DA_PCB
DA80000QL00
DA80000QL00
A
nVIDIA N13M-GE1
B
C
D
E
DDR3*4
VRAM 256M*16/
1 1
128M*16/64M*16
nVIDIA N13P-GL
DDR3*8
PCI-E X16
VRAM 256M*16/
128M*16/64M*16
Page 24~32
Intel
Ivy Bridge
rPGA 989 Socket
37.5mm * 37.5mm
Memory Bus
Dual Channel
1.5V DDR3 1600MHz
DDR3-SO-DIMM X2
Page 11~12
HDMI Connector
Page 34
CRT Connector
Page 33
HDMI
RGB
FDI x8
(UMA)
100MHz
2.7GT/s
Intel
2 2
LVDS Connector
Page 32
Card Reader
Realtek RTS5229
cable
Page 36
Realtek
RTL8111F(Giga)
Page 40
RJ45 CONN
3 3
Page 40
cable
LVDS
PCI-E
SPI ROM
BIOS 8M+4M
Page 13
SPI
Panther Point
FCBGA 989
25mm*25mm
EC
ENE KBC9012
Page 41
HM76
Page 4~10
DMI x4
100MHz
5GB/s
Page 13~21
LPC BUS
TPM
Page 40
HD Audio
USB 2.0
USB 3.0
SATA
2Channel Speaker
Audio Codec
CX20671-21Z CODEC
Page 35
CMOS Camera
Digital MIC
Audio combo Jack
Page 32
USB PORT 2.0 x 1(charger)
Page 39
Finger Printer
UPEK TCS5DA6C0
Page 40
USB PORT 3.0 x 3
Page 37
Page 35
Page 35
Page 35
Sub-Board
Sub-Board
Sub-Board
Track Point
Page 39
G-Sensor
Page 36
SATA3.0 HDD CONN
Page 36
PCI Express
Mini card
Slot 1
WLAN/WiMAX/BT
Page 38
PCI Express
Mini card
4 4
Slot 2
WWAN/mSATA
SIM Card
Page 38
A
Page 38
USB(BT)
PCI-E(WLAN)
USB
SATA
Click Pad
Page 39
Int.KBD
Page 39
Thermal Sensor
Fintek F75303M
Page 39
SATA ODD CONN
m-SATA CONN
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Page 36
Page 38
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
LA-8133P
LA-8133P
LA-8133P
E
2 58Friday, January 13, 2012
2 58Friday, January 13, 2012
2 58Friday, January 13, 2012
1.0
1.0
1.0
1
2
3
4
5
Voltage Rails
0
1
2
3
4
5
6
7
USB 2.0 Port
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON ON ON
ON
OFF
OFFLOW LOW LOW LOW
HIGH HIGH HIGH HIGH
LOW LOW
HIGH
LOWLOWLOW
HIGH
HIGH
PCB Revision
0.1
0.2
0.3
0.4
0.5
0.6
BOM Structure Table
3 External
0
USB Port
1
USB 3.0 Port (Left Side)
2
USB 3.0 Port (Left Side)
3
USB 3.0 Port (Left Side)
4
5
Camera
6
7
8
9
USB Port (Right Side)
10
Mini Card(WLAN/BT)
11
FPR
12
Mini Card(WWAN)
13
Blue Tooth
Connector CONN@
45 LEVEL 45@
Unpop
SIM Card Slot
Intel UMA
Intel SBA SBA@
Intel AOAC AOAC@
TPM TPM@
GPU N13M
GPU N13P
OFF
OFF
OFF
OFF
OFF
OFF
BTO Item BOM Structure
@
DIS@nVidia
M3@INTEL DD3 M3
3G@
UMA@
X76@VRAM Option
N13M@
N13MP
STATE
+5VS
power
plane
A A
State
+5VALW
+B
+1.5V
+3VALW
+3VS
+1.5VS
+VCCP
+CPU_CORE
+VGA_CORE
+VCC_GFXCORE_AXG
+1.8VS
+0.75VS
+1.05VS
+3VM
+1.05VM
Full ON
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
BOARD ID Table
Board ID
S0
S3
S5 S4/AC
S5 S4/ Battery only
B B
S5 S4/AC & Battery
don't exist
O
O
O
O
O
O
X
X
X
X X X
O
X X
X
OO
X
X
O
M3 Supported
O
M3 Supported
O
M3 Supported
USB Port Table
EC SM Bus1 address
Device
Smart Battery
Address Address
0001 011X b
EC SM Bus2 address
Device
Thermal Sensor Fintek F75303M
1001_101xb
EHCI1
USB3.0
PCH SM Bus address
Device Address
DDR DIMM0
DDR DIMM2
C C
1001 000Xb
1001 010Xb
EHCI2
SMBUS Control Table
Thermal
X
X
V
+3VS
X
WLAN
WWAN
X
XX
V
+3VS
X
Sensor
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
D D
KB9012
+3VALW
KB9012
+3VALW
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW
VGA BATT KE9012 SODIMM
1
X V
X
X
X
V
+3VS
+3VALW
X
X
X
X
X
X
V
+3VS
X
X
X
XX
V
+3VS
2
PCH
X
V
+3VS
X
X
XX X
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-8133P
LA-8133P
LA-8133P
5
3 58Friday, January 13, 2012
3 58Friday, January 13, 2012
3 58Friday, January 13, 2012
1.0
1.0
1.0
1
2
3
4
5
A A
DMI_CRX_PTX_N0(15)
DMI_CRX_PTX_N1(15)
DMI_CRX_PTX_N2(15)
DMI_CRX_PTX_N3(15)
DMI_CRX_PTX_P0(15)
DMI_CRX_PTX_P1(15)
DMI_CRX_PTX_P2(15)
DMI_CRX_PTX_P3(15)
DMI_CTX_PRX_N0(15)
DMI_CTX_PRX_N1(15)
DMI_CTX_PRX_N2(15)
DMI_CTX_PRX_N3(15)
DMI_CTX_PRX_P0(15)
DMI_CTX_PRX_P1(15)
DMI_CTX_PRX_P2(15)
DMI_CTX_PRX_P3(15)
FDI_CTX_PRX_N0(15)
FDI_CTX_PRX_N1(15)
FDI_CTX_PRX_N2(15)
FDI_CTX_PRX_N3(15)
FDI_CTX_PRX_N4(15)
FDI_CTX_PRX_N5(15)
FDI_CTX_PRX_N6(15)
B B
C C
FDI_CTX_PRX_N7(15)
FDI_CTX_PRX_P0(15)
FDI_CTX_PRX_P1(15)
FDI_CTX_PRX_P2(15)
FDI_CTX_PRX_P3(15)
FDI_CTX_PRX_P4(15)
FDI_CTX_PRX_P5(15)
FDI_CTX_PRX_P6(15)
FDI_CTX_PRX_P7(15)
FDI_FSYNC0(15)
FDI_FSYNC1(15)
FDI_INT(15)
FDI_LSYNC0(15)
FDI_LSYNC1(15)
+1.05VS
R2 24.9_0402_1%R2 24.9_0402_1%
1 2
R3 10K_0402_5%@R3 10K_0402_5%@
1 2
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
EDP_COMP
JCPU1A
JCPU1A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD#
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_COMP
J22
J21
H22
PCIE_CRX_GTX_N0
K33
PCIE_CRX_GTX_N1
M35
PCIE_CRX_GTX_N2
L34
PCIE_CRX_GTX_N3
J35
PCIE_CRX_GTX_N4
J32
PCIE_CRX_GTX_N5
H34
PCIE_CRX_GTX_N6
H31
PCIE_CRX_GTX_N7
G33
PCIE_CRX_GTX_N8
G30
PCIE_CRX_GTX_N9
F35
PCIE_CRX_GTX_N10
E34
PCIE_CRX_GTX_N11
E32
PCIE_CRX_GTX_N12
D33
PCIE_CRX_GTX_N13
D31
PCIE_CRX_GTX_N14
B33
PCIE_CRX_GTX_N15
C32
PCIE_CRX_GTX_P0
J33
PCIE_CRX_GTX_P1
L35
PCIE_CRX_GTX_P2
K34
PCIE_CRX_GTX_P3
H35
PCIE_CRX_GTX_P4
H32
PCIE_CRX_GTX_P5
G34
PCIE_CRX_GTX_P6
G31
PCIE_CRX_GTX_P7
F33
PCIE_CRX_GTX_P8
F30
PCIE_CRX_GTX_P9
E35
PCIE_CRX_GTX_P10
E33
PCIE_CRX_GTX_P11
F32
PCIE_CRX_GTX_P12
D34
PCIE_CRX_GTX_P13
E31
PCIE_CRX_GTX_P14
C33
PCIE_CRX_GTX_P15
B32
PCIE_CTX_GRX_C_N0
M29
PCIE_CTX_GRX_C_N1
M32
PCIE_CTX_GRX_C_N2
M31
PCIE_CTX_GRX_C_N3
L32
PCIE_CTX_GRX_C_N4
L29
PCIE_CTX_GRX_C_N5
K31
PCIE_CTX_GRX_C_N6
K28
PCIE_CTX_GRX_C_N7
J30
PCIE_CTX_GRX_C_N8
J28
PCIE_CTX_GRX_C_N9
H29
PCIE_CTX_GRX_C_N10
G27
PCIE_CTX_GRX_C_N11
E29
PCIE_CTX_GRX_C_N12
F27
PCIE_CTX_GRX_C_N13
D28
PCIE_CTX_GRX_C_N14
F26
PCIE_CTX_GRX_C_N15
E25
PCIE_CTX_GRX_C_P0
M28
PCIE_CTX_GRX_C_P1
M33
PCIE_CTX_GRX_C_P2
M30
PCIE_CTX_GRX_C_P3
L31
PCIE_CTX_GRX_C_P4
L28
PCIE_CTX_GRX_C_P5
K30
PCIE_CTX_GRX_C_P6
K27
PCIE_CTX_GRX_C_P7
J29
PCIE_CTX_GRX_C_P8
J27
PCIE_CTX_GRX_C_P9
H28
PCIE_CTX_GRX_C_P10
G28
PCIE_CTX_GRX_C_P11
E28
PCIE_CTX_GRX_C_P12
F28
PCIE_CTX_GRX_C_P13
D27
PCIE_CTX_GRX_C_P14
E26
PCIE_CTX_GRX_C_P15
D25
R1 24.9_0402_1%R1 24.9_0402_1%
1 2
C1 0.1U_0402_10V7KDIS@C1 0.1U_0402_10V7KDIS@
1 2
C2 0.1U_0402_10V7KDIS@C2 0.1U_0402_10V7KDIS@
1 2
C3 0.1U_0402_10V7KDIS@C3 0.1U_0402_10V7KDIS@
1 2
C4 0.1U_0402_10V7KDIS@C4 0.1U_0402_10V7KDIS@
1 2
C5 0.1U_0402_10V7KDIS@C5 0.1U_0402_10V7KDIS@
1 2
C6 0.1U_0402_10V7KDIS@C6 0.1U_0402_10V7KDIS@
1 2
C7 0.1U_0402_10V7KDIS@C7 0.1U_0402_10V7KDIS@
1 2
C8 0.1U_0402_10V7KDIS@C8 0.1U_0402_10V7KDIS@
1 2
C9 0.1U_0402_10V7KDIS@C9 0.1U_0402_10V7KDIS@
1 2
C10 0.1U_0402_10V7KDIS@C10 0.1U_0402_10V7KDIS@
1 2
C11 0.1U_0402_10V7KDIS@C11 0.1U_0402_10V7KDIS@
1 2
C12 0.1U_0402_10V7KDIS@C12 0.1U_0402_10V7KDIS@
1 2
C13 0.1U_0402_10V7KDIS@C13 0.1U_0402_10V7KDIS@
1 2
C14 0.1U_0402_10V7KDIS@C14 0.1U_0402_10V7KDIS@
1 2
C15 0.1U_0402_10V7KDIS@C15 0.1U_0402_10V7KDIS@
1 2
C16 0.1U_0402_10V7KDIS@C16 0.1U_0402_10V7KDIS@
1 2
C17 0.1U_0402_10V7KDIS@C17 0.1U_0402_10V7KDIS@
1 2
C18 0.1U_0402_10V7KDIS@C18 0.1U_0402_10V7KDIS@
1 2
C19 0.1U_0402_10V7KDIS@C19 0.1U_0402_10V7KDIS@
1 2
C20 0.1U_0402_10V7KDIS@C20 0.1U_0402_10V7KDIS@
1 2
C21 0.1U_0402_10V7KDIS@C21 0.1U_0402_10V7KDIS@
1 2
C22 0.1U_0402_10V7KDIS@C22 0.1U_0402_10V7KDIS@
1 2
C23 0.1U_0402_10V7KDIS@C23 0.1U_0402_10V7KDIS@
1 2
C24 0.1U_0402_10V7KDIS@C24 0.1U_0402_10V7KDIS@
1 2
C25 0.1U_0402_10V7KDIS@C25 0.1U_0402_10V7KDIS@
1 2
C26 0.1U_0402_10V7KDIS@C26 0.1U_0402_10V7KDIS@
1 2
C27 0.1U_0402_10V7KDIS@C27 0.1U_0402_10V7KDIS@
1 2
C28 0.1U_0402_10V7KDIS@C28 0.1U_0402_10V7KDIS@
1 2
C29 0.1U_0402_10V7KDIS@C29 0.1U_0402_10V7KDIS@
1 2
C30 0.1U_0402_10V7KDIS@C30 0.1U_0402_10V7KDIS@
1 2
C31 0.1U_0402_10V7KDIS@C31 0.1U_0402_10V7KDIS@
1 2
C32 0.1U_0402_10V7KDIS@C32 0.1U_0402_10V7KDIS@
1 2
+1.05VS
PCIE_CRX_GTX_N[0..15] (22)
PCIE_CRX_GTX_P[0..15] (22)
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15
PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1: Normal Operation; Lane # definition matches
socket pin map definition
*
0:Lane Reversed
PCIE_CTX_GRX_N[0..15] (22)
PCIE_CTX_GRX_P[0..15] (22)
Nvidia support PCIE Gen2
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
LA-8133P
LA-8133P
LA-8133P
5
4 58Friday, January 13, 2012
4 58Friday, January 13, 2012
4 58Friday, January 13, 2012
1.0
1.0
1.0
1
A A
H_SNB_IVB#(18)
+1.05VS
R5 62_0402_5%R5 62_0402_5%
1 2
Processor Pullups
H_PECI(18,41)
H_PROCHOT#(41)
H_THRMTRIP#(18)
2
R8 10K_0402_5%@R8 10K_0402_5%@
1 2
H_CATERR#
H_PECI
H_PROCHOT#H_PROCHOT#
R12 56_0402_5%R12 56_0402_5%
1 2
H_PROCHOT#_R
H_THRMTRIP#
C26
AN34
AL33
AN33
AL32
AN32
3
JCPU1B
JCPU1B
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
BCLK
BCLK#
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
DDR3
DDR3
MISC
MISC
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
A28
A27
A16
A15
R8
AK1
A5
A4
4
CLK_CPU_DMI_R
CLK_CPU_DMI#_R
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
R4 0_0402_5%@R4 0_0402_5%@
1 2
R7 0_0402_5%@R7 0_0402_5%@
1 2
R9 1K_0402_5%R9 1K_0402_5%
1 2
R10 1K_0402_5%R10 1K_0402_5%
1 2
R13 140_0402_1%R13 140_0402_1%
1 2
R14 25.5_.402_1%R14 25.5_.402_1%
1 2
R15 200_0402_1%R15 200_0402_1%
DDR3 Compensation Signals
1 2
CLK_CPU_DMI (14)
CLK_CPU_DMI# (14)
+1.05VS
H_DRAMRST# (6)
5
DBR#
XDP_PRDY#
AP29
XDP_PREQ#
AP27
XDP_TCK
AR26
TCK
XDP_TMS
AR27
TMS
XDP_TRST#
AP30
XDP_TDI
AR28
TDI
XDP_TDO
AP26
TDO
XDP_DBRESET#
AL35
XDP_BPM#0
AT28
XDP_BPM#1
AR29
XDP_BPM#2
AR30
XDP_BPM#3
AT30
XDP_BPM#4
AP32
XDP_BPM#5
AR31
XDP_BPM#6
AT31
XDP_BPM#7
AR32
PU/PD for JTAG signals
R21 51_0402_5%R21 51_0402_5%
1 2
R17 51_0402_5%R17 51_0402_5%
1 2
R22 51_0402_5%R22 51_0402_5%
1 2
R18 51_0402_5%R18 51_0402_5%
1 2
R19 51_0402_5%R19 51_0402_5%
1 2
R24 1K_0402_5%R24 1K_0402_5%
1 2
+1.05VS
+3VS
XDP_DBRESET# (15)
For 26 Pin XDP Conn.
R26 1K_0402_1%@R26 1K_0402_1%@
H_CPUPWRGD(18)
PBTN_OUT#(15,41)
XDP_CFG0(7)
SYS_PWROK(15)
CLK_XDP_CLK(14)
CLK_XDP_CLK#(14)
PLT_RST#(14,17,22,36,38,40,41)
PLT_RST#
1 2
R27 0_0402_5%@R27 0_0402_5%@
1 2
R28 1K_0402_1%@R28 1K_0402_1%@
1 2
R29 0_0402_5%@R29 0_0402_5%@
1 2
R30 0_0402_5%@R30 0_0402_5%@
1 2
R31 0_0402_5%@R31 0_0402_5%@
1 2
R32 1K_0402_1%@R32 1K_0402_1%@
1 2
P+
PRDY#
P+
PREQ#
P+
B B
C C
1
C34
@C34
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R35
@R35
@
10K_0402_5%
10K_0402_5%
PM_DRAM_PWRGD(15)
D D
PM_DRAM_PWRGD PM_SYS_PWRGD_BUF
R214 0_0402_5%R214 0_0402_5%
1 2
1 2
5
1
P
B
2
A
G
3
2
U1
@U1
@
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
4
O
RUN_ON_CPU1.5VS3#(9)
H_PM_SYNC(15)
R23 0_0402_5%@R23 0_0402_5%@
H_CPUPWRGD(18)
12
R33
R33
200_0402_5%
200_0402_5%
PM_SYS_PWRGD_BUF
12
R37
R37
39_0402_5%
39_0402_5%
@
@
13
D
D
Q1
Q1
2N7002K_SOT23-3
2N7002K_SOT23-3
2
G
@
G
@
S
S
1 2
R6 10K_0402_5%R6 10K_0402_5%
1 2
C33 220P_0402_50V7K@C33 220P_0402_50V7K@
1 2
R25 130_0402_5%R25 130_0402_5%
1 2
H_PM_SYNC
H_CPUPWRGD_R
PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF
BUF_CPU_RST#
Buffered reset to CPU
PCH_PLTRST#(17)
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
+3VS +1.05VS+1.5V_CPU_VDDQ+3VALW+3VS
1
2
5
1
P
NC
Y
2
A
G
U2
U2
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
3
C35
C35
0.1U_0402_16V4Z
0.1U_0402_16V4Z
BUFO_CPU_RST# BUF_CPU_RST#
4
12
R34
R34
75_0402_5%
75_0402_5%
R36
R36
43_0402_1%
43_0402_1%
1 2
P+
P+
TRST#
P+
BPM#[0]
BPM#[1]
JTAG & BPM
JTAG & BPM
12
R38
R38
0_0402_5%
0_0402_5%
@
@
BPM#[2]
BPM#[3]
P+
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
LA-8133P
LA-8133P
LA-8133P
5
5 58Friday, January 13, 2012
5 58Friday, January 13, 2012
5 58Friday, January 13, 2012
1.0
1.0
1.0
1
2
3
4
5
JCPU1C
JCPU1C
A A
B B
C C
DDR_A_D[0..63](11)
DDR_A_BS0(11)
DDR_A_BS1(11)
DDR_A_BS2(11)
DDR_A_CAS#(11)
DDR_A_RAS#(11)
DDR_A_WE#(11)
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
G10
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
N10
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
M10
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
AG6
SA_DQ[32]
AG5
SA_DQ[33]
AK6
SA_DQ[34]
AK5
SA_DQ[35]
AH5
SA_DQ[36]
AH6
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
AK8
SA_DQ[41]
AJ9
SA_DQ[42]
AK9
SA_DQ[43]
AH8
SA_DQ[44]
AH9
SA_DQ[45]
AL9
SA_DQ[46]
AL8
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
V6
SA_BS[2]
AE8
SA_CAS#
AD9
SA_RAS#
AF9
SA_WE#
CONN@
CONN@
AB6
SA_CLK[0]
AA6
SA_CLK#[0]
V9
SA_CKE[0]
AA5
SA_CLK[1]
AB5
SA_CLK#[1]
V10
SA_CKE[1]
AB4
RSVD_TP[1]
AA4
RSVD_TP[2]
W9
RSVD_TP[3]
AB3
RSVD_TP[4]
AA3
RSVD_TP[5]
W10
RSVD_TP[6]
AK3
SA_CS#[0]
AL3
SA_CS#[1]
AG1
RSVD_TP[7]
AH1
RSVD_TP[8]
AH3
SA_ODT[0]
AG3
SA_ODT[1]
AG2
RSVD_TP[9]
AH2
RSVD_TP[10]
DDR_A_DQS#0
C4
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 (11)
M_CLK_DDR#0 (11)
DDR_CKE0_DIMMA (11)
M_CLK_DDR1 (11)
M_CLK_DDR#1 (11)
DDR_CKE1_DIMMA (11)
DDR_CS0_DIMMA# (11)
DDR_CS1_DIMMA# (11)
M_ODT0 (11)
M_ODT1 (11)
DDR_A_DQS#[0..7] (11)
DDR_A_DQS[0..7] (11)
DDR_A_MA[0..15] (11) DDR_B_MA[0..15] (12)
DDR_B_D[0..63](12)
DDR_B_BS0(12)
DDR_B_BS1(12)
DDR_B_BS2(12)
DDR_B_CAS#(12)
DDR_B_RAS#(12)
DDR_B_WE#(12)
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AJ11
AH11
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
JCPU1D
JCPU1D
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
AM5
SB_DQ[32]
AM6
SB_DQ[33]
AR3
SB_DQ[34]
AP3
SB_DQ[35]
AN3
SB_DQ[36]
AN2
SB_DQ[37]
AN1
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
AN9
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
AN8
SB_DQ[45]
AR6
SB_DQ[46]
AR5
SB_DQ[47]
AR9
SB_DQ[48]
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
SB_DQ[52]
AR8
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
CONN@
CONN@
AE2
SB_CLK[0]
AD2
SB_CLK#[0]
R9
SB_CKE[0]
AE1
SB_CLK[1]
AD1
SB_CLK#[1]
R10
SB_CKE[1]
AB2
RSVD_TP[11]
AA2
RSVD_TP[12]
T9
RSVD_TP[13]
AA1
RSVD_TP[14]
AB1
RSVD_TP[15]
T10
RSVD_TP[16]
AD3
SB_CS#[0]
AE3
SB_CS#[1]
AD6
RSVD_TP[17]
AE6
RSVD_TP[18]
AE4
SB_ODT[0]
AD4
SB_ODT[1]
AD5
RSVD_TP[19]
AE5
RSVD_TP[20]
DDR_B_DQS#0
D7
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
M_CLK_DDR2 (12)
M_CLK_DDR#2 (12)
DDR_CKE2_DIMMB (12)
M_CLK_DDR3 (12)
M_CLK_DDR#3 (12)
DDR_CKE3_DIMMB (12)
DDR_CS2_DIMMB# (12)
DDR_CS3_DIMMB# (12)
M_ODT2 (12)
M_ODT3 (12)
DDR_B_DQS#[0..7] (12)
DDR_B_DQS[0..7] (12)
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
+1.5V
R39 0_0402_5%@R39 0_0402_5%@
1 2
D
S
D
D D
H_DRAMRST#(5)
R42
R42
4.99K_0402_1%
4.99K_0402_1%
R43 0_0402_5%@R43 0_0402_5%@
DRAMRST_CNTRL_PCH(14)
1
1 2
S
12
G
G
13
Q2
Q2
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
2
DRAMRST_CNTRL
1
C36
C36
0.047U_0402_16V4Z
0.047U_0402_16V4Z
2
DDR3_DRAMRST#_R
R40
R40
1K_0402_5%
1K_0402_5%
12
R41
R41
1K_0402_5%
1K_0402_5%
1 2
2
DDR3_DRAMRST# (11,12)
DRAMRST_CNTRL (9)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
LA-8133P
LA-8133P
LA-8133P
5
6 58Friday, January 13, 2012
6 58Friday, January 13, 2012
6 58Friday, January 13, 2012
1.0
1.0
1.0
1
2
3
4
5
CFG Straps for Processor
CFG2
12
R45
A A
R45
1K_0402_1%
1K_0402_1%
@
@
JCPU1E
JCPU1E
XDP_CFG0(5)
+CPU_CORE +VCC_GFXCORE_AXG
12
R48
R48
49.9_0402_1%
49.9_0402_1%
B B
C C
12
R46
R46
49.9_0402_1%
49.9_0402_1%
R176 100_0402_1%@R176 100_0402_1%@
1 2
R179 100_0402_1%@R179 100_0402_1%@
1 2
R47 49.9_0402_1%R47 49.9_0402_1%
1 2
R49 49.9_0402_1%R49 49.9_0402_1%
1 2
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE
CFG2
CFG4
CFG5
CFG6
CFG7
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
P+
CFG
CFG
RESERVED
RESERVED
CONN@
CONN@
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
PEG Static Lane Reversal - CFG2 is for the 16x
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
KEY
R173 0_0402_5%@R173 0_0402_5%@
1 2
T2T2
CFG2
Display Port Presence Strap
PCIE Port Bifurcation Straps
CFG[6:5]
1: Normal Operation; Lane # definition matches
socket pin map definition
*
0:Lane Reversed
CFG4
12
R50
@R50
@
1K_0402_1%
1K_0402_1%
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
*
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
CFG5
12
12
R51
@R51
@
1K_0402_1%
1K_0402_1%
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
12
R53
@R53
@
1K_0402_1%
1K_0402_1%
R52
@R52
@
1K_0402_1%
1K_0402_1%
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7
de assertion
0: PEG Wait for BIOS for training
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
LA-8133P
LA-8133P
LA-8133P
5
7 58Friday, January 13, 2012
7 58Friday, January 13, 2012
7 58Friday, January 13, 2012
1.0
1.0
1.0
1
2
3
4
5
+CPU_CORE +1.05VS
A A
B B
C C
D D
JCPU1F
JCPU1F
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
POWER
POWER
PEG AND DDR
PEG AND DDR
CORE SUPPLY
CORE SUPPLY
VSS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
CONN@
CONN@
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
8.5A97A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
12
1
R54
C37
C37
0.1U_0402_16V4Z
0.1U_0402_16V4Z
H_CPU_SVIDALRT#
AJ29
H_CPU_SVIDCLK
AJ30
H_CPU_SVIDDAT
AJ28
Trace Impedance = 27 ~ 33 ohm
Trace Length Match < 25 mils
VCCSENSE_R
AJ35
VSSSENSE_R
AJ34
R64 10_0402_1%R64 10_0402_1%
1 2
VCCIO_SENSE
B10
VSSIO_SENSE
A10
R63
R63
10_0402_1%
10_0402_1%
R54
130_0402_5%
130_0402_5%
2
R56 43_0402_1%R56 43_0402_1%
R57 0_0402_5%@R57 0_0402_5%@
R58 0_0402_5%@R58 0_0402_5%@
R174 100_0402_1%@R174 100_0402_1%@
R60 0_0402_5%@R60 0_0402_5%@
R61 0_0402_5%@R61 0_0402_5%@
12
1 2
1 2
1 2
1 2
1 2
1 2
+1.05VS
VCCIO_SENSE (50)
R55
R55
75_0402_5%
75_0402_5%
+1.05VS+1.05VS
12
VCCSENSE_RVSSSENSE_R
+CPU_CORE
12
12
1
C38
C38
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Place the PU
resistors close to VR
VR_SVID_ALRT# (52)
VR_SVID_CLK (52)
VR_SVID_DAT (52)
R59
R59
Place the PU
100_0402_1%
100_0402_1%
resistors close to CPU
VCCSENSE (52)
VSSSENSE (52)
R62
R62
100_0402_1%
100_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
LA-8133P
LA-8133P
LA-8133P
5
8 58Friday, January 13, 2012
8 58Friday, January 13, 2012
8 58Friday, January 13, 2012
1.0
1.0
1.0
1
A A
+VCC_GFXCORE_AXG
B B
C C
D D
+1.8VS
R76 0_0805_5%R76 0_0805_5%
1 2
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
56
56
1
2
Vaxg
Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
+1.8VS_VCCPLL
C58
C58
C
C
57
57
1
2
1
C59
C59
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
@
@
2
1
2
+
+
1.5A
330U_D2_2V_Y
330U_D2_2V_Y
33A
JCPU1G
JCPU1G
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
VAXG13
AP23
VAXG14
AP21
VAXG15
AP20
VAXG16
AP18
VAXG17
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
AN18
VAXG23
AN17
VAXG24
AM24
VAXG25
AM23
VAXG26
AM21
VAXG27
AM20
VAXG28
AM18
VAXG29
AM17
VAXG30
AL24
VAXG31
AL23
VAXG32
AL21
VAXG33
AL20
VAXG34
AL18
VAXG35
AL17
VAXG36
AK24
VAXG37
AK23
VAXG38
AK21
VAXG39
AK20
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48
AH24
VAXG49
AH23
VAXG50
AH21
VAXG51
AH20
VAXG52
AH18
VAXG53
AH17
VAXG54
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
POWER
POWER
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
2
+VCC_GFXCORE_AXG
R73 100_0402_1%@R73 100_0402_1%@
CONN@
CONN@
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCIO_SEL
2
AK35
AK34
+V_SM_VREF_CNT
AL1
+V_DDR_REFA_R
B4
+V_DDR_REFB_R
D1
+1.5V_CPU_VDDQ
10A
AF7
AF4
C40
C40
10U_0603_6.3V6M
10U_0603_6.3V6M
AF1
AC7
1
AC4
AC1
Y7
2
Y4
Y1
U7
U4
U1
P7
P4
P1
C48
C48
1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
2
H_VCCP_SEL
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
VAXG_SENSE
VSSAXG_SENSE
SENSE
SENSE
LINES
LINES
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
1 2
12
C41
C41
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
R65
R65
10_0402_1%
10_0402_1%
1 2
R66
R66
10_0402_1%
10_0402_1%
+V_SM_VREF should
have 10 mil trace width
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
C43
C43
C42
C42
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
C50
C50
C49
C49
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
R75 0_0402_5%@R75 0_0402_5%@
1 2
R77 0_0402_5%@R77 0_0402_5%@
1 2
+1.5V_CPU_VDDQ
12
R68
R68
12
R72
R72
C44
C44
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
C51
C51
C52
C52
10U_0603_6.3V6M
10U_0603_6.3V6M
1
@
@
@
@
2
1
+
+
2
3
VCC_AXG_SENSE (52)
VSS_AXG_SENSE (52)
R70 0_0402_5%@R70 0_0402_5%@
1 2
3
C39
C39
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
@
@
2
@JP1
@
1 2
C46
C46
C45
C45
330U_D2_2V_Y
330U_D2_2V_Y
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
+VCCSA
330U_D2_2V_Y
330U_D2_2V_Y
R78 10K_0402_5%R78 10K_0402_5%
1
+
+
2
+VCCSA_SENSE (49)
H_VCCSA_VID0 (49)
H_VCCSA_VID1 (49)
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
3
4
M3 Support
+1.5V
12
R69
@R69
@
100_0402_5%
100_0402_5%
+1.5V
CPU1.5V_S3_GATE(41)
RUN_ON_CPU1.5VS3#(5)
+V_SM_VREF
12
R74
@R74
@
100_0402_5%
100_0402_5%
R80
R80
100K_0402_5%
100K_0402_5%
@
@
R83 0_0402_5%@R83 0_0402_5%@
SUSP(24,42,50,51)
SUSP#(24,41,42,46,48,50,51)
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
1 2
R84 0_0402_5%@R84 0_0402_5%@
1 2
R86
@R86
@
1 2
0_0402_5%
0_0402_5%
RUN_ON_CPU1.5VS3#
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Q12
Q12
2
2N7002K_SOT23-3
2N7002K_SOT23-3
@
@
4
G
G
1
Q4
Q4
AP2302GN-HF_SOT23-3
AP2302GN-HF_SOT23-3
@
@
RUN_ON_CPU1.5VS3
JP1
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
from 1PCS 2N7002 dual channel change to BSS138 2pCS
12
R81
R81
82K_0402_1%
82K_0402_1%
Q11
Q11
2
G
G
13
2N7002K_SOT23-3
2N7002K_SOT23-3
D
D
S
S
R67 0_0402_5%@R67 0_0402_5%@
1 2
Q3
Q3
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
S
+V_DDR_REFA_R
R79
R79
1K_0402_1%
1K_0402_1%
@
@
+V_DDR_REFB_R
R108
R108
1K_0402_1%
1K_0402_1%
@
@
+1.5V_CPU_VDDQ +1.5V
S
12
R71 0_0402_5%@R71 0_0402_5%@
1 2
Q6
Q6
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
S
S
12
C47 0.1U_0402_10V7KC47 0.1U_0402_10V7K
C53 0.1U_0402_10V7KC53 0.1U_0402_10V7K
C54 0.1U_0402_10V7KC54 0.1U_0402_10V7K
C55 0.1U_0402_10V7KC55 0.1U_0402_10V7K
+1.5V_CPU_VDDQ Source
+VSB+3VALW +1.5V_CPU_VDDQ+1.5V
12
RUN_ON_CPU1.5VS3
13
12
D
D
R85
R85
@
@
S
S
330K_0402_5%
330K_0402_5%
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
J2@
J2@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
Q5
Q5
AP4800BGM-HF_SO-8
AP4800BGM-HF_SO-8
8
7
6
5
R201
R201
1 2
15K_0402_5%
15K_0402_5%
C61
C61
0.047U_0603_25V7K
0.047U_0603_25V7K
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
D
D
13
G
G
2
DRAMRST_CNTRL
D
D
13
G
G
2
1 2
1 2
1 2
1 2
4
1
2
5
DRAMRST_CNTRL (6)
1
R82 220_0402_5%R82 220_0402_5%
2
3
12
13
D
D
G
G
S
S
LA-8133P
LA-8133P
LA-8133P
5
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
1
C60
C60
0.1U_0402_10V6K
0.1U_0402_10V6K
@
@
2
RUN_ON_CPU1.5VS3#
2
Q7
Q7
2N7002K_SOT23-3
2N7002K_SOT23-3
9 58Friday, January 13, 2012
9 58Friday, January 13, 2012
9 58Friday, January 13, 2012
1.0
1.0
1.0
1
A A
B B
C C
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AR25
AR22
AR19
AR16
AR13
AR10
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AJ25
2
JCPU1H
JCPU1H
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
AN7
VSS43
AN4
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
AK7
VSS78
AK4
VSS79
VSS80
VSS
VSS
CONN@
CONN@
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
3
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS
CONN@
CONN@
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
4
5
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
D D
1
2
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
LA-8133P
LA-8133P
LA-8133P
5
10 58Friday, January 13, 2012
10 58Friday, January 13, 2012
10 58Friday, January 13, 2012
1.0
1.0
1.0
1
+1.5V
12
R2001
R2001
1K_0402_1%
1K_0402_1%
A A
B B
C C
D D
+VREF_DQ_DIMMA
R2003
R2003
1K_0402_1%
1K_0402_1%
All VREF traces should
have 10 mil trace width
C2001
C2001
12
1
2
DDR_CKE0_DIMMA(6)
DDR_A_BS2(6)
M_CLK_DDR0(6)
M_CLK_DDR#0(6)
DDR_A_BS0(6)
DDR_A_WE#(6)
DDR_A_CAS#(6)
DDR_CS1_DIMMA#(6)
+3VS
+0.75VS +0.75VS
<Address: 00>
DIMM_A Reserve H:4.0mm
1
2
+1.5V
JDIMM1
C2002
C2002
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C2021
C2021
C2046
C2046
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
+VREF_DQ_DIMMA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_D0
DDR_A_D1
1
2
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32 DDR_A_D36
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42 DDR_A_D46
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
C2022
C2022
R2006
R2006
R2007
R2007
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
10K_0402_5%
10K_0402_5%
10K_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
@
@
2
10K_0402_5%
12
12
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013310-1
TYCO_2-2013310-1
CONN@
CONN@
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
2
4
DQ4
6
DQ5
8
10
12
14
16
DQ6
18
DQ7
20
22
24
26
28
DM1
30
32
34
36
38
40
42
44
46
DM2
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
CK1
104
106
108
BA1
110
112
114
S0#
116
118
120
122
NC2
124
126
128
130
132
134
136
DM4
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
DM6
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SDA
202
SCL
204
206
G2
+1.5V
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14DDR_A_MA14
DDR_A_MA11DDR_A_MA12
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
+VREF_CA
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3
3
DDR3_DRAMRST# (6,12)
DDR_CKE1_DIMMA (6)
M_CLK_DDR1 (6)
M_CLK_DDR#1 (6)
DDR_A_BS1 (6)
DDR_A_RAS# (6)
DDR_CS0_DIMMA# (6)
M_ODT0 (6)
M_ODT1 (6)
C2015
C2015
C2016
C2016
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
SMB_DATA_S3 (12,14,38,39)
SMB_CLK_S3 (12,14,38,39)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.5V
12
R2004
R2004
1K_0402_1%
1K_0402_1%
12
R2005
R2005
1K_0402_1%
1K_0402_1%
Compal Secret Data
Compal Secret Data
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
4
Deciphered Date
Deciphered Date
Deciphered Date
4
5
DDR_A_DQS#[0..7] (6)
DDR_A_DQS[0..7] (6)
DDR_A_D[0..63] (6)
DDR_A_MA[0..15] (6)
Layout Note:
Place near
JDIMM1
+1.5V
C2004
C2004
C2005
C2005
C2006
C2003
C2003
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
2
2
+1.5V
C2007
C2007
C2008
C2008
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
+0.75VS
C2017
C2017
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
Title
Title
Title
DDRIII DIMMA
DDRIII DIMMA
DDRIII DIMMA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
C2006
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
2
2
C2010
C2010
C2011
C2009
C2009
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
C2018
C2018
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
C2011
C2012
C2012
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
C2020
C2020
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
LA-8133P
LA-8133P
LA-8133P
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
Layout Note:
Place near
JDIMM1.203,204
5
10U_0603_6.3V6M
10U_0603_6.3V6M
C2019
C2019
1
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
C2013
C2013
C2014
C2014
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
+
+
@
@
2
@
@
2
11 58Friday, January 13, 2012
11 58Friday, January 13, 2012
11 58Friday, January 13, 2012
330U_D2_2V_Y
330U_D2_2V_Y
1.0
1.0
1.0
1
2
3
4
5
+1.5V
12
R2008
R2008
1K_0402_1%
1K_0402_1%
+1.5V +1.5V
JDIMM2
12
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A626-U2SN-7F
FOX_AS0A626-U2SN-7F
CONN@
CONN@
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
2
DDR_B_D4
4
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
+VREF_CB
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
SMB_DATA_S3
SMB_CLK_S3
DDR3_DRAMRST# (6,11)
DDR_CKE3_DIMMB (6)
M_CLK_DDR3 (6)
M_CLK_DDR#3 (6)
DDR_B_BS1 (6)
DDR_B_RAS# (6)
DDR_CS2_DIMMB# (6)
M_ODT2 (6)
M_ODT3 (6)
C2038
C2038
C2037
C2037
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
1
2
2
SMB_DATA_S3 (11,14,38,39)
SMB_CLK_S3 (11,14,38,39)
+0.75VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.5V
12
R2011
R2011
1K_0402_1%
1K_0402_1%
12
R2012
R2012
1K_0402_1%
1K_0402_1%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Deciphered Date
4
+1.5V
C2027
C2025
C2025
1
2
+1.5V
C2029
C2029
1
2
+0.75VS
C2039
C2039
1
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
C2027
C2026
C2026
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
Layout Note:
Place near
JDIMM2.203,204
1U_0402_6.3V6K
1U_0402_6.3V6K
DDRIII DIMMB
DDRIII DIMMB
DDRIII DIMMB
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
2
2
C2031
C2031
C2030
C2030
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
C2041
C2041
C2040
C2040
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
A A
B B
C C
D D
1
+VREF_DQ_DIMMB
R2013
R2013
10K_0402_5%
10K_0402_5%
+0.75VS
C2024
C2024
1
12
R2010
R2010
1K_0402_1%
1K_0402_1%
All VREF traces should
have 10 mil trace width
+3VS
12
2
DDR_CKE2_DIMMB(6)
DDR_B_BS2(6)
M_CLK_DDR2(6)
M_CLK_DDR#2(6)
DDR_B_BS0(6)
DDR_B_WE#(6)
DDR_B_CAS#(6)
DDR_CS3_DIMMB#(6)
C2044
C2044
C2043
C2043
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+3VS
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C2023
C2023
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VREF_DQ_DIMMB
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
R2014
R2014
10K_0402_5%
10K_0402_5%
2
DDR_B_DQS#[0..7] (6)
DDR_B_DQS[0..7] (6)
DDR_B_D[0..63] (6)
DDR_B_MA[0..15] (6)
C2028
C2028
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
C2033
C2033
C2032
C2032
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
C2042
C2042
C2045
C2045
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
LA-8133P
LA-8133P
LA-8133P
5
Layout Note:
Place near
JDIMM2
C2035
C2035
C2034
C2034
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
@
@
2
2
@
@
12 58Friday, January 13, 2012
12 58Friday, January 13, 2012
12 58Friday, January 13, 2012
C2036
C2036
330U_D2_2V_Y
330U_D2_2V_Y
1
+
+
@
@
2
1.0
1.0
1.0
1
PCH_RTCX1
1
C64
C64
18P_0402_50V8J
18P_0402_50V8J
2
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
1
C179
C179
1U_0402_6.3V6K
1U_0402_6.3V6K
2
R106
R106
1K_0402_5%
1K_0402_5%
1 2
+RTCVCC
R87 10M_0402_5%R87 10M_0402_5%
1 2
Y1
Y1
1 2
1
1
8P_0402_50V8J
8P_0402_50V8J
32.768KHZ_12.5PF_CM31532768DZFT
32.768KHZ_12.5PF_CM31532768DZFT
1
C63
C63
11/14
2
A A
+RTCVCC
R90 1M_0402_5%R90 1M_0402_5%
1 2
R91 330K_0402_5%R91 330K_0402_5%
1 2
INTVRMEN
HIntegrated VRM enable
*
LIntegrated VRM disable
(INTVRMEN should always be pull high.)
+3VS
R93 1K_0402_5%@R93 1K_0402_5%@
1 2
HIGH= Enable ( No Reboot )
LOW= Disable (Default)
*
B B
+3V_PCH
R95 1K_0402_5%@R95 1K_0402_5%@
1 2
HDA_SDO
ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
*
High = Enabled [Flash Descriptor Security Overide]
+3V_PCH
R99 1K_0402_5%R99 1K_0402_5%
1 2
HDA_SPKR
HDA_SDOUT
HDA_SYNC
+3VS
R202 10K_0402_5%R202 10K_0402_5%
1 2
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when sampled high
*
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
C C
HDA_BITCLK_AUDIO(35)
HDA_SYNC_AUDIO(35)
HDA_RST#_AUDIO(35)
HDA_SDOUT_AUDIO(35)
C76 22P_0402_50V8JC76 22P_0402_50V8J
1 2
C77 22P_0402_50V8J@C77 22P_0402_50V8J@
1 2
+3V_PCH +3V_PCH+3V_PCH
D D
12
R120
200_0402_5%
200_0402_5%
12
R123
100_0402_1%
100_0402_1%
12
@R120
@
PCH_JTAG_TMSPCH_JTAG_TDO PCH_JTAG_TDI
12
@R123
@
R121
@R121
@
200_0402_5%
200_0402_5%
R124
@R124
@
100_0402_1%
100_0402_1%
R107
R107
33_0402_5%
33_0402_5%
1 2
R241
R241
33_0402_5%
33_0402_5%
1 2
R109
R109
33_0402_5%
33_0402_5%
1 2
R111
R111
33_0402_5%
33_0402_5%
1 2
1
HDA_BIT_CLK
HDA_SYNC_R
HDA_RST#
HDA_SDOUT
HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
12
R122
@R122
@
200_0402_5%
200_0402_5%
12
R125
@R125
@
100_0402_1%
100_0402_1%
Prevent back drive issue.
+5VS
G
G
2
13
D
S
D
S
Q8
Q8
12
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
R303
R303
1M_0402_5%
1M_0402_5%
2
W=20milsW=20mils
+RTCBATT+RTCVCC
12
CLRP1
CLRP1
SHORT PADS
SHORT PADS
1U_0402_6.3V6K
1U_0402_6.3V6K
R88 20K_0402_5%R88 20K_0402_5%
1 2
R89 20K_0402_5%R89 20K_0402_5%
1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
WLBT_OFF_5#
9/27
HDA_SYNC
2
WLBT_OFF_5#(38)
C62
C62
C66
C66
ME_FLASH(41)
+3V_PCH
3
CMOS
JCMOS1
JCMOS1
SHORT PADS
SHORT PADS
1
12
@
@
2
SHORT PADS
SHORT PADS
1
12
@
@
2
ME
R94 0_0402_5%@R94 0_0402_5%@
R209 10K_0402_5%@R209 10K_0402_5%@
R96 51_0402_5%R96 51_0402_5%
JME1
JME1
HDA_SPKR(35)
HDA_SDIN0(35)
1 2
1 2
1 2
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDIN0
HDA_SDOUT
WLBT_OFF_5#
PCH_GPIO13
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
SPI_CLK_PCH_R
SPI_SB_CS0#
SPI_SB_CS1#
SPI_SI
SPI_SO_R
U3A
U3A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
PP-
PPPP-
P-
PP+
P+
PP+
8MB+4MB SPI ROM FOR 5M ME(SBA)
& Non-share ROM.
U6
SPI_SB_CS1#
R336 0_0402_5%R336 0_0402_5%
1 2
R343 33_0402_5%R343 33_0402_5%
1 2
SPI_SB_CS0#
R340 0_0402_5%R340 0_0402_5%
SPI_SO_R SPI_SO_L
EON
8M:SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P
4M:SA00004LI00 S IC FL 32M EN25Q32B-104HIP SOP 8P
1 2
R337 33_0402_5%R337 33_0402_5%
1 2
CS1#
SPI_SO1SPI_SO_R
SPI_WP#1
3
U6
1
2
3
4
W25Q16BVSSIG_SO8
W25Q16BVSSIG_SO8
CS#
1
2
SPI_WP#
3
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
P+
U6 4M
CS#
DO(IO1)
HOLD#(IO3)
WP#(IO2)
GND
DI(IO0)
U5 8M
U5
U5
CS#
VCC
DO
HOLD#
WP#
GND
W25Q32BVSSIG_SO8
W25Q32BVSSIG_SO8
4
LPC_AD0
P+
P+
P+
P+
LPC
LPC
FWH4 / LFRAME#
P+
P+
LDRQ1# / GPIO23
SATA 6G
SATA 6G
SATA
SATA
SATAICOMPO
SATA3RCOMPO
SATA0GP / GPIO21
SATA1GP / GPIO19
VCC
CLK
8
7
6
CLK
5
DI
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
C38
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPI
SATA3COMPI
SATA3RBIAS
SATALED#
8
SPI_HOLD#1
7
SPI_CLK1
6
SPI_SI1
5
+3VS_SPI
SPI_HOLD#
SPI_CLK_PCH SPI_CLK_PCH_R
SPI_SI_R
LPC_AD1
A38
LPC_AD2
B37
LPC_AD3
C37
LPC_FRAME#
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
R110 0_0402_5%
R110 0_0402_5%
1 2
R112 0_0402_5%SBA@R112 0_0402_5%SBA@
1 2
R339 33_0402_5%R339 33_0402_5%
R338 33_0402_5%R338 33_0402_5%
C191 0.1U_0402_16V4ZC191 0.1U_0402_16V4Z
1 2
R92 10K_0402_5%R92 10K_0402_5%
SERIRQ
SATA_PTX_C_DRX_N0
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N2
SATA_PTX_C_DRX_P2
SATA_COMP
SATA3_COMP
RBIAS_SATA3
PCH_SATALED#
PCH_GPIO21
ODD_DET#
9/22
@
@
1 2
1 2
R342 33_0402_5%R342 33_0402_5%
1 2
1 2
R341 33_0402_5%R341 33_0402_5%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1 2
C67 0.01U_0402_16V7KC67 0.01U_0402_16V7K
C68 0.01U_0402_16V7KC68 0.01U_0402_16V7K
C69 0.01U_0402_16V7KC69 0.01U_0402_16V7K
C70 0.01U_0402_16V7KC70 0.01U_0402_16V7K
C71 0.01U_0402_16V7KC71 0.01U_0402_16V7K
C72 0.01U_0402_16V7KC72 0.01U_0402_16V7K
R97 37.4_0402_1%R97 37.4_0402_1%
1 2
R98 49.9_0402_1%R98 49.9_0402_1%
1 2
R100 750_0402_1%R100 750_0402_1%
1 2
R101 10K_0402_5%R101 10K_0402_5%
1 2
R102 10K_0402_5%R102 10K_0402_5%
1 2
R103 10K_0402_5%R103 10K_0402_5%
1 2
+3VS+3VS_SPI
+3VM
SPI_CLK_PCH_R
SPI_SI
SPI_SI
4
1 2
1 2
1 2
1 2
1 2
1 2
if not supply SBA function R110 mount , R112 @
if supply SBA function R110 @,R112 mount
LPC_AD0 (38,40,41)
LPC_AD1 (38,40,41)
LPC_AD2 (38,40,41)
LPC_AD3 (38,40,41)
LPC_FRAME# (38,40,41)
+3VS
SERIRQ (40,41)
SATA_DTX_C_PRX_N0
SATA_DTX_C_PRX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA_DTX_C_PRX_N1
SATA_DTX_C_PRX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SATA_DTX_C_PRX_N2
SATA_DTX_C_PRX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
+1.05VS_PCH
+1.05VS_VCC_SATA
+1.05VS_SATA3
+3VS
ODD_DET# (36)
SPI_WP#1
SPI_HOLD#1
SPI_WP#
SPI_HOLD#
SPI_CLK_PCH_R
R104 3.3K_0402_5%R104 3.3K_0402_5%
R105 3.3K_0402_5%R105 3.3K_0402_5%
R334 3.3K_0402_5%R334 3.3K_0402_5%
R335 3.3K_0402_5%R335 3.3K_0402_5%
R119 33_0402_5%@R119 33_0402_5%@
Reserve for EMI please close to U3
SPI_CLK_PCH_R
Reserve for RF please close to U5, U6
C84 22P_0402_50V8JC84 22P_0402_50V8J
C85 22P_0402_50V8JC85 22P_0402_50V8J
9/28 RF modify
Title
Title
Title
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
SATA_DTX_C_PRX_N0 (36)
SATA_DTX_C_PRX_P0 (36)
SATA_PTX_DRX_N0 (36)
SATA_PTX_DRX_P0 (36)
SATA_DTX_C_PRX_N1 (36)
SATA_DTX_C_PRX_P1 (36)
SATA_PTX_DRX_N1 (36)
SATA_PTX_DRX_P1 (36)
SATA_DTX_C_PRX_N2 (38)
SATA_DTX_C_PRX_P2 (38)
SATA_PTX_DRX_N2 (38)
SATA_PTX_DRX_P2 (38)
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-8133P
LA-8133P
LA-8133P
5
+3VS_SPI
C78 22P_0402_50V8J@C78 22P_0402_50V8J@
1 2
HDD
ODD
m-SATA
13 58Friday, January 13, 2012
13 58Friday, January 13, 2012
13 58Friday, January 13, 2012
1.0
1.0
1.0
1
PCIE_PRX_DTX_N1(36)
Card Reader
Wireless LAN
A A
PCIE LAN
Card Reader
B B
Wireless LAN
PCIE LAN
+3VS
R170 10K_0402_5%R170 10K_0402_5%
1 2
R162 10K_0402_5%R162 10K_0402_5%
1 2
+3V_PCH
R177 10K_0402_5%R177 10K_0402_5%
C C
D D
1 2
R175 10K_0402_5%R175 10K_0402_5%
1 2
R181 10K_0402_5%R181 10K_0402_5%
1 2
R182 10K_0402_5%R182 10K_0402_5%
1 2
R159 10K_0402_5%R159 10K_0402_5%
1 2
R183 10K_0402_5%R183 10K_0402_5%
1 2
R184 10K_0402_5%@R184 10K_0402_5%@
1 2
PCIE_PRX_DTX_P1(36)
PCIE_PTX_C_DRX_N1(36)
PCIE_PTX_C_DRX_P1(36)
PCIE_PRX_DTX_N2(38)
PCIE_PRX_DTX_P2(38)
PCIE_PTX_C_DRX_N2(38)
PCIE_PTX_C_DRX_P2(38)
PCIE_PRX_DTX_N4(40)
PCIE_PRX_DTX_P4(40)
PCIE_PTX_C_DRX_N4(40)
PCIE_PTX_C_DRX_P4(40)
CLK_PCIE_CARD#(36)
CLK_PCIE_CARD(36)
CARD_CLKREQ#(36)
CLK_PCIE_WLAN1#(38)
CLK_PCIE_WLAN1(38)
WLAN_CLKREQ1#(38)
CLK_PCIE_LAN#(40)
CLK_PCIE_LAN(40)
LAN_CLKREQ#(40)
WLAN_CLKREQ1#
PCH_GPIO20
CARD_CLKREQ#
LAN_CLKREQ#
PCH_GPIO26
PCH_GPIO44
PCH_GPIO56
PCH_GPIO45
ON_ODD_DET
ON_ODD_DET(36)
CLK_XDP_CLK#(5)
CLK_XDP_CLK(5)
C86 0.1U_0402_10V7KC86 0.1U_0402_10V7K
1 2
C79 0.1U_0402_10V7KC79 0.1U_0402_10V7K
1 2
C82 0.1U_0402_10V7KC82 0.1U_0402_10V7K
1 2
C83 0.1U_0402_10V7KC83 0.1U_0402_10V7K
1 2
C80 0.1U_0402_10V7KC80 0.1U_0402_10V7K
1 2
C81 0.1U_0402_10V7KC81 0.1U_0402_10V7K
1 2
R147 0_0402_5%@R147 0_0402_5%@
1 2
R149 0_0402_5%@R149 0_0402_5%@
1 2
R141 0_0402_5%@R141 0_0402_5%@
1 2
R142 0_0402_5%@R142 0_0402_5%@
1 2
R145 0_0402_5%@R145 0_0402_5%@
1 2
R146 0_0402_5%@R146 0_0402_5%@
1 2
R164 0_0402_5%@R164 0_0402_5%@
1 2
R165 0_0402_5%@R165 0_0402_5%@
1 2
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
CLK_CARD#
CLK_CARD
CARD_CLKREQ#
CLK_MINI1#
CLK_MINI1
WLAN_CLKREQ1#
PCH_GPIO20
CLK_LAN#
CLK_LAN
LAN_CLKREQ#
PCH_GPIO26
PCH_GPIO44
PCH_GPIO56
PCH_GPIO45
ON_ODD_DET
CLK_BCLK_ITP#
CLK_BCLK_ITPCLK_BCLK_ITP
2
U3B
U3B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
P+
P+
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
P+/P-
P+/P-
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
P-
CLKOUTFLEX0 / GPIO64
P-
CLKOUTFLEX1 / GPIO65
P-
CLKOUTFLEX2 / GPIO66
P-
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
3
PCH_GPIO11
E12
PCH_SMBCLK
H14
PCH_SMBDATA
C9
DRAMRST_CNTRL_PCH
A12
PCH_SML0CLK
C8
PCH_SML0DATA
G12
PCH_HOT#
C13
PCH_SML1CLK
E14
PCH_SML1DATA
M16
M7
T11
P10
PCH_GPIO47
M10
AB37
AB38
CLK_CPU_DMI#
AV22
CLK_CPU_DMI
AU22
AM12
AM13
CLK_BUF_CPU_DMI#
BF18
CLK_BUF_CPU_DMI
BE18
CLKIN_DMI2#
BJ30
CLKIN_DMI2
BG30
CLK_BUF_DREF_96M#
G24
CLK_BUF_DREF_96M
E24
CLK_BUF_PCIE_SATA#
AK7
CLK_BUF_PCIE_SATA
AK5
CLK_BUF_ICH_14M
K45
CLK_PCI_LPBACK
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
PCH_GPIO64
K43
PCH_GPIO65
F47
LAN_25M
H47
PCH_GPIO67
K49
DIS@
R139 0_0402_5%@R139 0_0402_5%@
1 2
R140 10K_0402_5%@R140 10K_0402_5%@
1 2
DIS@
R144 0_0402_5%@R144 0_0402_5%@
1 2
DIS@
R151 0_0402_5%@R151 0_0402_5%@
1 2
R148 10K_0402_5%R148 10K_0402_5%
R150 10K_0402_5%R150 10K_0402_5%
R152 10K_0402_5%R152 10K_0402_5%
R153 10K_0402_5%R153 10K_0402_5%
R154 10K_0402_5%R154 10K_0402_5%
R155 10K_0402_5%R155 10K_0402_5%
R156 10K_0402_5%R156 10K_0402_5%
R157 10K_0402_5%R157 10K_0402_5%
R158 10K_0402_5%R158 10K_0402_5%
R160 90.9_0402_1%R160 90.9_0402_1%
R163 22_0402_5%@R163 22_0402_5%@
DRAMRST_CNTRL_PCH (6)
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+1.05VS_PCH
4
GPU_CLKREQA (22)
CLK_PCIE_VGA# (22)
CLK_PCIE_VGA (22)
CLK_CPU_DMI# (5)
CLK_CPU_DMI (5)
CLK_PCI_LPBACK (17)
+1.05VS_VCCDIFFCLKN
PCH_LAN_25M (40)
PCH_GPIO67 (18)
PLT_RST#(5,17,22,36,38,40,41)
PCH_SMBDATA
PCH_SMBCLK
PCH_SML1DATA
PCH_SML1CLK
C87
C87
18P_0402_50V8J
18P_0402_50V8J
+3VS
5
PCH_SMBCLK
PCH_SMBDATA
PCH_SML0CLK
PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
PCH_HOT#
PCH_GPIO11
DRAMRST_CNTRL_PCH
PCH_GPIO47
6 1
Q9A 2N7002KDWH_SOT363-6Q9A 2N7002KDWH_SOT363-6
Q9B 2N7002KDWH_SOT363-6Q9B 2N7002KDWH_SOT363-6
6 1
Q10A 2N7002KDWH_SOT363-6Q10A 2N7002KDWH_SOT363-6
Q10B 2N7002KDWH_SOT363-6Q10B 2N7002KDWH_SOT363-6
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
R128 2.2K_0402_5%R128 2.2K_0402_5%
R129 2.2K_0402_5%R129 2.2K_0402_5%
R130 2.2K_0402_5%R130 2.2K_0402_5%
R131 2.2K_0402_5%R131 2.2K_0402_5%
R126 2.2K_0402_5%R126 2.2K_0402_5%
R132 2.2K_0402_5%R132 2.2K_0402_5%
R133 10K_0402_5%R133 10K_0402_5%
R135 10K_0402_5%R135 10K_0402_5%
R127 1K_0402_5%R127 1K_0402_5%
R138 10K_0402_5%R138 10K_0402_5%
+3VS
R136 2.2K_0402_5%R136 2.2K_0402_5%
2
1 2
SMB_DATA_S3
R137 2.2K_0402_5%R137 2.2K_0402_5%
5
1 2
2
5
3 4
R168 33_0402_5%
R168 33_0402_5%
1 2
R169 33_0402_5%
R169 33_0402_5%
1 2
SMB_CLK_S3
EC_SMB_DA2
EC_SMB_CK2
@
@
@
@
3 4
+3VS
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Reserve for EMI please close to U60
XTAL25_IN
XTAL25_OUT
12
R172
R172
10K_0402_5%
10K_0402_5%
@
@
PLT_RST#
R161 1M_0402_5%R161 1M_0402_5%
1 2
Y2
Y2
25MHZ_20PF_ X3G025000DK1H
25MHZ_20PF_ X3G025000DK1H
1
1
1
2
1
2
3
4
GND
2
U8
U8
NC
VCC
NC
WP
SCL
PROT#
SDA
GND
PCA24S08D_SO8
PCA24S08D_SO8
EEPROM SA00004MK00
EEPROM SA00004ML00
GND
11/14
8
7
SMB_CLK_S3
6
SMB_DATA_S3
5
+3VS
SMB_DATA_S3 (11,12,38,39)
DDR, WALN, WWAN
+3VS
SMB_CLK_S3 (11,12,38,39)
Pull up at EC side.
EC_SMB_DA2 (22,39,41)
EC, VGA, Theraml
EC_SMB_CK2 (22,39,41)
C89 22P_0402_50V8J
C89 22P_0402_50V8J
@
@
1 2
C90 22P_0402_50V8J
C90 22P_0402_50V8J
@
@
1 2
3
3
4
ROM_WP
+3V_PCH
1
C88
C88
18P_0402_50V8J
18P_0402_50V8J
2
+3VS
1
C91
C91
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
LA-8133P
LA-8133P
LA-8133P
5
14 58Friday, January 13, 2012
14 58Friday, January 13, 2012
14 58Friday, January 13, 2012
1.0
1.0
1.0
1
DMI_CTX_PRX_N0(4)
A A
B B
C C
DMI_CTX_PRX_N1(4)
DMI_CTX_PRX_N2(4)
DMI_CTX_PRX_N3(4)
DMI_CTX_PRX_P0(4)
DMI_CTX_PRX_P1(4)
DMI_CTX_PRX_P2(4)
DMI_CTX_PRX_P3(4)
DMI_CRX_PTX_N0(4)
DMI_CRX_PTX_N1(4)
DMI_CRX_PTX_N2(4)
DMI_CRX_PTX_N3(4)
DMI_CRX_PTX_P0(4)
DMI_CRX_PTX_P1(4)
DMI_CRX_PTX_P2(4)
DMI_CRX_PTX_P3(4)
+1.05VS_VCC_EXP
XDP_DBRESET#(5)
PCH_PWROK(41)
PCH_APWROK(41)
PM_DRAM_PWRGD(5)
EC_RSMRST#(41)
PBTN_OUT#(5,41)
ACIN(40,41,44)
+1.05VS_PCH
R186 49.9_0402_1%R186 49.9_0402_1%
1 2
R188 750_0402_1%R188 750_0402_1%
1 2
4mil width and place
within 500mil of the PCH
R193 0_0402_5%@R193 0_0402_5%@
1 2
PCH_PWROK
R197 0_0402_5%R197 0_0402_5%
1 2
R198 0_0402_5%@R198 0_0402_5%@
1 2
R200 0_0402_5%R200 0_0402_5%
1 2
R203 0_0402_5%@R203 0_0402_5%@
1 2
D3
D3
1 2
2
T8T8
RB751V-40_SOD323-2
RB751V-40_SOD323-2
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_IRCOMP
RBIAS_CPY
SUSACK#_R
XDP_DBRESET#_R
SYS_PWROK
PCH_POK_R
APWROK
PM_DRAM_PWRGD
PCH_RSMRST#_R
SUSWARN#
AC_PRESENT_R
PCH_GPIO72
RI#
U3C
U3C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
P+
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
H20
E10
A10
P+
PWRBTN#
ACPRESENT / GPIO31
BATLOW# / GPIO72
RI#
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
BJ14
FDI_RXN0
AY14
FDI_RXN1
BE14
FDI_RXN2
BH13
FDI_RXN3
BC12
FDI_RXN4
BJ12
FDI_RXN5
BG10
FDI_RXN6
BG9
FDI_RXN7
BG14
FDI_RXP0
BB14
FDI_RXP1
BF14
FDI_RXP2
BG13
FDI_RXP3
BE12
FDI_RXP4
BG12
FDI_RXP5
BJ10
FDI_RXP6
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
DMI
FDI
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
System Power Management
P-
P+
SLP_LAN# / GPIO29
3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_DPWROK_R
WAKE#
PM_CLKRUN#
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PCH_SLPA#
PM_SLP_SUS#
H_PM_SYNC
PCH_GPIO29
R189 0_0402_5%@R189 0_0402_5%@
1 2
R194 0_0402_5%@R194 0_0402_5%@
1 2
FDI_CTX_PRX_N0 (4)
FDI_CTX_PRX_N1 (4)
FDI_CTX_PRX_N2 (4)
FDI_CTX_PRX_N3 (4)
FDI_CTX_PRX_N4 (4)
FDI_CTX_PRX_N5 (4)
FDI_CTX_PRX_N6 (4)
FDI_CTX_PRX_N7 (4)
FDI_CTX_PRX_P0 (4)
FDI_CTX_PRX_P1 (4)
FDI_CTX_PRX_P2 (4)
FDI_CTX_PRX_P3 (4)
FDI_CTX_PRX_P4 (4)
FDI_CTX_PRX_P5 (4)
FDI_CTX_PRX_P6 (4)
FDI_CTX_PRX_P7 (4)
FDI_INT (4)
FDI_FSYNC0 (4)
FDI_FSYNC1 (4)
FDI_LSYNC0 (4)
FDI_LSYNC1 (4)
PCH_RSMRST#_R
PCIE_WAKE# (40)
PM_CLKRUN# (40)
SUSCLK (41)
T11T11
PM_SLP_S5# (41)
T12T12
PM_SLP_S4# (41)
T13T13
PM_SLP_S3# (41)
PCH_SLPA# (41)
T14T14
PM_SLP_SUS# (41)
T15T15
H_PM_SYNC (5)
4
DSWODVREN
DSWODVREN - On Die DSW VR Enable
HEnable
*
LDisable
WAKE#
PCH_GPIO29
PM_CLKRUN#
EC team suggestion
South Bridge side must have
pull-low 10K on this pin(GPIO32)
Use CLKRUN# Requires a 8.2- k weak
pull-up resistor to Vcc3_3S
Can be left NC when
IAMT is not support on
the platfrom
5
R185 330K_0402_5%R185 330K_0402_5%
1 2
R187 330K_0402_5%@R187 330K_0402_5%@
1 2
R192 10K_0402_5%R192 10K_0402_5%
1 2
R195 10K_0402_5%@R195 10K_0402_5%@
1 2
R196 8.2K_0402_5%R196 8.2K_0402_5%
1 2
R199 10K_0402_5%@R199 10K_0402_5%@
1 2
+RTCVCC
+3V_PCH
+3VS
+3VS
U9
U9
+3VS
R204 200_0402_5%@R204 200_0402_5%@
1 2
+3V_PCH
1
PM_DRAM_PWRGD
SUSWARN#
AC_PRESENT_R
PCH_GPIO72
RI#
PCH_RSMRST#_R
2
R305 200_0402_5%@R305 200_0402_5%@
1 2
R205 10K_0402_5%R205 10K_0402_5%
D D
1 2
R206 200K_0402_5%R206 200K_0402_5%
1 2
R207 10K_0402_5%R207 10K_0402_5%
1 2
R208 10K_0402_5%R208 10K_0402_5%
1 2
R210 10K_0402_5%R210 10K_0402_5%
1 2
VGATE(52)
PCH_PWROKPM_DRAM_PWRGD
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
5
1
VCC
IN1
2
IN2
SYS_PWROK
4
OUT
GND
3
12
R211
R211
100K_0402_5%
100K_0402_5%
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
SYS_PWROK (5)
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM,
PCH (3/8) DMI,FDI,PM,
PCH (3/8) DMI,FDI,PM,
LA-8133P
LA-8133P
LA-8133P
5
15 58Friday, January 13, 2012
15 58Friday, January 13, 2012
15 58Friday, January 13, 2012
1.0
1.0
1.0
1
A A
ENBKL(41)
+3VS
B B
+3VS
R218 2.2K_0402_5%R218 2.2K_0402_5%
C C
1 2
R219 2.2K_0402_5%R219 2.2K_0402_5%
1 2
R220 150_0402_1%R220 150_0402_1%
1 2
R221 150_0402_1%R221 150_0402_1%
1 2
R222 150_0402_1%R222 150_0402_1%
1 2
CRT_DDC_CLK
CRT_DDC_DATA
DAC_BLU
DAC_GRN
DAC_RED
2
PCH_ENVDD(32)
PCH_PWM(32)
EDID_CLK(32)
EDID_DATA(32)
LVDS_ACLK#(32)
LVDS_ACLK(32)
LVDS_A0#(32)
LVDS_A1#(32)
LVDS_A2#(32)
LVDS_A0(32)
LVDS_A1(32)
LVDS_A2(32)
LVDS_BCLK#(32)
LVDS_BCLK(32)
LVDS_B0#(32)
LVDS_B1#(32)
LVDS_B2#(32)
LVDS_B0(32)
LVDS_B1(32)
LVDS_B2(32)
DAC_BLU(33)
DAC_GRN(33)
DAC_RED(33)
CRT_DDC_CLK(33)
CRT_DDC_DATA(33)
CRT_HSYNC(33)
CRT_VSYNC(33)
1 2
1 2
1 2
1 2
1 2
1 2
1 2
3
R253100K_0402_5% R253100K_0402_5%
PCH_ENBKL
R2520_0402_5% @ R2520_0402_5% @
CTRL_CLK
R2122.2K_0402_5% R2122.2K_0402_5%
CTRL_DATA
R2132.2K_0402_5% R2132.2K_0402_5%
LVDS_IBG
R2152.37K_0402_1% R2152.37K_0402_1%
LVD_VREF
R2170_0402_5% @ R2170_0402_5% @
DAC_BLU
DAC_GRN
DAC_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
CRT_IREF
R2231K_0402_0.5% R2231K_0402_0.5%
U3D
U3D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
P-
SDVO_TVCLKINN
P-
SDVO_TVCLKINP
P-
SDVO_STALLN
P-
P-
LVDS
LVDS
CRT
CRT
SDVO_STALLP
P-
SDVO_INTN
P-
SDVO_INTP
SDVO_CTRLCLK
P-
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
P-
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
P-
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
4
HDMICLK_NB (34)
HDMIDAT_NB (34)
PCH_DPB_HPD (34)
PCH_DPB_N0 (34)
PCH_DPB_P0 (34)
PCH_DPB_N1 (34)
PCH_DPB_P1 (34)
PCH_DPB_N2 (34)
PCH_DPB_P2 (34)
PCH_DPB_N3 (34)
PCH_DPB_P3 (34)
5
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
LA-8133P
LA-8133P
LA-8133P
5
16 58Friday, January 13, 2012
16 58Friday, January 13, 2012
16 58Friday, January 13, 2012
1.0
1.0
1.0
1
+3VS
R225
R225
1 8
2 7
3 6
4 5
8.2K_8P4R_5%
8.2K_8P4R_5%
R228
R228
1 8
2 7
3 6
A A
B B
4 5
8.2K_8P4R_5%
8.2K_8P4R_5%
R227
R227
1 8
2 7
3 6
4 5
8.2K_8P4R_5%
8.2K_8P4R_5%
R230 8.2K_0402_5%R230 8.2K_0402_5%
1 2
R231 8.2K_0402_5%R231 8.2K_0402_5%
1 2
R246 8.2K_0402_5%R246 8.2K_0402_5%
1 2
R244 8.2K_0402_5%@R244 8.2K_0402_5%@
1 2
R232 8.2K_0402_5%@R232 8.2K_0402_5%@
1 2
R234 100K_0402_5%@R234 100K_0402_5%@
1 2
R243 1K_0402_5%@R243 1K_0402_5%@
1 2
Boot BIOS Strap bit1 BBS1
Bit11
0
1
1
0
R245 1K_0402_5%@R245 1K_0402_5%@
1 2
A16 swap overide Strap/Top-Block
C C
Swap Override jumper
PCI_GNT3#
Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default
RF Boris Tsai suggests
GPIO19GPIO51
1 2
1 2
1 2
Bit10
1
0
1
0
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQA#
PCH_GPIO52
PCH_GPIO5
PCH_GPIO51
PCH_GPIO53
ODD_DA#
PCH_GPIO4
PCH_GPIO2
PCH_GPIO55
PCH_GPIO50
PCH_GPIO54
PCH_GPIO54
PCH_GPIO50
PCH_PLTRST#
PCH_GPIO51
Boot BIOS
Destination
*
PCH_GPIO55
*
CLK_PCI_TPM
C11910P_0402_50V8J C11910P_0402_50V8J
CLK_PCI_LPBACK
C9210P_0402_50V8J @ C9210P_0402_50V8J @
CLK_PCI_EC
C9310P_0402_50V8J C9310P_0402_50V8J
Reserved
PCI
(Default)
SPI
LPC
USB3_RX1_N(37)
USB3_RX2_N(37)
USB3_RX3_N(37)
USB3_RX1_P(37)
USB3_RX2_P(37)
USB3_RX3_P(37)
USB3_TX1_N(37)
USB3_TX2_N(37)
USB3_TX3_N(37)
USB3_TX1_P(37)
USB3_TX2_P(37)
USB3_TX3_P(37)
DGPU_HOLD_RST#(22)
NVDD_PWR_EN(51)
DGPU_PWR_EN(22,24)
BT_DET#(38)
ODD_DA#(36)
PCI_PME#(41)
PCH_PLTRST#(5)
CLK_PCI_LPBACK(14)
CLK_PCI_EC(41)
CLK_PCI_DB(38,40)
CLK_PCI_TPM(40)
2
CLK_PCI_EC
DIS@
DIS@
DIS@
R254 0_0402_5%@R254 0_0402_5%@
1 2
R348 0_0402_5%@R348 0_0402_5%@
1 2
R264 0_0402_5%@R264 0_0402_5%@
1 2
R332 0_0402_5%@R332 0_0402_5%@
1 2
R248 22_0402_5%R248 22_0402_5%
1 2
R249 22_0402_5%R249 22_0402_5%
1 2
R250 22_0402_5%R250 22_0402_5%
1 2
R350 22_0402_5%
R350 22_0402_5%
1 2
TPM@
TPM@
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCH_GPIO50
PCH_GPIO52
PCH_GPIO54
PCH_GPIO51
PCH_GPIO53
PCH_GPIO55
PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5
PCH_PLTRST#
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
U3E
U3E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3Tp1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
PCH_PLTRST#
TC7SH08FUF_SSOP5
TC7SH08FUF_SSOP5
3
RSVD
RSVD
P-
PCI
PCI
USB
USB
P+
P+
P+
P+
PPPPP-
R251 0_0402_5%R251 0_0402_5%
1 2
+3VS
5
U11
U11
1
P
B
Y
2
A
G
@
@
3
4
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
12
R255
R255
100K_0402_5%
100K_0402_5%
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
PCH HM65 config not support USB port 6 & 7.
C24
A24
USB20_N1
C25
USB20_P1
B25
USB20_N2
C26
USB20_P2
A26
USB20_N3
K28
USB20_P3
H28
E28
D28
USB20_N5
C28
USB20_P5
A28
C29
B29
N28
M28
L30
K30
USB20_N9
G30
USB20_P9
E30
USB20_N10
C30
USB20_P10
A30
USB20_N11
L32
USB20_P11
K32
USB20_N12
G32
USB20_P12
E32
USB20_N13
C32
USB20_P13
A32
USBRBIAS
C33
B33
USB_OC0#
A14
USB_OC1#
K20
USB_OC2#
B17
USB_OC3#
C16
USB_OC4#
L16
USB_OC5#
A16
USB_OC6#
D14
USB_OC7#
C14
PLT_RST# (5,14,22,36,38,40,41)
Within 500 mils
R247 22.6_0402_1%R247 22.6_0402_1%
1 2
USB20_N1 (37)
USB20_P1 (37)
USB20_N2 (37)
USB20_P2 (37)
USB20_N3 (37)
USB20_P3 (37)
USB20_N5 (32)
USB20_P5 (32)
USB20_N9 (39)
USB20_P9 (39)
USB20_N10 (38)
USB20_P10 (38)
USB20_N11 (40)
USB20_P11 (40)
USB20_N12 (38)
USB20_P12 (38)
USB20_N13 (38)
USB20_P13 (38)
USB_OC0# (37)
USB_OC1# (37)
USB_OC4# (39)
4
USB 3.0
USB 3.0
USB 3.0
CMOS Camera (LVDS)
USB 2.0
Mini Card(WLAN/BT)
FingerPrint
Mini Card(WWAN)
Bluetooth Module
(To USB S/B)
OC[0..3] use for EHCI 1
OC[4..7] use for EHCI 2
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
R233
R233
1 8
2 7
3 6
4 5
10K_8P4R_5%
10K_8P4R_5%
R235
R235
1 8
2 7
3 6
4 5
10K_8P4R_5%
10K_8P4R_5%
5
+3V_PCH
D D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (5/9) PCI, USB, NVRAM
PCH (5/9) PCI, USB, NVRAM
PCH (5/9) PCI, USB, NVRAM
LA-8133P
LA-8133P
LA-8133P
5
17 58Friday, January 13, 2012
17 58Friday, January 13, 2012
17 58Friday, January 13, 2012
1.0
1.0
1.0
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
HOn-Die voltage regulator enable
*
LOn-Die PLL Voltage Regulator disable
R265 1K_0402_5%@R265 1K_0402_5%@
1 2
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
A A
HOn-Die voltage regulator enable
*
LOn-Die PLL Voltage Regulator disable
R274 1K_0402_5%@R274 1K_0402_5%@
1 2
+3VS
R280 10K_0402_5%@R280 10K_0402_5%@
1 2
R282 10K_0402_5%R282 10K_0402_5%
1 2
+3V_PCH
R288 10K_0402_5%R288 10K_0402_5%
1 2
R290 10K_0402_5%@R290 10K_0402_5%@
1 2
+3VS
R285 10K_0402_5%@R285 10K_0402_5%@
1 2
R284 10K_0402_5%R284 10K_0402_5%
1 2
+3VS
R269 10K_0402_5%R269 10K_0402_5%
B B
+3V_PCH
C C
1 2
R270 10K_0402_5%R270 10K_0402_5%
1 2
R266 10K_0402_5%R266 10K_0402_5%
1 2
R344 10K_0402_5%@R344 10K_0402_5%@
1 2
R275 10K_0402_5%R275 10K_0402_5%
1 2
R268 10K_0402_5%R268 10K_0402_5%
1 2
R277 10K_0402_5%R277 10K_0402_5%
1 2
R346 10K_0402_5%R346 10K_0402_5%
1 2
R283 10K_0402_5%R283 10K_0402_5%
1 2
R287 10K_0402_5%R287 10K_0402_5%
1 2
R289 10K_0402_5%R289 10K_0402_5%
1 2
R291 10K_0402_5%R291 10K_0402_5%
1 2
R345 10K_0402_5%R345 10K_0402_5%
1 2
R271 10K_0402_5%R271 10K_0402_5%
1 2
R273 1K_0402_5%R273 1K_0402_5%
1 2
R347 10K_0402_5%R347 10K_0402_5%
1 2
R292 10K_0402_5%@R292 10K_0402_5%@
1 2
1
PCH_GPIO28
EC_SMI#
WLBT_OFF_51#
PCH_GPIO24
PCH_GPIO37
PCH_GPIO0
PCH_GPIO1
PCH_GPIO6
EC_SCI#
PCH_GPIO16
DGPU_PWROK
PCH_GPIO22
BT_ON#
3G_DET#
3G_OFF#
PCH_GPIO48
PCH_GPIO49
EC_SMI#
PCH_GPIO12
PCH_GPIO15
PCH_GPIO28
PCH_GPIO57
EC_SCI#(41)
EC_SMI#(41)
DGPU_PWROK(24,51)
EC_WAKE#(41)
BT_ON#(38)
3G_DET#(38)
WLBT_OFF_51#(38)
3G_OFF#(38)
mSATA_PCH(38)
mSATA_DETEC#(41)
GPIO34
For Edge code setting
PCH_GPIO69
PCH_GPIO38 PCH_GPIO67
Function
2
EC_WAKE#
R293 0_0402_5%@R293 0_0402_5%@
R294 10K_0402_5%R294 10K_0402_5%
R178 0_0402_5%@R178 0_0402_5%@
1 2
R167 0_0402_5%R167 0_0402_5%
1 2
1 2
1 2
PCH_GPIO0
PCH_GPIO1
PCH_GPIO6
EC_SCI#
EC_SMI#
PCH_GPIO12
PCH_GPIO15
PCH_GPIO16
DGPU_PWROK
PCH_GPIO22
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
BT_ON#
3G_DET#
WLBT_OFF_51#
PCH_GPIO37
PCH_GPIO38
3G_OFF#
PCH_GPIO48
PCH_GPIO49
PCH_GPIO57
T22T22
T24T24
T26
T28
T30T30
T32T32
T34T34
T36
T38T38
T40T40
T42T42
T44T44
T46T46
T48T48
U3F
U3F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
D40
E16
V13
A44
A45
A46
B47
BD1
BD49
BE1
BE49
BF1
BF49
P+
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
P-
GPIO15
U2
SATA4GP / GPIO16
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
P+
GPIO27
P8
P+
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
3
ODD_EN#
A20GATE
P-
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
C40
PCH_GPIO69
B41
PCH_GPIO70
C41
PCH_GPIO71
A40
P4
PCH_PECI_R
AU16
KB_RST#
P5
H_CPUPWRGD
AY11
R278 390_0402_5%R278 390_0402_5%
AY10
1 2
T14
DF_TVS
AY1
AH8
AK11
AH10
AK10
P37
BG2
T18T18
BG48
T19T19
BH3
T20T20
BH47
T21T21
BJ4
T23T23
BJ44
T25T25
BJ45
T27T27
BJ46
T29T29
BJ5
T31T31
BJ6
T33T33
C2
T35T35
T37
C48
D1
T39T39
T41
D49
E1
T43T43
T45
E49
F1
T47T47
T49
F49
R267 0_0402_5%@R267 0_0402_5%@
1 2
INIT3_3V
This signal has weak internal
PU, can't pull low
Intel schematic reviwe recommand.
P+
GPIO
GPIO
P+
P+
P+
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
P+
P+
P+
P+
P-
CPU/MISC
CPU/MISC
PP-
NCTF
NCTF
H_THRMTRIP#
4
ODD_EN# (36)
GATEA20 (41)
H_PECI (5,41)
KB_RST# (41)
H_CPUPWRGD (5)
H_THRMTRIP# (5)
VGA_THRMTRIP# (22)
5
ODD_EN#
PCH_GPIO70
PCH_GPIO71
GATEA20
KB_RST#
DF_TVS
R256 8.2K_0402_5%R256 8.2K_0402_5%
1 2
R260 8.2K_0402_5%@R260 8.2K_0402_5%@
1 2
R258 10K_0402_5%R258 10K_0402_5%
R262 10K_0402_5%@R262 10K_0402_5%@
1 2
R257 10K_0402_5%R257 10K_0402_5%
R263 10K_0402_5%@R263 10K_0402_5%@
1 2
R272 10K_0402_5%R272 10K_0402_5%
1 2
R276 10K_0402_5%R276 10K_0402_5%
1 2
R229 1K_0402_5%R229 1K_0402_5%
1 2
DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
CLOSE TO THE BRANCHING POINT
12
12
+1.8VS
12
R226
R226
2.2K_0402_5%
2.2K_0402_5%
+3VS
+3VS
+3VS
+3VS
H_SNB_IVB# (5)
0
0
0
0
12
R259
R259
10K_0402_5%
D D
10K_0402_5%
@
@
12
R261
R261
10K_0402_5%
10K_0402_5%
0
0 1
1
1 1
+3VS
12
R330
R330
10K_0402_5%
10K_0402_5%
UMA@
UMA@
12
R329
R329
10K_0402_5%
10K_0402_5%
DIS@
DIS@
0
Optimus
Reserved
0
DIS
UMA
12
R311
R311
10K_0402_5%
10K_0402_5%
UMA@
UMA@
PCH_GPIO69
PCH_GPIO38
PCH_GPIO67
12
R286
R286
10K_0402_5%
10K_0402_5%
DIS@
DIS@
1
PCH_GPIO67 (14)
(MB_ID_2)
(MB_ID_1)
(MB_ID_0)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/07/12 2012/07/01
2011/07/12 2012/07/01
2011/07/12 2012/07/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
LA-8133P
LA-8133P
LA-8133P
5
18 58Friday, January 13, 2012
18 58Friday, January 13, 2012
18 58Friday, January 13, 2012
1.0
1.0
1.0
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