Compal LA-7984P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

QIWG5/QIWG6 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH

nVIDIA N13X

2011-11-08

3 3

LA-7984P

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-7984P

E

160Tuesday, December 06, 2011

0.1

of

A

Compal confidential

File Name : QIWG5/QIWG6

Page23‐32

B

C

D

ZZZ

LA7981

DA_PCB

DA80000Q000

E

QIWG5

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B

1 1

nVIDIA N13M-GE nVIDIA N13P-GL

Intel

Ivy Bridge

VRAM 128*16

DDR3*8

PCI-E x16

Socket-rPGA988B

37.5mm*37.5mm

HDMI Connector

CRT

2 2

Connector LVDS

Connector

Page35

Page34

Page33

100MHz

2.7GT/s

FDI *8

Intel

Panther Point

HM75 / HM76

Page5‐11

Dual Channel DDR3 1066MHz(1.5V) DDR3 1333MHz(1.5V) DDR3 1600MHz(1.5V)

DMI *4

AZALIA

FCBGA 989

USB3.0 *2(Left)

Option

Page45

PCI-E x1 *6

USB3.0

Renesas

uPD720202

3 3

Realtek

RTL8111F(GLAN) RTL8105E(10/100)

Page37

SPIROM BIOS

Page14

25mm*25mm

Page14‐22

LPC BUS

Page42

EC

ENE KB9012

USB2.0 *14

SATA *6

DDR3 SO-DIMM *2

BANK 0, 1, 2, 3

Up to 8GB

Page12‐13

Audio Codec Conexant

CX20671-21Z

Page41

Camera Conn. BlueTooth Conn. Mini Card Slot *1 Card Reader

Reltek

RTS5178 for SDR50 SDXC/MMC

2 channel speaker Int. MIC x1 Audio Jacks

Page33

Page40

Page36

Page43

Page41

Page43

QIWG6

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B LS7984P LED/B LS7985P ODD/B

USB2.0 *2(Right) RJ-45 Connector

PCI Express

Mini Card Slot *1

WLAN

4 4

Page38

Page36

PCI-E(WLAN)

Touch Pad Int. KBD

Page43

Thermal Sensor

EMC1403

Page39

Page43

USB2.0 *2(Left)

SATA HDD SATA ODD

Page43;44

Page45

Page40

(Port 0/Port 1 support SATA3)

www.schematic-x.blogspot.com

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-7984P

E

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Voltage Rails

power

State

S0

S3

S5 S4/AC

Device

Smart Battery

plane

Address

0001 011X b

+B

O

O O O

X

+5VALW

+3VALW

O

O O

X XX X

+1.5V

EC SM Bus2 address

Device

Thermal Sensor F75303M

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

EC SM Bus1 address

PCH SM Bus address

Device Address

DDR DIMM0

3 3

DDR DIMM2

1001 000Xb 1001 010Xb

NV-GPU SM Bus address

Device Address

Internal thermal sensor

1001 111Xb (0x9E)

B

+5VS +3VS +1.5VS +V1.05S_VCCP +VCC_CORE +VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS +1.05VS

Board ID

OO

O

X XX X

X

Address

1001_101xb

USB Port Table

EHCI1

USB3.0

EHCI2

0 1 2 3 4 5 6 7

USB 2.0 Port

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

C

PCB Revision

0.1

3 External USB Port

0

USB Port (Right Side CR-BD)

1 2

USB Port (Left Side)

3

USB Port (Left Side)

4 5

Camera

6 7 8

USB/B (Right Side USB-BD)

9

10

Mini Card(WLAN)

11

Card Reader

12 13

Blue Tooth

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

Board ID / SKU ID Table for AD channelBOARD ID Table

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

USB3.0 USB3.0

D

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

0

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGHHIGHHIGH

LOW

HIGH

LOWLOWLOW

HIGH

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

BOM Structure Table

BTO Item BOM Structure

HDMI HDMI@ Interna-Intel-USB3.0 IU3@ External-NEC-USB3.0 EU3@ Blue Tooth BT@ Connector ME@ 45 LEVEL 45@ 10/100 LAN 8162@ GIGA LAN GIGA@ LAN LDO Mode LDO@ LAN Switch mode SWR@ Cameara CMOS@ For QIWG5 (14") 14@ For QIWG6 (15") 15@ Unpop

ON

OFF

ON

OFF

ON

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

N13P@ GPU:N13P-GL N13M@GPU:N13M-GE

@

E

ON ON

ON

OFF

max

LOW

OFF

Porject Phase

G-series

MP

G-series

PVT

G-series

DVT

G-series

EVT

Y-series

EVT

Y-series

DVT

Y-series

PVT

Y-series

MP

SMBUS Control Table

X X

V

+3VS

X

WLAN WWAN

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2

4 4

SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012 SODIMM

X V

+3VALW

X X X

V

+3VS

A

X X X

X

X X

V

+3VS

X XX

V

+3VS

X

B

Thermal Sensor

X X X XX

V

+3VS

PCH

X

V

+3VS

X X XXX

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

LA-7984P

Date: Sheet

Compal Electronics, Inc.

Notes List

of

360Tuesday, December 06, 2011

E

0.1

5

4

3

2

1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails (N13x GPIO)

GPIO I/O ACTIVE Function Description GPIO0

D D

GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10

C C

GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19

B B

+1.05VS_VGA

OUT GPU VID4-

OUT OUT OUT OUT OUT OUT I/O OUT OUT

IN OUT OUT IN OUT IN IN IN

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

-

GPU VID3OUT

H

Panel Back-Light brightness(PWM capable)

H

Panel Power Enable

H

Panel Back-Light On/Off (PWM) GPU VID1

GPU VID2

-

N/A

-

Thermal Catastrophic Over Temperature

-

Thermal Alert

-

Memory VREF Control GPU VID0-OUT AC Power Detect Input GPU VID5-

N/A

Hot plug detect for IFP link C

N/A N/A

Hot Plug Detect for IFPE

N/A

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

(10K pull low)

Performance Mode P0 TDP at Tj = 102 C* (GDDR3)

GPU Mem

Products

N13P-GL 64bit 1GB GDDR3

Physical Strapping pin ROM_SCLK

(4) (1,5) (6) (W) (W) (MHz)

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

ROM_SI ROM_SO FB[0] STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

NVCLK /MCLK NVVDD

TBD TBD

Power Rail

+3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA

(V) (A) (W) (A) (W)

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] SOR3_EXPOSED

RESERVED PCIE_SPEED_

FBVDD

Logical Strapping Bit2 SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

FBVDDQ (GPU+Mem) (1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

Device ID

N13P-GL (28nm)

N13M-GE (28nm)

GPU STRAP2 STRAP1 STRAP0

N13P-GL N13M-GE

???

FB Memory (GDDR3)

Samsung 2500MHz

Hynix 2500MHz

Samsung 2500MHz

2500MHz

K4G10325FG-HC04

H5GQ1H24BFR-T2C

K4G20325FG-HC04

H5GQ2H24MFR-T2CHynix

ROM_SO

32Mx32

32Mx32 PD 15K

PD 10K PU 20K

64Mx32

ROM_SCLK ROM_SI

PD 15K

PD 15K PD 35KPU 20KPD 10K PD 20K PU 45K

PCI Express (1.05V)

Logical Strapping Bit1

SLOT_CLK_CFG RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

I/O and PLLVDD

Logical Strapping Bit0

PEX_PLL_EN_TERM RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

SOR0_EXPOSED

PCIE_MAX_SPEED DP_PLL_VDD33V

PD 20KPD 10K PU 45K

PU 20K

X76

I/O and PLLVDD

PD 35K

Other (3.3V)(1.05V)(1.8V)

PU 45K

1. all power rail ramp up time should be larger than 40us

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

A A

1.all GPU power rails should be turned off within 10ms

5

Tpower-off <10ms

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA Notes List

VGA Notes List LA-7984P

LA-7984P

460Tuesday, December 06, 2011

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5

D D

DMI_CRX_PTX_N0<16> DMI_CRX_PTX_N1<16> DMI_CRX_PTX_N2<16> DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16> DMI_CRX_PTX_P1<16> DMI_CRX_PTX_P2<16> DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16> DMI_CTX_PRX_N1<16> DMI_CTX_PRX_N2<16> DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16> DMI_CTX_PRX_P1<16> DMI_CTX_PRX_P2<16> DMI_CTX_PRX_P3<16>

C C

+V1.05S_VCCP

12

R7

24.9_0402_1%

B B

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

FDI_CTX_PRX_N0<16> FDI_CTX_PRX_N1<16> FDI_CTX_PRX_N2<16> FDI_CTX_PRX_N3<16> FDI_CTX_PRX_N4<16> FDI_CTX_PRX_N5<16> FDI_CTX_PRX_N6<16> FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16> FDI_CTX_PRX_P1<16> FDI_CTX_PRX_P2<16> FDI_CTX_PRX_P3<16> FDI_CTX_PRX_P4<16> FDI_CTX_PRX_P5<16> FDI_CTX_PRX_P6<16> FDI_CTX_PRX_P7<16>

FDI_FSYNC0<16> FDI_FSYNC1<16>

FDI_LSYNC0<16> FDI_LSYNC1<16>

4

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

eDP_HPD

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

FDI_INT<16>

EDP_COMP

DMI

Intel(R) FDI

eDP

3

+V1.05S_VCCP

12

R1

24.9_0402_1%

PEG_COMP

PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10

PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0

PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0

PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0

PCIE_CRX_GTX_N[0..15] <23>

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

PCIE_CRX_GTX_P[0..15] <23>

C1 0.22U_0402_10V6KC1 0.22U_0402_10V6K

1 2

C2 0.22U_0402_10V6KC2 0.22U_0402_10V6K

1 2

C3 0.22U_0402_10V6KC3 0.22U_0402_10V6K

1 2

C4 0.22U_0402_10V6KC4 0.22U_0402_10V6K

1 2

C5 0.22U_0402_10V6KC5 0.22U_0402_10V6K

1 2

C6 0.22U_0402_10V6KC6 0.22U_0402_10V6K

1 2

C7 0.22U_0402_10V6KC7 0.22U_0402_10V6K

1 2

C8 0.22U_0402_10V6KC8 0.22U_0402_10V6K

1 2

C9 0.22U_0402_10V6KC9 0.22U_0402_10V6K

1 2

C10 0.22U_0402_10V6KC10 0.22U_0402_10V6K

1 2

C11 0.22U_0402_10V6KC11 0.22U_0402_10V6K

1 2

C12 0.22U_0402_10V6KC12 0.22U_0402_10V6K

1 2

C13 0.22U_0402_10V6KC13 0.22U_0402_10V6K

1 2

C14 0.22U_0402_10V6KC14 0.22U_0402_10V6K

1 2

C15 0.22U_0402_10V6KC15 0.22U_0402_10V6K

1 2

C16 0.22U_0402_10V6KC16 0.22U_0402_10V6K

1 2

C17 0.22U_0402_10V6KC17 0.22U_0402_10V6K

1 2

C18 0.22U_0402_10V6KC18 0.22U_0402_10V6K

1 2

C19 0.22U_0402_10V6KC19 0.22U_0402_10V6K

1 2

C20 0.22U_0402_10V6KC20 0.22U_0402_10V6K

1 2

C21 0.22U_0402_10V6KC21 0.22U_0402_10V6K

1 2

C22 0.22U_0402_10V6KC22 0.22U_0402_10V6K

1 2

C23 0.22U_0402_10V6KC23 0.22U_0402_10V6K

1 2

C24 0.22U_0402_10V6KC24 0.22U_0402_10V6K

1 2

C25 0.22U_0402_10V6KC25 0.22U_0402_10V6K

1 2

C26 0.22U_0402_10V6KC26 0.22U_0402_10V6K

1 2

C27 0.22U_0402_10V6KC27 0.22U_0402_10V6K

1 2

C28 0.22U_0402_10V6KC28 0.22U_0402_10V6K

1 2

C29 0.22U_0402_10V6KC29 0.22U_0402_10V6K

1 2

C30 0.22U_0402_10V6KC30 0.22U_0402_10V6K

1 2

C31 0.22U_0402_10V6KC31 0.22U_0402_10V6K

1 2

C32 0.22U_0402_10V6KC32 0.22U_0402_10V6K

1 2

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

2

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0

PCIE_CTX_GRX_N[0..15] <23>

PCIE_CTX_GRX_P[0..15] <23>

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

Compal Secret Data

3

Deciphered Date

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

2

Date: Sheet

560Tuesday, December 06, 2011

1

0.1

of

5

D D

+V1.05S_VCCP

12

R9

62_0402_5%

H_PROCHOT#<42,48>

C C

H_CPUPWRGD<19>

H_PROCHOT#

R260_0402_5% R260_0402_5%

1 2

@ C549

@

100P_0402_50V8J

EMI Reserve

C549

H_PM_SYNC<16>

R27

1

10K_0402_5%

1 2

2

4

JCPU1B

H_SNB_IVB#<19>

H_PROCHOT#_R

R22

H_CPUPWRGD_R

PM_DRAM_PWRGD_R

BUF_CPU_RST#

H_CATERR#

H_PM_SYNC_R

T48T48

H_PECI<19,42>

R15

56_0402_5%

1 2

H_THRMTRIP#<19>

1 2

0_0402_5%

R29

1 2

130_0402_5%

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

V8

AR33

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

3

A28

BCLK

A27

BCLK#

PRDY#

PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

A16 A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28

TDI

AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

2

R10;R11 put on U4 side

0_0402_5%

CLK_CPU_DMI_R CLK_CPU_DMII#_R

R12 1K_0402_5%R12 1K_0402_5% R13 1K_0402_5%R13 1K_0402_5%

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

12 12

R16 140_0402_1%R16 140_0402_1% R17 25.5_0402_1%R17 25.5_0402_1% R18 200_0402_1%R18 200_0402_1%

0_0402_5%

R10

1 2 1 2

R11

0_0402_5%

H_DRAMRST# <7>

12 12 12

+V1.05S_VCCP

DDR3 Compensation Signals

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TDO XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

T97T97 T98T98

R28 1K_0402_5%R28 1K_0402_5%

12

T49T49 T90T90 T91T91 T92T92 T93T93 T94T94 T95T95 T96T96

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

XDP_TMS

R20 51_0402_5%R20 51_0402_5%

XDP_TDI

R21 51_0402_5%R21 51_0402_5% R23 51_0402_5%@R23 51_0402_5%@

XDP_TCK

R24 51_0402_5%R24 51_0402_5%

XDP_TRST#

R25 51_0402_5%R25 51_0402_5%

+3VS

1

+V1.05S_VCCP

12 12 12

12 12

PU/PD for JTAG signals

TYCO_2013620-2_IVY BRIDGE

+3VALW

1

C33

0.1U_0402_16V4Z

B B

SYS_PWROK<16>

A A

R880

@R880

@

1 2

0_0402_5%

R161

1 2

+3VS

10K_0402_5%

PM_DRAM_PWRGD<16>

RUN_ON_CPU1.5VS3#<10>

5

2

U1

5

1

P

B

2

A

G

74AHC1G09GW_TSSOP5

3

PM_SYS_PWRGD_BUF

4

O

2

G

+1.5V_CPU_VDDQ

12

@

R33

R33 39_0402_5%

39_0402_5%

13

D

Q1

@

Q1

@

2N7002H_SOT23-3

S

12

R30

R30 200_0402_5%

200_0402_5%

BUF_CPU_RST#

4

TYCO_2013620-2_IVY BRIDGE

12

R35

@R35

@

0_0402_5%

Buffered reset to CPU

+3VS

+V1.05S_VCCP

0.1U_0402_16V4Z

12

R32

75_0402_5%

R34

43_0402_1%

1 2

BUFO_CPU_RST#

SN74LVC1G07DCKR_SC70-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C34

2

5

U2

4

1

P

NC

Y

PCH_PLTRST#

2

A

G

3

2011/06/15 2012/07/11

3V

PCH_PLTRST# <18>

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

1

of

660Tuesday, December 06, 2011

0.1

5

JCPU1C

DDR_A_D[0..63]<12>

D D

C C

B B

DDR_A_BS0<12> DDR_A_BS1<12> DDR_A_BS2<12>

DDR_A_CAS#<12> DDR_A_RAS#<12> DDR_A_WE#<12>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10 AF10

F10 G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8

AE8 AD9 AF9

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9

F9

F7 G8 G7

K4

K5

K1

J1

J5

J4

J2

K2 M8

N8 N7

M9 N9 M7

V6

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

4

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

RSVD_TP[1]

AA4

RSVD_TP[2]

W9

RSVD_TP[3]

AB3

RSVD_TP[4]

AA3

RSVD_TP[5]

W10

RSVD_TP[6]

AK3

SA_CS#[0]

AL3

SA_CS#[1]

AG1

RSVD_TP[7]

AH1

RSVD_TP[8]

AH3

SA_ODT[0]

AG3

SA_ODT[1]

AG2

RSVD_TP[9]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

RSVD_TP[10]

DDR SYSTEM MEMORY A

M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12>

M_ODT0 <12> M_ODT1 <12>

3

DDR_B_D[0..63]<13>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_BS0<13> DDR_B_BS1<13> DDR_B_BS2<13>

DDR_B_CAS#<13> DDR_B_RAS#<13> DDR_B_WE#<13>

DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AJ11

AH11

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA10

D10

K10

AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9

AT8 AT9

AR8

AA9 AA7

AB8 AB9

J10

C9

A7

C8

A9

A8 D9 D8 G4

F4

F1 G1 G5

F5

F2 G2

J7

J8

K9

J9

K8

K7 M5 N4 N2 N1 M4 N5 M2 M1

R6

JCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

RSVD_TP[17] RSVD_TP[18]

RSVD_TP[19] RSVD_TP[20]

DDR SYSTEM MEMORY B

1

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13>

M_ODT2 <13> M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

TYCO_2013620-2_IVY BRIDGE

DRAMRST_CNTRL <10>

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-7984P

1

760Tuesday, December 06, 2011

of

0.1

TYCO_2013620-2_IVY BRIDGE

+1.5V

R36

@R36

@

0_0402_5%

1 2

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

Q2

G

LBSS138LT1G_SOT-23-3

2

1

C35

0.047U_0402_16V4Z

2

H_DRAMRST#<6>

R39

4.99K_0402_1%

A A

5

DRAMRST_CNTRL

12

R37

1K_0402_5%

R38

R38 1K_0402_5%

1K_0402_5%

1 2

Eiffel used 0.01u Module design used 0.047u

4

DDR3_DRAMRST# <12,13>

DRAMRST_CNTRL_PCH<15>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R40 0_0402_5%

3

R02

@

DRAMRST_CNTRL

Compal Secret Data

2011/06/15 2012/07/11

Compal Secret Data

5

4

3

2

1

CFG Straps for Processor

CFG2

D D

JCPU1E

AK28

CFG[0]

AK29

CFG2 CFG4

CFG5 CFG6 CFG7

+VCC_GFXCORE_AXG

+VCC_CORE

R252

49.9_0402_1%

R253

49.9_0402_1%

C C

49.9_0402_1%

1 2

R82 100_0402_1%@R82 100_0402_1%@

1 2

R88 100_0402_1%@R88 100_0402_1%@

1 2

VCC_AXG_VAL_SENSE

VSS_AXG_VAL_SENSE

VCC_VAL_SENSE

VSS_VAL_SENSE

Need PWR add new circuit on 1.05V(refer CRB)

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

Check

R255

49.9_0402_1%

INTEL 12/28 recommand to add RC120, RC121, RC122, RC123

B B

Please place as close as JCPU1

R257

49.9_0402_1%

1 2

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

CFG

VCC_DIE_SENSE

VSS_DIE_SENSE

RESERVED

RSVD_NCTF10

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

Interl request AH26 short GND check on EVT phase

RSVD28 RSVD29 RSVD30 RSVD31

RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9

RSVD51 RSVD52

BCLK_ITP

BCLK_ITP#

KEY

AH27 AH26

L7 AG7 AE7 AK2

W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AN35 AM35

AT2 AT1 AR1

B1

R60 0_0402_5%

1 2

R02

@

PEG Static Lane Reversal - CFG2 is for the 16x

T13PAD T13PAD

CFG2

*

Display Port Presence Strap

CFG4

*

N13M@ R43

N13M@

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

R41

R41 1K_0402_1%

1K_0402_1%

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

1K_0402_1%

12

R42

@ R42

@

1K_0402_1%

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6 CFG5

CFG7

12

R44

@R44

12

@R45

@

1K_0402_1%

R45 1K_0402_1%

1K_0402_1%

R43

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-7984P

1

860Tuesday, December 06, 2011

0.1

of

5

POWER

+VCC_CORE

JCPU1F

POWER

QC=94A DC=53A

D D

C C

B B

A A

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CORE SUPPLY

4

8.5A

AH13

VCCIO1

AH10

VCCIO2

AG10

VCCIO3

AC10

VCCIO4

Y10

VCCIO5

U10

VCCIO6

P10

VCCIO7

L10

VCCIO8

J14

VCCIO9

J13

VCCIO10

J12

VCCIO11

J11

VCCIO12

H14

VCCIO13

H12

VCCIO14

H11

VCCIO15

G14

VCCIO16

G13

VCCIO17

G12

VCCIO18

F14

VCCIO19

F13

VCCIO20

F12

VCCIO21

F11

VCCIO22

E14

VCCIO23

E12

VCCIO24

E11

VCCIO25

D14

VCCIO26

D13

VCCIO27

D12

VCCIO28

D11

VCCIO29

C14

VCCIO30

C13

VCCIO31

PEG AND DDR

VCC_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VSS_SENSE

C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

+V1.05S_VCCP

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

3

1

C99

0.1U_0402_10V6K

R47 43_0402_5%R47 43_0402_5%

1 2

R48 0_0402_5%R48 0_0402_5%

1 2

R49 0_0402_5%R49 0_0402_5%

1 2

R50 130_0402_5%R50 130_0402_5%

2

12

+V1.05S_VCCP

12

R46

R46 75_0402_5%

75_0402_5%

+V1.05S_VCCP

VR_SVID_CLK

0.1uF on power side

2

series-resistors close to VR

VR_SVID_ALRT# <55> VR_SVID_CLK <55> VR_SVID_DAT <55>

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

Trace Impedance =27-33 ohm Trace Length Matc < 25 mils

VCCSENSE_R VSSSENSE_R

VSS_SENCE 100ohm +-1% pull-down to GND near processor

R52 0_0402_5%R52 0_0402_5%

1 2

R53 0_0402_5%R53 0_0402_5%

1 2

VSSIO_SENSEVSSIO_SENSE_L

R74

1 2

10_0402_1%

@

R74 & R79 put together

VSSIO_SENSE_L <53>

R79

10_0402_1%

VCCIO_SENSE <52,53>

+V1.05S_VCCP

12

R66

1 2

100_0402_1%

@R66

@

+VCC_CORE

12

R51

R51 100_0402_1%

100_0402_1%

R54

R54 100_0402_1%

100_0402_1%

VCCSENSE <55> VSSSENSE <55>

1

Security Classification

TYCO_2013620-2_IVY BRIDGE

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

2

Date: Sheet

960Tuesday, December 06, 2011

1

0.1

of

5

4

3

2

1

+1.5V +1.5V_CPU_VDDQ

R668

SUSP<46,53,54>

@ R667

@

100K_0402_5%

R580_0402_5% @ R580_0402_5%@

R590_0402_5% @ R590_0402_5% @

R69

0_0805_5%

1 2

R667

2

G

+3VALW

D D

CPU1.5V_S3_GATE<42>

SUSP#<25,42,46,51,52,53,54>

C C

B B

1 2

+1.8VS

1 2

0_0402_5%

+VSB

12

RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3

13

D

Q7

@

Q7

@

2N7002_SOT23

S

Check

10U

C154

22U_0805_6.3V6M@C154

22U_0805_6.3V6M

1

@

2

22U_0805_6.3V6M@C345

22U_0805_6.3V6M

C130

10U_0603_6.3V6M

C130

10U_0603_6.3V6M

C345

1

@

2

12

R03

13

D

2

G

S

RUN_ON_CPU1.5VS3# <6>

+VCC_GFXCORE_AXG

1.5A

+1.8VS_VCCPLL

C132

1U_0402_6.3V6K

C132

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

1

2

R56

R56 82K_0402_5%

82K_0402_5%

Q4

Q4 2N7002_SOT23

2N7002_SOT23

J1

@J1

@

1 2

PAD-OPEN 4x4m

U3

DMN3030LSS-13_SOP8L-8

8 7

5

4

12

R57

R57 330K_0402_5%

330K_0402_5%

@

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

1

AP4800

2

Id=9.6A

36

R02

R885

1 2

15K_0402_1%

1

C97

0.047U_0603_25V7K

2

POWER

GRAPHICS

1.8V RAIL

1

12

13

2

G

+VCC_GFXCORE_AXG

AK35 AK34

+V_SM_VREF_CNT

AL1

+V_DDR_REFA_R

B4

+V_DDR_REFB_R

D1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

+VCCSA

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

A19

C92

0.1U_0402_10V6K

2

12

R616

R616 10_0402_1%

10_0402_1%

12

R626

R626 10_0402_1%

10_0402_1%

R55

220_0402_5%

D

Q3

2N7002_SOT23

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VAXG_SENSE

VSSAXG_SENSE

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

VCCIO_SEL

S

@C92

@

RUN_ON_CPU1.5VS3#

12

R89

@R89

@

100_0402_1%

C117

10U_0603_6.3V6M

C117

10U_0603_6.3V6M

1

2

10U

10U_0603_6.3V6M

C124

10U_0603_6.3V6M

C124

10U_0603_6.3V6M

1

2

H_VCCSA_VID0 <52> H_VCCSA_VID1 <52>

+VREF_DQ_DIMMA

+VREF_DQ_DIMMB

DRAMRST_CNTRL

LBSS138LT1G_SOT-23-3

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

VCC_AXG_SENSE <55>

VSS_AXG_SENSE <55>

+V_SM_VREF should have 20 mil trace width

1

C98

0.1U_0402_10V6K

10U_0603_6.3V6M

C118

1

2

C125

10U_0603_6.3V6M

1

2

R68 0_0402_5%

0.1U_0402_10V6K

C119

C126

1 2

1

2

1

2

@

C120

10U_0603_6.3V6M

C120

10U_0603_6.3V6M

C127

10U_0603_6.3V6M

C127

10U_0603_6.3V6M

H_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SEL

10U_0603_6.3V6M

1

2

+VCCSA

2

C121

1

+

2

G

Q9

+1.5V_CPU_VDDQ

12

R67

R67 1K_0402_1%

1K_0402_1%

12

R78

R78 1K_0402_1%

1K_0402_1%

+1.5V_CPU_VDDQ

1

C122

10U_0603_6.3V6M

C122

10U_0603_6.3V6M

1

+

C123

C123 330U_2.5V_M

330U_2.5V_M

2

C128

@+C128

@

330U_D2_2.5VY_R9M

+VCCSA_SENSE <52>

10K_0402_5%

1 2

R77 0_0402_5%

R02

1 2 1 2

13

D

S

RUN_ON_CPU1.5VS3

R75

@

Q6

13

D

LBSS138LT1G_SOT-23-3

2

G

@R670

@

@R671

@

G

S

0_0402_5%~D

0_0402_5%~D 0_0402_5%~D

0_0402_5%~D

R353

1K_0402_1%

@

R670

R671

Q5-orignal part AP2302GN-HF_SOT23-3 SB523020210

G

2

PMV45EN_SOT23-3

PMV45EN_SOT23-3 Q5

@

Q5

@

13

D

S

D

S

R61

@R61

@

1 2

0_0402_5%

+1.5V +1.5V_CPU_VDDQ

+3VALW+3VS

R76

@R76

@

10K_0402_5%

1 2

DRAMRST_CNTRL

+V_DDR_REFA_R

+V_DDR_REFB_R

12

R64

1K_0402_1%

@

+V_SM_VREF

C396

@C396

@

0.1U_0402_10V6K

1 2

C129

@C129

@

0.1U_0402_10V6K

1 2

C96

0.1U_0402_10V6K

1 2

C95

0.1U_0402_10V6K

1 2

VCCP_PWRCTRL <52>

+1.5V

12

R62

@R62

@

1K_0402_1%

R63

@R63

@

1K_0402_1%

DRAMRST_CNTRL <7>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

IVY Bridge drives VCCIO_SEL low VCCP_PWRCTRL:0 Sandy Bridge is NC for A19 VCCP_PWRCTRL:1

Deciphered Date

2

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

1

of

10 60Tuesday, December 06, 2011

0.1

5

JCPU1H

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16

D D

C C

B B

A A

5

AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4 AJ25

TYCO_2013620-2_IVY BRIDGE

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

4

AJ22

VSS81

AJ19

VSS82

AJ16

VSS83

AJ13

VSS84

AJ10

VSS85

AJ7

VSS86

AJ4

VSS87

AJ3

VSS88

AJ2

VSS89

AJ1

VSS90

AH35

VSS91

AH34

VSS92

AH32

VSS93

AH30

VSS94

AH29

VSS95

AH28

VSS96

AH25

VSS98

AH22

VSS99

AH19

VSS100

AH16

VSS101

AH7

VSS102

AH4

VSS103

AG9

VSS104

AG8

VSS105

AG4

VSS106

AF6

VSS107

AF5

VSS108

AF3

VSS109

AF2

VSS110

AE35

VSS111

AE34

VSS112

AE33

VSS113

AE32

VSS114

AE31

VSS115

AE30

VSS116

AE29

VSS117

AE28

VSS118

VSS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

3

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

TYCO_2013620-2_IVY BRIDGE

Compal Secret Data

3

Compal Secret Data

Deciphered Date

2011/06/15 2012/07/11

VSS

2

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

2

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

Compal Electronics, Inc.

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

1

0.1

of

11 60Tuesday, December 06, 2011

1

R70

R70 1K_0402_1%

1K_0402_1%

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7> DDR_A_WE#<7>

DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

5

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C134

C134

1

2

+3VS

5

0.1U_0402_10V6K

0.1U_0402_10V6K C133

C133

1

2

2.2U_0603_6.3V4Z

1

2

+1.5V +1.5V

3A@1.5V

DDR3 SO-DIMM A

JDIMM1

R83

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F ME@

ME@

VREF_CA

EVENT#

+VREF_DQ_DIMMA

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 M_CLK_DDR0

M_CLK_DDR#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# M_ODT0 DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

R81

1 2

10K_0402_5%

0.1U_0402_10V6K

C155

C156

10K_0402_5%

1

2

10K_0402_5%

12

R71

1K_0402_1%

+1.5V

12

+VREF_DQ_DIMMA

D D

C C

B B

A A

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

VTT2

4

DDR_A_D[0..63]<7> DDR_A_DQS[0..7]<7>

+VREF_CA

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C136

C136

1

2

4*0402 1uf

DDR_A_DQS#[0..7]<7> DDR_A_MA[0..15]<7>

R72

1K_0402_1%

1*0402 2.2uf

2

DDR_A_D4

4

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A7 A6

A4 A2

A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

G2

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D5 DDR_A_DQS#0

DDR_A_DQS0 DDR_A_D6

DDR_A_D7 DDR_A_D12

DDR_A_D13 DDR_A_DM1

DDR3_DRAMRST# DDR_A_D14

DDR_A_D15 DDR_A_D20

DDR_A_D21 DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_BS1

DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

4

+0.75VS

0.65A@0.75V

DDR3_DRAMRST# <7,13>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K

0.1U_0402_10V6K C135

C135

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <13,15,36> SMB_CLK_S3 <13,15,36>

3

+1.5V

12

R73

Layout Note: Place near DIMM

10U_0603_6.3V6M

C137

10U_0603_6.3V6M

C137

10U_0603_6.3V6M

1

@

2

Layout Note: Place near DIMM

C138

+1.5V

C139

10U_0603_6.3V6M

C139

10U_0603_6.3V6M

1

2

1

2

(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

OSCAN

(10uF_0603_6.3V)*8 (0.1uF_402_10V)*4

C146

0.1U_0402_10V6K

C146

C140

10U_0603_6.3V6M

C140

10U_0603_6.3V6M

1

2

C141

C142

10U_0603_6.3V6M

C142

10U_0603_6.3V6M

1

2

C143

10U_0603_6.3V6M

C143

10U_0603_6.3V6M

1

2

C144

10U_0603_6.3V6M

C144

10U_0603_6.3V6M

1

2

C145

0.1U_0402_10V6K

C145

0.1U_0402_10V6K

1

2

0.1U_0402_10V6K

1

2

C147

0.1U_0402_10V6K

C147

0.1U_0402_10V6K

1

2

C148

0.1U_0402_10V6K

C148

0.1U_0402_10V6K

1

2

1

EVT Check

1

+

C149 220U_6.3V_M

220U_6.3V_M

2

@+C149

@

7/28 Update connect GND directly

+0.75VS

del

C150

1U_0402_6.3V6K

C150

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C152

1U_0402_6.3V6K

C152

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

C151

1U_0402_6.3V6K

C151

1U_0402_6.3V6K

1

2

2011/06/15 2012/07/11

del

1

2

Compal Secret Data

Deciphered Date

2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

Layout Note: Place near DIMM

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

LA-7984P

1

12 60Tuesday, December 06, 2011

of

0.1

R84

1K_0402_1%

R85

1K_0402_1%

5

2.2U_0603_6.3V4Z

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7> DDR_B_WE#<7>

DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

5

1

C158

2

0.1U_0402_10V6K

1

C157

2

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C177

C177

1

2

+VREF_DQ_DIMMB DDR_B_D0

DDR_B_D1 DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 M_CLK_DDR2

M_CLK_DDR#2 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

1 2

10K_0402_5%

C178

R95

1 2

R97 10K_0402_5%R97 10K_0402_5%

3A@1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17 VSS1849DQ22

51

DQ18

53

DQ19 VSS2055DQ28

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U8SN-7F

ME@

+VREF_DQ_DIMMB

D D

For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit.

C C

B B

A A

+1.5V

12

VSS3 DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

DQ23

VSS19

DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

4

+1.5V+1.5V

2

DDR_B_D4

4

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A7 A6

A4 A2

A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

G2

4

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_D5 DDR_B_DQS#0

DDR_B_DQS0 DDR_B_D6

DDR_B_D7 DDR_B_D12

DDR_B_D13 DDR_B_DM1

DDR3_DRAMRST# DDR_B_D14

DDR_B_D15 DDR_B_D20

DDR_B_D21 DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 M_CLK_DDR3

M_CLK_DDR#3 DDR_B_BS1

DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT2 M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3

0.65A@0.75V

DDR3_DRAMRST# <7,12>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K C160

C160

C159

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <12,15,36> SMB_CLK_S3 <12,15,36> +0.75VS

3

DDR_B_D[0..63]<7> DDR_B_DQS[0..7]<7> DDR_B_DQS#[0..7]<7> DDR_B_MA[0..15]<7>

+1.5V

12

R86

1K_0402_1%

12

R87

1K_0402_1%

4*0402 1uf

1*0402 2.2uf

3

2

Layout Note: Place near DIMM

10U_0603_6.3V6M

C161

C162

C163

1

@

2

C174

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

1

2

C163

1

2

1U_0402_6.3V6K

1

2

Compal Secret Data

1

@

2

Layout Note: Place near DIMM

+0.75VS

C173

1U_0402_6.3V6K

C173

1U_0402_6.3V6K

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

(10uF_0603_6.3V)*8 (0.1uF_402_10V)*4

+1.5V

10U_0603_6.3V6M

C164

C165

1

2

DDR_B_DM0 DDR_B_DM1

C176

1

2

Deciphered Date

DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

2

10U_0603_6.3V6M

C166

1

2

Layout Note: Place near DIMM

10U_0603_6.3V6M

C167

1

2

1

10U_0603_6.3V6M

C168

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C170

C170

C169

1

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

0.1U_0402_10V6K

C171

C172

1

2

DDRIII-SODIMM SLOT2

C172

1

2

LA-7984P

1

0.1

of

13 60Tuesday, December 06, 2011

of

13 60Tuesday, December 06, 2011

of

13 60Tuesday, December 06, 2011

5

W=20milsW=20mils

R99

1K_0402_5%

1

C179

C179 1U_0603_10V4Z

1U_0603_10V4Z

2

D D

1 2

+RTCBATT+RTCVCC

12

SHORT PADS

CLRP1

C180

15P_0402_50V8J

4

1 2

R98 10M_0402_5%R98 10M_0402_5%

Y1

1 2

1

2

PCH_RTCX1 PCH_RTCX2

32.768KHZ_12.5PF_CM31532768DZFT

1

C181

C181 18P_0402_50V8J

18P_0402_50V8J

2

3

2

1

CMOS

CLRP2

SHORT PADS

CLRP2

+RTCVCC

R101 1M_0402_5%R101 1M_0402_5%

1 2

R102 330K_0402_5%R102 330K_0402_5%

1 2

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

SM_INTRUDER# PCH_INTVRMEN

(INTVRMEN should always be pull high.)

+3VS

R105 1K_0402_5%@R105 1K_0402_5%@

1 2

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

+3V_PCH

C C

R106 1K_0402_5%@R106 1K_0402_5%@

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

R108 1K_0402_5%R108 1K_0402_5%

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low

*

Needs to be pulled High for Chief River platfrom

HDA_BITCLK_AUDIO<41>

HDA_SYNC_AUDIO<41>

B B

HDA_RST_AUDIO#<41>

HDA_SDOUT_AUDIO<41>

+3V_PCH +3V_PCH+3V_PCH

12

R121

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

R125

100_0402_1%

12

R122

200_0402_5%

12

R126

R126 100_0402_1%

100_0402_1%

R112

33_0402_5%

1 2

R114

33_0402_5%

1 2

R116

33_0402_5%

1 2

R118

33_0402_5%

1 2

HDA_SPKR

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

12

R123

200_0402_5%

12

R128

100_0402_1%

DPDG1.1

+RTCVCC

ME_FLASH<42>

R878

1M_0402_5%

1 2

check with vender

Del Q10 check with codec VDDIO using 3VALW

C183

1U_0603_10V4Z

1 2

R103 20K_0402_5%R103 20K_0402_5%

1 2

R100 20K_0402_5%R100 20K_0402_5%

C182

1U_0603_10V4Z

ME_FLASH

R107 1K_0402_1%@R107 1K_0402_1%@

1 2

+3V_PCH

+5VS

G

2

S

R175

1 2

0_0402_5%

22P_0402_50V8J

HDA_SPKR<41>

HDA_SDIN0<41>

13

D

33_0402_5%

SHORT PADS

1

12

2

CLRP3

SHORT PADS

CLRP3

SHORT PADS

1

12

2

R109

1 2

0_0402_5%

R26410K_0402_5% @R26410K_0402_5% @

R110

12

51_0402_5%

Q10

Q10 LBSS138LT1G_SOT-23-3

LBSS138LT1G_SOT-23-3

HDA_SYNC

@R175

@

SPI_CLK_PCH_R

12

R124

@

C190

@

PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_GPIO33

12

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

SPI_CLK_PCH_R SPI_SB_CS0# SPI_SB_CS1#

SPI_SI SPI_SO_R

R124;c190 close to U4.T3 pin

U4A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

RTCIHDA

JTAG

SPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36 E36

K36

SERIRQ

V5

AM3 AM1

SATA_ITX_C_DRX_N0

AP7

SATA_ITX_C_DRX_P0

AP5 AM10

AM8 AP11 AP10

SATA_DTX_C_IRX_N2

AD7

SATA_DTX_C_IRX_P2

AD5

SATA_ITX_C_DRX_N2

AH5

SATA_ITX_C_DRX_P2

AH4 AB8

AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

RBIAS_SATA3

AH1

SATALED#

P3

PCH_GPIO21

V14

BBS_BIT0_R

P1

LPC_AD0 <36,42> LPC_AD1 <36,42> LPC_AD2 <36,42> LPC_AD3 <36,42>

LPC_FRAME# <36,42>

R104 10K_0402_5%R104 10K_0402_5%

R111

37.4_0402_1%

SATA_COMP

SATA3_COMP

37.4_0402_1%

1 2

R113

49.9_0402_1%

1 2

R115

750_0402_1%

R117 10K_0402_5%R117 10K_0402_5% R119 10K_0402_5%R119 10K_0402_5% R187 10K_0402_5%R187 10K_0402_5%

+3VS

R266

1 2

R221

1 2

R127

1 2

R129

1 2

12 12 12

EC and Mini card debug port

12

SERIRQ <42>

CAP on Conn, side

SATA_DTX_C_IRX_N2 <40>

SATA_DTX_C_IRX_P2 <40> SATA_ITX_C_DRX_N2 <40> SATA_ITX_C_DRX_P2 <40>

+1.05VS_VCC_SATA

+1.05VS_SATA3

SPI_WP#1

3.3K_0402_5%

SPI_HOLD#1

3.3K_0402_5%

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

+3VS

SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_P0

C1840.01U_0402_16V7K C1840.01U_0402_16V7K

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

C1850.01U_0402_16V7K C1850.01U_0402_16V7K

SPI_SB_CS1# SPI_SO_R

SPI_SB_CS0# SPI_SO_R SPI_SO_L

+3VS +3VS +3VS

12 12

SATA_DTX_C_IRX_N0 <40> SATA_DTX_C_IRX_P0 <40> SATA_ITX_DRX_N0 <40> SATA_ITX_DRX_P0 <40>

ODD

8MB SPI ROM FOR ME & Non-share ROM.

R291

0_0402_5%

CS1#

1 2

SPI_SO1

1 2

SPI_WP#1

R188

33_0402_5%

U6 Rersver 4M+2M Solution

0_0402_5%

R130

1 2 1 2

33_0402_5%

R131

CS# SPI_WP#

1 2 3 4

U6

CS# SO WP# GND

16M W25Q16BVSSIG SOIC 8P

U5

1

CS#

2

SO

3

WP#

4

GND

32M W25Q32BVSSIG SOIC 8P

VCC

HOLD#

SCLK

HOLD#

HDD

+3VS

8

SPI_HOLD#1

7

SPI_CLK1

SI

VCC

SCLK

6 5

8 7 6 5

SI

1 2

SPI_SI1

1 2

+3VS

C191

1 2

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_PCH SPI_CLK_PCH_R SPI_SI_R

1 2 1 2

0_0402_5%

0_0402_5% R199

R199

SPI_CLK_PCH_R SPI_SI

R196

R196 33_0402_5%

33_0402_5%

0_0402_5%

0_0402_5% R132

R132

SPI_SI

R133

R133 33_0402_5%

33_0402_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

2

Date: Sheet

14 60Tuesday, December 06, 2011

1

0.1

of

5

LAN

WLAN

D D

USB3.0

C C

LAN

WLAN

USB3.0

B B

PCIE_PRX_DTX_N1<37>

PCIE_PRX_DTX_P1<37> PCIE_PTX_C_DRX_N1<37> PCIE_PTX_C_DRX_P1<37>

PCIE_PRX_DTX_N2<36>

PCIE_PRX_DTX_P2<36> PCIE_PTX_C_DRX_N2<36> PCIE_PTX_C_DRX_P2<36>

PCIE_PRX_DTX_N4<45>

PCIE_PRX_DTX_P4<45> PCIE_PTX_C_DRX_N4<45> PCIE_PTX_C_DRX_P4<45>

CLK_PCIE_LAN#<37> CLK_PCIE_LAN<37>

CLKREQ_LAN#<37>

CLK_PCIE_WLAN1#<36> CLK_PCIE_WLAN1<36>

CLKREQ_WLAN#<36>

CLK_PCIE_USB30#<45> CLK_PCIE_USB30<45>

CLKREQ_USB30#<45>

C192 0.1U_0402_10V7KC192 0.1U_0402_10V7K C193 0.1U_0402_10V7KC193 0.1U_0402_10V7K

C194 0.1U_0402_10V7KC194 0.1U_0402_10V7K C195 0.1U_0402_10V7KC195 0.1U_0402_10V7K

C309 0.1U_0402_10V7KEU3@C309 0.1U_0402_10V7KEU3@ C308 0.1U_0402_10V7KEU3@C308 0.1U_0402_10V7KEU3@

R152 10K_0402_5%R152 10K_0402_5%

+3V_PCH

R158 10K_0402_5%R158 10K_0402_5%

+3VS

R147 10K_0402_5%R147 10K_0402_5%

+3VS

R334 0_0402_5%EU3@R334 0_0402_5%EU3@ R330 0_0402_5%EU3@R330 0_0402_5%EU3@

R326 0_0402_5%EU3@R326 0_0402_5%EU3@ R301 10K_0402_5%R301 10K_0402_5%

+3V_PCH

R165 10K_0402_5%R165 10K_0402_5%

+3V_PCH

R168 10K_0402_5%R168 10K_0402_5%

+3V_PCH

R170 10K_0402_5%R170 10K_0402_5%

+3V_PCH

R172 10K_0402_5%R172 10K_0402_5%

+3V_PCH

R174 10K_0402_5%R174 10K_0402_5%

+3V_PCH

1 2 1 2

CAP on Conn, side

R153

0_0402_5%

R153

0_0402_5%

1 2

R154

0_0402_5%

R154

0_0402_5%

1 2

R151

0_0402_5%

R151

0_0402_5%

1 2

12

R149

0_0402_5%

R149

0_0402_5%

1 2

R150

0_0402_5%

R150

0_0402_5%

1 2

R156

0_0402_5%

R156

0_0402_5%

1 2

12

1 2 1 2

1 2

12

4

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

CLKREQ_LAN#_R

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

CLKREQ_WLAN#_R

PCH_GPIO20

CLK_USB30# CLK_USB30

CLKREQ_USB30#_R

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

PCIE_CLK_8N PCIE_CLK_8P

U4B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

E12 H14

SMBCLK

C9

SMBDATA

A12 C8

SML0CLK

G12

C13 E14 M16

M7

CL_CLK1

T11

CL_DATA1

P10

CL_RST1#

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43 F47 H47 K49

BIOS Request SKU ID

2

PCH_GPI011 PCH_SMBCLK PCH_SMBDATA

DRAMRST_CNTRL_PCH

PCH_SML0CLK PCH_SML0DATA

PCH_HOT# SML1CLK SML1DATA

PEG_CLKREQ#_R

CLK_PCIE_VGA#_R CLK_PCIE_VGA#

CLK_CPU_DMI# CLK_CPU_DMI

CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI

CLKIN_DMI2# CLKIN_DMI2

CLK_BUF_DREF_96M# CLK_BUF_DREF_96M

CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA

CLK_BUF_ICH_14M

CLK_PCI_LPBACK

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

27M_SSC

LAN_48M PCH_GPIO67

R134

12

10K_0402_5%

R140 10K_0402_5%R140 10K_0402_5%

12

+3V_PCH

R143

R143 10K_0402_5%

10K_0402_5%

1 2

R144 0_0402_5%

1 2

R145 10K_0402_5%

1 2

R146 0_0402_5%R146 0_0402_5%

1 2

R148 0_0402_5%R148 0_0402_5%

1 2

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

R155 10K_0402_5%R155 10K_0402_5%

1 2

R157 10K_0402_5%R157 10K_0402_5%

1 2

R159 10K_0402_5%R159 10K_0402_5%

1 2

R160 10K_0402_5%R160 10K_0402_5%

1 2

R162 10K_0402_5%R162 10K_0402_5%

1 2

R163 10K_0402_5%R163 10K_0402_5%

1 2

R164 10K_0402_5%R164 10K_0402_5%

1 2

R166 10K_0402_5%R166 10K_0402_5%

1 2

R167 10K_0402_5%R167 10K_0402_5%

1 2

CLK_PCI_LPBACK <18>

R171

90.9_0402_1%

1 2

R207 22_0402_5%@R207 22_0402_5%@

1 2

PCH_GPIO67 <19>

+3V_PCH

R139

1K_0402_5%

+3V_PCH

PCH_HOT# <42>

R02

@

+1.05VS_VCCDIFFCLKN

+3V_PCH

DRAMRST_CNTRL_PCH <7>

12

+3V_PCH

+3V_PCH +3VS

CLK_REQ_VGA# <23>

CLK_PCIE_VGACLK_PCIE_VGA_R

PCH_LAN_48M <37>

2.2K_0402_5%

2.2K_0402_5% R136

R136

1 2 1 2

R135

2.2K_0402_5%

2.2K_0402_5% R141

R141

1 2 1 2

R142

2.2K_0402_5%

XTAL25_IN XTAL25_OUT

12P_0402_50V8J

Q60A

Q60A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

6 1

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q60B

Q60B

Q61A

Q61A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

6 1

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q61B

Q61B

CLK_PCIE_VGA# <23>

CLK_PCIE_VGA <23>

25MHZ_20PF_FSX3M-25.M20FDO

1

C196

2

SMB_CLK_S3

2.2K_0402_5%

1 2

2

+3VS

1 2

5

2.2K_0402_5%

SMB_DATA_S3

4

EC_SMB_CK2

2 5

EC_SMB_DA2

4

1 2

R169 1M_0402_5%R169 1M_0402_5%

3

OSC

2

NC

Y2

1

SMB_CLK_S3 <12,13,36>

DIMM1

R137

DIMM2

R138

MINI CARD

SMB_DATA_S3 <12,13,36>

EC_SMB_CK2 <23,39,42>

VGA EC thermal sensor

EC_SMB_DA2 <23,39,42>

2.2K_0402_5%

PCH_SML0CLK PCH_SML0DATA

4

NC

1

OSC

R02

1

2

R544

C197

12P_0402_50V8J

+3V_PCH

1 2

R545

2.2K_0402_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

LA-7984P

1

15 60Tuesday, December 06, 2011

0.1

of

5

D D

U15

U15 MC74VHC1G08DFT2G SC70 5P

MC74VHC1G08DFT2G SC70 5P

3

R191

1

G

A

SYS_PWROK

4

Y

2

B

P

5

+3VS

12

12 12

12

PM_DRAM_PWRGD SUSWARN# AC_PRESENT_R

PCH_RSMRST#_R

12

R180 100K_0402_1%

100K_0402_1%

SYS_PWROK <6>

@R180

@

SUSACK# is only used on platform that support the Deep Sx state.

PCH_PWROK<42>

PCH_APWROK<42>

PM_DRAM_PWRGD<6>

EC_RSMRST#<42>

PBTN_OUT#<42>

ACIN<42,49>

VGATE<55>

PCH_PWROK

C C

AEPWROK can be connect to PWROK if iAMT disable

PCH_POK APWROK

+3VS

+3V_PCH

R192 200_0402_5%R192 200_0402_5%

B B

R194 10K_0402_5%R194 10K_0402_5% R195 200K_0402_5%R195 200K_0402_5%

R197 10K_0402_5%R197 10K_0402_5%

1 2

0_0402_5%

@

R556 200_0402_5%

1 2

4

DMI_CTX_PRX_N0<5> DMI_CTX_PRX_N1<5> DMI_CTX_PRX_N2<5> DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5> DMI_CTX_PRX_P1<5> DMI_CTX_PRX_P2<5> DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5> DMI_CRX_PTX_N1<5> DMI_CRX_PTX_N2<5> DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5> DMI_CRX_PTX_P1<5> DMI_CRX_PTX_P2<5> DMI_CRX_PTX_P3<5>

+1.05VS

1 2

R177 49.9_0402_1%R177 49.9_0402_1%

1 2

R178 750_0402_1%R178 750_0402_1%

4mil width and place within 500mil of the PCH

T72T72

+3VS

PCH_PWROK

1 2

R190 0_0402_5%

1 2

R193 0_0402_5%

1 2

R198 0_0402_5%

D29

CH751H-40PT_SOD323-2

+3V_PCH

21

10K_0402_5%

12

R18410K_0402_5% R18410K_0402_5%

@

R02

@

R3020_0402_5%@R3020_0402_5%

@

R02

@

R02

R200

12

10K_0402_5%

10K_0402_5% R201

R201

12

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP RBIAS_CPY

SUSACK#

SYS_RST#

SYS_PWROK

PCH_POK

APWROK

PM_DRAM_PWRGD

PCH_RSMRST#_R

SUSWARN#

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

U4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

3

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

FDI_RXP6

DMI

FDI

DMI

FDI

FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXP7

FDI_INT

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWODVREN

WAKE#

PM_CLKRUN#

SUS_STAT#

SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

R02

@

R185 0_0402_5%

1 2

10K_0402_5%

1 2

R186

1 2

R261

@R261

@

10K_0402_5%

2

FDI_CTX_PRX_N0 <5> FDI_CTX_PRX_N1 <5> FDI_CTX_PRX_N2 <5> FDI_CTX_PRX_N3 <5> FDI_CTX_PRX_N4 <5> FDI_CTX_PRX_N5 <5> FDI_CTX_PRX_N6 <5> FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5> FDI_CTX_PRX_P1 <5> FDI_CTX_PRX_P2 <5> FDI_CTX_PRX_P3 <5> FDI_CTX_PRX_P4 <5> FDI_CTX_PRX_P5 <5> FDI_CTX_PRX_P6 <5> FDI_CTX_PRX_P7 <5>

FDI_INT <5> FDI_FSYNC0 <5> FDI_FSYNC1 <5> FDI_LSYNC0 <5> FDI_LSYNC1 <5>

R02

R181 0_0402_5%@ R181 0_0402_5%@

1 2

T74T74

T99T99

T71T71

H_PM_SYNC <6>

+3V_PCH

PCIE_WAKE# <36,37,45>

+3V_PCH

SUSCLK <42>

PM_SLP_S5# <42>

PM_SLP_S4# <42>

PM_SLP_S3# <42>

*

DSWODVREN - On Die DSW VR Enable H

：

Enable

L

：

Disable

PCH_RSMRST#_RPCH_DPWROK

R189 8.2K_0402_5%@ R189 8.2K_0402_5%@

1 2

R299 10K_0402_5%R299 10K_0402_5%

12

Can be left NC when IAMT is not support on the platfrom

1

+RTCVCC

12

R179

R179 330K_0402_5%

330K_0402_5%

12

R183

R183 330K_0402_5%

+3VS

330K_0402_5%

@

Can be left NC if no use integrated LAN.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (3/9) DMI,FDI,PM,

LA-7984P

1

0.1

of

16 60Tuesday, December 06, 2011

5

+3VS

12

D D

C C

B B

2.2K_0402_5%

R559

2.2K_0402_5%

+3VS

12

R523

R524

2.2K_0402_5%

CRT_DDC_CLK CRT_DDC_DATA

R234

2.2K_0402_5%

EDID_CLK EDID_DATA

DAC_BLU<34> DAC_GRN<34> DAC_RED<34>

+3VS

4

PCH_ENBKL<33> PCH_ENVDD<33>

PCH_PWM<33>

EDID_CLK<33>

EDID_DATA<33>

R2042.2K_0402_5% R2042.2K_0402_5%

1 2

R2052.2K_0402_5% R2052.2K_0402_5%

1 2

R2062.37K_0402_1% R2062.37K_0402_1%

12

LVDS_ACLK#<33> LVDS_ACLK<33>

LVDS_A0#<33> LVDS_A1#<33> LVDS_A2#<33>

LVDS_A0<33> LVDS_A1<33> LVDS_A2<33>

R208 150_0402_1%R208 150_0402_1% R209 150_0402_1%R209 150_0402_1% R210 150_0402_1%R210 150_0402_1%

CRT_DDC_CLK<34> CRT_DDC_DATA<34>

CRT_HSYNC<34> CRT_VSYNC<34>

12 12 12

DAC_BLU DAC_GRN DAC_RED

1K_0402_1%

EDID_CLK EDID_DATA

CTRL_CLK CTRL_DATA

LVDS_IBG

LVD_VREF

CRT_DDC_CLK CRT_DDC_DATA

CRT_IREF

12

R211

U4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

3

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

CRT

DDPD_HPD

R202

HDMI@ R202

HDMI@

2.2K_0402_5%

HDMICLK_NB HDMIDAT_NB

TMDS_B_DATA2#_PCH TMDS_B_DATA2_PCH TMDS_B_DATA1#_PCH TMDS_B_DATA1_PCH TMDS_B_DATA0#_PCH TMDS_B_DATA0_PCH TMDS_B_CLK#_PCH TMDS_B_CLK_PCH

2

+3VS

12

R203

HDMI@R203

HDMI@

2.2K_0402_5%

HDMICLK_NB <35> HDMIDAT_NB <35>

TMDS_B_HPD# <35>

C200 0.1U_0402_10V6KHDMI@ C200 0.1U_0402_10V6KHDMI@

1 2

C201 0.1U_0402_10V6KHDMI@ C201 0.1U_0402_10V6KHDMI@

1 2

C202 0.1U_0402_10V6KHDMI@ C202 0.1U_0402_10V6KHDMI@

1 2

C203 0.1U_0402_10V6KHDMI@ C203 0.1U_0402_10V6KHDMI@

1 2

C204 0.1U_0402_10V6KHDMI@ C204 0.1U_0402_10V6KHDMI@

1 2

C205 0.1U_0402_10V6KHDMI@ C205 0.1U_0402_10V6KHDMI@

1 2

C206 0.1U_0402_10V6KHDMI@ C206 0.1U_0402_10V6KHDMI@

1 2

C207 0.1U_0402_10V6KHDMI@ C207 0.1U_0402_10V6KHDMI@

1 2

CAP move on Conn, side

HDMI_TX2-_CK <35> HDMI_TX2+_CK <35> HDMI_TX1-_CK <35> HDMI_TX1+_CK <35> HDMI_TX0-_CK <35> HDMI_TX0+_CK <35> HDMI_CLK-_CK <35> HDMI_CLK+_CK <35>

1

HDMI D2 HDMI D1

HDMI

HDMI D0 HDMI CLK

A A

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Title

PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Rev

B

LA-7984P

Date: Sheet

2

Date: Sheet

1

of

17 60Tuesday, December 06, 2011

0.1

5

+3VS

RP2

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5% RP1

D D

C C

GNT1#/ GPIO51

PCH_WL_OFF#

B B

A16 swap overide Strap/Top-Block Swap Override jumper

RP1

8.2K_0804_8P4R_5%

R213 8.2K_0402_5%R213 8.2K_0402_5%

1 2

R225 8.2K_0402_5%R225 8.2K_0402_5%

1 2

R292 8.2K_0402_5%@R292 8.2K_0402_5%@

1 2

R557 8.2K_0402_5%@R557 8.2K_0402_5%@

1 2

R259 8.2K_0402_5%R259 8.2K_0402_5%

1 2

R212 8.2K_0402_5%R212 8.2K_0402_5%

1 2

R214 8.2K_0402_5%@R214 8.2K_0402_5%@

1 2

Boot BIOS Strap bit1 BBS1

PCI_GNT3#

A A

PLT_RST#<23,36,37,42,45>

PCI_PIRQA#

18

PCI_PIRQD#

27

PCI_PIRQC#

36

PCI_PIRQB#

45

PCH_GPIO2

18

DGPU_PWR_EN_R

27

PCH_GPIO4

36

ODD_DA#_R

45

PCH_GPIO5 PCH_WL_OFF# PCH_GPIO51 PCH_GPIO53 DGPU_PWR_EN1 DGPU_HOLD_RST#_R DGPU_HOLD_RST#_R

Boot BIOS Destination

Bit10

Bit11

01 1 1 0

1 2

R319 0_0402_5%

@

R215 1K_0402_5%@R215 1K_0402_5%@

1 2

Low=A16 swap override/Top-Block Swap Override enabled High=Default

1U_0402_6.3V4Z

5

Reserved Reserved

0 1

SPI

*

0

LPC

NVDD_PWR_ENDGPU_PWR_EN_R

*

1

C208

@C208

@

2

(Default)

GPIO55

12

R223

R223 100K_0402_5%

100K_0402_5%

PPT EDS DOC#474146

DGPU_HOLD_RST#<23>

NVDD_PWR_EN<54> DGPU_PWR_EN<23,25>

PCH_WL_OFF#<36>

ODD_DA#<40,42>

CLK_PCI_LPBACK<15>

CLK_PCI_EC<42>

CLK_PCI_DB<36>

R222

1 2

0_0402_5%

3

1

G

A

4

Y

2

B

P

U7

@U7

@

5

MC74VHC1G08DFT2G SC70 5P

+3VS

4

USB3_RX3_N<45> USB3_RX4_N<45>

USB3_RX3_P<45> USB3_RX4_P<45>

USB3_TX3_N<45> USB3_TX4_N<45>

USB3_TX3_P<45> USB3_TX4_P<45>

PCH_PLTRST#

4

T1829T1829 T1825T1825

T1832T1832 T1826T1826

T1831T1831 T1827T1827

T1830T1830 T1828T1828

R553 0_0402_5%R553 0_0402_5%

1 2

R692 0_0402_5%R692 0_0402_5%

1 2

R691 0_0402_5%R691 0_0402_5%

1 2

R715 0_0402_5%@R715 0_0402_5%@

1 2

PCH_PLTRST#<6>

USB3_RX3_N USB3_RX4_N

USB3_RX3_P USB3_RX4_P

USB3_TX3_N USB3_TX4_N

USB3_TX3_P USB3_TX4_P

PCI_PME#<42>

1 2 1 2

R21922_0402_5% R21922_0402_5% R22022_0402_5% R22022_0402_5% R17322_0402_5% @ R17322_0402_5% @

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB3_RX1_N

USB3_RX1_P

USB3_TX1_N

USB3_TX1_P

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST#_R DGPU_PWR_EN1 DGPU_PWR_EN_R

PCH_GPIO51 PCH_GPIO53 PCH_WL_OFF#

PCH_GPIO2 ODD_DA#_R PCH_GPIO4 PCH_GPIO5

PCH_PLTRST#

CLK_PCI_LPBACK_R CLK_PCI_EC_R CLK_PCI_DB_R

3

U4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

2011/06/15 2012/07/11

3

RSVD

PCI

USB

Compal Secret Data

Deciphered Date

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AV10

AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

2

USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB20_N5 USB20_P5

USB20_N9 USB20_P9

USB20_N11 USB20_P11

USB20_N13 USB20_P13

USBRBIAS

USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# SMIB USB_OC7#

2

USB DEBUG=PORT1 AND PORT9

USB20_N1 <43> USB20_P1 <43> USB20_N2 <45> USB20_P2 <45> USB20_N3 <45> USB20_P3 <45>

USB20_N5 <33> USB20_P5 <33>

USB20_N9 <44> USB20_P9 <44> USB20_N10 <36> USB20_P10 <36> USB20_N11 <43> USB20_P11 <43>

USB20_N13 <40> USB20_P13 <40>

R218

1 2

22.6_0402_1%

Within 500 mils

Title

Size Document Number Rev

Custom

Date: Sheet

(CR-B/D USB) LEFT USB LEFT USB

(USB 3.0)

USB Camera

RIGHT USB WLAN CARD READER

Bluetooth

USB_OC0# Share with USB_OC4# due to same power switch

R02

USB_OC4# <44>

USB_OC1# <45>

USB_OC4# <44>

SMIB <45>

R03

PCH (5/9) PCI, USB

LA-7984P

USB_OC5# USB_OC2# USB_OC7#

USB_OC1# USB_OC4# USB_OC3#

SMIB

1

RP310K_1206_8P4R_5% RP310K_1206_8P4R_5%

4 5 3 6 2 7 1 8

RP410K_1206_8P4R_5% RP410K_1206_8P4R_5%

R262

1 2

10K_0402_5%

18 60Tuesday, December 06, 2011

of

+3V_PCH

0.1

5

D D

+3V_PCH

GPIO28

On-Die PLL Voltage Regulator

This signal has a weak internal pull up

*

PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable

C C

B B

Weak internal pull-high

R250

@R250

@

10K_0402_5%

R547

R547 10K_0402_5%

10K_0402_5%

EC_SMI#

PCH_GPIO27

+3VS

12

R235 10K_0402_5%R235 10K_0402_5%

1 2

：

On-Die voltage regulator enable

H L：On-Die PLL Voltage Regulator disable

R240 1K_0402_5%@R240 1K_0402_5%@

1 2

R245 10K_0402_5%@R245 10K_0402_5%@

1 2

+3VS

12

R244

@R244

@

10K_0402_5%

PCH_GPIO37 PCH_GPIO36

12

R881

R881 10K_0402_5%

10K_0402_5%

+3VS

+3V_PCH

EC_LID_OUT#<42>

DGPU_PWROK<46,54>

PU on power side

+3VS

BT_DISABLE<36>

R02

PCH_BT_ON#<36,40>

+3VS

+3V_PCH

BIOS Request SKU ID

+3VS

12

R246

R711

@

1 2

R708

A A

1 2

10K_0402_5%

R298

10K_0402_5%

PCH_GPIO38 PCH_GPIO67

12

PCH_GPIO38 PCH_GPIO67

10K_0402_5%

5

PCH_GPIO67 <15>

0 01 1

0

Optimus

Reserved

11

Function

DIS UMA

4

R233 10K_0402_5%R233 10K_0402_5%

1 2

R227 10K_0402_5%R227 10K_0402_5%

1 2

R228 10K_0402_5%R228 10K_0402_5%

1 2

EC_SCI#<42> EC_SMI#<42>

R229 10K_0402_5%@R229 10K_0402_5%@

1 2

R02

R230 1K_0402_5%R230 1K_0402_5%

1 2

R231 10K_0402_5%R231 10K_0402_5%

1 2

R297 0_0402_5%R297 0_0402_5%

1 2

R232 10K_0402_1%@R232 10K_0402_1%@

1 2

+3VS

R238 10K_0402_5%R238 10K_0402_5%

1 2

+3VS

+3V_PCH

1 2 1 2 1 2

R247 10K_0402_5%R247 10K_0402_5%

1 2

R248 10K_0402_5%R248 10K_0402_5%

1 2

R249 10K_0402_5%R249 10K_0402_5%

1 2

R251 10K_0402_5% R251 10K_0402_5%

1 2

4

ODD_EN<40>

R241

10K_0402_5%

10K_0402_5% R242 10K_0402_5%R242 10K_0402_5% R243 10K_0402_5%R243 10K_0402_5%

PCH_GPIO1 PCH_GPIO6 EC_SCI# EC_SMI# PCH_GPIO12PCH_GPIO28 EC_LID_OUT#

PCH_GPIO16

DGPU_PWROK_R BT_DISABLE ODD_EN PCH_GPIO27 PCH_GPIO28 PCH_BT_ON# PCH_GPIO35 PCH_GPIO36 PCH_GPIO37 PCH_GPIO38 PCH_GPIO39 PCH_GPIO48 PCH_GPIO49 PCH_GPIO57

3

@R702

@

U4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

GPIO

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

NCTF

VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

2011/06/15 2012/07/11

PCH_GPIO68

C40

PCH_GPIO69

B41

PCH_GPIO70

C41

PCH_GPIO71

A40

P4

PCH_PECI_R

AU16

KBRST#

P5 AY11

PCH_THRMTRIP#_R

AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

Compal Secret Data

INIT3_3V

This signal has weak internal PU,can't pull low

NV_CLE

Deciphered Date

2

R702

1 2

10K_0402_5%

R707

@

1 2

10K_0402_5%

R22410K_0402_5% R22410K_0402_5%

1 2

@

1 2

R2370_0402_5%@R2370_0402_5%

1 2

R239 390_0402_5%R239 390_0402_5%

2

200K_0402_5%

R703

@R703

@

1 2

10K_0402_5%

R705

1 2

+3VS

1 2

H_PECI <6,42> KBRST# <42> H_CPUPWRGD <6>

H_THRMTRIP#

NV_CLE

Weak internal PU,Do not pull low

1

PCH_GPIO70

0 1

PCH_GPIO71

0 1

R236

R236 10K_0402_5%

10K_0402_5%

GATEA20 <42>

H_THRMTRIP# <6>

PCH_THRMTRIP#_R <23>

DMI Termination Voltage

Set to Vcc when HIGH Set to Vss when LOW

Title

PCH (6/9) GPIO, CPU, MISC

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

Function

14/15"

17"

USB3.0 by PCH USB3.0 by NEC

KBRST#

R226 10K_0402_5%R226 10K_0402_5%

1 2

+1.8VS

12

R216

2.2K_0402_5%

12

R217 1K_0402_5%R217 1K_0402_5%

CLOSE TO THE BRANCHING POINT

H_SNB_IVB# <6>

1

R704

@ R704

@

PCH_GPIO71PCH_GPIO70PCH_GPIO69

R706

200K_0402_5%

of

19 60Tuesday, December 06, 2011

+3VS+3VS +3VS

1 2

10K_0402_5%

1 2

+3VS

0.1

Compal Electronics, Inc.

5

+1.05VS

J2

@J2

@

PAD-OPEN 4x4m

D D

+1.05VS

R254 0_0603_5%R254 0_0603_5%

This pin can be left as no connect in On-Die VR enabled mode (default).

C C

This pin can be left as no connect in On-Die VR enabled mode (default).

B B

+1.05VS

+3VS

10U

1

2

1 2

0_0603_5%

R260

12

C221

10U_0603_6.3V6M

C221

10U_0603_6.3V6M

+1.05VS_VCCCORE

C209

10U_0603_6.3V6M

C209

10U_0603_6.3V6M

1

2

12

+1.05VS_VCC_EXP

C222

1U_0402_6.3V6K

C222

1U_0402_6.3V6K

1

2

+1.05VS

C210

1U_0402_6.3V6K

C210

1U_0402_6.3V6K

1

2

T47T47

C223

1U_0402_6.3V6K

C223

1U_0402_6.3V6K

1

2

1

C227

0.1U_0402_10V7K

2

1 2

0_0603_5%

1

2

T50T50

R263

1U_0402_6.3V6K

1

2

C211

+VCCAPLLEXP

C224

1U_0402_6.3V6K

C224

1U_0402_6.3V6K

+VCCP_VCCDMI

C212

1U_0402_6.3V6K

C212

1U_0402_6.3V6K

1

2

+1.05VS_VCCDPLLEXP

C225

1U_0402_6.3V6K

C225

1U_0402_6.3V6K

1

2

+3VS_VCCA3GBG

+VCCAFDI_VRM

+1.05VS_VCCAPLL_FDI

+1.05VS_VCCDPLL_FDI

4

U4G

1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER-POINT_FCBGA989

3711mA

POWER

VCC CORE

VCCIO

FDI

1mA

CRTLVDS

1mA

VCCTX_LVDS[1] VCCTX_LVDS[2]

60mA

VCCTX_LVDS[3] VCCTX_LVDS[4]

DMI

20mA

VCCDFTERM[1]

190mA

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

20mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

+VCCADAC

U48

U47

+VCCA_LVDS

AK36 AK37

AM37 AM38 AP36 AP37

+3VS_VCC3_3_6

V33

V34

+VCCAFDI_VRM

AT16

+VCCP_VCCDMI

AT20

+1.05VS_VCC_DMI_CCI

AB36

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

V1

3

1

C213

0.01U_0402_16V7K

2

+VCCTX_LVDS

1

C216

0.01U_0402_16V7K

2

1

C219

0.1U_0402_10V7K

2

C226

1U_0402_6.3V6K

1

C228

0.1U_0402_10V7K

2

1

C230

C230 1U_0402_6.3V6K

1U_0402_6.3V6K

2

R256

0_0603_5%

1

2

1

2

1

C217

0.01U_0402_16V7K

2

+3VS

12

+VCCP_VCCDMI

0_0603_5%

1 2

0_0402_5%

C214

0.1U_0402_10V7K

1

2

+1.8VS+VCCPNAND

R293

12

R399

L1 Change to 1 ohm P/N S RES 1/10W 1 +-1% 0603

10U

L1 1_0603_1%L1 1_0603_1%

1

C215

C215 10U_0603_6.3V6M

10U_0603_6.3V6M

2

0_0603_5%

0.1UH_MLF1608DR10KT_10%_1608

R295

+3VS

12

L2

0.1uH inductor, 200mA

C218

C218 22U_0805_6.3V6M

22U_0805_6.3V6M

+1.05VS

R294

12

0_0603_5%

+3VS

12

2

+3VS

1

C395 10U_0603_6.3V6M

10U_0603_6.3V6M

2

+1.8VS

12

1

C220

C220 1U_0402_6.3V6K

1U_0402_6.3V6K

2

@C395

@

R258

0_0603_5%

+V1.05S_VCCP

12

1

PCH Power Rail Table Refer to CPU EDS R1.5

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

1.05

S0 Iccmax Current (A)

0.001

5

0.001

0.228

0.001

0.075

1.3

0.042

1.05VccIO 3.709

1.05VccASW 0.903

3.3VccSPI 0.01

3.3VccDSW 0.001

1.8 0.002VccDFTERM

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.065

0.01

VccVRM 1.8 / 1.5 0.167

1.05VccCLKDMI

0.075

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.04

+1.5VS

12

R02

R265 0_0603_5%R265 0_0603_5%

Intel recommand stuff R265 and unstuff R266

+VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP

VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (7/9) PWR

LA-7984P

1

0.1

of

20 60Tuesday, December 06, 2011

5

+3VS

12

10U

+3VS_VCC_CLKF33

1

2

1

C256

C256 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C259

C259 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C262

C262 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VM_VCCSUS

1

C264

@C264

@

1U_0402_6.3V6K

2

1

2

10U_0603_6.3V6M

+

C231

220U_B2_2.5VM_R35+C250

220U_B2_2.5VM_R35

C250

C186

22U_0805_6.3V6M@C186

22U_0805_6.3V6M

1

@

2

C232

1U_0402_6.3V6K

C232

1U_0402_6.3V6K

1

2

+1.05VS

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

C251

1U_0402_6.3V6K

C251

1U_0402_6.3V6K

1

2

+1.05VS_VCCDIFFCLKN

R303

0_0603_5%

12

D D

On-Die PLL Voltage Regulator

H：On-Die PLL voltage regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

C C

+1.05VS

L5

1 2

10UH_LB2012T100MR_20%

L6

1 2

10UH_LB2012T100MR_20%

B B

+1.05VS

A A

R274

R274 0_0603_5%

0_0603_5%

R280

R280 0_0603_5%

0_0603_5%

R284

R284 0_0603_5%

0_0603_5%

R290

@R290

@

0_0603_5%

1 2

0_0805_5%

C252

220U_B2_2.5VM_R35+C252

220U_B2_2.5VM_R35

1

+

2

+V1.05S_VCCP

+1.05VS

+3V_PCH

R277

C187

22U_0805_6.3V6M@C187

22U_0805_6.3V6M

@

0.1U_0402_10V7K

R286

R286 0_0603_5%

0_0603_5%

4

Have internal VRM

R268

@R268

@

0_0603_5%

12

R269

0_0603_5%

12

C235

@C235

@

0.1U_0402_10V7K

R271

12

0_0603_5%

C244

1U_0402_6.3V6K

C244

1U_0402_6.3V6K

1

2

12

R300

@R300

@

0_0603_5%

C253

1U_0402_6.3V6K

C253

1U_0402_6.3V6K

1

2

1

C258

2

1

C263

2

12

0.1U_0402_10V7K

C265

4.7U_0603_6.3V6K

C265

4.7U_0603_6.3V6K

1

2

+VCCACLK

+VCCPDSW

1

C234

0.1U_0402_10V7K

2

+PCH_VCCDSW

+3VS_VCC_CLKF33

T101T101

+VCCAPLL_CPY_PCH +VCCDPLL_CPY

+VCCSUS1

1

C239

@C239

@

1U_0402_6.3V6K

2

+1.05VM_VCCASW

22U_0805_6.3V6M

C241

22U_0805_6.3V6M

C241

22U_0805_6.3V6M

1

2

1U_0402_6.3V6K

C245

1U_0402_6.3V6K

C245

1U_0402_6.3V6K

1

2

+VCCRTCEXT

+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

+VCCSST

+1.05VM_VCCSUS

C266

C267

0.1U_0402_10V7K@C267

0.1U_0402_10V7K

1

+RTCVCC

2

@

1

2

C242

C246

+V_CPU_IO

C268

1U_0402_6.3V6K

C268

1U_0402_6.3V6K

1

2

3

POWER

U4J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

C270

0.1U_0402_10V7K@C270

0.1U_0402_10V7K

C269

0.1U_0402_10V7K

C269

0.1U_0402_10V7K

1

PANTHER-POINT_FCBGA989

@

2

POWER

VCCIO[29]

119mA

PCI/GPIO/LPCMISC

SATA USB

HDA

VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

1mA

VCCSUS3_3[1]

1mA

VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5]

VCCAPLLSATA

10mA

VCCSUSHDA

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

V5REF

VCC3_3[1] VCC3_3[8] VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12] VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2] VCCIO[3] VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

3mA

1010mA

Clock and Miscellaneous

80mA 80mA

55mA

95mA

1mA

CPURTC

N26 P26 P28 T27 T29

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

+1.05VS

T21

V21

T19

P32

+1.05VS_VCCUSBCORE

1

2

+3V_VCCPUSB

1

2

+1.05VS_VCCAUPLL

+PCH_V5REF_SUS

+VCCA_USBSUS +3V_VCCPSUS

+PCH_V5REF_RUN

+3V_VCCPSUS

+3VS_VCCPCORE

+3VS_VCCPPCI

+VCC3_3_2

+VCCSATAPLL

+VCCAFDI_VRM

+1.05VS_VCC_SATA

+VCCSUSHDA

1

C271

0.1U_0402_16V4Z

2

C233

C233 1U_0402_6.3V6K

1U_0402_6.3V6K

C236

0.1U_0402_10V7K

C236

0.1U_0402_10V7K

+3V_VCCAUBG

R283

R283 0_0603_5%

0_0603_5%

1

C255

2

0.1U_0402_10V7K

+1.05VS_SATA3

+1.05VS_VCC_SATA

R270

0_0603_5%

1

C238

0.1U_0402_10V7K

2

C243 1U_0402_6.3V6K@C243 1U_0402_6.3V6K@ C316 0.1U_0402_10V7K@C316 0.1U_0402_10V7K@

12

R287

R287 0_0603_5%

0_0603_5%

12

R272

R272 0_0603_5%

0_0603_5%

R273

R273 0_0603_5%

0_0603_5%

R276

R276 0_0603_5%

0_0603_5%

1 2 1 2

+3VS

T100T100

1

C261

C261 1U_0402_6.3V6K

1U_0402_6.3V6K

2

12

2

+1.05VS

+3V_PCH

12

+3V_PCH

12

+1.05VS

12

1

C247

C247 1U_0402_6.3V

1U_0402_6.3V

2

1

C249

0.1U_0402_10V7K

2

1

C254

0.1U_0402_10V7K

2

+1.05VS_SATA3

1

2

+1.05VS

R288

12

0_0603_5%

+3V_PCH

R278

R278 0_0603_5%

0_0603_5%

R281

R281 0_0603_5%

0_0603_5%

R282

R282 0_0603_5%

0_0603_5%

R285

R285 0_0603_5%

0_0603_5%

C257

C257 1U_0402_6.3V6K

1U_0402_6.3V6K

+5VALW +5VALW_PCH

+5VALW_PCH

R275

R275 10_0402_5%

10_0402_5%

R279

R279 10_0402_5%

10_0402_5%

12

R289 0_0603_5%R289 0_0603_5%

+3V_PCH

12

+3VS

12

+3VS

12

+1.05VS

12

On-Die PLL Voltage Regulator

H：On-Die PLL voltage regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

1

+3V_PCH

12

+3VS+5VS

12

21

D1

D1 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

+PCH_V5REF_SUS

1

C240

0.1U_0603_25V7K

2

21

D2

D2 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

+PCH_V5REF_RUN

1

C248

C248 1U_0603_10V6K

1U_0603_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (8/9) PWR

LA-7984P

1

0.1

of

21 60Tuesday, December 06, 2011

5

D D

C C

B B

A A

U4H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

PANTHER-POINT_FCBGA989

4

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

3

U4I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

PANTHER-POINT_FCBGA989

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

2

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (9/9) VSS

LA-7984P

1

0.1

of

22 60Tuesday, December 06, 2011

5

4

3

2

1

U65A

N13P@

U65A

PCIE_CTX_GRX_N[0..15]<5> PCIE_CTX_GRX_P[0..15]<5> PCIE_CRX_GTX_N[0..15]<5>

QV1B

3

+3VS_VGA +3VS_VGA

5

2

P

B

Y

1

A

G

3

UV2

+3VS_VGA

G

S

PCIE_CRX_GTX_P[0..15]<5>

EC_SMB_CK2 <15,39,42>

EC_SMB_DA2 <15,39,42>

@

RV105

RV105 10K_0402_5%

10K_0402_5%

1 2

4

12

RV18

RV18 100K_0402_5%

100K_0402_5%

RV30

RV30 10K_0402_5%

10K_0402_5%

1 2

CLK_REQ_GPU#

RV32

@RV32

@

10K_0402_5%

1 2

D D

+3VS_VGA

RV24

RV25

1 2

DGPU_HOLD_RST#<18>

RV25

2.2K_0402_5%

1 2

2N7002DW-T/R7_SOT363-6

PLT_RST#<18,36,37,42,45>

0.1U_0402_10V7K

2.2K_0402_5%

VGA_SMB_CK2

C C

VGA_SMB_DA2

B B

DGPU_PWR_EN<18,25>

A A

CLK_REQ_VGA#<15>

+3VS_VGA

5

4

2N7002DW-T/R7_SOT363-6

2

QV1A

61

MC74VHC1G08DFT2G SC70 5P

RV29 10K_0402_5%RV29 10K_0402_5%

12

1

R02

CV42

2

1 3

D

QV2

QV2 2N7002H 1N_SOT23-3

2N7002H 1N_SOT23-3

1 2

RV110 0_0402_5%@RV110 0_0402_5%@

5

PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P[0..15]

PCIE_CRX_GTX_N[0..15] PCIE_CRX_GTX_P[0..15]

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_C_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15

Differential signal

CV6 0.22U_0402_10V6KCV6 0.22U_0402_10V6K

1 2

CV7 0.22U_0402_10V6KCV7 0.22U_0402_10V6K

1 2

CV8 0.22U_0402_10V6KCV8 0.22U_0402_10V6K

1 2

CV9 0.22U_0402_10V6KCV9 0.22U_0402_10V6K

1 2

CV10 0.22U_0402_10V6KCV10 0.22U_0402_10V6K

1 2

CV11 0.22U_0402_10V6KCV11 0.22U_0402_10V6K

1 2

CV12 0.22U_0402_10V6KCV12 0.22U_0402_10V6K

1 2

CV13 0.22U_0402_10V6KCV13 0.22U_0402_10V6K

1 2

CV15 0.22U_0402_10V6KCV15 0.22U_0402_10V6K

1 2

CV17 0.22U_0402_10V6KCV17 0.22U_0402_10V6K

1 2

CV19 0.22U_0402_10V6KCV19 0.22U_0402_10V6K

1 2

CV14 0.22U_0402_10V6KCV14 0.22U_0402_10V6K

1 2

CV16 0.22U_0402_10V6KCV16 0.22U_0402_10V6K

1 2

CV18 0.22U_0402_10V6KCV18 0.22U_0402_10V6K

1 2

CV20 0.22U_0402_10V6KCV20 0.22U_0402_10V6K

1 2

CV22 0.22U_0402_10V6KCV22 0.22U_0402_10V6K

1 2

CV24 0.22U_0402_10V6KCV24 0.22U_0402_10V6K

1 2

CV26 0.22U_0402_10V6KCV26 0.22U_0402_10V6K

1 2

CV21 0.22U_0402_10V6KCV21 0.22U_0402_10V6K

1 2

CV23 0.22U_0402_10V6KCV23 0.22U_0402_10V6K

1 2

CV25 0.22U_0402_10V6KCV25 0.22U_0402_10V6K

1 2

CV27 0.22U_0402_10V6KCV27 0.22U_0402_10V6K

1 2

CV29 0.22U_0402_10V6KCV29 0.22U_0402_10V6K

1 2

CV31 0.22U_0402_10V6KCV31 0.22U_0402_10V6K

1 2

CV33 0.22U_0402_10V6KCV33 0.22U_0402_10V6K

1 2

CV28 0.22U_0402_10V6KCV28 0.22U_0402_10V6K

1 2

CV30 0.22U_0402_10V6KCV30 0.22U_0402_10V6K

1 2

CV32 0.22U_0402_10V6KCV32 0.22U_0402_10V6K

1 2

CV36 0.22U_0402_10V6KCV36 0.22U_0402_10V6K

1 2

CV41 0.22U_0402_10V6KCV41 0.22U_0402_10V6K

1 2

CV34 0.22U_0402_10V6KCV34 0.22U_0402_10V6K

1 2

CV35 0.22U_0402_10V6KCV35 0.22U_0402_10V6K

1 2

CLK_PCIE_VGA<15>

CLK_PCIE_VGA#<15>

1 2

RV20 200_0402_1%

4

@

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_N15

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 PCIE_CRX_C_GTX_P4

PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5 PCIE_CRX_C_GTX_P6 PCIE_CRX_C_GTX_N6 PCIE_CRX_C_GTX_P7 PCIE_CRX_C_GTX_N7 PCIE_CRX_C_GTX_P8 PCIE_CRX_C_GTX_N8 PCIE_CRX_C_GTX_P9 PCIE_CRX_C_GTX_N9 PCIE_CRX_C_GTX_P10 PCIE_CRX_C_GTX_N10 PCIE_CRX_C_GTX_P11 PCIE_CRX_C_GTX_N11 PCIE_CRX_C_GTX_P12 PCIE_CRX_C_GTX_N12 PCIE_CRX_C_GTX_P13 PCIE_CRX_C_GTX_N13 PCIE_CRX_C_GTX_P14 PCIE_CRX_C_GTX_N14 PCIE_CRX_C_GTX_P15 PCIE_CRX_C_GTX_N15

CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ_GPU#

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PLT_RST_VGA# PEX_TERMP

RV22

2.49K_0402_1%

1 2

U65

N13M-GE-B-A1

SA00004V010

AN12 AM12 AN14 AM14

AP14

AP15 AN15 AM15 AN17 AM17

AP17

AP18 AN18 AM18 AN20 AM20

AP20

AP21 AN21 AM21 AN23 AM23

AP23

AP24 AN24 AM24 AN26 AM26

AP26

AP27 AN27 AM27

AK14

AJ14 AH14 AG14

AK15

AJ15

AL16

AK16

AK17

AJ17 AH17 AG17

AK18

AJ18

AL19

AK19

AK20

AJ20 AH20 AG20

AK21

AJ21

AL22

AK22

AK23

AJ23 AH23 AG23

AK24

AJ24

AL25

AK25

AJ11

AL13

AK13

AK12

AJ26

AK26

AJ12

AP29

N13M@

15P_0402_50V8J

N13P@

Part 1 of 7

PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N

PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N

PEX_WAKE_N PEX_REFCLK

PEX_REFCLK_N PEX_CLKREQ_N

PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N

PEX_RST_N PEX_TERMP

N13P-GL-A1 MP

CV37

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Part 1 of 7

GPIO

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC DACA_VSYNC

DACs

DACA_VDD DACA_VREF DACA_RSET

PCI EXPRESS

YV1

4

XTALIN

1

27MHZ 16PF +-30PPM X3G027000FG1H-HX

1

2

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2C

I2CC_SDA

I2CS_SCL

I2CS_SDA

SP_PLLVDD

VID_PLLVDD

CLK

XTAL_OUT

XTAL_OUTBUFF

XTAL_SSIN

1 2

RV23 10M_0402_5%RV23 10M_0402_5%

3

NC

OSC

2

OSC

NC

R02

15P_0402_50V8J

2011/06/15 2012/07/11

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

PLLVDD

XTAL_IN

XTAL_OUT

CV38

GPU_VID4

P6

GPU_VID3

M3 L6

VGA_GPIO3

P5 P7

GPU_VID1

L7

GPU_VID2

M7 N8

OVERT#

M1

GC6_EVENT#_R

M2 L1

GPU_VID0

M5

VGA_GPIO12

N3

GPU_VID5

M4 N4

VGA_GPIO15

P2

VGA_GPIO16 DPRSLPVR_VGA

R8 M6 R1 P3 P4 P1

AK9 AL10 AL9

AM9 AN9

+DACA_VDD

AG10 AP9 AP8

VGA_CRT_CLK

R4

VGA_CRT_DATA

R5

I2CB_SCL

R7

I2CB_SDA

R6

VGA_EDID_CLK

R2

VGA_EDID_DATA

R3

VGA_SMB_CK2

T4

VGA_SMB_DA2

T3

60mA

+PLLVDD

RV112

AD8

45mA

AE8

45mA

AD7

XTALIN

H3

XTAL_OUT

H2

XTALOUT

J4

XTALSSIN

H1

RV26

10K_0402_5%

1

2

Compal Secret Data

Deciphered Date

0_0402_5% @

10K_0402_5%

RV107

@RV112

@

1 2

0_0402_5%

12

GPU_VID4 <54> GPU_VID3 <54>

1 2

GPU_VID1 <54> GPU_VID2 <54>

GPU_VID0 <54> GPU_VID5 <54>

DPRSLPVR_VGA

RV113

2 1

CH751H-40PT_SOD323-2

RV17100K_0402_5% @ RV17100K_0402_5% @

1 2

RV1140_0402_5% @ RV1140_0402_5% @

1 2

if GC6 is supported, stuff the BOM option to pull high to 3.3vs system power, if not, stuff the BOM option to pull high to NV3V3;

GC6_EVENT#_R VGA_EDID_CLK VGA_EDID_DATA VGA_CRT_DATA VGA_CRT_CLK

12

I2CB_SCL I2CB_SDA OVERT# VGA_GPIO12

+SP_PLLVDD

Under GPU

12

RV27

10K_0402_5%

+1.05VS_VGA

180ohms (ESR=0.2) Bead

2

BLM18PG330SN1D_0603

R03

DV3

1 2

DMN66D0LDW-7 2N_SOT363-6

VGA_AC_DET <42,54>

R03

1 2

RV49 10K_0402_5%RV49 10K_0402_5%

1 2

RV3 2.2K_0402_5%RV3 2.2K_0402_5%

1 2

RV4 2.2K_0402_5%RV4 2.2K_0402_5%

1 2

RV10 2.2K_0402_5%RV10 2.2K_0402_5%

1 2

RV11 2.2K_0402_5%RV11 2.2K_0402_5%

1 2

RV12 2.2K_0402_5%RV12 2.2K_0402_5%

1 2

RV13 2.2K_0402_5%RV13 2.2K_0402_5%

1 2

RV1 10K_0402_5%RV1 10K_0402_5%

1 2

RV2 10K_0402_5%RV2 10K_0402_5%

30 ohms @100MHz (ESR=0.05)

1

CV131

CV40

2

0.1U_0402_10V7K

22U_0805_6.3V6M

Under GPU(below 150mils)

LV1

22U_0805_6.3V6M

Title

Size Document Number Rev

Date: Sheet

+3VS_VGA

12

LV7

5

61

+1.05VS_VGA

3

4

QV7B

QV7B DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

RV208

10K_0402_5%

QV7A

2

DPRSLPVR_VGA <54>

+3VS_VGA

1 2

FBMA-10-100505-300T 0402

Near GPU

1

CV112

CV113

2

4.7U_0402_6.3V6M

Compal Electronics, Inc.

N13X-PCIE/DAC/GPIO

CV4

2

0.1U_0402_10V7K

LA-7984P

1

2

0.1U_0402_10V7K

PCH_THRMTRIP#_R <19>

150mA

+SP_PLLVDD

CV5

of

23 60Tuesday, December 06, 2011

of

23 60Tuesday, December 06, 2011

of

23 60Tuesday, December 06, 2011

0.1

5

D D

C C

B B

4

U65D

AM6

IFPA_TXC

AN6

IFPA_TXC_N

AP3

IFPA_TXD0

AN3

IFPA_TXD0_N

AN5

IFPA_TXD1

AM5

IFPA_TXD1_N

AL6

IFPA_TXD2

AK6

IFPA_TXD2_N

AJ6

IFPA_TXD3

AH6

IFPA_TXD3_N

AJ9

IFPB_TXC

AH9

IFPB_TXC_N

AP6

IFPB_TXD4

AP5

IFPB_TXD4_N

AM7

IFPB_TXD5

AL7

IFPB_TXD5_N

AN8

IFPB_TXD6

AM8

IFPB_TXD6_N

AK8

IFPB_TXD7

AL8

IFPB_TXD7_N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_I2CW_SCL

AG2

IFPC_AUX_I2CW_SDA_N

AK3

IFPD_AUX_I2CX_SCL

AK2

IFPD_AUX_I2CX_SDA_N

AB3

IFPE_AUX_I2CY_SCL

AB4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

Part 4 of 7

LVDS/TMDS

MULTI_STRAP_REF0_GND

3

NC

VDD_SENSE

GND_SENSE

TEST

TESTMODE

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N ROM_SCLK

ROM_SI

ROM_SO

GENERAL

BUFRST_N

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

THERMDP THERMDN

CEC

P8

NC

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

H31

NC

T8

NC

V32

NC

VCCSENSE_VGA

L4

VSSSENSE_VGA

L5

AK11 AM10

AM11 AP12 AP11 AN11

H6 H4 H5 H7

RV35 10K_0402_5%RV35 10K_0402_5%

L2 L3 J1

J2 J7 J6 J5 J3

K3 K4

VCCSENSE_VGA <54>

VSSSENSE_VGA <54>

trace width: 16mils differential voltage sensing. differential signal routing.

TESTMODE

TV2TV2 TV3TV3 TV4TV4

1 2

RV34 10K_0402_5%RV34 10K_0402_5%

ROM_CS ROM_SCLK ROM_SI ROM_SO

1 2

RV230 10K_0402_5%N13P@RV230 10K_0402_5%N13P@

1 2

RV38 40.2K_0402_1%N13P@RV38 40.2K_0402_1%N13P@

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

TV5TV5

12

ROM_SCLK <32> ROM_SI <32> ROM_SO <32>

+3VS_VGA

STRAP0 <32> STRAP1 <32> STRAP2 <32> STRAP3 <32> STRAP4 <32>

2

12

10K_0402_5%

10K_0402_5% RV33

RV33

R02 3V3 on N13P-GL/ for CEC signal

1

Reserve 1MB SPI ROM FOR VBIOS ROM

RV229

10K_0402_5%

ROM_CS_R ROM_SO_R

+3VS_VGA

12

@RV229

@

20mils

UV15

@

@ 1 2 3 4

VCC

CS#

HOLD#

DO

CLK

WP#

DIO

GND

MX25L1005AMC-12G SOP

8 7 6 5

ROM_HOLD#

ROM_SCLK_R ROM_SI_R

12

RV225

@ RV225

@

10K_0402_5%

RV228 0_0402_5%@RV228 0_0402_5%@

1 2 1 2

RV227 0_0402_5%@RV227 0_0402_5%@

ROM_SCLK ROM_SI

CV295

N13P-GL-A1 MP

N13P@

ROM_CS ROM_SO

A A

CV295

0.1U_0402_16V4Z

RV224 0_0402_5%@RV224 0_0402_5%@

1 2 1 2

RV226 0_0402_5%@RV226 0_0402_5%@

12

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N13X-LVDS/HDMI/DP/THM

LA-7984P

1

of

24 60Tuesday, December 06, 2011

of

24 60Tuesday, December 06, 2011

of

24 60Tuesday, December 06, 2011

0.1

5

4

3

2

1

+1.5VS_VGA

D D

+1.5VS_VGA

4.7uF X7R 0402 * 2

Under GPU(below 150mils)

1

4.7U_0603_6.3V6K

1

CV267

2

4.7U_0603_6.3V6K

CV277

CV268

2

1U_0603_6.3V6M

1

CV278

2

CV279

2

0.1U_0402_10V7K

1

CV280

2

0.1U_0402_10V7K

1

CV292

2

0.1U_0402_10V7K

Near GPU

2

10U_0603_6.3V6M

2

CV269

CV270

CV271

10U_0603_6.3V6M

CV271

1

10U_0603_6.3V6M

1

22U_0805_6.3V6M

1

CV273

@

2

0.1uF X7R 0402 * 8 1uF X7R 0402 * 2

1

CV294

CV287

2

0.1U_0402_10V7K

CV284

2

0.1U_0402_10V7K

1

CV285

2

0.1U_0402_10V7K

3.5A

2

CV272

1

CV286

2

rise 1.5v system source voltage to 1.55-1.57V

C C

+1.5VS_VGA

RV141

@RV141

@

FB_VDDQ_SENSE

12

10_0402_5%

@

RV142

RV142 10_0402_5%

10_0402_5%

+1.5VS_VGA

CALIBRATION PIN FB_CAL_x_PD_VDDQ FB_CAL_x_PU_GND FB_CAL_xTERM_GND

B B

A A

DDR3

40.2Ohm

42.2Ohm

51.1Ohm

FB_VSS_SENSE

12

1 2

RV6 40.2_0402_1%RV6 40.2_0402_1%

1 2

RV8 42.2_0402_1%RV8 42.2_0402_1%

1 2

RV9 51.1_0402_1%RV9 51.1_0402_1%

Place near balls

AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27

AG27

U65E

B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24

H8 H9

L27 M27 N27 P27 R27

T27

T30

T33 V27 W27 W30 W33 Y27

F1

F2

J27

H27

H25

N13P@

Part 5 of 7

FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43

FB_VDDQ_SENSE

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

N13P-GL-A1 MP

2000mA

PEX_PLLVDD

VDD33_0 VDD33_1 VDD33_2 VDD33_3

IFPAB_RSET

IFPA_IOVDD IFPB_IOVDD

IFPC_RSET

IFPC_IOVDD

IFPD_RSET

IFPD_IOVDD

IFPEF_RSET

IFPE_IOVDD IFPF_IOVDD

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

AH12

AG12

AG26

J8 K8 L8 M8

AH8 AJ8

AG8 AG9

AF7 AF8

AF6

AG7 AN2

AG6

AB8 AD6

AC7 AC8

PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13

PEX_PLL_HVDD

PEX_SVDD_3V3

POWER

IFPAB_PLLVDD

IFPC_PLLVDD

IFPD_PLLVDD

IFPEF_PLVDD

1

2

1U_0402_6.3V6K

Under GPU(below 150mils)

1

2

22U_0805_6.3V6M

+PEX_PLLHVDD

+IFPAB_PLLVDD

+IFPAB_IOVDD

+IFPC_PLLVDD

+IFPC_IOVDD

+IFPD_PLLVDD

+IFPD_IOVDD

+IFPEF_PLLVDD

+IFPE_IOVDD

DGPU_PWR_EN<18,23>

+PEX_PLLVDD

1 2

RV48

1 2 1 2

1 2

RV43 1K_0402_1%@RV43 1K_0402_1%@

1 2

RV46 1K_0402_1%@RV46 1K_0402_1%@

1 2 1 2

1 2

SUSP#<10,42,46,51,52,53,54>

RV138 0_0402_5%N13M@RV138 0_0402_5%N13M@

+PEX_SVDD3V3

+VDD33

RV40

RV65 10K_0402_5%RV65 10K_0402_5%

RV42 10K_0402_5%RV42 10K_0402_5%

RV44 10K_0402_5%RV44 10K_0402_5%

RV45 10K_0402_5%RV45 10K_0402_5%

RV47 10K_0402_5%RV47 10K_0402_5%

RV72 10K_0402_5%RV72 10K_0402_5% RV50 1K_0402_1%RV50 1K_0402_1%

RV73 10K_0402_5%RV73 10K_0402_5%

Near GPU

1

CV44

CV43

2

1U_0402_6.3V6K

1

CV53

CV54

2

22U_0805_6.3V6M

1 2

Place near balls Place near GPU

10K_0402_5%

10K_0402_5% 1K_0402_1%@

1K_0402_1%@

12

R1109

@R1109

@

0_0402_5%

12

R1104

R1104 0_0402_5%

0_0402_5%

1

CV46

CV45

2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

22U_0805_6.3V6M

1

2

+1.05VS_VGA

1

CV56

CV55

2

22U_0805_6.3V6M

Under GPU(below 150mils)

1

CV70

2

0.1U_0402_10V7K

1

CV109

CV111

2

0.1U_0402_10V7K

+5VALW

12

R1103

R1103 100K_0402_5%

100K_0402_5%

DGPU_PWR_EN#

13

D

Q128

2

2N7002_SOT23

G

S

12

R1105

R1105 100K_0402_5%

100K_0402_5%

1

CV47

2

1

2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

1

2

CV48

2

4.7U_0603_6.3V6K

+3VS_VGA

CV74

4.7U_0603_6.3V6K

1

CV293

2

4.7U_0603_6.3V6K

Reserve for NV DG

+VDD33

1

CV303

2

@

0.1U_0402_10V7K

R02

2

CV49

1

10U_0603_6.3V6M

1

CV73

2

+PEX_PLLVDD

+3VS_VGA

RV5

12

0_0603_5%

1

CV75

2

1

CV304

@

2

0.1U_0402_10V7K

+3VS to +3VS_VGA

+3VS +3VS_VGA

LP2301ALT1G_SOT23

RV205

1 2

10K_0402_5%

1

2

0.1U_0402_10V7K

2

CV51

CV50

1

10U_0603_6.3V6M

1

2

0.1U_0402_10V7K

Place near balls

J10

@

2

112

JUMP_43X79

QV5

D

S

D

S

13

G

2

CV241

QV6

@

QV6

@

2N7002_SOT23

10U_0603_6.3V6M

CV65

D

S

2

1

12

13

+1.05VS_VGA

CV52

120mA

1

CV3

2

1U_0603_10V6K

CV57

CV57 10U_0603_6.3V6M

10U_0603_6.3V6M

RV206

RV206 470_0603_5%

470_0603_5%

@

2

G

CV242

@ CV242

@

LV2

N13M@LV2

N13M@

0_0603_5%

+1.05VS_VGA

LV2

N13P@LV2

N13P@

@RV207

@

DGPU_PWR_EN#

12

BLM18PG121SN1D_0603

1

120ohms @100MHz (ESR=0.18)

CV66

2

4.7U_0805_25V6-K

12

RV207

10K_0402_5%

1

2

0.1U_0402_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N13X-POWER

LA-7984P

1

25 60Tuesday, December 06, 2011

0.1

of

5

U65F

A2

GND_0

AA17

GND_1

AA18

GND_2

AA20

GND_3

AA22

GND_4

AB12

GND_5

AB14

GND_6

AB16

GND_7

AB19

GND_8

AB2

GND_9

D D

C C

B B

A A

AB21 AB23

AB28 AB30 AB32

AB5

AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22

AE2 AE28 AE30 AE32 AE33

AE5

AE7 AH10 AA15 AH13 AH16 AH19

AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33

AH5

AH7 AK10

AK7

AL12 AL14 AL15 AL17 AL18

AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33

AM13 AM16 AM19 AM22 AM25

AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34

AN4

AN7

AP2 AP33

A33

AJ7

AL2

AL5

B10 B22 B25 B28 B31 B34

C10 C13 C19 C22 C25 C28

GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83

B1

GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90

B4

GND_91

B7

GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98

C7

GND_99

Part 6 of 7

4

D2

GND_100

D31

GND_101

D33

GND_102

E10

GND_103

E22

GND_104

E25

GND_105

E5

GND_106

E7

GND_107

F28

GND_108

F7

GND_109

G10

GND_110

G13

GND_111

G16

GND_112

G19

GND_113

G2

GND_114

G22

GND_115

G25

GND_116

G28

GND_117

G3

GND_118

G30

GND_119

G32

GND_120

G33

GND_121

G5

GND_122

G7

GND_123

K2

GND_124

K28

GND_125

K30

GND_126

K32

GND_127

K33

GND_128

K5

GND_129

K7

GND_130

M13

GND_131

M15

GND_132

M17

GND_133

M18

GND_134

M20

GND_135

M22

GND_136

N12

GND_137

N14

GND_138

N16

GND_139

N19

GND_140

N2

GND_141

N21

GND_142

N23

GND_143

N28

GND_144

N30

GND_145

N32

GND_146

N33

GND_147

N5

GND_148

N7

GND_149

P13

GND_150

P15

GND_151

P17

GND_152

GND

GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198

GND_199 GND_OPT GND_OPT

P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11 C16 W32

3

2

+VGA_CORE

AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23

M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22

U13 U15 U17 U18 U20 U22 V13 V15

T12 T14 T16 T19 T21 T23

U65G

VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55

N13P-GL-A1 MP

N13P@

Part 7 of 7

POWER

VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71

XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8

XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16

XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22

XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30

XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38

V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22

U1 U2 U3 U4 U5 U6 U7 U8

V1 V2 V3 V4 V5 V6 V7 V8

W2 W3 W4 W5 W7 W8

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

1

+VGA_CORE

Security Classification

N13P-GL-A1 MP

N13P@

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N13-VGA CORE, GND

LA-7984P

1

of

26 60Tuesday, December 06, 2011

of

26 60Tuesday, December 06, 2011

of

26 60Tuesday, December 06, 2011

0.1

5

FBA_D[0..63]

U65B

FBA_D0

L28

FBA_D1

M29

FBA_D2

L29

FBA_D3

M28

FBA_D4

D D

C C

B B

A A

FBA_D5 FBA_D6 FBA_D7 FBA_D8

FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS0 FBA_DQS1 FBA_DQS2 FBA_DQS3 FBA_DQS4 FBA_DQS5 FBA_DQS6 FBA_DQS7

FBA_DQS#0 FBA_DQS#1 FBA_DQS#2 FBA_DQS#3 FBA_DQS#4 FBA_DQS#5 FBA_DQS#6 FBA_DQS#7

N31 P29 R29 P28

J28

H29

J29 H28 G29 E31 E32

F30 C34 D32 B33 C33

F33

F32 H33 H32 P34 P32 P31 P33

L31

L34

L32

L33

AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30

AK28 AM29 AM31

AN29 AM30

AN31

AN32

AP30

AP32 AM33

AL31

AK33

AK32

AD34

AD32

AC30

AD33

AF31

AG34

AG32

AG33

P30

F31 F34

M32 AD31 AL29

AM32

AF34

M31

G31

E33

M33 AE31 AK30 AN33 AF33

M30

H30

E34

M34 AF30 AK31

AM34

AF32

N13P-GL-A1 MP N13P@

FBA_DQM[7..0]<28,29>

FBA_DQS[7..0]<28,29>

FBA_DQS#[7..0]<28,29>

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

Part 2 of 7

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_CMD_RFU0 FBA_CMD_RFU1

MEMORY INTERFACE

A

MEMORY INTERFACE

A

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

FB_CLAMP

FB_DLL_AVDD

FBA_PLL_AVDD

FB_VREF

FBA_CS0#_L

U30 T31

FBA_ODT_L

U29

FBA_CKE_L

R34

FBA_MA14

R33

FBA_RST#

U32

FBA_MA9

U33

FBA_MA7

U28

FBA_MA2

V28

FBA_MA0

V29

FBA_MA4

V30

FBA_MA1

U34

FBA_BA0

U31

FBA_WE#

V34

FBA_MA15

V33

FBA_CAS#

Y32

FBA_CS0#_H

AA31 AA29

FBA_ODT_H

AA28

FBA_CKE_H

AC34

FBA_MA13

AC33

FBA_MA8

AA32

FBA_MA6

AA33

FBA_MA11

Y28

FBA_MA5

Y29

FBA_MA3

W31

FBA_BA2

Y30

FBA_BA1

AA34

FBA_MA12

Y31

FBA_MA10

Y34

FBA_RAS#

Y33 V31

R32 AC32

RV58 60.4_0402_1%@RV58 60.4_0402_1%@

R28 AC28

R30 R31 AB31 AC31

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33

E1

K27

1 2

RV59 60.4_0402_1%@RV59 60.4_0402_1%@

1 2

can be unstuff by default

FBA_CLK0 FBA_CLK0# FBC_CLK1 FBA_CLK1 FBA_CLK1#

RV66 10K_0402_5%N13M@RV66 10K_0402_5%N13M@

FB_CLAMP

CV106 0.1U_0402_10V7KCV106 0.1U_0402_10V7K

1 2

Place close to ball

U27

H26

Place close to ball Place close to BGA

30ohms (ESR=0.01) Bead P/N;SM010007W00

FBA_MA[15..0] <28,29> FBA_BA[2..0] <28,29>

FBA_CS0#_L <28> FBA_ODT_L <28>

FBA_CKE_L <28> FBA_RST# <28,29>

FBA_WE# <28,29> FBA_CAS# <28,29>

FBA_CS0#_H <29> FBA_ODT_H <29>

FBA_CKE_H <29>

FBA_RAS# <28,29>

FBA_CLK0 <28> FBA_CLK0# <28> FBA_CLK1 <29> FBA_CLK1# <29>

R02

+FB_PLLAVDD

1

CV107

2

0.1U_0402_10V7K

4

+1.05VS_VGA +FB_PLLAVDD

12

1

CV110

2

1U_0402_6.3V6K

BLM18PG330SN1D_0603

+FB_PLLAVDD

1

CV39

2

22U_0805_6.3V6M

Place close to BGA

1 2

LV3

200mA

+FB_PLLAVDD

3

FBC_D[0..63]

U65C

G9 E9 G8

F9 F11 G11 F12 G12

G6

F5

E6

F6

F4

G4 E2

F3

C2 D4 D3 C1 B3 C4 B5

C5 A11 C11 D11 B11

D8

A8

C8

B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26

E11

E3

A3

C9 F23 F27 C30 A24

D10

D5

C3

B9 E23 E28 B30 A23

D9

E4

B2

A9 D22 D28 A30 B23

Part 3 of 7

FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7

N13P-GL-A1 MP N13P@

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_CMD_RFU0 FBB_CMD_RFU1

FBB_DEBUG0

FBB_DEBUG1

MEMORY INTERFACE B

FBB_CLK0

FBB_CLK0_N

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

FBB_PLL_AVDD

FBC_DQS#[7..0]<30,31>

FBC_D[0..63]<30,31>FBA_D[0..63]<28,29>

FBC_DQM[7..0]<30,31>

FBC_DQS[7..0]<30,31>

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8

FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DQS0

FBC_DQS1

FBC_DQS2

FBC_DQS3

FBC_DQS4

FBC_DQS5

FBC_DQS6

FBC_DQS7

FBC_DQS#0

FBC_DQS#1

FBC_DQS#2

FBC_DQS#3

FBC_DQS#4

FBC_DQS#5

FBC_DQS#6

FBC_DQS#7

2

FBC_MA[15..0] <30,31> FBC_BA[2..0] <30,31>

FBC_CS0#_L

D13 E14

FBC_ODT_L

F14

FBC_CKE_L

A12

FBC_MA14

B12

FBC_RST#

C14

FBC_MA9

B14

FBC_MA7

G15

FBC_MA2

F15

FBC_MA0

E15

FBC_MA4

D15

FBC_MA1

A14

FBC_BA0

D14

FBC_WE#

A15

FBC_MA15

B15

FBC_CAS#

C17

FBC_CS0#_H

D18 E18

FBC_ODT_H

F18

FBC_CKE_H

A20

FBC_MA13

B20

FBC_MA8

C18

FBC_MA6

B18

FBC_MA11

G18

FBC_MA5

G17

FBC_MA3

F17

FBC_BA2

D16

FBC_BA1

A18

FBC_MA12

D17

FBC_MA10

A17

FBC_RAS#

B17 E17

C12 C20

RV60 60.4_0402_1%@RV60 60.4_0402_1%@

G14

1 2

RV61 60.4_0402_1%@RV61 60.4_0402_1%@

G20

1 2

can be unstuff by default

FBC_CLK0

D12

FBC_CLK0#

E12 E20

FBC_CLK1#

F20

F8 E8 A5 A6 D24 D25 B27 C27

D6 D7 C6 B6 F26 E26 A26 A27

H17

1

2

0.1U_0402_10V7K

Mode D - Mirror Mode Mapping

FBC_CLK0 <30> FBC_CLK0# <30> FBC_CLK1 <31> FBC_CLK1# <31>

+FB_PLLAVDD

CV108

Place close to ball

FBC_CS0#_L <30> FBC_ODT_L <30>

FBC_CKE_L <30> FBC_RST# <30,31>

FBC_WE# <30,31> FBC_CAS# <30,31>

FBC_CS0#_H <31> FBC_ODT_H <31>

FBC_CKE_H <31>

FBC_RAS# <30,31>

+1.5VS_VGA+1.5VS_VGA

Address

FBx_CMD0 FBx_CMD1 FBx_CMD2 FBx_CMD3 FBx_CMD4 FBx_CMD5 FBx_CMD6 FBx_CMD7 FBx_CMD8 FBx_CMD9 FBx_CMD10 FBx_CMD11 FBx_CMD12 FBx_CMD13 FBx_CMD14 FBx_CMD15 FBx_CMD16 FBx_CMD17 FBx_CMD18 FBx_CMD19 FBx_CMD20 FBx_CMD21 FBx_CMD22 FBx_CMD23 FBx_CMD24 FBx_CMD25 FBx_CMD26 FBx_CMD27 FBx_CMD28 FBx_CMD29 FBx_CMD30

DATA Bus

0..31 CS0#_L

ODT_L CKE_L A14 RST

A9 A7 A2 A0 A4 A1 BA0 WE# A15

CAS#

A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

1

32..63

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# A15 CAS# CS0#_H

ODT_H CKE_H A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N13X-MEM Interface

LA-7984P

1

27 60Tuesday, December 06, 2011

0.1

of

5

4

3

2

1

Memory Partition A - Lower 32 bits

UV4

UV3

D D

C C

B B

+1.5VS_VGA

12

RV79

1.1K_0402_1%

+FBA_VREF0

12

FBA_CLK0

FBA_CLK0#

UV3 SIDE

1

CV118

2

0.01U_0402_25V7K

FBA_RST#<27,29>

FBA_CLK0<27> FBA_CLK0#<27> FBA_CKE_L<27>

FBA_ODT_L<27> FBA_CS0#_L<27> FBA_RAS#<27,29> FBA_CAS#<27,29> FBA_WE#<27,29>

RV78

10K_0402_5%

RV68

1.1K_0402_1%

RV80

RV80 160_0402_1%

160_0402_1%

1 2

+1.5VS_VGA +1.5VS_VGA

+FBA_VREF0

12

RV77

243_0402_1%

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLK0 FBA_CLK0# FBA_CKE_L

FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_WE#

FBA_DQS0 FBA_DQS3

FBA_DQM0 FBA_DQM3

FBA_DQS#0 FBA_DQS#3

FBA_RST#

12

UV3

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBA_D4

E3

FBA_D1

F7

FBA_D7

F2

FBA_D0

F8

FBA_D6

H3 H8

FBA_D5

G2

FBA_D2

H7

FBA_D29

D7

FBA_D25

C3

FBA_D28

C8

FBA_D26

C2

FBA_D31

A7

FBA_D24

A2

FBA_D30

B8

FBA_D27

A3

+1.5VS_VGA +1.5VS_VGA

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group0 (IN3)

Group3 (BOT)

+FBA_VREF0

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_D22 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLK0 FBA_CLK0# FBA_CKE_L

FBA_ODT_L FBA_CS0#_L FBA_RAS# FBA_CAS# FBA_ODT_L FBA_WE#

FBA_DQS2 FBA_DQS1

FBA_DQM2 FBA_DQM1

FBA_DQS#2 FBA_DQS#1

FBA_RST#

12

RV69

243_0402_1%

UV4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4W1G1646E-HC12_FBGA96

X76@

UV4 SIDE

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBA_D19

E3

FBA_D20

F7

FBA_D17

F2

FBA_D21

F8

FBA_D16

H3

FBA_D23FBA_D3

H8

FBA_D18

G2 H7

FBA_D10

D7

FBA_D15

C3

FBA_D8

C8

FBA_D13

C2

FBA_D9

A7

FBA_D12

A2

FBA_D11

B8

FBA_D14

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group2 (IN1)

Group1 (TOP)

FBA_CKE_L

10K_0402_5%

RV67

1 2

FBA_MA[15..0] <27,29> FBA_BA[2..0] <27,29>

RV76

10K_0402_5%

1 2

CMD mapping mod Mode D

Address

FBx_CMD0 FBx_CMD1 FBx_CMD2 FBx_CMD3 FBx_CMD4 FBx_CMD5 FBx_CMD6 FBx_CMD7 FBx_CMD8 FBx_CMD9 FBx_CMD10 FBx_CMD11 FBx_CMD12 FBx_CMD13 FBx_CMD14 FBx_CMD15 FBx_CMD16 FBx_CMD17 FBx_CMD18 FBx_CMD19 FBx_CMD20 FBx_CMD21 FBx_CMD22 FBx_CMD23 FBx_CMD24 FBx_CMD25 FBx_CMD26 FBx_CMD27 FBx_CMD28 FBx_CMD29 FBx_CMD30

FBA_D[0..63] <27,29>

FBA_DQM[7..0] <27,29>

FBA_DQS[7..0] <27,29>

FBA_DQS#[7..0] <27,29>

DATA Bus

0..31 CS0#_L

ODT_L CKE_L A14 RST

A9 A7 A2 A0 A4 A1 BA0 WE# A15

CAS#

A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

32..63

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# A15 CAS# CS0#_H

ODT_H CKE_H A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

1

2

1

CV120

2

1U_0402_6.3V6K

5

CV121

1U_0402_6.3V6K

1

CV119

A A

2

0.1U_0402_10V7K

1

2

1

CV123

2

1U_0402_6.3V6K

1

CV162

2

1U_0402_6.3V6K

CV161

@CV161

@

1

CV159

2

0.1U_0402_10V7K

1

CV134

2

1U_0402_6.3V6K

4

1

CV160

CV129

2

1U_0402_6.3V6K

1

CV133

2

1U_0402_6.3V6K

CV132

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

CV164

2

0.1U_0402_10V7K

1

CV136

@CV136

@

2

1U_0402_6.3V6K

2011/06/15 2012/07/11

3

1

2

1

CV163

2

1U_0402_6.3V6K

CV137

1U_0402_6.3V6K

Compal Secret Data

1

CV135

2

1U_0402_6.3V6K

Deciphered Date

1

CV157

@CV157

@

2

0.1U_0402_10V7K

1

CV155

@CV155

@

2

0.1U_0402_10V7K

1

CV138

@CV138

@

2

1

CV142

2

1U_0402_6.3V6K

1

CV143

@CV143

@

1

CV144

CV158

@CV144

@

2

1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

N13X-VRAM A Lower

LA-7984P

28 60Tuesday, December 06, 2011

1

0.1

of

5

4

3

2

1

Memory Partition A - Upper 32

FBA_D[0..63] <27,28>

bits

+1.5VS_VGA

12

RV70

D D

C C

FBA_CKE_H

FBA_ODT_H

B B

+1.5VS_VGA +1.5VS_VGA

A A

RV70

1.1K_0402_1%

RV82

1.1K_0402_1%

RV83

RV83 160_0402_1%

160_0402_1%

1 2

RV84

10K_0402_5%

UV5 SIDE

1

CV145

2

0.1U_0402_10V7K

12

FBA_CLK1

FBA_CLK1#

12

1

CV174

2

+FBA_VREF1

1

CV178

2

0.01U_0402_25V7K

12

10K_0402_5%

1

CV296

2

1U_0402_6.3V6K

1

2

FBA_CLK1<27> FBA_CLK1#<27> FBA_CKE_H<27>

FBA_ODT_H<27> FBA_CS0#_H<27> FBA_RAS#<27,28> FBA_CAS#<27,28> FBA_WE#<27,28>

RV87

FBA_RST#<27,28>

CV301

+FBA_VREF1 +FBA_VREF1

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLK1 FBA_CLK1# FBA_CKE_H

FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_WE#

FBA_DQS4 FBA_DQS5

FBA_DQM4 FBA_DQM5

FBA_DQS#4 FBA_DQS#5 FBA_DQS#6

FBA_RST#

12

RV86

243_0402_1%

1

2

1U_0402_6.3V6K

CV291

2

1U_0402_6.3V6K

CV302

UV5

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

1

2

0.1U_0402_10V7K

CV290

CV299

2

0.1U_0402_10V7K

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

1

CV300

2

1U_0402_6.3V6K

FBA_D36 FBA_D34 FBA_D37 FBA_D35 FBA_D39 FBA_D32 FBA_D38 FBA_D33

FBA_D45 FBA_D42 FBA_D46 FBA_D41 FBA_D47 FBA_D43 FBA_D44 FBA_D40

+1.5VS_VGA +1.5VS_VGA

Group4 (IN1)

Group5 (TOP)

FBA_RST#

RV85

243_0402_1%

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 FBA_MA15

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLK1 FBA_CLK1# FBA_CKE_H

FBA_ODT_H FBA_CS0#_H FBA_RAS# FBA_CAS# FBA_WE#

FBA_DQS7 FBA_DQS6

FBA_DQM7 FBA_DQM6

FBA_DQS#7

12

UV6 SIDE

1

CV298

CV297

2

1U_0402_6.3V6K

1

CV165

2

1U_0402_6.3V6K

1

CV177

2

0.1U_0402_10V7K

1

CV170

@CV170

@

2

1

CV166

2

1U_0402_6.3V6K

1

2

1

CV172

2

1U_0402_6.3V6K

UV6

M8

H1 N3

P7 P3 N2 P8 P2 R8 R2 T8 R3

L7 R7 N7 T3 T7

M7

M2

N8

M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

J1

L1

J9

L9

K4W1G1646E-HC12_FBGA96

X76@

1

CV179

CV173

@CV179

@

@CV173

@

2

1U_0402_6.3V6K

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

1

CV169

@CV169

@

2

0.1U_0402_10V7K

FBA_D63 FBA_D58 FBA_D60 FBA_D59 FBA_D61 FBA_D56 FBA_D62 FBA_D57

FBA_D55 FBA_D51 FBA_D54 FBA_D49 FBA_D52 FBA_D50 FBA_D53 FBA_D48

1

CV180

CV167

@CV180

@

2

1U_0402_6.3V6K

Group7 (IN3)

Group6 (BOT)

1

CV171

2

1U_0402_6.3V6K

CMD mapping mod Mode D

Address

FBx_CMD0 FBx_CMD1 FBx_CMD2 FBx_CMD3 FBx_CMD4 FBx_CMD5 FBx_CMD6 FBx_CMD7 FBx_CMD8 FBx_CMD9 FBx_CMD10 FBx_CMD11 FBx_CMD12 FBx_CMD13 FBx_CMD14 FBx_CMD15 FBx_CMD16 FBx_CMD17 FBx_CMD18 FBx_CMD19 FBx_CMD20 FBx_CMD21 FBx_CMD22 FBx_CMD23 FBx_CMD24 FBx_CMD25 FBx_CMD26 FBx_CMD27 FBx_CMD28 FBx_CMD29 FBx_CMD30

1

CV175

CV168

@CV175

@

@CV168

@

2

1U_0402_6.3V6K

FBA_MA[15..0] <27,28> FBA_BA[2..0] <27,28>

FBA_DQM[7..0] <27,28> FBA_DQS[7..0] <27,28>

FBA_DQS#[7..0] <27,28>

DATA Bus

0..31

32..63

CS0#_L

ODT_L CKE_L A14 RST

A9 A7 A2 A0 A4 A1 BA0 WE# A15

CAS#

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# A15 CAS# CS0#_H

ODT_H

CKE_H A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS#

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N13X-VRAM A Upper

LA-7984P

29 60Tuesday, December 06, 2011

1

0.1

of

5

4

3

2

1

Memory Partition C - Lower 32 bits

+1.5VS_VGA

12

243_0402_1%

+FBB_VREF0

FBC_MA0 FBC_MA1 FBC_MA2 FBC_MA3 FBC_MA4 FBC_MA5 FBC_MA6 FBC_MA7 FBC_MA8 FBC_MA9 FBC_MA10 FBC_MA11 FBC_MA12 FBC_MA13 FBC_MA14 FBC_MA15

FBC_BA0 FBC_BA1 FBC_BA2

FBC_CLK0 FBC_CLK0# FBC_CKE_L

FBC_ODT_L FBC_CS0#_L FBC_RAS# FBC_CAS# FBC_WE#

FBC_DQS0 FBC_DQS3

FBC_DQM0 FBC_DQM3

FBC_DQS#0 FBC_DQS#3

FBC_RST#

RV90

12

D D

1.1K_0402_1%

C C

B B

+1.5VS_VGA +1.5VS_VGA

12

RV111

12

RV115

FBC_CLK0

RV89

RV89 160_0402_1%

160_0402_1%

1 2

FBC_CLK0#

UV7 SIDE

+FBB_VREF0

1

CV202

2

0.01U_0402_25V7K

FBC_RST#<27,31>

10K_0402_5%

FBC_CLK0<27> FBC_CLK0#<27> FBC_CKE_L<27>

FBC_ODT_L<27> FBC_CS0#_L<27> FBC_RAS#<27,31> FBC_CAS#<27,31> FBC_WE#<27,31>

RV91

UV7

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

310mA

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

UV8

FBC_D4

E3

FBC_D3

F7

FBC_D7

F2

FBC_D0

F8

FBC_D5

H3

FBC_D1

H8

FBC_D6

G2

FBC_D2

H7

FBC_D28

D7

FBC_D27

C3

FBC_D31

C8

FBC_D25

C2

FBC_D29

A7

FBC_D24 FBC_D13

A2

FBC_D30

B8

FBC_D26

A3

+1.5VS_VGA +1.5VS_VGA

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group0 (IN3)

Group3 (BOT)

+FBB_VREF0

FBC_RST#

RV88

243_0402_1%

FBC_MA0 FBC_MA1 FBC_MA2 FBC_MA3 FBC_MA4 FBC_MA5 FBC_MA6 FBC_MA7 FBC_MA8 FBC_MA9 FBC_MA10 FBC_MA11 FBC_MA12 FBC_MA13 FBC_MA14 FBC_MA15

FBC_BA0 FBC_BA1 FBC_BA2

FBC_CLK0 FBC_CLK0# FBC_CKE_L

FBC_ODT_L FBC_CS0#_L FBC_RAS# FBC_CAS# FBC_WE#

FBC_DQS2 FBC_DQS1

FBC_DQM2 FBC_DQM1

FBC_DQS#2 FBC_DQS#1

12

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

UV8 SIDE

FBC_D16 FBC_D21 FBC_D18 FBC_D17 FBC_D20 FBC_D23 FBC_D19 FBC_D22

FBC_D8 FBC_D15 FBC_D11 FBC_D12

FBC_D9 FBC_D10

FBC_D14

Group2 (IN1)

Group1 (TOP)

FBC_ODT_L

FBC_CKE_L

10K_0402_5%

RV117

CMD mapping mod Mode D

Address

FBx_CMD0 FBx_CMD1 FBx_CMD2 FBx_CMD3 FBx_CMD4 FBx_CMD5 FBx_CMD6 FBx_CMD7 FBx_CMD8 FBx_CMD9 FBx_CMD10 FBx_CMD11 FBx_CMD12 FBx_CMD13 FBx_CMD14 FBx_CMD15

12

RV116

10K_0402_5%

FBx_CMD16 FBx_CMD17 FBx_CMD18 FBx_CMD19 FBx_CMD20 FBx_CMD21 FBx_CMD22 FBx_CMD23 FBx_CMD24 FBx_CMD25 FBx_CMD26 FBx_CMD27 FBx_CMD28 FBx_CMD29 FBx_CMD30

FBC_D[0..63] <27,31>

FBC_MA[15..0] <27,31>

FBC_BA[2..0] <27,31> FBC_DQM[7..0] <27,31> FBC_DQS[7..0] <27,31>

FBC_DQS#[7..0] <27,31>

DATA Bus

0..31 CS0#_L

ODT_L CKE_L A14 RST

A9 A7 A2 A0 A4 A1 BA0 WE# A15

CAS#

A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

32..63

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# A15 CAS# CS0#_H

ODT_H CKE_H A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

1

A A

2

0.1U_0402_10V7K

CV191

@CV191

@

2

0.1U_0402_10V7K

CV183

@CV183

@

1U_0402_6.3V6K

1

2

5

1

CV199

2

1U_0402_6.3V6K

1

CV189

2

1U_0402_6.3V6K

1

CV205

2

1U_0402_6.3V6K

CV188

@CV188

@

1

CV190

@CV190

@

2

0.1U_0402_10V7K

1

CV206

CV181

@CV181

@

2

1U_0402_6.3V6K

4

1

CV182

2

1U_0402_6.3V6K

1

CV185

CV194

@CV185

@

@CV194

@

2

0.1U_0402_10V7K

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_10V7K

1

CV192

2

1

CV203

CV195

2

0.1U_0402_10V7K

CV195

2

1U_0402_6.3V6K

2011/06/15 2012/07/11

3

1

2

CV197

CV184

2

1U_0402_6.3V6K

Compal Secret Data

Deciphered Date

1

CV186

2

1U_0402_6.3V6K

1

CV187

2

0.1U_0402_10V7K

1

CV198

2

0.1U_0402_10V7K

1U_0402_6.3V6K

2

CV200

1

CV201

2

1U_0402_6.3V6K

1

CV204

CV193

2

1U_0402_6.3V6K

Title

Size Document Number Rev

Custom

Date: Sheet

CV193

2

1U_0402_6.3V6K

Compal Electronics, Inc.

N13X-VRAM C Lower

LA-7984P

1

0.1

of

30 60Tuesday, December 06, 2011

5

4

3

2

1

Memory Partition C - Upper 32 bits

FBC_D[0..63] <27,30>

FBC_MA[15..0] <27,30>

UV10

UV9

+1.5VS_VGA

D D

1.1K_0402_1%

C C

FBC_ODT_H

FBC_CKE_H

10K_0402_5%

B B

10K_0402_5%

RV120

RV127

RV118

12

RV129

RV129 160_0402_1%

160_0402_1%

1 2

12

+FBB_VREF1

1

CV229

2

0.01U_0402_25V7K

FBC_CLK1

FBC_CLK1#

12

RV119

10K_0402_5%

FBC_CLK1<27> FBC_CLK1#<27> FBC_CKE_H<27>

FBC_ODT_H<27> FBC_CS0#_H<27> FBC_RAS#<27,30> FBC_CAS#<27,30> FBC_WE#<27,30>

FBC_RST#<27,30>

+FBB_VREF1

FBC_CLK1 FBC_CLK1# FBC_CKE_H

FBC_ODT_H FBC_CS0#_H FBC_RAS# FBC_CAS# FBC_WE#

RV123

243_0402_1%

FBC_MA0 FBC_MA1 FBC_MA2 FBC_MA3 FBC_MA4 FBC_MA5 FBC_MA6 FBC_MA7 FBC_MA8 FBC_MA9 FBC_MA10 FBC_MA11 FBC_MA12 FBC_MA13 FBC_MA14 FBC_MA15

FBC_BA0 FBC_BA1 FBC_BA2

FBC_DQS4 FBC_DQS5

FBC_DQM4 FBC_DQM5

FBC_DQS#4 FBC_DQS#5

FBC_RST#

12

UV9

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBC_D39

E3

FBC_D33

F7

FBC_D38

F2

FBC_D32

F8

FBC_D36

H3

FBC_D35

H8

FBC_D37

G2

FBC_D34

H7

FBC_D47

D7

FBC_D43

C3

FBC_D46

C8

FBC_D42

C2

FBC_D40

A7

FBC_D45

A2

FBC_D44

B8

FBC_D41

A3

+1.5VS_VGA +1.5VS_VGA

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group4 (IN1)

Group5 (TOP)

+FBB_VREF1

FBC_RST#

RV128

243_0402_1%

FBC_MA0 FBC_MA1 FBC_MA2 FBC_MA3 FBC_MA4 FBC_MA5 FBC_MA6 FBC_MA7 FBC_MA8 FBC_MA9 FBC_MA10 FBC_MA11 FBC_MA12 FBC_MA13 FBC_MA14 FBC_MA15

FBC_BA0 FBC_BA1 FBC_BA2

FBC_CLK1 FBC_CLK1# FBC_CKE_H

FBC_ODT_H FBC_CS0#_H FBC_RAS# FBC_CAS# FBC_WE#

FBC_DQS7 FBC_DQS6

FBC_DQM7 FBC_DQM6

FBC_DQS#7 FBC_DQS#6

12

UV10

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBC_D60

E3

FBC_D57

F7

FBC_D63

F2

FBC_D58

F8

FBC_D61

H3

FBC_D56

H8

FBC_D62

G2

FBC_D59

H7

FBC_D54

D7

FBC_D51

C3

FBC_D55

C8

FBC_D49

C2

FBC_D52

A7

FBC_D50

A2

FBC_D53

B8

FBC_D48

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group7 (IN3)

Group6 (BOT)

CMD mapping mod Mode D

Address

FBx_CMD0 FBx_CMD1 FBx_CMD2 FBx_CMD3 FBx_CMD4 FBx_CMD5 FBx_CMD6 FBx_CMD7 FBx_CMD8 FBx_CMD9 FBx_CMD10 FBx_CMD11 FBx_CMD12 FBx_CMD13 FBx_CMD14 FBx_CMD15 FBx_CMD16 FBx_CMD17 FBx_CMD18 FBx_CMD19 FBx_CMD20 FBx_CMD21 FBx_CMD22 FBx_CMD23 FBx_CMD24 FBx_CMD25 FBx_CMD26 FBx_CMD27 FBx_CMD28 FBx_CMD29

+1.5VS_VGA +1.5VS_VGA

UV9 SIDE

UV10 SIDE

FBx_CMD30

FBC_BA[2..0] <27,30> FBC_DQM[7..0] <27,30> FBC_DQS[7..0] <27,30>

FBC_DQS#[7..0] <27,30>

DATA Bus

0..31

32..63

CS0#_L

ODT_L CKE_L A14 RST

A9 A7 A2 A0 A4 A1 BA0 WE# A15

CAS#

A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# A15 CAS# CS0#_H

ODT_H CKE_H A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS#

1

CV209

2

A A

0.1U_0402_10V7K

1

2

1

CV227

@CV227

@

2

1U_0402_6.3V6K

1

CV213

2

1U_0402_6.3V6K

5

1

CV233

2

1U_0402_6.3V6K

1

CV226

2

1U_0402_6.3V6K

CV207

1

CV230

@CV230

@

2

0.1U_0402_10V7K

1

CV220

2

0.1U_0402_10V7K

1U_0402_6.3V6K

4

CV221

1

CV228

@CV228

@

2

1U_0402_6.3V6K

1

CV225

CV210

2

1U_0402_6.3V6K

1

CV208

@CV208

@

2

0.1U_0402_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

CV211

CV223

@CV211

@

2

1U_0402_6.3V6K

2011/06/15 2012/07/11

3

1

CV222

CV212

@CV222

@

2

1U_0402_6.3V6K

Compal Secret Data

1

CV231

@CV231

@

2

1U_0402_6.3V6K

Deciphered Date

0.1U_0402_10V7K

1

CV224

2

1

CV214

2

0.1U_0402_10V7K

1U_0402_6.3V6K

2

1

CV215

CV217

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

Custom

CV232

CV218

2

1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

N13X-VRAM C Upper

LA-7984P

31 60Tuesday, December 06, 2011

1

of

0.1

5

RV93

X76@RV93

RV92

45.3K_0402_1%

1 2

STRAP0<24> STRAP1<24>

D D

STRAP2<24> STRAP3<24> STRAP4<24>

C C

ROM_SI<24>

ROM_SO<24>

ROM_SCLK<24>

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

ROM_SI ROM_SO ROM_SCLK

X76

X76@

1 2

+3VS_VGA

1 2

RV95

X76@RV95

X76@

45.3K_0402_1%

RV98

4.99K_0402_1%

X76@

RV101

RV101 20K_0402_1%

20K_0402_1%

X76@

45.3K_0402_1%

1 2

RV96

X76@RV96

X76@

45.3K_0402_1%

1 2

RV96

N13M@

RV96

N13M@

34.8K_0402_1%

SD034348280

RV99

X76@RV99

X76@

30K_0402_1%

1 2

RV102

RV102 30K_0402_1%

30K_0402_1%

X76@

1 2

For N13P-GL strap table

B B

N13P-GL

Frenq. strap3 strap4GPU

900 MHz 900 MHz 900 MHz 900 MHz

128M* 16* 8 2GB 128M* 16* 8 2GB 64M* 16* 8 1GB 64M* 16* 8 1GB

Memory Config

Samsung (2Gb) K4W2G1646C-HC11 Hynix (2Gb) H5TQ1G63DFR-11C Samsung (1Gb) K4W1G1646G-BC11 Hynix (1Gb) H5TQ1G63DFR-11C

strap0 strap1 strap2 ROM_SI ROM_SO ROM_SCLKMemory Size R

PU 45K R PU 45K R PU 45K R PU 45K

R PD 45KRPU 10K R PD 45K R PD 45K R PD 45K

R02

RV94

X76@RV94

X76@

10K_0402_1%

R02

RV97

X76@RV97

X76@

10K_0402_1%

RV100

X76@RV100

X76@

4.99K_0402_1%

RV103

X76@RV103

X76@

15K_0402_1%

R PU 10K R PU 10K R PU 10K

4

1 2

RV103

n/a n/a n/a n/a

RV121

X76@RV121

X76@

20K_0402_1%

RV124

X76@RV124

X76@

4.99K_0402_1%

N13M@

4.99K_0402_1%

SD034499180

n/a n/a n/a n/a

+3VS_VGA

1 2

X76

R PD 45K R PD 35K R PD 20K R PD 15K

RV122

X76@RV122

X76@

20K_0402_1%

RV125

X76@RV125

X76@

10K_0402_1%

ZZZ

Samsung

S2GP@

X7634138L01

ZZZ

Hynix

H2GP@

X7634138L02

ZZZ

Samsung

S1GP@

X7634138L03

ZZZ

Hynix

H1GP@

X7634138L04

R PD 30KRPD 15K R PD 30K R PD 30K R PD 30K

ZZZ

Samsung

S1GM@

X7634138L05

ZZZ

Hynix

H1GM@

X7634138L06

ZZZ

Samsung

S512M@

X7634138L07

ZZZ

Hynix

H512M@

X7634138L08

R PD 15K R PD 15K R PD 15K

3

Physical Strapping pin ROM_SCLK

ROM_SI ROM_SO FB[0] STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

Power Rail

+3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA

Resistor Values

5K 10K 15K 20K 25K 30K 35K 45K

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] SOR3_EXPOSED

RESERVED PCIE_SPEED_

Pull-up to +3VS_VGA

1000 1001 1010 1011 1100 1101 1110 1111

SUB_VENDOR

0

No VBIOS ROM

1

BIOS ROM is present (Default)

FB_0_BAR_SIZE

0

Reserved

1

Reserved

2

256MB (Default)

3

Reserved

USER Straps

2

Logical Strapping Bit2 SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

CHANGE_GEN3

Pull-down to Gnd

0000 0001 0010 0011 0100 0101 0110 0111

3GIO_PADCFG

3GIO_PADCFG[3:0]

0110

SLOT_CLK_CFG

0

GPU and MCH don't share a common reference clock

1

GPU and MCH share a common reference clock (Default)

SMBUS_ALT_ADDR

0

0x9E (Default)

1

0x9C (Multi-GPU usage)

User[3:0]

1000-1100

Customer defined

Logical Strapping Bit1

SLOT_CLK_CFG RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

PCIE_MAX_SPEED DP_PLL_VDD33V

Notebook Default

XCLK_417

0

277MHz (Default)

1

Reserved

VGA_DEVICE

0

3D Device (Class Code 302h)

1

VGA Device (Default)

1

Logical Strapping Bit0

PEX_PLL_EN_TERM RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

PEX_PLL_EN_TERM

0

Disable (Default)

For N13M-GE strap table

GPU

N13M-GE

A A

Frenq. strap3 strap4

128M* 16* 4

900 MHz

1GB 128M* 16* 4

900 MHz

1GB 64M* 16* 4

900 MHz

512MB 64M* 16* 4

900 MHz

512MB

Memory Config

Samsung (2Gb) K4W2G1646C-HC11 Hynix (2Gb) H5TQ1G63DFR-11C Samsung (1Gb) K4W1G1646G-BC11 Hynix (1Gb) H5TQ1G63DFR-11C

strap0 strap1 strap2 ROM_SI ROM_SO ROM_SCLKMemory Size R

PU 45KRPD 35KRPD 10K R

R PD 35K R PD 35K R PD 35K

R PD 10K R PD 10K R PD 10K

PU 45K R PU 45K R PU 45K

R PD 5KRPD 10K R PD 5K R PD 5K R PD 5K

R PD 10K R PD 10K R PD 10K

R PD 45K R PD 35K R PD 20K R PD 15K

R PD 30KRPD 5K R PD 30K R PD 30K R PD 30K

R PD 5K R PD 5K R PD 5K

1

Enable

PCIE_MAX_SPEED

0

Limit to PCIE Gen1

1

PCIE Gen 2/3 Capable

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

N13X_MISC

LA-7984P

1

of

32 60Tuesday, December 06, 2011

0.1

5

4

3

2

1

LCD POWER CIRCUIT

+5VALW

R400

R400 150_0603_1%

D

Q79

S

@ R408

@

100K_0402_5%

150_0603_1%

13

2

G

12

R408

2

D D

2N7002_SOT23

PCH_ENVDD<17>

12

R401

R401 100K_0402_5%

100K_0402_5%

1

OUT

IN

GND

DTC124EKAT146_SC59-3

3

R403

220K_0402_5%

1 2

C515

0.1U_0402_16V4Z

Q81

C515

DTC124EK

+3VS+LCDVDD

W=60mils

1

C513

4.7U_0805_10V4Z

2

S

G

Q80

2

1

2

FBMA-L11-201209-221LMA30T_0805

Q80 PMV65XP_SOT23-3~D

PMV65XP_SOT23-3~D

D

1 3

+LCDVDD

1 2

+LCDVDD_CONN

L29

C516

4.7U_0805_10V4Z

W=60mils

1

C517

0.1U_0402_16V4Z

2

+3VS

(20 MIL)

Q83

Q83 PMV65XP_SOT23-3~D

@C542

@

CMOS@C520

CMOS@

PMV65XP_SOT23-3~D

S

+3VALW

1

C542

0.1U_0402_16V4Z

R435

CMOS@R435

CMOS@

150K_0402_5%

CMOS_ON#<42>

150K_0402_5%

0.1U_0402_16V4Z

2

4.7V

1

C520

0.1U_0402_16V4Z

2

CMOS Camera

CMOS@

D

13

G

2

+3VS_CMOS

CMOS@

(20 MIL)

12

R296

1

2

R296

CMOS@

0_0603_5%

C518

0.1U_0402_16V4Z

R296 for CMOS shake issue reserve

R02

10U

1

C519

@C519

@

10U_0603_6.3V6M

2

VGA LCD/PANEL BD. Conn.

C C

1 2

1

C539

680P_0402_50V7K

+3VS

R717 0_0402_5%R717 0_0402_5%

1 2

BKOFF#<42> PCH_PWM<17>

12

R716

1 2

R716 10K_0402_5%

10K_0402_5%

@

100K_0402_1%

B B

PCH_ENBKL<17>

R538 0_0402_5%

R02

21

D4

@D4

@

CH751H-40PT_SOD323-2

R438

1 2

12

R433

4.7K_0402_5%

@R433

@

DISPOFF#BKOFF#

ENBKL <42>

DISPOFF#

R430 0_0402_5%R430 0_0402_5%

1 2

@C540

@

CMOS

LVDS_ACLK<17> LVDS_ACLK#<17>

LVDS_A2<17> LVDS_A2#<17> LVDS_A1<17> LVDS_A1#<17> LVDS_A0<17> LVDS_A0#<17>

EDID_DATA<17> EDID_CLK<17>

1

+LCDVDD_CONN

2

+3VS_CMOS

USB20_P5<18> USB20_N5<18>

+3VS

R431 0_0402_5%@R431 0_0402_5%@

EC_INVT_PWM<42>

1 2

+3VS

680P_0402_50V7K

C540

INVT_PWM

(60 MIL)

USB20_P5

USB20_N5

@

JLVDS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_88341-3001 ME@

2

G1 G2 G3 G4

C541

4.7U_0805_25V6-K

31 32 33 34

R813

R813 0_0805_5%

0_0805_5%

B++LEDVDD

A A

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

LVDS/CAMERA

LA-7984P

1

of

33 60Tuesday, December 06, 2011

0.1

A

B

+5VS +5VS +5VS

3

2

1

@

D5

D5 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

3

2

1

@

D6

D6 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

C

3

2

REDGREENBLUE

1

@

D7

D7 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

D

E

1 1

+5VS

RB491D_SC59-3

FCM1608CF-121T03 0603

1

2

10P_0402_50V8J

CRT_HSYNC_1

CRT_VSYNC_1

C524

1 2

L30

FCM1608CF-121T03 0603

1 2

L31

FCM1608CF-121T03 0603

1 2

L32

1

2

FCM1608CF-121T03 0603

1

C525

2

10P_0402_50V8J

1 2

L33

1 2

L34

1

C526

2

10P_0402_50V8J

DAC_RED<17>

DAC_GRN<17>

DAC_BLU<17>

2 2

3 3

12

R445

R445 150_0402_1%

150_0402_1%

CRT_HSYNC<17>

CRT_VSYNC<17>

12

R443

R443 150_0402_1%

150_0402_1%

CLOSE TO CONN

C529

0.1U_0402_16V4Z

C531

0.1U_0402_16V4Z

12

R446

R446 150_0402_1%

150_0402_1%

+CRT_VCC

1

2

+CRT_VCC

1

2

1

C522

2

10P_0402_50V8J

R448

1 2

1K_0402_5%

1

5

P

4

OE#

A2Y

G

U23

U23 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

R451

1 2

1K_0402_5%

1

5

P

4

OE#

A2Y

G

U24

U24 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

C523

10P_0402_50V8J

RED

GREEN

BLUE

1

C527

2

10P_0402_50V8J

1

@

C530

C530 10P_0402_50V8J

10P_0402_50V8J

2

1

C532

@C532

@

10P_0402_50V8J

2

T66PAD T66PAD

JVGA_HS

JVGA_VS

RB491D_SC59-3

NC11 RED

CRT_DDC_DAT_CONN GREEN

JVGA_HS BLUE

JVGA_VS

CRT_DDC_CLK_CONN

+CRT_VCC

D10

2 1

100P_0402_50V8J

JVGA_VS

CRT_DDC_CLK_CONN

CRT Connector

F1

21

1.1A_6V_SMD1812P110TF

W=40mils

11

12

13

14 10

15

1

C528

2

D8

@

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23-6

VDD

+CRT_VCC_F

1

C521

0.1U_0402_16V4Z

2

CONTE_80431-5K1-152

CONTE_80431-5K1-152 JCRT1

ME@

JCRT1

ME@

6 1

7 2

8

16

G

17

G

3 9

4

5

6

I/O4

5

CRT_DDC_DAT_CONN

4

I/O3

R02

12

R436

0_0603_5%

12

0_0402_5%

R437

EMI Request

JVGA_HS

+5VS

12

R434

0_0402_5%

R432

0_0402_5%

12

R456

2.2K_0402_5%

3

100P_0402_50V8J

+CRT_VCC

12

@

C533

12

R457

2.2K_0402_5%

CRT_DDC_DAT_CONN

CRT_DDC_CLK_CONN

1

@

C534

C534 68P_0402_50V8K

68P_0402_50V8K

2

Compal Secret Data

C

Compal Secret Data

Deciphered Date

2011/06/15 2012/07/11

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

Custom

LA-7984P

0.1

34 60Tuesday, December 06, 2011

of

E

of

+3VS

Pull high at chipset/VGA side

CRT_DDC_DATA<17>

CRT_DDC_CLK<17>

4 4

A

2N7002DW-T/R7_SOT363-6

B

5

4

2

Q62B

61

Q62A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

1

+5VS

R488

R488 20K_0402_5%

20K_0402_5%

HDMI@

1 2

+5VS

3

2

D14

@D14

@

BAT54S-7-F_SOT23-3

1

HDMI_CLK-_CK HDMI_CLK+_CK

HDMI_TX0-_CK HDMI_TX0+_CK

HDMI_TX1-_CK HDMI_TX1+_CK

HDMI_TX2-_CK HDMI_TX2+_CK

R465 0_0402_5%@R465 0_0402_5%@ R464 0_0402_5%@R464 0_0402_5%@

R467 0_0402_5%@R467 0_0402_5%@ R466 0_0402_5%@R466 0_0402_5%@

R469 0_0402_5%@R469 0_0402_5%@ R468 0_0402_5%@R468 0_0402_5%@

R471 0_0402_5%@R471 0_0402_5%@ R470 0_0402_5%@R470 0_0402_5%@

+3VS

D D

TMDS_B_HPD#<17>

C C

HDMI@ R783

HDMI@

R783

0_0402_5%

+3VS

1 2

R485

1M_0402_5%

HDMI@

TMDS_B_HPD#

1 2

Q93

HDMI@

G

2

2N7002H_SOT23-3

S

13

D

HDMI_CLK-_CK<17> HDMI_CLK+_CK<17>

HDMI_TX0-_CK<17>

HDMI_TX0+_CK<17> HDMI_TX1-_CK<17>

HDMI_TX1+_CK<17> HDMI_TX2-_CK<17>

HDMI_TX2+_CK<17>

1 2 1 2

RB491D_SC59-3

RB491D_SC59-3 D13

HDMI@D13

HDMI@

2 1

R482

0_0805_5%

R483

HDMI@ R483

HDMI@

2.2K_0402_5%

@R482

@

+HDMI_5V

1 2

Pull up R for PCH OR VGA SIDE

Q63A

HDMI@

2

2N7002DW-T/R7_SOT363-6

HDMICLK_R

HDMICLK_NB<17>

B B

A A

HDMIDAT_NB<17>

5

4

3

Q63B

HDMI@

2N7002DW-T/R7_SOT363-6

HDMIDAT_R

HDMICLK_R

2

3

1

61

HDMIDAT_R

@

D11

@D11

PJDLC05_SOT23-3

HDMI_CLK+_CK

HDMI_CLK-_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_TX1+_CK

HDMI_TX1-_CK

HDMI_TX2+_CK

HDMI_TX2-_CK

L35

1

4

WCM-2012-900T_4P

WCM-2012-900T_4P L36

1

4

WCM-2012-900T_4P

WCM-2012-900T_4P L37

1

4

WCM-2012-900T_4P

WCM-2012-900T_4P L38

1

4

WCM-2012-900T_4P

HDMI@L35

HDMI@

HDMI@L36

HDMI@

HDMI@L37

HDMI@

HDMI@L38

HDMI@

HDMI_CLK+_CONN

2

C982 0.1U_0402_16V4Z @C982 0.1U_0402_16V4Z @

1 2

HDMI_CLK-_CONN

3

C983 0.1U_0402_16V4Z @C983 0.1U_0402_16V4Z @

1 2

HDMI_TX0+_CONN

2

C984 0.1U_0402_16V4Z @C984 0.1U_0402_16V4Z @

1 2

HDMI_TX0-_CONN

3

C985 0.1U_0402_16V4Z @C985 0.1U_0402_16V4Z @

1 2

HDMI_TX1+_CONN

2

C986 0.1U_0402_16V4Z @C986 0.1U_0402_16V4Z @

1 2

HDMI_TX1-_CONN

3

C987 0.1U_0402_16V4Z @C987 0.1U_0402_16V4Z @

1 2

HDMI_TX2+_CONN

2

C988 0.1U_0402_16V4Z @C988 0.1U_0402_16V4Z @

1 2

HDMI_TX2-_CONN

3

C989 0.1U_0402_16V4Z @C989 0.1U_0402_16V4Z @

1 2

HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN

HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN

680 +-5% 8P4R

45 36 27 18

RP5

HDMI@RP5

HDMI@

680 +-5% 8P4R

45 36 27 18

RP6

HDMI@RP6

HDMI@

W=40mils

F2

1.1A_6VDC_FUSE

R484

HDMI@R484

HDMI@

2.2K_0402_5%

1 2

HDMI_DET

+5VS_HDMI

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CONN HDMI_CLK+_CONN

HDMI_TX0-_CONN HDMI_TX0+_CONN

HDMI_TX1-_CONN HDMI_TX1+_CONN

HDMI_TX2-_CONN HDMI_TX2+_CONN

13

D

S

HDMI@F2

HDMI@

0.1U_0402_16V4Z

SD309680080 S ROW RES 1/16W 680 +-5% 8P4R

2

G

Q95

HDMI@

2N7002H_SOT23-3

+5VS_HDMI

21

C543

HDMI@

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042GR019M23DZL

+3VS

1

2

ME@JHDMI1

ME@

20

G1

21

G2

22

G3

23

G4

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

HDMI CONN

LA-7984P

0.1

of

35 60Tuesday, December 06, 2011

1

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half)

1 1

+3VALW

+3VS_WLAN+3VS

80mil

J6

@

Mini-Express Card(WLAN/WiMAX)

JWLN1

PCH_BT_ON#<19,40>

R02

BT_DISABLE<19>

2 2

3 3

@

1 2

R892 0_0402_5%

1 2

R897 0_0402_5%R897 0_0402_5%

PCIE_WAKE#<16,37,45>

BT_ACTIVE<40>

CLKREQ_WLAN#<15>

CLK_PCIE_WLAN1#<15>

CLK_PCIE_WLAN1<15>

PCIE_PRX_DTX_N2<15> PCIE_PRX_DTX_P2<15>

PCIE_PTX_C_DRX_N2<15> PCIE_PTX_C_DRX_P2<15>

EC_TX<42,43> EC_RX<42,43>

PCIE_WAKE# BT_ACTIVE BT_DISABLE_R

For EC to detect debug card insert.

R514 0_0402_5%R514 0_0402_5%

1 2

R497 0_0402_5%@R497 0_0402_5%@

1 2

PCI_RST#_R CLK_PCI_DB

+3VS_WLAN

100_0402_1%

R505

1 2 1 2

R506

100_0402_1%

R507

R507 100K_0402_5%

100K_0402_5%

1 2

JWLN1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

NC

53

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

ME@

3.3V

GND

1.5V

GND

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

SMB_DATA

GND

USB_D-

USB_D+

GND

LED_WWAN#

LED_WLAN#

LED_WPAN#

+1.5V

GND

+3.3V

GND

NC NC NC NC NC

NC

@

112

JUMP_43X79

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

2

+1.5VS_CONN

R503 0_0402_5%@R503 0_0402_5%@ R504 0_0402_5%@R504 0_0402_5%@

+1.5VS

R498 0_0402_5%@ R498 0_0402_5%@

1 2

R499 0_0402_5%@R499 0_0402_5%@

1 2

R500 0_0402_5%@ R500 0_0402_5%@

1 2

R501 0_0402_5%@R501 0_0402_5%@

1 2

R502 0_0402_5%@R502 0_0402_5%@

1 2

12 12

R02

C548

4.7U_0603_6.3V6K

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R

USB20_N10 <18> USB20_P10 <18>

WLAN_LED#

1

C547

@C548

@

0.1U_0402_16V4Z

2

PCH_WL_OFF# <18>

PLT_RST# <18,23,37,42,45> +3VALW +3VS

SMB_CLK_S3 <12,13,15> SMB_DATA_S3 <12,13,15>

NC

1

C544

0.1U_0402_16V4Z

2

+1.5VS_CONN+3VS_WLAN

1

C545

@C545

@

0.1U_0402_16V4Z

2

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

4 4

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

R508 0_0402_5%@R508 0_0402_5%@

1 2

R509 0_0402_5%@R509 0_0402_5%@

1 2

R510 0_0402_5%@R510 0_0402_5%@

1 2

R511 0_0402_5%@R511 0_0402_5%@

1 2

R512 0_0402_5%@R512 0_0402_5%@

1 2

R513 0_0402_5%@R513 0_0402_5%@

1 2

2011/06/15 2012/07/11

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

C

LPC_FRAME# <14,42> LPC_AD3 <14,42> LPC_AD2 <14,42> LPC_AD1 <14,42> LPC_AD0 <14,42>

CLK_PCI_DB <18>

Compal Secret Data

Deciphered Date

PLT_RST#

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Mini-Card/NEW Card/SIM

LA-7984P

36 60Tuesday, December 06, 2011

E

0.1

of

5

4

3

2

1

D D

U42

8105@U42

8105@

RTL8105E-VL-CGT

U41

22

HSOP

23

HSON

17

HSIP

18

HSIN

16

CLKREQB

25

PERSTB

19

REFCLK_P

20

REFCLK_N

43

CKXTAL1

44

CKXTAL2

28

LANWAKEB

26

ISOLATEB

14

NC/SMBCLK

15

NC/SMBDATA

38

GPO/SMBALERT

33

ENSWREG

34

VDDREG

35

VDDREG

46

RSET

24

GND

49

PGND

RTL8111F-CGT_QFN48_6x6

GIGA@

SA00004Y700

Y6

4

NC

OSC

1

OSC

25MHZ_20PF_FSX3M-25.M20FDO

1

C968

2

27P_0402_50V8J

NC

R02

LED3/EEDO

LED1/EESK

NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3

DVDD10 DVDD10 DVDD10

DVDD33 DVDD33

AVDD33 AVDD33 AVDD33 AVDD33

EVDD10 AVDD10

AVDD10 AVDD10 AVDD10

REGOUT

3 2

LED0

EECS

EEDI

MDIP0 MDIN0 MDIP1 MDIN1

LAN_XTALI

LAN_XTALO

1

C969

2

31

LAN_LINK#

37

LAN_ACTIVITY#

40

R571 10K_0402_5%

@

R571 10K_0402_5%

30 32

1 2 4 5 7 8 10 11

13 29 41

27 39

12 42 47 48

21 3

6 9 45

36

27P_0402_50V8J

@

R573 10K_0402_5%

@

MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3-

+LAN_VDD10

+3V_LAN

+LAN_EVDD10 +LAN_VDD10

+LAN_REGOUT

12 12

LAN_LINK# 38 LAN_ACTIVITY# 38

MDI0+ 38 MDI0- 38 MDI1+ 38 MDI1- 38 MDI2+ 38 MDI2- 38 MDI3+ 38 MDI3- 38

R569 10K_0402_5%

R569 10K_0402_5% R577 1K_0402_5%

R577 1K_0402_5%

1 2

+LAN_VDDREG

PCIE_PRX_C_DTX_P1 PCIE_PRX_C_DTX_N1

LAN_XTALI LAN_XTALO

PCIE_WAKE#_R

ISOLATEB

12

ENSWREG

1 2

R575 2.49K_0402_1%R575 2.49K_0402_1%

C947 0.1U_0402_16V7KC947 0.1U_0402_16V7K

PCIE_PRX_DTX_P115 PCIE_PRX_DTX_N115

PCIE_PTX_C_DRX_P115

PCIE_PTX_C_DRX_N115

CLKREQ_LAN#15

PLT_RST#18,23,36,42,45

CLK_PCIE_LAN15

C C

B B

CLK_PCIE_LAN#15

Pin 16 and Pin 28 are OD pins

LAN_WAKE#42 PCIE_WAKE#16,36,45

11/15 Realtek suggest to reserve R569,R577,R571,R573 to follow their reference design.

1 2

C946 0.1U_0402_16V7KC946 0.1U_0402_16V7K

1 2

R1370 0_0402_5%R1370 0_0402_5%

1 2

R1369@0_0402_5%R1369@0_0402_5%

1 2

@

@ @

+3V_LAN

@

+LAN_REGOUT

Layout Note: L39 must be within 200mil to Pin36, C700,C738 must be within 200mil to LL1 +LAN_REGOUT: Width =60mil

+LAN_VDD10

R576

1K_0402_1%

R578

15K_0402_5%

L39

1 2

2.2UH +-5% NLC252018T-2R2J-N

4.7U_0603_6.3V6K

X5R

12

L480_0603_5% L480_0603_5%

C732

1U_0402_6.3V4Z

Close to Pin 21

12

L400_0603_5% L400_0603_5%

C711

4.7U_0603_6.3V6K

X5R

+3VS

12

C700

+LAN_EVDD10

12

ENSWREGISOLATEB

H: Enable internal Regular L: Disable

12

C695

0.1U_0402_16V4Z

1 2

+LAN_VDDREG+3V_LAN

1 2

+LAN_VDD10

C738

0.1U_0402_16V4Z

1 2

C708

0.1U_0402_16V4Z

+3V_LAN

R572

R572 0_0402_5%

0_0402_5%

R574

R574 0_0402_5%

0_0402_5%

@

Layout Notice : Place as close chip as possible.

+3VALW

J3

112

JUMP_43X79

@

+3V_LAN

2

Rising time (10%~90%)1mS <Rising time <100mS

Close to Pin 12,27,39,42,47,48

+3V_LAN

1 2

C7450.1U_0402_16V4Z C7450.1U_0402_16V4Z

1 2

C7010.1U_0402_16V4Z C7010.1U_0402_16V4Z

1 2

C7420.1U_0402_16V4Z C7420.1U_0402_16V4Z

1 2

GIGA@

GIGA@ GIGA@

GIGA@

Close to Pin 3,6,9,13,29,41,45

GIGA@

GIGA@ GIGA@

GIGA@

1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

C6990.1U_0402_16V4Z

C6990.1U_0402_16V4Z C7310.1U_0402_16V4Z

C7310.1U_0402_16V4Z C7060.1U_0402_16V4Z

C7060.1U_0402_16V4Z

+LAN_VDD10

C7370.1U_0402_16V4Z C7370.1U_0402_16V4Z C7050.1U_0402_16V4Z C7050.1U_0402_16V4Z C6940.1U_0402_16V4Z C6940.1U_0402_16V4Z C7430.1U_0402_16V4Z

C7430.1U_0402_16V4Z C7410.1U_0402_16V4Z

C7410.1U_0402_16V4Z C7390.1U_0402_16V4Z

C7390.1U_0402_16V4Z C7400.1U_0402_16V4Z

C7400.1U_0402_16V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

LAN-RTL8111F/8105E

LA-7984P

Tuesday, December 06, 2011

LA-7984P

1

of

37 60

0.1

5

MDI3+

MDI3-

9

GND

5

10

6677889

10

RCLAMP3304N.TCT_SLP2626P10-10

112233445

D69

@

MDI2-

MDI2+

D D

11

Place Close to T2

MDI1+

C C

11

Place Close to T1

B B

6677889

GND

5

9

10

RCLAMP3304N.TCT_SLP2626P10-10

112233445

D68

@

MDI0MDI0+

LAN_ACTIVITY#37

4

1

C975

0.01U_0402_16V7K

2

3

T2

MDI3+37 MDI3-37

MDI2+37 MDI2-37

MDI3+ MDI3-

MDI2+ MDI2-

MDI0+37 MDI0-37

MDI1+37 MDI1-37

MDI0+ MDI0-

MDI1+ MDI1-

1

TD+

2 3 4 5 6 7

1 2 3 4 5 6 7

TX+

TD-

TX-

CT

NC

CT

RD+

RX+

RD-8RX-

BOTHHAND_NS0013LF

GIGA@

R02

T1

TD+

TX+

TD-

TX-

CT

NC

CT

RD+

RX+

RD-8RX-

BOTHHAND_NS0013LF

2

MDO3+

16

MDO3-

15

MCT3

14 13 12

MCT2

11

MDO2+

10

MDO2-

9

MDO0+

16

MDO0-MDI1-

15

MCT0

14 13 12

MCT1

11

MDO1+

10

MDO1-

9

R1374

1 2

75_0603_5%GIGA@

1 2

R1375 75_0603_5%

GIGA@

R1376

1 2

75_0603_5%

R1377

1 2

75_0603_5%

1

1 2

C973

1000P_1206_2KV7K

Reserve gas tube for EMI go rural solution

Place Close to T1,T2

JRJ1

LAN_LINK#37

LAN_LINK#

LAN_ACTIVITY#

R1449 510_0402_5%R1449 510_0402_5%

12

C978

@C978

@

470P_0402_50V7K

1

2

Overclocking mode stick

R1448 510_0402_5%R1448 510_0402_5%

12

@

C979

470P_0402_50V7K

1

2

+3V_LAN

MDO0+

MDO0MDO1+ MDO2+

MDO2-

MDO1MDO3+

MDO3-

+3V_LAN

JRJ1

9

Green LED-

10

Green LED+

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

11

Yellow LED-

12

Yellow LED+

SANTA_130452-D ME@

MCT3 MCT2 MCT1 MCT0

DL2

DL1

@

14

G2

13

G1

@

DL2

@

1 2

LSE-200NX3216TRLF_1206-2

DL3

@

1 2

LSE-200NX3216TRLF_1206-2

DL4

@

1 2

LSE-200NX3216TRLF_1206-2

1 2

LSE-200NX3216TRLF_1206-2

Reserve for EMI go rural solution

A A

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

LAN_Transformer

LA-7984P

1

0.1

of

38 60Tuesday, December 06, 2011

5

4

3

2

1

SMSC thermal sensor placed near by VRAM

D D

C C

Close U27

C587

2200P_0402_50V7K

C588

@C588

2200P_0402_50V7K

@

1

2

1

2

REMOTE1+

REMOTE1-

REMOTE2+

REMOTE2-

C590

0.1U_0402_16V4Z

+3VS

U27

1

REMOTE1+

2

REMOTE1REMOTE2+

1

REMOTE2-

VDD

2

DP1

3

DN1

4

DP2

5

DN2

EMC1403-2-AIZL-TR_MSOP10

SMCLK

SMDATA

ALERT#

THERM#

GND

Address 1001_101xb

+3VS

12

R540

R540 10K_0402_5%

10K_0402_5%

@

10 9 8 7 6

EC_SMB_CK2 EC_SMB_DA2

EC_SMB_CK2 <15,23,42> EC_SMB_DA2 <15,23,42>

REMOTE1+

C586

@ C586

@

100P_0402_50V8J

REMOTE1-

REMOTE2+

C589

@ C589

@

100P_0402_50V8J

REMOTE2-

REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8"

Close to DDR

1

C

2

B

2

E

3 1

1

C

2

B

2

E

3 1

Q97

Q97 MMST3904-7-F_SOT323-3

MMST3904-7-F_SOT323-3

Under WWAN

Q98

@

Q98

@

MMST3904-7-F_SOT323-3

H1

H1 HOLEA

HOLEA

1

H_3P8

H2

H2 HOLEA

HOLEA

1

H_3P8

H3

H3 HOLEA

HOLEA

1

H_3P8

VGA_L VGA_RCPU

H4

H4 HOLEA

HOLEA

1

H_3P3

H5

H5 HOLEA

HOLEA

1

H_3P3

FD1FD1

FD2FD2

FD3FD3

FD4FD4

1

BA

B B

+5VS

R581

12

0_0603_5%

2

C591

C591 10U_0603_6.3V6M

10U_0603_6.3V6M

1

10U

A A

5

EC_TACH<42>

EC_FAN_PWM<42>

FAN1 Conn

JFAN1

1

2

3

4

5

G5

6

G6

ACES_85205-04001

ME@

4

M/B

H13

H6

H6 HOLEA

HOLEA

1

H_2P8

H7

H7 HOLEA

HOLEA

1

H_2P8

H8

H8 HOLEA

HOLEA

1

H_2P8

H9

H9 HOLEA

HOLEA

1

H_2P8

H10

H10 HOLEA

HOLEA

1

H_2P8

H11

H11 HOLEA

HOLEA

1

H_2P8

H12

H12 HOLEA

HOLEA

1

H_2P8

H13 HOLEA

HOLEA

1

H_2P8

H14

H14 HOLEA

HOLEA

1

H_2P8

D

2P8 * 9 pcd

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

2

橢圓孔

LR

H16

H15

HOLEA

1

H_3P0X4P0N

E

Title

Size Document Number Rev

B

Date: Sheet

M/B

圓孔

H17

H17 HOLEA

HOLEA

1

H_3P0N

Compal Electronics,Ltd.

Fintek-Thermal IC/FAN/screw

LA-7984P

1

0.1

of

39 60Tuesday, December 06, 2011

A

1 1

PCH_BT_ON#<19,36>

B

BT MODULE CONN

+3VALW

1

C710

@C710

@

0.1U_0402_16V4Z

BT@R632

BT@

2

C709

0.1U_0402_16V4Z

1 2

+3VS

USB20_P13<18> USB20_N13<18>

BT_ACTIVE<36>

BT@C709

BT@

S

R632 100K_0402_5%

100K_0402_5%

1 2

R02

R583

R583 0_0603_5%

0_0603_5%

D

13

G

Q104

2

PMV65XP_SOT23-3~D

USB20_P13 USB20_N13

BT_ACTIVE

C

+3VS_BT

12

BTON_LED:NC

30mils

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z C712

C712

BT@

2

JBT1

1

2

3

4

5

G1

6

G2

ACES_87213-0600G

ME@

D

E

F

G

H

SATA HDD Conn.

JHDD1

1

SATA_ITX_DRX_P0<14> SATA_ITX_DRX_N0<14>

C596 0.01U_0402_16V7KC596 0.01U_0402_16V7K

SATA_DTX_C_IRX_N0<14> SATA_DTX_C_IRX_P0<14>

+5V_HDD +3VS

R02

1

C598

C598 1000P_0402_50V7K

7 8

1000P_0402_50V7K

2

SATA_DTX_C_IRX_P0

1

C599

0.1U_0402_16V4Z

2

1

C600 1U_0603_10V4Z

1U_0603_10V4Z

2

1 2

C597 0.01U_0402_16V7KC597 0.01U_0402_16V7K

1 2

+5VS

R02

@C600

@

10U

1

2

SATA_ITX_DRX_P0 SATA_ITX_DRX_N0

SATA_DTX_IRX_N0SATA_DTX_C_IRX_N0 SATA_DTX_IRX_P0

R550

1 2

0_0805_5%

C602

C602 10U_0603_6.3V6M

10U_0603_6.3V6M

+3VS

+5V_HDD

1

@

C603

0.1U_0402_16V4Z

2

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18

Reserved

19

GND

20

12V

21 22

SUYIN_127043FB022G278ZR

GND

12V

GND

12V

23 24

2 2

+5VS

+5VALW

12

R568

@ R568

@

10K_0402_5%

ODD_EN<19>

3 3

2

R552 10K_0402_5%

10K_0402_5%

1

OUT

IN

GND

3

ODD Power Control

@R552

@

R675

@R675

@

100K_0402_5%

1 2

Q100

@Q100

@

DTC124EKAT146_SC59-3

J9

@ J9

@

112

JUMP_43X79

S

G

2

1

2

D

13

Q99

@

Q99

@

PMV65XP_SOT23-3~D

C607

@C607

@

0.01U_0402_16V7K

+5V_ODD

1

2

10U

1

C604

0.1U_0402_16V4Z

2

C608

C608 10U_0603_6.3V6M

10U_0603_6.3V6M

FOR 15"

SATA ODD FFC Conn.

JP2

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_87056-01001-001

ME@

1 2

R710 0_0402_5%@R710 0_0402_5%@

1 2

R554 0_0402_5%R554 0_0402_5%

SATA_ITX_DRX_P2_15 SATA_ITX_DRX_N2_15

SATA_DTX_IRX_N2_15

ODD_DETECT# +5V_ODD

R02

SATA_ITX_C_DRX_P2<14> SATA_ITX_C_DRX_N2<14>

SATA_DTX_C_IRX_N2<14>

SATA_DTX_C_IRX_P2<14>

SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_N2

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_DTX_IRX_P2_15

C605 0.01U_0402_16V7K15@C605 0.01U_0402_16V7K15@

1 2

C606 0.01U_0402_16V7K15@C606 0.01U_0402_16V7K15@

1 2

C618 0.01U_0402_16V7K15@C618 0.01U_0402_16V7K15@

1 2

C617 0.01U_0402_16V7K15@C617 0.01U_0402_16V7K15@

1 2

ODD_DA#<18,42>

ODD_DA# R_ODD_DA#

R555

1 2

+3VS

10K_0402_5%

Co-lay

FOR 14"

SATA ODD Conn.

JODD1

ME@JODD1

C616 0.01U_0402_16V7K14@C616 0.01U_0402_16V7K14@

1 2

SATA_ITX_C_DRX_N2 SATA_DTX_C_IRX_N2

SATA_DTX_C_IRX_P2 SATA_DTX_IRX_P2_14

4 4

C615 0.01U_0402_16V7K14@C615 0.01U_0402_16V7K14@

1 2

C614 0.01U_0402_16V7K14@C614 0.01U_0402_16V7K14@

1 2

C613 0.01U_0402_16V7K14@C613 0.01U_0402_16V7K14@

1 2

SATA_ITX_DRX_P2_14SATA_ITX_C_DRX_P2 SATA_ITX_DRX_N2_14

SATA_DTX_IRX_N2_14

ODD_DETECT# +5V_ODD

R_ODD_DA#

R02

1 2 3 4 5 6 7

8

9 10 11 12 13

ME@

GND RX+ RXGND TXTX+ GND

DP +5V +5V MD

GND1

GND

GND2

GND

TYCO_2-1759838-8~D

14 15

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

D

Compal Secret Data

Deciphered Date

E

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

F

Date: Sheet

Compal Electronics, Inc.

HDD/ODD/BT Connector

LA-7984P

G

40 60Tuesday, December 06, 2011

H

0.1

of

5

CX20671 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO).

An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).

D D

+3VS

1

C583

C582

2

4.7U_0603_6.3V6K

R527 0_0402_5%R527 0_0402_5%

+3VS

+3VALW

C C

1 2

R528 0_0402_5%@R528 0_0402_5%@

1 2

HDA_RST_AUDIO#<14>

HDA_SYNC_AUDIO<14>

HDA_SDIN0<14>

HDA_SDOUT_AUDIO<14>

HDA_BITCLK_AUDIO<14>

CX_GPIO0<43>

EAPD<42>

EC_MUTE#<42>

EAPD active low 0=power down ex AMP 1=power up ex AMP

4.7U_0603_6.3V6K

1

C593

C623

2

1U_0603_10V4Z

@

R495 33_0402_5%R495 33_0402_5%

1 2

Internal SPEAKER

Short GND and GNDA on

B B

GND1 & GND2 on layout

R516

@R516

@

1 2

0_0402_5%

GND GNDA

PC Beep

EC Beep

ICH Beep

A A

BEEP#<42>

HDA_SPKR<14>

5

1 2

C619 0.1U_0402_16V4ZC619 0.1U_0402_16V4Z

PC_BEEP1 PC_BEEP

1 2

C612 0.1U_0402_16V4ZC612 0.1U_0402_16V4Z

1 2

33_0402_5%

12

@

R480

R480 10K_0402_5%

10K_0402_5%

R492

C579

0.1U_0402_16V4Z

1 2

4

1

C580

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

1

C626

2

10U_0603_6.3V6M

HDA_RST_AUDIO# HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO HDA_SDOUT_AUDIO

PC_BEEP

R5190_0402_5% @ R5190_0402_5% @

12

R4960_0402_5% R4960_0402_5%

SPK_L2+ SPK_L1-

SPK_R2+ SPK_R1-

MIC1

WM-64PCY_2P

45@

4

1

C581

2

@

1

C634

2

@

CX_GPIO0

1 2

0.1U_0402_16V4Z

10 mils

0.1U_0402_16V4Z

10

38 37

40

11 13

16 14

GNDA

1

C585

C584

2

1U_0603_10V4Z

0.1U_0402_16V4Z

7

18

2

3

41

GND

VDD_IO

FILT_1.8

29

VAUX_3.3

DVDD_3.3

CX20671-21Z_QFN40_6X6

U25

9

RESET#

5

BIT_CLK

8

SYNC

6

SDATA_IN

4

SDATA_OUT

PC_BEEP

GPIO0/EAPD# GPIO1/SPK_MUTE#

DMIC_CLK

1

DMIC_1/2

LEFT+ LEFT-

RIGHT+ RIGHT-

Place colose to Codec chip

+MICBIASC

12

R518

2.2K_0402_5%

C633 2.2U_0603_6.3V4ZC633 2.2U_0603_6.3V4Z

1

2

C640

C636

0.1U_0402_16V4Z

@

27

FILT_1.65

AVDD_3.3

1 2

1

C625

2

26

28

AVDD_5V

AVDD_HP CLASS-D_REF

C592

4.7U_0603_6.3V6K

C638

LPWR_5.0

RPWR_5.0

SENSE_A

PORTB_R

PORTB_L

B_BIAS

C_BIAS

PORTC_R

PORTC_L

PORTA_R

PORTA_L

AVEE FLY_P FLY_N

1

2

@

NC NC NC

AVDD_3.3 pinis output of internal LDO. NOT connect to external supply.

0.1U_0402_16V4Z

1

C631

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

12 15 17

SENSE_A

36

35 34 33

32 31 30

23 22

24 25 39

21 19 20

1 2

C635 1U_0603_10V4ZC635 1U_0603_10V4Z

wide 30MIL

MIC_INR MIC_INL

+MICBIASB

+MICBIASC

3

+LDO_OUT_3.3V

+5VS

1

C620

2

3

Layout Note:Path from +5VS to LPWR_5.0 RPWR_5.0 must be very low resistance (<0.01 ohms)

1

C632

2

C594

2

0.1U_0402_16V4Z

1

C595

@

2

0.1U_0402_16V4Z

Please bypass caps very close to device.

0.1U_0402_16V4Z

R526 0_0402_5%@R526 0_0402_5%@

1 2

C629

@

SPK_R1SPK_R2+ SPK_L1SPK_L2+

2.2U_0603_6.3V4Z

C621

1 2

C622

1 2

2.2U_0603_6.3V4Z

MIC_INR

MIC_INL

Internal MIC

1

C609

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

L41 FBMA-L11-160808-121LMT_0603L41 FBMA-L11-160808-121LMT_0603

1 2

L42 FBMA-L11-160808-121LMT_0603L42 FBMA-L11-160808-121LMT_0603

1 2

L43 FBMA-L11-160808-121LMT_0603L43 FBMA-L11-160808-121LMT_0603

1 2

L46 FBMA-L11-160808-121LMT_0603L46 FBMA-L11-160808-121LMT_0603

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C628

2

4.7U_0603_6.3V6K

R481 15_0402_5%

R481 15_0402_5% R493 15_0402_5%

R493 15_0402_5%

Changed from 5.1ohm to 15ohm for "zi zi"noise.

MIC_JD

Q75

LBSS138LT1G_SOT-23-3

PLUG_IN_R

2

HDA_RST_AUDIO# HDA_SYNC_AUDIO

R517 100_0402_1%R517 100_0402_1%

1 2 1 2

+5VS

SENSE_A

EXT_MIC

1

C575

2

@

22P_0402_50V8J

R458 5.11K_0402_1%R458 5.11K_0402_1%

1 2

R491 20K_0402_1%R491 20K_0402_1%

1 2

R494 39.2K_0402_1%R494 39.2K_0402_1%

1 2

R490 2K_0402_5%R490 2K_0402_5%

12

R490 & R700 for App & Nokia combo ear phone un-pop

EXT_MIC <43>

HP_OUTR <43>

Headphone

HP_OUTL <43>

1

C576

2

@

22P_0402_50V8J

+MICBIASB

External MIC

HDA_SDOUT_AUDIO

1

C578

C577

2

@

22P_0402_50V8J

R700 4.7K_0402_5%R700 4.7K_0402_5%

R515

1 2

0_0402_5%

@

+3VS

MIC_JD PLUG_IN_R

12

HDA_BITCLK_AUDIO

Sense resistors must be connected same power that is used for VAUX_3.3

Combo Jack detect (normal close)

13

D

2

G

S

CX_GPIO0

SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN

R02

C610

2011/06/15 2012/07/11

33K_0402_5%

R693

1 2

12

C787

C787 1U_0402_6.3V6K

1U_0402_6.3V6K

R182 47K_0402_5%

1 2

@

1

C630

@

0.1U_0402_16V4Z

2

close to Codec

1

C627

C624

2

220P_0402_50V7K

Compal Secret Data

Deciphered Date

2

EXT_MICEXT_MIC

1

C611

2

TVNST52302AB0 C/C SOT523

220P_0402_50V7K

+5VS

12

R724

R724 10K_0402_5%

10K_0402_5%

PLUG_IN<43>

D70

@ D70

@

R723

20K_0402_5%

2

3

2

3

D71

1

TVNST52302AB0 C/C SOT523

Title

Size Document Number Rev

Custom

Date: Sheet

1

EMI

Port B Port A

PLUG_IN_R

13

D

Q85

2

G

2N7002_SOT23

S

@D71

@

Compal Electronics, Inc.

CX20671 Codec

LA-7984P

1

R351

@R351

@

4.7K_0402_5%

HDA_RST_AUDIO#

C641

@C641

@

100P_0402_50V8J

ESD Reserve

JSPK1

ME@JSPK1

ME@

1

2

3

4

5

GND1

6

GND2

ACES_88231-04001

+3VS

12

1

2

0.1

41 60Tuesday, December 06, 2011

0.1

of

L44

FBM-11-160808-601-T_0603

+3VALW +EC_VCCA

+3VALW

+3VS

R601

2.2K_0402_5%

1

@

C665

C665 100P_0402_50V8J

100P_0402_50V8J

2

1 2

0.1U_0402_16V4Z

1 2

L45

FBM-11-160808-601-T_0603

12

C660 22P_0402_50V8J@C660 22P_0402_50V8J@

1 2

R590 47K_0402_5%R590 47K_0402_5%

0.1U_0402_16V4Z

KSO[0..15]<43>

KSI[0..7]<43>

R595 47K_0402_5%R595 47K_0402_5%

1 2

R597 47K_0402_5%R597 47K_0402_5%

1 2

R602

2.2K_0402_5%

EC_SMB_CK2 EC_SMB_DA2

1

@

C666

C666 100P_0402_50V8J

100P_0402_50V8J

2

+3VS

1 2

R120 10M_0402_5%

10M_0402_5%

1

2

check

@R120

@

OSC4OSC

NC3NC

EC_TACH

PCH_PWROK<16>

Y5

@

1 2

R605 10K_0402_5%R605 10K_0402_5%

18P_0402_50V8J

1

C347

@

2

C656

C661

KSO[0..15] KSI[0..7]

32.768KHZ_12.5PF_9H03200413

1

2

ECAGND

R589 10_0402_5%@R589 10_0402_5%@

2

1

KSO1 KSO2

+3VALW

1 2

R608

@ R608

@

10K_0402_5%

EC_RTCX1 SUSCLK_R

1

C367

@C367

@

18P_0402_50V8J

2

R600

R604

12

1

C659

C659 1000P_0402_50V7K

1000P_0402_50V7K

2

12

2.2K_0402_5%

SUSCLK<16>

EC_SMB_CK1

EC_SMB_DA1

EC_TX<36,43> EC_RX<36,43>

C653

0.1U_0402_16V4Z

C653

0.1U_0402_16V4Z

LPC_FRAME#<14,36>

CLK_PCI_EC<18>

PLT_RST#<18,23,36,37,45>

EC_SCI#<19> BATT_LEN#<48>

EC_SMB_CK1<48,49> EC_SMB_DA1<48,49> EC_SMB_CK2<15,23,39> EC_SMB_DA2<15,23,39>

PM_SLP_S3#<16> PM_SLP_S5#<16>

EC_SMI#<19>

CMOS_ON#<33>

ODD_DA#<18,40>

EC_INVT_PWM<33>

EC_TACH<39>

EC_FAN_PWM<39>

1

2

GATEA20<19>

KBRST#<19>

SERIRQ<14>

LPC_AD3<14,36> LPC_AD2<14,36> LPC_AD1<14,36> LPC_AD0<14,36>

KSO16<43> KSO17<43>

R611

0_0402_5%

C654

0.1U_0402_16V4Z

C654

0.1U_0402_16V4Z

100K_0402_5%

+3VLP

+3VALW

22

33

96

9

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

SM Bus

GPIO

GND/GND

24

35

11

ACES_50521-0084N-P01

RST

INT#

+3VALW

+EC_VCCA

111

67

125

EC_VDD0

EC_VDD/VCC

BEEP#/GPIO10

EC_VDD/AVCC

ACOFF/GPIO13

BATT_TEMP/GPIO38

AD Input

CPU1.5V_S3_GATE/GPXIOA00

GPIO

GND/GND

GND0

94

113

10

ADP_I/GPIO3A

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00

SPIDO/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

SYSON/GPIO56 VR_ON/GPIO57

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

BKOFF#/GPXIOA08

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

GPI

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

PECI_KB9012/GPXIOD07

AGND/AGND

69

KB9012QF A3 LQFP 128P_14X14

ECAGND

JCAP1

ME@JCAP1

ME@

1

2

3

4

5

6

7

8

9

GND1 GND2

GPIO0F GPIO12

GPIO39 GPIO3B

GPIO42

IMON/GPIO43

IREF/GPIO3E

SPIDI/GPIO5B

GPXIOD06

V18R

C662

0.1U_0402_16V4Z

C662

0.1U_0402_16V4Z

C655

0.1U_0402_16V4Z

C655

0.1U_0402_16V4Z

C657

1000P_0402_50V7K

C657

1000P_0402_50V7K

C658

1000P_0402_50V7K

C658

1

2

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMI# ESB_CLK

ESB_DAT ODD_DA# EC_INVT_PWM EC_TACH EC_PME# EC_TX EC_RX PCH_PWROK EC_FAN_PWM

1

2

LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMP LPC_AD0

EC_RST# EC_SCI# BATT_LEN#

NUM_LED#: NC

EC_RTCX1 SUSCLK_RSUSCLK_R

12

C93

R740

C93 20P_0402_50V8

20P_0402_50V8

1

2

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

1000P_0402_50V7K

1

2

LPC & MISC

Int. K/B

Int. K/B Matrix

Matrix

PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER

+3VS

EC_SMB_DA2 EC_SMB_CK2

+5VS

R03

Capsensor Board For best buy use

3.3V +/- 5%

Vcc

100K +/- 5%

R694

Board ID

U31

21

BEEP#

23

NOVO#

26

ACOFF

27

63

VGA_IMVP_IMON

64 65 66

BRDID BRDID

75 76

68 70 71 72

83

USB_ON#

84

INT#

85 86

TP_CLK

87

TP_DATA

88

CPU1.5V_S3_GATE

97

VGA_AC_DET

98 99

NTC_V_R

109

PCH_PWR_EN

119 120 126 128

73

RST

74 89

BATT_CHG_LED#

90

CAPS_LED#

91 92

BATT_LOW_LED#

93

SYSON

95 121 127

100

EC_LID_OUT#

101

Turbo_V

102

H_PROCHOT#_EC

103

MAINPWON

104

BKOFF#

105

PBTN_OUT#

106 107 108

ACIN

110

EC_ON

112 114

LID_SW#

115

SUSP#

116

PCH_HOT#_R

117

PECI_KB9012

118

+V18R

124

1

C667

4.7U_0805_10V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R758 0_0402_5%R758 0_0402_5%

R750 0_0402_5%R750 0_0402_5%

R792 0_0402_5%@R792 0_0402_5%@

1 2

R669 43_0402_1%R669 43_0402_1%

BEEP# <41> NOVO# <43> ACOFF <49>

12

ADP_I <48,49>

IMVP_IMON <55>

EC_MUTE#

12

CAPS_LED# <43> PWR_LED# <43>

BATT_LOW_LED# <43>

SYSON <45,46,51> VR_ON <55>

PM_SLP_S4# <16>

EC_RSMRST# <16> EC_LID_OUT# <19>

BKOFF# <33>

PBTN_OUT# <16>

PCH_APWROK <16> SA_PGOOD <52>

12

BATT_TEMP <48>

GPU_IMON <54>

EC_FAN_PWM

R593 10K_0402_5%R593 10K_0402_5%

1 2

EC_MUTE# <41> USB_ON# <44,45>

EAPD <41>

TP_CLK <43>

TP_DATA <43>

R757 0_0402_5%R757 0_0402_5%

2011/06/15 2012/07/11

0

8.2K +/- 5%

1

18K +/- 5%

2

33K +/- 5%

3

+3VS +3VALW

12

R588

R588 10K_0402_5%

10K_0402_5%

@

+3VALW

USB_ON#

CPU1.5V_S3_GATE <10>

VGA_AC_DET <23,54>

ME_FLASH <14>

NTC_V <48>

+3VLP

12

KB9012A2 work around

R4945 47K_0402_5%

47K_0402_5%

MAINPWON <48,50>

EMC Request

SYSON

@

0.1U_0402_10V6K

Deciphered Date

PCH_PWR_EN

C492

1

2

PCH_PWR_EN <46>

ENBKL <33>

BATT_CHG_LED# <43>

12

ACIN <16,49> EC_ON <43,50>

ON/OFF <43>

LID_SW# <43> SUSP# <10,25,46,51,52,53,54> PCH_HOT# <15>

H_PECI <6,19>

Compal Secret Data

0

R594

1 2

10K_0402_5%

@R4945

@

Turbo_V <48>

PROCHOT <48>

VR695

AD_BID

0 V

0.436 V

0.712 V

+5VALW

R599 100K_0402_1%@R599 100K_0402_1%@

EC_PME#

VR_HOT#<55>

12

min

+3VALW

typ

V

AD_BID

0.503 V

0.819 V

TP_CLK

R591 4.7K_0402_5%R591 4.7K_0402_5%

TP_DATA

R592 4.7K_0402_5%R592 4.7K_0402_5%

BATT_TEMP

C663 100P_0402_50V8JC663 100P_0402_50V8J

ACIN

C664 100P_0402_50V8JC664 100P_0402_50V8J

1 2

VR_HOT#

R737

1 2

0_0402_5%

H_PROCHOT#_EC

R606

10K_0402_5%

1 2

0_0402_5% @

Q102

2N7002_SOT23

Q37

2N7002H_SOT23-3

R609

12

0_0402_5%

R610

12

D

S

D

S

1 3

@

G

2

Title

Size Document Number Rev

Custom

Date: Sheet

max

V

AD_BID

0 V0 V

0.289 V0.250 V0.216 V

0.538 V

0.875 V

R694

R694 100K_0402_1%

100K_0402_1%

1 2

R695

R695 18K_0402_5%

18K_0402_5%

1 2

1 2 1 2

R522 4.7K_0402_5%@R522 4.7K_0402_5%@

2

G

+3VALW

Compal Electronics, Inc.

MP PVT DVT EVT

R02

+5VS

13

D

1

C493

2

PCI_PME# <18>

LA-7984P

C493 47P_0402_50V8J

47P_0402_50V8J

S

LAN_WAKE# <37>

BIOS & EC I/O Port

H_PROCHOT# <6,48>

42 60Tuesday, December 06, 2011

of

0.1

KSI[0..7] KSO[0..17]

KSO2 KSO1 KSO15 KSO6 KSO8 KSO13 KSO12 KSO11 KSO10 KSO3 KSO4 KSI0 KSO0

JP3

+3VALW EC_TX<36,42> EC_RX<36,42>

1

2

3

4

ACES_85205-0400

ME@

C668 100P_0402_50V8J@C668 100P_0402_50V8J@

1 2

C670 100P_0402_50V8J@C670 100P_0402_50V8J@

1 2

C672 100P_0402_50V8J@C672 100P_0402_50V8J@

1 2

C674 100P_0402_50V8J@C674 100P_0402_50V8J@

1 2

C676 100P_0402_50V8J@C676 100P_0402_50V8J@

1 2

C678 100P_0402_50V8J@C678 100P_0402_50V8J@

1 2

C680 100P_0402_50V8J@C680 100P_0402_50V8J@

1 2

C682 100P_0402_50V8J@C682 100P_0402_50V8J@

1 2

C684 100P_0402_50V8J@C684 100P_0402_50V8J@

1 2

C686 100P_0402_50V8J@C686 100P_0402_50V8J@

1 2

C688 100P_0402_50V8J@C688 100P_0402_50V8J@

1 2

C690 100P_0402_50V8J@C690 100P_0402_50V8J@

1 2

KSI[0..7] <42> KSO[0..17] <42>

KSO16 KSO17

KSO7 KSI2 KSO5 KSI3 KSO14 KSI7 KSI6 KSI5 KSI4 KSO9 KSI1

C693 100P_0402_50V8J@C693 100P_0402_50V8J@

1 2

C692 100P_0402_50V8J@C692 100P_0402_50V8J@

1 2

C669 100P_0402_50V8J@C669 100P_0402_50V8J@

1 2

C671 100P_0402_50V8J@C671 100P_0402_50V8J@

1 2

C673 100P_0402_50V8J@C673 100P_0402_50V8J@

1 2

C675 100P_0402_50V8J@C675 100P_0402_50V8J@

1 2

C677 100P_0402_50V8J@C677 100P_0402_50V8J@

1 2

C679 100P_0402_50V8J@C679 100P_0402_50V8J@

1 2

C681 100P_0402_50V8J@C681 100P_0402_50V8J@

1 2

C683 100P_0402_50V8J@C683 100P_0402_50V8J@

1 2

C685 100P_0402_50V8J@C685 100P_0402_50V8J@

1 2

C687 100P_0402_50V8J@C687 100P_0402_50V8J@

1 2

C689 100P_0402_50V8J@C689 100P_0402_50V8J@

1 2

C691 100P_0402_50V8J@C691 100P_0402_50V8J@

1 2

JKB1

ME@JKB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

GND

29

30

GND

30

ACES_88514-3001

ME@

JKB2

ME@JKB2

ME@

26

GND2

25

GND1

KSI1

24

KSI7

23

KSI6

22

KSO9

21

KSI4

20

KSI5

19

KSO0

18

KSI2

17

KSI3

16

KSO5

15

KSO1

14

KSI0

13

KSO2

12

KSO4

11

KSO7

10

KSO8

9

KSO6

8

KSO3

7

KSO12

6

KSO13

5

KSO14

4

KSO11

3

KSO10

2

KSO15

1 31 32

1

ACES_88514-2401

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16

KSO16<42>

KSO17

KSO17<42>

+5VS

+3VS

4 3

TP_CLK<42> TP_DATA<42>

5

EC_ON<42,50>

R889 0_0402_5%

nonBBH@

R890 0_0402_5%

BBH@

C697

@C697

@

100P_0402_50V8J

SW4

14@SW4

14@

SMT1-05_4P

6

2

SW_L

1

1 2

ON/OFFBTN#

12

1

C698 100P_0402_50V8J

100P_0402_50V8J

2

PSOT24C_SOT23-3

R621 0_0402_5%

0_0402_5%

R622 0_0402_5%

0_0402_5%

+3VLP

SW3SMT1-05_4P @SW3SMT1-05_4P @

3 4

5

6

J11

1 2

SHORT PADS

EC_ON

@C698

@

D15

@D15

@

15_nonBBH@R621

15_nonBBH@

TP_2

12

14@R622

14@

TP_3 TP_2

12

R720

1 2

0_0402_5%

1

D23

DAN202UT106_SC70-3

2N7002_SOT23-3

R639

@R639

@

10K_0402_5%

1 2

C696

0.1U_0402_16V4Z

2

3

1

4 3

@D23

@

Q106

5

3 2

6

R701

R701 100K_0402_5%

100K_0402_5%

1 2

2

G

@

R627

R627 0_0402_5%

0_0402_5% R619

0_0402_5%

SW5

14@SW5

14@

SMT1-05_4P

2 1

12

SW_R

13

D

S

15@

TP_3

TP_1

14@R619

14@

+3VALW

R624 0_0402_5%

0_0402_5%

R625 0_0402_5%

0_0402_5%

R535 100K_0402_5%

100K_0402_5%

1 2

ON/OFF 51_ON#

TP_CLK TP_DATA TP_3 TP_2

TP_1

@

0.1U_0402_10V6K

15_nonBBH@R624

15_nonBBH@

TP_1

12

14@R625

14@

12

@R535

@

1

C490

2

1

C491

@

2

0.1U_0402_10V6K

ON/OFF <42>

51_ON# <47>

JTP1

ME@JTP1

ME@

8

GND

7

GND

6

5

4

3

2

1

ACES_88058-060N

NOVO#<42>

ON/OFF 51_ON#

R532

@R532

@

100K_0402_5%

NOVO#

R725

0_0402_5%

1 2 1 2

R722

@R722

@

0_0402_5%

+3VALW+3VLP

R642

R642 100K_0402_5%

100K_0402_5%

1 2

D26

2 3

DAN202UT106_SC70-3

+3VALW

1

BATT_LOW_LED#<42>

BATT_CHG_LED#<42>

CAPS_LED#<42>

NOVO_BTN#

PWR_LED#<42>

@

1 2

R614 0_0402_5%

0.1U_0402_16V4Z

PWR_LED#

BATT_LOW_LED#

BATT_CHG_LED#

CAPS_LED#

C702

14@C702

14@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VALW

NOVO_BTN# ON/OFFBTN#

2

3

D24 PJSOT24C 3P C/A SOT-23

PJSOT24C 3P C/A SOT-23

1

LED1

19-213A-T1D-CP2Q2HY-3T_WHITE

19-213A-T1D-CP2Q2HY-3T_WHITE LED2

HT-191UD5_AMBER

HT-191UD5_AMBER LED5

19-213A-T1D-CP2Q2HY-3T_WHITE

19-213A-T1D-CP2Q2HY-3T_WHITE LED6

LED6

19-213A-T1D-CP2Q2HY-3T_WHITE

+VCC_LID

1 2

2

1

VDD

OUTPUT

2

GND

1

U34

S-5711ACDL-M3T1S_SOT23-3

JPWRB1

ME@

1

2

3

5

3

G1

4

6

4

G2

E-T_7182K-F04N-00R

@D24

@

14@

R623

14@R623

14@

12

21

300_0402_5%

14@LED2

14@

R764

14@R764

14@

12

21

470_0402_5%

14@LED5

14@

R765

14@R765

21

14@

21

R615

R615 100K_0402_5%

100K_0402_5%

3

14@U34

14@

12

300_0402_5%

R2

14@R2

14@

12

300_0402_5%

LID_SW#

2

C703

10P_0402_50V8J

1

2011/06/15 2012/07/11

+5VS

+5VALW

+3VALW

+5VALW

+5VS

LID_SW# <42>

14@C703

14@

Compal Secret Data

Deciphered Date

R689 0_0402_5%@R689 0_0402_5%@ R690 0_0402_5%R690 0_0402_5%

CR_GND

12 12

+USB_VCCB

1

C734

+

220U_6.3V_M

2

L47

1

USB20_P1 USB20_P11 USB20_P11_C

4

WCM-2012-900T_4P

+3VS

1

C733

C733 470P_0402_50V7K

470P_0402_50V7K

2

@L47

@

HP_OUTR<41> HP_OUTL<41>

EXT_MIC<41>

PLUG_IN<41>

USB20_N11<18>

USB20_P11<18>

USB20_N1<18> USB20_P1<18>

CX_GPIO0<41>

+MICBIASB

2

USB20_P1_C

3

+5VALW +3VALW

+5VS

LID_SW# PWR_LED#

BATT_LOW_LED# BATT_CHG_LED# CAPS_LED# SW_R SW_L

Title

Size Document Number Rev

C

Date: Sheet

HP_OUTR HP_OUTL

EXT_MIC

PLUG_IN

R687 0_0402_5%R687 0_0402_5%

12

R683 0_0402_5%R683 0_0402_5%

12

R534 0_0402_5%R534 0_0402_5%

12

R533 0_0402_5%R533 0_0402_5%

12

R684 0_0402_5%@R684 0_0402_5%@

12

R685 0_0402_5%@R685 0_0402_5%@

12

R688 0_0402_5%R688 0_0402_5%

12

R686 0_0402_5%R686 0_0402_5%

12

L57

@L57

USB20_N11USB20_N1_C USB20_N11_CUSB20_N1

ACES_88058-120N

ROM/KBD/PWR/CR/LED/TP Conn.

@

1

4

WCM-2012-900T_4P

JLED1

ME@JLED1

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

GND

14

GND

Compal Electronics, Inc.

LA-7984P

USB20_N11_C USB20_P11_C

CR_GND USB20_N1_C USB20_P1_C

2

3

JCR1

ME@JCR1

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

GND

18

GND

ACES_51524-0160N-001

2

3

43 60Tuesday, December 06, 2011

of

0.1

A

1 1

B

C

D

E

Right Ext.USB Conn.

2 2

C713 0.1U_0402_16V4ZC713 0.1U_0402_16V4Z

12

USB_ON#<42,45> USB_OC4# <18>

+5VALW

R02

U36

1

GND

2

VIN VIN3VOUT

4

EN

G547I2P81U_MSOP8

+USB_VCCB +USB_VCCB

8

VOUT

7

VOUT

6 5

FLG

RIGHT USB PORT X1

1

C716

1000P_0402_50V7K@

2

220U_6.3V_M

6.3Φ * 5.9 SF000001500

C714

+USB_VCCB

1

+

2

W=80mils

C715

C715 470P_0402_50V7K

470P_0402_50V7K

USB20_N9

USB20_P9

JUSB3

ME@JUSB3

ME@

1

USB20_N9_C

USB20_P9_C

2

3

D25

@D25

@

1

PJDLC05_SOT23-3

3

2

USB20_N9_C

3

USB20_P9_C

2

R868 0_0402_5%@R868 0_0402_5%@ R869 0_0402_5%@R869 0_0402_5%@

12 12

USB20_N9<18> USB20_P9<18>

4

1

L66

USB20_N9 USB20_P9

WCM-2012-900T_4P

1

2

3 4

E-T_7182K-F04N-00R

5

G1

3

6

G2

4

3 3

4 4

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

USB ext. ports

LA-7984P

44 60Tuesday, December 06, 2011

E

0.1

of

5

+1.5V to +1.05V Transfer

EU3@

+1.5V+5VALW +1.05V

10U_0603_6.3V6M

1U_0603_10V6K

C864

C863

EU3@

C863

EU3@

1

2

D D

Vout=0.8(1+10K/32.4K)

1.042 ~ 1.0469 ~ 1.0519V Spec: 0.9975 ~ 1.05 ~ 1.1025

+3VALWto+3VTransfer

C C

B B

CLKREQ_USB30#<15>

A A

+5VALW

+1.5V

+5VALW

SYSON

R1150 5.1K_0402_1%

EU3@

+3VALW +3V

SYSON<42,46,51>

PCIE_WAKE#<16,36,37>

SSM3K7002FU_SC70-3

PLT_RST#<18,23,36,37,42>

Q121

SSM3K7002FU_SC70-3

R1177

EU3@R1177

EU3@

10K_0402_5%

U52

EU3@

EU3@ 6 5 9

8 7

12

APL5930KAI-TRG_SO8

U30

3

VIN

4

VIN/CE

2

GND

RT9701-PB_SOT23-5

1 3

D

Q125

EU3@

Q125

EU3@

R02

EU3@

R747

1 2

430K_0402_5%

2

1 3

D

R02

EU3@

+3V +3V+3V

1 2

SPI_CLK_USB USB_SO_SPI_SI

5

VCNTL VIN

VOUT

VIN

VOUT

EN POK

FB

GND

1

EU3@U30

EU3@

0.2A

1

VOUT

5

VOUT

+3V+3V

R1187

2

G

10K_0402_5%

1 2

S

PCIE_WAKE#_USB3

1

2

PLT_RST#_USB3

1

2

+3V+3V

R745 10K_0402_5%

10K_0402_5%

G

1 2

S

1

2

1

C895 .1U_0402_16V7K

.1U_0402_16V7K

2

U53

EU3@

EU3@ 8 7 6 5

AT25F512AN-10SU-2.7_SO8~D

3 4

2

12

R1151

32.4K_0402_1%

EU3@

EU3@R1187

EU3@

C837

EU3@C837

EU3@

1000P_0402_50V7K

C832

1U_0402_6.3V6K

C832

1U_0402_6.3V6K

EU3@

EU3@R745

EU3@

CLKREQ_USB3

C836

EU3@C836

EU3@

1000P_0402_50V7K

EU3@C895

EU3@

VCC HOLD#

WP#

SCK

GND

SI

R1149

1 2

10K_0402_1%

EU3@

R03

R1175 10K_0402_5%

10K_0402_5%

CS#

SO

10U_0603_6.3V6M

C886

1

EU3@C886

EU3@

2

C887

10U_0603_6.3V6M

C887

10U_0603_6.3V6M

C816

0.1U_0402_16V7K

C816

0.1U_0402_16V7K

1

2

EU3@

CLK_PCIE_USB30<15> CLK_PCIE_USB30#<15>

PCIE_PRX_DTX_P4<15> PCIE_PRX_DTX_N4<15>

PCIE_PTX_C_DRX_P4<15> PCIE_PTX_C_DRX_N4<15>

SMIB<18>

SMIB_R

R267

1 2

10K_0402_5%

EU3@

24MHZ_12PF_X5H024000DC1H

R1176

EU3@R1176

1 2

EU3@

47K_0402_5%

1 2

SPI_CS_USB#

USB_SI_SPI_SO

EU3@R1175

EU3@

1 2 3 4

4

+1.05VDD

22U_0603_6.3V6M

C794

C796

1

2

EU3@

C817

0.1U_0402_16V7K

C817

0.1U_0402_16V7K

C810

C809

0.01U_0402_16V7K

C809

0.01U_0402_16V7K

1

2

EU3@

.1U_0402_16V7K EU3@

R770

0_0402_5%@

1 2

R1172 300K_0402_5%EU3@ R1172 300K_0402_5%EU3@

1 2

+3V

1

D67

EU3@D67

EU3@

1SS355TE-17_SOD323-2

+3V

C897

EU3@C897

EU3@

12P_0402_50V8J

4

C799

22U_0603_6.3V6M

1

2

0.01U_0402_16V7K

1

2

EU3@

12 12

221

R1180 100_0402_5%

100_0402_5%

1 2

Y7

1

2

C802

0.1U_0402_16V7K

1

2

EU3@

C812

C811

0.01U_0402_16V7K

C811

0.01U_0402_16V7K

1

2

EU3@

PCIE_PRX_C_DTX_P4

C834.1U_0402_16V7K

PCIE_PRX_C_DTX_N4

C835

PLT_RST#_USB3 PCIE_WAKE#_USB3 CLKREQ_USB3

SMIB_R

1U_0603_10V6K

C894

1

EU3@C894

EU3@

2

EU3@R1180

EU3@

EU3@Y7

EU3@

0.1U_0402_16V7K

C805

1

2

EU3@

C813

0.01U_0402_16V7K

1

2

EU3@

SPI_CLK_USB SPI_CS_USB# USB_SO_SPI_SI USB_SI_SPI_SO

USB3_XT1 USB3_XT2

12

1

C898

EU3@C898

EU3@

15P_0402_50V8J

2

3

D27

@

9

9 7

7 6 5

6 5

1 2 1 2

R774 0_0402_5%EU3@R774 0_0402_5%EU3@ R776 0_0402_5%EU3@R776 0_0402_5%EU3@

R772 0_0402_5%EU3@R772 0_0402_5%EU3@ R763 0_0402_5%EU3@R763 0_0402_5%EU3@

10K_0402_5%

10K_0402_5% 10K_0402_5%

10K_0402_5%

C843 .1U_0402_16V7KEU3@C843 .1U_0402_16V7KEU3@ C845 .1U_0402_16V7KEU3@C845 .1U_0402_16V7KEU3@

R759 0_0402_5%EU3@R759 0_0402_5%EU3@ R754 0_0402_5%EU3@R754 0_0402_5%EU3@

R760 0_0402_5%EU3@R760 0_0402_5%EU3@ R762 0_0402_5%EU3@R762 0_0402_5%EU3@

R570

1 2

0_0402_5%

1

C735

C735 470P_0402_50V7K

470P_0402_50V7K

2

1

1 2

2 4

4

3

1 2 1 2

1 2 4 5 3

8

12 12

10

0.1U_0402_16V7K

C798

0.01U_0402_16V7K

C798

0.01U_0402_16V7K

C797

0.01U_0402_16V7K

C797

0.01U_0402_16V7K

C800

1

2

EU3@

L60

1 2

FBMA-L11-201209-221LMA30T_0805

0.01U_0402_16V7K

1

2

EU3@

+3V +1.05VDD

U32

EU3@

12

1

PECLKP

2

PECLKN

4

PETXP

5

PETXN

7

PERXP

8

PERXN

47

PERSTB

48

PEWAKEB

10

PECREQB

46

SMIB

11

PONRSTB

15

SPISCK

14

SPICSB

16

SPISI

13

SPISO

24

XT1

23

XT2

27

IC(L)

USB_ON#<42,44> USB_OC1# <18>

C806

0.01U_0402_16V7K

C806

0.01U_0402_16V7K

C803

0.01U_0402_16V7K

C803

0.01U_0402_16V7K

1

2

EU3@

VDD3322VDD33

EU3@

+3AVDD+3V+3V

EU3@L60

EU3@

C888

1

2

EU3@

+1.05V

R766

R766 0_0603_5%

0_0603_5%

EU3@

1 2

34

UPD720202K8-701-BAA_QFN48_7X7

C704

.1U_0402_16V7K

1 2

R566 0_0402_5%R566 0_0402_5%

C808

0.01U_0402_16V7K

C808

0.01U_0402_16V7K

1

2

EU3@

0.1U_0402_16V7K

1

2

EU3@

C825

1

2

EU3@

VDD1039VDD1033VDD1030VDD1021VDD109VDD106VDD3343VDD33

0.01U_0402_16V7K

42

VDD10

1 2

4

Close to U32.25

C827

C823

0.1U_0402_16V7K

C823

0.1U_0402_16V7K

1

2

EU3@

+3AVDD

3

AVDD3325AVDD33

37

U3TXDP2

38

U3TXDN2

45

U2DM2

44

U2DP2

40

U3RXDP2

41

U3RXDN2

17

OCI2B

19

OCI1B

18

PPON2

20

PPON1

28

U3TXDP1

29

U3TXDN1

36

U2DM1

35

U2DP1

31

U3RXDP1

32

U3RXDN1

26

RREF

R02

U35

8

GND

VOUT VOUT7VIN

6

VIN3VOUT

5

FLG

EN

G547I2P81U_MSOP8

Close to U32.3

C821

10U_0603_6.3V6M

GND

49

+5VALW +USB3_VCCA

1 2

2A/Active Low

6.3Φ * 5.9 SF000001500

3

9

U3RXDP1 U3RXDP2U3RXDP2U3RXDP1

8

U3TXDN1

7

U3TXDP1

6

YSCLAMP0524P_SLP2510P8-10-9

0.01U_0402_16V7K

U3TXDP2_R

C844 .1U_0402_16V7KEU3@C844 .1U_0402_16V7KEU3@

U3TXDN2_R

C846 .1U_0402_16V7KEU3@C846 .1U_0402_16V7KEU3@

U2DN2_R U2DN2_L U2DP2_R

U3RXDP2_R U3RXDN2_R

R1161

EU3@R1161

EU3@

OCI2B

1 2

OCI1B

1 2

R1162

EU3@R1162

EU3@

U3TXDP1_R U3TXDN1_R

U2DN1_R U2DN1_L U2DP1_R

U3RXDP1_R U3RXDP1_L U3RXDN1_R

R1152

EU3@R1152

EU3@

1 2

1.6K_0402_1%

W=80mils

1

+

220U_6.3V_M

C736

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

D30

@

10

9

8

7

6 5

6

YSCLAMP0524P_SLP2510P8-10-9

1

2

4

4 5

3

8

U3TXDN2 U3TXDP2

For EMI request

U3TXDN1 U3TXDP1

U3RXDN2 U3RXDN2U3RXDN1U3RXDN1

U3TXDN2 U3TXDP2

Intel_PCH_USB2.0

USB20_N3<18>

USB20_P3<18>

Intel_PCH_USB3.0

USB3_RX4_N<18>

USB3_RX4_P<18>

U3TXDP2_L U3TXDN2_L

U2DP2_L

U3RXDP2_L U3RXDN2_L

+3V

U3TXDP1_L U3TXDN1_L

U2DP1_L

U3RXDN1_L

USB3_TX4_N<18>

USB3_TX4_P<18>

Intel_PCH_USB2.0

USB20_N2<18>

USB20_P2<18>

Intel_PCH_USB3.0

USB3_RX3_N<18>

USB3_RX3_P<18>

USB3_TX3_N<18>

USB3_TX3_P<18>

Place TX AC coupling Cap (C843~C850). Close to connector

Compal Secret Data

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

D22

U2DN1

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23-6

R730

U2DN2_L U2DN2

IU3@

12

0_0402_5%

R640

U2DP2_LU2DP2_L

IU3@

12

0_0402_5%

R709

IU3@R709

IU3@

U3RXDN2_L

12

0_0402_5%

U3RXDP2_L

12

R714

IU3@R714

IU3@

0_0402_5%

C850

IU3@C850

IU3@

.1U_0402_16V7K

U3TXDN2_L

1 2

U3TXDP2_L

1 2

C848

IU3@C848

IU3@

.1U_0402_16V7K

0_0402_5%

U2DN1_L

IU3@

12

R755

U2DP1_L

R741

12

IU3@

0_0402_5%

R773

IU3@R773

IU3@

U3RXDN1_L

12

0_0402_5%

U3RXDP1_L

12

R739

IU3@R739

IU3@

0_0402_5%

C849

IU3@C849

IU3@

.1U_0402_16V7K

U3TXDN1_L

1 2

U3TXDP1_L

1 2

C847

IU3@C847

IU3@

.1U_0402_16V7K

1

D31

@

6

I/O4

5

+5VALW +5VALW

VDD

U2DP1

4

I/O3

R728

@R728

@

1 2

0_0402_5%

WCM-2012-900T_4P

1

4

WCM-2012-900T_4P

1

4

WCM-2012-900T_4P

1

4

1 2

WCM-2012-900T_4P

1

4

L51

WCM-2012-900T_4P

1

4

L50

WCM-2012-900T_4P

1

4

L49

2

U2DP2

3

L55

R721

@R721

@

1 2

0_0402_5%

R742

@R742

@

1 2

0_0402_5%

U3RXDN2

2

U3RXDP2

3

L54

R743

@R743

@

1 2

0_0402_5%

0_0402_5% R636

@R636

@

1 2

0_0402_5%

U3TXDN2

2

U3TXDP2

3

L53

R638

@R638

@

0_0402_5%

R563

@R563

@

1 2

0_0402_5%

U2DN1

2

U2DP1

3

R562

@R562

@

1 2

0_0402_5%

R564

@R564

@

1 2

0_0402_5%

U3RXDN1

2

U3RXDP1

3

R561

@R561

@

1 2

0_0402_5%

0_0402_5% R565

@R565

@

1 2

0_0402_5%

U3TXDN1

2

U3TXDP1

3

R546

@R546

@

1 2

0_0402_5%

Title

USB3.0/Left USB Ports

Size Document Number Rev

Custom

Custom Date: Sheet

Date: Sheet

D31

@

U3TXDP2 U3TXDN2

U2DP2 U2DN2

U3RXDP2 U3RXDN2

U3TXDP1 U3TXDN1

U2DP1 U2DN1

U3RXDP1 U3RXDN1

3

2

1

+USB3_VCCA

AZC099-04S.R7G_SOT23-6

W=80mils

@

I/O2

GND

I/O1

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND D-2GND

6

SSRX+

4

GND

5

SSRX-

TAITW_PUBAU1-09FNLSCNN4H0

ME@

JUSB1

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND D-2GND

6

SSRX+

4

GND

5

SSRX-

TAITW_PUBAU1-09FNLSCNN4H0

ME@

U2DP2

Compal Electronics, Inc.

LA-7984P

45 60Tuesday, December 06, 2011

1

45 60Tuesday, December 06, 2011

VDD

I/O4

I/O3

LP2

GND GND GND

LP1

GND GND GND

of

6

5

U2DN2

4

10 11 12 13

0.1

A

B

C

D

E

+5VALW TO +5VS

+5VALW

U38

DMN3030LSS-13_SOP8L-8

8 7

1

C720

1 1

2 2

Check

220K_0402_5%

SUSP<10,53,54>

DTC124EKAT146_SC59-3

3 3

4 4

SUSP#0,25,42,51,52,53,54>

C720

10U_0603_6.3V6M

10U

+VSB

SUSP

2

G

12

R655

R655 470_0603_5%

470_0603_5%

@

13

D

2

G

Q113

S

2N7002_SOT23

@

R652

1 2

SUSP SYSON#

Q117

2

IN

12

R1110

@R1110

@

100K_0402_5%

A

5

2

12

R646

R646 150K_0402_5%

150K_0402_5%

5VS_GATE

R649

13

D

Q110

Q110 2N7002_SOT23

2N7002_SOT23

S

+5VALW+RTCVCC +5VALW

12

@

R653

R653 100K_0402_5%

100K_0402_5%

1

OUT

GND

3

12

82K_0402_5%

+1.5V+1.8VS +0.75VS+1.05VS

12

R656

R656 470_0603_5%

470_0603_5%

@

13

D

2

G

Q114

S

2N7002_SOT23

@

SYSON<42,45,51>

1 2 36

4

5VS_GATE_R

1

2

SYSON# SUSPSUSP

DTC124EKAT146_SC59-3

+5VS

1

C721

C721 10U_0603_6.3V6M

10U_0603_6.3V6M

2

R03

C726

0.01U_0603_50V7K

12

R659

R659 470_0603_5%

470_0603_5%

@

13

D

S

100K_0402_5%

Q119

@Q119

@

SYSON

2

DGPU_PWROK<19,54>

1

2

SUSP

2

G

Q116

Q116 2N7002_SOT23

2N7002_SOT23

@

C722

C722 1U_0603_10V4Z

1U_0603_10V4Z

D

S

12

13

D

S

12

R644

R644 470_0603_5%

470_0603_5%

@

13

2

G

Q107

Q107 2N7002_SOT23

2N7002_SOT23

@

R658

R658 22_0603_5%

22_0603_5%

2

G

Q115

Q115 2N7002_SOT23

2N7002_SOT23

SUSP

For Intel S3 Power Reduction.

12

@

R654

1

OUT

IN

GND

3

R1106

R1106 0_0402_5%

0_0402_5%

12

B

2

G

12

R1108

R1108 100K_0402_5%

100K_0402_5%

@

2N7002_SOT23

+5VALW

12

R1107

R1107 100K_0402_5%

100K_0402_5%

DGPU_PWROK#

13

D

Q129

Q129 2N7002_SOT23

2N7002_SOT23

S

10U

C723

10U_0603_6.3V6M

SUSP

Q112

SUSP#

2

G

1

2

+VSB

12

13

2

G

+1.5V

1

C717

C717 10U_0603_6.3V6M

10U_0603_6.3V6M

2

+3VALW

12

100K_0402_5%

100K_0402_5% R648

R648

13

D

S

+3VALW

R647

R647 470K_0402_1%

470K_0402_1%

D

S

DGPU_PWROK# <54>

+3VALW TO +3VS

U39

DMN3030LSS-13_SOP8L-8

8 7

5

4

R650

1 2

R650 0_0402_5%

0_0402_5%

@

Q111

Q111 2N7002_SOT23

2N7002_SOT23

+1.5V to +1.5VS

Q8

PMV65XP_SOT23-3~D

D

S

D

S

13

G

2

R651

0_0402_5%

1.5VS_GATE

12

1

C728

2

0.1U_0603_25V7K

DGPU_PWROK#

SUSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+3VS

1 2

1

36

2

1

C727

0.01U_0603_50V7K

2

+1.5VS

1

2

1

C729

0.1U_0603_25V7K

2

C724

C724 10U_0603_6.3V6M

10U_0603_6.3V6M

C718

C718 10U_0603_6.3V6M

10U_0603_6.3V6M

1

C725

C725 1U_0603_10V4Z

1U_0603_10V4Z

2

10U10U

R03

1

C719

C719 1U_0603_10V4Z

1U_0603_10V4Z

2

10U

12

R645

R645 470_0603_5%

470_0603_5%

@

13

D

S

12

R643

R643 470_0603_5%

470_0603_5%

@

13

D

Q109

S

2N7002_SOT23

@

SUSP

2

G

Q108

Q108 2N7002_SOT23

2N7002_SOT23

@

SUSP

2

G

+1.5V to +1.5VS_VGA Transfer

+1.5V +1.5VS_VGA

J12

@J12

300mil(7.2A)

1

C856

@C856

@

10U_0603_6.3V6M

2

10U 10U

C852

10U_0603_6.3V6M

10U

+VSB

R1102 10K_0402_5%R1102 10K_0402_5%

Q126

Q126 2N7002_SOT23

2N7002_SOT23

R782

12

0_0402_5%

R789

@R789

@

12

0_0402_5%

AO4430: Rdson: 5.5mohm @ VGS=10V

1

2

12

13

D

2

G

S

2011/06/15 2012/07/11

@

2

112

JUMP_43X118

U49

AO4304L_SO8

8 7 6 5

4

1

R02

C855

0.1U_0603_25V7K

R784

@R784

@

0_0402_5%

2

1 2

Compal Secret Data

Deciphered Date

1 2 3

1

C853

C853 10U_0603_6.3V6M

10U_0603_6.3V6M

2

10U

D

+3VALW TO +3VALW(PCH AUX Power)

@

PJ1

JUMP_43X118

U40

DMN3030LSS-13_SOP8L-8

8 7

5

1 2

+5VALW

R780

100K_0402_5%

2

G

Q124

300mil(7.2A)

Q127

@

Q127

@

2N7002_SOT23

Title

Size Document Number Rev

Custom

Date: Sheet

10U_0603_6.3V6M

PCH_PWR_EN#

PCH_PWR_EN<42>

+3VALW +3V_PCH

1

C782

2

+VSB

12

R778

R778 47K_0402_5%

47K_0402_5%

13

D

Q120

2

2N7002_SOT23

G

S

PCH_PWR_EN#

PCH_PWR_EN

12

2N7002_SOT23

R781

100K_0402_5%

1

C851

C851 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C854

0.1U_0402_16V4Z

2

12

R02

1 2

1

36

C780

C780 1U_0603_10V4Z

1U_0603_10V4Z

2

4

R779 0_0402_5%

0_0402_5%

12

13

D

S

1

C783

C783 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

@R779

@

C781

0.1U_0603_25V7K

2

D

S

R1101

@R1101

@

470_0603_5%

1 2

13

@

R790

2

0_0402_5%

G

R791

0_0402_5%

Compal Electronics, Inc.

DC Interface

LA-7984P

DGPU_PWROK#

12

SUSP

@R791

@

12

E

12

R777

R777 470_0603_5%

470_0603_5%

13

D

S

@

PCH_PWR_EN#

2

G

Q118

@

Q118

@

2N7002_SOT23

46 60Tuesday, December 06, 2011

of

0.1

5

4

3

2

1

2

12

PR128

PR128 200_0603_5%

200_0603_5%

@

12

PC115

PC115 1U_0805_25V6K

1U_0805_25V6K

@

12

2

VIN

12

100P_0402_50V8J

PC103

PR118

68_1206_5%

13

PC104

1000P_0402_50V7K

VIN

@

PD103

LL4148_LL34-2

1 2

51ON-1

12

@

12

PC113

0.1U_0603_25V7K

@

12

@

PR119

PR119 68_1206_5%

68_1206_5%

VS

DC030006J00

PF101

7A_24VDC_429007.WRML

4

3

2

4602-Q04C-09R 4P P2.5@

4602-Q04C-09R 4P P2.5@ JDCIN1

JDCIN1

2

1

D D

APDIN1APDIN

21

12

PC101

12

1000P_0402_50V7K

PL101

SMB3025500YA_2P

1 2

100P_0402_50V8J

PC102

Unpop for KB9012

PD104

@PD104

@

LL4148_LL34-2

CHGRTCP

LL4148_LL34-2

PR120

200_0603_5%

1 2

@

100K_0402_1%

PR124

22K_0402_1%

1 2

@

RTCVREF

3.3V

12

@

PC114

PC114 10U_0603_6.3V6M

10U_0603_6.3V6M

12

PR123

@

@PU102

@

APL5156-33DI-TRL_SOT89-3

3

C C

+3VLP

PR127

PR127 0_0402_5%

0_0402_5%

1 2

B B

BATT+

51_ON#<43>

PU102

VOUT

1 2

@

GND

PJ101

PJ101 JUMP_43X39@

JUMP_43X39@

112

TP0610K-T1-E3_SOT23-3

51ON-2

PC112

0.22U_0603_25V7K

51ON-3

CHGRTCIN

2

VIN

1

PQ104

@

+CHGRTC

PD109

JRTC2

-+

MAXEL_ML1220T10@

PR131

560_0603_5%

12

1 2

PR132

560_0603_5%

1 2

PD109

RB751V-40_SOD323-2

12

1 2

PD108

RB751V-40_SOD323-2

+RTCBATT

RTCVREF

RTC Battery

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/01/25 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR DCIN / Vin Detector /Pre-charge

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

LA-7984P

1

47 60Tuesday, December 06, 2011

0.1

of

5

4

3

2

1

JBATT1

VMB2

JBATT1

1

2

2 3 4

D D

C C

5 6

7 GND GND

TYCO_1775789-1

@

JBATT2

GND GND

TYCO_1775789-1

@

EC_SMCA

3

EC_SMDA

4 5 6 7 8 9

1

2

3

4

5

6

7

8 9

12

PR201

100_0402_1%

PR201

100_0402_1%

12

PR202

100_0402_1%

PR202

100_0402_1%

1 2

PR203

6.49K_0402_1%

1 2

PR204

PR204 10K_0402_5%

10K_0402_5%

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

21

VMB

SMB3025500YA_2P

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 <42,49>

EC_SMB_DA1 <42,49>

+3VALW

BATT_TEMP <42>

PL201

1 2

A/D

BATT+

12

PC202

0.01U_0402_25V7K

PH1 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

VL

12

PC203

H_PROCHOT#<6,42>

PROCHOT<42>

0.1U_0603_16V7K

+3VS

@

PR208

1 2

PQ201

13

D

ADP_OCP_1

2

G

SSM3K7002FU_SC70-3

S

PR212

PR212 0_0402_5%

0_0402_5%

1 2

100K_0402_1%

@PU201

@

1 2 3 4

OTP_N_003

PR213 0_0402_5%

@

PU201

VCC GND OT1 OT2

G718TM1U_SOT23-8

TMSNS1 RHYST1 TMSNS2 RHYST2

12

ADP_I need to write Charge Options Register (0x12H)=> bit6=1

0: IOUT is the 20x current amplifier output <default @ POR> 1: IOUT is the 40x current amplifier output

8

OTP_N_002

7 6

ADP_OCP_2

5

29.4K_0402_1%@

MAINPWON <42,50>

For KB930 --> Keep PU201 circuit (Vth = 0.825V)

For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206 PH201, PR205, PR211,PQ201,PR208,PR212

NTC_V

+3VLP

12

PR206

12.7K_0402_1%

<42>

PR209

@PR209

@

10K_0402_1%

12

PH201

100K_0402_1%_NCP15WF104F03RC

12

@

12

ADP_I<42,49>

PR210

1 2

PR205

Turbo_V

90W(DIS) : 6.65K 65W(UMA) : 1.65K

1 2

6.65K_0402_1%

Turbo_V

PR211

<42>

1 2

10K_0402_1%

PR207

21.5K_0402_1%

B B

VMB2

PR217

768K_0402_1%

PR219

10K_0402_1%

1 2

PR221

221K_0402_1%

1 2

A A

5

12

PC204

3 2

PR223

PR223 10K_0402_1%

10K_0402_1%

PR225

PR225 10K_0402_1%

10K_0402_1%

@

0.01U_0402_25V7K

P2

+

-

10M_0402_5%

8

P

O

G

LM393DG_SO8

4

12

PR218

1 2

1

PU202A

2VREF_8205

RTCVREF

BATT_LEN#<42>

PR214

PR214 100K_0402_1%

100K_0402_1%

1 2

PR226

100K_0402_1%

+3VLP

1 2

+3VALW+3VLP

1 2

13

2

G

2

G

PR215

PR215 100K_0402_1%

100K_0402_1%

PQ202

D

2N7002KW_SOT323-3

S

PQ203

13

D

2N7002KW_SOT323-3

S

4

BATT_OUT <49>

PQ205

TP0610K-T1-E3_SOT23-3

B+

VL

PR222

100K_0402_1%

SPOK<50>

PR224

1 2

1K_0402_5%

1 2

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

22K_0402_1%

13

D

2

G

2N7002W-T/R7_SOT323-3

S

PC207

1U_0402_6.3V6K

2010/01/25 2012/07/11

PR220

1 2

PQ204

12

PC205

PR216

100K_0402_1%

0.22U_0603_25V7K

Compal Secret Data

Deciphered Date

2

13

2

12

PC206

0.1U_0603_25V7K

+VSBP

PJ201

PJ201 JUMP_43X39@

JUMP_43X39@

2

112

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

Date: Sheet

+VSB

LA-7984P

1

0.1

of

48 60Tuesday, December 06, 2011

5

13

1 2 36

12

P2

PC301

0.1U_0603_25V7K

P2-2

PQ307B

5

12

PR303

200K_0402_1%

P2-1

12

PR308

34

2N7002KDW-2N_SOT363-6

150K_0402_1%

PQ302

SI4459_SO8

1 2 3 6

4

5600P_0402_25V7K

12

PR307

PR307 20K_0402_1%

20K_0402_1%

PQ308

13

D

2N7002KW_SOT323-3

2

G

S

PR314

PR317

1 2

64.9K_0603_1%

EC_SMB_DA1<42,48>

EC_SMB_CK1<42,48>

PQ301

PQ301 AO4407A_SO8

AO4407A_SO8

DTA144EUA_SC70-3

47K_0402_5%

13

2

PQ307A

PACIN

PQ311

DTC115EUA_SC70-3

PR321

1 2

10K_0402_5%

8 7

5

PQ304

2

1 3

PQ305

DTC115EUA_SC70-3

PR318

47K_0402_1%

1 2

ACOFF-1

2

12

PR325

PR325 0_0402_5%

0_0402_5%

PQ313

13

D

2

G

S

4

2N7002KW_SOT323-3

VIN

D D

C C

B B

12

PR301

61

2N7002KDW-2N_SOT363-6

2

PACIN

ACON

ACOFF<42>

BATT_OUT<48>

CHGVADJ=(Vcell-4)/0.10627

Vcell 4V

4.2V

4.35V

CC=0.25A~3A IREF=1.016*Icharge IREF=0.254V~3.048V VCHLIM need over 95mV

A A

CHGVADJ

0V

1.882V

3.2935V

PR335

47K_0402_1%

ACPRN <50>

DTC115EUA_SC70-3

12

PQ316

BQ24727VDD

2

4

P3

8 7

5

1UH_PCMB061H-1R0MS_7A_20%

1 2

PC304

BATT_OUT <48>

VIN

12

PR315

390K_0603_1%

12

PC323

0.1U_0603_25V7K

+3VALW

12

PR336

PR336 10K_0402_1%

10K_0402_1%

13

SH00000AA00

1 2

PC302

10U_0805_25V6K@

+3VALW

PR316

10K_0402_5%

1 2

@

PR323

1 2

316K_0402_1%

PR337

10K_0402_1%

1 2

PACIN

12

PR339

12K_0402_1%

1 2

PL301

ACPRN<50>

ADP_I<42,48>

PC312

1 2

100P_0603_50V8

PR302

0.01_1206_1%

1 2

PC315

10U_0805_25V6K@

@

PR312

@PR312

@

12

39.2K_0402_1%

6

ACDET

7

IOUT

8

SDA

BQ24727RGRR_VQFN20_3P5X3P5

9

SCL

10

12

ILIM

PR326

PR326 100K_0402_1%

100K_0402_1%

ACIN <16,42>

B+

4 3

ACP

PC308

+3VALW

1 2

12

0.1U_0603_25V7K

PR310

PR309

100K_0402_1%

10K_0603_1%

PR313

@

1 2

4.7M_0603_1%

3

5

4

ACOK

CMPIN

CMPOUT

PU301

SA000051W00

SRN

BM

SRP

12

13

11

12

PR328

PR327

10_0603_5%

6.8_0603_5%

6.8_0603_5% PC320

PC320

0.1U_0603_25V7K

12

PC321

0.1U_0603_25V7K

ACN

0.1U_0603_25V7K

PC310

2

ACP

GND

14

3

PC309

12

0.1U_0603_25V7K

12

1

ACN

TP

VCC

PHASE

HIDRV

BTST

REGN

LODRV

15

12

<BOM Structure> 21

20

19

18

BST_CHG

17

PD303

16

RB751V-40_SOD323-2

12

PC318

PC318 1U_0603_25V6K

1U_0603_25V6K

@

PC322

0.1U_0603_25V7K

P2

PR319

10_1206_5%

BQ24727VCC

DH_CHG

12

DL_CHG

1 2

PC313

1 2

1U_0603_25V6K

PR324

2.2_0603_5%

1 2

2

Need EC write ChargeOption() bit[8]=0 Setting (ACP to PHASE Rising Threshold)=1350mV(min)

B+

1 2 3 6

DISCHG_G

PC307

1 2

PC303

LX_CHG

0.047U_0603_25V7M

BQ24727VDD

1 2

PC305

4.7U_0805_25V6-K

PC314

12

1 2

PC306

PC307

1 2

4.7U_0805_25V6-K

2200P_0402_50V7K

6

578

4

6

578

4

PR304

47K_0402_1%

1 2

PR305

PR305 10K_0402_1%

10K_0402_1%

1 2

DISCHG_G-1

PQ306

13

DTC115EUA_SC70-3

2

PQ310

AO4466L_SO8

SH000005Y80

4.7UH_PCMB104E-4R7MS_10A_20%

123

12

PQ312

123

PR322

AO4466L_SO8

6251_SN

12

PC319

PD301

PL302

1 2

4.7_1206_5%

680P_0603_50V7K

PQ303

AO4407A_SO8

4

ACOFF-1

1SS355_SOD323-2

1 2

PD302

PD302 1SS355_SOD323-2

1SS355_SOD323-2

1 2

0.01_1206_1%

CHGCHG

1 2

SRP

1 2

12

PC311

0.1U_0603_25V7K

PR320

1

8 7

5

PR306

PR306 402K_0402_1%

402K_0402_1%

PQ309

2N7002W-T/R7_SOT323-3

13

D

2

G

S

4 3

SRN

VIN

PACIN

12

PC316

PC317

10U_0805_25V6K

BATT+

12

10U_0805_25V6K

For disable pre-charge circuit.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/07/112010/01/13

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CHARGER

LA-7984P

49 60Tuesday, December 06, 2011

1

0.1

of

5

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

4

3

2

1

2VREF_8205

+3VALWP +3VALW

D D

PR401

13K_0402_1%

1 2

PR403

RT8205_B+

PJ401

B+

PC405

C C

B B

2

12

0.1U_0603_25V7K

EC_ON<42,43>

MAINPWON<42,48>

PJ401

112

JUMP_43X118@

PC402

0.1U_0603_25V7K

For KB9012

12

PC403

4.7U_0805_25V6-K

+3VALWP

PR418

PR418 10K_0402_5%

10K_0402_5%

PR413

PR413 0_0402_5%

0_0402_5%

12

PC404

PC406

4.7U_0805_25V6-K

12

2N7002KDW-2N_SOT363-6

12

2200P_0402_50V7K

4.7UH +-20% PCMC063T-4R7MN 5.5A

1

+

2

AO4466L_SO8

PL401

1 2

PC415

PC415 150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M

61

PQ405A

PR409

PC418

VL

6

PQ401

123

12

4.7_1206_5%

12

3 6

241

680P_0603_50V7K

2

PR414

100K_0402_1%

12

578

4

578

PQ403

PQ403 AO4712_SO8

AO4712_SO8

Typ: 175mA

34

5

+3VLP

12

PC411

4.7U_0805_10V6K

1 2

2.2_0603_5%

PC412

0.1U_0603_25V7K

PR411

499K_0402_1%

1 2

B+

ENTRIP2ENTRIP1

PQ405B

PQ405B 2N7002KDW-2N_SOT363-6

2N7002KDW-2N_SOT363-6

PR407

12

PR412

100K_0402_1%

PR403

20K_0402_1%

1 2

PR405

130K_0402_1%

1 2

25

7 8

BST_3V

9

UG_3V

10

LX_3V

11

LG_3V

12

PC420

1U_0603_10V6K

2VREF_8205

PU401

P PAD

VO2 VREG3 BOOT2 UGATE2 PHASE2 LGATE2

12

PC401

1U_0603_10V6K

ENTRIP2

6

5

FB2

ENTRIP2

VFB=2.0V

SKIPSEL

EN

14

13

RT8205_B+

4

TONSEL

15

3

2

REF

VIN16GND

17

12

PC422

0.1U_0603_25V7K

FB1

UGATE1 PHASE1

PC421

PR402

30K_0402_1%

1 2

PR404

19.6K_0402_1%

1 2

PR406

66.5K_0402_1%

ENTRIP1

1 2

1

ENTRIP1

24

VO1

23

PGOOD

22

BOOT1

21 20 19

LGATE1

RT8205EGQW_WQFN24_4X4

NC18VREG5

VL

Typ: 175mA

4.7U_0805_10V6K

BST_5V UG_5V LX_5V LG_5V

PC407

4.7U_0805_25V6-K

PR408

0_0603_5%

1 2

RT8205_B+

12

PC408

4.7U_0805_25V6-K

SPOK <48>

PC413

0.1U_0603_25V7K

1 2

12

PC410

PC409

0.1U_0603_25V7K

2200P_0402_50V7K

+5VALWP +5VALW

12

678

PQ402

35241

5

PQ404TPC8A03-H_SO8 PQ404TPC8A03-H_SO8

4

+3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A

PJ402

2

112

JUMP_43X118@

PJ403

2

112

JUMP_43X118@

TPC8065-H_SO8

PL402

1 2

12

PR410

4.7_1206_5%

12

PC419

680P_0603_50V7K

PL402

4.7UH_PCMB104E-4R7MS_10A_20%

786

123

+5VALWP

1

+

PC417

PC417 150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M

2

13

PR415

200K_0402_1%

ACPRN<49>

A A

200K_0402_1%

EC_ON<42,43>

12

@

2

@

5

2

G

13

@

13

D

1 2

VS

PQ407

S

100K_0402_1%

2N7002W-T/R7_SOT323-3

PQ408

DTC115EUA_SC70-3

PR416

@

12

PR417

40.2K_0402_1%

@

For KB9012

2

PC423

4.7U_0603_6.3V6M

4

PQ406

PQ406 DTC115EUA_SC70-3

DTC115EUA_SC70-3

Security Classification

2010/01/25 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/25 2012/07/11

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

3VALWP/5VALWP

Size Document Number Rev

Custom

Date: Sheet

LA-7984P

50 60Tuesday, December 06, 2011

of

1

of

0.1

A

1 1

PR501

0_0402_5%

SYSON<42,45,46>

2 2

1 2

PR502

1 2

47K_0402_5%

12

@

PC501

.1U_0402_16V7K

12

PR507

1 2

11.5K_0402_1%

PR508

PR508 10K_0402_1%

10K_0402_1%

100K_0402_1%

PR505

PR506

1 2

470K_0402_1%

12

B

PU501

1

VBST

PGOOD

2

TRIP

DRVH

3

EN

4 5

SW

V5IN

VFB

DRVL

RF

TP

TPS51212DSCR_SON10_3X3

VFB=0.7V

C

1.5V_B+

678

PQ501

PQ501 TPC8065-H_SO8

TPC8065-H_SO8

PC506

PR503

2.2_0603_5%

BST_1.5V DH_1.5V LX_1.5V

DL_1.5V

1 2

12

10 9 8 7 6 11

0.22U_0603_16V7K

BST_1.5V-1

+5VALW

PC508

1U_0603_10V6K

PC506

1 2

35241

786

5

PQ502

4

TPC8A03-H_SO8

123

PC502

1UH_PCMC063T-1R0MN_11A_20%

12

PR504

4.7_1206_5%

12

PC509

1000P_0603_50V7K

12

PC503

10U_0805_25V6K

PL501

1 2

12

PC504

0.1U_0402_25V6

12

PC505

2200P_0402_50V7K

1

+

2

PJ501

2

JUMP_43X118@

PC507

PC507 220U_6.3V_M

220U_6.3V_M

+1.5VP

112

D

B+

+1.5VP

+1.5VP OCP(min)=15.6A

PJ502

2

112

JUMP_43X118@

JUMP_43X118@ PJ503

PJ503

2

112

JUMP_43X118@

+1.5V

3 3

PU502

PJ505

+5VALW

2

112

JUMP_43X118@

SUSP#<10,25,42,46,52,53,54>

4 4

A

1.8VSP_VIN

12

PC510

PC510 22U_0805_6.3VAM

22U_0805_6.3VAM

PR511

1 2

0_0402_5%

EN_1.8VSP

PR512

PR512 1M_0402_5%

1M_0402_5%

@PC515

@

12

PC515

1 2

10

PVIN

9

PVIN

8

SVIN

5

EN

11

0.1U_0402_10V7K

4

2

LX

PG

3

LX

6

FB

TP

NC

7

1

SY8033BDBC_DFN10_3X3

B

1.8VSP_LX

FB=0.6Volt

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PL503

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR510

20K_0402_1%

PR509

4.7_1206_5%

12

PC512

680P_0603_50V7K

1.8VSP_FB

PR513

10K_0402_1%

Issued Date

C

PC514

22U_0805_6.3VAM

+1.8VSP

12

PC511

68P_0402_50V8J

12

2010/01/25 2012/07/11

12

PC513

22U_0805_6.3VAM

Compal Secret Data

Deciphered Date

PJ504

2

112

JUMP_43X118@

+1.8VS+1.8VSP

1.8VSP max current=4A

Compal Electronics, Inc.

Title

PWR-+1.5VP/+1.8VSP

Size Document Number Rev

Custom

Date: Sheet

D

LA-7984P

of

51 60Tuesday, December 06, 2011

0.1

5

VID [0] VID[1] VCCSA Vout 0 0 0.9V 0 1 0.8V 1 0 0.725V 1 1 0.675V

output voltage adjustable network

D D

1

PC614

PC613

1 2

2

2200P_0402_50V7K

0.1U_0603_25V7K

PJ601

+3VALW

C C

B B

A A

PJ601

2

112

JUMP_43X118@

+V1.05S_VCCP_PWRGOOD<53>

1 2

66.5K_0402_1%

PR615

0_0402_5%

1 2

SUSP#<10,25,42,46,51,53,54>

0.1U_0402_16V7K

5

12

@

PC625

@

+VCCSA_PWR_SRC

PR614

TRIP_+V1.05S_VCCPP EN_+V1.05S_VCCPP

@

PR621

PR621 10K_0402_1%

10K_0402_1%

1 2

@

0.1U_0603_25V7K

FB_+V1.05S_VCCPP RF_+V1.05S_VCCPP

12

PR616

470K_0402_1%

2

PC615

1

10U_0805_6.3V6M

+3VS

PR612

PR612 100K_0402_5%

100K_0402_5%

1 2

@

1 2 3 4 5

PR619

4.32K_0402_1%

@

71.5K_0402_1%

10U_0805_6.3V6M

PR622

2

PC616

1

PU602

PGOOD TRIP EN VFB RF

TPS51212DSCR_SON10_3X3

@

PC629

12

1000P_0402_50V7K

12

13

D

@

PQ603

S

SSM3K7002FU_SC70-3

@

2.2U_0603_10V7K

+VCCSA_PWR_SRC

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

11

TP

@

2

G

12

@

4

SA_PGOOD<42>

PC602

1 2

PC617

12

0.22U_0402_10V6K

BST_+V1.05S_VCCPP

UG_+V1.05S_VCCPP SW_+V1.05S_VCCPP +V1.05S_VCCPP_5V LG_+V1.05S_VCCPP

PR618

@

12

1.2K_0402_1%

+3VS

PR623

PR623 100K_0402_5%

100K_0402_5%

1 2

@

PR625

PR625 100K_0402_5%

100K_0402_5%

.01U_0402_16V7K

PC630

1 2

@

4

+5VALW

PC618

3300P_0402_50V7K

1 2

0_0603_5%

PR624

0_0402_5%

@

PR604

10_0402_1%

PU601

19

PGND

20

PGND

21

PGND

22

VIN

23

VIN

24

VIN

12

PR613

@

12

13

6

@

4

@

PR601

1K_0402_5%

PR603

1K_0402_5%

EN

BST

SW

TP

MODE

678

35241

786

5

3

12

+VCCSA_EN

+VCCSA_BT

12

+VCCSA_PHASE

11

10

9

8

7

25

PR608

@ PR608

@

33K_0402_5%

+V1.05S_VCCPP_B+

PQ601

PQ601 TPC8037-H_SO8

TPC8037-H_SO8

PQ602

TPC8A03-H_SO8

123

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VS

12

PR602

100K_0402_5%

+VCCSA_PWRGD

+VCCSA_VID0

+VCCSA_VID1

PC601

1 2

1U_0603_10V6K

12

18

17

16

14

15

VID0

VID1

V5FILT

V5DRV

PGOOD

TPS51461RGER_QFN24_4X4

VOUT

COMP

VREF

2

12

PC624

1 2

@

3

PC619

0.01U_0402_25V7K

SLEW

5

4

1 2

GND

1

PR610

5.1K_0402_1%

0.22U_0603_16V7K

+5VALW

12

PC626

PC626 1U_0603_6.3V6M

1U_0603_6.3V6M

@

VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB) VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)

VCCP_PWRCTRL <10>

H_VCCSA_VID1 <10>

H_VCCSA_VID0 <10>

PR605

0_0402_5%

1 2

PR606

PR606 0_0603_5%

0_0603_5%

+VCCSA_BT_1

1 2

12

PR607

4.7_1206_5%

12

PC604

1000P_0603_50V7K

12

PC621

PC620

0.1U_0402_25V6

2200P_0402_50V7K

@

PL602

1UH_PCMC063T-1R0MN_11A_20%

1 2

@

12

@

PR617

4.7_1206_5%

@

12

PC628

1000P_0603_50V7K

Issued Date

2

+VCC_SAP TDC 4.2A Peak Current 6A OCP current 7.2A

The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability.

+V1.05S_VCCP_PWRGOOD <53>

PC603

0.22U_0603_16V7K

12

1 2

12

@

PL601

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

1 2

PC605

22U_0805_6.3V6M

PJ603

2

112

JUMP_43X118@

PC623

JUMP_43X118@

4.7U_0805_25V6-K

PC622

12

4.7U_0805_25V6-K

@

PC606

1 2

PC607

22U_0805_6.3V6M

+V1.05S_VCCPP

1 2

PC627

0.1U_0402_10V7K

@

PR620

0_0402_5%

12

@

Compal Secret Data

2010/01/25 2012/07/11

Compal Secret Data

Deciphered Date

2

@

12

PC608

0.1U_0402_10V7K

PR609

100_0402_5%

PR611

0_0402_5%

B+

VCCIO_SENSE <9,53>

1 2

22U_0805_6.3V6M

12

1

PJ602

2

+VCCSAP

@

PC609

12

PC611

1 2

22U_0805_6.3V6M

PJ604

2

JUMP_43X118@

PC611

PC610

2200P_0402_50V7K

+VCCSA_SENSE <10>

112

@

Compal Electronics, Inc.

Title

PWR +VCCSAP/1.0

Size Document Number Rev

C

Date: Sheet

JUMP_43X118@

PC612

1 2

22U_0805_6.3V6M

+V1.05S_VCCP+V1.05S_VCCPP

1

+

PC631

PC631 150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M

2

112

@

1 2

LA-7984P

1

+VCCSA

+VCCSAP

0.1

52 60Tuesday, December 06, 2011

0.1

of

5

4

3

2

1

+1.5V

1

PJ701

1

JUMP_43X118

D D

PQ701

PQ701 2N7002W-T/R7_SOT323-3

2N7002W-T/R7_SOT323-3

PR703

49.9K_0402_1%

PU702

1

VREF

2

REFIN

3

GSNS

4

VSNS

PC712

1 2

12

PC701

0.1U_0402_10V7K

+3VS

PR705

100K_0402_1%

PR706

100K_0402_1%

1 2

16

17

15

PAD

MODE

PGOOD

TPS51219RTER_QFN16_3X3

COMP5TRIP6GND

PR711

12

75K_0402_1%

7

SUSP<10,46,54>

C C

PR710

60.4K_0402_1%

+V1.05S_VCCP_PWRGOOD<52>

PC708

0.1U_0402_25V6

60.4K_0402_1%

1 2

10.7K_0402_1%

12

PR714

1 2

10_0402_5%

PR717

1 2

10_0402_5%

PR707

1 2

PR708

1 2

PR709

1 2

PC720

12K_0402_1%

0.01UF_0402_25V7K

1 2

PC716

PC716 1000P_0402_50V7K

1000P_0402_50V7K

1 2

12

10K_0402_1%@

PR716

1 2

10_0402_5%

@

PC707

.1U_0402_16V7K

PR715

0_0402_5%

1 2

0.01UF_0402_25V7K

SUSP#

,52,54>

B B

VCCIO_SENSE<9,52>

VSSIO_SENSE_L<9>

A A

2

G

BST_1.05VS_VCCP

14

13

EN

8

BST

PGND

13

SW

D

S

DH

DL

V5

PR713

2.2_0603_5%

1 2

12

11

10

9

LX_1.05VS_VCCP

DH_1.05VS_VCCP

JUMP_43X118

@

2

PC702

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K PR702

PR702

1 2

1K_0402_1%

PR704

PC710

0.1U_0603_25V7K

1 2

DL_1.05VS_VCCP

12

PC713

1U_0603_10V6K

12

+5VALW

PC704

1K_0402_1%

12

PC705

.1U_0402_16V7K

10U_0603_6.3V6M

PQ702

4

PQ703

4

TPCA8057-H_PPAK56-8-5

PU701

1

VIN

2

GND

3

VREF

VCNTL

4

VOUT

APL5336KAI-TRL_SOP8P8

+0.75VSP

12

PC706

10U_0603_6.3V6M

1.05VS_B+

5

TPCA8065-H_PPAK56-8-5

123

5

123

8

NC

7

NC

6 5

NC

9

TP

PC718

12

PC719

PC714

0.1U_0402_25V6

1.0UH +-20% PCMC104T-1R0MN 20A

12

PR712

4.7_1206_5%

12

PC715

1000P_0603_50V7K

PC719

PC718

2200P_0402_50V7K

PL701

12

+3VALW

12

PC703

PC703 1U_0603_10V6K

1U_0603_10V6K

+1.05VS_VCCPP OCP(min)=20.75A

PJ705

2

112

JUMP_43X118@

12

PC717

4.7U_0805_25V6-K

+1.05VS_VCCPP

1

+

2

PC709

330U_X_2VM_R6M

PJ702

2

112

JUMP_43X118@

PJ703

2

112

JUMP_43X118@

JUMP_43X118@ PJ704

+1.05VS

PJ704

2

JUMP_43X118@

PJ605

2

JUMP_43X118

JUMP_43X118 PJ606

2

JUMP_43X118

112

@PJ605

@

112

@PJ606

@

112

+1.05VS+1.05VS_VCCPP

+V1.05S_VCCP

Ivy Bridge CPU ES2 Using

B+

+0.75VS+0.75VSP

Security Classification

2010/01/25 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/25 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR +1.05VS_VCCPP/+0.75VSP

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

LA-7984P

1

53 60Tuesday, December 06, 2011

of

0.1

1 2

PR856 10K_0402_5%

GPU_VID0

@

PD808

PR802

PR802 147K_0402_1%

147K_0402_1%

1 2

@

PR803

1 2

@0_0402_5%

PR805

10K_0402_1%

1 2

@PR806

@

1.91K_0402_1%

1 2

12

PR811

1.91K_0402_1%

+3VS

@PR869

@

PR818

499_0402_1%

1 2

1000P_0402_50V7K

PR820

1.15K_0402_1%

1 2

ISEN2_VGA

ISEN1_VGA

12

PR824

68.1K_0402_1%

A

1 2

PR857 10K_0402_5%

GPU_VID5

@

DGPU_PWROK#<46>

1 2

VRON_VGA

PD809

DPRSLPVR_VGADPRSLPVR_VGA

PR806

1 2

147K_0402_1%

VW_VGA

22P_0402_50V8J

FB1_VGA

1 2

PR825

10_0402_5%

1 2

PR829

0_0402_5%

PR835

0_0402_5%

1 2

PR836

10_0402_5%

1 2

A

1 2

PR858 10K_0402_5%PR858 10K_0402_5%

PR859 10K_0402_5%

PR860 10K_0402_5%PR860 10K_0402_5%

GPU_VID3

GPU_VID2

GPU_VID4

@

SUSP<10,46,53>

RB751V-40_SOD323-2

PC806 0.1U_0402_16V7KPC806 0.1U_0402_16V7K

CLK_ENABLE#_VGA

PR812

100K_0402_5%

PR813

12

RBIAS_VGA

COMP_VGA

FB_VGA

ISEN3_VGA

1 2

PC823

PC837

1 2

390P_0402_50V7K

PR815

@PR815

@

0_0402_5%

+5VS

For 15W one phase

12

PC848

0.22U_0402_10V6K

VSUM-_VGA

330P_0402_50V7K

1000P_0402_50V7K

1 2

PR861 10K_0402_5%

@

1 2

PSI#_VGA

12

PC857

PC862

1 2

PR862 10K_0402_5%PR862 10K_0402_5%

GPU_VID1

PR863

@PR863

@

47K_0402_5%

PU801

1 2 3 4 5 6 7 8 9

10 41

PR865

@PR865

@

0_0402_5%

VSEN_VGA

PC849

0.22U_0402_10V6K

1 2

GPU_VID0

SUSP

12

PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2

AGND

12

PC863

@330P_0402_50V7K

PR848

PR848 0_0402_5%

0_0402_5%

1 2 1 2

PR801

PR801 0_0402_5%

0_0402_5%

1 2

GPU_VID6

38

39

37

40

VR_ON

CLK_EN#

DPRSLPVR

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

RTN_VGA

ISUM-_VGA

12

PR841 0_0402_5%

0_0402_5%

<23>

35

VID4

17

16

VDD_VGA

12

PR826

VSUM_VGA_N001

12

PC864

PR837

PR837 1K_0402_1%

1K_0402_1%

1 2

10U_0805_10V6K

2

G

@PR841

@

PR842

0_0402_5%

UGATE2 PHASE2

LGATE2

LGATE1 PHASE1

VIN

IMON18BOOT119UGATE1

20

IMON_VGA

VIN_VGA

12

PC850

1U_0603_10V6K

@82.5_0402_5%

@0.01U_0402_25V7K

+5VALW

+1.05VS +1.05VS_VGA

12

PC867

PR840

PR840 20K_0402_1%

20K_0402_1%

PR839

100K_0402_5%

1 2

13

100K_0402_5%

1 2

PQ809

D

2N7002KW_SOT323-3

S

N13P-GL:0.975V(VID5~0=101010) N13M-GE:0.9V(VID5~0=110000)

<23>

GPU_VID3

GPU_VID4

GPU_VID5

PR845

PR844

0_0402_5%

1 2

30 29 28 27 26 25 24 23 22 21

PR823

12

PC858

0.22U_0603_10V7K

0_0402_5%

1 2

VCCP_VGA

+VGA_B+

PC859

PR845

0_0402_5%

1 2

+5VS

12

0.033U_0603_25V7K

12

0.1U_0402_16V7K

PR843

1 2

VID031VID132VID233VID334VID536VID6 BOOT2

VSSP2

VCCP PWM3

VSSP1

ISL62883CHRTZ-T_TQFN40_5X5

PR821 0_0402_5%PR821 0_0402_5%

1 2

1_0402_5%

1 2

PC851

0.22U_0603_25V7K

+3VS_VGA

1 2

PR853 10K_0402_5%PR853 10K_0402_5%

PR852 10K_0402_5%

GPU_VID5

GPU_VID4

@

1 1

DGPU_PWROK<19,46>

2 2

VGA_AC_DET<23,42>

@

PR871

470K_0402_5%_TSM0B474J4702RE

1 2

4.02K_0402_1%

PR816

1 2

@249K_0402_1%

3 3

4 4

1 2

PC847

150P_0402_50V8J

For N13M-GE(15W without turbo)

@:PR806,PR812,PC823,PC848,PC849,PR832, PC801,PC802,PQ801,PQ802,PQ803,PR804, PC805,PC803,PR808,PR809,PR810,PC807, PC804

POP:PR815,PC803

PR816->120K(SD034120380) PR820->1.69K(SD00000JB80) PR822->22K(SD034220280) PR837->866(SD034866080) PC858->0.1uF(SE026104M80) PC859->0.068uF(SE026683K80) PR850->22.1K(SD034221280)

1 2

PR864 10K_0402_5%PR864 10K_0402_5%

PR854 10K_0402_5%

GPU_VID2

GPU_VID3

@

NVDD_PWR_EN<18>

SUSP#<10,25,42,46,51,52,53>

DPRSLPVR_VGA<23>

+3VS

@

1 2

PH802

12

PR817

8.06K_0402_1%

PC838

100P_0402_50V8J

1 2

FB2_VGA

1 2

33K_0402_1%

+VGA_COREP

VCCSENSE_VGA<24>

VSSSENSE_VGA<24>

1 2

PR855 10K_0402_5%PR855 10K_0402_5%

GPU_VID1

RB751V-40_SOD323-2

PR870

@PR870

@

100K_0402_5%

1 2 1 2

PR869 0_0402_5%

0_0402_5%

PC836

PR822

8 7 6 5

GPU_VID2

PC866

PR846

0_0402_5%

1 2

12

PC874

PR834

11K_0402_1%

B

1 2 3

10U_0805_10V6K

PQ807TPC8A03-H_SO8PQ807TPC8A03-H_SO8

4

12

PC870

0.1U_0603_25V7K

<23>

GPU_VID0

GPU_VID1

PR847

0_0402_5%

1 2

12

PC871

PC871 1U_0603_10V6K

1U_0603_10V6K

PR814

1 2

0_0402_5%

12

PC824

PC824 1U_0603_10V6K

1U_0603_10V6K

PR819 0_0402_5%@PR819 0_0402_5%@

1 2 1 2

PR866

0_0402_5%

PR850

1 2

11.3K_0402_1%

0.047U_0402_16V7-K

12

VSSSENSE_VGA <24>

VSUM+_VGA

12

PR828

2.61K_0402_1%

NTC_VGA

12

PH801

PH801 10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

Layout Note: Place near Phase1 Choke

B

+1.05VS +1.05VS_VGA

@

12

PC868

BOOT2_VGA BOOT2_2_VGA

PC869

1U_0603_10V6K

PR838

PR838 470_0603_1%

470_0603_1%

1 2

2N7002KW_SOT323-3@

13

D

S

PR804

0_0603_5%

PQ808

G

2

<23>

+5VS

GPU_IMON <42>

BOOT1_VGA

UGATE1_VGA

PHASE1_VGA

LGATE1_VGA

VSUM-_VGA

C

PJ806

2

112

JUMP_43X118@

PR851

PR851 0_0402_5%

0_0402_5%

1 2 1 2

PR849

@PR849

@

0_0402_5%

0.22U_0603_10V7K

12

+VGA_CORE

PR827

0_0603_5%

1 2

UGATE2_VGA

LGATE2_VGA

Under VGA Core

12

PC811

4.7U_0603_6.3V6M

12

PC825

4.7U_0603_6.3V6M

@

12

PC839

0.1U_0402_10V7K

BOOT1_1_VGA

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DGPU_PWROK# <46>

SUSP

PC805

12

PC812

PC813

4.7U_0603_6.3V6M

12

PC826

PC827

4.7U_0603_6.3V6M

12

PC840

PC841

0.1U_0402_10V7K

PC856

0.22U_0603_10V7K

1 2

SUSP <10,46,53>

5

PQ801

4

TPCA8065-H_PPAK56-8-5

123

PHASE2_VGA

PQ803

5

4

123

12

PC817

PC818

4.7U_0603_6.3V6M

12

PC831

4.7U_0603_6.3V6M

12

PC846

PC845

@0.1U_0402_10V7K

PQ804

4

PQ806

4

123

Compal Secret Data

PQ803

@4.7_1206_5%

123

TPCA8057-H_PPAK56-8-5

4.7U_0603_6.3V6M

@0.1U_0402_10V7K

5

123

5

123

@

TPCA8057-H_PPAK56-8-5

Deciphered Date

@4.7_1206_5%

PQ802

5

4

@

TPCA8057-H_PPAK56-8-5

12

PC816

PC815

PC814

4.7U_0603_6.3V6M

12

PC830

PC829

PC828

4.7U_0603_6.3V6M

12

PC844

PC843

PC842

0.1U_0402_10V7K

0.1U_0402_10V7K @0.1U_0402_10V7K

@0.1U_0402_10V7K

TPCA8065-H_PPAK56-8-5

5

PQ805

4

TPCA8057-H_PPAK56-8-5

2008/09/15 2012/07/11

C

PR807

+VGA_B+

PC801

0.1U_0402_25V6

12

SNUB2_VGA

12

@680P_0402_50V7K

PC852

PR830

12

PC802

2200P_0402_50V7K

PR808

VSUM+_VGA

PC809

12

PC853

0.1U_0402_25V6

2200P_0402_50V7K

12

SNUB1_VGA

12

PC865

@680P_0402_50V7K

12

3.65K_0805_1%

12

PC803

PC804

10U_0805_25V6K

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

12

PR809

10K_0402_1%

ISEN2_VGA

+VGA_CORE

1

PC819

2

22U_0805_6.3V6M

12

PC832

4.7U_0805_6.3V6K

+VGA_B+

12

PC854

PC855

10U_0805_25V6K

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

LF1_VGA

12

PR831

PR832

10K_0402_1%

3.65K_0805_1%

VSUM+_VGA

ISEN1_VGA

D

PJ801

2

112

JUMP_43X118@

PL803

1

4

V2N_VGALF2_VGA

3

2

12

PR810

1

1_0402_1%

VSUM-_VGA

2

B+

+VGA_COREP

1

+

PC808

PC807

2

330U_D2_2V_Y

Near VGA Core

12

PC820

PC821

PC822

47U_0805_4V6

22U_0805_6.3V6M

4.7U_0805_6.3V6K

12

Date: Sheet

12

PC833

1 2

Title

Size Document Number Rev

PC835

PC834

4.7U_0805_6.3V6K

PL804

4.7U_0805_6.3V6K

PJ802

2

JUMP_43X118@

JUMP_43X118@ PJ803

PJ803

2

JUMP_43X118@

4

V1N_VGA

3

12

PR833

PR833 1_0402_1%

1_0402_1%

VSUM-_VGA

Compal Electronics, Inc.

PWR - VGA_COREP

LA-7984P

D

112

+VGA_CORE+VGA_COREP

112

+VGA_COREP

1

+

PC860

PC861

2

330U_D2_2V_Y

of

54 60Tuesday, December 06, 2011

of

54 60Tuesday, December 06, 2011

of

54 60Tuesday, December 06, 2011

0.1

5

PC901

PR901

FBA3

D D

TRBSTA#

1 2

10_0402_1%

PR902

1 2

1.21K_0402_1%

4700P_0402_25V7K

VCC_AXG_SENSE<10>

VSS_AXG_SENSE<10>

PC901

1 2

680P_0402_50V7K

12

PC905

FBA1

PR903

1 2

10.7K_0402_1%

+V1.05S_VCCP

C C

12

PC916

PR922

.1U_0402_16V7K

130_0402_1%

VR_SVID_DAT<9>

VR_SVID_ALRT#<9>

VR_SVID_CLK<9>

1 2

+V1.05S_VCCP

12

PR932

@PR932

@

75_0402_1%

VR_HOT#<42>

VSSSENSE<9>

VCCSENSE<9>

B B

A A

VGATE<16>

TRBST#

PR923

1 2

12

PC917

54.9_0402_1%

54.9_0402_1% PR926

PR926

1 2

PR944

1 2

10_0402_1%

.1U_0402_16V7K

0_0402_5%

VR_SVID_DAT1

+3VS

12

3P: 330p 2P: 1000p

FB_CPU3

PR947

1 2

1.21K_0402_1%

3P: 348 2P: 1.21K

PR955

1 2

1K_0402_1%

3P: 806 2P: 1K

CPU_B+

PR933

PR933 10K_0402_5%

10K_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

PC930

1 2

680P_0402_50V7K

DROOP

VR_ON<42>

PR929 1K_0402_1%PR929 1K_0402_1%

PR936

PR938

49.9_0402_1%

FB_CPU2

PC933

PR908

1 2

10_0402_1%

PR909

1 2

1K_0402_1%

+5VS

PR927

95.3K_0402_1%

1 2

PC921

12

PC923

PC923 1000P_0402_50V7K

1000P_0402_50V7K

PR942

1 2

12

9.53K_0402_1%

4700P_0402_25V7K

PC937

1 2

1000P_0402_50V7K

4

FBA2

PR937

1 2

0_0402_5%

PR954

1 2

0_0402_5%

1 2

2_0603_5%

1 2

2.2U_0603_10V7K

1 2

0_0402_5%

VSN

VSP

PR940

1 2

1K_0402_1%

FB_CPU1

680P_0402_50V7K

PR948

3P: 3.65K 2P: 9.53K

CSREFCSCOMP

PC907

1 2

330P_0402_50V7K

PR919

PC915

PR920

VR_ON_CPU

PR925

1 2

10K_0402_1%

12

0.01U_0402_25V7K

PC928

1 2

IMVP_IMON<42>

2P: 24K 1P: 24.9K

PR910

1 2

5.11K_0402_1%

2P: 21.5K 1P: 15.8K

1000P_0402_50V7K

6132_VCC

VR_SVID_DAT1 VR_SVID_ALRT# VR_SVID_CLK

VBOOT

ROSC_CPU VRMP VR_HOT# VGATE

DIFF_CPU

3P: 22p

2P: 10p

PR943

5.11K_0402_1%

3P: 6.04K 2P: 4.32K

3P: 2200p

2P: 3300p

3P: 23.7K

2P: 24.9K

PC908

1 2

10P_0402_50V8J

COMPA1

PC912

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

PC926

10P_0402_50V8J

COMP_CPU1

12

PC902

1 2

.1U_0402_16V7K

PR904

1 2

24.9K_0402_1%

PC909

1 2

3300P_0402_25V7K

1 2

DIFFA

58

61

59

60

PU901

PAD

VSPA

VSNA

VCC VDDBP VRDYA EN SDIO ALERT# SCLK VBOOT

NCP6132AMNR2G_QFN60_7X7

ROSC VRMP VRHOT# VRDY VSN VSP DIFF

FB

TRBST#

18

17

16

TRBST#

FB_CPU

COMP_CPU

12

PC929

12

1500P_0402_50V7K

PC935

PR950

1 2

24.9K_0402_1%

PUT COLSE TO VCORE Phase 1 Inductor

TRBSTA#

57

DIFFA

COMP

19

IMON

IMVP_IMON IMON

1 2

TRBSTA#

IOUT

FBA

COMPA

IMONAIMONA

56

54

55

FBA

IOUTA

COMPA

CSCOMP22CSP325CSREF24CSSUM

DROOP

ILIM

21

20

DROOP

ILIM_CPU

1 2

PR939 12.4K_0402_1%PR939 12.4K_0402_1%

CSCOMPCSCOMPCSCOMPCSCOMPCSCOMPCSCOMP

.1U_0402_16V7K

3

1 2

PC903

1200P_0402_50V7K

1 2

63.4K_0603_1%

PC911

PC911 1000P_0402_50V7K

1000P_0402_50V7K

1 2

PR914

CSCOMPA

1 2

15.8K_0402_1%

CSP1A

CSSUMA

DROOPA

ILIMA

51

53

50

48

47

52

49

ILIMA

CSP2A

CSREFA

CSSUMA

DROOPA

CSCOMPA

CSP1

CSP2

TSNS

23

27

29

26

28

TSENSETSENSE CSP2A

CSP1 CSP2 CSP3

3P: 21K 2P: 12.4K

PC932

PC932 1000P_0402_50V7K

1000P_0402_50V7K

1 2

PC934

1 2

1000P_0402_50V7K

1 2

NTC_PH201

PR952

1 2

75K_0402_1%

PH903

12

220K_0402_5%_ERTJ0EV224J

1 2

PC904

165K_0402_1%

PR912

1 2

.1U_0402_16V7K

TSENSEA

46

CSP1A

TSNSA

PWMA

BSTA

HGA SWA

LGA

BST2

HG2

SW2

LG2 PVCC PGND

LG1

SW1

HG1

BST1

DRVEN

PWM

30

PC924

1 2

CSSUM

PR905

330P_0402_50V7K

PR907

12

SWN1A

PC914

45 44 43 42 41

BST2

40 39 38 37

6132P_VCCP

36 35 34 33 32

BST1

31

PR934

1 2

41.2K_0402_1%

.1U_0402_16V7K

PC936

PC936 680P_0402_50V7K

680P_0402_50V7K

PR953

1 2

165K_0402_1%

75K_0402_1%

1 2

NTC_PH203

CSREFA <56>

1 2

26.1K_0402_1%

BSTA1

6132_PWM

CSREF <56>

3P: 1500p 2P: 1200p

PUT COLSE

12

TO GT

PH901

Inductor

220K_0402_5%_ERTJ0EV224J

CSREFA

1 2

CSP1A

PR918

2P: 36K 1P: 26.1K

PR921

1 2

2.2_0603_5%

HG1A <56> LG1A <56>

PR924

1 2

2.2_0603_5%

HG2 <56> LG2 <56>

PR930

1 2

0_0402_5%

LG1 <56> HG1 <56>

PR931

1 2

2.2_0603_5%

3P: 73.2K 2P: 41.2K

0.047U_0402_16V7K

CSREF

0.047U_0402_16V7K

CSREF

PR949

1 2

130K_0603_1%

PR951

1 2

130K_0603_1%

PC910

0.047U_0402_16V7K

0.047U_0402_16V7K PR913 6.98K_0402_1%PR913 6.98K_0402_1%

1 2

6132_PWMA

BSTA1_1

BST2_1

BST1_1

CSP2

12

PC927

CSP1

12

PC931

SWN1

SWN2

2

PC918

1 2

0.22U_0603_25V7K

PC919

1 2

0.22U_0603_25V7K

PC920

1 2

2.2U_0603_10V7K

PC922

1 2

0.22U_0603_25V7K

PR941

6.98K_0402_1%

1 2

PR960

6.98K_0402_1%

1 2

PR945

1 2

6.98K_0402_1%

PR961

6.98K_0402_1%

1 2

@PR960

@

@PR961

@

SWN1A <56>

+5VS

1 2

1K_0402_1%

2P: 1.65K 1P: 1K

SW1A <56>

SW2 <56>

SW1 <56>

SWN2 <56>

SWN1 <56>

PR915,PR946=200K(setting 113 degreeC) PR915,PR946=8.25K(setting 93 degreeC)

PR906

PC906

1 2

1000P_0402_50V7K

TSENSEA

12

PR915

200K_0402_1%

PUT COLSE TO V_GT HOT SPOT

CSREFACSCOMPA DROOPA

PH904

PH904 100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ

1 2

+5VS

CSP2A

12

PR928

PR928 0_0402_5%

0_0402_5%

Option for 1 phase GFX

+5VS

CSP3

TSENSE

12

PR946

200K_0402_1%

PUT COLSE TO VCORE HOT SPOT

12

1 2

PR935

PR935 0_0402_5%

0_0402_5%

PH902

PH902 100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ

Option for 2 phase CPU

1

2Phase: @ 1Phase: install

3Phase: @ 2Phase: install

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

PWR-CPU_CORE

LA-7984P

1

0.1

of

55 60Tuesday, December 06, 2011

5

4

3

2

1

CPU_B+ CPU_B+

5

PQ901

HG1<55>

D D

SW1<55>

LG1<55>

4

TPCA8065-H_PPAK56-8-5

123

5

PQ903

123

TPCA8057-H_PPAK56-8-5

12

PC938

PC939

10U_0805_25V6K

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

12

PR956

4.7_1206_5%

SNUB_CPU1

12

PC948

680P_0603_50V7K

12

PC940

1 2

12

PC941

0.1U_0402_25V6

PL902

12

2200P_0402_25V7K

4 3

V1N_CPU

B+

+VCC_CORE +VCC_CORE

PR958

12

10_0402_1%

PC947

220U_25V_M

SWN1 <55>

PL901

HCB4532KF-800T90_1812

1 2

1

+

2

CPU_B+

HG2<55>

SW2<55>

LG2<55>CSREF <55>

PQ902

4

5

TPCA8065-H_PPAK56-8-5

123

5

PQ904

TPCA8057-H_PPAK56-8-5

123

12

PC942

PC943

10U_0805_25V6K

PL903

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

PR957

4.7_1206_5%

PC949

680P_0603_50V7K

2

12

SNUB_CPU2

12

PC944

0.1U_0402_25V6

4 3

12

PC946

2200P_0402_25V7K

V2N_CPU

12

PR959

10_0402_1%

CSREF

12

SWN2 <55>

C C

QC 45W CPU VID1=0.9V IccMax=94A Icc_Dyn=66A Icc_TDC=52A R_LL=1.9m ohm OCP~110A

DC 35W CPU VID1=1.05V IccMax=53A Icc_Dyn=43A Icc_TDC=36A R_LL=1.9m ohm OCP~65A

CPU_B+

B B

5

PQ907

PQ909

4

5

4

HG1A<55>

SW1A<55>

LG1A<55>

A A

12

PC957

10U_0805_25V6K

TPCA8065-H_PPAK56-8-5

123

TPCA8057-H_PPAK56-8-5

123

12

PC958

10U_0805_25V6K

SNUB_GFX1

12

PC959

0.1U_0402_25V6

12

PR967

4.7_1206_5%

12

PC968

680P_0603_50V7K

12

PC960

2200P_0402_25V7K

PL905

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

2

4 3

V1N_GFX

+VCC_GFXCORE_AXG

PR971

12

10_0402_1%

CSREFA <55>

SWN1A <55>

QC 45W GT2 VID1=1.23V IccMax=46A Icc_Dyn=37A Icc_TDC=38A R_LL=3.9m ohm OCP~55A

5

4

DC 35W GT2 VID1=1.23V IccMax=33A Icc_Dyn=20.2A Icc_TDC=21.5A R_LL=3.9m ohm OCP~40A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR-CPU_CORE

Size Document Number Rev

C

Date: Sheet

LA-7984P

1

56 60Tuesday, December 06, 2011

of

0.1

5

4

3

2

1

+VCC_CORE

1

PC1

PC1 10U_0805_6.3VAM

10U_0805_6.3VAM

2

D D

1

PC6

PC6 10U_0805_6.3VAM

10U_0805_6.3VAM

2

1

PC2

PC2 10U_0805_6.3VAM

10U_0805_6.3VAM

2

1

PC7

PC7 10U_0805_6.3VAM

10U_0805_6.3VAM

2

1

PC3

PC3 10U_0805_6.3VAM

10U_0805_6.3VAM

2

1

PC8

PC8 10U_0805_6.3VAM

10U_0805_6.3VAM

2

1

PC4

PC4 10U_0805_6.3VAM

10U_0805_6.3VAM

2

1

PC9

PC9 10U_0805_6.3VAM

10U_0805_6.3VAM

2

+VCC_CORE +VCC_GFXCORE_AXG

1

PC5

PC5 10U_0805_6.3VAM

10U_0805_6.3VAM

2

1

PC10

PC10 10U_0805_6.3VAM

10U_0805_6.3VAM

2

1

@

PC11

PC11 10U_0805_6.3VAM

10U_0805_6.3VAM

2

+VCC_GFXCORE_AXG

@

22U_0805_6.3V6M

PC12

1

2

22U_0805_6.3V6M

PC13

1

2

@

22U_0805_6.3V6M

PC14

1

2

22U_0805_6.3V6M

1

2

PC15

22U_0805_6.3V6M

@

PC16

1

2

22U_0805_6.3V6M

PC17

1

2

22U_0805_6.3V6M

PC18

1

2

22U_0805_6.3V6M

PC19

1

2

+VCC_CORE

1

PC20

PC20 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC44

PC44 22U_0805_6.3V6M

22U_0805_6.3V6M

2

C C

1

PC61

PC61 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

@

PC69

PC69 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC21

PC21 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC45

PC45 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC62

PC62 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

@

PC70

PC70 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC22

PC22 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC46

PC46 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC63

PC63 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC71

PC71 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC23

PC23 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC47

PC47 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC64

PC64 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC72

PC72 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC24

PC24 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC48

PC48 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

@

PC65

PC65 22U_0805_6.3V6M

22U_0805_6.3V6M

2

22U_0805_6.3V6M

PC36

1

2

330U_D2_2VM_R6M

1

@

+

2 3

22U_0805_6.3V6M

@

1

2

1

PC57

2 3

PC37

+

1

2

22U_0805_6.3V6M

PC38

330U_D2_2VM_R6M

PC58

22U_0805_6.3V6M

PC39

1

2

330U_D2_2VM_R6M

1

@

+

2 3

22U_0805_6.3V6M

1

2

PC59

PC40

1

+

2 3

22U_0805_6.3V6M

PC41

1

2

330U_D2_2VM_R6M

PC60

22U_0805_6.3V6M

PC42

1

2

22U_0805_6.3V6M

PC43

1

2

Below is 458544_CRV_PDDG_0.5 Table 5-8.

5 x 22 µF (0805)

Socket Bottom

5 x (0805) no-stuff sites

7 x 22 µF (0805)

Socket Top

2 x (0805) no-stuff sites

+V1.05S_VCCP

PC27

22U_0805_6.3V6M

1

PC28

2

22U_0805_6.3V6M

1

@

PC49

2

+V1.05S_VCCP

22U_0805_6.3V6M

1

PC29

2

22U_0805_6.3V6M

1

PC50

2

22U_0805_6.3V6M

1

PC30

2

22U_0805_6.3V6M

1

PC51

2

1

+

2 3

PC31

PC52

330U_D2_2VM_R9M

@

PC66

22U_0805_6.3V6M

1

PC32

2

22U_0805_6.3V6M

1

PC53

2

1

2

1

2

1

+

2 3

22U_0805_6.3V6M

1

@

PC25

2

22U_0805_6.3V6M

1

@

PC26

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

PC33

2

22U_0805_6.3V6M

1

@

PC54

2

330U_D2_2VM_R9M

PC67

@

PC34

PC55

22U_0805_6.3V6M

1

@

PC35

2

22U_0805_6.3V6M

1

PC56

2

330U_D2_2VM_R9M

1

+

2 3

PC68

+VCC_CORE

1

+

PC73

330U_D2_2VM_R6M

B B

A A

2 3

1

+

PC77

330U_D2_2VM_R6M

2 3

1

+

330U_D2_2VM_R6M

2 3

5

PC74

1

+

PC78

330U_D2_2VM_R6M

2 3

1

+

PC75

@+PC75

@

330U_D2_2VM_R6M

2 3

1

+

PC76

@+PC76

@

330U_D2_2VM_R6M

2 3

Security Classification

2008/09/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PWR - PROCESSOR DECOUPLING

LA-7984P

1

of

57 60Tuesday, December 06, 2011

of

57 60Tuesday, December 06, 2011

of

57 60Tuesday, December 06, 2011

0.1

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

add PR865 for ISL62883 one phase solution and unpop for two phase solution.

1

D D

unpop PR315,PR316 for SMBus SPEC.

2

P54 add PR865

unpop PR315,PR316

P49

2011.08.29 DVT

2011.08.29

DVT

3

delet PSI#_VGA for NV chip.

P54

2011.10.14

DVT2

4

5

6

7

8

C C

9

10

11

12

13

14

B B

15

16

17

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/06 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

LA-7984P

58 60Tuesday, December 06, 2011

1

0.1

of

5

4

COMPAL CONFIDENTIAL

3

2

1

MODEL NAME: PCB NAME:

D D

REVISION: DATE:

AC MODE

BATT MODE

C C

A1

VIN

BATT

B1

V

PU301

V

Power Sequence Block Diagram LA-7981P

2011/07/13

A3

B4

+3VALW +5VALW

B5

A5

V

B7

A2

PU401

V

B+

B2

V

B+

V

PQ2

EC

VV

A5

A4

ON/OFF

B7

B6

V

B3

51ON#

EC_ON

10

PCH_PWROK

+3V_PCH

7

+5V_PCH

4

5

SYSON#

3

V

PCH

VV

10

PCH_PWROK

V

PM_DRAM_PWRGD

H_CPUPWRGD

PLT_RST#

SYS_PWROK

15

11

VGATE

14

V

12

CPU

V

16

SVID

13

V

6

+1.5V

V

PU501

8

DGPU_PWR_EN

DGPU_PWROK

3

V

3

V

PCH_RSMRST#_R

PBTN_OUT#

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_SUS#

V

SYSON

SUSP#,SUSP

PU601

B B

V

+VCC_SA

PU702

V

+V1.05S

PU602

V

+V1.05S_VCCP

U38

V

+5VS

U39

V

+3VS

Q8

VV

+1.5VS

(DIS)

8a

(DIS)

8b

V

DGPU

PU701 +0.75VS

13 SVID

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Power sequence

LA-7984P

1

59 60Tuesday, December 06, 2011

0.1

of

59 60Tuesday, December 06, 2011

PU901 +VCC_CORE

V

3

8a

2011/06/15 2012/07/11

SA_PGOOD

VR_ON

A A

5

4

9

14

VGATE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Version change list (P.I.R. List) Page 1 of 2 for HW PIR

Reason for change PG# Modify List Date PhaseItem

1

GPU 13M GPU Device loss (Pcie lan x8 issue)

10

11

12

13

14

15

16

17

18

19

20

21

22

1

2

HDD no function 40 Add R550

3

10/100 lan no function & change to overclocking mode 37 ADD R1372 ; DEL R31

For DGPU_PWROK leakage issue.(Let timing +5VS > +3VS)

4

For S3 can't wake up 10

5

Can unstuff RV66 for N13P-GL & as NV DG 27 RV66 change to N13M@

6

GPU N13P-GL QS sample change strap RV94 change from 45.3K to 10K32

7

8

PCH 25Mhz for vender crystal test report change CL to 12pF 15 C196;C197

GPU 27Mhz for vender crystal test report change CL to 15pF 23 CV37;CV38

9

EC_LID_OUT# internal PD 20K, follow ORB change R230 from 10k to 1K 19 R230

For GPIO70;GPIO71 voltage level issue ( internal Pull High 20k ) 19 R705;R706 Change from 10K to 200K

for DVT board ID Change R695 from 33k to 18k 42 R695

LAN Surge test fail change P/N from SP050006E00 to SP050006W00 27 T1;T2

Del ODD Power Control function component 40 R568;Q100;R675;C607;Q99

AO4430L(SB000007O10)EOL Change to AO4304 (SB00000RV00) 46 U49

Del (PCH AUX Power) Reserve component no use 46 C780;C781;C782;C783;R778;Q120;U40

PCH(U4) P/N Change from SA00004NQ30 to SA00004NQ80 14 U4

NV-GPU (U65)P/N change N13M from SA00004V000 to SA00004V010 N13P Keep SA000051A00

EXT USB 3.0 IC PCIE_WAKE# ; CLKREQ_USB30# leakage on S4 45 Swap Q125;Q121 pin1 & pin3

No function DEL R76945

add LAN LDO mode function 37;38 ADD R65;R596;R1449;R1380

USB_OC0# Share with USB_OC4# due to same power switch

D D

C C

B B

8 Add R43 DVT

DVT

46 Change C726 from 0.1uF to 0.01uF

Change R56 from 15K to 4.7K change R885 from 0 ohm to 15K

DVT

23 U65

DVT

18 short USB_OC0#;USB_OC4# ; del R267 DVT

23

A A

Add Capsensor B/D Conn. For best buy use

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

42 ADD JCAP1 Conn.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

DVT

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

HW-PIR1

LA-7984P

1

60 60Tuesday, December 06, 2011

0.1

of

5

4

3

2

Version change list (P.I.R. List) Page 2 of 2 for HW PIR

Reason for change PG# Modify List Date PhaseItem

1

D D

24

25

26

27

L1 change to 1 ohm R 20 L1 change to R footprint

Reserve 0 ohm for CMOS Camera shake 33 add R296 0 ohm

Reserve 0 ohm for U49 MOS VGS 20V will burn out issue 46 add R784 0 ohm

For HDD +5VS Power plant del C601; change C598 pin1 power name for good power plant

40 change from +5VS to +5V_HDD ;DEL C601

DVT

28

29

C C

30

31

32

33

34

B B

35

36

37

For Audio jack support APPLE and NOKIA function Reserve 43 add R684;R685;R688;R686 0ohm R

10,20

For standard part cost down change 10uF 0805 type to 0603 type

change Crystal foot print follow standard parts from 5032 to 3225 package 15;23;

change 0ohm to short-pad (R0402_0ohm)

21,33 37,39 40,46

37 7;8;

10;15 16;20; 33;36; 40;43

C124;C125;C126;C127;C130;C221;C215;C395; C231;C519;C937;C953;C954;C591;C608;C602; C720;C721;C723;C724;C782;C783;C717;C718; C856;C852;C851;C853

Y2;Y6;YV1

R40;R60;R77;R144;R190;R193;R198;R181;R185; R265;R538;R498;R500;R583;R614

Reserve BT_DISABLE (GPI022) for combo card(BT+WLAN) 19 ADD R892;R897

U35;U36 Change footprint without thermal PAD type 44;45 U35;U36

PU 10K with 3V3 on N13P-GL/ for CEC signal 24 RV230

VGA_GPIO3;VGA_GPIO16 change connect DPRSLPVR_VGA to PSI#_VGA 23;54 RV113;RV114

Fix VGA power on CLKREQ has drop (QV2 gate add 0.1uF)

和

LED5

LED2 Location sawp ; Location name D9 change to LED6

23

43 LED2;LED5;LED6

CV42

DVT

For Lan surge fail add 0 ohm on MDO2-;MDO2+;MDO3-;MDO3+ 38 R304;R305;R306;R307

38

Change UV2 PN from SA007080B90 to SA00000OH00 23 UV2 DVT09/28

39

09/29 DVT

10/03 DVT

10/04

Compal Electronics, Inc.

HW-PIR2

3

14Change 2M BIOS ROM from SA00003FO00 to SA00003FO10 U6

45

43

U32

R689 (@),R690

47~58

Compal Secret Data

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

40

41

42

A A

43

Correct PCIE_PRX_DTX_P4/N4 of U32 (SWAP)

Reserve +5VS to JCR1, add R689 ,R690

Update Power sheet of 1003 version

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DVT

LA-7984P

1

0.1

of

61 60Tuesday, December 06, 2011

Compal LA-7984P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual