Compal LA-7984P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

QIWG5/QIWG6 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH

nVIDIA N13X

2011-11-08

3 3

LA-7984P

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-7984P

E

160Tuesday, December 06, 2011

0.1

of

A

Compal confidential

File Name : QIWG5/QIWG6

Page23‐32

B

C

D

ZZZ

LA7981

DA_PCB

DA80000Q000

E

QIWG5

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B

1 1

nVIDIA N13M-GE nVIDIA N13P-GL

Intel

Ivy Bridge

VRAM 128*16

DDR3*8

PCI-E x16

Socket-rPGA988B

37.5mm*37.5mm

HDMI Connector

CRT

2 2

Connector LVDS

Connector

Page35

Page34

Page33

100MHz

2.7GT/s

FDI *8

Intel

Panther Point

HM75 / HM76

Page5‐11

Dual Channel DDR3 1066MHz(1.5V) DDR3 1333MHz(1.5V) DDR3 1600MHz(1.5V)

DMI *4

AZALIA

FCBGA 989

USB3.0 *2(Left)

Option

Page45

PCI-E x1 *6

USB3.0

Renesas

uPD720202

3 3

Realtek

RTL8111F(GLAN) RTL8105E(10/100)

Page37

SPIROM BIOS

Page14

25mm*25mm

Page14‐22

LPC BUS

Page42

EC

ENE KB9012

USB2.0 *14

SATA *6

DDR3 SO-DIMM *2

BANK 0, 1, 2, 3

Up to 8GB

Page12‐13

Audio Codec Conexant

CX20671-21Z

Page41

Camera Conn. BlueTooth Conn. Mini Card Slot *1 Card Reader

Reltek

RTS5178 for SDR50 SDXC/MMC

2 channel speaker Int. MIC x1 Audio Jacks

Page33

Page40

Page36

Page43

Page41

Page43

QIWG6

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B LS7984P LED/B LS7985P ODD/B

USB2.0 *2(Right) RJ-45 Connector

PCI Express

Mini Card Slot *1

WLAN

4 4

Page38

Page36

PCI-E(WLAN)

Touch Pad Int. KBD

Page43

Thermal Sensor

EMC1403

Page39

Page43

USB2.0 *2(Left)

SATA HDD SATA ODD

Page43;44

Page45

Page40

(Port 0/Port 1 support SATA3)

www.schematic-x.blogspot.com

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-7984P

E

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Voltage Rails

power

State

S0

S3

S5 S4/AC

Device

Smart Battery

plane

Address

0001 011X b

+B

O

O O O

X

+5VALW

+3VALW

O

O O

X XX X

+1.5V

EC SM Bus2 address

Device

Thermal Sensor F75303M

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

EC SM Bus1 address

PCH SM Bus address

Device Address

DDR DIMM0

3 3

DDR DIMM2

1001 000Xb 1001 010Xb

NV-GPU SM Bus address

Device Address

Internal thermal sensor

1001 111Xb (0x9E)

B

+5VS +3VS +1.5VS +V1.05S_VCCP +VCC_CORE +VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS +1.05VS

Board ID

OO

O

X XX X

X

Address

1001_101xb

USB Port Table

EHCI1

USB3.0

EHCI2

0 1 2 3 4 5 6 7

USB 2.0 Port

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

C

PCB Revision

0.1

3 External USB Port

0

USB Port (Right Side CR-BD)

1 2

USB Port (Left Side)

3

USB Port (Left Side)

4 5

Camera

6 7 8

USB/B (Right Side USB-BD)

9

10

Mini Card(WLAN)

11

Card Reader

12 13

Blue Tooth

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

Board ID / SKU ID Table for AD channelBOARD ID Table

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

USB3.0 USB3.0

D

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

0

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGHHIGHHIGH

LOW

HIGH

LOWLOWLOW

HIGH

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

BOM Structure Table

BTO Item BOM Structure

HDMI HDMI@ Interna-Intel-USB3.0 IU3@ External-NEC-USB3.0 EU3@ Blue Tooth BT@ Connector ME@ 45 LEVEL 45@ 10/100 LAN 8162@ GIGA LAN GIGA@ LAN LDO Mode LDO@ LAN Switch mode SWR@ Cameara CMOS@ For QIWG5 (14") 14@ For QIWG6 (15") 15@ Unpop

ON

OFF

ON

OFF

ON

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

N13P@ GPU:N13P-GL N13M@GPU:N13M-GE

@

E

ON ON

ON

OFF

max

LOW

OFF

Porject Phase

G-series

MP

G-series

PVT

G-series

DVT

G-series

EVT

Y-series

EVT

Y-series

DVT

Y-series

PVT

Y-series

MP

SMBUS Control Table

X X

V

+3VS

X

WLAN WWAN

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2

4 4

SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012 SODIMM

X V

+3VALW

X X X

V

+3VS

A

X X X

X

X X

V

+3VS

X XX

V

+3VS

X

B

Thermal Sensor

X X X XX

V

+3VS

PCH

X

V

+3VS

X X XXX

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

LA-7984P

Date: Sheet

Compal Electronics, Inc.

Notes List

of

360Tuesday, December 06, 2011

E

0.1

5

4

3

2

1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails (N13x GPIO)

GPIO I/O ACTIVE Function Description GPIO0

D D

GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10

C C

GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19

B B

+1.05VS_VGA

OUT GPU VID4-

OUT OUT OUT OUT OUT OUT I/O OUT OUT

IN OUT OUT IN OUT IN IN IN

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

-

GPU VID3OUT

H

Panel Back-Light brightness(PWM capable)

H

Panel Power Enable

H

Panel Back-Light On/Off (PWM) GPU VID1

GPU VID2

-

N/A

-

Thermal Catastrophic Over Temperature

-

Thermal Alert

-

Memory VREF Control GPU VID0-OUT AC Power Detect Input GPU VID5-

N/A

Hot plug detect for IFP link C

N/A N/A

Hot Plug Detect for IFPE

N/A

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

(10K pull low)

Performance Mode P0 TDP at Tj = 102 C* (GDDR3)

GPU Mem

Products

N13P-GL 64bit 1GB GDDR3

Physical Strapping pin ROM_SCLK

(4) (1,5) (6) (W) (W) (MHz)

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

ROM_SI ROM_SO FB[0] STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

NVCLK /MCLK NVVDD

TBD TBD

Power Rail

+3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA

(V) (A) (W) (A) (W)

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] SOR3_EXPOSED

RESERVED PCIE_SPEED_

FBVDD

Logical Strapping Bit2 SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

FBVDDQ (GPU+Mem) (1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

Device ID

N13P-GL (28nm)

N13M-GE (28nm)

GPU STRAP2 STRAP1 STRAP0

N13P-GL N13M-GE

???

FB Memory (GDDR3)

Samsung 2500MHz

Hynix 2500MHz

Samsung 2500MHz

2500MHz

K4G10325FG-HC04

H5GQ1H24BFR-T2C

K4G20325FG-HC04

H5GQ2H24MFR-T2CHynix

ROM_SO

32Mx32

32Mx32 PD 15K

PD 10K PU 20K

64Mx32

ROM_SCLK ROM_SI

PD 15K

PD 15K PD 35KPU 20KPD 10K PD 20K PU 45K

PCI Express (1.05V)

Logical Strapping Bit1

SLOT_CLK_CFG RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

I/O and PLLVDD

Logical Strapping Bit0

PEX_PLL_EN_TERM RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

SOR0_EXPOSED

PCIE_MAX_SPEED DP_PLL_VDD33V

PD 20KPD 10K PU 45K

PU 20K

X76

I/O and PLLVDD

PD 35K

Other (3.3V)(1.05V)(1.8V)

PU 45K

1. all power rail ramp up time should be larger than 40us

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

A A

1.all GPU power rails should be turned off within 10ms

5

Tpower-off <10ms

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA Notes List

VGA Notes List LA-7984P

LA-7984P

460Tuesday, December 06, 2011

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5

D D

DMI_CRX_PTX_N0<16> DMI_CRX_PTX_N1<16> DMI_CRX_PTX_N2<16> DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16> DMI_CRX_PTX_P1<16> DMI_CRX_PTX_P2<16> DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16> DMI_CTX_PRX_N1<16> DMI_CTX_PRX_N2<16> DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16> DMI_CTX_PRX_P1<16> DMI_CTX_PRX_P2<16> DMI_CTX_PRX_P3<16>

C C

+V1.05S_VCCP

12

R7

24.9_0402_1%

B B

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

FDI_CTX_PRX_N0<16> FDI_CTX_PRX_N1<16> FDI_CTX_PRX_N2<16> FDI_CTX_PRX_N3<16> FDI_CTX_PRX_N4<16> FDI_CTX_PRX_N5<16> FDI_CTX_PRX_N6<16> FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16> FDI_CTX_PRX_P1<16> FDI_CTX_PRX_P2<16> FDI_CTX_PRX_P3<16> FDI_CTX_PRX_P4<16> FDI_CTX_PRX_P5<16> FDI_CTX_PRX_P6<16> FDI_CTX_PRX_P7<16>

FDI_FSYNC0<16> FDI_FSYNC1<16>

FDI_LSYNC0<16> FDI_LSYNC1<16>

4

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

eDP_HPD

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

FDI_INT<16>

EDP_COMP

DMI

Intel(R) FDI

eDP

3

+V1.05S_VCCP

12

R1

24.9_0402_1%

PEG_COMP

PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10

PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0

PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0

PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0

PCIE_CRX_GTX_N[0..15] <23>

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

PCIE_CRX_GTX_P[0..15] <23>

C1 0.22U_0402_10V6KC1 0.22U_0402_10V6K

1 2

C2 0.22U_0402_10V6KC2 0.22U_0402_10V6K

1 2

C3 0.22U_0402_10V6KC3 0.22U_0402_10V6K

1 2

C4 0.22U_0402_10V6KC4 0.22U_0402_10V6K

1 2

C5 0.22U_0402_10V6KC5 0.22U_0402_10V6K

1 2

C6 0.22U_0402_10V6KC6 0.22U_0402_10V6K

1 2

C7 0.22U_0402_10V6KC7 0.22U_0402_10V6K

1 2

C8 0.22U_0402_10V6KC8 0.22U_0402_10V6K

1 2

C9 0.22U_0402_10V6KC9 0.22U_0402_10V6K

1 2

C10 0.22U_0402_10V6KC10 0.22U_0402_10V6K

1 2

C11 0.22U_0402_10V6KC11 0.22U_0402_10V6K

1 2

C12 0.22U_0402_10V6KC12 0.22U_0402_10V6K

1 2

C13 0.22U_0402_10V6KC13 0.22U_0402_10V6K

1 2

C14 0.22U_0402_10V6KC14 0.22U_0402_10V6K

1 2

C15 0.22U_0402_10V6KC15 0.22U_0402_10V6K

1 2

C16 0.22U_0402_10V6KC16 0.22U_0402_10V6K

1 2

C17 0.22U_0402_10V6KC17 0.22U_0402_10V6K

1 2

C18 0.22U_0402_10V6KC18 0.22U_0402_10V6K

1 2

C19 0.22U_0402_10V6KC19 0.22U_0402_10V6K

1 2

C20 0.22U_0402_10V6KC20 0.22U_0402_10V6K

1 2

C21 0.22U_0402_10V6KC21 0.22U_0402_10V6K

1 2

C22 0.22U_0402_10V6KC22 0.22U_0402_10V6K

1 2

C23 0.22U_0402_10V6KC23 0.22U_0402_10V6K

1 2

C24 0.22U_0402_10V6KC24 0.22U_0402_10V6K

1 2

C25 0.22U_0402_10V6KC25 0.22U_0402_10V6K

1 2

C26 0.22U_0402_10V6KC26 0.22U_0402_10V6K

1 2

C27 0.22U_0402_10V6KC27 0.22U_0402_10V6K

1 2

C28 0.22U_0402_10V6KC28 0.22U_0402_10V6K

1 2

C29 0.22U_0402_10V6KC29 0.22U_0402_10V6K

1 2

C30 0.22U_0402_10V6KC30 0.22U_0402_10V6K

1 2

C31 0.22U_0402_10V6KC31 0.22U_0402_10V6K

1 2

C32 0.22U_0402_10V6KC32 0.22U_0402_10V6K

1 2

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

2

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0

PCIE_CTX_GRX_N[0..15] <23>

PCIE_CTX_GRX_P[0..15] <23>

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

Compal Secret Data

3

Deciphered Date

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

2

Date: Sheet

560Tuesday, December 06, 2011

1

0.1

of

5

D D

+V1.05S_VCCP

12

R9

62_0402_5%

H_PROCHOT#<42,48>

C C

H_CPUPWRGD<19>

H_PROCHOT#

R260_0402_5% R260_0402_5%

1 2

@ C549

@

100P_0402_50V8J

EMI Reserve

C549

H_PM_SYNC<16>

R27

1

10K_0402_5%

1 2

2

4

JCPU1B

H_SNB_IVB#<19>

H_PROCHOT#_R

R22

H_CPUPWRGD_R

PM_DRAM_PWRGD_R

BUF_CPU_RST#

H_CATERR#

H_PM_SYNC_R

T48T48

H_PECI<19,42>

R15

56_0402_5%

1 2

H_THRMTRIP#<19>

1 2

0_0402_5%

R29

1 2

130_0402_5%

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

V8

AR33

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

3

A28

BCLK

A27

BCLK#

PRDY#

PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

A16 A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28

TDI

AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

2

R10;R11 put on U4 side

0_0402_5%

CLK_CPU_DMI_R CLK_CPU_DMII#_R

R12 1K_0402_5%R12 1K_0402_5% R13 1K_0402_5%R13 1K_0402_5%

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

12 12

R16 140_0402_1%R16 140_0402_1% R17 25.5_0402_1%R17 25.5_0402_1% R18 200_0402_1%R18 200_0402_1%

0_0402_5%

R10

1 2 1 2

R11

0_0402_5%

H_DRAMRST# <7>

12 12 12

+V1.05S_VCCP

DDR3 Compensation Signals

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TDO XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

T97T97 T98T98

R28 1K_0402_5%R28 1K_0402_5%

12

T49T49 T90T90 T91T91 T92T92 T93T93 T94T94 T95T95 T96T96

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

XDP_TMS

R20 51_0402_5%R20 51_0402_5%

XDP_TDI

R21 51_0402_5%R21 51_0402_5% R23 51_0402_5%@R23 51_0402_5%@

XDP_TCK

R24 51_0402_5%R24 51_0402_5%

XDP_TRST#

R25 51_0402_5%R25 51_0402_5%

+3VS

1

+V1.05S_VCCP

12 12 12

12 12

PU/PD for JTAG signals

TYCO_2013620-2_IVY BRIDGE

+3VALW

1

C33

0.1U_0402_16V4Z

B B

SYS_PWROK<16>

A A

R880

@R880

@

1 2

0_0402_5%

R161

1 2

+3VS

10K_0402_5%

PM_DRAM_PWRGD<16>

RUN_ON_CPU1.5VS3#<10>

5

2

U1

5

1

P

B

2

A

G

74AHC1G09GW_TSSOP5

3

PM_SYS_PWRGD_BUF

4

O

2

G

+1.5V_CPU_VDDQ

12

@

R33

R33 39_0402_5%

39_0402_5%

13

D

Q1

@

Q1

@

2N7002H_SOT23-3

S

12

R30

R30 200_0402_5%

200_0402_5%

BUF_CPU_RST#

4

TYCO_2013620-2_IVY BRIDGE

12

R35

@R35

@

0_0402_5%

Buffered reset to CPU

+3VS

+V1.05S_VCCP

0.1U_0402_16V4Z

12

R32

75_0402_5%

R34

43_0402_1%

1 2

BUFO_CPU_RST#

SN74LVC1G07DCKR_SC70-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C34

2

5

U2

4

1

P

NC

Y

PCH_PLTRST#

2

A

G

3

2011/06/15 2012/07/11

3V

PCH_PLTRST# <18>

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

1

of

660Tuesday, December 06, 2011

0.1

5

JCPU1C

DDR_A_D[0..63]<12>

D D

C C

B B

DDR_A_BS0<12> DDR_A_BS1<12> DDR_A_BS2<12>

DDR_A_CAS#<12> DDR_A_RAS#<12> DDR_A_WE#<12>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10 AF10

F10 G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8

AE8 AD9 AF9

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9

F9

F7 G8 G7

K4

K5

K1

J1

J5

J4

J2

K2 M8

N8 N7

M9 N9 M7

V6

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

4

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

RSVD_TP[1]

AA4

RSVD_TP[2]

W9

RSVD_TP[3]

AB3

RSVD_TP[4]

AA3

RSVD_TP[5]

W10

RSVD_TP[6]

AK3

SA_CS#[0]

AL3

SA_CS#[1]

AG1

RSVD_TP[7]

AH1

RSVD_TP[8]

AH3

SA_ODT[0]

AG3

SA_ODT[1]

AG2

RSVD_TP[9]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

RSVD_TP[10]

DDR SYSTEM MEMORY A

M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12>

M_ODT0 <12> M_ODT1 <12>

3

DDR_B_D[0..63]<13>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_BS0<13> DDR_B_BS1<13> DDR_B_BS2<13>

DDR_B_CAS#<13> DDR_B_RAS#<13> DDR_B_WE#<13>

DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AJ11

AH11

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA10

D10

K10

AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9

AT8 AT9

AR8

AA9 AA7

AB8 AB9

J10

C9

A7

C8

A9

A8 D9 D8 G4

F4

F1 G1 G5

F5

F2 G2

J7

J8

K9

J9

K8

K7 M5 N4 N2 N1 M4 N5 M2 M1

R6

JCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

RSVD_TP[17] RSVD_TP[18]

RSVD_TP[19] RSVD_TP[20]

DDR SYSTEM MEMORY B

1

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13>

M_ODT2 <13> M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

TYCO_2013620-2_IVY BRIDGE

DRAMRST_CNTRL <10>

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-7984P

1

760Tuesday, December 06, 2011

of

0.1

TYCO_2013620-2_IVY BRIDGE

+1.5V

R36

@R36

@

0_0402_5%

1 2

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

Q2

G

LBSS138LT1G_SOT-23-3

2

1

C35

0.047U_0402_16V4Z

2

H_DRAMRST#<6>

R39

4.99K_0402_1%

A A

5

DRAMRST_CNTRL

12

R37

1K_0402_5%

R38

R38 1K_0402_5%

1K_0402_5%

1 2

Eiffel used 0.01u Module design used 0.047u

4

DDR3_DRAMRST# <12,13>

DRAMRST_CNTRL_PCH<15>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R40 0_0402_5%

3

R02

@

DRAMRST_CNTRL

Compal Secret Data

2011/06/15 2012/07/11

Compal Secret Data

5

4

3

2

1

CFG Straps for Processor

CFG2

D D

JCPU1E

AK28

CFG[0]

AK29

CFG2 CFG4

CFG5 CFG6 CFG7

+VCC_GFXCORE_AXG

+VCC_CORE

R252

49.9_0402_1%

R253

49.9_0402_1%

C C

49.9_0402_1%

1 2

R82 100_0402_1%@R82 100_0402_1%@

1 2

R88 100_0402_1%@R88 100_0402_1%@

1 2

VCC_AXG_VAL_SENSE

VSS_AXG_VAL_SENSE

VCC_VAL_SENSE

VSS_VAL_SENSE

Need PWR add new circuit on 1.05V(refer CRB)

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

Check

R255

49.9_0402_1%

INTEL 12/28 recommand to add RC120, RC121, RC122, RC123

B B

Please place as close as JCPU1

R257

49.9_0402_1%

1 2

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

CFG

VCC_DIE_SENSE

VSS_DIE_SENSE

RESERVED

RSVD_NCTF10

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

Interl request AH26 short GND check on EVT phase

RSVD28 RSVD29 RSVD30 RSVD31

RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9

RSVD51 RSVD52

BCLK_ITP

BCLK_ITP#

KEY

AH27 AH26

L7 AG7 AE7 AK2

W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AN35 AM35

AT2 AT1 AR1

B1

R60 0_0402_5%

1 2

R02

@

PEG Static Lane Reversal - CFG2 is for the 16x

T13PAD T13PAD

CFG2

*

Display Port Presence Strap

CFG4

*

N13M@ R43

N13M@

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

R41

R41 1K_0402_1%

1K_0402_1%

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

1K_0402_1%

12

R42

@ R42

@

1K_0402_1%

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6 CFG5

CFG7

12

R44

@R44

12

@R45

@

1K_0402_1%

R45 1K_0402_1%

1K_0402_1%

R43

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-7984P

1

860Tuesday, December 06, 2011

0.1

of

5

POWER

+VCC_CORE

JCPU1F

POWER

QC=94A DC=53A

D D

C C

B B

A A

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CORE SUPPLY

4

8.5A

AH13

VCCIO1

AH10

VCCIO2

AG10

VCCIO3

AC10

VCCIO4

Y10

VCCIO5

U10

VCCIO6

P10

VCCIO7

L10

VCCIO8

J14

VCCIO9

J13

VCCIO10

J12

VCCIO11

J11

VCCIO12

H14

VCCIO13

H12

VCCIO14

H11

VCCIO15

G14

VCCIO16

G13

VCCIO17

G12

VCCIO18

F14

VCCIO19

F13

VCCIO20

F12

VCCIO21

F11

VCCIO22

E14

VCCIO23

E12

VCCIO24

E11

VCCIO25

D14

VCCIO26

D13

VCCIO27

D12

VCCIO28

D11

VCCIO29

C14

VCCIO30

C13

VCCIO31

PEG AND DDR

VCC_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VSS_SENSE

C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

+V1.05S_VCCP

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

3

1

C99

0.1U_0402_10V6K

R47 43_0402_5%R47 43_0402_5%

1 2

R48 0_0402_5%R48 0_0402_5%

1 2

R49 0_0402_5%R49 0_0402_5%

1 2

R50 130_0402_5%R50 130_0402_5%

2

12

+V1.05S_VCCP

12

R46

R46 75_0402_5%

75_0402_5%

+V1.05S_VCCP

VR_SVID_CLK

0.1uF on power side

2

series-resistors close to VR

VR_SVID_ALRT# <55> VR_SVID_CLK <55> VR_SVID_DAT <55>

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

Trace Impedance =27-33 ohm Trace Length Matc < 25 mils

VCCSENSE_R VSSSENSE_R

VSS_SENCE 100ohm +-1% pull-down to GND near processor

R52 0_0402_5%R52 0_0402_5%

1 2

R53 0_0402_5%R53 0_0402_5%

1 2

VSSIO_SENSEVSSIO_SENSE_L

R74

1 2

10_0402_1%

@

R74 & R79 put together

VSSIO_SENSE_L <53>

R79

10_0402_1%

VCCIO_SENSE <52,53>

+V1.05S_VCCP

12

R66

1 2

100_0402_1%

@R66

@

+VCC_CORE

12

R51

R51 100_0402_1%

100_0402_1%

R54

R54 100_0402_1%

100_0402_1%

VCCSENSE <55> VSSSENSE <55>

1

Security Classification

TYCO_2013620-2_IVY BRIDGE

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

2

Date: Sheet

960Tuesday, December 06, 2011

1

0.1

of

5

4

3

2

1

+1.5V +1.5V_CPU_VDDQ

R668

SUSP<46,53,54>

@ R667

@

100K_0402_5%

R580_0402_5% @ R580_0402_5%@

R590_0402_5% @ R590_0402_5% @

R69

0_0805_5%

1 2

R667

2

G

+3VALW

D D

CPU1.5V_S3_GATE<42>

SUSP#<25,42,46,51,52,53,54>

C C

B B

1 2

+1.8VS

1 2

0_0402_5%

+VSB

12

RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3

13

D

Q7

@

Q7

@

2N7002_SOT23

S

Check

10U

C154

22U_0805_6.3V6M@C154

22U_0805_6.3V6M

1

@

2

22U_0805_6.3V6M@C345

22U_0805_6.3V6M

C130

10U_0603_6.3V6M

C130

10U_0603_6.3V6M

C345

1

@

2

12

R03

13

D

2

G

S

RUN_ON_CPU1.5VS3# <6>

+VCC_GFXCORE_AXG

1.5A

+1.8VS_VCCPLL

C132

1U_0402_6.3V6K

C132

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

1

2

R56

R56 82K_0402_5%

82K_0402_5%

Q4

Q4 2N7002_SOT23

2N7002_SOT23

J1

@J1

@

1 2

PAD-OPEN 4x4m

U3

DMN3030LSS-13_SOP8L-8

8 7

5

4

12

R57

R57 330K_0402_5%

330K_0402_5%

@

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

1

AP4800

2

Id=9.6A

36

R02

R885

1 2

15K_0402_1%

1

C97

0.047U_0603_25V7K

2

POWER

GRAPHICS

1.8V RAIL

1

12

13

2

G

+VCC_GFXCORE_AXG

AK35 AK34

+V_SM_VREF_CNT

AL1

+V_DDR_REFA_R

B4

+V_DDR_REFB_R

D1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

+VCCSA

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

A19

C92

0.1U_0402_10V6K

2

12

R616

R616 10_0402_1%

10_0402_1%

12

R626

R626 10_0402_1%

10_0402_1%

R55

220_0402_5%

D

Q3

2N7002_SOT23

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VAXG_SENSE

VSSAXG_SENSE

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

VCCIO_SEL

S

@C92

@

RUN_ON_CPU1.5VS3#

12

R89

@R89

@

100_0402_1%

C117

10U_0603_6.3V6M

C117

10U_0603_6.3V6M

1

2

10U

10U_0603_6.3V6M

C124

10U_0603_6.3V6M

C124

10U_0603_6.3V6M

1

2

H_VCCSA_VID0 <52> H_VCCSA_VID1 <52>

+VREF_DQ_DIMMA

+VREF_DQ_DIMMB

DRAMRST_CNTRL

LBSS138LT1G_SOT-23-3

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

VCC_AXG_SENSE <55>

VSS_AXG_SENSE <55>

+V_SM_VREF should have 20 mil trace width

1

C98

0.1U_0402_10V6K

10U_0603_6.3V6M

C118

1

2

C125

10U_0603_6.3V6M

1

2

R68 0_0402_5%

0.1U_0402_10V6K

C119

C126

1 2

1

2

1

2

@

C120

10U_0603_6.3V6M

C120

10U_0603_6.3V6M

C127

10U_0603_6.3V6M

C127

10U_0603_6.3V6M

H_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SEL

10U_0603_6.3V6M

1

2

+VCCSA

2

C121

1

+

2

G

Q9

+1.5V_CPU_VDDQ

12

R67

R67 1K_0402_1%

1K_0402_1%

12

R78

R78 1K_0402_1%

1K_0402_1%

+1.5V_CPU_VDDQ

1

C122

10U_0603_6.3V6M

C122

10U_0603_6.3V6M

1

+

C123

C123 330U_2.5V_M

330U_2.5V_M

2

C128

@+C128

@

330U_D2_2.5VY_R9M

+VCCSA_SENSE <52>

10K_0402_5%

1 2

R77 0_0402_5%

R02

1 2 1 2

13

D

S

RUN_ON_CPU1.5VS3

R75

@

Q6

13

D

LBSS138LT1G_SOT-23-3

2

G

@R670

@

@R671

@

G

S

0_0402_5%~D

0_0402_5%~D 0_0402_5%~D

0_0402_5%~D

R353

1K_0402_1%

@

R670

R671

Q5-orignal part AP2302GN-HF_SOT23-3 SB523020210

G

2

PMV45EN_SOT23-3

PMV45EN_SOT23-3 Q5

@

Q5

@

13

D

S

D

S

R61

@R61

@

1 2

0_0402_5%

+1.5V +1.5V_CPU_VDDQ

+3VALW+3VS

R76

@R76

@

10K_0402_5%

1 2

DRAMRST_CNTRL

+V_DDR_REFA_R

+V_DDR_REFB_R

12

R64

1K_0402_1%

@

+V_SM_VREF

C396

@C396

@

0.1U_0402_10V6K

1 2

C129

@C129

@

0.1U_0402_10V6K

1 2

C96

0.1U_0402_10V6K

1 2

C95

0.1U_0402_10V6K

1 2

VCCP_PWRCTRL <52>

+1.5V

12

R62

@R62

@

1K_0402_1%

R63

@R63

@

1K_0402_1%

DRAMRST_CNTRL <7>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

IVY Bridge drives VCCIO_SEL low VCCP_PWRCTRL:0 Sandy Bridge is NC for A19 VCCP_PWRCTRL:1

Deciphered Date

2

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

1

of

10 60Tuesday, December 06, 2011

0.1

5

JCPU1H

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16

D D

C C

B B

A A

5

AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4 AJ25

TYCO_2013620-2_IVY BRIDGE

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

4

AJ22

VSS81

AJ19

VSS82

AJ16

VSS83

AJ13

VSS84

AJ10

VSS85

AJ7

VSS86

AJ4

VSS87

AJ3

VSS88

AJ2

VSS89

AJ1

VSS90

AH35

VSS91

AH34

VSS92

AH32

VSS93

AH30

VSS94

AH29

VSS95

AH28

VSS96

AH25

VSS98

AH22

VSS99

AH19

VSS100

AH16

VSS101

AH7

VSS102

AH4

VSS103

AG9

VSS104

AG8

VSS105

AG4

VSS106

AF6

VSS107

AF5

VSS108

AF3

VSS109

AF2

VSS110

AE35

VSS111

AE34

VSS112

AE33

VSS113

AE32

VSS114

AE31

VSS115

AE30

VSS116

AE29

VSS117

AE28

VSS118

VSS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

3

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

TYCO_2013620-2_IVY BRIDGE

Compal Secret Data

3

Compal Secret Data

Deciphered Date

2011/06/15 2012/07/11

VSS

2

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

2

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

Compal Electronics, Inc.

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

1

0.1

of

11 60Tuesday, December 06, 2011

1

R70

R70 1K_0402_1%

1K_0402_1%

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7> DDR_A_WE#<7>

DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

5

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C134

C134

1

2

+3VS

5

0.1U_0402_10V6K

0.1U_0402_10V6K C133

C133

1

2

2.2U_0603_6.3V4Z

1

2

+1.5V +1.5V

3A@1.5V

DDR3 SO-DIMM A

JDIMM1

R83

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F ME@

ME@

VREF_CA

EVENT#

+VREF_DQ_DIMMA

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 M_CLK_DDR0

M_CLK_DDR#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# M_ODT0 DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

R81

1 2

10K_0402_5%

0.1U_0402_10V6K

C155

C156

10K_0402_5%

1

2

10K_0402_5%

12

R71

1K_0402_1%

+1.5V

12

+VREF_DQ_DIMMA

D D

C C

B B

A A

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

VTT2

4

DDR_A_D[0..63]<7> DDR_A_DQS[0..7]<7>

+VREF_CA

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C136

C136

1

2

4*0402 1uf

DDR_A_DQS#[0..7]<7> DDR_A_MA[0..15]<7>

R72

1K_0402_1%

1*0402 2.2uf

2

DDR_A_D4

4

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A7 A6

A4 A2

A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

G2

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D5 DDR_A_DQS#0

DDR_A_DQS0 DDR_A_D6

DDR_A_D7 DDR_A_D12

DDR_A_D13 DDR_A_DM1

DDR3_DRAMRST# DDR_A_D14

DDR_A_D15 DDR_A_D20

DDR_A_D21 DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_BS1

DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

4

+0.75VS

0.65A@0.75V

DDR3_DRAMRST# <7,13>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K

0.1U_0402_10V6K C135

C135

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <13,15,36> SMB_CLK_S3 <13,15,36>

3

+1.5V

12

R73

Layout Note: Place near DIMM

10U_0603_6.3V6M

C137

10U_0603_6.3V6M

C137

10U_0603_6.3V6M

1

@

2

Layout Note: Place near DIMM

C138

+1.5V

C139

10U_0603_6.3V6M

C139

10U_0603_6.3V6M

1

2

1

2

(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

OSCAN

(10uF_0603_6.3V)*8 (0.1uF_402_10V)*4

C146

0.1U_0402_10V6K

C146

C140

10U_0603_6.3V6M

C140

10U_0603_6.3V6M

1

2

C141

C142

10U_0603_6.3V6M

C142

10U_0603_6.3V6M

1

2

C143

10U_0603_6.3V6M

C143

10U_0603_6.3V6M

1

2

C144

10U_0603_6.3V6M

C144

10U_0603_6.3V6M

1

2

C145

0.1U_0402_10V6K

C145

0.1U_0402_10V6K

1

2

0.1U_0402_10V6K

1

2

C147

0.1U_0402_10V6K

C147

0.1U_0402_10V6K

1

2

C148

0.1U_0402_10V6K

C148

0.1U_0402_10V6K

1

2

1

EVT Check

1

+

C149 220U_6.3V_M

220U_6.3V_M

2

@+C149

@

7/28 Update connect GND directly

+0.75VS

del

C150

1U_0402_6.3V6K

C150

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C152

1U_0402_6.3V6K

C152

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

C151

1U_0402_6.3V6K

C151

1U_0402_6.3V6K

1

2

2011/06/15 2012/07/11

del

1

2

Compal Secret Data

Deciphered Date

2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

Layout Note: Place near DIMM

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

LA-7984P

1

12 60Tuesday, December 06, 2011

of

0.1

R84

1K_0402_1%

R85

1K_0402_1%

5

2.2U_0603_6.3V4Z

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7> DDR_B_WE#<7>

DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

5

1

C158

2

0.1U_0402_10V6K

1

C157

2

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C177

C177

1

2

+VREF_DQ_DIMMB DDR_B_D0

DDR_B_D1 DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 M_CLK_DDR2

M_CLK_DDR#2 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

1 2

10K_0402_5%

C178

R95

1 2

R97 10K_0402_5%R97 10K_0402_5%

3A@1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17 VSS1849DQ22

51

DQ18

53

DQ19 VSS2055DQ28

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U8SN-7F

ME@

+VREF_DQ_DIMMB

D D

For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit.

C C

B B

A A

+1.5V

12

VSS3 DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

DQ23

VSS19

DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

4

+1.5V+1.5V

2

DDR_B_D4

4

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A7 A6

A4 A2

A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

G2

4

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_D5 DDR_B_DQS#0

DDR_B_DQS0 DDR_B_D6

DDR_B_D7 DDR_B_D12

DDR_B_D13 DDR_B_DM1

DDR3_DRAMRST# DDR_B_D14

DDR_B_D15 DDR_B_D20

DDR_B_D21 DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 M_CLK_DDR3

M_CLK_DDR#3 DDR_B_BS1

DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT2 M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3

0.65A@0.75V

DDR3_DRAMRST# <7,12>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K C160

C160

C159

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <12,15,36> SMB_CLK_S3 <12,15,36> +0.75VS

3

DDR_B_D[0..63]<7> DDR_B_DQS[0..7]<7> DDR_B_DQS#[0..7]<7> DDR_B_MA[0..15]<7>

+1.5V

12

R86

1K_0402_1%

12

R87

1K_0402_1%

4*0402 1uf

1*0402 2.2uf

3

2

Layout Note: Place near DIMM

10U_0603_6.3V6M

C161

C162

C163

1

@

2

C174

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

1

2

C163

1

2

1U_0402_6.3V6K

1

2

Compal Secret Data

1

@

2

Layout Note: Place near DIMM

+0.75VS

C173

1U_0402_6.3V6K

C173

1U_0402_6.3V6K

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

(10uF_0603_6.3V)*8 (0.1uF_402_10V)*4

+1.5V

10U_0603_6.3V6M

C164

C165

1

2

DDR_B_DM0 DDR_B_DM1

C176

1

2

Deciphered Date

DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

2

10U_0603_6.3V6M

C166

1

2

Layout Note: Place near DIMM

10U_0603_6.3V6M

C167

1

2

1

10U_0603_6.3V6M

C168

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C170

C170

C169

1

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

0.1U_0402_10V6K

C171

C172

1

2

DDRIII-SODIMM SLOT2

C172

1

2

LA-7984P

1

0.1

of

13 60Tuesday, December 06, 2011

of

13 60Tuesday, December 06, 2011

of

13 60Tuesday, December 06, 2011

5

W=20milsW=20mils

R99

1K_0402_5%

1

C179

C179 1U_0603_10V4Z

1U_0603_10V4Z

2

D D

1 2

+RTCBATT+RTCVCC

12

SHORT PADS

CLRP1

C180

15P_0402_50V8J

4

1 2

R98 10M_0402_5%R98 10M_0402_5%

Y1

1 2

1

2

PCH_RTCX1 PCH_RTCX2

32.768KHZ_12.5PF_CM31532768DZFT

1

C181

C181 18P_0402_50V8J

18P_0402_50V8J

2

3

2

1

CMOS

CLRP2

SHORT PADS

CLRP2

+RTCVCC

R101 1M_0402_5%R101 1M_0402_5%

1 2

R102 330K_0402_5%R102 330K_0402_5%

1 2

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

SM_INTRUDER# PCH_INTVRMEN

(INTVRMEN should always be pull high.)

+3VS

R105 1K_0402_5%@R105 1K_0402_5%@

1 2

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

+3V_PCH

C C

R106 1K_0402_5%@R106 1K_0402_5%@

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

R108 1K_0402_5%R108 1K_0402_5%

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low

*

Needs to be pulled High for Chief River platfrom

HDA_BITCLK_AUDIO<41>

HDA_SYNC_AUDIO<41>

B B

HDA_RST_AUDIO#<41>

HDA_SDOUT_AUDIO<41>

+3V_PCH +3V_PCH+3V_PCH

12

R121

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

R125

100_0402_1%

12

R122

200_0402_5%

12

R126

R126 100_0402_1%

100_0402_1%

R112

33_0402_5%

1 2

R114

33_0402_5%

1 2

R116

33_0402_5%

1 2

R118

33_0402_5%

1 2

HDA_SPKR

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

12

R123

200_0402_5%

12

R128

100_0402_1%

DPDG1.1

+RTCVCC

ME_FLASH<42>

R878

1M_0402_5%

1 2

check with vender

Del Q10 check with codec VDDIO using 3VALW

C183

1U_0603_10V4Z

1 2

R103 20K_0402_5%R103 20K_0402_5%

1 2

R100 20K_0402_5%R100 20K_0402_5%

C182

1U_0603_10V4Z

ME_FLASH

R107 1K_0402_1%@R107 1K_0402_1%@

1 2

+3V_PCH

+5VS

G

2

S

R175

1 2

0_0402_5%

22P_0402_50V8J

HDA_SPKR<41>

HDA_SDIN0<41>

13

D

33_0402_5%

SHORT PADS

1

12

2

CLRP3

SHORT PADS

CLRP3

SHORT PADS

1

12

2

R109

1 2

0_0402_5%

R26410K_0402_5% @R26410K_0402_5% @

R110

12

51_0402_5%

Q10

Q10 LBSS138LT1G_SOT-23-3

LBSS138LT1G_SOT-23-3

HDA_SYNC

@R175

@

SPI_CLK_PCH_R

12

R124

@

C190

@

PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_GPIO33

12

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

SPI_CLK_PCH_R SPI_SB_CS0# SPI_SB_CS1#

SPI_SI SPI_SO_R

R124;c190 close to U4.T3 pin

U4A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

RTCIHDA

JTAG

SPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36 E36

K36

SERIRQ

V5

AM3 AM1

SATA_ITX_C_DRX_N0

AP7

SATA_ITX_C_DRX_P0

AP5 AM10

AM8 AP11 AP10

SATA_DTX_C_IRX_N2

AD7

SATA_DTX_C_IRX_P2

AD5

SATA_ITX_C_DRX_N2

AH5

SATA_ITX_C_DRX_P2

AH4 AB8

AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

RBIAS_SATA3

AH1

SATALED#

P3

PCH_GPIO21

V14

BBS_BIT0_R

P1

LPC_AD0 <36,42> LPC_AD1 <36,42> LPC_AD2 <36,42> LPC_AD3 <36,42>

LPC_FRAME# <36,42>

R104 10K_0402_5%R104 10K_0402_5%

R111

37.4_0402_1%

SATA_COMP

SATA3_COMP

37.4_0402_1%

1 2

R113

49.9_0402_1%

1 2

R115

750_0402_1%

R117 10K_0402_5%R117 10K_0402_5% R119 10K_0402_5%R119 10K_0402_5% R187 10K_0402_5%R187 10K_0402_5%

+3VS

R266

1 2

R221

1 2

R127

1 2

R129

1 2

12 12 12

EC and Mini card debug port

12

SERIRQ <42>

CAP on Conn, side

SATA_DTX_C_IRX_N2 <40>

SATA_DTX_C_IRX_P2 <40> SATA_ITX_C_DRX_N2 <40> SATA_ITX_C_DRX_P2 <40>

+1.05VS_VCC_SATA

+1.05VS_SATA3

SPI_WP#1

3.3K_0402_5%

SPI_HOLD#1

3.3K_0402_5%

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

+3VS

SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_P0

C1840.01U_0402_16V7K C1840.01U_0402_16V7K

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

C1850.01U_0402_16V7K C1850.01U_0402_16V7K

SPI_SB_CS1# SPI_SO_R

SPI_SB_CS0# SPI_SO_R SPI_SO_L

+3VS +3VS +3VS

12 12

SATA_DTX_C_IRX_N0 <40> SATA_DTX_C_IRX_P0 <40> SATA_ITX_DRX_N0 <40> SATA_ITX_DRX_P0 <40>

ODD

8MB SPI ROM FOR ME & Non-share ROM.

R291

0_0402_5%

CS1#

1 2

SPI_SO1

1 2

SPI_WP#1

R188

33_0402_5%

U6 Rersver 4M+2M Solution

0_0402_5%

R130

1 2 1 2

33_0402_5%

R131

CS# SPI_WP#

1 2 3 4

U6

CS# SO WP# GND

16M W25Q16BVSSIG SOIC 8P

U5

1

CS#

2

SO

3

WP#

4

GND

32M W25Q32BVSSIG SOIC 8P

VCC

HOLD#

SCLK

HOLD#

HDD

+3VS

8

SPI_HOLD#1

7

SPI_CLK1

SI

VCC

SCLK

6 5

8 7 6 5

SI

1 2

SPI_SI1

1 2

+3VS

C191

1 2

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_PCH SPI_CLK_PCH_R SPI_SI_R

1 2 1 2

0_0402_5%

0_0402_5% R199

R199

SPI_CLK_PCH_R SPI_SI

R196

R196 33_0402_5%

33_0402_5%

0_0402_5%

0_0402_5% R132

R132

SPI_SI

R133

R133 33_0402_5%

33_0402_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

2

Date: Sheet

14 60Tuesday, December 06, 2011

1

0.1

of

5

LAN

WLAN

D D

USB3.0

C C

LAN

WLAN

USB3.0

B B

PCIE_PRX_DTX_N1<37>

PCIE_PRX_DTX_P1<37> PCIE_PTX_C_DRX_N1<37> PCIE_PTX_C_DRX_P1<37>

PCIE_PRX_DTX_N2<36>

PCIE_PRX_DTX_P2<36> PCIE_PTX_C_DRX_N2<36> PCIE_PTX_C_DRX_P2<36>

PCIE_PRX_DTX_N4<45>

PCIE_PRX_DTX_P4<45> PCIE_PTX_C_DRX_N4<45> PCIE_PTX_C_DRX_P4<45>

CLK_PCIE_LAN#<37> CLK_PCIE_LAN<37>

CLKREQ_LAN#<37>

CLK_PCIE_WLAN1#<36> CLK_PCIE_WLAN1<36>

CLKREQ_WLAN#<36>

CLK_PCIE_USB30#<45> CLK_PCIE_USB30<45>

CLKREQ_USB30#<45>

C192 0.1U_0402_10V7KC192 0.1U_0402_10V7K C193 0.1U_0402_10V7KC193 0.1U_0402_10V7K

C194 0.1U_0402_10V7KC194 0.1U_0402_10V7K C195 0.1U_0402_10V7KC195 0.1U_0402_10V7K

C309 0.1U_0402_10V7KEU3@C309 0.1U_0402_10V7KEU3@ C308 0.1U_0402_10V7KEU3@C308 0.1U_0402_10V7KEU3@

R152 10K_0402_5%R152 10K_0402_5%

+3V_PCH

R158 10K_0402_5%R158 10K_0402_5%

+3VS

R147 10K_0402_5%R147 10K_0402_5%

+3VS

R334 0_0402_5%EU3@R334 0_0402_5%EU3@ R330 0_0402_5%EU3@R330 0_0402_5%EU3@

R326 0_0402_5%EU3@R326 0_0402_5%EU3@ R301 10K_0402_5%R301 10K_0402_5%

+3V_PCH

R165 10K_0402_5%R165 10K_0402_5%

+3V_PCH

R168 10K_0402_5%R168 10K_0402_5%

+3V_PCH

R170 10K_0402_5%R170 10K_0402_5%

+3V_PCH

R172 10K_0402_5%R172 10K_0402_5%

+3V_PCH

R174 10K_0402_5%R174 10K_0402_5%

+3V_PCH

1 2 1 2

CAP on Conn, side

R153

0_0402_5%

R153

0_0402_5%

1 2

R154

0_0402_5%

R154

0_0402_5%

1 2

R151

0_0402_5%

R151

0_0402_5%

1 2

12

R149

0_0402_5%

R149

0_0402_5%

1 2

R150

0_0402_5%

R150

0_0402_5%

1 2

R156

0_0402_5%

R156

0_0402_5%

1 2

12

1 2 1 2

1 2

12

4

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

CLKREQ_LAN#_R

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

CLKREQ_WLAN#_R

PCH_GPIO20

CLK_USB30# CLK_USB30

CLKREQ_USB30#_R

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

PCIE_CLK_8N PCIE_CLK_8P

U4B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

E12 H14

SMBCLK

C9

SMBDATA

A12 C8

SML0CLK

G12

C13 E14 M16

M7

CL_CLK1

T11

CL_DATA1

P10

CL_RST1#

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43 F47 H47 K49

BIOS Request SKU ID

2

PCH_GPI011 PCH_SMBCLK PCH_SMBDATA

DRAMRST_CNTRL_PCH

PCH_SML0CLK PCH_SML0DATA

PCH_HOT# SML1CLK SML1DATA

PEG_CLKREQ#_R

CLK_PCIE_VGA#_R CLK_PCIE_VGA#

CLK_CPU_DMI# CLK_CPU_DMI

CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI

CLKIN_DMI2# CLKIN_DMI2

CLK_BUF_DREF_96M# CLK_BUF_DREF_96M

CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA

CLK_BUF_ICH_14M

CLK_PCI_LPBACK

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

27M_SSC

LAN_48M PCH_GPIO67

R134

12

10K_0402_5%

R140 10K_0402_5%R140 10K_0402_5%

12

+3V_PCH

R143

R143 10K_0402_5%

10K_0402_5%

1 2

R144 0_0402_5%

1 2

R145 10K_0402_5%

1 2

R146 0_0402_5%R146 0_0402_5%

1 2

R148 0_0402_5%R148 0_0402_5%

1 2

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

R155 10K_0402_5%R155 10K_0402_5%

1 2

R157 10K_0402_5%R157 10K_0402_5%

1 2

R159 10K_0402_5%R159 10K_0402_5%

1 2

R160 10K_0402_5%R160 10K_0402_5%

1 2

R162 10K_0402_5%R162 10K_0402_5%

1 2

R163 10K_0402_5%R163 10K_0402_5%

1 2

R164 10K_0402_5%R164 10K_0402_5%

1 2

R166 10K_0402_5%R166 10K_0402_5%

1 2

R167 10K_0402_5%R167 10K_0402_5%

1 2

CLK_PCI_LPBACK <18>

R171

90.9_0402_1%

1 2

R207 22_0402_5%@R207 22_0402_5%@

1 2

PCH_GPIO67 <19>

+3V_PCH

R139

1K_0402_5%

+3V_PCH

PCH_HOT# <42>

R02

@

+1.05VS_VCCDIFFCLKN

+3V_PCH

DRAMRST_CNTRL_PCH <7>

12

+3V_PCH

+3V_PCH +3VS

CLK_REQ_VGA# <23>

CLK_PCIE_VGACLK_PCIE_VGA_R

PCH_LAN_48M <37>

2.2K_0402_5%

2.2K_0402_5% R136

R136

1 2 1 2

R135

2.2K_0402_5%

2.2K_0402_5% R141

R141

1 2 1 2

R142

2.2K_0402_5%

XTAL25_IN XTAL25_OUT

12P_0402_50V8J

Q60A

Q60A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

6 1

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q60B

Q60B

Q61A

Q61A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

6 1

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q61B

Q61B

CLK_PCIE_VGA# <23>

CLK_PCIE_VGA <23>

25MHZ_20PF_FSX3M-25.M20FDO

1

C196

2

SMB_CLK_S3

2.2K_0402_5%

1 2

2

+3VS

1 2

5

2.2K_0402_5%

SMB_DATA_S3

4

EC_SMB_CK2

2 5

EC_SMB_DA2

4

1 2

R169 1M_0402_5%R169 1M_0402_5%

3

OSC

2

NC

Y2

1

SMB_CLK_S3 <12,13,36>

DIMM1

R137

DIMM2

R138

MINI CARD

SMB_DATA_S3 <12,13,36>

EC_SMB_CK2 <23,39,42>

VGA EC thermal sensor

EC_SMB_DA2 <23,39,42>

2.2K_0402_5%

PCH_SML0CLK PCH_SML0DATA

4

NC

1

OSC

R02

1

2

R544

C197

12P_0402_50V8J

+3V_PCH

1 2

R545

2.2K_0402_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

LA-7984P

1

15 60Tuesday, December 06, 2011

0.1

of

5

D D

U15

U15 MC74VHC1G08DFT2G SC70 5P

MC74VHC1G08DFT2G SC70 5P

3

R191

1

G

A

SYS_PWROK

4

Y

2

B

P

5

+3VS

12

12 12

12

PM_DRAM_PWRGD SUSWARN# AC_PRESENT_R

PCH_RSMRST#_R

12

R180 100K_0402_1%

100K_0402_1%

SYS_PWROK <6>

@R180

@

SUSACK# is only used on platform that support the Deep Sx state.

PCH_PWROK<42>

PCH_APWROK<42>

PM_DRAM_PWRGD<6>

EC_RSMRST#<42>

PBTN_OUT#<42>

ACIN<42,49>

VGATE<55>

PCH_PWROK

C C

AEPWROK can be connect to PWROK if iAMT disable

PCH_POK APWROK

+3VS

+3V_PCH

R192 200_0402_5%R192 200_0402_5%

B B

R194 10K_0402_5%R194 10K_0402_5% R195 200K_0402_5%R195 200K_0402_5%

R197 10K_0402_5%R197 10K_0402_5%

1 2

0_0402_5%

@

R556 200_0402_5%

1 2

4

DMI_CTX_PRX_N0<5> DMI_CTX_PRX_N1<5> DMI_CTX_PRX_N2<5> DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5> DMI_CTX_PRX_P1<5> DMI_CTX_PRX_P2<5> DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5> DMI_CRX_PTX_N1<5> DMI_CRX_PTX_N2<5> DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5> DMI_CRX_PTX_P1<5> DMI_CRX_PTX_P2<5> DMI_CRX_PTX_P3<5>

+1.05VS

1 2

R177 49.9_0402_1%R177 49.9_0402_1%

1 2

R178 750_0402_1%R178 750_0402_1%

4mil width and place within 500mil of the PCH

T72T72

+3VS

PCH_PWROK

1 2

R190 0_0402_5%

1 2

R193 0_0402_5%

1 2

R198 0_0402_5%

D29

CH751H-40PT_SOD323-2

+3V_PCH

21

10K_0402_5%

12

R18410K_0402_5% R18410K_0402_5%

@

R02

@

R3020_0402_5%@R3020_0402_5%

@

R02

@

R02

R200

12

10K_0402_5%

10K_0402_5% R201

R201

12

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP RBIAS_CPY

SUSACK#

SYS_RST#

SYS_PWROK

PCH_POK

APWROK

PM_DRAM_PWRGD

PCH_RSMRST#_R

SUSWARN#

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

U4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

3

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

FDI_RXP6

DMI

FDI

DMI

FDI

FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXP7

FDI_INT

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWODVREN

WAKE#

PM_CLKRUN#

SUS_STAT#

SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

R02

@

R185 0_0402_5%

1 2

10K_0402_5%

1 2

R186

1 2

R261

@R261

@

10K_0402_5%

2

FDI_CTX_PRX_N0 <5> FDI_CTX_PRX_N1 <5> FDI_CTX_PRX_N2 <5> FDI_CTX_PRX_N3 <5> FDI_CTX_PRX_N4 <5> FDI_CTX_PRX_N5 <5> FDI_CTX_PRX_N6 <5> FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5> FDI_CTX_PRX_P1 <5> FDI_CTX_PRX_P2 <5> FDI_CTX_PRX_P3 <5> FDI_CTX_PRX_P4 <5> FDI_CTX_PRX_P5 <5> FDI_CTX_PRX_P6 <5> FDI_CTX_PRX_P7 <5>

FDI_INT <5> FDI_FSYNC0 <5> FDI_FSYNC1 <5> FDI_LSYNC0 <5> FDI_LSYNC1 <5>

R02

R181 0_0402_5%@ R181 0_0402_5%@

1 2

T74T74

T99T99

T71T71

H_PM_SYNC <6>

+3V_PCH

PCIE_WAKE# <36,37,45>

+3V_PCH

SUSCLK <42>

PM_SLP_S5# <42>

PM_SLP_S4# <42>

PM_SLP_S3# <42>

*

DSWODVREN - On Die DSW VR Enable H

：

Enable

L

：

Disable

PCH_RSMRST#_RPCH_DPWROK

R189 8.2K_0402_5%@ R189 8.2K_0402_5%@

1 2

R299 10K_0402_5%R299 10K_0402_5%

12

Can be left NC when IAMT is not support on the platfrom

1

+RTCVCC

12

R179

R179 330K_0402_5%

330K_0402_5%

12

R183

R183 330K_0402_5%

+3VS

330K_0402_5%

@

Can be left NC if no use integrated LAN.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (3/9) DMI,FDI,PM,

LA-7984P

1

0.1

of

16 60Tuesday, December 06, 2011

5

+3VS

12

D D

C C

B B

2.2K_0402_5%

R559

2.2K_0402_5%

+3VS

12

R523

R524

2.2K_0402_5%

CRT_DDC_CLK CRT_DDC_DATA

R234

2.2K_0402_5%

EDID_CLK EDID_DATA

DAC_BLU<34> DAC_GRN<34> DAC_RED<34>

+3VS

4

PCH_ENBKL<33> PCH_ENVDD<33>

PCH_PWM<33>

EDID_CLK<33>

EDID_DATA<33>

R2042.2K_0402_5% R2042.2K_0402_5%

1 2

R2052.2K_0402_5% R2052.2K_0402_5%

1 2

R2062.37K_0402_1% R2062.37K_0402_1%

12

LVDS_ACLK#<33> LVDS_ACLK<33>

LVDS_A0#<33> LVDS_A1#<33> LVDS_A2#<33>

LVDS_A0<33> LVDS_A1<33> LVDS_A2<33>

R208 150_0402_1%R208 150_0402_1% R209 150_0402_1%R209 150_0402_1% R210 150_0402_1%R210 150_0402_1%

CRT_DDC_CLK<34> CRT_DDC_DATA<34>

CRT_HSYNC<34> CRT_VSYNC<34>

12 12 12

DAC_BLU DAC_GRN DAC_RED

1K_0402_1%

EDID_CLK EDID_DATA

CTRL_CLK CTRL_DATA

LVDS_IBG

LVD_VREF

CRT_DDC_CLK CRT_DDC_DATA

CRT_IREF

12

R211

U4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

3

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

CRT

DDPD_HPD

R202

HDMI@ R202

HDMI@

2.2K_0402_5%

HDMICLK_NB HDMIDAT_NB

TMDS_B_DATA2#_PCH TMDS_B_DATA2_PCH TMDS_B_DATA1#_PCH TMDS_B_DATA1_PCH TMDS_B_DATA0#_PCH TMDS_B_DATA0_PCH TMDS_B_CLK#_PCH TMDS_B_CLK_PCH

2

+3VS

12

R203

HDMI@R203

HDMI@

2.2K_0402_5%

HDMICLK_NB <35> HDMIDAT_NB <35>

TMDS_B_HPD# <35>

C200 0.1U_0402_10V6KHDMI@ C200 0.1U_0402_10V6KHDMI@

1 2

C201 0.1U_0402_10V6KHDMI@ C201 0.1U_0402_10V6KHDMI@

1 2

C202 0.1U_0402_10V6KHDMI@ C202 0.1U_0402_10V6KHDMI@

1 2

C203 0.1U_0402_10V6KHDMI@ C203 0.1U_0402_10V6KHDMI@

1 2

C204 0.1U_0402_10V6KHDMI@ C204 0.1U_0402_10V6KHDMI@

1 2

C205 0.1U_0402_10V6KHDMI@ C205 0.1U_0402_10V6KHDMI@

1 2

C206 0.1U_0402_10V6KHDMI@ C206 0.1U_0402_10V6KHDMI@

1 2

C207 0.1U_0402_10V6KHDMI@ C207 0.1U_0402_10V6KHDMI@

1 2

CAP move on Conn, side

HDMI_TX2-_CK <35> HDMI_TX2+_CK <35> HDMI_TX1-_CK <35> HDMI_TX1+_CK <35> HDMI_TX0-_CK <35> HDMI_TX0+_CK <35> HDMI_CLK-_CK <35> HDMI_CLK+_CK <35>

1

HDMI D2 HDMI D1

HDMI

HDMI D0 HDMI CLK

A A

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Title

PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Rev

B

LA-7984P

Date: Sheet

2

Date: Sheet

1

of

17 60Tuesday, December 06, 2011

0.1

5

+3VS

RP2

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5% RP1

D D

C C

GNT1#/ GPIO51

PCH_WL_OFF#

B B

A16 swap overide Strap/Top-Block Swap Override jumper

RP1

8.2K_0804_8P4R_5%

R213 8.2K_0402_5%R213 8.2K_0402_5%

1 2

R225 8.2K_0402_5%R225 8.2K_0402_5%

1 2

R292 8.2K_0402_5%@R292 8.2K_0402_5%@

1 2

R557 8.2K_0402_5%@R557 8.2K_0402_5%@

1 2

R259 8.2K_0402_5%R259 8.2K_0402_5%

1 2

R212 8.2K_0402_5%R212 8.2K_0402_5%

1 2

R214 8.2K_0402_5%@R214 8.2K_0402_5%@

1 2

Boot BIOS Strap bit1 BBS1

PCI_GNT3#

A A

PLT_RST#<23,36,37,42,45>

PCI_PIRQA#

18

PCI_PIRQD#

27

PCI_PIRQC#

36

PCI_PIRQB#

45

PCH_GPIO2

18

DGPU_PWR_EN_R

27

PCH_GPIO4

36

ODD_DA#_R

45

PCH_GPIO5 PCH_WL_OFF# PCH_GPIO51 PCH_GPIO53 DGPU_PWR_EN1 DGPU_HOLD_RST#_R DGPU_HOLD_RST#_R

Boot BIOS Destination

Bit10

Bit11

01 1 1 0

1 2

R319 0_0402_5%

@

R215 1K_0402_5%@R215 1K_0402_5%@

1 2

Low=A16 swap override/Top-Block Swap Override enabled High=Default

1U_0402_6.3V4Z

5

Reserved Reserved

0 1

SPI

*

0

LPC

NVDD_PWR_ENDGPU_PWR_EN_R

*

1

C208

@C208

@

2

(Default)

GPIO55

12

R223

R223 100K_0402_5%

100K_0402_5%

PPT EDS DOC#474146

DGPU_HOLD_RST#<23>

NVDD_PWR_EN<54> DGPU_PWR_EN<23,25>

PCH_WL_OFF#<36>

ODD_DA#<40,42>

CLK_PCI_LPBACK<15>

CLK_PCI_EC<42>

CLK_PCI_DB<36>

R222

1 2

0_0402_5%

3

1

G

A

4

Y

2

B

P

U7

@U7

@

5

MC74VHC1G08DFT2G SC70 5P

+3VS

4

USB3_RX3_N<45> USB3_RX4_N<45>

USB3_RX3_P<45> USB3_RX4_P<45>

USB3_TX3_N<45> USB3_TX4_N<45>

USB3_TX3_P<45> USB3_TX4_P<45>

PCH_PLTRST#

4

T1829T1829 T1825T1825

T1832T1832 T1826T1826

T1831T1831 T1827T1827

T1830T1830 T1828T1828

R553 0_0402_5%R553 0_0402_5%

1 2

R692 0_0402_5%R692 0_0402_5%

1 2

R691 0_0402_5%R691 0_0402_5%

1 2

R715 0_0402_5%@R715 0_0402_5%@

1 2

PCH_PLTRST#<6>

USB3_RX3_N USB3_RX4_N

USB3_RX3_P USB3_RX4_P

USB3_TX3_N USB3_TX4_N

USB3_TX3_P USB3_TX4_P

PCI_PME#<42>

1 2 1 2

R21922_0402_5% R21922_0402_5% R22022_0402_5% R22022_0402_5% R17322_0402_5% @ R17322_0402_5% @

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB3_RX1_N

USB3_RX1_P

USB3_TX1_N

USB3_TX1_P

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST#_R DGPU_PWR_EN1 DGPU_PWR_EN_R

PCH_GPIO51 PCH_GPIO53 PCH_WL_OFF#

PCH_GPIO2 ODD_DA#_R PCH_GPIO4 PCH_GPIO5

PCH_PLTRST#

CLK_PCI_LPBACK_R CLK_PCI_EC_R CLK_PCI_DB_R

3

U4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

2011/06/15 2012/07/11

3

RSVD

PCI

USB

Compal Secret Data

Deciphered Date

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AV10

AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

2

USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB20_N5 USB20_P5

USB20_N9 USB20_P9

USB20_N11 USB20_P11

USB20_N13 USB20_P13

USBRBIAS

USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# SMIB USB_OC7#

2

USB DEBUG=PORT1 AND PORT9

USB20_N1 <43> USB20_P1 <43> USB20_N2 <45> USB20_P2 <45> USB20_N3 <45> USB20_P3 <45>

USB20_N5 <33> USB20_P5 <33>

USB20_N9 <44> USB20_P9 <44> USB20_N10 <36> USB20_P10 <36> USB20_N11 <43> USB20_P11 <43>

USB20_N13 <40> USB20_P13 <40>

R218

1 2

22.6_0402_1%

Within 500 mils

Title

Size Document Number Rev

Custom

Date: Sheet

(CR-B/D USB) LEFT USB LEFT USB

(USB 3.0)

USB Camera

RIGHT USB WLAN CARD READER

Bluetooth

USB_OC0# Share with USB_OC4# due to same power switch

R02

USB_OC4# <44>

USB_OC1# <45>

USB_OC4# <44>

SMIB <45>

R03

PCH (5/9) PCI, USB

LA-7984P

USB_OC5# USB_OC2# USB_OC7#

USB_OC1# USB_OC4# USB_OC3#

SMIB

1

RP310K_1206_8P4R_5% RP310K_1206_8P4R_5%

4 5 3 6 2 7 1 8

RP410K_1206_8P4R_5% RP410K_1206_8P4R_5%

R262

1 2

10K_0402_5%

18 60Tuesday, December 06, 2011

of

+3V_PCH

0.1

5

D D

+3V_PCH

GPIO28

On-Die PLL Voltage Regulator

This signal has a weak internal pull up

*

PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable

C C

B B

Weak internal pull-high

R250

@R250

@

10K_0402_5%

R547

R547 10K_0402_5%

10K_0402_5%

EC_SMI#

PCH_GPIO27

+3VS

12

R235 10K_0402_5%R235 10K_0402_5%

1 2

：

On-Die voltage regulator enable

H L：On-Die PLL Voltage Regulator disable

R240 1K_0402_5%@R240 1K_0402_5%@

1 2

R245 10K_0402_5%@R245 10K_0402_5%@

1 2

+3VS

12

R244

@R244

@

10K_0402_5%

PCH_GPIO37 PCH_GPIO36

12

R881

R881 10K_0402_5%

10K_0402_5%

+3VS

+3V_PCH

EC_LID_OUT#<42>

DGPU_PWROK<46,54>

PU on power side

+3VS

BT_DISABLE<36>

R02

PCH_BT_ON#<36,40>

+3VS

+3V_PCH

BIOS Request SKU ID

+3VS

12

R246

R711

@

1 2

R708

A A

1 2

10K_0402_5%

R298

10K_0402_5%

PCH_GPIO38 PCH_GPIO67

12

PCH_GPIO38 PCH_GPIO67

10K_0402_5%

5

PCH_GPIO67 <15>

0 01 1

0

Optimus

Reserved

11

Function

DIS UMA

4

R233 10K_0402_5%R233 10K_0402_5%

1 2

R227 10K_0402_5%R227 10K_0402_5%

1 2

R228 10K_0402_5%R228 10K_0402_5%

1 2

EC_SCI#<42> EC_SMI#<42>

R229 10K_0402_5%@R229 10K_0402_5%@

1 2

R02

R230 1K_0402_5%R230 1K_0402_5%

1 2

R231 10K_0402_5%R231 10K_0402_5%

1 2

R297 0_0402_5%R297 0_0402_5%

1 2

R232 10K_0402_1%@R232 10K_0402_1%@

1 2

+3VS

R238 10K_0402_5%R238 10K_0402_5%

1 2

+3VS

+3V_PCH

1 2 1 2 1 2

R247 10K_0402_5%R247 10K_0402_5%

1 2

R248 10K_0402_5%R248 10K_0402_5%

1 2

R249 10K_0402_5%R249 10K_0402_5%

1 2

R251 10K_0402_5% R251 10K_0402_5%

1 2

4

ODD_EN<40>

R241

10K_0402_5%

10K_0402_5% R242 10K_0402_5%R242 10K_0402_5% R243 10K_0402_5%R243 10K_0402_5%

PCH_GPIO1 PCH_GPIO6 EC_SCI# EC_SMI# PCH_GPIO12PCH_GPIO28 EC_LID_OUT#

PCH_GPIO16

DGPU_PWROK_R BT_DISABLE ODD_EN PCH_GPIO27 PCH_GPIO28 PCH_BT_ON# PCH_GPIO35 PCH_GPIO36 PCH_GPIO37 PCH_GPIO38 PCH_GPIO39 PCH_GPIO48 PCH_GPIO49 PCH_GPIO57

3

@R702

@

U4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

GPIO

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

NCTF

VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

2011/06/15 2012/07/11

PCH_GPIO68

C40

PCH_GPIO69

B41

PCH_GPIO70

C41

PCH_GPIO71

A40

P4

PCH_PECI_R

AU16

KBRST#

P5 AY11

PCH_THRMTRIP#_R

AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

Compal Secret Data

INIT3_3V

This signal has weak internal PU,can't pull low

NV_CLE

Deciphered Date

2

R702

1 2

10K_0402_5%

R707

@

1 2

10K_0402_5%

R22410K_0402_5% R22410K_0402_5%

1 2

@

1 2

R2370_0402_5%@R2370_0402_5%

1 2

R239 390_0402_5%R239 390_0402_5%

2

200K_0402_5%

R703

@R703

@

1 2

10K_0402_5%

R705

1 2

+3VS

1 2

H_PECI <6,42> KBRST# <42> H_CPUPWRGD <6>

H_THRMTRIP#

NV_CLE

Weak internal PU,Do not pull low

1

PCH_GPIO70

0 1

PCH_GPIO71

0 1

R236

R236 10K_0402_5%

10K_0402_5%

GATEA20 <42>

H_THRMTRIP# <6>

PCH_THRMTRIP#_R <23>

DMI Termination Voltage

Set to Vcc when HIGH Set to Vss when LOW

Title

PCH (6/9) GPIO, CPU, MISC

Size Document Number Rev

Custom

LA-7984P

Date: Sheet

Function

14/15"

17"

USB3.0 by PCH USB3.0 by NEC

KBRST#

R226 10K_0402_5%R226 10K_0402_5%

1 2

+1.8VS

12

R216

2.2K_0402_5%

12

R217 1K_0402_5%R217 1K_0402_5%

CLOSE TO THE BRANCHING POINT

H_SNB_IVB# <6>

1

R704

@ R704

@

PCH_GPIO71PCH_GPIO70PCH_GPIO69

R706

200K_0402_5%

of

19 60Tuesday, December 06, 2011

+3VS+3VS +3VS

1 2

10K_0402_5%

1 2

+3VS

0.1

Compal Electronics, Inc.

Compal LA-7984P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual