Page 1
A
B
C
D
E
MODEL NAME :
PCB NO :
BOM P/N :
1 1
LA-7931P ( DAA00002T00 )
4319FN31L01
4319FN31L02
QAR00
Compal Confidential
Vans 15
rPGAIvyBridge+FCBGAPCHPantherPoint+MXM typeAx1Ⅲ
Rev: 1.0 (A00)
2 2
CONN@ : ME connector
2012.06.07
@ : Nopop component
5@ : 6-bit LCD panel
6@ : 10-bit LCD panel
1@, 2@, 3@, 4@ : for TPM / TCM
3 3
MBType
SATARe‐driver
(U26,U637)
PS8520B
(SA00004WF00)
4 4
MB PCB
Part
Description
Number
DAA00002T00
power CKT: 05/17
PCB0FELA‐7931PREV0M/BDIS
MAX4951C
(SA00002EY1L)
A
Source
mainsource
2ndsource X7641231L02
PXDP@,JTAG@ : Total debug connector (pop them until ST)
BOMP/N
4319FN31L01 4319FN31L02
Include6‐bit Include10‐bit
1@TPM
3@
5@ 6@1@ 3@
PXDP@ PXDP@
JTAG@ JTAG@
X76P/N
X7641231L01
B
Page
35,43
USB3Re‐driver
(U638)
PS8720B
(SA00004UI00)
PS8720A
(SA00005PO00)
Source
mainsource
2ndsource X7641231L04
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
MBType
TPM
X76P/N
X7641231L03
C
Page
40
BOMP/N
ROMpart Source
U52(SA000039A2L)
U53(SA00003K80L)
main(Winbond)
U52(SA000046400)
U53(SA00004LI00)
D
2nd(EON) X7640631L03
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
X76P/N
X7640631L01
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
Page
17
LA-7931P
LA-7931P
LA-7931P
1.0
1.0
170Monday, July 23, 2012
170Monday, July 23, 2012
170Monday, July 23, 2012
E
1.0
Page 2
A
&
LVDS6‐bit
LVDS10‐bit
&
eDPtoLVDS
1 1
LVDSPanel
P.28
Conn
DP1.2
Conn
P.29
CRTConn
Docking CRT
P.32
HDMI1.4a
Conn
P.34
Port 8
Docking DP1
Docking DP2
Port 3
2 2
IEEE1394
+
ExpressCard
(STDP4010)
P.30~P.31
LVDSMUX
(TS3DV20812)
DPRedriver
(PS8330B)
CRTSW
(MAX14885)
DP/HDMIDeMUX
(PS8336B)
IntelLewisville
(82579LM)
Cardreader
USB Port 10
SDXC1394
3 3
SIMCard
P.43
FreeFallSensor
(LNG3DMTR)
P.35
CurrentMonitor
(EMC1701)
4 4
P.26
Thermal
GUARDIANIII
EMC4002
P.25
On IO board
SATA Port 5
USB 2.0 Port 8
Docking DAI
Docking CRT
Docking LAN
USB3.0 Port 3
Docking LPC
Docking DP1
Docking DP2
A
LANswitch
(PI3L720)
RJ45
P.38
(10-bit panel output)
P.27
P.29
(10-bit panel output)
P.32
P.34
DP(DIS)
Port 7
P.37
P.37
Docking LAN
E‐Dock
LVDS (DIS)
LVDS
DP (DIS)
DP (DIS)
MiniCard‐3
PP
P.45
B
PEG x16 (DIS)
DP
DP_D
LVDS
DP_A
MXMConn.
TYPEA
CRT
DP_C
DP_B
PCIE BUS
Port 5
P.42
SMSCSIO
ECE5048
SATA Port 2
PCIE/SATAMUX
(PI2DBS212)
MiniCard‐2
WWAN/GPS
mSATA
USB Port 5
P.47
Port 6
P.43
P.43
BC BUS
MiniCard‐1
WLAN/WiGi
USB Port 4
ChinaTCM1.2
SSX44B
DiscreteTPM
AT97SC3204
SMSCKBC
Docking LPC
MEC5055
TPCONN
On IO board
DC‐IN
P.53
www.schematic-x.blogspot.com
B
LVDS
CRT
Port 2
C
P.16
P.42
P.41
P.41
P.48
KBCONN
C
D
Intel
IvyBridge
Processorr
PGA989Socket
35WDualCore
45WQuadCore
55WQCExtremeEdition
P.6~P.11
FDI x8
(DDRIII)
Memory Bus
Dual Channel
1.5V DDRIII
1333 /1600 MHz
DMI x4 gen 2
SATA3.0
204pinDDRIIISO‐DIMMx4
SATA Port 0
SATA Port 3
SATA Port 4
SATA2.0
LVDS
CRT
Intel
PantherPoint
PCH
BGA989Balls
8MB
P.17~P.24
W25X64ZE
USB3.0
USB2.0
HD Audio
P.17
USB Port 0
USB Port 1
USB Port 2
USB Port 6
USB Port 11
USB Port 12
USB Port 13
USB Port 7
SPI
W25Q32BV
4MB
P.17
On USH Board
LPC BUS
AudioCodec
92HD93
P.49
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
D
P.12~P.15
OC : 1866 MHz
SATA3.0Repeater
(PS8520B)
P.35
ODDConn.
P.36
USB/eSATAConn.
USB Port 9
P.39
USB3.0Repeater
(PS8710B)
USB3.0Repeater
(PS8710B)
P.40
P.40
USB2.0ConnLeftSide
USB2.0ConnLeftSide
BT4.0+LE
DigitalCamera
P.49
Touchscreen
P.28
P.28
BRCM5882
TPM1.2
FP_USB
HeadPhoneJack
ArrayMICJack
Int.Speaker
Speaker module
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
E
1stHDDConn.
USB2.0 port 0
USB3.0ConnRightSide
USBCharger
USB3.0ConnRightSide
USB2.0 port 1
On IO board
through LVDS Cable
RFID
TDA8034HN
SmartCard
Fingerprint
CONN
On IO board
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
LA-7931P
LA-7931P
LA-7931P
E
P.35
270Monday, July 23, 2012
270Monday, July 23, 2012
270Monday, July 23, 2012
P.40
P.40
1.0
1.0
1.0
Page 3
5
4
3
2
1
POWER STATES
State
S0 (Full ON) / M0
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH ON ON ON OFF
D D
S4 (Suspend to DISK) / M1 ON ON OFF
S5 (SOFT OFF) / M1 ON ON OFFLOW LOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
SLP
S3#
S4#
HIGH
HIGH HIGH HIGH
LOW
LOW HIGH HIGHLOW
LOW
LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
S5#
S4
STATE#
SLP
M#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCH
PM TABLE
+15V_ALW
+5V_ALW
C C
State
S0
S3
S5 S4/AC
power
plane
+3.3V_ALW_PCH
+3.3V_RTC_LDO
ON
ON
+3.3V_SUS
+1.5V_MEM
ON ON
ON
OFF
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
OFFON
OFF
+3.3V_M +3.3V_M
+1.05V_M
ON
ON
ON
+1.05V_M
(M-OFF)
ON
OFF
OFF
SATA
SATA 0
SATA 1
SATA 2
SATA 3
SATA 4
SATA 5
DESTINATION
HDD 1
NA
mSATA
ODD
ESATA
Dock
USH
USB PORT#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
JUSB1 (Ext Right Side)
JUSB2 (Ext Right Side)
IO Board- JUSB1 (Ext Left Side)
Docking USB3.0
Docking USB 2.0
WWAN
IO Board- JUSB2 (Ext Left Side)
USH
WLAN
ESATA
Express Card
BT 4.0
Carmera
Touch Screen
DESTINATION
USB3.0
USB3.0
BIO
NA
S5 S4/AC don't exist
B B
A A
Stack up
OFFOFF
OFF
OFFOFF
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
NA
MINI CARD-1 WLAN/DMC
Express Card
NA
MINI CARD-3 (Pink Panther)
MINI CARD-2 WWAN/mSATA/GPS
10/100/1G LOM
DESTINATION
Lane 8 Cardreader
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Index and Config.
Index and Config.
Index and Config.
LA-7931P
LA-7931P
LA-7931P
370Monday, July 23, 2012
370Monday, July 23, 2012
370Monday, July 23, 2012
1
1.0
1.0
1.0
Page 4
5
4
3
2
1
DOCK
D D
EN_INVPWR
RUN_GFX_ON
ADAPTER
PCH_ALW_ON
+PWR_SRC
BATTERY
CHARGER
C C
SI3456DDV
EN_LCDPWR
(Q18)
MXM_ENVDD
ENVDD_PCH
FDC654P
(Q21)
SI4835DDY
(Q186)
TP0610K
(PQ4)
LCD_VCC_TEST_EN
+LCDVDD
+BL_PWR_SRC
+MXM_PWR_SRC
+PWR_SRC_S
+1.8V_RUN
PWR_SHARE_EN#
TPS2560
(U45)
+5V_USB_PWR1
+5V_USB_PWR2
SY8033
(PU4)
SIO_SLP_S3#
Pop option
+5V_HDD
+5V_RUN
ALWON
SIO_SLP_S3#
MODC_EN
SI3456DDVSI3456DDV
(Q30)(Q27)
+5V_MOD
RT8205
(PU101)
+3.3V_ALW
+5V_ESATA_PWR
ALW_ON_3.3V#
+5V_ALW
ESATA_USB_PWR_EN#
TPS2560
(U48)
+5V_ALW_PCH
SSM3K7002FU
(QH4)
RUN_GFX_ON
+5V_RUN_ENABLE
+5V_MXM
SI4800BDY
(Q76)
DMN3030LSS
(Q329)
+5V_RUN
SYSON
RT8207
(PU151)
B B
SIO_SLP_A#
TPS51212
(PU5)
CPU_VTT_ON
TPS51212
(PU6)
1.05V_VTTPWRGD
TPS51461
(PU7)
1.05V_0.8V_PWROK
NVRAM_PWR_EN
SI3456DDV
(Q46)
MCARD_WWAN_PWREN
SI3456DDV
(Q40)
MCARD_MISC_PWREN
SI3456DDV
(Q44)
PCH_ALW_ON
SI3456DDV
(Q49)
SUS_ON
SI3456DDV
(Q54)
SIO_SLP_LAN#
SI3456DDV
SLG59M232VTR
(Q34) (U78)
SIO_SLP_A#
(Q58)
RUN_GFX_ON
SI3456DDV
(Q25)
SIO_SLP_S3#
SI3456DDV
+1.5V_MEM
+1.05V_M
SIO_SLP_S3#
SI4164
(Q63)
+1.05V_RUN_VTT
ISL95836
(PU702)
+VCC_SA
+3.3V_PCIE_NVM
+3.3V_PCIE_WWAN
+3.3V_PCIE_FLASH
+3.3V_ALW_PCH
Pop option
+3.3V_M
+3.3V_LAN+3.3V_SUS
LDO of 82579
(U31)
+3.3V_RUN
PMV65XP
+3.3V_M
CCD_OFF
+3V_MXM
(Q24)
+1.05V_RUN
+VCC_CORE
+VCC_GFXCORE
Pop option
+1.0V_LAN+1.05V_M
A A
SUSP#
+0.75V_DDR_VTT
SIO_SLP_S3#
AO4728L
(QC3)
+1.5V_CPU_VDDQ
5
SIO_SLP_S3#
NTGS4141
+1.5V_RUN
(Q59)
+VCCAFDI_VRM
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
+CAMERA_VDD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power Rail
Power Rail
Power Rail
LA-7931P
LA-7931P
LA-7931P
470Monday, July 23, 2012
470Monday, July 23, 2012
470Monday, July 23, 2012
1
1.0
1.0
1.0
Page 5
5
4
3
2
1
SMBUS Address [0x9a]
H14
MEM_SMBCLK
C9
MEM_SMBDATA
3A
PCH
E14M16
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
1A
1A
1B
1B
C8
G12
LAN_SMBCLK
LAN_SMBDATA
2.2K
2.2K
B4
A3
B5
A4
+3.3V_ALW_PCH
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMBDAT
D D
C C
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
100 ohm
100 ohm
2N7002
2N7002
SMBUS Address [C8]
127
129
DOCKING
7
BATTERY
6
CONN
SMBUS Address [0x16]
SMBUS Address
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
U5
1
Current Monitor
10
U6
1
10
Current Monitor
12
14
JLVDS3
202
200
202
200
202
200
202
200
53
51
DIMM1
DIMM2
DIMM3
SMBUS Address [A0h]
A0h --> 1010 0000
SMBUS Address [A4h]
A4h --> 1010 0100
SMBUS Address [A4h]
A4h --> 1010 0100
DIMM4
XDP2
SMBUS Address [TBD]
10K
14
13
+3.3V_RUN
G Sensor
WWAN
SMBUS Address [TBD]
SMBUS Address [TBD]
SMBUS Address
SMB_ADM1032: 0x98
SMB_DIAG_DUMP: 0x04
SMB_DIAG_DUMP2: 0x05
SMB_BLACKTOP: 0x60
10K
30
32
A50
B53
USH_SMBCLK
USH_SMBDAT
1E
1E
2.2K
+3.3V_SUS
M9
L9
SMBUS Address [0xa4]
USH
2.2K
B B
MEC 5055
2B
2B
A49
B52
CARD_SMBCLK
CARD_SMBDAT
2.2K
2.2K
2.2K
B50
1G
1G
CHARGER_SMBCLK
A47
CHARGER_SMBDAT
2.2K
B7
A7
BAY_SMBDAT
BAY_SMBCLK
2D
2D
2.2K
4.7K
A A
5
B49
B48
GPU_SMBCLK
GPU_SMBDAT
2A
2A
4.7K
4
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
2N7002
2N7002
10
9
Charger
7
Express card
8
SMBUS Address [0x12]
SMBUS Address [TBD]
70
68
MXM
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SMBUS Address [0x30]
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SMBUS Bolck Diagram
SMBUS Bolck Diagram
SMBUS Bolck Diagram
LA-7931P
LA-7931P
LA-7931P
570Monday, July 23, 2012
570Monday, July 23, 2012
570Monday, July 23, 2012
1
of
of
of
1.0
1.0
1.0
Page 6
5
4
3
2
1
PEG_CRX_GTX_C_P[0..15]
PEG_CRX_GTX_C_N[0..15]
JCPU1A
D D
C C
B B
DMI_CRX_PTX_N0<19>
DMI_CRX_PTX_N1<19>
DMI_CRX_PTX_N2<19>
DMI_CRX_PTX_N3<19>
DMI_CRX_PTX_P0<19>
DMI_CRX_PTX_P1<19>
DMI_CRX_PTX_P2<19>
DMI_CRX_PTX_P3<19>
DMI_CTX_PRX_N0<19>
DMI_CTX_PRX_N1<19>
DMI_CTX_PRX_N2<19>
DMI_CTX_PRX_N3<19>
DMI_CTX_PRX_P0<19>
DMI_CTX_PRX_P1<19>
DMI_CTX_PRX_P2<19>
DMI_CTX_PRX_P3<19>
FDI_CTX_PRX_N0<19>
FDI_CTX_PRX_N1<19>
FDI_CTX_PRX_N2<19>
FDI_CTX_PRX_N3<19>
FDI_CTX_PRX_N4<19>
FDI_CTX_PRX_N5<19>
FDI_CTX_PRX_N6<19>
FDI_CTX_PRX_N7<19>
FDI_CTX_PRX_P0<19>
FDI_CTX_PRX_P1<19>
FDI_CTX_PRX_P2<19>
FDI_CTX_PRX_P3<19>
FDI_CTX_PRX_P4<19>
FDI_CTX_PRX_P5<19>
FDI_CTX_PRX_P6<19>
FDI_CTX_PRX_P7<19>
FDI_FSYNC0<19>
FDI_FSYNC1<19>
FDI_INT<19>
FDI_LSYNC0<19>
FDI_LSYNC1<19>
(1)EDP_COMPIOuse4miltracetoRC1
(2)EDP_ICOMPOuse12miltoRC1
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
B27
B25
A25
B24
B28
B26
A24
B23
G21
E22
F21
D21
G22
D22
F20
C21
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
J18
J17
H20
J19
H17
A18
A17
B16
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15
CONN@
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
TYCO_2134146-3_IVYBRIDGE~D
DMI
Intel(R) FDI
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PCI EXPRESS* - GRAPHICS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
PEG_COMP
J21
H22
K33
PEG_CRX_GTX_N0
M35
PEG_CRX_GTX_N1
L34
PEG_CRX_GTX_N2
J35
PEG_CRX_GTX_N3
J32
PEG_CRX_GTX_N4
H34
PEG_CRX_GTX_N5
H31
PEG_CRX_GTX_N6
G33
PEG_CRX_GTX_N7
G30
PEG_CRX_GTX_N8
F35
PEG_CRX_GTX_N9
E34
PEG_CRX_GTX_N10
E32
PEG_CRX_GTX_N11
D33
PEG_CRX_GTX_N12
D31
PEG_CRX_GTX_N13
B33
PEG_CRX_GTX_N14
C32
PEG_CRX_GTX_N15
J33
PEG_CRX_GTX_P0
L35
PEG_CRX_GTX_P1
K34
PEG_CRX_GTX_P2
H35
PEG_CRX_GTX_P3
H32
PEG_CRX_GTX_P4
G34
PEG_CRX_GTX_P5
G31
PEG_CRX_GTX_P6
F33
PEG_CRX_GTX_P7
F30
PEG_CRX_GTX_P8
E35
PEG_CRX_GTX_P9
E33
PEG_CRX_GTX_P10
F32
PEG_CRX_GTX_P11
D34
PEG_CRX_GTX_P12
E31
PEG_CRX_GTX_P13
C33
PEG_CRX_GTX_P14
B32
PEG_CRX_GTX_P15
M29
PEG_CTX_GRX_C_N0
M32
PEG_CTX_GRX_C_N1
M31
PEG_CTX_GRX_C_N2
L32
PEG_CTX_GRX_C_N3
L29
PEG_CTX_GRX_C_N4
K31
PEG_CTX_GRX_C_N5
K28
PEG_CTX_GRX_C_N6
J30
PEG_CTX_GRX_C_N7
J28
PEG_CTX_GRX_C_N8
H29
PEG_CTX_GRX_C_N9
G27
PEG_CTX_GRX_C_N10
E29
PEG_CTX_GRX_C_N11
F27
PEG_CTX_GRX_C_N12
D28
PEG_CTX_GRX_C_N13
F26
PEG_CTX_GRX_C_N14
E25
PEG_CTX_GRX_C_N15
M28
PEG_CTX_GRX_C_P0
M33
PEG_CTX_GRX_C_P1
M30
PEG_CTX_GRX_C_P2
L31
PEG_CTX_GRX_C_P3
L28
PEG_CTX_GRX_C_P4
K30
PEG_CTX_GRX_C_P5
K27
PEG_CTX_GRX_C_P6
J29
PEG_CTX_GRX_C_P7
J27
PEG_CTX_GRX_C_P8
H28
PEG_CTX_GRX_C_P9
G28
PEG_CTX_GRX_C_P10
E28
PEG_CTX_GRX_C_P11
F28
PEG_CTX_GRX_C_P12
D27
PEG_CTX_GRX_C_P13
E26
PEG_CTX_GRX_C_P14
D25
PEG_CTX_GRX_C_P15
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
12
CC8 0.22U_0402_16V7K~D
12
CC9 0.22U_0402_16V7K~D
12
CC10 0.22U_0402_16V7K~D
12
CC1 0.22U_0402_16V7K~D
12
CC2 0.22U_0402_16V7K~D
12
CC11 0.22U_0402_16V7K~D
12
CC12 0.22U_0402_16V7K~D
12
CC3 0.22U_0402_16V7K~D
12
CC4 0.22U_0402_16V7K~D
12
CC13 0.22U_0402_16V7K~D
12
CC14 0.22U_0402_16V7K~D
12
CC5 0.22U_0402_16V7K~D
12
CC6 0.22U_0402_16V7K~D
12
CC15 0.22U_0402_16V7K~D
12
CC16 0.22U_0402_16V7K~D
12
CC7 0.22U_0402_16V7K~D
12
CC17 0.22U_0402_16V7K~D
12
CC18 0.22U_0402_16V7K~D
12
CC19 0.22U_0402_16V7K~D
12
CC20 0.22U_0402_16V7K~D
12
CC21 0.22U_0402_16V7K~D
12
CC22 0.22U_0402_16V7K~D
12
CC23 0.22U_0402_16V7K~D
12
CC24 0.22U_0402_16V7K~D
12
CC25 0.22U_0402_16V7K~D
12
CC26 0.22U_0402_16V7K~D
12
CC27 0.22U_0402_16V7K~D
12
CC28 0.22U_0402_16V7K~D
12
CC29 0.22U_0402_16V7K~D
12
CC30 0.22U_0402_16V7K~D
12
CC31 0.22U_0402_16V7K~D
12
CC32 0.22U_0402_16V7K~D
12
CC33 0.22U_0402_16V7K~D
12
CC34 0.22U_0402_16V7K~D
12
CC35 0.22U_0402_16V7K~D
12
CC36 0.22U_0402_16V7K~D
12
CC37 0.22U_0402_16V7K~D
12
CC38 0.22U_0402_16V7K~D
12
CC39 0.22U_0402_16V7K~D
12
CC40 0.22U_0402_16V7K~D
12
CC41 0.22U_0402_16V7K~D
12
CC42 0.22U_0402_16V7K~D
12
CC43 0.22U_0402_16V7K~D
12
CC44 0.22U_0402_16V7K~D
12
CC45 0.22U_0402_16V7K~D
12
CC46 0.22U_0402_16V7K~D
12
CC47 0.22U_0402_16V7K~D
12
CC48 0.22U_0402_16V7K~D
12
CC49 0.22U_0402_16V7K~D
12
CC50 0.22U_0402_16V7K~D
12
CC51 0.22U_0402_16V7K~D
12
CC52 0.22U_0402_16V7K~D
12
CC53 0.22U_0402_16V7K~D
12
CC54 0.22U_0402_16V7K~D
12
CC55 0.22U_0402_16V7K~D
12
CC56 0.22U_0402_16V7K~D
12
CC57 0.22U_0402_16V7K~D
12
CC58 0.22U_0402_16V7K~D
12
CC59 0.22U_0402_16V7K~D
12
CC60 0.22U_0402_16V7K~D
12
CC61 0.22U_0402_16V7K~D
12
CC62 0.22U_0402_16V7K~D
12
CC63 0.22U_0402_16V7K~D
12
CC64 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P[0..15] <16>
PEG_CRX_GTX_C_N[0..15] <16>
PEG_CTX_GRX_P[0..15] <16>
PEG_CTX_GRX_N[0..15] <16>
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_P15
PEG_CTX_GRX_N0
PEG_CTX_GRX_N1
PEG_CTX_GRX_N2
PEG_CTX_GRX_N3
PEG_CTX_GRX_N4
PEG_CTX_GRX_N5
PEG_CTX_GRX_N6
PEG_CTX_GRX_N7
PEG_CTX_GRX_N8
PEG_CTX_GRX_N9
PEG_CTX_GRX_N10
PEG_CTX_GRX_N11
PEG_CTX_GRX_N12
PEG_CTX_GRX_N13
PEG_CTX_GRX_N14
PEG_CTX_GRX_N15
PEG_CTX_GRX_P0
PEG_CTX_GRX_P1
PEG_CTX_GRX_P2
PEG_CTX_GRX_P3
PEG_CTX_GRX_P4
PEG_CTX_GRX_P5
PEG_CTX_GRX_P6
PEG_CTX_GRX_P7
PEG_CTX_GRX_P8
PEG_CTX_GRX_P9
PEG_CTX_GRX_P10
PEG_CTX_GRX_P11
PEG_CTX_GRX_P12
PEG_CTX_GRX_P13
PEG_CTX_GRX_P14
PEG_CTX_GRX_P15
CONN@
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
LinkCISOK
+1.05V_RUN_VTT +1.05V_RUN_VTT
RC1 24.9_0402_1%~D
12
eDPCompensation
eDP_COMPIOandICOMPOsignalsshouldbeshortednear
ballsandroutedwithtypicalimpedance<25mohms
A A
5
EDP_COMP
0722
1 2
RC2 24.9_0402_1%~D
PEGCompensation
PEG_ICOMPIandRCOMPOsignals
shouldbeshortedandroutedwith
‐maxlength=500mils
‐typicalimpedance=43mohms
PEG_ICOMPOsignalsshouldberoutedwith
‐maxlength=500mils
‐typicalimpedance=14.5mohms
PEG_COMP
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Ivy Bridge (1/6)
Ivy Bridge (1/6)
Ivy Bridge (1/6)
LA-7931P
LA-7931P
LA-7931P
670Monday, July 23, 2012
670Monday, July 23, 2012
670Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 7
5
4
3
2
1
FollowDGRev0.71SM_DRAMPWROKtopology
+3.3V_ALW_PCH
RUNPWROK<48,49>
D D
C C
B B
PM_DRAM_PWRGD<19>
+3.3V_ALW_PCH
+1.05V_RUN_VTT
RC11 56_0402_5%~D@
RC13 49.9_0402_1%~D@
RC16 62_0402_5%~D
H_PROCHOT#<26,49,60,62>
H_THERMTRIP#<25>
H_CPUPWRGD<21>
1 2
RC6 200_0402_5%~D
1 2
H_THERMTRIP#
1 2
1 2
H_CATERR#
H_PROCHOT#
CPU_DETECT#<48>
PECI_EC<49>
1 2
RC22 56_0402_5%~D
PlaceRC22nearCPU
1 2
RC24 0_0402_5%~D@
H_PM_SYNC<19>
1 2
RC27
@
BufferedresettoCPU
A A
PCH_PLTRST#<20>
1
2
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#_R
H_PM_SYNC
H_CPUPWRGD_R
0_0402_5%~D
VDDPWRGOOD_R
PCH_PLTRST#_R
+3.3V_RUN
5
1
P
NC
Y
2
A
G
SN74LVC1G07DCKR_SC70-5~D
3
CC65
1 2
0.1U_0402_16V4Z~D
5
B
4
VCC
Y
A
G
UC1
MC74VHC1G09DFT2G_SC70-5
3
RUN_ON_CPU1.5VS3#<11,52>
C26
AN34
AL33
AN33
AL32
AN32
AM34
AP33
V8
AR33
0.1U_0402_16V4Z~D
1
CC69
2
4
PCH_PLTRST#_BUF
UC2
Opendrainbuffer
5
+1.5V_CPU_VDDQ
12
200_0402_5%~D
39_0402_5%~D
12
13
D
2
G
S
JCPU1B
CONN@
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
+1.05V_RUN_VTT
75_0402_1%~D
12
RC49
1 2
RC51 43_0402_5%~D
RC4
VDDPWRGOOD
@
RC7
SSM3K7002FU_SC70-3~D
1 2
RC5 130_0402_5%~D
@
QC1
MISCTHERMALPWR MANAGEMENT
VDDPWRGOOD_R
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
BPM#[0]
BPM#[1]
BPM#[2]
JTAG & BPM
PCH_PLTRST#_R
4
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
BCLK
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
A28
CPU_DMI
A27
CPU_DMI#
A16
CPU_DPLL
A15
CPU_DPLL#
R8
DDR3_DRAMRST#_CPU
AK1
SM_RCOMP0
A5
SM_RCOMP1
A4
SM_RCOMP2
AP29
XDP_PRDY#
AP27
XDP_PREQ#
AR26
XDP_TCLK
AR27
XDP_TMS
AP30
XDP_TRST#
AR28
TDI
XDP_TDI_R
AP26
XDP_TDO_R
AL35
XDP_DBRESET#_R
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
XDP_TDO_R XDP_TDO
ForESDconcern,pleaseputnearCPU
H_CPUPWRGD
AvoidstubinthePWRGDpath
whileplacingresistorsRC27&RC46
+3.3V_ALW_PCH
1 2
RC3 1K_0402_5%~D@
+1.05V_RUN_VTT
PlacenearJXDP1
1 2
RC17 0_0402_5%~D@
1 2
RC18 0_0402_5%~D@
1 2
RC19 1K_0402_1%~D
1 2
RC21 1K_0402_1%~D
4.99K_0402_1%~D
12
RC23
DDR_HVREF_RST_PCH<18>
DDR_HVREF_RST_GATE<49>
RC29
@
1 2
0_0402_5%~D
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
1 2
RC34 0_0402_5%~D@
1 2
RC40 0_0402_5%~D@
1
2
0.1U_0402_16V4Z~D
CC66
T69PAD~D @
T70PAD~D @
T68PAD~D @
T67PAD~D @
T78PAD~D @
T77PAD~D @
T79PAD~D @
T80PAD~D @
SYS_PWROK_XDP
0.1U_0402_16V4Z~D
1
CC67
2
CLK_CPU_DMI <18>
CLK_CPU_DMI# <18>H_SNB_IVB#<21>
+1.05V_RUN_VTT
D
S
13
G
BSS138W-7-F_SOT323-3~D
2
1
CC68
0.047U_0402_16V4Z~D
2
RC25 0_0402_5%~D@
RC26 0_0402_5%~D@
XDP_DBRESET# <17,19>
XDP_TDIXDP_TDI_R
SIO_PWRBTN#_R<17,19>
CFG0<9>
SYS_PWROK<19,48>
QC2
DDR_HVREF_RST
1 2
1 2
H_CPUPWRGD H_CPUPWRGD_XDP
DDR3_DRAMRST# <12>
1 2
RC8 1K_0402_5%~D
1 2
RC9 0_0402_5%~D@
1 2
RC10 1K_0402_5%~D
1 2
RC12 0_0402_5%~D@
DDR_HVREF_RST <12>
Maxlength=500mils
Tracewidth=15mils
SM_RCOMP2
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RC4610K_0402_5%~D
3
SM_RCOMP1
SM_RCOMP0
1 2
1 2
1 2
2
+1.05V_RUN_VTT
JXDP1
CONN@
XDP_PREQ#
XDP_PRDY#
CFD_PWRBTN#_XDP
XDP_HOOK2
SYS_PWROK_XDP
CLK_XDP
CLK_XDP#
XDP_RST#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCLK
1
OBSFN_A0
2
OBSFN_A1
3
GND
4
OBSDATA_A[0]
5
OBSDATA_A[1]
6
GND
7
OBSDATA_A[2]
8
OBSDATA_A[3]
9
GND
10
HOOK0
11
HOOK1
12
HOOK2
13
HOOK3
14
HOOK4
15
HOOK5
16
VCCOBS_AB
17
HOOK6
18
HOOK7
19
GND
20
TDO
21
TRSTn
22
TDI
23
TMS
TCK124GND
25
GND
26
TCK0
MOLEX_52435-2671
GND
27
28
LinkCISOK
0722
XDP_RST#_R
RC20 1K_0402_5%~D
CLK_XDP
RH1 0_0402_5%~D@
CLK_XDP#
RH2 0_0402_5%~D@
CLK_XDP_ITP<9>
CLK_XDP_ITP#<9>
RC47200_0402_1%~D
RC4825.5_0402_1%~D
RC50140_0402_1%~D
RH3 0_0402_5%~D@
RH4 0_0402_5%~D@
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
12
1 2
1 2
1 2
1 2
PU/PDforJTAGsignals
XDP_DBRESET#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Ivy Bridge (2/6)
Ivy Bridge (2/6)
Ivy Bridge (2/6)
LA-7931P
LA-7931P
LA-7931P
RC281K_0402_5%~D
+1.05V_RUN_VTT
RC3151_0402_1%~D
RC3551_0402_1%~D
RC3851_0402_1%~D @
RC4251_0402_1%~D
RC4451_0402_1%~D
RC4551_0402_1%~D
1
PLTRST_XDP# <20>
CLK_CPU_ITP <18>
CLK_CPU_ITP# <18>
+3.3V_RUN
770Monday, July 23, 2012
770Monday, July 23, 2012
770Monday, July 23, 2012
of
1.0
1.0
1.0
Page 8
5
4
3
2
1
D D
JCPU1C
CONN@
AB6
DDR_A_D[0..63]<12,13>
C C
B B
DDR_A_BS0<12,13>
DDR_A_BS1<12,13>
DDR_A_BS2<12,13>
DDR_A_CAS#<12,13>
DDR_A_RAS#<12,13>
DDR_A_WE#<12,13>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AD9
AF9
F10
AJ5
AJ6
AJ8
AJ9
AE8
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N8
N7
M9
N9
M7
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
SA_CK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CK[2]
SA_CLK#[2]
SA_CKE[2]
SA_CK[3]
SA_CLK#[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
DDR SYSTEM MEMORY A
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMM2
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMM2
M_CLK_DDR4
M_CLK_DDR#4
DDR_CKE4_DIMM1
M_CLK_DDR5
M_CLK_DDR#5
DDR_CKE5_DIMM1
DDR_CS0_DIMM2#
DDR_CS1_DIMM2#
DDR_CS4_DIMM1#
DDR_CS5_DIMM1#
M_ODT0
M_ODT1
M_ODT4
M_ODT5
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 <13>
M_CLK_DDR#0 <13>
DDR_CKE0_DIMM2 <13>
M_CLK_DDR1 <13>
M_CLK_DDR#1 <13>
DDR_CKE1_DIMM2 <13>
M_CLK_DDR4 <12>
M_CLK_DDR#4 <12>
DDR_CKE4_DIMM1 <12>
M_CLK_DDR5 <12>
M_CLK_DDR#5 <12>
DDR_CKE5_DIMM1 <12>
DDR_CS0_DIMM2# <13>
DDR_CS1_DIMM2# <13>
DDR_CS4_DIMM1# <12>
DDR_CS5_DIMM1# <12>
M_ODT0 <13>
M_ODT1 <13>
M_ODT4 <12>
M_ODT5 <12>
DDR_A_DQS#[0..7] <12,13>
DDR_A_DQS[0..7] <12,13>
DDR_A_MA[0..15] <12,13>
DDR_B_D[0..63]<14,15>
DDR_B_BS0<14,15>
DDR_B_BS1<14,15>
DDR_B_BS2<14,15>
DDR_B_CAS#<14,15>
DDR_B_RAS#<14,15>
DDR_B_WE#<14,15>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
AM5
AM6
AR3
AN3
AN2
AN1
AN9
AN8
AR6
AR5
AR9
AJ11
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
D10
K10
AP3
AP2
AP5
AT5
AT6
AP6
AT8
AT9
AA9
AA7
AB8
AB9
C9
C8
D9
D8
G4
G1
G5
G2
J10
M5
N4
N2
N1
M4
N5
M2
M1
R6
A7
A9
A8
F4
F1
F5
F2
J7
J8
K9
J9
K8
K7
JCPU1D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
CONN@
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMM4
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMM4
M_CLK_DDR6
M_CLK_DDR#6
DDR_CKE6_DIMM3
M_CLK_DDR7
M_CLK_DDR#7
DDR_CKE7_DIMM3
DDR_CS2_DIMM4#
DDR_CS3_DIMM4#
DDR_CS6_DIMM3#
DDR_CS7_DIMM3#
M_ODT2
M_ODT3
M_ODT6
M_ODT7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
SB_CK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CK[2]
SB_CLK#[2]
SB_CKE[2]
SB_CK[3]
SB_CLK#[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
M_CLK_DDR2 <15>
M_CLK_DDR#2 <15>
DDR_CKE2_DIMM4 <15>
M_CLK_DDR3 <15>
M_CLK_DDR#3 <15>
DDR_CKE3_DIMM4 <15>
M_CLK_DDR6 <14>
M_CLK_DDR#6 <14>
DDR_CKE6_DIMM3 <14>
M_CLK_DDR7 <14>
M_CLK_DDR#7 <14>
DDR_CKE7_DIMM3 <14>
DDR_CS2_DIMM4# <15>
DDR_CS3_DIMM4# <15>
DDR_CS6_DIMM3# <14>
DDR_CS7_DIMM3# <14>
M_ODT2 <15>
M_ODT3 <15>
M_ODT6 <14>
M_ODT7 <14>
DDR_B_DQS#[0..7] <14,15>
DDR_B_DQS[0..7] <14,15>
DDR_B_MA[0..15] <14,15>
TYCO_2134146-3_IVYBRIDGE~D
A A
LinkCISOK
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Ivy Bridge (3/6)
Ivy Bridge (3/6)
Ivy Bridge (3/6)
LA-7931P
LA-7931P
LA-7931P
870Monday, July 23, 2012
870Monday, July 23, 2012
870Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 9
5
4
3
2
1
CFGStrapsforProcessor
CFG2
D D
JCPU1E
CONN@
1K_0402_5%~D
12
@
RC52
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
KEY
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
CFG0<7>
T60 PAD~D@
T55 PAD~D@
T65 PAD~D@
T64 PAD~D@
T76 PAD~D@
T75 PAD~D@
T2 PAD~D@
T3 PAD~D@
+VCC_GFXCORE
1 2
RC54 49.9_0402_1%~D@
C C
1 2
RC56 49.9_0402_1%~D@
+VCC_CORE
1 2
RC57 49.9_0402_1%~D@
1 2
RC61 49.9_0402_1%~D@
B B
VAXG_VAL_SENSE
12
RC55
@
100_0402_1%~D
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
12
RC58
@
100_0402_1%~D
VSS_VAL_SNESE
T11 PAD~D@
T13 PAD~D@
T72 PAD~D@
T71 PAD~D@
T18PAD~D @
T24PAD~D @
T25PAD~D @
T26PAD~D @
T27PAD~D @
T29PAD~D @
T31PAD~D @
T33PAD~D @
T35PAD~D @
T37PAD~D @
T38PAD~D @
T39PAD~D @
T40PAD~D @
T41PAD~D @
T43PAD~D @
T45PAD~D @
T46PAD~D @
T47PAD~D @
T48PAD~D @
T49PAD~D @
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
VSS_VAL_SNESE
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
CFG
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RESERVED
RSVD_NCTF9
RSVD_NCTF10
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
T4 PAD~D@
T5 PAD~D@
T6 PAD~D@
T7 PAD~D@
T8 PAD~D@
T1 PAD~D@
T9 PAD~D@
T10 PAD~D@
T12 PAD~D@
T14 PAD~D@
T15 PAD~D@
T16 PAD~D@
T17 PAD~D@
T19 PAD~D@
T20 PAD~D@
T21 PAD~D@
T22 PAD~D@
T23 PAD~D@
T28 PAD~D@
T30 PAD~D@
T32 PAD~D@
T34 PAD~D@
T36 PAD~D@
T42 PAD~D@
T44 PAD~D@
CLK_XDP_ITP <7>
CLK_XDP_ITP# <7>
T50 PAD~D@
T51 PAD~D@
T52 PAD~D@
T53 PAD~D@
PEGStaticLaneReversal‐CFG2isforthe16x
1:(Default)NormalOperation;Lane#
definitionmatchessocketpinmapdefinition
CFG2
0:LaneReversed
CFG4
1K_0402_5%~D
12
@
RC53
DisplayPortPresenceStrap
1:Disabled;NoPhysicalDisplayPort
CFG4
attachedtoEmbeddedDisplayPort
0:Enabled;AnexternalDisplayPortdeviceis
connectedtotheEmbeddedDisplayPort
CFG6
CFG5
1K_0402_5%~D
@
RC60
1K_0402_5%~D
12
12
@
RC59
PCIEPortBifurcationStraps
11:(Default)x16‐Device1functions1and2disabled
10:x8,x8‐Device1function1enabled;function2
CFG[6:5]
disabled
01:Reserved‐(Device1function1disabled;function
2enabled)
00:x8,x4,x4‐Device1functions1and2enabled
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
CFG7
1K_0402_5%~D
12
@
RC62
PEGDEFERTRAINING
1:(Default)PEGTrainimmediately
A A
CFG7
followingxxRESETBdeassertion
0:PEGWaitforBIOSfortraining
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Ivy Bridge (4/6)
Ivy Bridge (4/6)
Ivy Bridge (4/6)
LA-7931P
LA-7931P
LA-7931P
970Monday, July 23, 2012
970Monday, July 23, 2012
970Monday, July 23, 2012
1
1.0
1.0
1.0
Page 10
5
JCPU1F
4
CONN@
POWER
3
2
1
+VCC_CORE
97A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
D D
C C
B B
A A
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
CORE SUPPLY
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
PEG AND DDR
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
8.5A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
+1.05V_RUN_VTT
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
VCCSENSE_R
VSSSENSE_R
VIDSCLK <60>
PlaceRC68,RC69nearCPU
1 2
RC68 0_0402_5%~D@
1 2
RC69 0_0402_5%~D@
10_0402_1%~D
12
RC72
Note:PlacethePUresistorsclosetoCPU
RC63closetoCPU300‐1500mils
H_CPU_SVIDALRT#
+1.05V_RUN_VTT
12
RC65
130_0402_1%~D
12
+1.05V_RUN_VTT
RC7010_0402_1%
VTT_SENSE <58>
VSSIO_SENSE_R <58>
VIDSOUT <60>
RC66
@
1 2
100_0402_1%~D
1 2
RC64 43_0402_5%~D
CADNote:PlacethePU
resistorsclosetoCPU
RC65closetoCPU300‐1500mils
+VCC_CORE
12
RC67
100_0402_1%~D
12
RC71
100_0402_1%~D
+1.05V_RUN_VTT
12
VCCSENSE <60>
VSSSENSE <60>
RC63
75_0402_1%~D
VIDALERT_N <60>
SENSE LINES SVID
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Ivy Bridge (5/6)
Ivy Bridge (5/6)
Ivy Bridge (5/6)
LA-7931P
LA-7931P
LA-7931P
10 70Monday, July 23, 2012
10 70Monday, July 23, 2012
10 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 11
5
4
3
2
1
+1.5V_CPU_VDDQSource
+3.3V_ALW2
100K_0402_5%~D
Solve300mW
12
RC76
PWRconsumption
2
issue.
RUN_ON_CPU1.5VS3#
DMN66D0LDW-7_SOT363-6~D
61
QC5A
D D
1 2
SIO_SLP_S3#<19,35,47,48,52,56>
CPU1.5V_S3_GATE<49>
RC82 0_0402_5%~D@
1 2
RC83 0_0402_5%~D@
+PWR_SRC_S
330K_0402_5%~D
12
RC73
3
5
4
+1.5V_MEM +1.5V_CPU_VDDQ
RUN_ON_CPU1.5VS3
DMN66D0LDW-7_SOT363-6~D
QC5B
Solve300mW
PWRconsumption
issue.
RUN_ON_CPU1.5VS3# <7,52>
+VCC_GFXCORE
C C
B B
1 2
1 2
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
RC87 1K_0402_5%~D@
RC88 1K_0402_5%~D@
33A
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
JCPU1G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
CONN@
POWER
VSSAXG_SENSE
SENSE
LINES
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
GRAPHICS
DDR3 -1.5V RAILS
VAXG_SENSE
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
AK35
AK34
AL1
B4
D1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
SA RAIL
VCCIO_SEL
H23
C22
C24
A19
+1.8V_RUN
10U_0603_6.3V6M~D
CC88
A A
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CC90
CC89
2
2
1.5A
B6
VCCPLL1
330U_D2_2.5VM_R6M~D
1
+
CC91
2
A6
VCCPLL2
A2
VCCPLL3
TYCO_2134146-3_IVYBRIDGE~D
1.8V RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
LinkCISOK
5
4
Solvebackdrive(followB4).
QC3
AO4304L_SO8
8
7
6
5
4
0.022U_0603_50V7~D
1M_0402_5%~D
12
RC79
1
CC71
2
+VCC_GFXCORE
100_0402_1%~D
12
RC84
100_0402_1%~D
12
RC86
+V_SM_VREF_CNT
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
Checkingagain
5A
1
2
6A
VCCP_PWRCTRL_R
1
2
3
1
2
1 2
RC85
@
100_0402_1%~D
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC75
1
2
10U_0603_6.3V6M~D
1
2
1 2
@
10U_0805_6.3V6M~D
20K_0402_5%~D
12
CC70
@
CC76
CC83
RC89
RC77
10U_0603_6.3V6M~D
CC77
1
2
10U_0603_6.3V6M~D
CC84
1
2
+1.5V_MEM
VCC_AXG_SENSE <60>
VSS_AXG_SENSE <60>
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC78
1
1
2
2
+VCC_SA
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC85
1
1
2
2
0_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+V_DDR_SMREF
1K_0402_1%~D
12
@
RC78
1K_0402_1%~D
12
@
RC80
+1.5V_CPU_VDDQ
330U_D2_2VM_R6M~D
10U_0603_6.3V6M~D
CC79
CC80
1
1
+
2
2
330U_D2_2VM_R6M~D
1
@
CC87
CC86
+
2
VCCSA_SENSE <59>
VCCSA_VID_0 <59>
VCCSA_VID_1 <59>
VCCP_PWRCTRL <58>
1 2
RC74 0_0402_5%~D@
QC4
@
NTR4503NT1G_SOT23-3~D
1
RUN_ON_CPU1.5VS3
CC72 0.1U_0402_10V7K~D
CC73 0.1U_0402_10V7K~D
CC74 0.1U_0402_10V7K~D
CC82 0.1U_0402_10V7K~D
CC81
12
12
12
12
2
3
+1.5V_CPU_VDDQ
1K_0402_1%~D
12
1K_0402_1%~D
12
2
RC75
+V_SM_VREF_CNT
RC81
6A
+1.5V_MEM
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AR25
AR22
AR19
AR16
AR13
AR10
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AJ25
CONN@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
AN7
VSS43
AN4
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
AK7
VSS78
AK4
VSS79
VSS80
TYCO_2134146-3_IVYBRIDGE~D
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
LinkCISOK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Ivy Bridge (6/6)
Ivy Bridge (6/6)
Ivy Bridge (6/6)
LA-7931P
LA-7931P
LA-7931P
11 70Monday, July 23, 2012
11 70Monday, July 23, 2012
11 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 12
5
4
3
2
1
AllVREFtracesshould
have10miltracewidth
PopulateRD1forIntelDDR3
D D
DDR_A_DQS#[0..7]<8,13>
DDR_A_D[0..63]<8,13>
DDR_A_DQS[0..7]<8,13>
DDR_A_MA[0..15]<8,13>
+1.5V_MEM
+1.5V_MEM
C C
B B
10U_0603_6.3V6M~D
1
2
DIMMSelect
A A
VREFDQmultiplemethodsM1
CD5
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1
2
CD9
CD15
DIMM10
DIMM2
DIMM3
DIMM4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD6
CD3
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD10
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD16
2
2
+3.3V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD4
2
2
10U_0603_6.3V6M~D
CD8
CD7
1
1
2
2
LayoutNote:
PlacenearJDIMM1.203,204
+0.75V_DDR_VTT
1
2
SA01SA1
0
0
1
1
0
1
CD11
CD17
0_0402_5%~D
0_0402_5%~D
+3.3V_RUN
1
2
1
2
DDR_CKE4_DIMM1<8>
M_CLK_DDR4<8>
M_CLK_DDR#4<8>
DDR_CS5_DIMM1#<8>
0.1U_0402_16V4Z~D
1
CD21
2
+DIMM1_VREF_DQ
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
1
CD1
CD2
2
DDR_A_BS2<8,13>
DDR_A_BS0<8,13>
DDR_A_WE#<8,13>
DDR_A_CAS#<8,13>
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
CD22
RD1
@
+V_DDR_REFA_M3
+V_DDR_REF
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_SX_2VY~D
@
1
CD12
CD13
1
2
10K_0402_5%~D
1 2
10K_0402_5%~D
1 2
2
@
RD9
DIMM1_SA0
DIMM1_SA1
RD11
CD14
+
1
2
1U_0402_6.3V6K~D
1
CD18
2
10K_0402_5%~D
RD8
1 2
10K_0402_5%~D
@
RD10
1 2
1 2
1 2
RD2
@
JDIMM1STDTypeH=5.2
DDR_A_D0
DDR_A_D4
DDR_A_D7
DDR_A_D6
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D15
DDR_A_D14
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D19
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D30
DDR_A_D31
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR4
M_CLK_DDR#4
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D44
DDR_A_D45
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D62
DDR_A_D63
DIMM1_SA0
DIMM1_SA1
+1.5V_MEM
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
VSS1849DQ22
51
DQ18
DQ1953VSS19
VSS2055DQ28
57
DQ24
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1~D
CONN@
VREF_CA
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ23
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
+1.5V_MEM
DDR_A_D5
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D12
DDR_A_D13
DDR3_DRAMRST#_R
DDR_A_D10
DDR_A_D11
DDR_A_D20
DDR_A_D21
DDR_A_D18
DDR_A_D22
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D27
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR5
M_CLK_DDR#5
DDR_A_BS1
DDR_A_RAS#
M_ODT4
M_ODT5
DDR_A_D32
DDR_A_D33
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D50
DDR_A_D51
DDR_A_D61
DDR_A_D60
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D58
DDR_A_D59
+0.75V_DDR_VTT
DDR_CKE5_DIMM1 <8>
M_CLK_DDR5 <8>
M_CLK_DDR#5 <8>
DDR_A_BS1 <8,13>
DDR_A_RAS# <8,13>
DDR_CS4_DIMM1# <8>
M_ODT4 <8>
M_ODT5 <8>
Remove0ohm,duetolayoutspacelimitation.
CPU
+DIMM1_VREF_CA
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
CD19
1
1
2
2
CD20
JDIMM3 (Ch B1 H=9.2 STD)
JDIMM1 (Ch A1 H=5.2 STD)
TOP
BOT
JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
+1.5V_MEM
1K_0402_1%~D
12
RD4
DDR3_DRAMRST#_R<13,14,15> DDR3_DRAMRST# <7>
+DIMM0_1_VREF_CPU
DDR_HVREF_RST<7>
+DIMM0_1_CA_CPU
DDR_HVREF_RST
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RD7
@
1 2
0_0402_5%~D
DDR_XDP_WAN_SMBDAT <13,14,15,17,18,35,43>
DDR_XDP_WAN_SMBCLK <13,14,15,17,18,35,43>
1 2
RD3 1K_0402_1%~D
1 2
RD5 0_0402_5%~D@
S
1 2
RD6 0_0402_5%~D@
S
+V_DDR_REF
D
13
QD1
G
BSS138-G_SOT23-3
2
D
13
QD2
G
BSS138-G_SOT23-3
2
+V_DDR_REFA_M3
+V_DDR_REFB_M3
LinkCISOK
0722
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-7931P
LA-7931P
LA-7931P
1
12 70Monday, July 23, 2012
12 70Monday, July 23, 2012
12 70Monday, July 23, 2012
of
of
of
1.0
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Page 13
5
4
3
2
1
JDIMM3 (Ch B1 H=9.2 STD)
AllVREFtracesshould
have10miltracewidth
1
+
2
+V_DDR_REFA_M3
+V_DDR_REF
330U_SX_2VY~D
CD36
DDR_A_DQS#[0..7]<8,12>
D D
+1.5V_MEM
+1.5V_MEM
10U_0603_6.3V6M~D
C C
1
2
DDR_A_D[0..63]<8,12>
DDR_A_DQS[0..7]<8,12>
DDR_A_MA[0..15]<8,12>
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD27
2
2
10U_0603_6.3V6M~D
CD30
CD29
1
1
2
2
1U_0402_6.3V6K~D
1
1
CD24
CD25
CD28
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD31
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD32
1
2
10U_0603_6.3V6M~D
@
CD34
CD33
CD35
1
1
2
2
RD14
@
1 2
1 2
RD15
@
0_0402_5%~D
0_0402_5%~D
+DIMM2_VREF_DQ
2.2U_0603_6.3V6K~D
CD26
1
1
2
2
DDR_CKE0_DIMM2<8>
DDR_A_BS2<8,12>
0.1U_0402_16V4Z~D
CD23
LayoutNote:
PlacenearJDIMM3.Pin203,204
M_CLK_DDR0<8>
M_CLK_DDR#0<8>
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD38
CD37
2
2
B B
DIMMSelect
+3.3V_RUN
1 2
SA0 SA1
0 DIMM1
1
DIMM2
00
1
1
0
1
A A
DIMM3
DIMM4
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD40
CD39
2
2
10K_0402_5%~D
10K_0402_5%~D
@
@
RD18
RD17
1 2
DIMM2_SA0
DIMM2_SA1
10K_0402_5%~D
10K_0402_5%~D
RD19
RD20
1 2
+3.3V_RUN
DDR_A_BS0<8,12>
DDR_A_WE#<8,12>
DDR_A_CAS#<8,12>
DDR_CS1_DIMM2#<8>
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
1
1
+0.75V_DDR_VTT +0.75V_DDR_VTT
CD44
CD43
2
2
JDIMM2REVTypeH=5.2
DDR_A_D5
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D12
DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D20
DDR_A_D21
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D22
DDR_A_D28
DDR_A_D29
DDR_A_D26
DDR_A_D27
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D61
DDR_A_D60
DDR_A_D58
DDR_A_D59
DIMM2_SA0
DIMM2_SA1
+1.5V_MEM
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
TYCO_2-2013290-1
CONN@
VREF_CA
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
DQ4
DQ5
DQ6
DQ7
DM1
DM2
DM4
DM6
SDA
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
CK1
104
106
108
BA1
110
112
114
S0#
116
118
120
122
NC2
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
SCL
204
206
G2
+1.5V_MEM
DDR_A_D0
DDR_A_D4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D7
DDR_A_D6
DDR_A_D8
DDR_A_D9
DDR_A_D15
DDR_A_D14
DDR_A_D16
DDR_A_D17
DDR_A_D19
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D34
DDR_A_D35
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
CPU
DDR3_DRAMRST#_R <12,14,15>
DDR_CKE1_DIMM2 <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>
DDR_A_BS1 <8,12>
DDR_A_RAS# <8,12>
DDR_CS0_DIMM2# <8>
M_ODT0 <8>
M_ODT1 <8>
Remove0ohm,duetolayoutspacelimitation.
LinkCISOK
0722
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
JDIMM1 (Ch A1 H=5.2 STD)
TOP
BOT
JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
+DIMM2_VREF_CA
2.2U_0603_6.3V6K~D
CD41
1
2
RD16
@
1 2
0_0402_5%~D
0.1U_0402_16V4Z~D
CD42
1
2
DDR_XDP_WAN_SMBDAT <12,14,15,17,18,35,43>
DDR_XDP_WAN_SMBCLK <12,14,15,17,18,35,43>
+V_DDR_REF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-7931P
LA-7931P
LA-7931P
1
1.0
1.0
13 70Monday, July 23, 2012
13 70Monday, July 23, 2012
13 70Monday, July 23, 2012
1.0
of
of
Page 14
5
4
3
2
1
RD23
@
1 2
1 2
RD24
@
0_0402_5%~D
0_0402_5%~D
+V_DDR_REFB_M3
DDR_B_DQS#[0..7]<8,15>
D D
C C
DDR_B_D[0..63]<8,15>
DDR_B_DQS[0..7]<8,15>
DDR_B_MA[0..15]<8,15>
+1.5V_MEM
1
2
10U_0603_6.3V6M~D
CD51
+1.5V_MEM
1
2
10U_0603_6.3V6M~D
CD52
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD47
CD48
2
10U_0603_6.3V6M~D
CD53
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD50
CD49
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD55
CD54
CD56
1
1
2
2
+V_DDR_REF
DFX issue solution.
AllVREFtracesshould
have10miltracewidth
10U_0603_6.3V6M~D
330U_SX_2VY~D
@
1
CD58
CD57
1
+
2
2
LayoutNote:
PlacenearJDIMM3.Pin203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
B B
1
CD59
2
DIMMSelect
SA0 SA1
0 DIMM1
1
A A
1
001
0
1
5
1
2
DIMM2
DIMM3
DIMM4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD60
CD61
CD62
2
2
+3.3V_RUN
10K_0402_5%~D
10K_0402_5%~D
RD27
RD26
1 2
1 2
DIMM3_SA0
DIMM3_SA1
10K_0402_5%~D
10K_0402_5%~D
@
@
RD29
RD28
1 2
1 2
4
+DIMM3_VREF_DQ
0.1U_0402_16V4Z~D
2.2U_0402_6.3V6M~D
CD45
1
1
2
2
DDR_CKE6_DIMM3<8>
DDR_B_BS2<8,15>
M_CLK_DDR6<8>
M_CLK_DDR#6<8>
DDR_B_BS0<8,15>
DDR_B_WE#<8,15>
DDR_B_CAS#<8,15>
DDR_CS7_DIMM3#<8>
+3.3V_RUN
0.1U_0402_16V4Z~D
1
CD65
2
CD46
JDIMM3STDTypeH=9.2
JDIMM3
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013310-1~D
LinkCISOK_1006
follow connector list 1005A.
2.2U_0603_6.3V6K~D
1
CD66
2
DDR_B_D4
DDR_B_D5
DDR_B_D2
DDR_B_D3
DDR_B_D12
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR6
M_CLK_DDR#6
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D62
DDR_B_D63
DIMM3_SA0
DIMM3_SA1
+0.75V_DDR_VTT
CONN@
VREF_CA
EVENT#
3
+1.5V_MEM+1.5V_MEM
2
4
DQ4
6
DQ5
8
VSS3
10
12
DQS0
14
VSS6
16
DQ6
18
DQ7
20
VSS8
22
DQ12
24
DQ13
26
VSS10
28
DM1
30
32
34
DQ14
36
DQ15
38
40
DQ20
42
DQ21
44
46
DM2
48
VSS17
50
DQ22
52
DQ23
54
VSS19
56
DQ28
58
DQ29
60
VSS21
62
64
DQS3
66
68
DQ30
70
DQ31
72
74
CKE1
76
VDD2
78
A15
80
A14
82
VDD4
84
A11
86
A7
88
VDD6
90
A6
92
A4
94
VDD8
96
A2
98
A0
100
102
CK1
104
CK1#
106
VDD12
108
BA1
110
RAS#
112
VDD14
114
S0#
116
ODT0
118
VDD16
120
ODT1
122
NC2
124
VDD18
126
128
VSS28
130
DQ36
132
DQ37
134
VSS30
136
DM4
138
VSS31
140
DQ38
142
DQ39
144
VSS33
146
DQ44
148
DQ45
150
VSS35
152
DQS#5
154
DQS5
156
VSS38
158
DQ46
160
DQ47
162
VSS40
164
DQ52
166
DQ53
168
VSS42
170
DM6
172
VSS43
174
DQ54
176
DQ55
178
VSS45
180
DQ60
182
DQ61
184
VSS47
186
DQS#7
188
DQS7
190
VSS50
192
DQ62
194
DQ63
196
VSS52
198
200
SDA
202
SCL
204
VTT2
206
G2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR3_DRAMRST#_R
DDR_B_D10
DDR_B_D11
DDR_B_D20
DDR_B_D21
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR7
M_CLK_DDR#7
DDR_B_BS1
DDR_B_RAS#
M_ODT6
M_ODT7
DDR_B_D32
DDR_B_D33
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D42
DDR_B_D43
DDR_B_D52
DDR_B_D53
DDR_B_D50
DDR_B_D51
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D58
DDR_B_D59
+0.75V_DDR_VTT
DDR3_DRAMRST#_R <12,13,15>
DDR_CKE7_DIMM3 <8>
M_CLK_DDR7 <8>
M_CLK_DDR#7 <8>
DDR_B_BS1 <8,15>
DDR_B_RAS# <8,15>
DDR_CS6_DIMM3# <8>
M_ODT6 <8>
M_ODT7 <8>
DDR_XDP_WAN_SMBDAT <12,13,15,17,18,35,43>
DDR_XDP_WAN_SMBCLK <12,13,15,17,18,35,43>
Dueto+PWR_SRCtracewidthnearbyH16wasn’t
enough,wehavetoincreaseit.soremoveRD30&RD31.
+DIMM3_VREF_CA
2.2U_0603_6.3V6K~D
CD63
1
1
2
2
CPU
0.1U_0402_16V4Z~D
CD64
2
RD25
@
1 2
JDIMM3 (Ch B1 H=9.2 STD)
JDIMM1 (Ch A1 H=5.2 STD)
TOP
BOT
JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
0_0402_5%~D
+V_DDR_REF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT3
DDRIII-SODIMM SLOT3
DDRIII-SODIMM SLOT3
LA-7931P
LA-7931P
LA-7931P
1
14 70Monday, July 23, 2012
14 70Monday, July 23, 2012
14 70Monday, July 23, 2012
of
of
1.0
1.0
1.0
Page 15
5
4
3
2
1
AllVREFtracesshould
have10miltracewidth
DDR_B_DQS#[0..7]<8,14>
+1.5V_MEM
1
2
DDR_B_D[0..63]<8,14>
DDR_B_DQS[0..7]<8,14>
10U_0603_6.3V6M~D
DDR_B_MA[0..15]<8,14>
CD73
+1.5V_MEM
1
2
10U_0603_6.3V6M~D
CD74
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD68
CD67
2
10U_0603_6.3V6M~D
CD75
1
1
2
2
1U_0402_6.3V6K~D
1
1
CD69
CD70
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD77
CD76
CD78
1
1
2
2
D D
C C
+V_DDR_REFB_M3
+V_DDR_REF
10U_0603_6.3V6M~D
330U_SX_2VY~D
@
1
CD80
CD79
1
+
2
2
RD32
@
1 2
1 2
RD33
@
0_0402_5%~D
0_0402_5%~D
+DIMM4_VREF_DQ
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
CD71
1
1
2
2
DDR_CKE2_DIMM4<8>
DDR_B_BS2<8,14>
CD72
LayoutNote:
PlacenearJDIMM3.Pin203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1
2
CD83
+3.3V_RUN
1 2
1 2
1U_0402_6.3V6K~D
1
CD84
2
10K_0402_5%~D
10K_0402_5%~D
RD36
@
RD35
1 2
DIMM4_SA0
DIMM4_SA1
10K_0402_5%~D
10K_0402_5%~D
@
RD38
RD37
1 2
4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD82
CD81
2
B B
2
DIMMSelect
SA0 SA1
0 DIMM1
1
00
DIMM2
1
1
A A
DIMM3
0
1
DIMM4
5
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8,14>
DDR_B_WE#<8,14>
DDR_B_CAS#<8,14>
DDR_CS3_DIMM4#<8>
+3.3V_RUN
1
2
0.1U_0402_16V4Z~D
1
CD87
2
JDIMM4STDTypeH=5.2
CONN@
JDIMM4
VREF_DQ1VSS1
3
VSS2
DDR_B_D0
DDR_B_D1
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D20
DDR_B_D21
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D52
DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D60
DDR_B_D61
DDR_B_D58
DDR_B_D59
DIMM4_SA0
DIMM4_SA1
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
CD88
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1~D
VREF_CA
LinkCISOK
0722
3
+1.5V_MEM+1.5V_MEM
2
4
DQ4
6
DQ5
8
VSS3
10
DQS#0
12
DQS0
14
VSS6
16
DQ6
18
DQ7
20
VSS8
22
DQ12
24
DQ13
26
VSS10
28
DM1
30
32
34
DQ14
36
DQ15
38
40
DQ20
42
DQ21
44
46
DM2
48
VSS17
50
DQ22
52
DQ23
54
VSS19
56
DQ28
58
DQ29
60
VSS21
62
64
DQS3
66
68
DQ30
70
DQ31
72
74
CKE1
76
VDD2
78
A15
80
A14
82
VDD4
84
A11
86
A7
88
VDD6
90
A6
92
A4
94
VDD8
96
A2
98
A0
100
VDD10
102
CK1
104
CK1#
106
VDD12
108
BA1
110
RAS#
112
VDD14
114
S0#
116
ODT0
118
VDD16
120
ODT1
122
NC2
124
VDD18
126
128
VSS28
130
DQ36
132
DQ37
134
VSS30
136
DM4
138
VSS31
140
DQ38
142
DQ39
144
VSS33
146
DQ44
148
DQ45
150
VSS35
152
DQS#5
154
DQS5
156
VSS38
158
DQ46
160
DQ47
162
VSS40
164
DQ52
166
DQ53
168
VSS42
170
DM6
172
VSS43
174
DQ54
176
DQ55
178
VSS45
180
DQ60
182
DQ61
184
VSS47
186
DQS#7
188
DQS7
190
VSS50
192
DQ62
194
DQ63
196
VSS52
198
EVENT#
200
SDA
202
SCL
204
VTT2
206
G2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D34
DDR_B_D35
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
DIMM4_SMBDAT
DIMM4_SMBCLK
+0.75V_DDR_VTT
CPU
DDR3_DRAMRST#_R <12,13,14>
DDR_CKE3_DIMM4 <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8,14>
DDR_B_RAS# <8,14>
DDR_CS2_DIMM4# <8>
M_ODT2 <8>
M_ODT3 <8>
RD39 0_0402_5%~D@
RD40 0_0402_5%~D@
1 2
1 2
+DIMM4_VREF_CA
1
2
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
CD85
CD86
1
2
2
JDIMM3 (Ch B1 H=9.2 STD)
JDIMM1 (Ch A1 H=5.2 STD)
TOP
BOT
JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
RD34
@
1 2
0_0402_5%~D
DDR_XDP_WAN_SMBDAT <12,13,14,17,18,35,43>
DDR_XDP_WAN_SMBCLK <12,13,14,17,18,35,43>
+V_DDR_REF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT4
DDRIII-SODIMM SLOT4
DDRIII-SODIMM SLOT4
LA-7931P
LA-7931P
LA-7931P
1
1.0
1.0
15 70Monday, July 23, 2012
15 70Monday, July 23, 2012
15 70Monday, July 23, 2012
1.0
of
of
Page 16
5
+MXM_PWR_SRC
+5V_MXM
PEG_CRX_GTX_C_P[0..15]
PEG_CRX_GTX_C_N[0..15]
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
JMXM1A
1
PWR_SRC
3
PWR_SRC
5
PWR_SRC
7
PWR_SRC
9
PWR_SRC
11
PWR_SRC
13
PWR_SRC
15
PWR_SRC
17
PWR_SRC
19
GND
21
GND
23
GND
25
GND
27
GND
29
GND
31
GND
33
GND
35
GND
37
5V
39
5V
41
5V
43
5V
45
5V
47
GND
49
GND
51
GND
53
GND
55
PEX_STD_SW#
57
VGA_DISABLE#
59
PNL_PWR_EN
61
PNL_BL_EN
63
PNL_BL_PWM
65
HDMI_CEC
67
DVI_HPD
69
LVDS_DDC_DAT
71
LVDS_DDC_CLK
73
GND
75
OEM
77
OEM
79
OEM
81
OEM
83
GND
85
PEX_RX15#
87
PEX_RX15
89
GND
91
PEX_RX14#
93
PEX_RX14
95
GND
97
PEX_RX13#
99
PEX_RX13
101
GND
103
PEX_RX12#
105
PEX_RX12
107
GND
109
PEX_RX11#
111
PEX_RX11
113
GND
115
PEX_RX10#
117
PEX_RX10
119
GND
121
PEX_RX9#
123
PEX_RX9
125
GND
127
PEX_RX8#
129
PEX_RX8
131
GND
133
PEX_RX7#
135
PEX_RX7
137
GND
139
PEX_RX6#
141
PEX_RX6
143
GND
145
PEX_RX5#
147
PEX_RX5
149
GND
151
PEX_RX4#
153
PEX_RX4
155
GND
157
PEX_RX3#
159
PEX_RX3
161
GND
JAE_MM70-314-310B1-1-R300
PEG_CRX_GTX_C_P[0..15]<6>
PEG_CRX_GTX_C_N[0..15]<6>
PEG_CTX_GRX_P[0..15]<6>
PEG_CTX_GRX_N[0..15]<6>
D D
+5V_MXM
10U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
C328
1
1
C7
2
2
100mil(2.5A, 5VIA)
1 2
R1970 0_0402_5%~D@
1 2
R1971 0_0402_5%~D@
MXM_ENVDD<28>
C C
B B
MXM_PANEL_BKEN<28>
MXM_BIA_PWM<28>
MXM_LVDS_DDC_DAT<27>
MXM_LVDS_DDC_CLK<27>
PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P15
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_P3
CONN@
E1 E2
E3 E4
+3.3V_MXM
1 2
R3 4.3K_0402_5%@
1 2
R5 4.3K_0402_5%@
1 2
R8 10K_0402_5%~D
1 2
R7 10K_0402_5%~D
Heightlimitationissue.
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT_R#
WAKE#
PWR_GOOD
PWR_EN
RSVD
RSVD
RSVD
RSVD
PWR_LEVEL
TH_OVERT#
TH_ALERT#
TH_PWM
GPIO0
GPIO1
GPIO2
SMB_DAT
SMB_CLK
GND
OEM
OEM
OEM
OEM
GND
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
LinkCISOK
0722
+3.3V_ALW +3.3V_RUN
0.1U_0402_10V7K~D
+3.3V_MXM
1
C90
RV29
750_0402_1%~D
DGPU_PEX_RST#
MeethighlevelforDGPU_PEX_RST#
onN14P
A A
MXM_DPC_HPD
MXM_MB_DP_HPD
DPC_GPU_HPD
2
1 2
4
Y
DV2
2 1
RB751VM-40TE-17_SOD323-2~D
DV3
2 1
RB751VM-40TE-17_SOD323-2~D
DV4
2 1
RB751VM-40TE-17_SOD323-2~D
5
100K_0402_5%~D
12
R36
5
1
B
VCC
2
A
G
U16
3
MC74VHC1G09DFT2G_SC70-5
DGPU_HOLD_RST# <21>
PLTRST_GPU# <20>
MXM_DP_HDMI_HPD <48>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
DGPU_PWROK<21,48>
DPC_GPU_HPD_GATE
4
MXM_CRT_DDC_DAT
MXM_CRT_DDC_CLK
DGPU_PWR_GOOD
MXM_CLK_REQ#
400mil(10A)
10U_0805_25V6K~D
1
C2
2
1 2
R1972 0_0402_5%~D@
DGPU_PWR_GOOD
MXM_PWR_LEVEL
MXM_OVERT#
MXM_ALERT#
GPU_SMBDAT_R
GPU_SMBCLK_R
SYSTEM
PEG_CTX_GRX_N15
PEG_CTX_GRX_P15
PEG_CTX_GRX_N14
PEG_CTX_GRX_P14
PEG_CTX_GRX_N13
PEG_CTX_GRX_P13
PEG_CTX_GRX_N12
PEG_CTX_GRX_P12
PEG_CTX_GRX_N11
PEG_CTX_GRX_P11
PEG_CTX_GRX_N10
PEG_CTX_GRX_P10
PEG_CTX_GRX_N9
PEG_CTX_GRX_P9
PEG_CTX_GRX_N8
PEG_CTX_GRX_P8
PEG_CTX_GRX_N7
PEG_CTX_GRX_P7
PEG_CTX_GRX_N6
PEG_CTX_GRX_P6
PEG_CTX_GRX_N5
PEG_CTX_GRX_P5
PEG_CTX_GRX_N4
PEG_CTX_GRX_P4
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
74AHC1G08GW_SOT353-5~D
C1330
100K_0402_5%~D
@
R758
1 2
4
680P_0603_50V7K~D
1
C3
2
0.1U_0402_10V7K~D
C91
U8
0.1U_0402_10V7K~D
1
2
4
+MXM_PWR_SRC
68P_0402_50V8J~D
0.1U_0603_25V7K~D
1
1
C4
2
2
+3.3V_RUN
1
2
5
P
IN1
4
O
IN2
G
3
+3.3V_MXM
5
1
P
IN1
O
2
IN2
G
U641
3
74AHC1G08GW_SOT353-5~D
C1
MXM_PRESENTR# <21>
PCIE_WAKE# <42,43,47,49>
DGPU_PWR_EN <48>
LVDS_Upper/even
HDMI/DockingDP
MUX
1
DGPU_PWR_GOOD
2
DGPU_PWR_EN
DGPU_PWROK
DPC_GPU_HPD <46>
MBDP
3
+3.3V_MXM
10K_0402_5%~D
R4
MXM_ALERT#
CLK_PCIE_VGA#<18>
CLK_PCIE_VGA<18>
2011/09/01 change.
MXM_LVDS_BCLK-<27>
MXM_LVDS_BCLK+<27>
MXM_LVDS_B2-<27>
MXM_LVDS_B2+<27>
MXM_LVDS_B1-<27>
MXM_LVDS_B1+<27>
MXM_LVDS_B0-<27>
MXM_LVDS_B0+<27>
MXM_DPC_N0<34>
MXM_DPC_P0<34>
MXM_DPC_N1<34>
MXM_DPC_P1<34>
MXM_DPC_N2<34>
MXM_DPC_P2<34>
MXM_DPC_N3<34>
MXM_DPC_P3<34>
MXM_DPC_AUX#<34,45>
MXM_DPC_AUX<34,45>
MXM_MB_DP_N0<29>
MXM_MB_DP_P0<29>
MXM_MB_DP_N1<29>
MXM_MB_DP_P1<29>
MXM_MB_DP_N2<29>
MXM_MB_DP_P2<29>
MXM_MB_DP_N3<29>
MXM_MB_DP_P3<29>
MXM_MB_DP_AUX#<29>
MXM_MB_DP_AUX<29>
MXM_PRESENTL#<21>
C1328
MXM_DPC_HPD_GATE
100K_0402_5%~D
@
R2124
1 2
DYN_TURB_GPU_PWR_ALRT#<26,49>
3
2
+3.3V_MXM
4.7K_0402_5%~D
4.7K_0402_5%~D
12
12
@
PEX_TX2#
PEX_TX2
PEX_TX1#
PEX_TX1
PEX_TX0#
PEX_TX0
PEX_RST#
VGA_DDC_DAT
VGA_DDC_CLK
VGA_VSYNC
VGA_HSYNC
VGA_RED
VGA_GREEN
VGA_BLUE
LVDS_LCLK#
LVDS_LCLK
LVDS_LTX3#
LVDS_LTX3
LVDS_LTX2#
LVDS_LTX2
LVDS_LTX1#
LVDS_LTX1
LVDS_LTX0#
LVDS_LTX0
DP_D_L0#
DP_D_L0
DP_D_L1#
DP_D_L1
DP_D_L2#
DP_D_L2
DP_D_L3#
DP_D_L3
DP_D_AUX#
DP_D_AUX
DP_C_HPD
DP_D_HPD
RSVD
RSVD
RSVD
DP_B_L0#
DP_B_L0
DP_B_L1#
DP_B_L1
DP_B_L2#
DP_B_L2
DP_B_L3#
DP_B_L3
DP_B_AUX#
DP_B_AUX
DP_B_HPD
DP_A_HPD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3V3
3V3
GND
R1
DMN66D0LDW-7_SOT363-6~D
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270
272
274
276
278
280
282
284
286
288
290
292
294
296
298
300
302
304
306
308
312
12
G
2
13
D
S
Q5
SSM3K7002FU_SC70-3~D
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P0
CLK_PCIE_VGA#
CLK_PCIE_VGA
MXM_LVDS_BCLKMXM_LVDS_BCLK+
MXM_LVDS_B2MXM_LVDS_B2+
MXM_LVDS_B1MXM_LVDS_B1+
MXM_LVDS_B0MXM_LVDS_B0+
MXM_DPC_N0
MXM_DPC_P0
MXM_DPC_N1
MXM_DPC_P1
MXM_DPC_N2
MXM_DPC_P2
MXM_DPC_N3
MXM_DPC_P3
MXM_DPC_AUX#
MXM_DPC_AUX
MXM_MB_DP_N0
MXM_MB_DP_P0
MXM_MB_DP_N1
MXM_MB_DP_P1
MXM_MB_DP_N2
MXM_MB_DP_P2
MXM_MB_DP_N3
MXM_MB_DP_P3
MXM_MB_DP_AUX#
MXM_MB_DP_AUX
MXM_PRESENTL#
DGPU_ALERT# <48>
JMXM1B
CONN@
163
GND
165
PEX_RX2#
167
PEX_RX2
169
GND
171
PEX_RX1#
173
PEX_RX1
175
GND
177
PEX_RX0#
179
PEX_RX0
181
GND
183
PEX_REFCLK#
185
PEX_REFCLK
187
GND
189
RSVD
191
RSVD
193
RSVD
195
RSVD
197
RSVD
199
LVDS_UCLK#
201
LVDS_UCLK
203
GND
205
LVDS_UTX3#
207
LVDS_UTX3
209
GND
211
LVDS_UTX2#
213
LVDS_UTX2
215
GND
217
LVDS_UTX1#
219
LVDS_UTX1
221
GND
223
LVDS_UTX0#
225
LVDS_UTX0
227
GND
229
DP_C_L0#
231
DP_C_L0
233
GND
235
DP_C_L1#
237
DP_C_L1
239
GND
241
DP_C_L2#
243
DP_C_L2
245
GND
247
DP_C_L3#
249
DP_C_L3
251
GND
253
DP_C_AUX#
255
DP_C_AUX
257
RSVD
259
RSVD
261
RSVD
263
RSVD
265
RSVD
267
RSVD
269
RSVD
271
RSVD
273
RSVD
275
RSVD
277
RSVD
279
RSVD
281
GND
283
DP_A_L0#
285
DP_A_L0
287
GND
289
DP_A_L1#
291
DP_A_L1
293
GND
295
DP_A_L2#
297
DP_A_L2
299
GND
301
DP_A_L3#
303
DP_A_L3
305
GND
307
DP_A_AUX#
309
DP_A_AUX
310
PRSNT_L#
311
GND
JAE_MM70-314-310B1-1-R300
GPU_SMBDAT_R
GPU_SMBCLK_R
PEX_CLK_REQ#
LinkCISOK
+3.3V_MXM
+3.3V_MXM
0.1U_0402_10V7K~D
1
2
5
1
DGPU_PWROK
P
IN1
4
O
2
MXM_DPC_HPD <34>
IN2
G
U640
3
74AHC1G08GW_SOT353-5~D
+3.3V_MXM
MXM_PWR_LEVEL
D102
RB751VM-40TE-17_SOD323-2~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_ALW
100K_0402_5%~D
12
R2063
4
Y
@
21
MXM_MB_DP_HPD_GATE
0.1U_0402_10V7K~D
1
C1264
2
5
1
B
VCC
2
A
G
U634
3
MC74VHC1G09DFT2G_SC70-5
2
0.1U_0402_10V7K~D
1
C1329
2
4
U639
74AHC1G08GW_SOT353-5~D
ACAV_IN <25,49,62,63>
GPU_PWR_LEVEL <48>
O
+3.3V_MXM
@
R2
5
DMN66D0LDW-7_SOT363-6~D
3
4
Q295B
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
MXM_CLK_REQ#
DGPU_PEX_RST#
MXM_CRT_VSYNC
MXM_CRT_HSYNC
MXM_CRT_RED
MXM_CRT_GRN
MXM_CRT_BLU
MXM_LVDS_ACLKMXM_LVDS_ACLK+
MXM_LVDS_A2MXM_LVDS_A2+
MXM_LVDS_A1MXM_LVDS_A1+
MXM_LVDS_A0MXM_LVDS_A0+
MXM_EDP_TX0MXM_EDP_TX0+
MXM_EDP_TX1MXM_EDP_TX1+
MXM_EDP_C_AUXMXM_EDP_C_AUX+
MXM_DPC_HPD_GATE
MXM_EDP_HPD
1 2
R2194 0_0402_5%~D@
1 2
R2195 0_0402_5%~D@
MXM_DPB_N0
MXM_DPB_P0
MXM_DPB_N1
MXM_DPB_P1
MXM_DPB_N2
MXM_DPB_P2
MXM_DPB_N3
MXM_DPB_P3
MXM_DPB_AUX#
MXM_DPB_AUX
DPC_GPU_HPD_GATE
MXM_MB_DP_HPD_GATE
40mil(1A)
2
Q295A
+3.3V_MXM
61
C1297 0.1U_0402_10V6K~D6@
C1298 0.1U_0402_10V6K~D6@
GPU_SMBDAT <49>
GPU_SMBCLK <49>
MXM_CRT_DDC_DAT <32>
MXM_CRT_DDC_CLK <32>
MXM_CRT_VSYNC <32>
MXM_CRT_HSYNC <32>
MXM_CRT_RED <32>
MXM_CRT_GRN <32>
MXM_CRT_BLU <32>
MXM_LVDS_ACLK- <27>
MXM_LVDS_ACLK+ <27>
MXM_LVDS_A2- <27>
MXM_LVDS_A2+ <27>
MXM_LVDS_A1- <27>
MXM_LVDS_A1+ <27>
MXM_LVDS_A0- <27>
MXM_LVDS_A0+ <27>
MXM_EDP_TX0- <30>
MXM_EDP_TX0+ <30>
MXM_EDP_TX1- <30>
MXM_EDP_TX1+ <30>
1 2
1 2
MXM_EDP_HPD <30>
+3.3V_MXM
MXM_DPB_N0 <46>
MXM_DPB_P0 <46>
MXM_DPB_N1 <46>
MXM_DPB_P1 <46>
MXM_DPB_N2 <46>
MXM_DPB_P2 <46>
MXM_DPB_N3 <46>
MXM_DPB_P3 <46>
MXM_DPB_AUX# <33>
MXM_DPB_AUX <33>
changefrom+3.3V_RUNto+3.3V_AVDD.
MXM_EDP_AUX-
MXM_EDP_AUX+
change to 6@ for only 10-bit panel use.
5
1
DGPU_PWROK
P
IN1
2
MXM_MB_DP_HPD <29>
IN2
G
3
+3.3V_MXM
10K_0402_5%~D
R10
MXM_OVERT#
+3.3V_ALW
12
G
2
13
D
S
Q4
SSM3K7002FU_SC70-3~D
10K_0402_5%~D
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MXM3
MXM3
MXM3
LA-7931P
LA-7931P
LA-7931P
1
2011/09/01 change.
LVDS_Lower/odd
MXM_EDP_AUX- <30>
MXM_EDP_AUX+ <30>
ForNVDIArequest.
DMC/DockingDP
MUX
R2095
6@
1 2
1 2
R2096
6@
+3.3V_MXM
10U_0603_6.3V6M~D
1
2
R11
DGPU_THERMTRIP# <25>
1
CRT
100K_0402_5%~D
100K_0402_5%~D
0.1U_0402_16V4Z~D
1
C332
C8
2
16 70Monday, July 23, 2012
16 70Monday, July 23, 2012
16 70Monday, July 23, 2012
of
eDP
+3.3V_AVDD
1.0
1.0
1.0
Page 17
5
+3.3V_ALW_PCH
12
RH66
1K_0402_1%~D
PCH_AZ_SYNC
12
D D
C C
B B
RH282
100K_0402_5%~D
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
+RTC_CELL
12
RH38
330K_0402_1%~D
PCH_INTVRMEN
12
@
330K_0402_1%~D
INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable Internal VRs
Low - Enable External VRs
1 2
RH31 1M_0402_5%~D
PCH_AZ_SYNCissampled
attherisingedgeofRSMRST#pin.
SosignalshouldbePUtotheALWAYSrail.
@
RH39
Shunt
Open
ME_CLR1
TPM setting
Shunt Clear ME RTC Registers
Keep ME RTC Registers
Open
PCH_AZ_CODEC_SDOUT<47>
PCH_AZ_CODEC_SYNC<47>
PCH_AZ_CODEC_RST#<47>
PCH_AZ_CODEC_BITCLK<47>
CMOS settingCMOS_CLR1
Clear CMOS
Keep CMOS
27P_0402_50V8J~D
1
@
ME1 SHORT PADS~D
@
CH101
RH22 20K_0402_5%~D
+RTC_CELL
RH23 20K_0402_5%~D
RH11 1M_0402_5%~D
2
1
2
1 2
CH5 1U_0402_6.3V6K~D
+3.3V_ALW_PCH
12
JTAG@
RH288
0_0603_5%~D
+3.3V_ALW_PCH_JTAG
1 2
RH29 33_0402_5%~D
RH27 33_0402_5%~D
RH41 33_0402_5%~D
RH25 33_0402_5%~D
1
2
+5V_RUN
G
2
S
PCH_AZ_SDOUT
1 2
PCH_AZ_SYNC_Q
1 2
PCH_AZ_RST#
1 2
PCH_AZ_BITCLK
QH7
SSM3K7002FU_SC70-3~D
13
PCH_AZ_SYNCPCH_AZ_SYNC_Q
D
SLP_ME_CSW_DEV#<21,48>
PCH_GPIO35<21>
1 2
1 2
1 2
INTELHDA_SYNCisolationcircuit
A A
1 2
SPI_PCH_CS0# SPI_PCH_CS0#_R
R963 47_0402_5%~D
1 2
SPI_PCH_DIN SPI_DIN64
R894 33_0402_5%~D
SPI_WP#_SEL<48>
1 2
R898 0_0402_5%~D@
5
R890
3.3K_0402_5%~D
SPI_WP#_SEL_R
12
200 MIL SO8
64Mb Flash ROM
U52
X76@
1
/CS
2
DO
3
/WP
GND4DIO
CreateX76BOMfor2ndsource.
USB_OC0#_R<20>
USB_OC1#_R<20>
USB_OC2#<20>
USB_OC3#<20,47>
USB_OC4#_R<20>
USB_OC5#<20>
USB_OC6#<20>
SIO_EXT_SMI#<20,49>
PCH_GPIO36<21>
PCH_GPIO37<21>
PCH_GPIO16<21>
TEMP_ALERT#<21,48>
PCH_GPIO15<21>
SIO_EXT_SCI#_R<21>
PCH_RSMRST#_Q<19,50>
Crystal EA.
1
@
CMOS1 SHORT PADS~D
CH4
CMOS place near DIMM
U52
U53
+3.3V_SPI
8
VCC
7
/HOLD
6
CLK
5
W25Q64FVSSIG_SO8~D
4
Pop them until ST.
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
SLP_ME_CSW_DEV#
PCH_GPIO35
HDD_DET#_R
BBS_BIT0_R
PCH_GPIO36
PCH_GPIO37
PCH_GPIO16
TEMP_ALERT#
PCH_GPIO15
SIO_EXT_SCI#_R
PCH_RSMRST#_Q RSMRST#_XDP
CH2
18P_0402_50V8J~D
12
12
CH3
18P_0402_50V8J~D
12
PCH_RTCX2_R PCH_RTCX2
2
1
2
1 2
1U_0402_6.3V6K~D
+3.3V_ALW_PCH
ME_FWP<48>
12
RH59 51_0402_1%~DJTAG@
12
RH44 200_0402_1%~DJTAG@
12
RH45 200_0402_1%~DJTAG@
12
RH43 200_0402_1%~DJTAG@
Pop them until ST.
1 2
RH51 33_0402_5%~DPXDP@
1 2
RH7 33_0402_5%~DPXDP@
1 2
RH16 33_0402_5%~DPXDP@
1 2
RH5 33_0402_5%~DPXDP@
1 2
RH6 33_0402_5%~DPXDP@
1 2
RH14 33_0402_5%~DPXDP@
1 2
RH8 33_0402_5%~DPXDP@
1 2
RH9 33_0402_5%~DPXDP@
1 2
RH10 33_0402_5%~DPXDP@
1 2
RH12 33_0402_5%~DPXDP@
1 2
RH13 33_0402_5%~DPXDP@
1 2
RH26 33_0402_5%~DPXDP@
1 2
RH20 33_0402_5%~DPXDP@
1 2
RH34 33_0402_5%~DPXDP@
1 2
RH17 33_0402_5%~DPXDP@
1 2
RH18 33_0402_5%~DPXDP@
1 2
RH19 33_0402_5%~DPXDP@
1 2
RH53 33_0402_5%~DPXDP@
1 2
RH24 1K_0402_1%~DPXDP@
PCH_RTCX1
YH1
32.768KHZ_12.5PF_Q13FC1350000~D
1 2
RH286 0_0402_5%~D@
SPKR<47>
PCH_AZ_CODEC_SDIN0<47>
1 2
RH287 1K_0402_1%~D@
1 2
RH50 1K_0402_1%~D
100_0402_1%~DJTAG@
100_0402_1%~DJTAG@
12
12
12
RH48
RH49
12
100_0402_1%~DJTAG@
RH47
BIOS ROM Select Component
SPI_HOLD#
SPI_PCH_CLK
SPI_PCH_DO
X76(2nd)
X7640631L03
EON
SA000046400
(EN25Q64-104HIP)
SA00004LI00
(EN25Q32B-104HIP)
X76(Main)
X7640631L01
WINBOND
SA000039A2L
(W25Q64FVSSIG)
SA00003K80L
(W25Q32BVSSIG)
12
3.3K_0402_5%~D
1 2
SPI_CLK64
R899 33_0402_5%~D
1 2
SPI_DO64
R901 33_0402_5%~D
4
C787
1 2
0.1U_0402_25V6K~D
R891
3
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17
RH15
10M_0402_5%~D
PCH_RTCRST#
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_SDOUT
PCH_GPIO33
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
A20
C20
D20
G22
K22
C17
N34
K34
E34
G34
C34
A34
A36
C36
N32
Y14
SPI_PCH_CS1# SPI_PCH_CS1#_R
SPI_PCH_DIN SPI_DIN32
SPI_WP#_SEL_R
@
33_0402_5%~D
SPI_CLK32
@
33_0402_5%~D
SPI_CLK64
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DDR_XDP_WAN_SMBDAT<12,13,14,15,18,35,43>
DDR_XDP_WAN_SMBCLK<12,13,14,15,18,35,43>
UH4A
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
BD82PPSM-QNHN-A0_BGA989~D
1 2
R936 47_0402_5%~D
1 2
R895 33_0402_5%~D
R2065
R2066
12
12
C1265
@
10P_0402_50V8J~D
1 2
C1266
@
10P_0402_50V8J~D
1 2
Pop them until ST.
+3.3V_ALW_PCH
1.05V_0.8V_PWROK<49,60>
SIO_PWRBTN#_R<7,19>
RH284 0_0402_5%~DPXDP@
RH285 0_0402_5%~D
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
FWH4 / LFRAME#
LDRQ1# / GPIO23
RTCIHDA
SATA 6G
SATA
SATAICOMPO
SATAICOMPI
JTAG
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATA0GP / GPIO21
SPI
SATA1GP / GPIO19
200 MIL SO8
32Mb Flash ROM
U53
1
CS#
2
DO
3
WP#
4
GND
W25Q32BVSSIG_SO8~D
CreateX76BOMfor2ndsource.
0.1U_0402_25V6K~D
PXDP@
1
CH1
2
RH283 1K_0402_1%~DPXDP@
1 2
1 2
RH21 0_0402_5%~D
PXDP@
1 2
DDR_XDP_WAN_SMBDAT_R2
1 2
DDR_XDP_WAN_SMBCLK_R2
PXDP@
C38
A38
B37
C37
D36
E36
LDRQ0#
K36
V5
SERIRQ
AM3
SATA0RXN
AM1
SATA0RXP
AP7
SATA0TXN
AP5
SATA0TXP
AM10
SATA1RXN
AM8
SATA1RXP
AP11
SATA1TXN
AP10
SATA1TXP
AD7
SATA2RXN
AD5
SATA2RXP
AH5
SATA2TXN
AH4
SATA2TXP
AB8
SATA3RXN
AB10
SATA3RXP
AF3
SATA3TXN
AF1
SATA3TXP
Y7
SATA4RXN
Y5
SATA4RXP
AD3
SATA4TXN
AD1
SATA4TXP
Y3
SATA5RXN
Y1
SATA5RXP
AB3
SATA5TXN
AB1
SATA5TXP
Y11
Y10
AB12
AB13
AH1
P3
SATALED#
V14
P1
X76@
VCC
HOLD#
CLK
DI
2
1.05V_0.8V_PWROK_R
PCH_PWRBTN#_XDP
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
LPC_LDRQ1#
IRQ_SERIRQ
SATA_COMP
SATA3_COMP
RBIAS_SATA3
SATA_ACT#
HDD_DET#_R
BBS_BIT0_R
+3.3V_SPI
8
7
6
5
SPI_DO32
2
+3.3V_ALW_PCH
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
LPC_LAD0 <41,42,48,49>
LPC_LAD1 <41,42,48,49>
LPC_LAD2 <41,42,48,49>
LPC_LAD3 <41,42,48,49>
LPC_LFRAME# <41,42,48,49>
LPC_LDRQ1# <48>
IRQ_SERIRQ <41,48,49>
PSATA_PRX_DTX_N0_C <35>
PSATA_PRX_DTX_P0_C <35>
PSATA_PTX_DRX_N0_C <35>
PSATA_PTX_DRX_P0_C <35>
SATA_NVRAM_PRX_DTX_N2_C <43>
SATA_NVRAM_PRX_DTX_P2_C <43>
SATA_NVRAM_PTX_DRX_N2_C <43>
SATA_NVRAM_PTX_DRX_P2_C <43>
SATA_ODD_PRX_DTX_N3_C <36>
SATA_ODD_PRX_DTX_P3_C <36>
SATA_ODD_PTX_DRX_N3_C <36>
SATA_ODD_PTX_DRX_P3_C <36>
ESATA_PRX_DTX_N4_C <39>
ESATA_PRX_DTX_P4_C <39>
ESATA_PTX_DRX_N4_C <39>
ESATA_PTX_DRX_P4_C <39>
SATA_PRX_DKTX_N5_C <46>
SATA_PRX_DKTX_P5_C <46>
SATA_PTX_DKRX_N5_C <46>
SATA_PTX_DKRX_P5_C <46>
1 2
RH40 37.4_0402_1%~D
1 2
RH42 49.9_0402_1%~D
1 2
RH46 750_0402_1%~D
SATA_ACT# <51>
RH290 0_0402_5%~D@
+3.3V_SPI
C788
1 2
0.1U_0402_25V6K~D
1 2
R897 33_0402_5%~D
1 2
R900 33_0402_5%~D
1
JXDP2
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A CONN@
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
GND17
2
4
XDP_FN16
6
XDP_FN17
8
10
XDP_FN8
12
XDP_FN9
14
16
XDP_FN10
18
XDP_FN11
20
22
24
26
28
XDP_FN12
30
XDP_FN13
32
34
XDP_FN14
36
XDP_FN15
38
40
42
44
46
RSMRST#_XDP
48
XDP_DBRESET#
50
52
PCH_JTAG_TDO
TD0
54
56
PCH_JTAG_TDI
TDI
58
PCH_JTAG_TMSPCH_JTAG_TCK
TMS
60
LinkCISOK
0722
+1.05V_RUN
+1.05V_RUN
1 2
SPI_HOLD#
SPI_PCH_CLKSPI_CLK32
SPI_PCH_DO
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
PCH_GPIO33
IRQ_SERIRQ
BBS_BIT0_R
HDD1_DET#
SPKR
No Reboot Strap
SPKR
HDD1
NVRAM
ODD
E-SATA
DOCK
HDD1_DET# <35>
12
SPI_PCH_CS1#
PCH_SPI_CS1#
RH3450_0402_5%~D
12
SPI_PCH_DO
PCH_SPI_DO
RH3460_0402_5%~D
12
SPI_PCH_DIN
PCH_SPI_DIN
RH3470_0402_5%~D
12
SPI_PCH_CLK
PCH_SPI_CLK
RH3480_0402_5%~D
12
SPI_PCH_CS0#
PCH_SPI_CS0#
RH3490_0402_5%~D
+3.3V_M
12
RH3500_0402_5%~D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PCH (1/8)
PCH (1/8)
PCH (1/8)
LA-7931P
LA-7931P
LA-7931P
1
Low = Default
High = No Reboot
Followconnlist1223A.
LinkCISOK
0109
+3.3V_ALW_PCH
XDP_DBRESET# <7,19>
1 2
RH355100K_0402_5%~D
1 2
RH288.2K_0402_5%~D
1 2
RH524.7K_0402_5%~D
1 2
RH3010K_0402_5%~D
1 2
RH3510K_0402_5%~D @
CONN@
JSPI1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
GND
18
GND
TYCO_1-2041070-6~D
17 70Monday, July 23, 2012
17 70Monday, July 23, 2012
17 70Monday, July 23, 2012
+3.3V_RUN
+3.3V_RUN
of
1.0
1.0
1.0
Page 18
5
D D
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5
PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
PCIE_PRX_MMITX_N8
PCIE_PRX_MMITX_P8
PCIE_PTX_MMIRX_N8
PCIE_PTX_MMIRX_P8
RH307 0_0402_5%~D@
RH308 0_0402_5%~D@
RH81 10K_0402_5%~D
RH82 0_0402_5%~D@
RH83 0_0402_5%~D@
RH85 0_0402_5%~D@
RH86 0_0402_5%~D@
1 2
RH87 10K_0402_5%~D
RH88 0_0402_5%~D@
RH90 0_0402_5%~D@
RH152 10K_0402_5%~D
RH92 0_0402_5%~D@
RH93 0_0402_5%~D@
RH94 10K_0402_5%~D
RH95 0_0402_5%~D@
RH96 0_0402_5%~D@
RH97 10K_0402_5%~D
1 2
RH98 10K_0402_5%~D
1 2
RH368 10K_0402_5%~D
1 2
RH369 10K_0402_5%~D
1 2
RH280 0_0402_5%~D@
1 2
RH281 0_0402_5%~D@
WWAN/
NVRAM (Mini Card 2)--->
WLAN (Mini Card 1)--->
EXPRESS Card--->
PP (Mini Card 3)--->
C C
10/100/1G LAN --->
MMI --->
WWAN/
NVRAM (Mini Card 2)--->
10/100/1G LAN --->
MMI --->
B B
PP (Mini Card 3)--->
Express card--->
WLAN (Mini Card 1)--->
A A
PCIEREQpowerrail:
Suspend:034567
PCIE_PTX_WANRX_N1<43>
PCIE_PTX_WANRX_P1<43>
PCIE_PTX_WLANRX_N2<42>
PCIE_PTX_WLANRX_P2<42>
PCIE_PTX_EXPRX_N3<47>
PCIE_PTX_EXPRX_P3<47>
PCIE_PRX_WPANTX_N5<42>
PCIE_PRX_WPANTX_P5<42>
PCIE_PTX_WPANRX_N5<42>
PCIE_PTX_WPANRX_P5<42>
PCIE_PTX_GLANRX_N7<37>
PCIE_PTX_GLANRX_P7<37>
PCIE_PTX_MMIRX_N8<47>
PCIE_PTX_MMIRX_P8<47>
PCIE_PRX_WANTX_N1<43>
PCIE_PRX_WANTX_P1<43>
PCIE_PRX_WLANTX_N2<42>
PCIE_PRX_WLANTX_P2<42>
PCIE_PRX_EXPTX_N3<47>
PCIE_PRX_EXPTX_P3<47>
PCIE_PRX_GLANTX_N7<37>
PCIE_PRX_GLANTX_P7<37>
PCIE_PRX_MMITX_N8<47>
PCIE_PRX_MMITX_P8<47>
CLK_PCIE_MINI1#<43>
CLK_PCIE_MINI1<43>
+3.3V_ALW_PCH
MINI1CLK_REQ#<43>
CLK_PCIE_LAN#<37>
CLK_PCIE_LAN<37>
LANCLK_REQ#<37>
CLK_PCIE_CARD#<47>
CLK_PCIE_CARD<47>
+3.3V_RUN
CARDCLK_REQ#<47>
CLK_PCIE_MINI3#<42>
CLK_PCIE_MINI3<42>
+3.3V_ALW_PCH
MINI3CLK_REQ#<42>
CLK_PCIE_EXP#<47>
CLK_PCIE_EXP<47>
+3.3V_ALW_PCH
EXPCLK_REQ#<47>
CLK_PCIE_MINI2#<42>
CLK_PCIE_MINI2<42>
+3.3V_ALW_PCH
MINI2CLK_REQ#<42>
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
CLK_CPU_ITP#<7>
CLK_CPU_ITP<7>
Core:12
5
4
MEM_SMBCLK
MEM_SMBDATA
BG34
BJ34
AV32
AU32
BE34
BF34
BB32
AY32
BG36
BJ36
AV34
AU34
BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
4
PCIE_MINI1#
PCIE_MINI1
MINI1CLK_REQ#
PCIE_LAN#
PCIE_LAN
LANCLK_REQ#
PCIE_CARD#
PCIE_CARD
CARDCLK_REQ#
PCIE_MINI3#
PCIE_MINI3
MINI3CLK_REQ#
PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#
PCIE_MINI2#
PCIE_MINI2
MINI2CLK_REQ#
PEG_B_CLKRQ#
PCIECLKRQ6#
PCIECLKRQ7#
CLK_BCLK_ITP#
AB49
AB47
AA48
AA47
AB42
AB40
AK14
AK13
+3.3V_RUN
6 1
5
DMN66D0LDW-7_SOT363-6~D
3
4
DMN66D0LDW-7_SOT363-6~D
UH4B
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
BD82PPSM-QNHN-A0_BGA989~D
2
QH5A
QH5B
PCI-E*
3
DDR_XDP_WAN_SMBCLK <12,13,14,15,17,35,43>
DDR_XDP_WAN_SMBDAT <12,13,14,15,17,35,43>
E12
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
Link
CLOCKS
FLEX CLOCKS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA
PCH_GPIO74
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
GFX_CLK_REQ#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
CLK_PCI_LOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
PCI_TPM_TCM
SIO_14M
CLK_80H
JETWAY_14MCLK_BCLK_ITP
RH100 90.9_0402_1%~D
RH311 22_0402_5%~D
RH313 22_0402_5%~D
RH314 22_0402_5%~D
RH315 22_0402_5%~D@
2
DDR_HVREF_RST_PCH <7>
LAN_SMBCLK <37>
LAN_SMBDATA <37>
SML1_SMBCLK <49>
SML1_SMBDATA <49>
PCH_CL_CLK1 <42>
PCH_CL_DATA1 <42>
PCH_CL_RST1# <42>
CLK_PCIE_VGA# <16>
CLK_PCIE_VGA <16>
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
CLK_PCI_LOOPBACK <20>
1 2
12
12
12
12
2
SML1_SMBCLK
+3.3V_ALW_PCH
RUN_GFX_ON<48,52>
SML1_SMBDATA
DDR_HVREF_RST_PCH
PCH_GPIO74
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
LAN_SMBCLK
LAN_SMBDATA
RH80
10K_0402_5%~D
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
13
D
2
SSM3K7002FU_SC70-3~D
G
S
1 2
1 2
RH74 10K_0402_5%~D
RH75 10K_0402_5%~D
1 2
RH91 10K_0402_5%~D
1 2
1 2
RH76 10K_0402_5%~D
RH77 10K_0402_5%~D
1 2
1 2
RH78 10K_0402_5%~D
RH79 10K_0402_5%~D
1 2
RH183 10K_0402_5%~D
CLOCK TERMINATION for FCIM and need close to PCH
12
+1.05V_RUN
CLK_PCI_TPM_TCM <41>
CLK_SIO_14M <48>
PCLK_80H <42>
JETWAY_CLK14M <41>
RH309 0_0402_5%~D@
RH99
1M_0402_5%~D
25MHZ_10PF_Q22FA2380049900~D
3
CH18
4
2
1
10P_0402_50V8J~D
YH2
OUT
GND
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (2/8)
PCH (2/8)
PCH (2/8)
LA-7931P
LA-7931P
LA-7931P
1
GFX_CLK_REQ#
QH2
12
1
IN
2
GND
1
+3.3V_ALW_PCH
12
RH2982.2K_0402_5%~D
12
RH2992.2K_0402_5%~D
RH3001K_0402_1%~D
RH30110K_0402_5%~D
RH3022.2K_0402_5%~D
RH3032.2K_0402_5%~D
RH30410K_0402_5%~D
+3.3V_LAN
RH3052.2K_0402_5%~D
RH3062.2K_0402_5%~D
18 70Monday, July 23, 2012
18 70Monday, July 23, 2012
18 70Monday, July 23, 2012
Crystal EA.
10P_0402_50V8J~D
2
CH19
1
of
of
of
1.0
1.0
1.0
Page 19
5
4
3
2
1
+3.3V_ALW_PCH
D D
+3.3V_RUN
C C
XDP_DBRESET#<7,17>
PM_DRAM_PWRGD<7>
PCH_RSMRST#_Q<17,50>
ME_SUS_PWR_ACK<49>
SIO_PWRBTN#_R<7,17>
SIO_PWRBTN#<49>
+3.3V_ALW_PCH
SIO_SLP_A#<48,52,57>
PM_APWROK<49>
SYS_PWROK<7,48>
RESET_OUT#<49>
AC_PRESENT<49>
B B
A A
1 2
RH318 10K_0402_5%~D@
1 2
RH144 10K_0402_5%~D
1 2
RH142 10K_0402_5%~D
1 2
RH319 10K_0402_5%~D@
1 2
RH140 10K_0402_5%~D
1 2
RH137 8.2K_0402_5%~D
+1.05V_RUN
RH111 49.9_0402_1%~D
RH112 750_0402_1%~D
SUSACK#<48> PCH_DPWROK <48>
74AHC1G08GW_SOT353-5~D
RH114 0_0402_5%~D@
RH359 0_0402_5%~D@
RH116 0_0402_5%~D@
RH117 0_0402_5%~D@
RH320 0_0402_5%~D@
RH120 0_0402_5%~D@
RH121 0_0402_5%~D@
RH122 0_0402_5%~D@
RH139 8.2K_0402_5%~D
5
DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>
1 2
1 2
RH367 0_0402_5%~D@
SUS_STAT#/LPCPD#
ME_SUS_PWR_ACK
PCH_PCIE_WAKE#
SIO_SLP_LAN#
PCH_RI# PCH_CRT_DDC_CLK
CLKRUN#
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_COMP_R
RBIAS_CPY
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_ALW2
UC4
1
IN1
2
IN2
1 2
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PM_DRAM_PWRGD_R
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SIO_PWRBTN#_R
AC_PRESENT
PCH_BATLOW#
PCH_RI#
CH112
1 2
5
0.1U_0402_25V6K~D
P
4
PM_APWROK_R
O
G
3
preventmaterialshortageforThaiflood.
BC24
BE20
BG18
BG20
BE24
BC20
BJ18
BJ20
AW24
AW20
BB18
AV18
AY24
AY20
AY18
AU18
BJ24
BG25
BH21
C12
K3
P12
L22
L10
B13
C21
K16
E20
H20
E10
A10
PCH_DPWROK PCH_RSMRST#_R
ME_SUS_PWR_ACK_R SUSACK#_R
UH4C
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP
DMI_IRCOMP
DMI2RBIAS
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#
ACPRESENT / GPIO31
BATLOW# / GPIO72
RI#
BD82PPSM-QNHN-A0_BGA989~D
4
1 2
RH113 0_0402_5%~D@
1 2
RH321 0_0402_5%~D@
1 2
RH323 0_0402_5%~D@
DMI
FDI
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
SLP_LAN# / GPIO29
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SYS_PWROKRESET_OUT#
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
H_PM_SYNC
SIO_SLP_LAN#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+RTC_CELL
330K_0402_1%~D
RH127
1 2
DSWODVREN
330K_0402_1%~D
@
RH129
1 2
FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>
FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>
FDI_INT <6>
FDI_FSYNC0 <6>
FDI_FSYNC1 <6>
FDI_LSYNC0 <6>
FDI_LSYNC1 <6>
PCH_PCIE_WAKE# <49>
CLKRUN# <41,48,49>
T56 PAD~D@
T57 PAD~D@
T58 PAD~D@
SIO_SLP_S5# <49>
T59 PAD~D@
SIO_SLP_S4# <48,52,55>
SIO_SLP_S3# <11,35,47,48,52,56>
SIO_SLP_A# <48,52,57>
T62 PAD~D@
SIO_SLP_SUS# <48>
T63 PAD~D@
H_PM_SYNC <7>
SIO_SLP_LAN# <37,48>
3
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
Disabled
PANEL_BKEN_PCH<28>
LDDC_CLK_PCH<27>
LDDC_DATA_PCH<27>
Minimumspeacingof20milsforLVD_IBG
LCD_ACLK-_PCH<27>
LCD_ACLK+_PCH<27>
LCD_BCLK-_PCH<27>
LCD_BCLK+_PCH<27>
PCH_CRT_BLU<32>
PCH_CRT_GRN<32>
PCH_CRT_RED<32>
PCH_CRT_DDC_CLK<32>
PCH_CRT_DDC_DAT<32>
PCH_CRT_HSYNC<32>
PCH_CRT_VSYNC<32>
1 2
1 2
1 2
1 2
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH
RH131 150_0402_1%~D
RH132 150_0402_1%~D
RH133 150_0402_1%~D
RH134 100K_0402_5%~D
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
LOW: RH129 STUFFED,
RH127 UNSTUFFED
PANEL_BKEN_PCH
1 2
ENVDD_PCH
BIA_PWM_PCH
LDDC_CLK_PCH
LDDC_DATA_PCH
LVD_IBG
LCD_ACLK-_PCH
LCD_ACLK+_PCH
LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH
LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH
LCD_BCLK-_PCH
LCD_BCLK+_PCH
LCD_B0-_PCH
LCD_B1-_PCH
LCD_B2-_PCH
LCD_B0+_PCH
LCD_B1+_PCH
LCD_B2+_PCH
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
1K_0402_0.5%~D
12
RH126
2
ENVDD_PCH<28,48>
BIA_PWM_PCH<28>
RH344 2.37K_0402_1%~D
LCD_A0-_PCH<27>
LCD_A1-_PCH<27>
LCD_A2-_PCH<27>
LCD_A0+_PCH<27>
LCD_A1+_PCH<27>
LCD_A2+_PCH<27>
LCD_B0-_PCH<27>
LCD_B1-_PCH<27>
LCD_B2-_PCH<27>
LCD_B0+_PCH<27>
LCD_B1+_PCH<27>
LCD_B2+_PCH<27>
1 2
RH123 20_0402_1%~D
1 2
RH124 20_0402_1%~D
HSYNC
VSYNC
CRT_IREF
MAX14885EETL has internal 3K pu for
PCH_CRT_DDC_CLK and PCH_CRT_DDC_DAT
+3.3V_RUN
12
RH3172.2K_0402_5%~D @
PCH_CRT_DDC_DAT
1 2
RH3162.2K_0402_5%~D @
Intel request DDPB can not support eDP
UH4D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
BD82PPSM-QNHN-A0_BGA989~D
LVDS
CRT
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (3/8)
PCH (3/8)
PCH (3/8)
LA-7931P
LA-7931P
LA-7931P
1
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
1.0
1.0
19 70Monday, July 23, 2012
19 70Monday, July 23, 2012
19 70Monday, July 23, 2012
1.0
of
of
of
Page 20
5
4
3
2
1
UH4E
+3.3V_RUN
1 2
RH324 8.2K_0402_5%~D
1 2
D D
C C
RH325 8.2K_0402_5%~D
1 2
RH326 8.2K_0402_5%~D
1 2
RH329 8.2K_0402_5%~D
1 2
RH327 10K_0402_5%~D
1 2
RH330 10K_0402_5%~D
1 2
RH328 10K_0402_5%~D
1 2
RH332 10K_0402_5%~D
1 2
RH331 10K_0402_5%~D
1 2
RH360 10K_0402_5%~D
PCI_GNT3#
1K_0402_1%~D
@
12
RH333
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3
B B
Low = A16 swap
High = Default
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
LCD_CBL_DET#
PCH_GPIO54
PCH_GPIO3
CAM_MIC_CBL_DET#
PCH_GPIO52
PLTRST_GPU#<16>
PLTRST_USH#<41>
PLTRST_MMI#<47>
PLTRST_XDP#<7>
PLTRST_LAN#<37>
USB3RN1<40>
USB3RN2<40>
USB3RN4<46>
USB3RP1<40>
USB3RP2<40>
USB3RP4<46>
USB3TN1<40>
USB3TN2<40>
USB3TN4<46>
USB3TP1<40>
USB3TP2<40>
USB3TP4<46>
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
PCH_GPIO52
PCH_GPIO54
BBS_BIT1
PCI_GNT3#
LCD_CBL_DET#<28>
CAM_MIC_CBL_DET#<28>
1 2
RH343 0_0402_5%~D@
1 2
RH335 0_0402_5%~D@
1 2
RH336 0_0402_5%~D@
1 2
RH337 0_0402_5%~D@
1 2
RH338 0_0402_5%~D@
CLK_PCI_5048<48>
CLK_PCI_MEC<49>
CLK_PCI_DOCK<46>
CLK_PCI_LOOPBACK<18>
HDD_FALL_INT<35>
RH160 22_0402_5%~D
RH102 22_0402_5%~D
RH103 22_0402_5%~D
RH105 22_0402_5%~D
RH334 0_0402_5%~D@
12
12
12
12
LCD_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET# USB_OC2#
1 2
FFS_PCH_INT
T104PAD~D @
PCH_PLTRST#
PCI_5048
PCI_MEC
PCI_DOCK
PCI_LOOPBACKOUT
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3TP1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
BD82PPSM-QNHN-A0_BGA989~D
RSVD
USB30
PCI
USB
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
USBP12USBP12+
USBRBIAS
Route single-end 50-ohms and max 500-mils length.
Minimum spacing to other signals: 15 mils
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
USBP0- <40>
USBP0+ <40>
USBP1- <40>
USBP1+ <40>
USBP2- <47>
USBP2+ <47>
USBP3- <46>
USBP3+ <46>
USBP4- <46>
USBP4+ <46>
USBP5- <43>
USBP5+ <43>
USBP6- <47>
USBP6+ <47>
USBP7- <41>
USBP7+ <41>
USBP8- <42>
USBP8+ <42>
USBP9- <39>
USBP9+ <39>
USBP10- <47>
USBP10+ <47>
USBP11- <50>
USBP11+ <50>
USBP12- <28>
USBP12+ <28>
1 2
RH151
22.6_0402_1%~D
1 2
RH339 0_0402_5%~D@
1 2
RH341 0_0402_5%~D@
1 2
RH356 0_0402_5%~D@
SIO_EXT_SMI#
----->Right Side
----->Right Side
----->Left Side
----->MLK DOCK
----->DOCK
----->WWAN/UWB
----->Left Side
----->USH
----->WLAN/WIMAX
----->ESATA
----->Express Card
----->Blue Tooth
----->Camera
USB_OC0# <40>
USB_OC1# <47>
USB_OC2# <17>
USB_OC3# <17,47>
USB_OC4# <39>
USB_OC5# <17>
USB_OC6# <17>
SIO_EXT_SMI# <17,49>
USB_OC0#_R <17>
USB_OC1#_R <17>
USB_OC4#_R <17>
USB_OC0#_R
USB_OC1#_R
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
RPH1
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
RPH2
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
+3.3V_ALW_PCH
1 2
1 2
1 2
1 2
ForRFlayoutrequest
A A
PCH_PLTRST#<7>
5
CLK_PCI_5048
C132412P_0402_50V8J @
CLK_PCI_MEC
C132512P_0402_50V8J @
CLK_PCI_DOCK
C132612P_0402_50V8J @
CLK_PCI_LOOPBACK
C132712P_0402_50V8J @
74AHC1G08GW_SOT353-5~D
+3.3V_RUN
1
2
0.1U_0402_25V6K~D
5
UH3
P
IN1
O
IN2
G
3
CH102
1 2
4
PCH_PLTRST#_EC <41,42,43,47,48,49>
preventmaterialshortageforThaiflood.
4
Boot BIOS Strap
BBS_BIT1 Boot BIOS Location
*
SATA_SLPD
(BBS_BIT0)
00
01
10
11
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
LPC
Reserved (NAND)
PCI
SPI
BBS_BIT1
12
@
1K_0402_1%~D
RH342
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (4/8)
PCH (4/8)
PCH (4/8)
LA-7931P
LA-7931P
LA-7931P
20 70Monday, July 23, 2012
20 70Monday, July 23, 2012
20 70Monday, July 23, 2012
1
of
of
of
1.0
1.0
1.0
Page 21
5
4
3
2
1
12
12
12
12
12
12
+3.3V_RUN
RH25610K_0402_5%~D
RH15810K_0402_5%~D
RH20310K_0402_5%~D
RH26310K_0402_5%~D
RH164100K_0402_5%~D
RH17110K_0402_5%~D @
RH1731K_0402_1%~D @
RH26610K_0402_5%~D
RH18110K_0402_5%~D
RH17810K_0402_5%~D
RH2698.2K_0402_5%~D
RH16310K_0402_5%~D
RH2728.2K_0402_5%~D
RH3618.2K_0402_5%~D @
RH362100K_0402_5%~D
+3.3V_ALW_PCH
RH54
4.7K_0402_5%~D
1 2
SLP_ME_CSW_DEV#
12
RH353
D D
Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)
@
1K_0402_1%~D
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE
ENABLED - HIGH DEFAULT
DISABLED - LOW
+3.3V_ALW_PCH
12
12
12
12
12
12
12
SIO_EXT_WAKE#
PCH_GPIO15
KB_DET#
PCH_GPIO27
PCH_GPIO36
PCH_GPIO37
PCH_GPIO17
PCH_GPIO16
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
C C
B B
RH177 10K_0402_5%~D
1 2
RH354 1K_0402_1%~D
RH170 10K_0402_5%~D
RH175 10K_0402_5%~D@
PCHhasinternalpullup20kohmon(GPIO27)
RH174 10K_0402_5%~D
RH172 10K_0402_5%~D
RH273 1K_0402_1%~D@
RH274 1K_0402_1%~D@
SIO_EXT_SCI#_R<17>
SIO_EXT_SCI#<49>
USH_DET#<41>
MXM_PRESENTL#<16>
SIO_EXT_WAKE#<48>
PM_LANPHY_ENABLE<37>
PCH_GPIO15<17>
PCH_GPIO16<17>
T107PAD~D@
SLP_ME_CSW_DEV#<17,48>
DGPU_HOLD_RST#<16>
PCH_GPIO35<17>
PCH_GPIO36<17>
PCH_GPIO37<17>
TEMP_ALERT#<17,48>
KB_DET#<50>
SIO_EXT_SCI#
FFS_INT2<35>
1 2
RH259 0_0402_5%~D@
USH_DET#
DP_MUX_PRIORITY
MXM_PRESENTL#
SIO_EXT_WAKE#
PM_LANPHY_ENABLE
PCH_GPIO15
PCH_GPIO16
PCH_GPIO17
PCH_GPIO22
PCH_GPIO24
PCH_GPIO27
SLP_ME_CSW_DEV#
DGPU_HOLD_RST#
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37
TPM_ID0
TPM_ID1
FFS_INT2
TEMP_ALERT#
KB_DET#
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
UH4F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
BD82PPSM-QNHN-A0_BGA989~D
GPIO
NCTF
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
CONTACTLESS_DET#
DGPU_PWROK
MXM_PRESENTR#
PCH_GPIO71
SIO_A20GATE
SIO_RCIN#
H_CPUPWRGD
PCH_THRMTRIP#_R
INIT3_3V#
DF_TVS
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
CONTACTLESS_DET# <41>
DGPU_PWROK <16,48>
MXM_PRESENTR# <16>
T109PAD~D @
SIO_A20GATE <49>
SIO_RCIN# <49>
H_CPUPWRGD <7>
T106PAD~D @
T108PAD~D @
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
RH262 56_0402_5%~D
0.1U_0402_25V6K~D
1
CH97
2
12
+1.05V_RUN_VTT
PLACE RH150 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)
+VCCDFTERM
2.2K_0402_5%~D
RH149
12
CONTACTLESS_DET#
SIO_A20GATE
SIO_RCIN#
SIO_EXT_SCI#
USH_DET#
PCH_GPIO36
PCH_GPIO37
TEMP_ALERT#
PCH_GPIO22
MXM_PRESENTL#
PCH_GPIO17
DP_MUX_PRIORITY
PCH_GPIO16
PCH_GPIO35
MXM_PRESENTR#
powerSaving.
RH149 need to close to CPU
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_RUN +3.3V_RUN
12
RH268
RH267
1@
10K_0402_5%~D
TPM_ID0
A A
1 2
RH270
10K_0402_5%~D
1 2
TPM_ID1
2@
20K_0402_5%~D
12
RH271
2.2K_0402_5%~D
3@
TCM
No TPM, No TCM
4@
TBD
TPM
TPM_ID1TPM_ID0
0
0
0
1
11
H_SNB_IVB#<7>
1 2
RH150 0_0402_5%~D@
DF_TVS
1 2
RH358 1K_0402_1%~D
DF_TVSDF_TVS_R
DMI & FDI Termination Voltage
Set to Vss when LOW
Set to Vcc when HIGH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (5/8)
PCH (5/8)
PCH (5/8)
LA-7931P
LA-7931P
LA-7931P
21 70Monday, July 23, 2012
21 70Monday, July 23, 2012
21 70Monday, July 23, 2012
1
1.0
1.0
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Page 22
5
+1.05V_RUN
D D
+1.05V_RUN
C C
B B
+1.05V_RUN
1 2
RH195 0.022_0805_1%@
RH247
@
1 2
1UH_LB2012T1R0M_20%~D
+1.05V_RUN
+3.3V_RUN
+VCCAPLL_FDI
+1.05V_RUN
+VCCAPLLEXP
10U_0603_6.3V6M~D
1
CH44
2
0.1U_0402_10V7K~D
1
CH51
2
+1.05V_RUN
+1.05V_RUN_VTT
10U_0603_6.3V6M~D
1
CH30
2
1U_0402_6.3V6K~D
1
CH45
2
+VCCAFDI_VRM
1U_0402_6.3V6K~D
1
1
CH32
2
2
1U_0402_6.3V6K~D
1
CH46
2
1U_0402_6.3V6K~D
CH33
10U_0603_6.3V6M~D
1
@
2
1U_0402_6.3V6K~D
1
CH47
2
+VCCAPLL_FDI
1
2
CH40
4
UH4G
AA23
VCCCORE[1]
AC23
VCCCORE[2]
1U_0402_6.3V6K~D
CH31
1U_0402_6.3V6K~D
1
CH48
2
AD21
VCCCORE[3]
AD23
VCCCORE[4]
AF21
VCCCORE[5]
AF23
VCCCORE[6]
AG21
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9]
AG26
VCCCORE[10]
AG27
VCCCORE[11]
AG29
VCCCORE[12]
AJ23
VCCCORE[13]
AJ26
VCCCORE[14]
AJ27
VCCCORE[15]
AJ29
VCCCORE[16]
AJ31
VCCCORE[17]
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VccAFDIPLL
AP17
VCCIO[27]
AU20
VCCDMI[2]
BD82PPSM-QNHN-A0_BGA989~D
POWER
VCC CORE
VCCIO
FDI
CRTLVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
DMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
DFT / SPI HVCMOS
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCSPI
3
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
+1.05V_RUN_VCCCLKDMI
AG16
AG17
AJ16
AJ17
V1
1
2
1
2
0.1U_0402_10V7K~D
1
CH43
2
+VCCDFTERM
1
2
+VCCSPI
1U_0402_6.3V6K~D
CH54
1
2
+VCCADAC
0.01U_0402_16V7K~D
CH34
0.01U_0402_16V7K~D
CH103
+3.3V_RUN
1U_0402_6.3V6K~D
1
2
0.1U_0402_10V7K~D
CH52
2
for solving dispaly ripples.
need change to SHI00003Y0L, after footprint ok.
LH1
1 2
4.7UH_LQM18FN4R7M00D_20%~D
0.1U_0402_10V7K~D
1
1
CH35
CH36
22U_0805_6.3V6M~D
2
2
+1.8V_RUN_LVDS
22U_0805_6.3V6M~D
1
2
CH50
RH202 0_0603_5%~D@
0.01U_0402_16V7K~D
CH104
1 2
100NH_HCI1608F-R10J-M_5%_0603~D
CH105
1
TAIYOEOL,changetoTAI‐TECH,
footprintisTAIYO_HK1608R10J‐T_L0603_2P.
2
+VCCAFDI_VRM
CH49
1U_0402_6.3V6K~D
RH205 0_0603_5%~D@
10U_0603_6.3V6M~D
@
1
CH106
2
RH276 0_0805_5%~D@
PJP70
@
1 2
PAD-OPEN1x1m
12
12
+3.3V_RUN
+3.3V_RUN
LH8
+1.05V_RUN_VTT
12
+3.3V_M
+1.8V_RUN
12
+1.05V_RUN
+3.3V_RUN
+1.8V_RUN
1
PCH Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC3
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1.05
1.05
1.05
1.1
S0 Iccmax
Current (A)
0.001
5
5
0.001
0.001
0.228
0.063
0.08
0.08
1.7
0.047
1.05VccIO 3.711
VccASW
VccSPI
VccDSW3_3 0.001
1.05
3.3
3.3
0.903
0.01
1.8 0.002VCCDFTERM
3.3VccRTC 2 (mA)
3.3VccSus3_3
3.3VccSusHDA
0.095
0.01
VccVRM 1.5 0.167
1.05VccClkDMI 0.07
1.05VccSSC
VccDIFFCLKN 0.055
1.05
VccALVDS 3.3
0.095
0.001
1.8VccTX_LVDS 0.04
+1.5V_RUN +VCCAFDI_VRM
RH211 0_0603_5%~D@
A A
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (6/8)
PCH (6/8)
PCH (6/8)
LA-7931P
LA-7931P
LA-7931P
22 70Monday, July 23, 2012
22 70Monday, July 23, 2012
22 70Monday, July 23, 2012
1
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of
Page 23
5
4
3
2
1
+PWR_SRC_S
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_ALW2
D D
+1.05V_RUN
+3.3V_RUN
1 2
RH215 0.022_0805_1%
Note:IfEMIconcern,popwith
+1.05V_RUN
RH248 0.022_0805_1%@
1 2
SHI00008S0L,10UH+‐20%
LH6
1 2
10UH_LBR2012T100M_20%~D
LH7
1 2
10UH_LBR2012T100M_20%~D
+1.05V_M_VCCSUS
C C
B B
+1.05V_M
A A
1 2
RH201
@
1 2
RH253 0_0402_5%~D@
LH3
@
1 2
10UH_LBR2012T100M_20%~D
+3.3V_RUN_VCC_CLKF33
1
2
220U_B2_2.5VM_R35M~D
1
CH94
+
2
+1.05V_RUN
1
2
0_0402_5%~D
10U_0603_6.3V6M~D
+1.05V_RUN
@
1
CH58
2
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1
CH74
@
CH73
2
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
220U_B2_2.5VM_R35M~D
1U_0402_6.3V6K~D
1
CH92
CH95
CH81
1 2
1
2
+
2
1U_0402_6.3V6K~D
1
2
CH96
+1.05V_RUN_VTT
1
2
CH79
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
1U_0402_6.3V6K~D
CH93
4.7U_0603_6.3V6K~D
1
2
0.1U_0402_10V7K~D
CH55
+1.05V_M
1
2
RH200 0.022_0805_1%@
1U_0402_6.3V6K~D
1 2
1
CH67
2
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
@
CH57
1
2
1U_0402_6.3V6K~D
@
CH61
1U_0402_6.3V6K~D
1
CH68
CH69
2
0.1U_0402_10V7K~D
CH78
1
2
+VCCACLK
+VCCDSW3_3
+PCH_VCCDSW
+3.3V_RUN_VCC_CLKF33
+VCCAPLL_CPY_PCH
+VCCSUS1
1
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH64
CH65
1
1
2
2
+VCCRTCEXT
+VCCAFDI_VRM
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
18mil
AF33,AF34andAG34routtracewidth=18mil,
AG33routtracewidth=10milandisolatedeachother.
0.1U_0402_10V7K~D
10mil
CH84
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
CH86
CH85
CH87
2
2
+VCCSST
1U_0402_6.3V6K~D
+1.05V_M_VCCSUS
1
@
1
CH83
2
2
+RTC_CELL
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
CH88
2
2
UH4J
AD49
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3[5]
BH23
VCCAPLLDMI2
AL29
VCCIO[14]
AL24
DCPSUS[3]
AA19
VCCASW[1]
AA21
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD29
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
N16
DCPRTC
Y49
VCCVRM[4]
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO[7]
AF33
VCCDIFFCLKN[1]
AF34
VCCDIFFCLKN[2]
AG34
VCCDIFFCLKN[3]
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS[1]
V19
DCPSUS[2]
BJ8
V_PROC_IO
A22
VCCRTC
1U_0402_6.3V6K~D
1
BD82PPSM-QNHN-A0_BGA989~D
CH90
CH89
2
POWER
N26
VCCIO[29]
P26
VCCIO[30]
P28
VCCIO[31]
T27
VCCIO[32]
T29
VCCIO[33]
VCCIO[34]
V5REF_SUS
DCPSUS[4]
V5REF
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12]
VCCIO[13]
VCCIO[6]
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
VCCASW[22]
VCCASW[23]
VCCASW[21]
VCCSUSHDA
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
Clock and Miscellaneous
PCI/GPIO/LPCMISC
VCCAPLLSATA
SATA USB
CPURTC
HDA
+1.05V_RUN
+3.3V_ALW_PCH
+PCH_V5REF_SUS
+VCCA_USBSUS
+PCH_V5REF_RUN
+3.3V_ALW_PCH
1
2
1U_0402_6.3V6K~D
1
2
0.1U_0402_10V7K~D
CH59
1
2
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_RUN
1
2
+VCCAFDI_VRM
0.1U_0402_10V7K~D
CH91
CH56
+3.3V_ALW_PCH
1U_0603_10V7K~D
CH70
1
2
0.1U_0402_10V7K~D
CH76
+1.05V_RUN
+1.05V_M
0.1U_0402_10V7K~D
1
CH60
2
+3.3V_ALW_PCH
+3.3V_RUN
1
2
1U_0402_6.3V6K~D
1
CH82
2
1
2
0.1U_0402_10V7K~D
CH72
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CH66
+3.3V_RUN
1
CH75
2
ALW_ON_3.3V#<52>
+1.05V_RUN
1
2
1U_0402_6.3V6K~D
CH77
100K_0402_5%~D
12
RH363
+5V_ALW_PCH_ENABLE
SSM3K7002FU_SC70-3~D
13
D
S
RH208
10_0402_1%~D
RH213
10_0402_1%~D
QH8
12
12
2
G
CRB0.7RH208,RH213tracewidth20mil.
QH4
SSM3K7002FU_SC70-3~D
1 3
D
2
1M_0402_5%~D
@
12
RH364
+3.3V_ALW_PCH+5V_ALW_PCH
21
DH2
RB751S40T1_SOD523-2~D
+PCH_V5REF_SUS
0.1U_0402_10V7K~D
1
CH63
2
+3.3V_RUN+5V_RUN
21
DH3
RB751S40T1_SOD523-2~D
+PCH_V5REF_RUN
1U_0603_10V7K~D
1
CH71
2
+VCCA_USBSUS
+5V_ALW_PCH+5V_ALW
S
0.1U_0402_10V7K~D
20K_0402_5%~D
12
CH98
G
1
2
3300P_0402_50V7K~D
CH110
1
2
1U_0402_6.3V6K~D
1
2
RH278
@
CH62
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (7/8)
PCH (7/8)
PCH (7/8)
LA-7931P
LA-7931P
LA-7931P
1
23 70Monday, July 23, 2012
23 70Monday, July 23, 2012
23 70Monday, July 23, 2012
1.0
1.0
1.0
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Page 24
5
D D
C C
B B
A A
UH4H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
BD82PPSM-QNHN-A0_BGA989~D
4
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
3
UH4I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
BD82PPSM-QNHN-A0_BGA989~D
2
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (8/8)
PCH (8/8)
PCH (8/8)
LA-7931P
LA-7931P
LA-7931P
24 70Monday, July 23, 2012
24 70Monday, July 23, 2012
24 70Monday, July 23, 2012
1
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Page 25
5
4
3
2
1
+3.3V_M
12
8.2K_0402_5%~D
R396
CPUFAN
12
21
Followconnlist0301A.
CONN@
JFAN1
1
1
2
2
3
3
4
4
5
GND1
6
GND2
ACES_50271-0040N-001
LinkCISOK
0301
Followconnlist0301A.
FAN2_TACH_FB
FAN2_PWM_DFAN2_PWM
CONN@
JFAN2
1
1
2
2
3
3
4
4
5
GND1
6
GND2
ACES_50271-0040N-001
LinkCISOK
0301
THERMATRIP1#
PMST3904_SOT323-3~D
+1.05V_RUN_VTT
@
2.2K_0402_5%~D
12
R401
THERMB3
2
B
E
2
B
1 2
R399
2.2K_0402_5%~D
H_THERMTRIP#<7>
+3.3V_MXM
10K_0402_5%~D
12
R400
DGPU_THERMTRIP#<16>
C
Q28
3 1
+3.3V_M
8.2K_0402_5%~D
12
PMST3904_SOT323-3~D
C
E
3 1
1
2
R397
THERMATRIP3#
Q115
0.1U_0402_25V6K~D
C327
0.1U_0402_25V6K~D
1
C343
2
PlaceQ26underCPUforOTPsensor.
PlaceC339closetotheQ26aspossible
100P_0402_50V8J~D
@
2
D D
C C
C339
1
PutQ17ontheBotsideforSkintemperature
100P_0402_50V8J~D
@
1
C340
2
PlaceQ14nearDockingCONNonBOTside
100P_0402_50V8J~D
1
@
C272
2
C
2
B
E
3 1
Q26
MMBT3904WT1G_SC70-3~D
C
2
B
E
3 1
Q17
MMBT3904WT1G_SC70-3~D
C
2
B
E
Q14
3 1
MMBT3904WT1G_SC70-3~D
REM_DIODE1_P_4002
REM_DIODE1_N_4002
REM_DIODE2_P_4002
REM_DIODE2_N_4002
REM_DIODE3_P_4002
REM_DIODE3_N_4002
100P_0402_50V8J~D
PlaceQ15underButterfly'sCHA(BOTside).
@
C288
1
2
PlaceQ33underStack_SODIMMonTOPside.
100P_0402_50V8J~D
@
C349
2
1
100P_0402_50V8J~D
PlaceQ16underButterfly'sCHB(BOTside).
@
C294
1
2
C
2
B
E
3 1
MMBT3904WT1G_SC70-3~D
C
2
B
E
3 1
Q33
MMBT3904WT1G_SC70-3~D
C
2
B
E
3 1
Q16
MMBT3904WT1G_SC70-3~D
REM_DIODE4_P_4002
1
C335
2200P_0402_50V7K~D
Q15
2
REM_DIODE4_N_4002
REM_DIODE5_P_4002
1
C347
2200P_0402_50V7K~D
2
REM_DIODE5_N_4002
REM_DIODE8_P_4002
REM_DIODE8_N_4002
+5V_RUN
+5V_RUN
0.1U_0402_25V6K~D
10U_0805_10V6K~D
C370
C330
1
1
2
2
FAN1_TACH_FB
FAN1_PWM
10U_0805_10V6K~D
0.1U_0402_25V6K~D
C329
C364
1
1
2
2
MXMFAN
R2071
@
0_0603_5%~D
D98
RB751S40T1_SOD523-2~D
+3.3V_M
12
1U_0402_6.3V6K~D
1
2
+3.3V_M
12
1
2
BC_INT#_EMC4002
12
EMC4022_GPIO2
12
FAN2_PWM
0.1U_0402_25V6K~D
1
C348
C341
2
8.2K_0402_5%~D
R398
THERMATRIP2#
0.1U_0402_25V6K~D
C350
+RTC_CELL
1 2
C334 2200P_0402_50V7K~D
1 2
C344 2200P_0402_50V7K~D
1 2
C346 2200P_0402_50V7K~D
+3VM_THRM
1U_0402_6.3V6K~D
1
C336
PCH_PWRGD#<49>
2
0.1U_0402_25V6K~D
1
C333
2
VSET_4002
1.33K_0402_1%~D
12
R406
+3.3V_M
R389 10K_0402_5%~D
R391 1K_0402_1%~D
+3VM_THRM
changeVSETfrom88to93 .℃℃
R385 10K_0402_5%~D
R404 10K_0402_5%~D
R2058 10K_0402_5%~D
R289 0_0603_5%~D@
+3.3V_M
B B
12
BC_DAT_EMC4002<49>
BC_CLK_EMC4002<49>
1 2
1 2
R393 4.7K_0402_5%~D
REM_DIODE1_P_4002
REM_DIODE1_N_4002
REM_DIODE2_P_4002
REM_DIODE2_N_4002
REM_DIODE3_P_4002
REM_DIODE3_N_4002
VDD_PWRGD
3V_PWROK#
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#
VSET_4002
12
+ADDR_XEN
FAN1_TACH_FB
EMC4022_GPIO2
U18
10
SMDATA/BC-LINK_DATA
11
SMCLK/BC-LINK_CLK
36
DP1/VREF_T
35
DN1/THERM
38
DP2
37
DN2
41
DP3/DN7
40
DN3/DP7
4
VDD
21
RTC_PWR3V
THERMTRIP_SIO/PWM1/GPIO5
18
VDD_PWRGD
17
3V_PWROK#
22
THERMTRIP1#
23
THERMTRIP2#
24
THERMTRIP3#
42
VSET
3
ADDR_MODE/XEN
6
VDDH1
5
VDDH1
9
VDDL1
7
FAN_OUT1
8
FAN_OUT1
15
TACH1/GPIO3
14
CLK_IN/GPIO2
DP6/VREF_T2
ATF_INT#/BC-LINK_IRQ#
POWER_SW#
ACAVAIL_CLR
SYS_SHDN#
LDO_SHDN#
LDO_POK
LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2
TACH2/GPIO4
PWM2/GPIO1
VSS
EMC4002-HZH C_QFN48_7X7~D
49
VIN1
VCP1
VCP2
DP4/DN8
DN4/DP8
DP5/DN9
DN5/DP9
DN6/VIN2
LDO_SET
VDDH2
VDDH2
VDDL2
39
48
45
VCP2
44
43
47
REM_DIODE5_P_4002
46
REM_DIODE5_N_4002
1
2
12
BC_INT#_EMC4002
26
POWER_SW#
27
20
FAN1_PWM
25
19
34
33
LDO_SET
32
31
28
29
30
16
FAN2_TACH_FB
13
FAN2_PWM
1 2
R388 4.7K_0402_5%~D
1 2
R392 1K_0402_1%~D
REM_DIODE4_P_4002
REM_DIODE4_N_4002
REM_DIODE8_N_4002
REM_DIODE8_P_4002
BC_INT#_EMC4002 <49>
ACAV_IN <16,49,62,63>
1 2
R390 47K_0402_1%~D@
12
R40210K_0402_5%~D
12
+3.3V_M
R39510K_0402_5%~D @
MAX8731_IINP <62>
THERM_STP# <54>
+RTC_CELL
0.1U_0402_25V6K~D
DOCK_PWR_SW#<49>
POWER_SW_IN#<49>
74AHC1G08GW_SOT353-5~D
FAN2_PWM_D
FAN2_TACH_FB
FAN1_PWM
FAN1_TACH_FB
C287
+3.3V_RUN
12
R40310K_0402_5%~D
12
R40510K_0402_5%~D
12
R40710K_0402_5%~D
12
R40810K_0402_5%~D
+RTC_CELL
12
5
U10
1
P
IN1
4
POWER_SW#
O
2
IN2
G
3
preventmaterialshortageforThaiflood.
Rest=1330ohm,Tp=93degree
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
FAN control
FAN control
FAN control
LA-7931P
LA-7931P
LA-7931P
1
25 70Monday, July 23, 2012
25 70Monday, July 23, 2012
25 70Monday, July 23, 2012
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D D
4
3
2
1
MonitorChargercurrent
+3.3V_ALW
DYN_TURB_SYS_PWR_ALRT#
CHARGE_ALERT
U5
@
1
SMCLK
2
N/C
0.1U_0402_16V4Z~D
1U_0402_6.3V6K~D
@
1
C17
2
3
SENSE-
4
SENSE+
5
VDD
EMC1701-2-AIZL-TR_MSOP10
@
C363
RESISTOR
(5%)
SMBUS
ADDRESS
1001_100(r/w)0
1001_101(r/w)100
C C
180
1001_110(r/w)
1001_111(r/w)300
1001_000(r/w)430
EMC1700_SENSE_N<62>
EMC1700_SENSE_P<62>
+3.3V_ALW
1
2
SMDATA
ALERT#
THERM#
GND
ADDR_SEL
10
LCD_SMBDATLCD_SMBCLK
9
CHARGE_ALERT
8
7
6
LCD_SMBDAT <28,49>LCD_SMBCLK<28,49>
DYN_TURB_SYS_PWR_ALRT# <48>
1 2
R2143 0_0402_5%~D@
20K_0402_5%~D
@
12
R1975
1001_001(r/w)560
1001_010(r/w)750
1001_011(r/w)1270
Removecurrentsensorfunction.
0101_000(r/w)1600
0101_001(r/w)2000
0101_010(r/w)2700
3600 0101_011(r/w)
9100 0101_100(r/w)
0101_100(r/w)5600
MonitorPWR_SRC_MXM
0101_101(r/w)20000
Open
B B
0011_000(r/w)
DYN_TURB_GPU_PWR_ALRT#
PWR_SRC_ALERT
U6
@
LCD_SMBCLK LCD_SMBDAT
MXM_SENSE_N<52>
MXM_SENSE_P<52>
+3.3V_ALW
1
2
1
SMCLK
2
N/C
3
SENSE-
4
SENSE+
5
VDD
EMC1701-2-AIZL-TR_MSOP10
0.1U_0402_16V4Z~D
1U_0402_6.3V6K~D
@
@
1
C361
C16
2
SMDATA
ALERT#
THERM#
GND
ADDR_SEL
10
9
PWR_SRC_ALERT
8
7
6
DYN_TURB_GPU_PWR_ALRT# <16,49>
2.7K_0402_5%~D
@
12
R1974
12
R3510K_0402_5%~D
12
R2010K_0402_5%~D @
H_PROCHOT# <7,49,60,62>
+3.3V_ALW
12
R1410K_0402_5%~D
12
R1910K_0402_5%~D @
Removecurrentsensorfunction.
A A
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Current Sensor
Current Sensor
Current Sensor
LA-7931P
LA-7931P
LA-7931P
26 70Monday, July 23, 2012
26 70Monday, July 23, 2012
26 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
Page 27
5
D D
ChannelA
U11
MXM_LVDS_ACLK+<16>
MXM_LVDS_ACLK-<16>
MXM_LVDS_A2+<16>
MXM_LVDS_A2-<16>
FromMXM
C C
FromPCH
MXM_LVDS_A1+<16>
MXM_LVDS_A1-<16>
MXM_LVDS_A0+<16>
MXM_LVDS_A0-<16>
MXM_LVDS_DDC_CLK<16>
MXM_LVDS_DDC_DAT<16>
LCD_ACLK+_PCH<19>
LCD_ACLK-_PCH<19>
LCD_A2+_PCH<19>
LCD_A2-_PCH<19>
LCD_A1+_PCH<19>
LCD_A1-_PCH<19>
LCD_A0+_PCH<19>
LCD_A0-_PCH<19>
LDDC_CLK_PCH<19>
LDDC_DATA_PCH<19>
31
D0_A+
30
D0_A-
26
D1_A+
25
D1_A-
22
D2_A+
21
D2_A-
18
D3_A+
17
D3_A-
5
1A_A
13
2A_A
33
3A_A
29
D0_B+
28
D0_B-
24
D1_B+
23
D1_B-
20
D2_B+
19
D2_B-
16
D3_B+
15
D3_B-
6
1A_B
14
2A_B
32
3A_B
TS3DV20812RHHR_VQFN36_6X6~D
4
+3.3V_RUN
5@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@
C1146
C1145
1
1
2
5@
35
VDD
36
SW_LVDS_ACLK+
D0+
1
SW_LVDS_ACLK-
D0-
2
SW_LVDS_A2+
D1+
3
SW_LVDS_A2-
D1-
7
SW_LVDS_A1+
D2+
8
SW_LVDS_A1-
D2-
9
SW_LVDS_A0+
D3+
10
SW_LVDS_A0-
D3-
4
LDDC_CLK_SW
1A
12
LDDC_DATA_SW
2A
34
3A
27
DGPU_SELECT#
SEL
37
TPAD
11
GND
2
SW_LVDS_ACLK+ <28>
SW_LVDS_ACLK- <28>
SW_LVDS_A2+ <28>
SW_LVDS_A2- <28>
SW_LVDS_A1+ <28>
SW_LVDS_A1- <28>
SW_LVDS_A0+ <28>
SW_LVDS_A0- <28>
LDDC_CLK_SW <28>
LDDC_DATA_SW <28>
DGPU_SELECT# <28,32,48>
ChanelSEL
0
1
DO=B
Source
GPUDO=A
PCH
3
FromMXM
FromPCH
2
+3.3V_RUN
0.1U_0402_16V4Z~D5@
0.1U_0402_16V4Z~D
@
C1149
C1159
1
ChannelB
U13
5@
31
MXM_LVDS_BCLK+<16>
MXM_LVDS_BCLK-<16>
MXM_LVDS_B2+<16>
MXM_LVDS_B2-<16>
MXM_LVDS_B1+<16>
MXM_LVDS_B1-<16>
MXM_LVDS_B0+<16>
MXM_LVDS_B0-<16>
LCD_BCLK+_PCH<19>
LCD_BCLK-_PCH<19>
LCD_B2+_PCH<19>
LCD_B2-_PCH<19>
LCD_B1+_PCH<19>
LCD_B1-_PCH<19>
LCD_B0+_PCH<19>
LCD_B0-_PCH<19>
D0_A+
30
D0_A-
26
D1_A+
25
D1_A-
22
D2_A+
21
D2_A-
18
D3_A+
17
D3_A-
5
1A_A
13
2A_A
33
3A_A
29
D0_B+
28
D0_B-
24
D1_B+
23
D1_B-
20
D2_B+
19
D2_B-
16
D3_B+
15
D3_B-
6
1A_B
14
2A_B
32
3A_B
TS3DV20812RHHR_VQFN36_6X6~D
VDD
TPAD
GND
D0+
D0-
D1+
D1-
D2+
D2-
D3+
D3-
1A
2A
3A
SEL
35
36
1
2
3
7
8
9
10
4
12
34
27
37
11
1
2
SW_LVDS_BCLK+
SW_LVDS_BCLKSW_LVDS_B2+
SW_LVDS_B2SW_LVDS_B1+
SW_LVDS_B1SW_LVDS_B0+
SW_LVDS_B0-
DGPU_SELECT#
2
SW_LVDS_BCLK+ <28>
SW_LVDS_BCLK- <28>
SW_LVDS_B2+ <28>
SW_LVDS_B2- <28>
SW_LVDS_B1+ <28>
SW_LVDS_B1- <28>
SW_LVDS_B0+ <28>
SW_LVDS_B0- <28>
0
1
ChanelSEL
DO=B
1
Source
GPUDO=A
PCH
+3.3V_MXM
B B
+3.3V_RUN
A A
5
R1122 2.2K_0402_5%~D@
R1121 2.2K_0402_5%~D@
1 2
1 2
MXM_LVDS_DDC_CLK
MXM_LVDS_DDC_DAT
Solve+3.3V_MXMbackdrivewhendisableRUN_GFX_ON.
R1124 2.2K_0402_5%~D5@
R1123 2.2K_0402_5%~D5@
1 2
1 2
LDDC_CLK_PCH
LDDC_DATA_PCH
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
LVDS SW
LVDS SW
LVDS SW
LA-7931P
LA-7931P
LA-7931P
27 70Monday, July 23, 2012
27 70Monday, July 23, 2012
27 70Monday, July 23, 2012
1
of
1.0
1.0
1.0
Page 28
5
LDDC_CLK
C1318 5P_0402_50V8C~D@
LVDS_ACLK-
C1319 5P_0402_50V8C~D@
LVDS_ACLK+
C1320 5P_0402_50V8C~D@
LVDS_BCLK-
C1321 5P_0402_50V8C~D@
LVDS_BCLK+
For6‐bitLCDpanel
CONN@
JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
+BL_PWR_SRC
LVDS_GND
USBP12_DUSBP12_D+
CAM_MIC_CBL_DET#
R2072
@
LCD_TST
LDDC_CLK
R1991 0_0402_5%~D5@
LDDC_DATA
R1992 0_0402_5%~D5@
LVDS_A0-
R1993 0_0402_5%~D5@
LVDS_A0+
R1994 0_0402_5%~D5@
LVDS_A1-
R1995 0_0402_5%~D5@
LVDS_A1+
R1996 0_0402_5%~D5@
LVDS_A2-
R1997 0_0402_5%~D5@
LVDS_A2+
R1998 0_0402_5%~D5@
LVDS_ACLK-
R1999 0_0402_5%~D5@
LVDS_ACLK+
R2000 0_0402_5%~D5@
LVDS_B0-
R2001 0_0402_5%~D5@
LVDS_B0+
R2002 0_0402_5%~D5@
LVDS_B1-
R2003 0_0402_5%~D5@
LVDS_B1+
R2004 0_0402_5%~D5@
LVDS_B2-
R2005 0_0402_5%~D5@
LVDS_B2+
R2006 0_0402_5%~D5@
LVDS_BCLK-
R2007 0_0402_5%~D5@
LVDS_BCLK+
R2008 0_0402_5%~D5@
solveLVDScableburnoutissue.
LCD_CBL_DET# <20>
+LCDVDD
+3.3V_RUN
+CAMERA_VDD
DMIC_CLK <47>
DMIC0 <47>
12
BIA_PWM_LVDSPWM_LVDS
DISP_ON
0_0603_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
41
36
G1
42
37
G2
43
38
G3
44
39
G4
45
40
G5
ACES_50398-04071-001
1
2
3
4
5
6
7
8
9
D D
C C
C1322 5P_0402_50V8C~D@
closedtoJLVDS1
ForRFlayoutrequest
T73PAD~D @
CAM_MIC_CBL_DET# <20>
LCD_TST <48>
LDDC_CLK_SW <27>
LDDC_DATA_SW <27>
SW_LVDS_A0- <27>
SW_LVDS_A0+ <27>
SW_LVDS_A1- <27>
SW_LVDS_A1+ <27>
SW_LVDS_A2- <27>
SW_LVDS_A2+ <27>
SW_LVDS_ACLK- <27>
SW_LVDS_ACLK+ <27>
SW_LVDS_B0- <27>
SW_LVDS_B0+ <27>
SW_LVDS_B1- <27>
SW_LVDS_B1+ <27>
SW_LVDS_B2- <27>
SW_LVDS_B2+ <27>
SW_LVDS_BCLK- <27>
SW_LVDS_BCLK+ <27>
LinkCISOK
0914
For10‐bitLCDpanel
CONN@
JLVDS2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
B B
A A
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
GND_57
58
GND_58
59
GND_59
60
GND_60
61
GND_61
62
GND_62
63
GND_63
64
GND_64
65
GND_65
66
GND_66
JAE_FI-M56S1-R1500-DT
LinkCISOK
CONNlist_0511
5
+BL_PWR_SRC
LVDS_GND
solveLVDScableburnoutissue.
LCD_CBL_DET# <20>
+LCDVDD
+3.3V_RUN
+CAMERA_VDD
DMIC_CLK <47>
USBP12_DUSBP12_D+
CAM_MIC_CBL_DET#
PWM_LVDS
DISP_ON
LCD_TST
LDDC_CLK
LDDC_DATA
LVDS_A0LVDS_A0+
LVDS_A1LVDS_A1+
LVDS_A2LVDS_A2+
LVDS_ACLKLVDS_ACLK+
LVDS_B0LVDS_B0+
LVDS_B1LVDS_B1+
LVDS_B2LVDS_B2+
LVDS_BCLKLVDS_BCLK+
DMIC0 <47>
CAM_MIC_CBL_DET# <20>
1 2
R2011 0_0402_5%~D6@
1 2
R2009 0_0402_5%~D6@
1 2
R2010 0_0402_5%~D6@
1 2
R2012 0_0402_5%~D6@
1 2
R2013 0_0402_5%~D6@
1 2
R2014 0_0402_5%~D6@
1 2
R2015 0_0402_5%~D6@
1 2
R2016 0_0402_5%~D6@
1 2
R2017 0_0402_5%~D6@
1 2
R2018 0_0402_5%~D6@
1 2
R2019 0_0402_5%~D6@
1 2
R2020 0_0402_5%~D6@
1 2
R2021 0_0402_5%~D6@
1 2
R2022 0_0402_5%~D6@
1 2
R2023 0_0402_5%~D6@
1 2
R2024 0_0402_5%~D6@
1 2
R2025 0_0402_5%~D6@
1 2
R2026 0_0402_5%~D6@
for JLVDS1 connector change then GND shield shift
(different from original).because JLVDS1 and JLVDS2
co-lay,we need modify them.
LCD_TST <48>
EDP_CLK <30>
EDP_DATA <30>
EDP_LVDS_A0- <30>
EDP_LVDS_A1+ <30>
EDP_LVDS_A2+ <30>
EDP_LVDS_ACLK- <30>
EDP_LVDS_ACLK+ <30>
EDP_LVDS_B0+ <30>
EDP_LVDS_B1+ <30>
EDP_LVDS_B2+ <30>
EDP_LVDS_BCLK- <30>
EDP_LVDS_BCLK+ <30>
EDP_LVDS_A3+ <30>
EDP_LVDS_A4+ <30>
EDP_LVDS_B3+ <30>
EDP_LVDS_B4+ <30>
1 2
1 2
1 2
1 2
1 2
+LCDVDD +3.3V_RUN+BL_PWR_SRC
0.1U_0603_50V7K~D
2
C249
1
EDP_LVDS_A0+ <30>
EDP_LVDS_A1- <30>
EDP_LVDS_A2- <30>
EDP_LVDS_B0- <30>
EDP_LVDS_B1- <30>
EDP_LVDS_B2- <30>
EDP_LVDS_A3- <30>
EDP_LVDS_A4- <30>
EDP_LVDS_B3- <30>
EDP_LVDS_B4- <30>
4
BIA_PWM_LVDS
10K_0402_5%~D
12
changetonewmanufacturing
technologyforcostdown.
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C298
C243
1
1
2
2
+LCDVDD
+BL_PWR_SRC
LinkCISOK_0802
4
DGPU_SELECT#<27,32,48>
RB751VM-40TE-17_SOD323-2~D
R1137
DISP_ON
+3.3V_RUN
3
+3.3V_RUN +3.3V_ALW
1 2
LDDC_CLK_SW
R159 2.2K_0402_5%~D
1 2
LDDC_DATA_SW
R160 2.2K_0402_5%~D
LCDPower
Place near to JLVDS1
+3.3V_RUN
1 2
C248
0.1U_0402_10V7K~D
5
D100
100K_0402_5%~D
12
Webcam Circuit
1
4
OE#
D101
21
D66
21
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
+CAMERA_VDD
0.1U_0402_25V6K~D
C299
1
2
P
A2Y
G
TC7SH125FU_SSOP5
3
preventmaterialshortageforThaiflood.
D67
D64
D69
10U_0805_10V6K~D
1
2
21
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
R1138
U3
C300
21
21
21
CCD_OFF<48>
MXM_BIA_PWM <16>
BIA_PWM_EC <49>
BIA_PWM_PCH <19>
PANEL_BKEN_PCH <19>
MXM_PANEL_BKEN <16>
PANEL_BKEN_EC <48>
PMV65XP_SOT23-3~D
1 3
D
changetonewmanufacturing
technologyforcostdown.
ENVDD_PCH<19,48>
RB751VM-40TE-17_SOD323-2~D
LCD_VCC_TEST_EN<48>
MXM_ENVDD<16>
BAT54CW_SOT323-3~D
+3.3V_RUN
Q24
S
G
2
0.1U_0402_25V6K~D
C301
1
2
2
+LCDVDD
130_0402_1%~D
12
D53
5@
2 1
D6
2
3
R413
+LCVDVDD_CHG
DMN66D0LDW-7_SOT363-6~D
61
Q19A
2
1
2
+3.3V_ALW
10K_0402_5%~D
12
13
+PWR_SRC_S
R414
5
Q20
PDTC124EU_SC70-3~D
PanelbacklightpowercontrolbyEC
+PWR_SRC
1000P_0402_50V7K~D
12
1
C297
2
FDC654P-G_SSOT-6~D
40mil
4 5
R422
100K_0402_5%~D
PWR_SRC_ON
1 2
R423 47K_0402_5%~D
EN_INVPWR<49>
SI3456DDV-T1-GE3_TSOP6~D
+LCDVDD
470K_0402_5%~D
12
R412
Solve300mW
PWRconsumption
issue.
DMN66D0LDW-7_SOT363-6~D
3
12
Q19B
4
Q21
D
6
S
2
1
G
3
Q22
SSM3K7002FU_SC70-3~D
D
1 3
2
1
Q18
D
S
6
4 5
2
1
G
3
4.7M_0402_5%~D
0.022U_0402_25V7K~D
R1632
1
C293
2
40mil
1
C296
0.1U_0603_50V7K~D
2
S
G
FDC654P: P CHANNAL
WrongCPNforprefixnumber.
L10
DLW21SN121SQ2L_4P~D
USBP12-<20>
USBP12+<20>
CONN@
JLVDS3
2
112
4
334
6
556
8
778
10
9910
12
111112
14
131314
16
151516
18
171718
20
191920
22
GND21GND
ACES_50238-0207N-002
DMIC_CLK
DMIC0
LCD_SMBCLK
LCD_SMBDAT
4
4
1
1
R427 0_0402_5%~D@
R428 0_0402_5%~D@
D13
3
2
PESD5V0U2BT_SOT23-3~D
ForEMIrequest.
100P_0402_50V8J~D
100P_0402_50V8J~D
1
@
@
C1341
C1342
2
3
3
3
2
2
1 2
1 2
1
LCD_SMBCLK <26,49>
LCD_SMBDAT <26,49>
1
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
USBP12_D-
USBP12_D+
2
3
1
PESD5V0U2BT_SOT23-3~D
D87
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
LVDS & CAM & TS
LVDS & CAM & TS
LVDS & CAM & TS
LA-7931P
LA-7931P
LA-7931P
1
+BL_PWR_SRC
28 70Monday, July 23, 2012
28 70Monday, July 23, 2012
28 70Monday, July 23, 2012
0.1U_0402_25V6K~D
C292
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1
DP v1.2 Redriver
+3.3V_RUN+3.3V_RUN
12
R1977
D D
C C
@
4.7K_0402_5%
PEQ_DP
12
R1979
@
4.7K_0402_5%
Programmable input equalization levels; Internal pull down at ~150k ohm, 3.3V
I/O.
L: default, LEQ, compensate channel loss up to 12dB @ HBR2
H: HEQ, compensate channel loss up to 15dB @ HBR2
M: LLEQ, compensate channel loss up to 5dB @ HBR2
Configuration pin for automatic EQ and AUX interception; Internal pull down at ~150k ohm, 3.3V
I/O.
L: default, automatic EQ enable & AUX interception enable
H: automatic EQ disable & AUX interception enable
M: automatic EQ disable & AUX interception disable, no pre-emphasis, 600mVpp swing
Configuration pin for auto test and input offset cancellation, 3.3V IO, internal pull up at ~150K
H: default, auto test disable & input offset cancellation enable
L: auto test enable & input offset cancellation enable
M: auto test disable & input offset cancellation disable
12
@
12
@
SolveDP‐>HDMI/DP‐>S‐DVIdonglenofunctiononNVunits.
MXMDP_ADongleDDC
B B
DPB_MB_CA_DET
Fordebugissuethat(DF543750)DP‐>HDMI/DP‐>S‐DVIdongle
nofunctiononNVunits
A A
AddTMDSDDCpullupschematiconDPport
R1983
4.7K_0402_5%
CFG0_RE
R1984
4.7K_0402_5%
1
2
+3.3V_RUN
0.01U_0402_16V7K~D
C1343
12
R1988
@
4.7K_0402_5%
12
R1989
@
4.7K_0402_5%
+3.3V_ALW2
100K_0402_5%~D
2
CFG1_RE
12
R2200
61
+3.3V_RUN
0.1U_0402_25V6K~D
C1200
1
1
C1201
0.01U_0402_16V7K~D
2
2
25
36
1
6
U627
MXM_MB_DP_P0<16>
MXM_MB_DP_N0<16>
MXM_MB_DP_P1<16>
MXM_MB_DP_N1<16>
MXM_MB_DP_P2<16>
MXM_MB_DP_N2<16>
MXM_MB_DP_P3<16>
MXM_MB_DP_N3<16>
MXM_MB_DP_P0
MXM_MB_DP_N0
MXM_MB_DP_P1
MXM_MB_DP_N1
MXM_MB_DP_P2
MXM_MB_DP_N2
MXM_MB_DP_P3
MXM_MB_DP_N3
PD#:Internalpullup150kohm.
MXM_MB_DP_AUX<16>
MXM_MB_DP_AUX#<16>
MXM_MB_DP_AUX
MXM_MB_DP_AUX#
1 2
C1304 0.1U_0402_10V6K~D
1 2
C1305 0.1U_0402_10V6K~D
1 2
C1299 0.1U_0402_10V6K~D
1 2
C1300 0.1U_0402_10V6K~D
1 2
C1301 0.1U_0402_10V6K~D
1 2
C1302 0.1U_0402_10V6K~D
1 2
C1303 0.1U_0402_10V6K~D
1 2
C1306 0.1U_0402_10V6K~D
1 2
R1982 4.99K_0402_1%
MXM_MB_DP_HPD<16>
C1213
1 2
1 2
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
C1214
PEQ_DP
CFG0_RE
MXM_MB_DP_HPD
MXM_MB_DP_AUX
MXM_MB_DP_AUX#
AUX_SRCP
AUX_SRCN
AccordingtonewEIAruleandchangepackagetoGTR2
+3.3V_RUN
2.2K_0402_5%~D
+3.3V_RUN
2.2K_0402_5%~D
R2201
5
2
12
3
4
12
R2198
61
DMN66D0LDW-7_SOT363-6 ~D
Q340B
DMN66D0LDW-7_SOT363 -6~D
Q340A
MXM_MB_DP_AUX
MXM_MB_DP_AUX#
Place close JDP
MXM_MB_DP_P0_C MXM_MB_DP_P0_C
MXM_MB_DP_N0_C
MXM_MB_DP_N3_C
MXM_MB_DP_P3_C
+3.3V_RUN
ESD request change main source to SC300002F0L.
D88
@
1
2
4
5
3
8
IP4292CZ10-TBR_XSON10_2.5X1~D
3
2 1
BAT1000-7-F_SOT23-3~D
10
9
MXM_MB_DP_N0_C
7
MXM_MB_DP_N3_C
6
MXM_MB_DP_P3_C MXM_MB_DP_P2_C
D90
NC
+5V_RUN
100K_0402_5%~D
12
R2199
DP_A_MXM_AUX_Q
DMN66D0LDW-7_SOT363-6 ~D
3
Q339B
5
4
DMN66D0LDW-7_SOT363-6 ~D
Q339A
38
IN0P
IN0p
39
IN0N
IN0n
41
IN1P
IN1p
42
IN1N
IN1n
44
IN2P
IN2p
45
IN2N
IN2n
47
IN3P
IN3p
48
IN3N
IN3n
3
I2C_ADDR
4
SCL_CTL/PEQ
5
SDA_CTL/CFG0
26
PD#
7
REXT
8
CAD_SRC
9
HPD_SRC
33
SCL_DDC
34
SDA_DDC
30
AUX_SRCP
29
AUX_SRCN
PS8330BQFN48GTR2-A0_QFN48_7X7
F6
21
1.1A_6V_SMD1812P110TF
R1990 0_1206_5%@
12
12
23
OUT0P
VCC4
VCC532VCC6
VCC1
VCC2
VCC3
OUT0p
OUT0n
OUT1p
OUT1n
OUT2p
OUT2n
OUT3p
OUT3n
CFG1
NC
RST#
CAD_SNK
HPD_SINK
AUX_SNKP
AUX_SNKN
CEXT
NC2
NC3
NC4
NC5
EPAD
GND3
GND118GND2
49
31
24
D89
@
MXM_MB_DP_P1_C MXM_MB_DP_P1_C
MXM_MB_DP_N1_C MXM_MB_DP_N1_C
MXM_MB_DP_P2_C
1
2
4
5
3
8
IP4292CZ10-TBR_XSON10_2.5X1~D
+3.3V_RUN_DP
W=40mils
C1217
0.1U_0402_25V6K~D
1
1
2
2
C1219
0.1U_0402_25V6K~D
C1218
10U_0603_6.3V6M~D
1
2
C1202 0.1U_0402_10V6K~D
22
OUT0N
C1203 0.1U_0402_10V6K~D
20
OUT1P
C1204 0.1U_0402_10V6K~D
19
OUT1N
C1205 0.1U_0402_10V6K~D
17
OUT2P
C1206 0.1U_0402_10V6K~D
16
OUT2N
C1207 0.1U_0402_10V6K~D
14
OUT3P
C1208 0.1U_0402_10V6K~D
13
OUT3N
C1209 0.1U_0402_10V6K~D
40
CFG1_RE
46
35
10
11
28
27
2
15
21
37
43
R1980 10K_0402_5%~D
C1210 2.2U_0603_10V7K~D
DPB_MB_CA_DET
DP_SW_HPD
MXM_MB_DP_SW_AUX
MXM_MB_DP_SW_AUX#
C1215
10
9
7
MXM_MB_DP_N2_CMXM_MB_DP_N2_C
6
C1220
22U_0805_6.3V6M~D
1
2
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2.2U_0603_10V7K~D
MXM_MB_DP_SW_AUX#
MXM_MB_DP_SW_AUX
DP_MB_P14
DP_HPD
MXM_MB_DP_P0_C
MXM_MB_DP_N0_C
MXM_MB_DP_P1_C
MXM_MB_DP_N1_C
MXM_MB_DP_P2_C
MXM_MB_DP_N2_C
MXM_MB_DP_P3_C
MXM_MB_DP_N3_C
1 2
R1981 1M_0402_5%~D
preventthebackdrive
currentdamagingredriver.
+3.3V_RUN_DP
DP_HPD
MXM_MB_DP_SW_AUX#
MXM_MB_DP_SW_AUX
DP_MB_P14
DPB_MB_CA_DET
MXM_MB_DP_N3_C
MXM_MB_DP_P3_C
MXM_MB_DP_N2_C
MXM_MB_DP_P2_C
MXM_MB_DP_N1_C
MXM_MB_DP_P1_C
MXM_MB_DP_N0_C
MXM_MB_DP_P0_C
1 2
R1976 100K_0402_5%
1 2
R1978 100K_0402_5%
1 2
R1985 5.1M_0603_1%~D
1 2
R1987 1M_0402_5%
+3.3V_RUN
+5V_RUN
G
2
DP_SW_HPD
13
D
S
Q323
BSS138-G_SOT23-3
Vgs <=1.5 V
JDP1
CONN@
20
DP_PWR
19
RTN
18
HP_DET
17
AUX_CH-
16
GND
15
AUX_CH+
14
GND
13
CA_DET
12
LANE3-
11
LANE3_shield
10
LANE3+
9
LANE2-
8
LANE2_shield
7
LANE2+
6
LANE1-
5
LANE1_shield
4
LANE1+
3
LANE0-
2
LANE0_shield
1
LANE0+
FOX_3V1121C-N1YD7-7H
Link CIS OK_0722
DP_HPD
GND
GND
GND
GND
+3.3V_RUN
21
22
23
24
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP Redriver & DP CONN
DP Redriver & DP CONN
DP Redriver & DP CONN
LA-7931P
LA-7931P
LA-7931P
1
29 70Monday, July 23, 2012
29 70Monday, July 23, 2012
29 70Monday, July 23, 2012
1.0
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Page 30
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preventcurrentleakage.
+1.2V_AVDD
6@
0.1U_0402_10V6K~D
6@
240_0402_1%
12
C1221
MXM_EDP_AUX-_C
MXM_EDP_AUX+_C
MXM_EDP_TX0-_C
MXM_EDP_TX0+_C
MXM_EDP_TX1-_C
MXM_EDP_TX1+_C
27M_XO
SPI_DI
SPI_DO
SPI_CLK
SPI_CS#
EDP_BOOT7
EDP_BOOT6
EDP_BOOT5
EDP_BOOT4
EDP_BOOT3
EDP_BOOT2
EDP_BOOT1
EDP_BOOT0
R2035
C10
D10
B9
C9
B8
A8
B7
A7
C6
B6
D5
C5
A3
A2
E5
D13
E11
E12
F12
G4
D12
D4
F3
G3
BootStraps
U629C
6@
DPRX_REXT
DPRX_HPD_OUT/GPIO_26
DPRX_AUXN
DPRX_AUXP
DPRX_ML_L0N
DPRX_ML_L0P
DPRX_ML_L1N
DPRX_ML_L1P
DPRX_ML_L2N
DPRX_ML_L2P
DPRX_ML_L3N
DPRX_ML_L3P
TCLK
XTAL
RESETn
SPI_DI/HOST_D1/GPO_19
SPI_DO/HOST_D0/GPO_20
SPI_CLK/HOST_CLK/GPIO_18
SPI_CSn/HOST_CS/GPIO_17
IR_IN/GPIO_12
IRQ/GPIO_25
VBUFC_RPLL
TESTMODE0
TESTMODE1
STDP4010_LFBGA164~D
SYS, Audio & DPRX
AUX_I2C_SCL/GPIO_15
AUX_I2C_SDA_GPIO_16
I2C_SCL/GPIO_21
I2C_SDA/GPIO_22
I2C_MST_SCL/GPIO_2
I2C_MST_SDA/GPIO_3
UART_TX/BOOT6/GPIO_13
UART_RX/GPIO_14
AUX_UART_TX/BOOT7/GPIO_23
AUX_UART_RX/GPIO_24
I2S_0/BOOT2/GPIO_8
I2S_1/BOOT3/GPIO_9
I2S_2/BOOT4/GPIO_10
I2S_3/BOOT5/GPIO_11
I2S_BCLK/BOOT1/GPIO_7
I2S_WCLK/BOOT0/GPIO_6
I2S_MCLK/GPIO_4
CLK_OUT/GPIO_5
D D
prevent AUX swing overshoot
1 2
MXM_EDP_AUX-<16>
MXM_EDP_AUX+<16>
C C
R2188 10_0402_1%~D6@
R2187 10_0402_1%~D6@
1 2
MXM_EDP_AUX-_R
MXM_EDP_AUX+_R
MXM_EDP_TX0-<16>
MXM_EDP_TX0+<16>
MXM_EDP_TX1-<16>
MXM_EDP_TX1+<16>
1 2
C1291 0.1U_0402_10V6K~D6@
1 2
C1292 0.1U_0402_10V6K~D6@
1 2
C1293 0.1U_0402_10V6K~D6@
1 2
C1294 0.1U_0402_10V6K~D6@
1 2
C1295 0.1U_0402_10V6K~D6@
1 2
C1296 0.1U_0402_10V6K~D6@
1
2
MXM_EDP_HPD<16>
meetRGBpanelsequencing meetRGBpanelsequencing
6@
12
2.7K_0402_5%~D
R2038
47P_0402_50V8J~D
6@
1
C1222
2
PLACETHESEPARTSNEARSTDP4010
B B
A A
27M_XI 27M_XO
15P_0402_50V8J~D
vendor suggest.
Y76@27MHZ_12PF_X3G027000FC1H~D
1
2
6@
C1225
1 2
+3.3V_AVDDL +3.3V_AVDDL
IN
GND
OUT
GND
3
4
1 2
R2050 0_0402_5%~D
6@
6@
C1226
12P_0402_50V8J~D
1 2
+3.3V_AVDD
R2073 1M_0402_5%~D6@
1 2
R2043 4.7K_0402_5%~D6@
1 2
R2044 4.7K_0402_5%~D6@
1 2
R2045 4.7K_0402_5%~D6@
1 2
R2042 4.7K_0402_5%~D6@
1 2
R2046 4.7K_0402_5%~D6@
1 2
R2047 4.7K_0402_5%~D6@
1 2
R2048 4.7K_0402_5%~D6@
1 2
R2049 4.7K_0402_5%~D6@
R2074 1M_0402_5%~D6@
1 2
R2075 100K_0402_5%
12
12
MXM_EDP_AUX+
MXM_EDP_AUXMXM_EDP_HPD
+3.3V_AVDD
6@
4.7K_0402_5%~D
12
R2036
C13
B14
B13
D11
+5V_RUN
G10
F11
A1
EDP_BOOT6
E4
UART_RX
B12
EDP_BOOT7
A12
B1
EDP_BOOT227M_XI
G5
EDP_BOOT3
F4
EDP_BOOT4
E3
EDP_BOOT5
C2
EDP_BOOT1
D3
EDP_BOOT0
D2
C1
EDP_MODE
G11
NC1
G12
NC2
C11
NC3
A13
NC4
B4
NC5
E6
GPIO_0
C3
GPIO_1
R2080 10K_0402_5%~D6@
meetRGBpanelsequencing
+3.3V_AVDD
10K_0402_5%~D
6@
12
R2040
SPI_CS#
SPI_DI
6@
4.7K_0402_5%~D
12
R2037
EDP_CLK
EDP_DATA
6@
4.7K_0402_5%~D
1 2
R2077
@
1 2
1 2
R2078
@
R2076
0_0402_5%~D
0_0402_5%~D
EDP_CLK <28>
EDP_DATA <28>
PinE4:GeneralPurposeSchmitt
triggerInput/Tri‐state
Output14[5VTolerant]
EDP_MODE
EDP_MODE
1 2
4.7U_0603_6.3V6K~D
6@
1
C1223
2
U630
6@
1
CS#
VCC
2
SO
HOLD#
3
WP#
SCLK
4
GND
MX25L1005AMC-12G_SO8
1Mb Flash ROM
6@
@
SI
R2039
R2079
0.1U_0402_10V6K~D
1
2
8
7
6
5
12
12
MXM_EDP_AUX+
6@
C1224
4.7K_0402_5%~D
4.7K_0402_5%~D
10K_0402_5%~D
6@
12
R2041
SPI_CLK
SPI_DO
+3.3V_AVDD+3.3V_AVDD
U629B
6@
L9
O0_LVTX_CH5N
M8
O0_LVTX_CH5P
M12
O0_LVTX_CH6N
L11
O0_LVTX_CH6P
O0 & O1 LVDS Output
H11
O1_LVTX_CH5N
J10
O1_LVTX_CH5P
J11
O1_LVTX_CH6N
K10
O1_LVTX_CH6P
STDP4010_LFBGA164~D
U629A
6@
L6
E0_LVTX_CH5N
M7
E0_LVTX_CH5P
L4
E0_LVTX_CH6N
M3
E0_LVTX_CH6P
E0 & E1 LVDS Output
H4
E1_LVTX_CH5N
J5
E1_LVTX_CH5P
K5
E1_LVTX_CH6N
J4
E1_LVTX_CH6P
STDP4010_LFBGA164~D
O0_LVTX_CH0N
O0_LVTX_CH0P
O0_LVTX_CH1N
O0_LVTX_CH1P
O0_LVTX_CH2N
O0_LVTX_CH2P
O0_LVTX_CLKN
O0_LVTX_CLKP
O0_LVTX_CH3N
O0_LVTX_CH3P
O0_LVTX_CH4N
O0_LVTX_CH4P
O1_LVTX_CH0N
O1_LVTX_CH0P
O1_LVTX_CH1N
O1_LVTX_CH1P
O1_LVTX_CH2N
O1_LVTX_CH2P
O1_LVTX_CLKN
O1_LVTX_CLKP
O1_LVTX_CH3N
O1_LVTX_CH3P
O1_LVTX_CH4N
O1_LVTX_CH4P
E0_LVTX_CH0N
E0_LVTX_CH0P
E0_LVTX_CH1N
E0_LVTX_CH1P
E0_LVTX_CH2N
E0_LVTX_CH2P
E0_LVTX_CLKN
E0_LVTX_CLKP
E0_LVTX_CH3N
E0_LVTX_CH3P
E0_LVTX_CH4N
E0_LVTX_CH4P
E1_LVTX_CH0N
E1_LVTX_CH0P
E1_LVTX_CH1N
E1_LVTX_CH1P
E1_LVTX_CH2N
E1_LVTX_CH2P
E1_LVTX_CLKN
E1_LVTX_CLKP
E1_LVTX_CH3N
E1_LVTX_CH3P
E1_LVTX_CH4N
E1_LVTX_CH4P
N13
P13
N12
P12
M11
N11
L10
M10
M9
N9
N8
P8
G14
G13
H14
H13
J13
J12
K11
K12
L13
L12
M14
M13
N7
P7
M6
N6
L5
M5
M4
N4
N3
P3
N2
P2
M2
M1
L3
L2
K4
K3
J3
J2
H2
H1
G2
G1
EDP_LVDS_A0- <28>
EDP_LVDS_A0+ <28>
EDP_LVDS_A1- <28>
EDP_LVDS_A1+ <28>
EDP_LVDS_A2- <28>
EDP_LVDS_A2+ <28>
EDP_LVDS_ACLK- <28>
EDP_LVDS_ACLK+ <28>
EDP_LVDS_A3- <28>
EDP_LVDS_A3+ <28>
EDP_LVDS_A4- <28>
EDP_LVDS_A4+ <28>
EDP_LVDS_B0- <28>
EDP_LVDS_B0+ <28>
EDP_LVDS_B1- <28>
EDP_LVDS_B1+ <28>
EDP_LVDS_B2- <28>
EDP_LVDS_B2+ <28>
EDP_LVDS_BCLK- <28>
EDP_LVDS_BCLK+ <28>
EDP_LVDS_B3- <28>
EDP_LVDS_B3+ <28>
EDP_LVDS_B4- <28>
EDP_LVDS_B4+ <28>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
eDP to LVDS(1)
eDP to LVDS(1)
eDP to LVDS(1)
LA-7931P
LA-7931P
LA-7931P
1
30 70Monday, July 23, 2012
30 70Monday, July 23, 2012
30 70Monday, July 23, 2012
1.0
1.0
1.0
of
of
of
Page 31
5
4
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1
Find 60 R 600 mA @100Mhz
+3.3V_AVDD
D D
C C
+1.2V_RUN +1.2V_AVDD
B B
L55
6@
BLM18PG330SN1D_0603
12
L53
6@
BLM18PG330SN1D_0603
12
+1.2V_AVDD
10U_0603_6.3V6M~D
6@
1
1
C1267
2
2
22U_0805_6.3V6M~D
6@
1
1
C1236
2
2
0.1U_0402_10V6K~D
22U_0805_6.3V6M~D
6@
C1240
1
1
2
2
4.7U_0603_6.3V6K~D
+LCDVDD
6@
C1268
ChangeU631solutiontonewp/n:SA00005EU00
meetRGBpanelsequencing
+3.3V_AVDD
10U_0805_6.3V6M
6@
1
C1254
2
APL5932BKAI-TRG_SO8
U631
6@
1
POK
3
VIN
4
VCNTL
2
EN
8
VOUT
GND
9
6
7
FB
5
NC
GND
+3.3V_AVDDL
0.01U_0402_25V7K~D
0.1U_0402_10V6K~D
6@
C1241
6@
C1237
1
2
0.1U_0402_10V6K~D
1
2
6@
C1242
6@
0.1U_0402_10V6K~D
6@
C1239
1
C1238
2
0.1U_0402_10V6K~D
6@
0.1U_0402_10V6K~D
6@
C1244
C1243
1
1
2
2
meetRGBpanelsequencing
L56
6@
BLM18PG330SN1D_0603
BLM18PG330SN1D_0603
12
L57
@
12
6@
12
10K_0402_5%
R2051
6@
20K_0402_5%
12
R2053
+1.2V_RUN
1
2
+1.2V_RUN
0.1U_0402_10V6K~D
22U_0805_6.3V6M~D
6@
C1245
1
2
6@
0.1U_0402_10V6K~D
6@
C1247
C1246
1
1
2
2
0.1U_0402_10V6K~D
6@
0.1U_0402_10V6K~D
6@
C1249
C1248
1
1
2
2
meetRGBpanelsequencing
+3.3V_AVDD
0.1U_0402_10V6K~D
22U_0805_6.3V6M~D
+1.2V_AVDD
+3.3V_AVDD+3.3V_RUN
+3.3V_AVDD +3.3V_AVDD_LVTX
10U_0805_6.3V6M
6@
C1253
Find 60 R 600 mA @100Mhz
L54
6@
BLM18PG330SN1D_0603
Find 60 R 600 mA @100Mhz
L52
6@
BLM18PG330SN1D_0603
12
0.1U_0402_10V6K~D
6@
C1227
1
2
12
22U_0805_6.3V6M~D
6@
C1230
1
2
6@
6@
C1229
C1228
1
1
2
2
+1.2V_VDD_RPLL
0.01U_0402_25V7K~D
22U_0805_6.3V6M~D
6@
0.1U_0402_10V6K~D
C1250
1
1
2
2
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
6@
C1231
1
1
2
2
6@
C1251
6@
C1232
6@
C1252
1
2
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
6@
6@
C1234
C1233
1
1
2
1
2
2
+3.3V_AVDDL
+1.2V_AVDD
0.1U_0402_10V6K~D
6@
C1235
U629D
E7
PVDD1
C12
PVDD1
K6
PVDD1
K9
PVDD1
E8
PVDD1
F5
PVDD22
F10
PVDD21
B3
VDD_RPLL
D6
VDDA_3V3
L7
AVDD_LVTX_33
B11
DPRX_VDDA_1V2
C7
DPRX_VDDA_1V2
C8
DPRX_VDDA_1V2
D9
DPRX_VDDA_1V2
N1
AVDD_OUT_LVTX_33
N14
AVDD_OUT_LVTX_33
L8
AVDD_OUT_LVTX_33
H3
AVDD_OUT_LVTX_33
H12
AVDD_OUT_LVTX_33
STDP4010_LFBGA164~D
6@
PWR & GND
AVSS_OUT_LVTX
AVSS_OUT_LVTX
AVSS_OUT_LVTX
AVSS_OUT_LVTX
AVSS_OUT_LVTX
AVSS_OUT_LVTX
AVSS_OUT_LVTX
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
DPRX_VSSA
DPRX_VSSA
DPRX_VSSA
DPRX_VSSA
VSS_RPLL
AVSS_LVTX
A14
C14
C4
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
E9
D7
D8
E10
B2
K7
P14
P1
F2
F13
H5
K8
H10
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
eDP to LVDS(2)
eDP to LVDS(2)
eDP to LVDS(2)
LA-7931P
LA-7931P
LA-7931P
31 70Monday, July 23, 2012
31 70Monday, July 23, 2012
31 70Monday, July 23, 2012
1
1.0
1.0
1.0
Page 32
5
4
3
2
1
+5V_RUN
U19
7
MXM_CRT_RED<16>
PCH_CRT_RED<19>
MXM_CRT_GRN<16>
Channel A --> GPU
D D
Channel B --> PCH
CRT_SWITCH
DGPU_SELECT#
EDID_SELECT#
0
0
0
0
1
PCH_CRT_GRN<19>
MXM_CRT_BLU<16>
PCH_CRT_BLU<19>
MXM_CRT_DDC_CLK<16>
PCH_CRT_DDC_CLK<19>
MXM_CRT_DDC_DAT<16>
PCH_CRT_DDC_DAT<19>
1 2
+3.3V_RUN
R421 100K_0402_5%~D
MXM_CRT_HSYNC<16>
PCH_CRT_HSYNC<19>
MXM_CRT_VSYNC<16>
PCH_CRT_VSYNC<19>
EDID_SELECT#<48>
CRT_SWITCH<48>
DGPU_SELECT#<27,28,48>
CRT_EN
CRT_SWITCH
11
10
011
MAX14885E
REDA
17
REDB
8
GRNA
18
GRNB
9
BLUA
19
BLUB
5
SCLA
15
SCLB
6
SDAA
16
SDAB
2
EN
3
SHA
13
SHB
4
SVA
14
SVB
1
S00
40
S01
39
S10
38
S11
30
GND
20
GND
10
GND
41
GPAD
MAX14885EETL+T_TQFN40_5X5~D
VCC
VCC
RED1
RED2
GRN1
GRN2
BLU1
BLU2
SCL1
SCL2
SDA1
SDA2
SH1
SH2
29
21
11
VL
33
24
32
23
31
22
35
26
34
25
37
28
36
SV1
27
SV2
12
NC
RED_CRT
GREEN_CRT
BLUE_CRT
CLK_DDC2_CRT
DAT_DDC2_CRT
HSYNC_BUF
VSYNC_BUFCRT_SWITCH
1
C1182
1U_0603_10V7K~D
2
+3.3V_RUN
RED_DOCK <46>
GREEN_DOCK <46>
BLUE_DOCK <46>
CLK_DDC2_DOCK <46>
DAT_DDC2_DOCK <46>
HSYNC_DOCK <46>
VSYNC_DOCK <46>
1U_0402_6.3V6K~D
1
C1181
2
Port 1 --> MB Port RGB
Port 2 --> Docking Port RGB
A --> Port 1 B --> Port 1 A --> Port 2 B --> Port 2
C C
RED_CRT RED_CRT_L
GREEN_CRT
BLUE_CRT
12
R53
B B
150_0402_1%~D
12
12
R55
R54
150_0402_1%~D
150_0402_1%~D
22P_0402_50V8J~D
22P_0402_50V8J~D
1
1
C20
2
2
EMI Request. EMI Request.
1 2
L1 BLM18BB470SN1D_2P~D
1 2
L2 BLM18BB470SN1D_2P~D
1 2
L3 BLM18BB470SN1D_2P~D
22P_0402_50V8J~D
1
C22
C23
2
DAT_DDC2_CRT
CLK_DDC2_CRT
ESD request reserve it.
PESD5V0U2BT_SOT23-3~D
2
3
@
D91
1
GREEN_CRT_L
BLUE_CRT_L
10P_0402_50V8J~D
1
C21
2
+5V_RUN_CRT
1K_0402_5%~D
1K_0402_5%~D
12
12
@
@
R50
R52
PESD5V0U2BT_SOT23-3~D
2
3
@
D92
1
10P_0402_50V8J~D
1
C12
2
10P_0402_50V8J~D
1
C13
2
+5V_RUN_CRT
0.5A_8VDC_SMD1812P200TF
21
+5V_RUN
F5
21
3
NC
0_1206_5%~D
1 2
DAT_DDC2_CRT
D9
BAT1000-7-F_SOT23-3~D
+CRT_VCC
1U_0402_6.3V6K~D
1
@
C14
R49
2
CLK_DDC2_CRT
+CRT_VCC
M_ID2#
0.1U_0402_16V4Z~D
1
C15
2
T61
PAD~D
@
6
CRT_11
11
1
7
12
2
8
13
3
9
14
4
10
15
5
SUYIN_070449HR015M221ZR
LinkCISOK
0722
CONN@
JCRT1
16
G
17
G
18
G
19
G
L4
1 2
HSYNC_BUF
A A
5
VSYNC_BUF
R43 0_0402_5%~D
1 2
R44 0_0402_5%~D
1 2
BLM18AG121SN1D_0603~D
L5
1 2
BLM18AG121SN1D_0603~D
4
HSYNC_L
VSYNC_L
22P_0402_50V8J~D
22P_0402_50V8J~D
@
@
1
1
C18
C19
2
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
VGA
VGA
VGA
LA-7931P
LA-7931P
LA-7931P
32 70Monday, July 23, 2012
32 70Monday, July 23, 2012
32 70Monday, July 23, 2012
1
of
of
of
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Page 33
5
D D
4
3
2
1
AUX/DDCGPUforDPCtoE‐DOCK
U20
C C
B B
MXM_DPB_AUX<16>
MXM_DPB_AUX#<16>
R2089 0_0402_5%~D@
R2090 0_0402_5%~D@
1 2
1 2
HDMI/DVI
DP
DPC_DOCK_AUX DPC_DOCK_AUX_C
DPC_DOCK_SW_AUX<45,46>
DPC_DOCK_AUX#
DPC_DOCK_SW_AUX#<45,46>
CA_DET
1
0
Output
A2=B2
A3=B3
A0=B0
A1=B1
DPC_CA_DET<45,46>
12
C1308 0.1U_0402_10V7K~D
12
DPC_DOCK_AUX#_C
C1309 0.1U_0402_10V7K~D
DPC_CA_DET DPC_CA_DET#
R2128
1 2
1M_0402_5%~D
1
2
3
4
5
6
7
C1310
0.1U_0402_25V6K~D
BE0
A0
B0
BE1
A1
B1
GND
PI3C3125LEX_TSSOP14~D
+5V_RUN
12
A2Y
14
VCC
13
BE3
12
A3
11
B3
10
BE2
9
A2
8
B2
5
1
U636
P
4
NC
G
NC7ST04P5X_SC70-5~D
3
preventmaterialshortageforThaiflood.
+3.3V_RUN
0.1U_0402_25V6K~D
DPC_DOCK_AUX
DPC_DOCK_AUX#
1 2
C1307
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Docking DP/DMC MUX
Docking DP/DMC MUX
Docking DP/DMC MUX
LA-7931P
LA-7931P
LA-7931P
33 70Monday, July 23, 2012
33 70Monday, July 23, 2012
33 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
Page 34
5
4
3
2
1
+3.3V_RUN
4.7U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C410
1
1
1
C766
2
2
2
D D
MXM_DPC_P0<16>
MXM_DPC_N0<16>
MXM_DPC_P1<16>
MXM_DPC_N1<16>
MXM_DPC_P2<16>
MXM_DPC_N2<16>
MXM_DPC_P3<16>
MXM_DPC_N3<16>
R518
DOCKED#
MXM_DPC_AUX<16,45>
MXM_DPC_AUX#<16,45>
MXM_DPC_HPD<16>
Change from 100k to 10kohm
to meet the input high-level voltage.
SSM3K7002FU_SC70-3~D
C C
DOCKED<37,48>
+3.3V_RUN
10K_0402_5%~D
12
Q328
13
D
2
G
S
ForControlSwitching:
SW=L:DPoutputisselected
SW=H:TMDSoutputisselected
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
MXM_DPC_HPD
REXT3 REXT3
4.99K_0402_1%~D
R74
2.2U_0402_6.3V6M
C86
1
1 2
2
CEXT
C405
1
2
12
C2530.1U_0402_10V6K~D
12
C2470.1U_0402_10V6K~D
12
C2420.1U_0402_10V6K~D
12
C2520.1U_0402_10V6K~D
12
C2510.1U_0402_10V6K~D
12
C2540.1U_0402_10V6K~D
12
C2450.1U_0402_10V6K~D
12
C2460.1U_0402_10V6K~D
C389
12
C390
12
0.1U_0402_16V4Z~D
C437
C402
1
2
DP_CFG0
DOCKED#
MXM_DPC_P0_C
MXM_DPC_N0_C
MXM_DPC_P1_C
MXM_DPC_N1_C
MXM_DPC_P2_C
MXM_DPC_N2_C
MXM_DPC_P3_C
MXM_DPC_N3_C
MXM_DPC_AUX_C
MXM_DPC_AUX#_C
CEXT
TMDS_DDCBUF
PEQ
MODE
U9
14
VDD33
28
VDD33
41
VDD33
56
VDD33
44
DP_CFG0/SCL_CTL
45
SW/SDA_CTL
38
I2C_CTL_EN
3
IN_D0p
4
IN_D0n
6
IN_D1p
7
IN_D1n
9
IN_D2p
10
IN_D2n
12
IN_D3p
13
IN_D3n
52
IN_AUXp
51
IN_AUXn
50
IN_DDC_SCL
49
IN_DDC_SDA
11
IN_CA_DET
5
IN_HPD
1
CEXT
2
TMDS_DDCBUF
8
PEQ
27
REXT
46
PD
53
MODE
PS8336BQFN56GTR-A0_QFN56_7X7
DP_D0p
DP_D0n
DP_D1p
DP_D1n
DP_D2p
DP_D2n
DP_D3p
DP_D3n
DP_AUXp_SCL
DP_AUXn_SDA
DP_HPD
DP_CA_DET
DP_CFG1
TMDS_CH0p
TMDS_CH0n
TMDS_CH1p
TMDS_CH1n
TMDS_CH2p
TMDS_CH2n
TMDS_CLKp
TMDS_CLKn
TMDS_SCL
TMDS_SDA
TMDS_HPD
TMDS_RT
TMDS_PRE
Thermal/GND
Choice DDC active buffer mode.
40
DPD_GPU_LANE_P0
39
DPD_GPU_LANE_N0
37
DPD_GPU_LANE_P1
36
DPD_GPU_LANE_N1
34
DPD_GPU_LANE_P2
33
DPD_GPU_LANE_N2
31
DPD_GPU_LANE_P3
30
DPD_GPU_LANE_N3
55
DPD_DOCK_AUX
54
DPD_DOCK_AUX#
32
DPD_GPU_HPD
42
DPD_CA_DET
29
DP_CFG1
19
TMDSE_RP_P0
18
TMDSE_RP_N0
22
TMDSE_RP_P1
21
TMDSE_RP_N1
25
TMDSE_RP_P2
24
TMDSE_RP_N2
16
TMDSE_RP_CLK
15
TMDSE_RP_CLK#
48
HDMI_SCL_SINK
47
HDMI_SDA_SINK
17
HDMI_HPD_SINK
23
TMDS_RT
20
TMDS_PRE
26
GND
35
GND
43
GND
57
DPD_GPU_LANE_P0 <46>
DPD_GPU_LANE_N0 <46>
DPD_GPU_LANE_P1 <46>
DPD_GPU_LANE_N1 <46>
DPD_GPU_LANE_P2 <46>
DPD_GPU_LANE_N2 <46>
DPD_GPU_LANE_P3 <46>
DPD_GPU_LANE_N3 <46>
DPD_DOCK_AUX <45,46>
DPD_DOCK_AUX# <45,46>
DPD_GPU_HPD <46>
DPD_CA_DET <45,46>
ForHDMI
Choice Auto-Switching Mode.
ForDockingDPportD
Meet AMD HDMI 297 MHz EA setting.
EMI request.(for PT2)
1 2
R451
@
TMDSE_RP_CLK
TMDSE_RP_CLK#
B B
TMDSE_RP_P0
TMDSE_RP_N0
TMDSE_RP_P1
TMDSE_RP_N1
A A
TMDSE_RP_P2
TMDSE_RP_N2
DLW21SN900HQ2L_0805_4P~D
R452 0_0402_5%~D@
R453
@
DLW21SN900HQ2L_0805_4P~D
R454 0_0402_5%~D@
R455
@
DLW21SN900HQ2L_0805_4P~D
R456 0_0402_5%~D@
R459
@
DLW21SN900HQ2L_0805_4P~D
R458 0_0402_5%~D@
L19
4
4
1
1
1 2
1 2
L23
4
4
1
1
1 2
1 2
L24
4
4
1
1
1 2
1 2
L25
4
4
1
1
1 2
0_0402_5%~D
3
3
2
2
0_0402_5%~D
3
3
2
2
0_0402_5%~D
3
3
2
2
0_0402_5%~D
3
3
2
2
pop R451~R456,R458,R459 and non-pop L19,L23,L24,L25 for HDMI EA.(for PT1)
5
EMI request reserve C(3.3pF) for HDMI signals.
TMDSE_CON_CLK
TMDSE_CON_CLK#
TMDSE_CON_P0
TMDSE_CON_N0
TMDSE_CON_P1
TMDSE_CON_N1
TMDSE_CON_P2
TMDSE_CON_N2
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
@
@
C1333
C1334
1
1
2
2
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
@
@
C1335
C1336
1
1
2
2
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
@
@
C1337
C1338
1
1
2
2
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
@
@
C1339
C1340
1
1
2
2
4
+5V_RUN
+5V_RUN
0.5A_8VDC_SMD1812P200TF
F4
RB751V-40GTE-17_SOD323-2~D
21
@
12
R1169
0_0402_5%~D
@
D70
+5V_HDMI_DDC
HDMI_CEC
HDMI_HPD_SINK
1 2
R460 1.5K_0402_5%~D
1 2
R461 1.5K_0402_5%~D
+3.3V_RUN
1 2
R116510K_0402_5%~D
1 2
R1128100K_0402_5%~D
3
HDMI_HPD_SINK HDMI_HPD_SINK_R
HDMI_SDA_SINK
HDMI_SCL_SINK
HDMI 46@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 2
R1164 10K_0402_5%~D
Part Number Description
HDMI W/Logo:RO0000002HM
RO0000002HM
Meet AMD HDMI 297 MHz EA setting.
DP_CFG0=L:default,automaticEQenable&AUXinterceptionenable
=H:automaticEQdisable&AUXinterceptionenable
=M:automaticEQdisable&AUXinterceptiondisable,nopre‐emphasis,800mVppswing
21
3
D12
NC
BAT1000-7-F_SOT23-3~D
+5V_RUN_HDMI
0_1206_5%~D
21
@
R45
1 2
HDMI_SDA_SINK
HDMI_SCL_SINK
HDMI_CEC
TMDSE_CON_CLK#
TMDSE_CON_CLK
TMDSE_CON_N0
TMDSE_CON_P0
TMDSE_CON_N1
TMDSE_CON_P1
TMDSE_CON_N2
TMDSE_CON_P2
2
TMDS_RT
DP_CFG0
TMDS_DDCBUF
PEQ
DP_CFG1
MODE
TMDS_PRE
Meet AMD HDMI 297 MHz EA setting.
TMDS_RT
DP_CFG0
TMDS_DDCBUF
PEQ
DP_CFG1
MODE
TMDS_PRE
DPD_CA_DET
MODE=L:ControlSwitchingMode,HDMIIDdisable
=H:AutomaticSwitchingMode,HDMIIDdisable
=M:AutomaticSwitchingMode,HDMIIDenable
TMDS_PRE=L:nopre‐emphasis
=H:1.5dBpre‐emphasis
=M:3.0dBpre‐emphasis
TMDS_RT=L:Standardopendraindriver
=H:Opendraindriverwithterminationresistors
TMDS_DDCBUF=L:DDCpassthrough
=H:DDCactivebuffer
=M:DDCpassthroughwith40kohmpullupresistor
PEQ=L:default,LEQ,compensatechannellossupto12dB@HBR2
=H:HEQ,compensatechannellossupto15dB@HBR2
=M:LLEQ,compensatechannellossupto5dB@HBR2
DP_CFG1=L:default,autotestdisable&inputoffsetcancellationenable
=H:autotestenable&inputoffsetcancellationenable
=M:autotestdisable&inputoffsetcancellationdisable
HDMICONN
+VDISPLAY_VCC
10U_0805_10V4Z~D
0.1U_0402_10V7K~D
1
1
C338
C337
2
2
JHDMI1
CONN@
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
3
2
1
D1+
GND
D2-
GND
D2_shield
GND
D2+
GND
FOX_QJ1119L-BT11-7H
20
21
22
23
LinkCISOK
0722
+3.3V_RUN
12
R714.7K_0402_5%~D
12
R644.7K_0402_5%~D @
12
R684.7K_0402_5%~D
12
R704.7K_0402_5%~D @
12
R724.7K_0402_5%~D @
12
R584.7K_0402_5%~D
12
R654.7K_0402_5%~D
12
R574.7K_0402_5%~D @
12
R614.7K_0402_5%~D @
12
R664.7K_0402_5%~D @
12
R694.7K_0402_5%~D @
12
R734.7K_0402_5%~D @
12
R634.7K_0402_5%~D
12
R674.7K_0402_5%~D
12
R4911M_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
HDMI CONN
HDMI CONN
HDMI CONN
LA-7931P
LA-7931P
LA-7931P
34 70Monday, July 23, 2012
34 70Monday, July 23, 2012
34 70Monday, July 23, 2012
1
of
1.0
1.0
1.0
Page 35
+3.3V_RUN
D D
5
1 2
R501 10K_0402_5%~D
1 2
R502 10K_0402_5%~D
1 2
R503 100K_0402_5%~D
+3.3V_RUN
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
1
1
C392
2
2
DDR_XDP_WAN_SMBDAT<12,13,14,15,17,18,43>
DDR_XDP_WAN_SMBCLK<12,13,14,15,17,18,43>
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
HDD_FALL_INT
FreeFallSensor
C391
HDD_FALL_INT<20>
HDD_FALL_INT
FFS_INT2
U88
LNG3DM
1
VDD_IO
14
VDD
11
INT 1
9
INT 2
7
SDO/SA0
6
SDA / SDI / SDO
4
SCL/SPC
8
CS
LNG3DMTR_LGA16_3X3~D
4
3
2
1
HDD PWR
R500
+PWR_SRC_S
100K_0402_5%~D
12
R499
12
3
5
DMN66D0LDW-7_SOT363-6~D
61
4
Q300A
+5V_HDD
100K_0402_5%~D
12
+3.3V_RUN
100K_0402_5%~D
12
R513
10
RES
13
RES
15
RES
16
RES
5
GND
12
GND
2
NC
3
NC
FFS_INT2<21>
DMN66D0LDW-7_SOT363-6~D
61
Q29A
2
@
R506
FFS_INT2_Q
DMN66D0LDW-7_SOT363-6~D
3
Q29B
5
4
RUN_ON<47,48,52,56>
SIO_SLP_S3#<11,19,47,48,52,56>
1 2
R1621 0_0402_5%~D@
1 2
R1624 0_0402_5%~D@
100K_0402_5%~D
12
+3.3V_ALW2
100K_0402_5%~D
2
@
R505
+HDD_EN_5V
DMN66D0LDW-7_SOT363-6~D
1M_0402_5%~D@
12
Q300B
R2125
+5V_ALW
3
1
2
2
1
G
0.1U_0603_50V7K~D
4 5
C393
1
2
6
D
Q27
@
SI3456DDV-T1-GE3_TSOP6~D
S
+5V_HDD
10U_0805_10V6K~D
100K_0402_5%~D
12
R504
SHORT DEFAULT
C394
PJP33
@
112
JUMP_43X79
+5V_RUN
2
C C
HDD Redriver Select Component
X76(Main)
X7641231L01
PARADE(Main)
SA00004WF00
U26
R1173
R1201
V
V
R1175
R1202
B B
R1204
V
V
R1206
R2180
R2181
R2182
R2183
R2184
A A
X76(2nd)
X7641231L02
MAXIM(2nd)
SA00002EY1L
VV
V
V
V
V
V
HDDRepeater
U26
X76@
1 2
C24 1U_0402_6.3V6K~D@
12
PSATA_PTX_DRX_P0_C<17>
PSATA_PTX_DRX_N0_C<17>
PSATA_PRX_DTX_P0_C<17>
PSATA_PRX_DTX_N0_C<17>
C423 0.01U_0402_16V7K~D
12
C422 0.01U_0402_16V7K~D
12
C418 0.01U_0402_16V7K~D
12
C421 0.01U_0402_16V7K~D
PSATA_PTX_DRX_P0
PSATA_PTX_DRX_N0
PSATA_PRX_DTX_P0
PSATA_PRX_DTX_N0
7
SATA_EN
1
2
5
4
17
B_PRE1
19
A_PRE1
18
TEST
3
13
21
PS8520BTQFN20GTR2_TQFN20_4X4
EN
A_INp
A_INn
B_OUTp
B_OUTn
B_PRE1
A_PRE1
TEST
GND
GND
EPAD
VDD
VDD
REXT
A_PRE0
B_PRE0
A_OUTp
A_OUTn
B_INp
B_INn
NC
Main:SA00004WF00(PS8520)
2nd:SA00002EY1L(MAX4951)
12
C383 0.01U_0402_16V7K~D
12
C384 0.01U_0402_16V7K~D
12
C385 0.01U_0402_16V7K~D
12
C386 0.01U_0402_16V7K~D
+3.3V_RUN
HDD1_DET#<17>
0.1U_0402_25V6K~D
1
C406
2
+5V_HDD
+3.3V_RUN
1
2
PSATA_PTX_DRX_P0_RP
PSATA_PTX_DRX_N0_RP
PSATA_PRX_DTX_N0_RP
PSATA_PRX_DTX_P0_RP
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C403
C404
2
+5V_HDD
1000P_0402_50V7K~D
1
C395
2
+3.3V_RUN
6
16
10
MAXIM_PWR
20
REXT
9
A_PRE0
8
B_PRE0
15
PSATA_PTX_DRX_P0_RP
14
PSATA_PTX_DRX_N0_RP
11
PSATA_PRX_DTX_P0_RP
12
PSATA_PRX_DTX_N0_RP
ForHDDTemp.
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
HDD1_DET#
FFS_INT2_Q
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
1
1
C420
C419
2
2
JSATA1
CONN@
1
GND
2
RX+
3
RX-
4
GND
5
TX-
6
TX+
7
GND
8
3.3V
9
3.3V
10
3.3V
11
GND
12
GND
13
GND
14
5V
15
5V
16
5V
17
GND
18
GND1
Reserved
19
GND2
GND
20
12V
21
12V
22
12V
SUYIN_127043HB022M26GZL
LinkCISOK
23
24
ForSATAGen2,Gen3EAsetting
+3.3V_RUN
12
1 2
1 2
1 2
1 2
1 2
12
12
12
12
12
X761@
R11734.7K_0402_5%~D
X761@
R12014.7K_0402_5%~D
@
R11754.7K_0402_5%~D
X761@
R12024.7K_0402_5%~D
X761@
R12044.7K_0402_5%~D
@
R12064.99K_0402_1%~D
+3.3V_RUN
X762@
R21800_0402_5%~D
X762@
R21810_0402_5%~D
X762@
R21820_0402_5%~D
X762@
R21830_0402_5%~D
X762@
R21840_0402_5%~D
B_PRE1
A_PRE1
TEST
A_PRE0
B_PRE0
REXT
MAXIM_PWR
REXT
SATA_EN
B_PRE1
TEST
2nd source for SATA redriver
(AddX762@for2ndsourceoption.)
Pleace near HDD CONNPleace near HDD CONN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
HDD CONN
HDD CONN
HDD CONN
LA-7931P
LA-7931P
LA-7931P
1
35 70Monday, July 23, 2012
35 70Monday, July 23, 2012
35 70Monday, July 23, 2012
1.0
1.0
1.0
of
of
of
Page 36
5
D D
4
3
2
1
+5VMOD Source
+PWR_SRC_S
470K_0402_5%~D
+3.3V_ALW2
100K_0402_5%~D
12
R516
MODC_EN#
DMN66D0LDW-7_SOT363-6~D
61
C C
MODC_EN<48>
100K_0402_5%~D
12
R514
Q301A
2
12
R515
+MOD_EN
DMN66D0LDW-7_SOT363-6~D
3
Q301B
5
4
Solve300mW
PWRconsumption
issue.
+5V_ALW
6
2
1
D
G
3
0.022U_0603_50V7~D
4.7M_0402_5%~D
12
R2126
1
C416
2
Q30
SI3456DDV-T1-GE3_TSOP6~D
S
+5V_MOD +5V_RUN
4 5
10U_0805_10V6K~D
1
C417
2
PJP32
@
112
100K_0402_5%~D
12
JUMP_43X79
R517
2
+3.3V_ALW
1 2
R796 10K_0402_5%~D
B B
ZODD_WAKE#
+5V_MOD
1
2
ODD CONN
JODD1
12
SATA_ODD_PTX_DRX_P3_C<17>
SATA_ODD_PTX_DRX_N3_C<17>
SATA_ODD_PRX_DTX_N3_C<17>
SATA_ODD_PRX_DTX_P3_C<17>
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
1
C428
C429
2
C433 0.01U_0402_16V7K~D
C434 0.01U_0402_16V7K~D
C432 0.01U_0402_16V7K~D
C430 0.01U_0402_16V7K~D
DEVICE_DET#<49>
ZODD_WAKE#<48>
SATA_ODD_PTX_DRX_P3
12
SATA_ODD_PTX_DRX_N3
12
SATA_ODD_PRX_DTX_N3
12
SATA_ODD_PRX_DTX_P3
+5V_MOD
1 2
R792 0_0402_5%~D
10
11
12
13
LinkCISOK
0722
CONN@
1
GND
2
RX+
3
RX-
4
GND
5
TX-
6
TX+
7
GND
8
DP
9
+5V
+5V
MD
GND1
GND
GND2
GND
FOX_LN21131-D009-9H
14
15
PleacenearODDCONN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
ODD CONN
ODD CONN
ODD CONN
LA-7931P
LA-7931P
LA-7931P
36 70Monday, July 23, 2012
36 70Monday, July 23, 2012
36 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 37
5
+3.3V_LAN
1 2
1 2
33P_0402_50V8J~D
1
C470
2
R555
@
1 2
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
+3.3V_LAN
12
R549
10K_0402_5%~D
0_0402_5%~D
@
10K_0402_5%~D
XTALO_R
Y3
25MHZ_18PF_X3G025000DI1H-H~D
1
2
LAN_SMBDATA<18>
12
R557
R1144 0_0402_5%~D@
3
IN
OUT
4
GND
GND
PCIE_PRX_GLANTX_P7<18>
PCIE_PRX_GLANTX_N7<18>
PCIE_PTX_GLANRX_P7<18>
PCIE_PTX_GLANRX_N7<18>
LAN_SMBCLK<18>
1 2
R1187
@
C458 0.1U_0402_10V7K~D
C459 0.1U_0402_10V7K~D
C460 0.1U_0402_10V7K~D
C461 0.1U_0402_10V7K~D
1 2
R551 0_0402_5%~D@
1 2
R552 0_0402_5%~D@
1 2
1 2
1 2
LANCLK_REQ#<18>
PLTRST_LAN#<20>
CLK_PCIE_LAN<18>
CLK_PCIE_LAN#<18>
SMBus Device Address 0xC8
LAN_DISABLE#_R<48>
T142 PAD~D@
T143 PAD~D@
33P_0402_50V8J~D
C471
1
2
12
R545 10K_0402_5%~D@
R546 10K_0402_5%~D@
D D
PM_LANPHY_ENABLE<21>
C C
+3.3V_RUN
12
0_0402_5%~D
CLK_PCIE_LAN
CLK_PCIE_LAN#
12
PCIE_PRX_GLANTX_P7_C
12
PCIE_PRX_GLANTX_N7_C
PCIE_PTX_GLANRX_P7_C
PCIE_PTX_GLANRX_N7_C
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
XTALO
XTALI
LAN_TEST_EN
RES_BIAS
3.01K_0402_1%~D
1K_0402_1%~D
12
R561
R562
4
10K_0402_5%~D
R547
LANCLK_REQ#_R
LAN_SMBCLK_R
LAN_SMBDATA_R
U31
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTAL_OUT
10
XTAL_IN
30
TEST_EN
12
RBIAS
MDI
PCIE
RSVD_VCC3P3_1
RSVD_VCC3P3_2
SMBUS
VDD3P3_OUT
JTAG LED
82579_QFN48_6X6~D
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI_PLUS2
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
RSVD_NC
VDD3P3_IN
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD1P0_47
VDD1P0_46
VDD1P0_37
VDD1P0_43
VDD1P0_11
VDD1P0_40
VDD1P0_22
VDD1P0_16
VDD1P0_8
CTRL_1P0
VSS_EPAD
13
14
17
18
20
21
23
24
6
1
+RSVD_VCC3P3_1
2
+RSVD_VCC3P3_2
5
4
15
19
29
47
46
37
43
11
40
22
16
8
7
REGCTL_PNP10
49
LAN_TX0+
LAN_TX0-
LAN_TX1+
LAN_TX1-
LAN_TX2+
LAN_TX2-
LAN_TX3+
LAN_TX3-
3
+3.3V_LAN_OUT
+1.0V_LAN
R553 4.7K_0402_5%~D
R554 4.7K_0402_5%~D
12
12
1
C464
1U_0603_10V7K~D
2
2
REGCTL_PNP10
+3.3V_LAN
+1.0V_LAN POWER OPTIONS
Shared with PCH
1.05V SVR
STUFF: R548
NO STUFF: L29
+1.0V_LAN
Note:
+1.0V_LAN will work at 0.95V to 1.15V
*
STUFF: L29
NO STUFF: R548
L29
1 2
4.7UH_CBC2012T4R7M_20%~D
Idc max=330mA
Place R548, C462, C463 and L29 close to U31
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
C467
C466
2
2
Internal SRV
1
+1.0V_LAN
1 2
R548 0_0805_5%~D@
0.1U_0402_10V7K~D
10U_0603_6.3V6M~D
C463
C462
1
1
2
2
+3.3V_LAN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
C468
2
22U_0805_6.3V6M~D
1
1
C469
2
2
C1177
22U_0805_6.3V6M~D
1
2
+1.05V_M
C1178
Place C1178 close to pin5
Need to verify A3 silicon drive
power before removing C427
KDS crystal vender verify
driving level in A3
+3.3V_LAN
B B
LAN_TX3-
LAN_TX2-
LAN_TX1-
LAN_TX1+
DOCKED<34,48>
Layout Notice : Place bead as
close PI3L500 as possible
A A
FROM NIC DOCKED
1 2
L37 12NH_0603CS-120EJTS_5%~D
1 2
L36 12NH_0603CS-120EJTS_5%~D
1 2
L35 12NH_0603CS-120EJTS_5%~D
1 2
L34 12NH_0603CS-120EJTS_5%~D
1 2
L32 12NH_0603CS-120EJTS_5%~D
1 2
L33 12NH_0603CS-120EJTS_5%~D
1 2
L31 12NH_0603CS-120EJTS_5%~D
1 2
L30 12NH_0603CS-120EJTS_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C472
C473
2
2
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
1: TO DOCK
0: TO RJ45
0.1U_0402_25V6K~D
1
C474
2
LAN_TX3-R
LAN_TX3+RLAN_TX3+
LAN_TX2-R
LAN_TX2+RLAN_TX2+
LAN_TX1-R
LAN_TX1+R
LAN_TX0-RLAN_TX0-
LAN_TX0+RLAN_TX0+
39
U32
2
A0+
3
A0-
6
A1+
7
A1-
9
A2+
10
A2-
11
A3+
12
A3-
13
SEL
15
LEDA0
16
LEDA1
42
LEDA2
5
PD
43
PAD_GND
PI3L720ZHEX_TQFN42_9X3P5~D
CPN:SA00003SI3L
LAN ANALOG
SWITCH
38
37
34
33
29
28
25
24
17
18
41
36
35
32
31
27
26
23
22
19
20
40
SW_LAN_TX3SW_LAN_TX3+
SW_LAN_TX2SW_LAN_TX2+
SW_LAN_TX1SW_LAN_TX1+
SW_LAN_TX0SW_LAN_TX0+
LAN_ACTLED_YEL#
LED_100_ORG#
LED_10_GRN#
DOCK_LOM_TRD3DOCK_LOM_TRD3+
DOCK_LOM_TRD2DOCK_LOM_TRD2+
DOCK_LOM_TRD1DOCK_LOM_TRD1+
DOCK_LOM_TRD0DOCK_LOM_TRD0+
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
VDD1VDD4VDD8VDD14VDD21VDD30VDD
B0+
B0-
B1+
B1-
B2+
B2-
B3+
B3-
LEDB0
LEDB1
LEDB2
C0+
C0-
C1+
C1-
C2+
C2-
C3+
C3-
LEDC0
LEDC1
LEDC2
SW_LAN_TX3- <38>
SW_LAN_TX3+ <38>
SW_LAN_TX2- <38>
SW_LAN_TX2+ <38>
SW_LAN_TX1- <38>
SW_LAN_TX1+ <38>
SW_LAN_TX0- <38>
SW_LAN_TX0+ <38>
LAN_ACTLED_YEL# <38>
LED_100_ORG# <38>
LED_10_GRN# <38>
DOCK_LOM_TRD3- <46>
DOCK_LOM_TRD3+ <46>
DOCK_LOM_TRD2- <46>
DOCK_LOM_TRD2+ <46>
DOCK_LOM_TRD1- <46>
DOCK_LOM_TRD1+ <46>
DOCK_LOM_TRD0- <46>
DOCK_LOM_TRD0+ <46>
DOCK_LOM_ACTLED_YEL# <46>
DOCK_LOM_SPD100LED_ORG# <46>
DOCK_LOM_SPD10LED_GRN# <46>
TO
DOCK
+PWR_SRC_S
+3.3V_ALW
100K_0402_5%~D
12
+3.3V_ALW2
100K_0402_5%~D
12
R565
DMN66D0LDW-7_SOT363-6~D
61
Q297A
SIO_SLP_LAN#<19,48>
2
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
R564
DMN66D0LDW-7_SOT363-6~D
3
Q297B
5
4
74AHC1G08GW_SOT353-5~D
+3.3V_LAN
1
IN1
2
IN2
+ENAB_3VLAN
Q34
SI3456DDV-T1-GE3_TSOP6~D
D
6
2
1
G
1M_0402_5%~D
12
R1638
C478
0.1U_0402_10V7K~D
1 2
5
U15
P
4
O
G
3
S
45
3
2200P_0402_50V7K~D
1
2
WLAN_LAN_DISB# <48>
C477
1
2
+3.3V_LAN
10U_0603_6.3V6M~D
C475
1
2
0_1206_5%~D
0.1U_0402_10V7K~D
C476
+3.3V_M
R563
@
12
preventmaterialshortageforThaiflood.
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
LAN/LAN SW
LAN/LAN SW
LAN/LAN SW
LA-7931P
LA-7931P
LA-7931P
37 70Monday, July 23, 2012
37 70Monday, July 23, 2012
37 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 38
5
D D
4
3
2
1
change to SP050006P0L for LAN EA.
T156
SW_LAN_TX0+<37>
SW_LAN_TX0-<37>
+TRM_CT1
+TRM_CT2
SW_LAN_TX1+<37>
1
1
C C
B B
2
C479
0.47U_0603_10V7K~D
1
C484
2
0.47U_0603_10V7K~D
C480
2
0.47U_0603_10V7K~D
+TRM_CT3
+TRM_CT4
1
C486
2
0.47U_0603_10V7K~D
SW_LAN_TX1-<37>
SW_LAN_TX2+<37>
SW_LAN_TX2-<37>
SW_LAN_TX3+<37>
SW_LAN_TX3-<37>
SW_LAN_TX0+
SW_LAN_TX0-
SW_LAN_TX1+
SW_LAN_TX1-
SW_LAN_TX2+
SW_LAN_TX2-
SW_LAN_TX3+
SW_LAN_TX3-
1
TD1+
2
TD1-
3
TDCT1
4
TDCT2
5
TD2+
6
TD2-
7
TD3+
8
TD3-
9
TDCT3
10
TDCT4
11
TD4+
12
TD4-
350uH_IH-115-F~D
1:1
TX1+
TX1-
TXCT1
TXCT2
1:1
TX2+
TX2-
1:1
TX3+
TX3-
TXCT3
TXCT4
1:1
TX4+
TX4-
1 2
C485 1000P_1808_3KV7K~D
24
23
22
21
20
19
18
17
16
15
14
13
NB_LAN_TX0+
NB_LAN_TX0-
Z2805
Z2807
NB_LAN_TX1+
NB_LAN_TX1-
NB_LAN_TX2+
NB_LAN_TX2-
Z2806
Z2808
NB_LAN_TX3+
NB_LAN_TX3-
GND
CHASSIS
12
R571 75_0402_1%~D
12
12
R573 75_0402_1%~D
R572 75_0402_1%~D
GND_CHASSIS
+3.3V_LAN
0.1U_0402_10V7K~D
1U_0603_10V6K~D
1
C481
2
470P_0402_50V7K~D
1
1
C483
C1167
2
2
+3.3V_LAN:20mils
+3.3V_LAN
JLOM1
LAN_ACTLED_YEL#<37>
12
R574 75_0402_1%~D
LED_10_GRN#<37>
LED_100_ORG#<37>
1 2
R1171 150_0402_5%~D
NB_LAN_TX3-
NB_LAN_TX3+
NB_LAN_TX1-
NB_LAN_TX2-
NB_LAN_TX2+
NB_LAN_TX1+
NB_LAN_TX0-
NB_LAN_TX0+
1 2
R1170 150_0402_5%~D
1 2
R1167 150_0402_5%~D
Link CIS OK
13
Yellow LED-
12
Yellow LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
LED+
11
ORANGE_LED-
TYCO_2041333-1~D
CONN@
for ESD Hi-Pot fail.
15
SHLD2
14
SHLD1
0722
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
RJ45
RJ45
RJ45
LA-7931P
LA-7931P
LA-7931P
38 70Monday, July 23, 2012
38 70Monday, July 23, 2012
38 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 39
5
D D
C C
+5V_ALW
1
2
PJP31
@
2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
JUMP_43X79
1
C676
C675
2
112
+5V_ALW_ESATA
ESATA_USB_PWR_EN#<48>
U48
1
GND
2
IN
3
IN
4
EN1#
EN2#5FAULT#2
TPS2560DRCR-PG1.1_SON10_3X3~D
FAULT1#
OUT1
OUT2
T-PAD
10
9
8
7
ILIM
6
11
4
+5V_ESATA_PWR
USB_OC4# <20>
3
L51
USBP9+<20>
USBP9-<20>
12
R783
24.9K_0402_1%~D
USBP9_D-
USBP9_D+
4
4
1
1
DLW21SN900SQ2L_0805_4P~D
1 2
R736 0_0402_5%~D@
1 2
R742 0_0402_5%~D@
D73
2
3
PESD5V0U2BT_SOT23-3~D
3
3
2
1
USBP9_D+
2
USBP9_D-
ESATA_PTX_DRX_P4_C<17>
ESATA_PTX_DRX_N4_C<17>
ESATA_PRX_DTX_N4_C<17>
ESATA_PRX_DTX_P4_C<17>
2
+5V_ESATA_PWR
1 2
C671 0.01U_0402_16V7K~D
1 2
C672 0.01U_0402_16V7K~D
1 2
C673 0.01U_0402_16V7K~D
1 2
C674 0.01U_0402_16V7K~D
150U_B2_6.3V-M~D
1
C667
1
+
2
2
SATA_PTX_DRX_P4
SATA_PTX_DRX_N4
SATA_PRX_DTX_N4
SATA_PRX_DTX_P4
1
0.1U_0402_16V4Z~D
C668
JESA1
CONN@
USB
1
USB_V
2
USBP9_DUSBP9_D+
USB_D-
3
USB_D+
4
USB_GND
5
GND
6
A+
ESATA
7
A-
8
GND
GND
9
B-
GND
10
B+
GND
11
GND
GND
TAIWI_EU093-117CRL-TW
12
13
14
15
LinkCISOK
0722
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
ESATA
ESATA
ESATA
LA-7931P
LA-7931P
LA-7931P
39 70Monday, July 23, 2012
39 70Monday, July 23, 2012
39 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 40
5
4
3
2
1
ForUSB3redriver2ndsource
+USB3
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
USB3_TEST
USB3_B_EQ0
USB3_B_EQ1
USB3_B_DE0
USB3_B_DE1
USB3_A_EQ0
USB3_A_EQ1
USB3_A_DE0
USB3_A_DE1
R26 4.7K_0402_5%~D@
R18 4.7K_0402_5%~D
R27 4.7K_0402_5%~D@
R28 4.7K_0402_5%~D
D D
R30 4.7K_0402_5%~D
R24 4.7K_0402_5%~D
R22 4.7K_0402_5%~D@
Solvekingstonissue.
R23 4.7K_0402_5%~D
R25 4.7K_0402_5%~D
Vender suggest for EA.
1 2
R2196 0_0402_5%~DX761@
+1.5V_MEM
1 2
R2197 0_0402_5%~DX762@
ForUSB3redriver2ndsource
USB3TN1_RP
C C
USB3TP1_RP
USB3TP2_RP
HDD Redriver Select Component
X76(Main)
X7641231L03
PS8720
BA
SA00004UI00
U638
B B
A A
R2196VVV
R2197
EQ : Equalizer control and program,
3.3V tolerant. Internally pulled down at ~150K ohm
[A_EQ1, A_EQ0] ==
LL: program EQ for channel loss up to 4.5dB
LH: program EQ for channel loss up to 7.5dB
HL: program EQ for channel loss up to 9.5dB
HH: program EQ for channel loss up to 13dB
DE : Programmable output pre-emphasis level setting,
3.3V tolerant. Internally pulled down at ~150K ohm
[A_DE1, A_DE0] ==
LL: 3.5dB de-emphasis
LH: No de-emphasis
HL: 2.7dB de-emphasis
HH: 5dB de-emphasis
+USB3+3.3V_RUN
1 2
1 2
1 2
1 2
X76(2nd)
X7641231L04
PS8720
SA00005PO00
V
USB_PWR_SHR_EN#<48>
CB=0
CB=1
CB
0
1
1
5
TEST : Chip test mode enable.
3.3V tolerant. Internally pulled down at ~150K ohm.
L: Normal operation (default)
H: Test mode enable
for compliance test, this pin should be pulled to high.
Pin 13 : B_EQ0 / SDA_CTL Pin28 : A_DE1 / NC
Pin 14 : B_EQ1 / SCL_CTL Pin29 : A_DE0 / NC
Pin 15 : B_DE0 / I2C_ADDR0 Pin31 : A_EQ1 / NC
Pin 16 : B_DE1 / I2C_ADDR1 Pin32 : A_EQ0 / NC
ForUSB3redriver2ndsource ForUSB3redriver2ndsource
+USB3+USB3
0.01U_0402_16V7K~D
1
C453
2
U638
C4880.1U_0402_16V4Z~D
C4890.1U_0402_16V4Z~D
C4920.1U_0402_16V4Z~D
C4930.1U_0402_16V4Z~D
USB3TN1_RP_C
USB3TP1_RP_C
USB3RN1_RP
USB3RP1_RP
USB3TN2_RP_CUSB3TN2_RP
USB3TP2_RP_C
USB3RN2_RP
USB3RP2_RP
USB3_B_EQ0
USB3_B_EQ1
USB3_B_DE0
USB3_B_DE1
X76@
1
A1_OUTn
2
A1_OUTp
3
GND
4
B1_INn
5
B1_INp
6
I2C_EN
7
A2_OUTn
8
A2_OUTp
9
VDD
10
B2_INn
11
B2_INp
12
PD#
13
B_EQ0/SDA_CTL
14
B_EQ1/SCL_CTL
15
B_DE0
16
B_DE1
PS8720BTQFN32GTR-A0_TQFN32_3X6
EPAD
A_EQ0
A_EQ1
REXT
A_DE0
A_DE1
A1_INn
A1_INp
B1_OUTn
B1_OUTp
TEST
A2_INn
A2_INp
B2_OUTn
B2_OUTp
33
32
31
30
R2141 4.7K_0402_1%~D
29
28
27
26
25
VDD
24
23
22
21
20
19
GND
18
17
USB3_A_EQ0
USB3_A_EQ1
USB3_A_DE0
USB3_A_DE1
USB3TN1_C
USB3TP1_C
USB3_TEST
USB3RN2_C
USB3RP2_C
changeSILEGOtobemainsource
1 2
R1626 0_0402_5%~D@
autodetection charger identification active
charging downstream port with active USB2.0 data communication
mode with 1.5A support
SELCDP
USBP0-<20>
USBP0+<20>
+5V_ALW
X
DCP autodetect with mouse/keyboard wakeup
0
S0 charging with SDP only
S0 charging with CDP or SDP only (depending on external device)
1
SB#
0.1U_0402_25V6K~D
1
C715
2
U2
8
CB
7
TDM
6
TDP
5
VDD
SLG55584AVTR_TDFN8_2X2
Function
SELCDP
Thermal Pad
1
PWRSHARE_EN
CEN
2
USBP0_D-
DM
3
USBP0_D+
DP
4
9
4
0.1U_0402_16V4Z~D
1
C450
2
Vender suggest.
12
1 2
1 2
USB3RN1_C
USB3RP1_C
USB3TN2_C
USB3TP2_C
PD# : chip power down, active LOW, 3.3V tolerant,
internally pulled up at ~ 150K ohm.
SEL
+5V_ALW
1 2
10K_0402_5%~D
@
R1613
13
D
S
1 2
1 2
1 2
1 2
1 2
1 2
1 2
10K_0402_5%~D
R1614
2
SB#
G
Q338
@
SSM3K7002FU_SC70-3~D
Reserveforsamsungmobileissue.
C4520.1U_0402_16V4Z~D
C4540.1U_0402_16V4Z~D
C4900.1U_0402_16V4Z~D
C4910.1U_0402_16V4Z~D
USB3TN1 <20>
USB3TP1 <20>
C4870.1U_0402_16V4Z~D
C4650.1U_0402_16V4Z~D
C4560.1U_0402_16V4Z~D
C4570.1U_0402_16V4Z~D
USB3RN2 <20>
USB3RP2 <20>
USB3RN1 <20>
USB3RP1 <20>
USB3TN2 <20>
USB3TP2 <20>
RB751VM-40TE-17_SOD323-2~D
USBP0_R_D-
U45
1
GND
2
IN
3
IN
4
EN1#
EN2#5FAULT#2
USBP0_R_D+
USB3_RX1_N_D-
USB3_RX1_P_D+
USB3_TX1_N_D-
USB3_TX1_P_D+
+5V_USB_PWR2 +5V_USB_PWR1
10
FAULT1#
9
OUT1
8
OUT2
7
ILIM
6
11
T-PAD
USBP1_DUSBP1_D+
USB3_RX2_N_DUSB3_RX2_P_D+
USB3_TX2_N_DUSB3_TX2_P_D+
+5V_USB_PWR2
10U_0603_6.3V6M~D
150U_D2_6.3VY_R15M~D
1
C794
C323
1
+
2
2
For EMI request
L42
12
R2094
33K_0402_5%
21
For EMI request
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R752 0_0402_5%~D@
R753 0_0402_5%~D@
3
2
DLW21SN900HQ2L_0805_4P~D
R743 0_0402_5%~D@
R744 0_0402_5%~D@
L40
3
2
DLW21SN900HQ2L_0805_4P~D
R746 0_0402_5%~D@
R745 0_0402_5%~D@
EMIrequest.
L39
2
3
DLW21SN900SQ2L_0805_4P~D
R749 0_0402_5%~D@
R748 0_0402_5%~D@
+5V_ALW
100K_0402_5%~D
R816
2
G
L44
2
2
3
3
1 2
R750 0_0402_5%~D@
1 2
R751 0_0402_5%~D@
L43
3
3
2
2
1 2
1 2
EMIrequest.
L41
2
2
3
3
DLW21SN900SQ2L_0805_4P~D
1 2
R754 0_0402_5%~D@
1 2
R764 0_0402_5%~D@
USB3TP1_RP
USB3TN1_RP
USB3RP1_RP
USB3RN1_RP
USBP0_D+
USBP0_D-
+3.3V_ALW
PWRSHARE_EN
D99
USB_PWR_SHR_VBUS_EN<48>
USB3TN2_RP
USB3TP2_RP
USB3RP2_RP
USB3RN2_RP
USBP1+<20>
USBP1-<20>
3
2
1 2
1 2
3
2
1 2
1 2
2
3
1 2
1 2
1 2
PWRSHARE_EN#
13
D
S
4
USB3_TX1_P_D+
4
1
USB3_TX1_N_D-
1
4
USB3_RX1_P_D+
4
1
USB3_RX1_N_D-
1
1
USBP0_R_D+
1
4
USBP0_R_D-
4
ESD request change main source to SC300002F0L.
ForESDrequest
D14
USB3_TX1_P_D+
USB3_TX1_N_D-
USB3_RX1_P_D+
USB3_RX1_N_D-
USBP0_R_D-
USBP0_R_D+
1
2
4
5
3
8
IP4292CZ10-TBR_XSON10_2.5X1~D
PESD5V0U2BT_SOT23-3~D
10
USB3_TX1_P_D+
9
USB3_TX1_N_D-
7
USB3_RX1_P_D+
6
USB3_RX1_N_D-
D15
2
3
1
NEC_TOKIN shortage issue for the flood in Tailand and small size for ME space.
+5V_ALW
SSM3K7002FU_SC70-3~D
Q55
1
USB3_TX2_N_D-
1
4
USB3_TX2_P_D+
4
4
USB3_RX2_P_D+
4
1
USB3_RX2_N_D-
1
1
1
4
4
1
2
USBP1_D+
USBP1_D-
PJP30
@
2
10U_0805_10V4Z~D
112
0.1U_0402_16V4Z~D
JUMP_43X79
1
C669
C670
2
USB_SIDE_EN#<47,48>
+5V_ALW_FUSE
USB_SIDE_EN#
PWRSHARE_EN#
TPS2560DRCR-PG1.1_SON10_3X3~D
ESD request change main source to SC300002F0L.
ForESDrequest
D16
USB3_TX2_P_D+
USB3_TX2_N_D-
USB3_RX2_P_D+
USB3_RX2_N_D-
USBP1_D-
USBP1_D+
1
2
4
5
3
8
IP4292CZ10-TBR_XSON10_2.5X1~D
PESD5V0U2BT_SOT23-3~D
10
USB3_TX2_P_D+
9
USB3_TX2_N_D-
7
USB3_RX2_P_D+
6
USB3_RX2_N_D-
D17
2
3
1
NEC_TOKIN shortage issue for the flood in Tailand.
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Followconnlist0220A.
+5V_USB_PWR1
CONN@
JUSB1
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
7
GND
8
SSTX-
9
SSTX+
LOTES_AUSB0041-P001A
LinkCISOK
0305
+5V_USB_PWR1
150U_B2_6.3V-M~D
1
+
2
USB_OC0# <20>
Followconnlist0220A.
+5V_USB_PWR2
JUSB2
CONN@
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
7
GND
8
SSTX-
9
SSTX+
LOTES_AUSB0041-P001A
LinkCISOK
0305
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
USB3.0
USB3.0
USB3.0
LA-7931P
LA-7931P
LA-7931P
1
10
GND
11
GND
12
GND
13
GND
10U_0603_6.3V6M~D
C793
C324
1
2
12
R747
24.9K_0402_1%~D
10
GND
11
GND
12
GND
13
GND
1.0
1.0
40 70Monday, July 23, 2012
40 70Monday, July 23, 2012
40 70Monday, July 23, 2012
1.0
of
of
of
Page 41
5
4
3
2
1
D D
1 2
+3.3V_RUN_TPM
Solve+3.3V_RUNGiltchinS5
whenACpluggingin.
SP_TPM_LPC_EN<48>
C C
CLK_PCI_TPM_TCM
33_0402_5%~D
12
@
RE5
27P_0402_50V8J~D
@
1
CE3
2
PAD-OPEN1x1m
1 2
R873 0_0402_5%~D1@
+3.3V_RUN_TPM
1 2
R2186 10K_0402_5%~D@
1 2
R2185 0_0402_5%~D
D103 RB751S40T1_SOD523-2~D@
PJP77
CLK_PCI_TPM_TCM<18>
PCH_PLTRST#_EC<20,42,43,47,48,49>
+3.3V_RUN_TPM+3.3V_RUN
+3.3V_SB3V
21
LPC_LAD0<17,42,48,49>
LPC_LAD1<17,42,48,49>
LPC_LAD2<17,42,48,49>
LPC_LAD3<17,42,48,49>
LPC_LFRAME#<17,42,48,49>
IRQ_SERIRQ<17,48,49>
CLKRUN#<19,48,49>
+3.3V_SB3V
0.1U_0402_25V6K~D
1@
1
C48
2
SP_TPM_LPC_EN_R
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLK_PCI_TPM_TCM
LPC_LFRAME#
PCH_PLTRST#_EC
IRQ_SERIRQ
CLKRUN#
TCM_BA1
ATMEL TPM for E4
4700P_0402_25V7K~D
1@
1
C45
2
U39
1@
5
SB3V
28
LPCPD#
26
LAD0
23
LAD1
20
LAD2
17
LAD3
21
LCLK
22
LFRAME#
16
LRESET#
27
SERIRQ
15
CLKRUN#
1
ATEST_1
2
ATEST_2
3
ATEST_3
AT97SC3204-X2A14-AB_TSSOP28
VCC_0
VCC_1
VCC_2
V_BAT
NBO_13
NBO_14
GPIO6
TESTBI
TESTI
NC_7
GND_4
GND_11
GND_18
GND_25
10
19
24
12
13
14
NC_P
6
9
TCM_BA0
8
7
PP
4
11
18
25
2200P_0402_50V7K~D
1
2
1 2
C554 1U_0402_6.3V6K~D4@
1 2
R656 4.7K_0402_5%~D@
1
C550
2
+3.3V_RUN_TPM
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
C552
C551
2
+3.3V_RUN_TPM
0.1U_0402_25V6K~D
C553
1
2
JETWAY_CLK14M <18>
ChangeU39TPMsolutiontonewp/n:SA00004WQ10
0914: modify JUSH1 pin define for USH/B pin define change.
CONN@
JUSH1
22
GND
21
GND
20
20
USBP7-<20>
USBP7+<20>
USH_SMBCLK<49>
USH_SMBDAT<49>
BCM5882_ALERT#<48>
+3.3V_SUS
BT_COEX_STATUS2<50>
BT_PRI_STATUS<50>
+3.3V_RUN
+5V_RUN
PLTRST_USH#<20>
USH_PWR_STATE#<48>
CONTACTLESS_DET#<21>
USH_DET#<21>
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
ACES_51522-02001-001
Link CIS OK
0722
+5V_RUN +3.3V_SUS+3.3V_RUN
0.1U_0402_25V6K~D
C52
1
1
2
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C53
C56
1
2
Co-lay U37 and U39
LPC layout: Place TCM first and then end LPC with TPM.
China TCM: NationZ & Jetway co-lay
VDD_0
VDD_1
VDD_2
GND_4
NC_5
NC_12
NC_13
NC_1
NC_2
NC_6
NC_8
NC_P
+3.3V_RUN_TPM
10
19
24
11
18
25
4
5
12
13
1
2
6
8
14
+3.3V_SB3V
JETWAY_CLK14M
NC_P
JETWAY_CLK14MCLK_PCI_TPM_TCM
33_0402_5%~D
12
@
RE6
27P_0402_50V8J~D
1
@
CE4
2
B B
+3.3V_RUN_TPM
10K_0402_5%~D
12
12
@
R657
10K_0402_5%~D
12
12
R659
LOW:Power Down Mode
High:Working Mode
10K_0402_5%~D
@
R658
TCM_BA0
TCM_BA1
10K_0402_5%~D
R660
SP_TPM_LPC_EN_R
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
IRQ_SERIRQ
CLKRUN#
PP
TCM_BA1
TCM_BA0
U37
4@
28
LPCPD#
26
LAD0
23
LAD1
20
LAD2
17
LAD3
21
LCLK
22
LFRAME#
16
LRESET#
27
SERIRQ
15
CLKRUN#
7
PP
3
BA_1
9
BA_0
SSX44-B-D-T1_TSSOP28~D
GND_11
GND_18
GND_25
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
TPM/TCM
TPM/TCM
TPM/TCM
LA-7931P
LA-7931P
LA-7931P
41 70Monday, July 23, 2012
41 70Monday, July 23, 2012
41 70Monday, July 23, 2012
1
1.0
1.0
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of
Page 42
5
D D
COEX2_WLAN_ACTIVE<50>
COEX1_BT_ACTIVE<50>
PCH_CL_CLK1<18>
PCH_CL_DATA1<18>
PCH_CL_RST1#<18>
4
Mini WLAN/WIMAX/WiGig H=4
+3.3V_WLAN
PCIE_WAKE#<16,43,47,49>
1 2
R707 0_0402_5%~D@
1 2
R702 0_0402_5%~D@
MINI2CLK_REQ#<18>
CLK_PCIE_MINI2#<18>
CLK_PCIE_MINI2<18>
HOST_DEBUG_RX<49>
MSCLK<49>
PCIE_PRX_WLANTX_N2<18>
PCIE_PRX_WLANTX_P2<18>
PCIE_PTX_WLANRX_N2<18>
PCIE_PTX_WLANRX_P2<18>
1 2
R709 0_0402_5%~D@
COEX2_WLAN_ACTIVE_R
COEX1_BT_ACTIVE_R
C596 0.1U_0402_10V7K~D
1 2
PCIE_PTX_WLANRX_N2_C
1 2
PCIE_PTX_WLANRX_P2_C
C598 0.1U_0402_10V7K~D
PCH_CL_RST1#_R
BT_RADIO_DIS#_R
AddWiGigcardfunction
follow connecter list 1005: AAA-PCI-092-P01_A footprint
same as DAN08-52526-0100. next phase need change.
LCN_DAN08-52526-0100
JMINI4
CONN@
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
GND153GND2
3
+3.3V_WLAN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
+1.5V_RUN
MSDATA
WLAN_RADIO_DIS#_R
1 2
R703 0_0402_5%~D@
AddWiGigcardfunction
WiGi_RADIO_DIS#_R
USBP8USBP8+
WIMAX_LED#
WLAN_LED#
WiGi_BTLEDfunction.
WiGi_BT_LED#
1 2
R706 0_0402_5%~D@
HOST_DEBUG_TX <49>
PCH_PLTRST#_ECPCH_PLTRST#_EC_R
USBP8- <20>
USBP8+ <20>
EMIissue
WiGi_BT_LED# <51>
MSDATA
MSDATA <49>
2
R700 0_0402_5%~D@
WLAN_RADIO_DIS#_R
WiGi_RADIO_DIS#_R
BT_RADIO_DIS#_R
2 1
D31
RB751S40T1_SOD523-2~D
R2204 0_0402_5%~D@
2 1
D104
@
RB751S40T1_SOD523-2~D
R2205 0_0402_5%~D@
2 1
D105
@
RB751S40T1_SOD523-2~D
ReserveforWiGigcardfunction
1
12
WLAN_RADIO_DIS# <48>
12
WiGi_RADIO_DIS# <48>
12
BT_RADIO_DIS# <48,50>
LinkCISOK_0722
C C
+3.3V_WLAN
+3.3V_WLAN
100K_0402_5%~D
+1.5V_RUN
WIMAX_LED#
WLAN_LED#
100K_0402_5%~D
R705
R718
1 2
1 2
4
2
DMN66D0LDW-7_SOT363-6~D
61
Q124A
DMN66D0LDW-7_SOT363-6~D
Q124B
5
3
WIRELESS_LED# <43,48,51>
+3.3V_WLAN
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C601
2
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
@
1
1
1
C602
2
C605
C604
C603
2
2
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
2
1
C608
C607
C606
2
1
HOST_DEBUG_TX
COEX2_WLAN_ACTIVE
1 2
C595 4700P_0402_25V7K~D
1 2
C600 33P_0402_50V8J~D@
B B
PCIE_WAKE#<16,43,47,49>
COEX2_WLAN_ACTIVE<50>
PCIE_PRX_WPANTX_N5<18>
PCIE_PRX_WPANTX_P5<18>
PCIE_PTX_WPANRX_N5<18>
PCIE_PTX_WPANRX_P5<18>
+1.5V_RUN
+3.3V_PCIE_FLASH
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C625
A A
C635
2
2
1/2 Minicard Pink Pather
follow connecter list 1005: AAA-PCI-092-P01_A footprint
1
2
MINI3CLK_REQ#<18>
CLK_PCIE_MINI3#<18>
CLK_PCIE_MINI3<18>
0.1U_0402_25V6K~D
@
C639
PCIE_WAKE#
PCLK_80H<18>
0.047U_0402_16V4Z~D
1
2
same as DAN08-52526-0100. next phase need change.
R724 0_0402_5%~D@
MINI3CLK_REQ#
CLK_PCIE_MINI3#
CLK_PCIE_MINI3
PCH_PLTRST#_EC
PCLK_80H
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
C636 0.1U_0402_10V7K~D
1 2
PCIE_PTX_WPANRX_N5_C
1 2
PCIE_PTX_WPANRX_P5_C
C626 0.1U_0402_10V7K~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
1
2
C634
C624
C637
2
1
+3.3V_PCIE_FLASH +3.3V_PCIE_FLASH
1 2
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
2
1
C638
C633
1
2
JMINI3
CONN@
2
112
4
334
6
556
8
778
10
9910
12
111112
14
131314
16
151516
18
171718
20
191920
22
212122
24
232324
26
252526
28
272728
30
292930
32
313132
34
333334
36
353536
38
373738
40
393940
42
414142
44
434344
46
454546
48
474748
50
494950
52
515152
54
GND153GND2
LCN_DAN08-52526-0100
LinkCISOK
0722
LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
R730
@
1 2
+1.5V_RUN
LPC_LFRAME# <17,41,48,49>
LPC_LAD3 <17,41,48,49>
LPC_LAD2 <17,41,48,49>
LPC_LAD1 <17,41,48,49>
LPC_LAD0 <17,41,48,49>
0_0402_5%~D
PCH_PLTRST#_EC <20,41,43,47,48,49>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Mini Card-1/2
Mini Card-1/2
Mini Card-1/2
LA-7931P
LA-7931P
LA-7931P
1
42 70Monday, July 23, 2012
42 70Monday, July 23, 2012
42 70Monday, July 23, 2012
of
1.0
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Page 43
5
1 2
C1313 1U_0402_6.3V6K~D@
1 2
D D
SATA_NVRAM_PTX_DRX_P2_C<17>
SATA_NVRAM_PTX_DRX_N2_C<17>
SATA_NVRAM_PRX_DTX_P2_C<17>
SATA_NVRAM_PRX_DTX_N2_C<17>
1 2
1 2
1 2
C4450.01U_0402_16V7K~D
C4460.01U_0402_16V7K~D
C4470.01U_0402_16V7K~D
C4480.01U_0402_16V7K~D
HDD Redriver Select Component
X76(Main)
X7641231L01
PARADE(Main)
SA00004WF00
U637
R2135
R2136
C C
R2137
R2140
R2138
V
V
V
V
R2139
R2189
R2190
R2191
R2192
B B
A A
R2193
PIN
mSATA
23
TX+
25
TX-
31
RX-
33
RX+
Function
Port A to Port B
Port A to Port C
WWAN
PERn0
PERp0
PETn0
PETp0
SEL
L
H
5
X76(2nd)
X7641231L02
MAXIM(2nd)
SA00002EY1L
VV
V
V
V
V
V
SATA_NVR_PRX_DTX_P2
SATA_NVR_PRX_DTX_N2
SATA_NVR_PTX_DRX_N2
SATA_NVR_PTX_DRX_P2
PCIE_PRX_WANTX_N1<18>
PCIE_PRX_WANTX_P1<18>
PCIE_PTX_WANRX_N1<18>
PCIE_PTX_WANRX_P1<18>
MCARD_PCIE_SATA#<48>
C1314 0.01U_0402_16V7K~D
C1315 0.01U_0402_16V7K~D
C1316 0.01U_0402_16V7K~D
C1317 0.01U_0402_16V7K~D
MCARD_PCIE_SATA#
12
12
12
12
+3.3V_PCIE_NVM
100K_0402_5%~D
R740
2
4
M_SATA_EN
SATA_NVRAM_PTX_DRX_P2
SATA_NVRAM_PTX_DRX_N2
SATA_NVRAM_PRX_DTX_P2
SATA_NVRAM_PRX_DTX_N2
M_B_PRE1
M_A_PRE1
M_TEST
+1.5V_RUN
0.1U_0402_16V4Z~D
C435
1
2
12
C6400.1U_0402_10V7K~D
12
C6410.1U_0402_10V7K~D
12
MCARD_PCIE_SATA
DMN66D0LDW-7_SOT363-6 ~D
61
Q322A
4
SATARepeater
X76@
U637
7
EN
1
A_INp
2
A_INn
5
B_OUTp
4
B_OUTn
17
B_PRE1
19
A_PRE1
18
TEST
3
GND
13
GND
21
EPAD
PS8520BTQFN20GTR2_TQFN20_4X4
ForGen2,Gen3EAsetting
M_B_PRE1
M_A_PRE1
M_TEST
M_A_PRE0
M_B_PRE0
M_REXT
C436
+1.5V_RUN
100K_0402_5%~D
R785
5
12
3
4
1 2
1 2
1 2
1 2
1 2
PCIE_SATA#
DMN66D0LDW-7_SOT363 -6~D
Q322B
M_MAXIM_PWR
M_REXT
M_SATA_EN
M_B_PRE1
M_TEST
2nd source for SATA redriver
(AddX762@for2ndsourceoption.)
0.1U_0402_16V4Z~D
1
2
SATA_NVR_PRX_DTX_P2_C
SATA_NVR_PRX_DTX_N2_C
SATA_NVR_PTX_DRX_N2_C
SATA_NVR_PTX_DRX_P2_C
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1_C
PCIE_PTX_WANRX_P1_C
6
VDD
16
VDD
10
M_MAXIM_PWR
NC
20
REXT
9
A_PRE0
8
B_PRE0
15
A_OUTp
14
A_OUTn
11
B_INp
12
B_INn
+3.3V_RUN
12
X761@
R21354.7K_0402_5%~D
12
X761@
R21364.7K_0402_5%~D
12
@
R21374.7K_0402_5%~D
12
X761@
R21404.7K_0402_5%~D
12
X761@
R21384.7K_0402_5%~D
12
@
R21394.99K_0402_1%~D
+3.3V_RUN
X762@
R21890_0402_5%~D
X762@
R21900_0402_5%~D
X762@
R21910_0402_5%~D
X762@
R21920_0402_5%~D
X762@
R21930_0402_5%~D
U12
9
VDD
11
13
19
26
28
24
23
22
21
18
17
16
15
2
8
PI2DBS212ZHEX_TQFN28_5P5X3P5~D
VDD
VDD
VDD
VDD
VDD
B0+
B0B1+
B1C0+
C0C1+
C1-
NC
NC
GND
GND
GND
GND
GND
GND
GND
TPAD
A0+
A1+
SEL
+3.3V_RUN
M_REXT
M_A_PRE0
M_B_PRE0
SATA_NVR_PTX_DRX_P2
SATA_NVR_PTX_DRX_N2
SATA_NVR_PRX_DTX_P2
SATA_NVR_PRX_DTX_N2
4
PCIE_SATA_PRX_WANTX_N
5
PCIE_SATA_PRX_WANTX_P
A0-
6
PCIE_SATA_PTX_WANRX_N
7
PCIE_SATA_PTX_WANRX_P
A1-
3
PCIE_SATA#
1
10
12
14
20
25
27
29
3
Mini WWAN/GPS/LTE/mSATA
follow connecter list 1005: AAA-PCI-092-P01_A footprint
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1
1
C1312
C1311
2
2
PCIE_WAKE#<16,42,47,49>
MINI1CLK_REQ#<18>
CLK_PCIE_MINI1#<18>
CLK_PCIE_MINI1<18>
HW_GPS_DISABLE2#<48>
pullhighonECside.
same as DAN08-52526-0100. next phase need change.
PCIE_WAKE#
MINI1CLK_REQ#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
PCIE_SATA_PRX_WANTX_N
PCIE_SATA_PRX_WANTX_P
PCIE_SATA_PTX_WANRX_N
PCIE_SATA_PTX_WANRX_p
@
1 2
0_0402_5%~D
+3.3V_PCIE_NVM
R2105
2
1
3
5
7
LinkCISOK
0722
U40
@
UIM_RESET
UIM_DATA
33P_0402_50V8J~D
1
2
1
2
3
33P_0402_50V8J~D
@
@
1
SRV05-4.TCT_SOT23-6~D
C629
C628
2
+1.5V_RUN
33P_0402_50V8J~D
1
1
C620
2
2
0.047U_0402_16V4Z~D
C609
6
5
4
1
2
+3.3V_PCIE_NVM
0.047U_0402_16V4Z~D
1
C623
2
UIM_VPP
UIM_CLK
33P_0402_50V8J~D
@
C630
0.047U_0402_16V4Z~D
1
2
+SIM_PWR
33P_0402_50V8J~D
@
1
C631
2
1
C621
2
33P_0402_50V8J~D
1
C618
2
ForRFlayoutrequest
PWR
Rail
+3.3V
+3.3Vaux
+1.5V NA
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Voltage
Tolerance
+-9% 750
+-9%
+-5%
Primary Power
1000
330 5 (Not wake enable)
500
250
375
Aux Power
250 (Wake enable)
WWAN_SMBCLK
WWAN_SMBDAT
22U_0805_6.3VAM~D
C622
NormalNormalPeak
2
33P_0402_50V8J~D
1
C617
2
+3.3V_PCIE_NVM
JMINI2
CONN@
1
2
3
4
5
6
7
8
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
GND153GND2
LCN_DAN08-52526-0100
2.2K_0402_5%~D
2.2K_0402_5%~D
12
@
12
R1160
330U_V_6.3VM~D@
1
C615
+
2
+3.3V_PCIE_NVM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
LED_WWAN_OUT#
@
R1159
R1157 0_0402_5%~D@
R1158 0_0402_5%~D@
1
+1.5V_RUN
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
R713 0_0402_5%~D@
WWAN_SMBCLK
WWAN_SMBDAT
USBP5USBP5+
LED_WWAN_OUT#
1 2
1 2
+SIM_PWR
UIM_RESET UIM_VPP
1U_0402_6.3V6K~D
1
C616
2
+SIM_PWR
1 2
+3.3V_PCIE_NVM
100K_0402_5%~D
R719
G
2
1 2
S
Q77
SSM3K7002FU_SC70-3~D
DDR_XDP_WAN_SMBCLK <12,13,14,15,17,18,35>
DDR_XDP_WAN_SMBDAT <12,13,14,15,17,18,35>
WWAN_RADIO_DIS# <48>
PCH_PLTRST#_EC <20,41,42,47,48,49>
USBP5- <20>
USBP5+ <20>
13
D
WIRELESS_LED# <42,48,51>
SIM Card Push-Push
JSIM1
CONN@
1
VCC
2
RST
3
CLK
4
NC
SUYIN_254070FB008S205ZL
GND
GND
GND
5
6
VPP
7
I/O
8
NC
9
10
Link CIS OK
0722
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
Mini Card-2/2
Mini Card-2/2
Mini Card-2/2
LA-7931P
LA-7931P
LA-7931P
1
43 70Monday, July 23, 2012
43 70Monday, July 23, 2012
43 70Monday, July 23, 2012
of
UIM_DATAUIM_CLK
1.0
1.0
1.0
Page 44
5
D D
4
3
2
1
PowerControlforMinicard1
+PWR_SRC_S
+3.3V_ALW
100K_0402_5%~D
R720
+3.3V_ALW
100K_0402_5%~D
12
R715
AUX_EN_WOWL#
DMN66D0LDW-7_SOT363-6~D
61
Q310A
C C
AUX_EN_WOWL<48>
2
100K_0402_5%~D
12
R717
12
DMN66D0LDW-7_SOT363-6~D
3
Q310B
5
4
Q38
SI3456DDV-T1-GE3_TSOP6~D
D
6
2
1
+AUX_EN
1M_0402_5%~D
12
R1620
G
3
PowerControlforMinicard3
+PWR_SRC_S
+3.3V_ALW
100K_0402_5%~D
B B
MCARD_MISC_PWREN<48>
12
R735
MCARD_MISC_PWREN#
DMN66D0LDW-7_SOT363-6~D
61
Q312A
2
100K_0402_5%~D
12
R733
5
470K_0402_5%~D
12
3
4
+3.3V_ALW
R731
+MISC_PWREN
DMN66D0LDW-7_SOT363-6~D
Q312B
Q44
SI3456DDV-T1-GE3_TSOP6~D
D
6
2
1
G
3
4.7M_0402_5%~D
12
12
R1628
S
45
4700P_0402_25V7K~D
1
C632
2
S
45
220P_0402_50V8J~D
C651
Solve300mW
PWRconsumption
issue.
+3.3V_WLAN
12
R716
47K_0402_1%~D
forpowersavinginDCmodeS3
+3.3V_PCIE_FLASH
20K_0402_5%~D
12
R732
PowerControlforMinicard2
+PWR_SRC_S
+3.3V_ALW
100K_0402_5%~D
12
R738
NVRAM_PWR_EN#
DMN66D0LDW-7_SOT363-6~D
61
Q313A
NVRAM_PWR_EN<48>
2
100K_0402_5%~D
12
@
R739
5
470K_0402_5%~D
12
R737
DMN66D0LDW-7_SOT363-6~D
3
4
+3.3V_ALW
+NVRAM_PWREN
Q313B
Q46
SI3456DDV-T1-GE3_TSOP6~D
D
6
S
45
2
1
G
3
220P_0402_50V8J~D
4.7M_0402_5%~D
12
12
R1629
C652
Solve300mW
PWRconsumption
issue.
+3.3V_PCIE_NVM
20K_0402_5%~D
12
R734
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Mini Card PWR
Mini Card PWR
Mini Card PWR
LA-7931P
LA-7931P
LA-7931P
44 70Monday, July 23, 2012
44 70Monday, July 23, 2012
44 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
Page 45
5
4
3
2
1
+3.3V_RUN
+3.3V_RUN
5
12
61
2
12
R2146
2.2K_0402_5%~D
R2148 0_0402_5%~D@
DMN66D0LDW-7_SOT363-6~D
3
Q333B
4
DPC_DOCK_SW_AUX#
+3.3V_RUN
2
+3.3V_RUN
12
3
5
4
R2145
2.2K_0402_5%~D
1 2
DMN66D0LDW-7_SOT363-6~D
R2147 0_0402_5%~D@
Q333A
DPC_DOCK_SW_AUX
1 2
12
R2151
2.2K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
R2156 0_0402_5%~D@
61
Q335A
R2157
2.2K_0402_5%~D
1 2
R2155 0_0402_5%~D@
DMN66D0LDW-7_SOT363-6~D
Q335B
1 2
DPD_DOCK_AUX
+5V_RUN
DMN66D0LDW-7_SOT363-6~D
Q334A
+3.3V_ALW2
100K_0402_5%~D
12
R2152
61
5
Q336A
12
3
4
5
DMN66D0LDW-7_SOT363-6~D
R2149
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
Q334B
+5V_RUN
12
R2153
100K_0402_5%~D
DPD_DOCK_AUX_Q
3
Q336B
4
DMN66D0LDW-7_SOT363-6~D
+3.3V_ALW2
D D
DPC_CA_DET<33,46>
C C
B B
DPD_CA_DET<34,46>
DPC_CA_DET
DPD_CA_DET
100K_0402_5%~D
12
R2150
61
2
0.01U_0402_16V7K~D
1
C1331
2
2
0.01U_0402_16V7K~D
1
C1332
2
DOCK DPB(PORT2) DDC
DPC_DOCK_SW_AUX <33,46>
DPC_DOCK_SW_AUX# <33,46>
DOCK DPA(PORT1) DDC
DPD_DOCK_AUX <34,46>
DPD_DOCK_AUX_Q
+3.3V_RUN
2
5
12
DMN66D0LDW-7_SOT363-6~D
61
+3.3V_RUN
12
3
4
R2161
2.2K_0402_5%~D
1 2
R2162 0_0402_5%~D@
Q337A
MXM_DPC_AUX
R2164
2.2K_0402_5%~D
1 2
R2163 0_0402_5%~D@
DMN66D0LDW-7_SOT363-6~D
Q337B
MXM_DPC_AUX <16,34>
DPD_DOCK_AUX#
A A
5
4
DPD_DOCK_AUX# <34,46>
3
MXM_DPC_AUX#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
2
Date: Sheet
MXM_DPC_AUX# <16,34>
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DOCK DP DDC SW
DOCK DP DDC SW
DOCK DP DDC SW
LA-7931P
LA-7931P
LA-7931P
45 70Monday, July 23, 2012
45 70Monday, July 23, 2012
45 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
Page 46
5
DPD_GPU_LANE_P0<34>
DPD_GPU_LANE_N0<34>
DPD_GPU_LANE_P1<34>
DPD_GPU_LANE_N1<34>
DPD_GPU_LANE_P2<34>
DPD_GPU_LANE_N2<34>
DPD_GPU_LANE_P3<34>
DPD_GPU_LANE_N3<34>
D D
DOCK DPA(PORT1)
DPD_GPU_HPD<34> DPC_GPU_HPD <16>
Close to DOCK
Its for Enhance ESD on dock issue.
C C
B B
A A
DPD_GPU_HPD
100K_0402_5%~D
12
R757
DPD_GPU_LANE_P0
DPD_GPU_LANE_N0
DPD_GPU_LANE_P1
DPD_GPU_LANE_N1
DPD_GPU_LANE_P2
DPD_GPU_LANE_N2
DPD_GPU_LANE_P3
DPD_GPU_LANE_N3
DPD_DOCK_LANE_P0
DPD_DOCK_LANE_N0
DPD_DOCK_LANE_P1
DPD_DOCK_LANE_N1
DPD_DOCK_LANE_P2
DPD_DOCK_LANE_N2
DPD_DOCK_LANE_P3
DPD_DOCK_LANE_N3
C1281 0.1U_0402_10V7K~D
C1282 0.1U_0402_10V7K~D
C1277 0.1U_0402_10V7K~D
C1284 0.1U_0402_10V7K~D
C1286 0.1U_0402_10V7K~D
C1278 0.1U_0402_10V7K~D
C1279 0.1U_0402_10V7K~D
C1280 0.1U_0402_10V7K~D
DOCK_LOM_SPD10LED_GRN#<37>
1 2
R2160 33_0402_5%~D
1 2
R2165 33_0402_5%~D
1 2
R2166 33_0402_5%~D
1 2
R2167 33_0402_5%~D
1 2
R2168 33_0402_5%~D
1 2
R2169 33_0402_5%~D
1 2
R2170 33_0402_5%~D
1 2
R2171 33_0402_5%~D
DPD_DOCK_AUX<34,45>
DPD_DOCK_AUX#<34,45>
0.033U_0402_16V7K~D
1
C695
2
SLICE_BAT_PRES#<48,53,63> DOCK_DET# <48>
12
12
12
12
12
12
12
12
DPD_GPU_HPD
+NBDOCK_DC_IN_SS
BLUE_DOCK<32>
RED_DOCK<32>
GREEN_DOCK<32>
HSYNC_DOCK<32>
VSYNC_DOCK<32>
CLK_MSE<49>
DAT_MSE<49>
DAI_BCLK#<47>
DAI_LRCK#<47>
DAI_DI<47>
DAI_DO#<47>
DAI_12MHZ#<47>
D_LFRAME#<48>
D_CLKRUN#<48>
D_DLDRQ1#<48>
CLK_PCI_DOCK<20>
DOCK_SMB_CLK<49>
DOCK_SMB_DAT<49>
DOCK_SMB_ALERT#<48,53>
DOCK_PSID<53>
DOCK_PWR_BTN#<49>
4
D_LAD0<48>
D_LAD1<48>
D_LAD2<48>
D_LAD3<48>
DPD_DOCK_LANE_P0
DPD_DOCK_LANE_N0
DPD_DOCK_LANE_P1
DPD_DOCK_LANE_N1
DPD_DOCK_LANE_P2
DPD_DOCK_LANE_N2
DPD_DOCK_LANE_P3
DPD_DOCK_LANE_N3
DOCK_DET_1
DPD_CA_DET
DPD_DOCK_LANE_P0_R
DPD_DOCK_LANE_N0_R
DPD_DOCK_LANE_P1_R
DPD_DOCK_LANE_N1_R
DPD_DOCK_LANE_P2_R
DPD_DOCK_LANE_N2_R
DPD_DOCK_LANE_P3_R
DPD_DOCK_LANE_N3_R
DPD_DOCK_AUX
DPD_DOCK_AUX#
BLUE_DOCK
RED_DOCK
GREEN_DOCK
D_SERIRQ<48>
2011/09/01 change.
3
DPC_DOCK_LANE_P0_C
DPC_DOCK_LANE_N0_C
DPC_DOCK_LANE_P1_C
DPC_DOCK_LANE_N1_C
DPC_DOCK_LANE_P2_C
DPC_DOCK_LANE_N2_C
DPC_DOCK_LANE_P3_C
DPC_DOCK_LANE_N3_C
EMIrequestadd33ohmforDOCKDVIsignals.
JDOCK1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
146
147
148
153
154
155
156
157
158
CONN@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
GND1
PWR1
PWR1
PWR1
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
JAE_WD2F144WB5R400
LinkCISOK
PWR2
PWR2
PWR2
GND2
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
149
150
151
152
159
160
161
162
163
164
DPC_DOCK_LANE_P0_R
DPC_DOCK_LANE_N0_R
DPC_DOCK_LANE_P1_R
DPC_DOCK_LANE_N1_R
DPC_DOCK_LANE_P2_R
DPC_DOCK_LANE_N2_R
DPC_DOCK_LANE_P3_R
DPC_DOCK_LANE_N3_R
DPC_GPU_HPD
SATA_PRX_DKTX_P5
SATA_PRX_DKTX_N5
SATA_PTX_DKRX_P5
SATA_PTX_DKRX_N5
DOCK_DET_R#
PESD24VS2UT_SOT23-3~D
@
D33
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
ESD request reserve it.
0904
DPC_DOCK_SW_AUX
DPC_DOCK_SW_AUX#
C697 0.01U_0402_16V7K~D
C698 0.01U_0402_16V7K~D
C699 0.01U_0402_16V7K~D
C700 0.01U_0402_16V7K~D
0.1U_0603_50V7K~D
2
3
C702
1
1 2
C12750.1U_0402_10V7K~D
1 2
C12760.1U_0402_10V7K~D
1 2
C12830.1U_0402_10V7K~D
1 2
C12850.1U_0402_10V7K~D
1 2
C12870.1U_0402_10V7K~D
1 2
C12880.1U_0402_10V7K~D
1 2
C12890.1U_0402_10V7K~D
1 2
C12900.1U_0402_10V7K~D
DOCK_AC_OFF <48,63>
DOCK_LOM_SPD100LED_ORG# <37>
DPC_CA_DET <33,45>DPD_CA_DET<34,45>
1 2
R2172 33_0402_5%~D
1 2
R2173 33_0402_5%~D
1 2
R2174 33_0402_5%~D
1 2
R2175 33_0402_5%~D
1 2
R2176 33_0402_5%~D
1 2
R2177 33_0402_5%~D
1 2
R2178 33_0402_5%~D
1 2
R2179 33_0402_5%~D
DPC_DOCK_SW_AUX <33,45>
DPC_DOCK_SW_AUX# <33,45>
ACAV_DOCK_SRC# <63>
DAT_DDC2_DOCK <32>
CLK_DDC2_DOCK <32>
12
12
1 2
1 2
USBP4+ <20>
USBP4- <20>
USBP3+ <20>
USBP3- <20>
CLK_KBD <49>
DAT_KBD <49>
USB3RN4 <20>
USB3RP4 <20>
USB3TN4 <20>
USB3TP4 <20>
BREATH_LED# <48,51>
DOCK_LOM_ACTLED_YEL# <37>
DOCK_LOM_TRD0+ <37>
DOCK_LOM_TRD0- <37>
DOCK_LOM_TRD1+ <37>
DOCK_LOM_TRD1- <37>
+LOM_VCT
DOCK_LOM_TRD2+ <37>
DOCK_LOM_TRD2- <37>
DOCK_LOM_TRD3+ <37>
DOCK_LOM_TRD3- <37>
DOCK_DCIN_IS+ <62>
DOCK_DCIN_IS- <62>
DOCK_POR_RST# <49>
0.1U_0603_50V7K~D
C703
1
1
2
2
4.7U_0805_25V6K~D
@
1
CE6
2
EMI issue
RB751S40T1_SOD523-2~D
2011/09/01 change.
2
MXM_DPB_P0
MXM_DPB_N0
MXM_DPB_P1
MXM_DPB_N1
MXM_DPB_P2
MXM_DPB_N2
MXM_DPB_P3
MXM_DPB_N3
DPC_DOCK_LANE_P0_C
DPC_DOCK_LANE_N0_C
DPC_DOCK_LANE_P1_C
DPC_DOCK_LANE_N1_C
DPC_DOCK_LANE_P2_C
DPC_DOCK_LANE_N2_C
DPC_DOCK_LANE_P3_C
DPC_DOCK_LANE_N3_C
SATA_PRX_DKTX_P5_C <17>
SATA_PRX_DKTX_N5_C <17>
SATA_PTX_DKRX_P5_C <17>
SATA_PTX_DKRX_N5_C <17>
+LOM_VCT
1U_0402_6.3V6K~D
@
1
C701
2
D32
21
+DOCK_PWR_BAR
DAI_12MHZ# DAI_BCLK#
12
@
10_0402_1%~D
1
@
4.7P_0402_50V8C~D
2
reduce layout via.
RE11
CE8
1
MXM_DPB_P0 <16>
MXM_DPB_N0 <16>
MXM_DPB_P1 <16>
MXM_DPB_N1 <16>
MXM_DPB_P2 <16>
MXM_DPB_N2 <16>
MXM_DPB_P3 <16>
MXM_DPB_N3 <16>
0.033U_0402_16V7K~D
1
C696
Close to DOCK
Its for Enhance ESD on dock issue.
2
Add pull-down R for DPC_GPU_HPD.
DPC_GPU_HPD
DOCK_DET#
100K_0402_5%~D
12
R773
+3.3V_ALW
12
R75510K_0402_5%~D
Solvedockdetectionissue.
12
RE12
@
10_0402_1%~D
1
CE9
@
4.7P_0402_50V8C~D
2
DOCK DPB(PORT2)
CLK_PCI_DOCK
12
R756
33_0402_5%~D
1
C704
12P_0402_50V8J~D
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Docking
Docking
Docking
LA-7931P
LA-7931P
LA-7931P
46 70Monday, July 23, 2012
46 70Monday, July 23, 2012
46 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 47
5
D D
JIO1
CONN@
1
1
PCH_AZ_CODEC_BITCLK<17>
PCH_AZ_CODEC_SDIN0<17>
PCH_AZ_CODEC_SDOUT<17>
PCH_AZ_CODEC_SYNC<17>
PCH_AZ_CODEC_RST#<17>
DAI_12MHZ#<46>
DAI_DI<46>
DAI_DO#<46>
DAI_BCLK#<46>
DAI_LRCK#<46>
EN_I2S_NB_CODEC#<48>
DMIC_CLK<28>
DMIC0<28>
DOCK_HP_DET<48>
DOCK_MIC_DET<48>
AUD_HP_NB_SENSE<48>
AUD_NB_MUTE#<48>
BEEP<49>
SPKR<17>
USB_OC1#<20>
USB_OC3#<17,20>
USBP2-<20>
USB_SIDE_EN#<40,48>
USBP2+<20>
USBP6-<20>
USBP6+<20>
LID_CL#<48,51>
VOL_UP<49>
VOL_DOWN<49>
VOL_MUTE<49>
+5V_ALW
+5V_RUN
C C
B B
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
GND
FOX_QTS01401-A021-9H
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
RemovenetVOL_MUTE_LED.
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
+3.3V_ALW
+1.5V_RUN
+3.3V_SUS
PLTRST_MMI# <20>
PCIE_PRX_MMITX_P8 <18>
PCIE_PRX_MMITX_N8 <18>
PCIE_PTX_MMIRX_P8 <18>
PCIE_PTX_MMIRX_N8 <18>
CLK_PCIE_CARD# <18>
CLK_PCIE_CARD <18>
CARDCLK_REQ# <18>
SIO_SLP_S3# <11,19,35,48,52,56>
RUN_ON <35,48,52,56>
PCH_PLTRST#_EC <20,41,42,43,48,49>
USBP10- <20>
USBP10+ <20>
CARD_SMBCLK <49>
CARD_SMBDAT <49>
PCIE_WAKE# <16,42,43,49>
EXPCLK_REQ# <18>
CLK_PCIE_EXP# <18>
CLK_PCIE_EXP <18>
PCIE_PRX_EXPTX_N3 <18>
PCIE_PRX_EXPTX_P3 <18>
PCIE_PTX_EXPRX_N3 <18>
PCIE_PTX_EXPRX_P3 <18>
SATA_SIDE_LED <51>
NUM_LED <51>
BT_LED <51>
WLAN_LED <51>
SATA_LED <51>
BREATH_LED#_Q <51>
BAT2_LED# <48>
BAT1_LED# <48>
MASK_BASE_LEDS# <51>
DAT_TP_SIO <49>
CLK_TP_SIO <49>
PS2_DAT_TS <50>
PS2_CLK_TS <50>
+3.3V_RUN
3
2
1
WireLessON/OFFCONN
JWL1
CONN@
1
1
2
2
WIRELESS_ON#/OFF<48>
3
3
4
GND
5
GND
ACES_50228-0037N-001
LinkCISOK_0722
PowerBottomCONN
JPB1
POWER_SW#_MB
PESD24VS2UT_SOT23-3~D
2
3
@
D97
1
+5V_ALW
BREATH_WHITE_LED<51>
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_50228-0067N-001
CONN@
LinkCISOK
0722
ESD request reserve it.
LinkCISOK
0722
+5V_ALW +3.3V_RUN +3.3V_ALW +1.5V_RUN +3.3V_SUS+5V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
A A
5
2
C763
C721
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
C722
C723
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
C724
C725
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PowerSwitchfordebug
POWER_SW#_MB<49>
100P_0402_50V8J~D
@
1
C759
2
2
112
PWRSW1
@
@SHORT PADS~D
PlaceonBottom
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
I/O board
I/O board
I/O board
LA-7931P
LA-7931P
LA-7931P
1
1.0
1.0
47 70Monday, July 23, 2012
47 70Monday, July 23, 2012
47 70Monday, July 23, 2012
1.0
of
Page 48
5
+3.3V_ALW_U46
1 2
R798 100K_0402_5%~D
1 2
R761 100K_0402_5%~D
1 2
R765 100K_0402_5%~D
1 2
R760 100K_0402_5%~D
1 2
R774 100K_0402_5%~D
1 2
R776 100K_0402_5%~D
D D
C C
B B
1 2
R768 10K_0402_5%~D
1 2
R769 100K_0402_5%~D
1 2
R778 100K_0402_5%~D
1 2
R763 10K_0402_5%~D
1 2
R2158 100K_0402_5%~D
1 2
R2202 100K_0402_5%~D@
1 2
R2203 100K_0402_5%~D@
+3.3V_RUN
1 2
R457 100K_0402_5%~D
1 2
R766 100K_0402_5%~D@
1 2
R772 10K_0402_5%~D@
1 2
R787 100K_0402_5%~D
1 2
R788 100K_0402_5%~D
+3.3V_ALW
12
12
+3.3V_ALW
100K_0402_5%~D
12
100K_0402_5%~D
12
100K_0402_5%~D
HW_GPS_DISABLE2#
PROCHOT_GATE
CPU_DETECT#
SLICE_BAT_PRES#
WWAN_RADIO_DIS#
USB_PWR_SHR_EN#
USB_SIDE_EN#
ESATA_USB_PWR_EN#
USB_PWR_SHR_VBUS_EN
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WiGi_RADIO_DIS#
ReserveforWiGigfunction.
MCARD_PCIE_SATA#
WIRELESS_ON#/OFF
SP_TPM_LPC_EN
GPU_PWR_LEVEL
DGPU_ALERT#
R2097
eDP_DET#
R2098
6@
1K_0402_5%~D
@
R800
VGA_ID
R803
ReserveforWiGigfunction.
CRT_SWITCH<32>
DDR_1.5V_CNTRL0<55>
MCARD_MISC_PWREN<44>
PROCHOT_GATE<62>
DOCK_SMB_ALERT#<46,53>
GPU_PWR_LEVEL<16>
USB_SIDE_EN#<40,47>
EN_I2S_NB_CODEC#<47>
USH_PWR_STATE#<41>
EN_DOCK_PWR_BAR<63>
PANEL_BKEN_EC<28>
ENVDD_PCH<19,28>
LCD_TST<28>
PSID_DISABLE#<53>
PBAT_PRES#<53>
DOCKED<34,37>
DOCK_DET#<46>
AUD_NB_MUTE#<47>
LCD_VCC_TEST_EN<28>
CCD_OFF<28>
AUD_HP_NB_SENSE<47>
ESATA_USB_PWR_EN#<39>
NVRAM_PWR_EN<44>
SLICE_BAT_ON<63>
SLICE_BAT_PRES#<46,53,63>
1.5V_RUN_PWRGD<56>
DDR_1.5V_CNTRL1<55>
ReserveforWiGigfunction.
WiGi_RADIO_DIS#<42>
USB_PWR_SHR_EN#<40>
NUM_LED#<51>
MCARD_PCIE_SATA#<43>
CPU_DETECT#<7>
DGPU_PWR_EN<16>
DGPU_ALERT#<16>
MXM_DP_HDMI_HPD<16>
ZODD_WAKE#<36>
BCM5882_ALERT#<41>
SUSACK#<19>
EDID_SELECT#<32>
DGPU_PWROK<16,21>
RUN_GFX_ON<18,52>
SLP_ME_CSW_DEV#<17,21>
LAN_DISABLE#_R<37>
SYS_LED_MASK#<51>
DYN_TURB_SYS_PWR_ALRT#<26>
SIO_EXT_WAKE#<21>
WIRELESS_LED#<42,43,51>
USB_PWR_SHR_VBUS_EN<40>
WLAN_RADIO_DIS#<42>
WIRELESS_ON#/OFF<47>
BT_RADIO_DIS#<42,50>
WWAN_RADIO_DIS#<43>
SYS_PWROK<7,19>
DGPU_SELECT#<27,28,32>
CPU_VTT_ON<58>
PCH_DPWROK<19>
R797 0_0402_5%~D@
VGA_ID0
Discrete
0
UMA 1
ME_FWPPCHhasinternal20KPD.
A A
5
(suspendpowerrail)
ME_FWP
1K_0402_1%~D
12
@
R793
4.7P_0402_50V8C~D
4
CRT_SWITCH
DDR_1.5V_CNTRL0
MCARD_MISC_PWREN
PROCHOT_GATE
LID_CL_SIO#
DOCK_SMB_ALERT#
USB_SIDE_EN#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
ENVDD_PCH
LCD_TST
PSID_DISABLE#
PBAT_PRES#
DOCKED
DOCK_DET#
AUD_NB_MUTE#
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#
NVRAM_PWR_EN
SLICE_BAT_ON
SLICE_BAT_PRES#
1.5V_RUN_PWRGD
DDR_1.5V_CNTRL1
WiGi_RADIO_DIS#
USB_PWR_SHR_EN#
NUM_LED#
MCARD_PCIE_SATA#
CPU_DETECT#
DGPU_PWR_EN
DGPU_ALERT#
MXM_DP_HDMI_HPD
ZODD_WAKE#
BCM5882_ALERT#
SUSACK#
EDID_SELECT#
DGPU_PWROK
VGA_ID
RUN_GFX_ON
SLP_ME_CSW_DEV#
LAN_DISABLE#_R
AUX_MODE_EN
SYS_LED_MASK#
DYN_TURB_SYS_PWR_ALRT#
1 2
WIRELESS_LED#
USB_PWR_SHR_VBUS_EN
WLAN_RADIO_DIS#
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
SYS_PWROK
DGPU_SELECT#
eDP_DET#
CPU_VTT_ON
1 2
R802 0_0402_5%~D@
CLK_SIO_14M
12
R794
@
10_0402_1%~D
1
C712
@
4
4.7P_0402_50V8C~D
2
U46
B52
GPIOA0
A49
GPIOA1
B53
GPIOA2
A50
GPIOA3
B54
GPIOA4
A51
GPIOA5
B55
GPIOA6
A52
GPIOA7
A33
GPIOB0
B36
GPIOB1
A34
GPOC2
B37
GPOC3
A35
GPOC4
B38
GPOC5
A36
GPOC6/TACH4
A37
GPIOC7
B40
GPIOD0
A38
GPIOC1
B41
GPIOC0
A39
GPIOB7
B42
GPIOB6
A40
GPIOB5
B43
GPIOB4
A41
GPIOB3
B44
GPIOB2
B32
GPIOD1
A31
GPIOD2
B33
GPIOD3
B15
GPIOD4
A15
GPIOD5
B16
GPIOD6
A16
GPIOD7
A1
GPIOE0/RXD
B2
GPIOE1/TXD
A2
GPIOE2/RTS#
B3
GPIOE3/DSR#
A3
GPIOE4/CTS#
B45
GPIOE5/DTR#
A42
GPIOE6/RI#
B4
GPIOE7/DCD#
A59
GPIOF0
B62
GPIOF1
A58
GPIOF2
B61
GPIOF3/TACH8
A56
GPIOF4/TACH7
B59
GPIOF5
A55
GPIOF6
B58
GPIOF7
B47
GPIOG0/TACH5
A45
GPIOG1
B48
GPIOG2
A46
GPIOG3
B49
GPIOG4
A47
GPIOG5
B50
GPIOG6
A48
GPIOG7/TACH6
B13
GPIOH0
A13
GPIOH1
A53
SYSOPT1/GPIOH2
B57
SYSOPT0/GPIOH3
B14
GPIOH4
A14
GPIOH5
B17
GPIOH6
B18
GPIOH7
CLK_PCI_5048
R795
@
10_0402_1%~D
C713
@
3
+3.3V_ALW_U46
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_10V7K~D
C710
1
2
B5
A17
B30
A43
A54
VCC1
VCC1
VCC1
VCC1
VCC1
14.318MHZ/GPIOM0
ECE5048-LZY_DQFN132_11X11~D
+3.3V_ALW
100K_0402_5%~D
12
12
LID_CL_SIO#
1
2
R805
R807 10_0402_1%~D
0.047U_0402_16V4Z~D
C716
1
2
C709
1
2
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
BC_INT#
BC_DAT
BC_CLK
PWRGD
OUT65
TEST_PIN
CAP_LDO
VSS
EP
DB Version 0.4
12
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
0.1U_0402_10V7K~D
C708
C717
1
1
1
2
2
2
B63
SIO_SLP_A#
A60
0.75V_DDR_VTT_ON
A61
SIO_SLP_S4#
B65
SIO_SLP_S3#
A62
IMVP_PWRGD
1 2
B66
R771 0_0402_5%~D@
A63
DOCK_AC_OFF_EC
B67
AUX_EN_WOWL
A64
WLAN_LAN_DISB#
A5
SIO_SLP_LAN#
B6
SIO_SLP_SUS#
A6
GPIO_PSID_SELECT
B7
MODC_EN
A7
DOCK_HP_DET
B8
DOCK_MIC_DET
A8
ME_FWP
B9
MASK_SATA_LED#
B10
1.8V_RUN_PWRGD
A10
LED_SATA_DIAG_OUT#
B11
TEMP_ALERT#_R
A11
RUN_ON
B12
A12
B60
SUS_ON
A57
B64
BAT1_LED#
B68
A9
BAT2_LED#
B1
A18
USH_PWR_ON
A44
B34
HW_GPS_DISABLE2#
B39
BREATH_LED#
B51
A27
LPC_LAD0
A26
LPC_LAD1
B26
LPC_LAD2
B25
LPC_LAD3
A21
LPC_LFRAME#
B22
PCH_PLTRST#_EC
A28
CLK_PCI_5048
B20
CLKRUN#
A23
A22
LPC_LDRQ1#
B21
IRQ_SERIRQ
A32
CLK_SIO_14M
B35
EC_32KHZ_ECE5048
B29
D_LAD0
B28
D_LAD1
A25
D_LAD2
A24
D_LAD3
B23
D_LFRAME#
A19
D_CLKRUN#
B24
D_DLDRQ1#
A20
D_SERIRQ
A29
BC_INT#_ECE5048
B31
BC_DAT_ECE5048
A30
BC_CLK_ECE5048
A4
RUNPWROK
B56
SP_TPM_LPC_EN
B19
B46
B27
C1
1 2
R804 1K_0402_1%~D
+CAP_LDO
+CAP_LDOtracewidth20mils
LID_CL# <47,51>
PAD-OPEN1x1m
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C719
C718
1
2
SP_TPM_LPC_EN <41>
4.7U_0603_6.3V6K~D
1
C714
2
+3.3V_ALW
PJP29
12
SIO_SLP_A# <19,52,57>
0.75V_DDR_VTT_ON <55>
SIO_SLP_S4# <19,52,55>
SIO_SLP_S3# <11,19,35,47,52,56>
IMVP_PWRGD <60>
IMVP_VR_ON <60>
DOCK_AC_OFF_EC <63>
AUX_EN_WOWL <44>
WLAN_LAN_DISB# <37>
SIO_SLP_LAN# <19,37>
SIO_SLP_SUS# <19>
GPIO_PSID_SELECT <53>
MODC_EN <36>
DOCK_HP_DET <47>
DOCK_MIC_DET <47>
ME_FWP <17>
MASK_SATA_LED# <51>
1.8V_RUN_PWRGD <56>
LED_SATA_DIAG_OUT# <51>
RUN_ON <35,47,52,56>
LED_WLAN_WWAN_DIAG_OUT# <51>
SPI_WP#_SEL <17>
SUS_ON <52>
BAT1_LED# <47>
BAT2_LED# <47>
T117PAD~D @
HW_GPS_DISABLE2# <43>
BREATH_LED# <46,51>
LPC_LAD0 <17,41,42,49>
LPC_LAD1 <17,41,42,49>
LPC_LAD2 <17,41,42,49>
LPC_LAD3 <17,41,42,49>
LPC_LFRAME# <17,41,42,49>
PCH_PLTRST#_EC <20,41,42,43,47,49>
CLK_PCI_5048 <20>
CLKRUN# <19,41,49>
LPC_LDRQ1# <17>
IRQ_SERIRQ <17,41,49>
CLK_SIO_14M <18>
EC_32KHZ_ECE5048 <49>
D_LAD0 <46>
D_LAD1 <46>
D_LAD2 <46>
D_LAD3 <46>
D_LFRAME# <46>
D_CLKRUN# <46>
D_DLDRQ1# <46>
D_SERIRQ <46>
BC_INT#_ECE5048 <49>
BC_DAT_ECE5048 <49>
BC_CLK_ECE5048 <49>
RUNPWROK <7,49>
ACAV_IN_NB<49,62,63>
2
R741
@
1 2
trace width 20 mils
trace width 20 mils
DOCK_AC_OFF_EC
2
0_0402_5%~D
+3.3V_ALW
5
1
B
2
A
3
TEMP_ALERT# <17,21>
C711
@
1 2
0.1U_0402_25V6K~D
P
4
O
D34
G
RB751S40T1_SOD523-2~D
U47
@
TC7SH08FU_SSOP5~D
DELL CONFIDENTIAL/PROPRIETARY
1
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
RUN_ON
CPU_VTT_ON
0.75V_DDR_VTT_ON
SLICE_BAT_ON
SUS_ONDOCK_SMB_ALERT#
LCD_TST
SYS_LED_MASK#
DGPU_PWR_EN
AUX_MODE_EN
MXM_DP_HDMI_HPD
USH_PWR_STATE#
2 1
@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
33K_0402_5%~D
@
R770
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+3.3V_RUN
R777100K_0402_5%~D
R780100K_0402_5%~D
R782100K_0402_5%~D
R786100K_0402_5%~D
R789100K_0402_5%~D
R790100K_0402_5%~D
R791100K_0402_5%~D
R888100K_0402_5%~D
12
R767100K_0402_5%~D
12
R77510K_0402_5%~D
12
R1582100K_0402_5%~D
12
R13100K_0402_5%~D
12
R2106100K_0402_5%~D
12
R21071M_0402_5%~D
DOCK_AC_OFF <46,63>
SIO
SIO
SIO
LA-7931P
LA-7931P
LA-7931P
1
48 70Monday, July 23, 2012
48 70Monday, July 23, 2012
48 70Monday, July 23, 2012
of
of
1.0
1.0
1.0
Page 49
5
+3.3V_ALW
C720
1 2
0.1U_0402_25V6K~D
5
U50
1
1.05V_VTTPWRGD<58,59>
VCCSAPWROK<59>
74AHC1G08GW_SOT353-5~D
D D
+5V_RUN
R845 4.7K_0402_5%~D
R846 4.7K_0402_5%~D
R851 4.7K_0402_5%~D
R852 4.7K_0402_5%~D
+RTC_CELL
R1156 100K_0402_5%~D
1 2
R870 100K_0402_5%~D
+3.3V_RUN
R1177 100K_0402_5%~D@
R1197 100K_0402_5%~D@
R1118 100K_0402_5%~D@
R829 4.7K_0402_5%~D
R822 4.7K_0402_5%~D
+3.3V_SUS
1 2
R589 2.2K_0402_5%~D
1 2
R585 2.2K_0402_5%~D
C C
JTAG_RST#citcuit
closetoU51.B57
1
JTAG1
@SHORT PADS~D
1
CONN@
2
2
32KHzClock
R1068 0_0402_5%~D@
MEC_XTAL2_R
B B
A A
39P_0402_50V8J~D
C743
PlacecloselypinA29
CLK_PCI_MEC
10_0402_1%~D
12
@
R885
4.7P_0402_50V8C~D
@
1
C747
2
49.9_0402_1%~D
11
12
TYCO_1-2041070-0~D
32.768KHZ_12.5PF_Q13FC1350000~D
2
1
R864
1 2
CONN@
JDEG1
1
2
3
4
5
6
G1
7
G2
8
9
10
P
IN1
O
2
IN2
G
3
preventmaterialshortageforThaiflood.
12
12
12
12
12
LAT_ON_SW#
12
12
12
12
GPU_SMBDAT
12
GPU_SMBCLK
USH_SMBCLK
USH_SMBDAT
+3.3V_ALW
0.1U_0402_25V6K~D
1
C735
2
1 2
Y6
12
+3.3V_ALW
10K_0402_5%~D
12
12
R858
+PWR
1
2
3
4
5
6
MSCLK
7
MSDATA
8
9
HOST_DEB_RX
10
4
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
VCI_IN1#
VOL_MUTE
VOL_DOWN
VOL_UP
10K_0402_5%~D
12
R824
JTAG_RST#
100_0402_1%~D
12
@
R836
MEC_XTAL2
MEC_XTAL1
39P_0402_50V8J~D
1
C741
2
PlacecloselypinB22
DOCK_POR_RST#
0.1U_0402_25V6K~D
1
2
10K_0402_5%~D
10K_0402_5%~D
12
12
R860
R859
1.05V_0.8V_PWROK <17,60>
Crystal EA.
C736
10K_0402_5%~D
R861
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
1 2
1 2
R853 0_0402_5%~D@
R855 0_0402_5%~D@
+3.3V_ALW
10K_0402_5%~D
12
LinkCISOK
0722
5
4
+RTC_CELL
100K_0402_5%~D
12
R810
1U_0402_6.3V6K~D
POWER_SW_IN#<25> DOCK_PWR_SW#<25>
+RTC_CELL
BEEP<47>
R867 0_0402_5%~D@
1 2
RESET_OUT#
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
DOCK_POR_RST#
PCH_ALW_ON
BIA_PWM_EC
BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
BC_CLK_EMC4002
BC_DAT_EMC4002
BC_INT#_EMC4002
PCH_PCIE_WAKE#
PCIE_WAKE#
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
BEEP
SIO_SLP_S5#
ACAV_IN_NB
SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
MEC_XTAL1
MEC_XTAL2
2
G
R875 C744
240K 4700p
130K 4700p
62K
33K
8.2K
*
4.3K
2K
1K
SML1_SMBDATA<18>
SML1_SMBCLK<18>
CLK_TP_SIO<47>
DAT_TP_SIO<47>
CLK_KBD<46>
DAT_KBD<46>
CLK_MSE<46>
DAT_MSE<46>
PBAT_SMBDAT<53>
PBAT_SMBCLK<53>
DOCK_POR_RST#<46>
PCH_ALW_ON<52,53>
BIA_PWM_EC<28>
BC_CLK_ECE5048<48>
BC_DAT_ECE5048<48>
BC_INT#_ECE5048<48>
BC_CLK_EMC4002<25>
BC_DAT_EMC4002<25>
BC_INT#_EMC4002<25>
PCH_PCIE_WAKE#<19>
PCIE_WAKE#<16,42,43,47>
BC_CLK_ECE1117<50>
BC_DAT_ECE1117<50>
BC_INT#_ECE1117<50>
SIO_SLP_S5#<19>
ACAV_IN_NB<48,62,63>
SIO_EXT_SMI#<17,20>
SIO_RCIN#<21>
IRQ_SERIRQ<17,41,48>
PCH_PLTRST#_EC<20,41,42,43,47,48>
CLK_PCI_MEC<20>
LPC_LFRAME#<17,41,42,48>
LPC_LAD0<17,41,42,48>
LPC_LAD1<17,41,42,48>
LPC_LAD2<17,41,42,48>
LPC_LAD3<17,41,42,48>
CLKRUN#<19,41,48>
SIO_EXT_SCI#<21>
EC_32KHZ_ECE5048<48>
100K_0402_5%~D
@
10K_0402_5%~D
10K_0402_5%~D
12
12
12
R850
R847
R849
R848
HOST_DEBUG_TXHOST_DEB_TX
HOST_DEBUG_RX
R811 10K_0402_5%~D
1U_0402_6.3V6K~D
1
2
1 2
R815 0_0402_5%~D@
+3.3V_M
12
R893
100K_0402_5%~D
SSM3K7002FU_SC70-3~D
13
D
Q52
S
4700p
4700p
4700p
4700p
4700p
4700p
1 2
C757
+RTC_CELL_VBAT
U54
PS/2 INTERFACE
A5
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
B6
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK
A37
GPIO110/PS2_CLK2/GPTP-IN6
B40
GPIO111/PS2_DAT2/GPTP-OUT6
A38
GPIO112/PS2_CLK1A
B41
GPIO113/PS2_DAT1A
A39
GPIO114/PS2_CLK0A
B42
GPIO115/PS2_DAT0A
B59
GPIO154/I2C1C_DATA/PS2_CLK1B
A56
GPIO155/I2C1C_CLK/PS2_DAT1B
JTAG INTERFACE
A51
GPIO145/I2C1K_DATA/JTAG_TDI
B55
GPIO146/I2C1K_CLK/JTAG_TDO
B56
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
A53
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
B57
JTAG_RST#
FAN PWM & TACH
B22
GPIO050/FAN_TACH1
A21
GPIO051/FAN_TACH2
B23
GPIO052/FAN_TACH3
B24
GPIO053/PWM0
A23
GPIO054/PWM1
B25
GPIO055/PWM2
A24
GPIO056/PWM3
BC-LINK
A43
GPIO123/BCM_A_CLK
B45
GPIO122/BCM_A_DAT
A42
GPIO121/BCM_A_INT#
A12
GPIO022/BCM_B_CLK
B13
GPIO023/BCM_B_DAT
A13
GPIO024/BCM_B_INT#
B20
GPIO044/BCM_C_CLK
A18
GPIO043/BCM_C_DAT
B19
GPIO042/BCM_C_INT#
A20
GPIO047/LSBCM_D_CLK
B21
GPIO046/LSBCM_D_DAT
A19
GPIO045/LSBCM_D_INT#
A16
GPIO032/GPTP-IN3/BCM_E_CLK
B16
GPIO31/GPTP-OUT2/BCM_E_DAT
A15
GPIO30/GPTP-IN2/BCM_E_INT#
HOST INTERFACE
A6
GPIO011/nSMI
A27
GPIO061/LPCPD#
B29
LDRQ#
A28
SER_IRQ
B30
LRESET#
A29
PCI_CLK
B31
LFRAME#
A30
LAD0
B32
LAD1
A31
LAD2
B33
LAD3
A32
CLKRUN#
A33
GPIO100/nEC_SCI
MASTER CLOCK
A61
XTAL1
A62
XTAL2
B62
GPIO160/32KHZ_OUT
B34
NC1
A64
NC2
B68
NC3
PCH_PWRGD# <25>
REV
X00_SSI
X01_Pre-PT
X02_PT2
X03_ST
A00_X-build
BOARD_IDrisetimeismeasuredfrom5%~68%.
4
3
+RTC_CELL
100K_0402_5%~D
12
C729
+3.3V_ALW
12
1
2
A10
B10
B14
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
A55
A57
B61
B65
A46
B2
A2
B8
B18
A8
B9
A9
A14
B15
A17
B39
A44
B47
A54
B58
A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50
A59
B63
A60
A63
B67
B1
A1
B51
A48
B17
B27
B28
2
G
1K_0402_1%~D
1
2
0.1U_0402_25V6K~D
C731
+3.3V_RUN
R871
4700P_0402_25V7K~D
C742
R819
1 2
R825 10K_0402_5%~D
1U_0402_6.3V6K~D
1
C734
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
1
C728
C726
2
2
2
SYSTEM_ID
BOARD_ID
DDR_ON
HOST_DEBUG_TX
HOST_DEBUG_RX
RUNPWROK
EN_INVPWR
DDR_HVREF_RST_GATE
DYN_TUR_CURRNT_SET#
CPU1.5V_S3_GATE
MSDATA
MSCLK
SIO_A20GATE
PS_ID
FWP#
PROCHOT#_EC
1 2
R884 1K_0402_1%~D
1 2
R886 1K_0402_1%~D
1 2
R887 1K_0402_1%~D
PM_APWROK
1.05V_A_PWRGD
ALW_PWRGD_3V_5V
DEVICE_DET#
RESET_OUT#
PCH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
BAY_SMBDAT
BAY_SMBCLK
GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
CARD_SMBDAT
CARD_SMBCLK
USH_SMBDAT
USH_SMBCLK
LAT_ON_SW#
ALWON
VCI_IN1#
POWER_SW_IN#
ACAV_IN
DOCK_PWR_SW#
+PECI_VREF
PECI_EC_R
R863 43_0402_5%~D
10K_0402_5%~D
12
R799
SSM3K7002FU_SC70-3~D
Q45
13
D
S
C739
C746
@
1 2
POWER_SW#_MB <47> DOCK_PWR_BTN# <46>
+3.3V_ALW_U54
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
A41
A58
A52
A26
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]B3VTR[8]
MISC INTERFACE
GPIO124/GPTP-OUT5/UART_RX
GENERAL PURPOSE I/O
GPIO014/GPTP-IN7/HSPI_CS1
GPIO040/GPTP-OUT3/HSPI_CS2
SMBUS INTERFACE
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
DELL PWR SW INF
VR_CAP
VSS_RO
B12
B54
+VR_CAP
4.7U_0603_6.3V6K~D
1
C740
2
C740closetoU51.B12
RUN_ON_ENABLE#<52>
ChangeboardIDtoA00
R875
8.2K_0402_5%~D
1
C744
4700P_0402_25V7K~D
2
0.1U_0402_25V6K~D
1
1
C727
C732
2
2
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO025/UART_CLK
GPIO120/UART_TX
VCC_PRWGD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/HSPI_SCLK
GPIO104/HSPI_MISO
GPIO106/HSPI_MOSI
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
PROCHOT#/PWM4
GPIO001/ECSPI_CS1
GPIO002/ECSPI_CS2
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO026/GPTP-IN1
GPIO027/GPTP-OUT1
GPIO041
GPIO107/nRESET_OUT
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#
PECI
PECI_VREF
PECI
I2S
I2S_DAT
I2S_CLK
I2S_WS
EP
MEC5055-LZY_DQFN132_11X11~D
C1
ChangetoCPN:SA00003TZ2L
RUNPWROK
SYSTEM_ID
15mil
0.1U_0402_25V6K~D
1
C745
2
B64
A11
A22
B35
VBAT
VTR[1]
VTR[2]
DB Version 0.12
VSS[1]
AGND
VSS[4]
B11
B66
B60
least
15mil
+3.3V_ALW
10K_0402_5%~D
12
R872
FWP#
10K_0402_5%~D
@
R879
1 2
+3.3V_ALW
12
BOARD_ID
CHIPSET_IDforBIDfunction
3
2
C733
@
1 2
1U_0402_6.3V6K~D
PJP28
PAD-OPEN1x1m
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
1
1
C738
C730
2
2
DDR_ON <55>
HOST_DEBUG_TX <42>
HOST_DEBUG_RX <42>
RUNPWROK <7,48>
EN_INVPWR <28>
DDR_HVREF_RST_GATE <7>
DYN_TUR_CURRNT_SET# <62>
CPU1.5V_S3_GATE <11>
MSDATA <42>
MSCLK <42>
SIO_A20GATE <21>
PS_ID <53>
ME_SUS_PWR_ACK <19>
1.5V_SUS_PWRGD <55>
PM_APWROK <19>
1.05V_A_PWRGD <57>
ALW_PWRGD_3V_5V <54>
DEVICE_DET# <36>
RESET_OUT# <19>
DYN_TURB_GPU_PWR_ALRT# <16,26>
PCH_RSMRST# <50>
AC_PRESENT <19>
SIO_PWRBTN# <19>
DOCK_SMB_DAT <46>
DOCK_SMB_CLK <46>
LCD_SMBDAT <26,28>
LCD_SMBCLK <26,28>
GPU_SMBDAT <16>
GPU_SMBCLK <16>
CHARGER_SMBDAT <62>
CHARGER_SMBCLK <62>
CARD_SMBDAT <47>
CARD_SMBCLK <47>
USH_SMBDAT <41>
USH_SMBCLK <41>
ALWON <54>
ACAV_IN <16,25,62,63>
1 2
PROCHOT#_EC
2
AC_PRESENT
SMBUS EA for rise timing fail.
+3.3V_ALW
12
VOL_MUTE <47>
VOL_UP <47>
VOL_DOWN <47>
PECI_EC <7>
2
G
R1180 0_0402_5%~D@
R862closeto
U54atleast250mils
0.1U_0402_25V6K~D
1
2
1 2
SSM3K7002FU_SC70-3~D
13
D
S
LCD_SMBCLK
LCD_SMBDAT
DOCK_SMB_DAT
DOCK_SMB_CLK
BAY_SMBDAT
BAY_SMBCLK
DYN_TUR_CURRNT_SET#
DEVICE_DET#
PCIE_WAKE#
BC_DAT_EMC4002
BC_DAT_ECE5048
BC_DAT_ECE1117
PBAT_SMBDAT
PBAT_SMBCLK
LPC_LDRQ#_MEC
CHARGER_SMBDAT
CHARGER_SMBCLK
MSDATA
DDR_ON
PCH_ALW_ON
DOCK_POR_RST#
EN_INVPWR
1.05V_0.8V_PWROK
RESET_OUT#
CPU1.5V_S3_GATE
PCH_RSMRST#
R862
@
1 2
C737
@
Q47
PROCHOT#_EC
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
1 2
1 2
R20992.2K_0402_5%~D
1 2
R21002.2K_0402_5%~D
1 2
R8382K_0402_5%~D
1 2
R8412K_0402_5%~D
1 2
R8542.2K_0402_5%~D
1 2
R8562.2K_0402_5%~D
1 2
R1178100K_0402_5%~D
1 2
R1125100K_0402_5%~D
12
R75910K_0402_5%~D
1 2
R821100K_0402_5%~D
12
R814100K_0402_5%~D
12
R817100K_0402_5%~D
12
R8182.2K_0402_5%~D
12
R8202.2K_0402_5%~D
12
R823100K_0402_5%~D @
12
R8272.2K_0402_5%~D
12
R8282.2K_0402_5%~D
12
12
12
12
12
12
12
12
12
+1.05V_RUN_VTT
0_0402_5%~D
H_PROCHOT# <7,26,60,62>
+1.05V_RUN_VTT
10K_0402_5%~D
12
@
R1179
100K_0402_5%~D
@
R812
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EMC5055
EMC5055
EMC5055
LA-7931P
LA-7931P
LA-7931P
1
+3.3V_ALW_PCH
R83510K_0402_5%~D
R86910K_0402_5%~D
R876100K_0402_5%~D
R880100K_0402_5%~D
R881100K_0402_5%~D
R882100K_0402_5%~D
R88310K_0402_5%~D
R8438.2K_0402_5%~D @
R889100K_0402_5%~D
R89210K_0402_5%~D
+3.3V_ALW
49 70Monday, July 23, 2012
49 70Monday, July 23, 2012
49 70Monday, July 23, 2012
1.0
1.0
1.0
of
of
of
Page 50
5
D D
4
3
2
1
BlueTooth
For meet T235(power off)= min 40ns(SPEC).T08a(power on)= max 90ms.
RSMRSTcircuit
+5V_ALW_PCH
12
R2159
0_0402_5%~D
+5V_ALW_PCH_R
0.01U_0402_16V7K~D
1
C C
C290
2
U4
1
VCC
RESET#
2
GND
RT9818A-44GU3_SC70-3~D
+3.3V_ALW_PCH
R1622
100K_0402_5%~D
1 2
EC SIDE
3
RSMRST#
PCH_RSMRST#<49>
74AHC1G08GW_SOT353-5~D
R1623 0_0402_5%~D@
1 2
+3.3V_ALW
C289
1 2
0.1U_0402_25V6K~D
5
U7
1
P
IN1
O
2
IN2
G
3
4
R2142
@
1 2
0_0402_5%~D
preventmaterialshortageforThaiflood.
PCH_RSMRST#_Q <17,19>
BT_RADIO_DIS#<42,48>
+3.3V_RUN
1 2
R2206 0_0402_5%~D
@
D106
RB751S40T1_SOD523-2~D
1 2
R1133 1K_0402_1%~D
1 2
R1134 1K_0402_1%~D
COEX2_WLAN_ACTIVE<42>
21
BT_RADIO_DIS#_D
JBT1 pin11 Need confirm with Dell to add BT_DET or not.
+3.3V_RUN
BT_COEX_STATUS2
BT_PRI_STATUS
COEX1_BT_ACTIVE<42>
BT_COEX_STATUS2<41>
BT_PRI_STATUS<41>
BT_ACTIVE<51>
USBP11-<20>
USBP11+<20>
BT_RADIO_DIS#_D
33P_0402_50V8J~D
C753
1
2
0.1U_0402_25V6K~D
C748
1
2
100P_0402_50V8J~D
10K_0402_5%~D
R904
@
C754
1
2
12
JBT1
CONN@
14
GND
13
GND
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
ACES_50450-0127N-001
LinkCISOK
0914
ReserveforWiGigcardfunction
JBT1 pin1~pin12 pin define order swap to
pin12~pin1 for BT connector change to
ACES_50450-0127N-001.
(because footprint different from ACES_50228-0127N_001)
Keyboard
B B
JKB1
+3.3V_ALW
0.1U_0402_25V6K~D
1
C756
2
PlaceclosetoJKB1
+5V_RUN
1
2
0.1U_0402_25V6K~D
C758
KB_DET#<21>
PS2_CLK_TS<47>
PS2_DAT_TS<47>
+3.3V_ALW
+5V_RUN
BC_INT#_ECE1117<49>
BC_DAT_ECE1117<49>
BC_CLK_ECE1117<49>
KB_DET#
PS2_CLK_TS
PS2_DAT_TS
CONN@
2
112
4
334
6
556
8
778
10
9910
12
111112
14
131314
16
151516
18
171718
20
191920
AMPHE_G281010112CHR~D
KB_DET#
PS2_CLK_TS
PS2_DAT_TS
+3.3V_ALW
+5V_RUN
BC_INT#_ECE1117
BC_DAT_ECE1117
BC_CLK_ECE1117
LinkCISOK
0722
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
Touch PAD/Int KB
Touch PAD/Int KB
Touch PAD/Int KB
LA-7931P
LA-7931P
LA-7931P
50 70Monday, July 23, 2012
50 70Monday, July 23, 2012
50 70Monday, July 23, 2012
1
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Page 51
5
4
3
2
1
HDDLED
+3.3V_ALW
12
R932
10K_0402_5%~D
Q74B
DMN66D0LDW-7_SOT363-6~D
D D
SATA_ACT#<17>
MASK_SATA_LED#<48>
LED_SATA_DIAG_OUT#<48>
4
5
D59
3
RB751S40T1_SOD523-2~D
D62
RB751S40T1_SOD523-2~D
21
21
DMN66D0LDW-7_SOT363-6~D
MASK_BASE_LEDS#
SSM3K7002FU_SC70-3~D
SYS_LED_MASK#
Q74A
2
Q326
D
S
13
G
2
+5V_ALW
61
2
1 3
+5V_ALW
2
1 3
Q75
PDTA114EU_SC70-3~D
1 2
R934680_0402_5%~D
MeetLEDbrightnessspec.
Q86
PDTA114EU_SC70-3~D
1 2
R943 510_0402_1%
MeetLEDbrightnessspec.
SATA_LED <47>
SATA_SIDE_LED <47>
NUMLED
NUM_LED#<48>
+5V_RUN
2
1 3
MeetLEDbrightnessspec.
Q80
PDTA114EU_SC70-3~D
1 2
R942806_0402_1%~D
NUM_LED <47>
BreathLED
WWAN/WLANLED
C C
WIRELESS_LED#<42,43,48>
+3.3V_ALW
12
R944
100K_0402_5%~D
Q78B
DMN66D0LDW-7_SOT363-6~D
3
4
MASK_SATA_LED#
LED_WLAN_WWAN_DIAG_OUT#<48>
5
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+3.3V_ALW
12
R937
100K_0402_5%~D
D60
21
21
MASK_BASE_LEDS#
D63
Q78A
DMN66D0LDW-7_SOT363-6~D
2
+5V_ALW
2
61
Q79
PDTA114EU_SC70-3~D
1 3
1 2
MeetLEDbrightnessspec.
R939680_0402_5%~D
WLAN_LED <47>
Change B39 of ECE5048 EC code to GPIO(input)
Solving LED flicker when AC-in plug.
BREATH_LED#<46,48>
changetosinglepackage.
SSM3K7002FU_SC70-3~D
Q84
D
S
G
2
MASK_BASE_LEDS#
MeetLEDbrightnessspec.
13
1 2
1 2
BREATH_LED side view.
R956340_0402_1%
R955300_0402_1%
BREATH_LED#_Q
BREATH_LED#_Q <47>
BREATH_WHITE_LED <47>
BREATH_LED TOP view.
BTLED
+3.3V_ALW
B B
WiGi_BT_LED#<42>
1 2
R2207 0_0402_5%~D@
WiGi_BTLEDfunction.
BT_ACTIVE<50>
100K_0402_5%~D
WiGi_BT_LED#_R
5
improve BT_LED behaviour abnormal(BT_LED must dark) in S3/S4/S5.
MASK_BASE_LEDS#
12
R938
2
61
DMN66D0LDW-7_SOT363-6~D
3
Q318B
4
Q318A
DMN66D0LDW-7_SOT363-6~D
1 2
R941 680_0402_5%~D
MeetLEDbrightnessspec.
BT_LED <47>
LED Circuit Control Table
SYS_LED_MASK# LID_CL#
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Fiducial Mark
FD1
@
1
FIDUCIAL MARK~D
A A
FD2
@
1
FIDUCIAL MARK~D
FD3
@
1
FIDUCIAL MARK~D
FD4
@
1
FIDUCIAL MARK~D
H1
@
H_2P8
1
H22
@
H_2P8
1
5
@
H_4P1
H23
1
for Hi-POT issue.
H4
@
H_2P8
1
H24
@
H_4P1
1
Do not Mask LEDs (Lid Opened) 11
H5
@
H_3P2x6P2N
1
H25
@
H_2P8
1
@
H_2P8
@
H_2P8
H26
H6
1
@
H_2P3
1
MErequest.
@
H_3P8
H27
H7
H9
@
H8
@
H_3P3
H_3P3
1
1
1
1
4
@
H_3P3
H10
H11
@
H_3P3
1
1
0
10
H13
@
H_2P3
@
@
H12
H_3P2
H_2P8
1
1
H16
@
H15
@
H14
1
H_2P8
@
H_3P8
H_2P8
1
1
1
X
H21
@
H19
@
H20
@
H18
@1H17
H_4P1
H_4P1
H_4P1x2P1
H_2P8
1
1
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
RemoveQ339forWiGigcardfunctionusage.
LID_CL#<47,48>
74AHC1G08GW_SOT353-5~D
2
SYS_LED_MASK#
LID_CL#
SYS_LED_MASK#<48>
+3.3V_ALW
C778
1 2
0.1U_0402_25V6K~D
5
U58
1
P
IN1
4
MASK_BASE_LEDS#
O
2
IN2
G
3
preventmaterialshortageforThaiflood.
MASK_BASE_LEDS# <47>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PAD & Standoff & LED
PAD & Standoff & LED
PAD & Standoff & LED
LA-7931P
LA-7931P
LA-7931P
1
51 70Monday, July 23, 2012
51 70Monday, July 23, 2012
51 70Monday, July 23, 2012
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5
4
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2
1
+3.3V_ALWto+3VMXM
+PWR_SRC_S
+3.3V_ALW2
1
2
100K_0402_5%~D
12
13
D
S
+3.3V_ALW2
12
R907
61
2
0.1U_0603_25V7K~D
@
C362
+PWR_SRC_MXM
R940
+MXM_SRC_EN#
SSM3K7002FU_SC70-3~D
Q87
ALW_ON_3.3V#
100K_0402_5%~D
12
61
R294
RUN_GFX_ON#
DMN66D0LDW-7_SOT363-6~D
Q294A
5
2
Q186
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
4
2200P_0402_50V7K~D
1
C774
2
+PWR_SRC_S
100K_0402_5%~D
12
R905
+3V_ALW_PCH_ENABLE
DMN66D0LDW-7_SOT363-6~D
3
Q305B
5
4
D D
RUN_GFX_ON<18,48>
100K_0402_5%~D
12
R301
Solve S4/S5 +MXM_PWR_SRC leakage in DC mode.
C C
MXM_PWR_SRCSource
+PWR_SRC_MXM
2
RUN_GFX_ON
G
+3.3V_ALW_PCHSource
100K_0402_5%~D
ALW_ON_3.3V#<23>
Q305A
DMN66D0LDW-7_SOT363-6~D
B B
PCH_ALW_ON<49,53>
2
+3.3V_ALW
10U_0805_10V4Z~D
200K_0402_5%
12
R269
C357
+3VMXM_GATE
DMN66D0LDW-7_SOT363-6~D
3
Q294B
4
+5V_ALW +5V_MXM
+PWR_SRC_S
1
200K_0402_5%
12
2
R275
+5VMXM_GATE
SSM3K7002FU_SC70-3~D
13
D
Q36
G
S
MXM_SENSE_N<26>
MXM_SENSE_P<26>
8
+MXM_PWR
7
5
+3.3V_ALW +3.3V_ALW_PCH
Q49
SI3456DDV-T1-GE3_TSOP6~D
D
6
2
1
G
1M_0402_5%~D
12
R1619
Q25
SI3456DDV-T1-GE3_TSOP6~D
D
6
2
1
1
G
2
1M_0402_5%~D
12
R2104
+5V_ALWto+5VMXM
Q76
SI4800BDY-T1-GE3_SO8
8
10U_0805_10V4Z~D
7
C353
5
0.1U_0603_25V7K~D
1
C355
2
2
134
0.005_2512_1%
R1973
S
45
10U_0603_6.3V6M~D
C760
1
3
2
3300P_0402_50V7K~D
C762
1
2
+3.3V_MXM
S
45
3
0.1U_0603_25V7K~D
C352
1
2
4
0_0402_5%~D
12
R278
40mil(1A)
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
C449
1
1
C354
2
2
RUN_ON_ENABLE#<49>
SIO_SLP_S3#<11,19,35,47,48,56>
1
10U_0805_10V4Z~D
2
36
@
0.1U_0402_16V4Z~D
1
1
C356
C351
2
2
+MXM_PWR_SRC
10U_1206_25V6M~D
100K_0402_5%~D
12
1
R935
C776
2
R935 form 20K to 100K
Power saving.
100mil(2.5A)
1 2
R781 0_0402_5%~D@
1 2
RUN_ON<35,47,48,56>
R762 0_0402_5%~D@
+3.3V_ALW2
12
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
61
Q304A
2
Solve300mW
PWRconsumption
issue.(R2069,C1274)
RUN_ON_ENABLE#
+3.3V_SUSSource
+3.3V_ALW2
12
R915
20K_0402_5%~D
12
R908
1 2
SUS_ON<48>
R806 0_0402_5%~D@
R808 0_0402_5%~D@
1 2
SIO_SLP_S4#<19,48,55>
100K_0402_5%~D
SUS_ON_3.3V#
DMN66D0LDW-7_SOT363-6~D
61
Q303A
2
tune +3.3V_SUS timing begin to +3.3V_RUN for solving Smart card detect issue.
+PWR_SRC_S
R909
5
2
G
+PWR_SRC_S
470K_0402_5%~D
12
13
D
2
G
S
+PWR_SRC_S
12
R911
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
3
Q303B
5
4
12
R930
330K_0402_5%~D
+1.05V_RUN_ENABLE
DMN66D0LDW-7_SOT363-6~D
3
Q304B
4
470K_0402_5%~D
12
R2067
+5V_RUN_ENABLE
SSM3K7002FU_SC70-3~D
13
D
Q330
Solve300mW
PWRconsumption
S
issue.
R2069
+3.3V_RUN_ENABLE
SSM3K7002FU_SC70-3~D
Q332
+SUS_ENABLE
+1.05V_RUNSource
+1.05V_M
Q63
SI4164DY-T1-GE3_SO8~D
8
7
5
1M_0402_5%~D
12
R1611
+5V_RUNSource
DMN3030LSS-13_SOP8L-8
8
7
5
+3.3V_RUNSource
+3.3V_ALW
DMN3030LSS-13_SOP8L-8
8
7
5
1M_0402_5%~D
@
12
R2127
Meet power sequencing 0.7V.
+3.3V_ALW
Q54
SI3456DDV-T1-GE3_TSOP6~D
D
6
S
45
2
1
G
3
470P_0402_50V7K~D
1M_0402_5%~D
12
R1618
C767
1
2
1
2
36
4
100P_0402_50V8J~D
1
C773
2
Solve300mW
PWRconsumption
issue.
Q329
1
2
36
4
220P_0402_50V8J~D
12
C1272
Q331
1
2
36
4
220P_0402_50V8J~D
C1274
12
10U_0603_6.3V6M~D
C765
1
2
1
2
+3.3V_SUS
12
20K_0402_5%~D
10U_0603_6.3V6M~D
C772
1
2
+3.3V_RUN
10U_0805_6.3V6M~D
1
2
R914
+1.05V_RUN
20K_0402_5%~D
12
+5V_RUN+5V_ALW+PWR_SRC_S
10U_0805_10V4Z~D
C1271
12
C1273
R931
20K_0402_5%~D
12
R2068
20K_0402_5%~D
R2070
+3.3V_MSource
DMN66D0LDW-7_SOT363-6~D
SIO_SLP_A#<19,48,57>
Q57A
+3.3V_ALW2
2
12
R918
100K_0402_5%~D
A_ON_3.3V#
61
+PWR_SRC_S
12
3
5
4
R917
470K_0402_5%~D
+A_ENABLE
DMN66D0LDW-7_SOT363-6~D
Q57B
+3.3V_ALW
4.7M_0402_5%~D
12
R1617
Q58
SI3456DDV-T1-GE3_TSOP6~D
D
6
S
45
2
1
G
3
220P_0402_50V8J~D
12
C770
Solve300mW
PWRconsumption
issue.
+3.3V_M
10U_0603_6.3V6M~D
20K_0402_5%~D
C768
@
1
12
R919
2
RUN_GFX_ON#
+3.3V_MXM +5V_MXM
470_0603_5%
12
@
R268
+3VMXM_D
SSM3K7002FU_SC70-3~D
13
D
@
Q48
2
G
2
G
S
470_0603_5%
12
@
R274
+5VMXM_D
SSM3K7002FU_SC70-3~D
13
D
S
@
Q50
pop for boot leakage to +3.3v_run.
R928
@
1K_0402_1%~D
SSM3K7002FU_SC70-3~D
@
Q66
DischargCircuit
RUN_ON_ENABLE#
+1.05V_RUN +0.75V_DDR_VTT+1.5V_CPU_VDDQ
R929
39_0603_5%~D
SSM3K7002FU_SC70-3~D
12
R925
@
39_0402_5%~D
+1.05V_RUN_CHG
SSM3K7002FU_SC70-3~D
@
13
D
Q69
Q70
2
G
S
RUN_ON_CPU1.5VS3#<7,11>
12
R926
220_0402_5%~D
+1.5V_CPU_VDDQ_CHG
13
D
2
G
S
3
R924
@
1K_0402_1%~D
SSM3K7002FU_SC70-3~D
@
Q68
4
12
+3.3V_RUN_CHG
13
D
2
G
S
12
12
R923
@
1K_0402_1%~D
+1.5V_RUN_CHG
+5V_RUN_CHG
SSM3K7002FU_SC70-3~D
@
13
13
D
D
Q67
2
2
G
G
S
S
12
R927
22_0603_5%~D
+DDR_CHG
SSM3K7002FU_SC70-3~D
Q71
SSM3K7002FU_SC70-3~D
13
D
Q72
2
A_ON_3.3V#
G
S
12
R916
39_0603_5%~D
+3.3V_M_CHG
SSM3K7002FU_SC70-3~D
13
D
Q60
2
G
S
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Power Control
Power Control
Power Control
LA-7931P
LA-7931P
LA-7931P
1
52 70Monday, July 23, 2012
52 70Monday, July 23, 2012
52 70Monday, July 23, 2012
of
of
of
1.0
1.0
1.0
+3.3V_SUS +1.5V_RUN +3.3V_RUN+5V_RUN+3.3V_ALW_PCH +3.3V_M
12
R922
A A
SUS_ON_3.3V# ALW_ON_3.3V#
@
1K_0402_1%~D
+3.3V_SUS_CHG
SSM3K7002FU_SC70-3~D
@
13
D
Q65
2
G
S
12
+3.3V_ALWPCH_CHG
13
D
2
G
S
5
Page 53
5
4
3
2
1
+COINCELL
COIN RTC Battery
PL1
HCB2012KF-121T50_0805
+PWR_SRC
D D
12
12
12
PC31
PC30
@
@
10U_0805_25V6K
0.1U_0603_25V7K~D
1
PD2
PESD24VS2UT_SOT23-3~D
2
3
Primary Battery Connector
PBATT1
11
GND
10
GND
1
9
2
8
3
7
4
6
12
PC4
C C
2200P_0402_50V7K~D
B B
5
5
6
4
7
3
8
2
9
1
SUYIN_200045GR009M28QL
Z4304
Z4305
Z4306
GND
NB_PSID
PR3
100_0402_5%~D
1 2
1
+
PC1
2
100U_25V_M~D
@
100_0402_5%~D
BLM18BD102SN1D_0603~D
+PWR_SRC_MXM
ESD Diodes
2
PR5
1 2
PL3
12
1
PD3
@
PESD24VS2UT_SOT23-3~D
3
100_0402_5%~D
PR4
1 2
PR10
1 2
100K_0402_1%~D
PR12
1 2
15K_0402_1%~D
PBATT+_C
PBAT_SMBCLK <49>
PBAT_SMBDAT <49>
@
1 2
0_0402_5%~D
1 3
2
B
PC3
0.1U_0603_25V7K~D
PR7
D
S
PQ2
FDV301N_G_NL_SOT23-3~D
G
2
C
PQ3
MMST3904-7-F_SOT323~D
E
3 1
PL2
FBMJ4516HS720NT_2P~D
1 2
PL6
FBMJ4516HS720NT_2P~D
1 2
12
PR9
33_0402_5%~D
1 2
PD7
@
+5V_ALW
3
DA204U_SOT323~D
2
1
+5V_ALW
+3.3V_RTC_LDO
RB715FGT106_UMD3
+3.3V_ALW
SLICE_BAT_PRES#<46,48,63>
PR13
1 2
10K_0402_5%~D@
12
PR2
100K_0402_5%~D
+3.3V_ALW
PR8
1 2
2.2K_0402_5%~D
PBAT_PRES# <48>
PQ1
PD5
1 2
SDMK0340L-7-F_SOD323-2~D
FDN338P_G_NL_SOT23-3~D
1 3
1
3
2
2
PR6
@
0_0402_5%~D
1 2
NB_PSID_TS5A63157
12
1500P_0402_7K~D
DOCK_PSID<46> GPIO_PSID_SELECT <48>
PSID_DISABLE# <48>
PBATT+
GND
12
PR11
10K_0402_1%~D
3
PD1
PC5
1
2
1
PU1
TS5A63157DCKR_SC70-6~D
12
PR1
1K_0402_5%~D
Z4012
2
+RTC_CELL
1
PC2
1U_0603_10V4Z~D
2
Move to power schematic
DOCK_SMB_ALERT# <46,48>
6
IN
NO
GND
NC3COM
5
V+
4
+COINCELL
+5V_ALW
PS_ID <49>
JRTC1
1
1
2
2
3
GND
4
GND
ACES_50271-0020N-001
DC_IN+ Source
+DC_IN
PL4
C8B BPH 853025_2P~D
1 2
PJPDC1
1
1
2
2
3
3
4
4
5
5
6
6
7
+DCIN_JACK
7
A A
8
8
9
9
10
10
11
11
ACES_50290-01101-001
12
PC11
0.1U_0603_25V7K~D
5
12
PC15
@
0.1U_0603_25V7K~D
+DC_IN
PC9
12
PR19
@
4.7K_0805_5%~D
12
1 2
PR16
1M_0402_5%~D
0.022U_0805_50V7K~D
12
PR22
4
1
2
3
PR20
1 2
10K_0402_5%~D
1M_0402_5%~D
PQ5SI7149DP
4
5
SOFT_START_GC <63>
12
12
PC10
PC12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+DC_IN_SS
12
12
12
PC13
0.1U_0603_25V7K~D
PC14
PR18
10U_0805_25V6K
100K_0402_5%~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+3.3V_ALW
PCH_ALW_ON<49,52>
+PWR_SRC
PR21 0_0402_5%~D@
1 2
1 2
@
PR23
0_0402_5%~D
VSB_N_002
12
12
PC7
PR15
PR17
22K_0402_1%
1 2
VSB_N_003
13
D
2
G
S
12
PC16
.1U_0402_16V7K~D
100K_0402_1%~D
PQ7
SSM3K7002FU_SC70-3~D
2
0.22U_0603_25V7K~D
VSB_N_001
2
TP0610K-T1-E3_SOT23-3
+PWR_SRC_S
13
12
PC8
PQ4
0.1U_0603_25V7K~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+DCIN
+DCIN
+DCIN
LA-7931
LA-7931
LA-7931
1
1.0
1.0
53 70Monday, July 23, 2012
53 70Monday, July 23, 2012
53 70Monday, July 23, 2012
1.0
Page 54
A
B
C
D
E
2VREF_6182
1 1
12
PC102
PC103
0.1U_0402_25V6K~D
ALWON<49>
A
+DC1_PWR_SRC
12
12
PC104
2200P_0402_50V7K~D
PR115
2K_0402_1%~D
1 2
PR118
@
0_0402_5%~D
1 2
4.7U_0805_25V6K~D
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
PC112
220U_6.3V_M
DMN66D0LDW-7_SOT363-6~D
PQ106B
12
PC119
@
1U_0603_10V6K~D
FDMC8884_POWER33-8-5
PL103
1 2
1
+
2
ENTRIP2
3
5
4
13
2
PQ101
12
@
PR110
4.7_1206_5%~D
SNUB_3V
12
@
PC114
+PWR_SRC
DMN66D0LDW-7_SOT363-6~D
ENTRIP1
61
PQ106A
2
PR117
100K_0402_1%~D
1 2
PQ105
PDTC115EU_SOT323-3
+3.3V_RTC_LDO
3 5
241
PQ103
FDMC7692S_POWER33-8-5
3 5
241
680P_0603_50V7K~D
MMSZ5229BS_SOD323~D
+5V_ALW2
B
PR105
@
0_0402_5%~D
1 2
PC105
10U_0805_6.3V6M~D
PC100
0.22U_0603_16V7K~D
1 2
LX_3V
PC199
56P_0402_50V8J~D
1 2
@
PD100
@
1 2
+3.3V_ALW2
12
1 2
2.2_0603_5%~D
PR113
@
499K_0402_1%~D
12
PR108
LG_3V
12
PR112
@
300K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
+PWR_SRC
PL100
1UH_PCMB053T-1R0MS_7A_20%
2 2
12
+3.3V_ALWP
+3.3V_ALWP
TDC 6 A
Peak Current 8 A
OCP current 9.6 A
3 3
4 4
THERM_STP#<25>
@
22P_0402_50V8J~D
13.7K_0402_1%~D
1 2
20K_0402_1%~D
1 2
PR106
110K_0402_1%~D
1 2
25
BST_3V
10
UG_3V
11
12
12
PC116
1U_0603_10V6K~D
2VREF_6182
1U_0603_16V6K~D
PC120
12
PR101
PR103
PU101
P PAD
7
VO2
8
VREG3
9
BOOT2
UGATE2
PHASE2
LGATE2
C
12
PC101
FB_3V
ENTRIP2
6
ENTRIP2
EN
13
+DC1_PWR_SRC
5
FB2
SKIPSEL
14
3
4
REF
TONSEL
VIN16GND
15
12
FB_5V
2
FB1
17
12
PC117
4.7U_0805_10V6K~D
PC118
0.1U_0603_25V7K~D
PC121
@
12
22P_0402_50V8J~D
PR102
30.9K_0402_1%~D
1 2
PR104
20K_0402_1%~D
1 2
PR107
124K_0402_1%~D
1 2
ENTRIP1
1
ENTRIP1
24
VO1
23
PGOOD
22
BOOT1
UGATE1
PHASE1
LGATE1
NC18VREG5
BST_5V
21
UG_5V
20
LX_5V
19
LG_5V
RT8205LZQW(2) WQFN 24P PWM
+5V_ALW2
+3.3V_ALWP
PR109
1 2
2.2_0603_5%~D
470K_0402_5%~D
+5V_ALWP
+DC1_PWR_SRC
12
12
PC106
PC107
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
PC110
0.22U_0603_16V7K~D
1 2
BST1_5VBST1_3V
PC198
@
56P_0402_50V8J~D
+3.3V_ALW
PR114
1 2
@
PJP102
1 2
PAD-OPEN 4x4m
@
PJP103
1 2
PAD-OPEN 4x4m
@
PJP104
1 2
PAD-OPEN 4x4m
@
PJP105
1 2
PAD-OPEN 4x4m
D
12
12
PC108
PC109
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
12
PQ104
ALW_PWRGD_3V_5V <49>
+5V_ALW
+3.3V_ALW
PQ102
FDMC8884_POWER33-8-5
3 5
241
PR111
4.7_1206_5%~D
3 5
241
@
FDMC7692S_POWER33-8-5
PL102
3.3UH_FDV0630-3R3M-P3_5.7A_20%
1 2
12
@
1
+
PC113
220U_6.3V_M
2
SNUB_5V
12
PC115
680P_0603_50V7K~D
+5V_ALWP
+5V_ALWP
TDC 6.5 A
Peak Current 9.2 A
OCP current 11 A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
Compal Electronics, Inc.
+5V_ALWP/+3.3V_ALWP
+5V_ALWP/+3.3V_ALWP
+5V_ALWP/+3.3V_ALWP
LA-7931
LA-7931
LA-7931
54 70Monday, July 23, 2012
54 70Monday, July 23, 2012
54 70Monday, July 23, 2012
E
of
of
1.0
1.0
1.0
Page 55
A
@
+PWR_SRC
1 1
1.5VP
TDC 13 A
Peak Current 18.4 A
PJP201
1 2
PAD-OPEN 4x4m
1.5V_B+
12
12
PC202
PC201
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
12
12
PC204
PC203
0.1U_0402_25V6K~D
2200P_0402_50V7K~D
OCP current 22 A
PL201
1.0UH_PCMC104T-1R0MN_20A_20%
PJP202
JUMP_43X118
112
PJP203
JUMP_43X118
112
1 2
2
2
+1.5V_MEM
12
@
PR203
4.7_1206_5%~D
SNUB_1.5V
12
@
PC212
680P_0603_50V7K~D
DDR_ON<49>
SIO_SLP_S4#<19,48,52>
PR210
@
0_0402_5%~D
1 2
PR226
@
0_0402_5%~D
1 2
DDR GPIO Output Voltage Selection
DDR_1.5V_CNTRL1 DDR VoutDDR_1.5V_CNTRL0
0
+1.5VP
1
+
PC209
2
220U_D2_4VM~D
2 2
Mode DDR_ON 0.75V_DDR_VTT_ON +1.5VP +0.75VSP +V_DDR_REF
S0 H H on on on
S3 H L on off on
S4 L L off off off
S5 L L off off off
Note: S3 - sleep ; S5 - power off
3 3
+1.5VP
@
@
0
PJP205
2
112
JUMP_43X79@
4 4
+0.75V_DDR_VTT+0.75VSP
1
11
FDMS7698 1N POWER56-8
FDMS0309S_POWER56-8-5
1.5V_SUS_PWRGD<49>
5
123
5
123
PC299
@
12
PC213
@
0.1U_0402_16V7K~D
0
1
0
B
1 2
PQ201
4
PQ202
+5V_ALW
4
+3.3V_ALW
1 2
PR205
470K_0402_5%~D
56P_0402_50V8J~D
PR201
1 2
2.2_0603_5%~D
PC205
0.22U_0603_16V7K~D
PR204
5.1_0603_5%~D
1 2
1U_0603_10V6K~D
12
0.75V_DDR_VTT_ON<48>
1.65V
1.6V
1.55V
1.5V (Default)
PC211
BOOT_1.5V
DH_1.5V
SW_1.5V
DL_1.5V
PR202
6.98K_0402_1%~D
1 2
PC208
1U_0603_10V6K~D
PR214
@
0_0402_5%~D
1 2
CS_1.5V
VDD_1.5V
+5V_ALW
PGOOD_1.5V
1.5V_B+
S5_1.5V
DDR_1.5V_CNTRL0<48>
DDR_1.5V_CNTRL1<48>
15
LGATE
14
PGND
13
CS
RT8207MZQW_WQFN20_3X3
12
VDDP
11
VDD
PR209
1M_0402_1%~D
1 2
S3_1.5V
PR216
10K_0402_5%~D
PR222
10K_0402_5%~D
16
PHASE
PGOOD
10
@
@
17
UGATE
TON
9
C
18
8
+3.3V_ALW
12
+3.3V_ALW
VLDOIN_1.5V
19
BOOT
VLDOIN
S5
S3
7
PR219
10K_0402_5%~D
1 2
@
12
PR223
10K_0402_5%~D
1 2
@
10K_0402_5%~D
20
VTTGND
VTTSNS
VTTREF
6
@
PR220
10K_0402_5%~D
PR225
PU201
VTT
PAD
GND
VDDQ
FB
+1.5VP
@
12
@
PJP204
@
1 2
PAD-OPEN1x1m
21
1
2
3
4
5
PQ204B
5
12
PC215
@
12
PR206
@
0_0402_5%~D
1 2
+3.3V_ALW
12
PR213
10K_0402_5%~D
3
4
0.01U_0402_25V7K~D
PQ205B
12
PC217
@
DMN66D0LDW-7 2N SOT363-6
5
0.01U_0402_25V7K~D
@
@
12
PR217
12
3
4
+1.5VP
PQ204A
@
2
12
PC214
@
10K_0402_5%~D
0.01U_0402_25V7K~D
+3.3V_ALW
PR221
@
10K_0402_5%~D
DMN66D0LDW-7 2N SOT363-6
@
0.75Volt +/- 5%
TDC 1.4 A
Peak Current 2 A
12
12
PC206
PC207
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
PC210
0.033U_0402_16V7~D
+1.5VP
@
22P_0402_50V8J~D
PR211
@
150K_0402_1%~D
1 2
61
12
@
PR218
DMN66D0LDW-7 2N SOT363-6
PQ205A
@
12
PR224
@
10K_0402_5%~D
@
75K_0402_1%~D
61
2
12
PC216
0.01U_0402_25V7K~D
PC218
DMN66D0LDW-7 2N SOT363-6
D
+0.75VSP
+V_DDR_REF
1 2
1 2
12
PR208
10K_0402_1%~D
PR215
10K_0402_1%~D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
+1.5VSP/0.75VSP
+1.5VSP/0.75VSP
+1.5VSP/0.75VSP
LA-7931
LA-7931
LA-7931
D
55 70Monday, July 23, 2012
55 70Monday, July 23, 2012
55 70Monday, July 23, 2012
1.0
1.0
1.0
of
of
Page 56
A
B
C
D
1.8Volt +/-5%
TDC 0.65A
Peak Current 0.93A
1 1
PR301
12
470K_0402_5%~D
+3.3V_RUN
1.8V_RUN_PWRGD <48>
PL301
HCB1608KF-121T30_0603
SIO_SLP_S3#<11,19,35,47,48,52>
1 2
PR311
@
0_0402_5%~D
1 2
@
PR314
0_0402_5%~D
1 2
@
PR304
0_0402_5%~D
1 2
PR307
@
0_0402_5%~D
1 2
PL303
HCB1608KF-121T30_0603
1 2
12
+5V_ALW
RUN_ON<35,47,48,52>
2 2
3 3
+3.3V_ALW
SIO_SLP_S3#<11,19,35,47,48,52>
RUN_ON<35,47,48,52>
4 4
1.8VSP_VIN
PC301
22U_0805_6.3VAM~D
EN_1.8VSP
PR305
@
47K_0402_5%~D
12
PC307
22U_0805_6.3VAM~D
47K_0402_5%~D
12
1.5VSP_VIN
EN_1.5VSP
PR312
@
10
12
@
PC305
0.1U_0402_16V7K~D
12
12
PU301
4
PVIN
PG
9
PVIN
8
SVIN
5
EN
TP
NC
7
11
SYN470DBC_DFN10_3X3
PU302
10
PVIN
9
PVIN
8
SVIN
5
EN
@
PC311
0.1U_0402_16V7K~D
2
1.8VSP_LX
LX
3
LX
6
1.8VSP_FB
FB
NC
1
PR308
470K_0402_5%~D
4
2
LX
PG
3
LX
6
FB
TP
NC
NC
7
1
11
SYN470DBC_DFN10_3X3
12
SNUB_1.8VSP
12
@
12
+3.3V_ALW
1.5V_RUN_PWRGD <48>
1.5VSP_LX
1.5VSP_FB
PL302
1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2
@
20K_0402_1%~D
PR302
4.7_1206_5%~D
10K_0402_1%~D
PC306
680P_0603_50V7K~D
1UH_NRS4018T1R0NDGJ_3.2A_30%
12
@
PR309
SNUB_1.5VSP
12
@
PC312
PR303
PR306
PL304
1 2
15K_0402_1%~D
4.7_1206_5%~D
10K_0402_1%~D
680P_0603_50V7K~D
12
12
PR310
PR313
+1.8V_RUNP
12
PC302
@
12
22P_0402_50V8J~D
12
PC303
22U_0805_6.3VAM~D
<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR303/PR306)=0.6*(1+20K/10K)=1.8V
PC304
22U_0805_6.3VAM~D
@
PJP301
+1.8V_RUNP
1 2
PAD-OPEN 3x3m
+1.8V_RUN
1.5Volt +/-5%
TDC 0.88 A
Peak Current 1.26 A
12
12
PC308
@
22P_0402_50V8J~D
12
12
12
PC310
22U_0805_6.3VAM~D
+1.5V_RUNP
<Vo=1.5V> VFB=0.6V
Vo=VFB*(1+PR310/PR313)=0.6*(1+15K/10K)=1.5V
PC309
22U_0805_6.3VAM~D
@
PJP302
+1.5V_RUNP
1 2
PAD-OPEN 3x3m
+1.5V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
+1.8V_RUN
+1.8V_RUN
+1.8V_RUN
LA-7931
LA-7931
LA-7931
D
56 70Monday, July 23, 2012
56 70Monday, July 23, 2012
56 70Monday, July 23, 2012
1.0
1.0
1.0
of
of
of
Page 57
5
4
3
+V1.05SP_B+
2
@
PJP401
1 2
PAD-OPEN 4x4m
1
+PWR_SRC
12
D D
1.05V_A_PWRGD<49>
PR403
1 2
68.1K_0402_1%~D
PR404
@
0_0402_5%~D
S0 mode be high level
C C
SIO_SLP_A#<19,48,52>
1 2
0.1U_0402_16V7K~D
PC407
@
12
+3.3V_ALW
PR401
470K_0402_5%~D
TRIP_+V1.05SP
EN_+V1.05SP
FB_+V1.05SP
RF_+V1.05SP
12
PR406
470K_0402_5%~D
12
PU401
1
2
3
4
5
4.99K_0402_1%~D
VBST
PGOOD
TRIP
DRVH
EN
SW
V5IN
VFB
DRVL
RF
TPS51212DSCR_SON10_3X3
PR407
TP
12
10
9
8
7
6
11
BST_+V1.05SP
UG_+V1.05SP
SW_+V1.05SP
LG_+V1.05SP
1 2
2.2_0603_5%~D
+5V_ALW
PC408
1U_0603_10V6K~D
PR402
PC405
0.22U_0603_16V7K~D
12
PQ402
FDMC7692S_POWER33-8-5
PC499
1 2
@
56P_0402_50V8J~D
PQ401
FDMC8884_POWER33-8-5
3 5
241
3 5
241
12
SNUB_+V1.05SP
12
12
PC402
PC401
0.1U_0402_25V6K~D
1UH_ETQP3W1R0WFN_11.8A_20%
@
PR405
4.7_1206_5%~D
@
PC409
680P_0603_50V7K~D
PL401
1 2
12
12
PC404
PC403
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
2200P_0402_50V7K~D
+1.05V_MP
1
+
PC406
2
220U_D2_4VM~D
+1.05Volt +/- 5%
PR408
10K_0402_1%~D
1 2
+1.05V_MP
2
PJP402
JUMP_43X118@
112
+1.05V_M
TDC 4.6 A
Peak Current 6.7 A
OCP current 8 A
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
+1.05V_M
+1.05V_M
+1.05V_M
LA-7931
LA-7931
LA-7931
57 70Monday, July 23, 2012
57 70Monday, July 23, 2012
57 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
Page 58
5
4
3
+V1.05S_VCCPP_B+
2
PJP501
@
2
112
JUMP_43X118
1
+PWR_SRC
+3.3V_RUN
12
12
12
D D
1.05V_VTTPWRGD<49,59>
PR503
93.1K_0402_1%~D
1 2
PR504
@
0_0402_5%~D
CPU_VTT_ON<48>
C C
1 2
0.1U_0402_16V7K~D
PC507
@
12
TRIP_+V1.05S_VCCPP
EN_+V1.05S_VCCPP
FB_+V1.05S_VCCPP
RF_+V1.05S_VCCPP
12
PR506
470K_0402_5%~D
12
PR501
470K_0402_5%~D
PU501
1
PGOOD
2
TRIP
3
EN
4
VFB
5
RF
TPS51212DSCR_SON10_3X3
VBST
DRVH
SW
V5IN
DRVL
TP
10
BST_+V1.05S_VCCPP
9
8
7
6
11
UG_+V1.05S_VCCPP
SW_+V1.05S_VCCPP
LG_+V1.05S_VCCPP
PR502
1 2
2.2_0603_5%~D
PC505
0.22U_0603_16V7K~D
12
+5V_ALW
PC506
1U_0603_10V6K~D
FDMC7692S_POWER33-8-5
PC599
1 2
@
56P_0402_50V8J~D
PQ501
FDMC8884_POWER33-8-5
3 5
241
PQ502
3 5
241
PC501
0.1U_0402_25V6K~D
PL501
1UH_ETQP3W1R0WFN_11.8A_20%
1 2
12
@
PR505
4.7_1206_5%~D
SNUB_+V1.05S_VCCPP
@
12
PC509
680P_0603_50V7K~D
PC502
2200P_0402_50V7K~D
12
12
PC503
PC504
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
PC511
.1U_0402_16V7K~D
+1.05VTTP
1
+
PC508
2
330U_2.5V_M
PR508
4.99K_0402_1%~D
12
+3.3V_RUN
12
PR512
PR511
10K_0402_1%~D
1 2
B B
12
PR515
10_0402_1%~D
@
@
71.5K_0402_1%~D
PQ503
@
SSM3K7002FU_SC70-3~D
13
D
2
G
S
12
PR514
10K_0402_5%~D
@
VCCP_PWRCTRL <11>
@
12
PC510
0.1U_0402_16V7K~D
VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB)
VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)
From GPIO
+1.05VTTP
A A
PR509
@
0_0402_5%~D
1 2
PR510
@
0_0402_5%~D
1 2
+1.05Volt +/- 5%
TDC 6.6 A
Peak Current 8.5 A
OCP current 10.2 A
PJP502
2
112
JUMP_43X118@
VTT_SENSE <10>
VSSIO_SENSE_R <10>
+1.05V_RUN_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.05V_RUN_VTT
+1.05V_RUN_VTT
+1.05V_RUN_VTT
LA-7931
LA-7931
LA-7931
58 70Monday, July 23, 2012
58 70Monday, July 23, 2012
58 70Monday, July 23, 2012
1
1.0
1.0
1.0
Page 59
5
4
3
2
1
VID [0] VID[1] VCCSA Vout
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
PR601
D D
PR603
@
0_0402_5%~D
VCCSAPWROK<49>
1 2
PR602
100K_0402_5%~D
+3.3V_RUN
12
+VCCSA_PWRGD+VCCSA_PWRGD
1K_0402_5%~D
PR613
@
0_0402_5%~D
1 2
PR614
@
0_0402_5%~D
1 2
PR604
1K_0402_5%~D
12
VCCSA_VID_1 <11>
VCCSA_VID_0 <11>
12
+5V_ALW
PR605
12
PC618
3300P_0402_50V7K~D
10_0402_1%~D
PU601
19
PGND
20
PGND
21
PGND
22
VIN
23
VIN
24
VIN
12
PC602
2.2U_0603_10V7K~D
1 2
C C
12
12
PC613
+5V_ALW
@
PAD-OPEN 43X118
PJP601
12
PC612
0.1U_0402_25V6K~D
2200P_0402_50V7K~D
GNDA_VCCSA
B B
PC614
10U_0805_25V6K
1 2
PC615
10U_0805_25V6K
1 2
+VCCSA_PWR_SRC
PC617
0.22U_0402_10V6K~D
PC601
1 2
12
1U_0603_10V6K~D
18
17
16
V5FILT
V5DRV
TPS51461RGER_QFN24_4X4~D
GND
VREF
3
1
2
PR612
5.1K_0402_1%~D
12
+VCCSA_EN
14
15
13
EN
VID0
VID1
PGOOD
COMP
SLEW
4
1 2
PC619
0.01U_0402_25V7K~D
12
+VCCSA_BT
BST
11
+VCCSA_PHASE
SW
10
SW
9
SW
8
SW
7
SW
25
TP
VOUT
MODE
5
6
@
33K_0402_5%~D
PR609
PR606
@
0_0402_5%~D
1 2
PR607
1 2
2.2_0603_5%~D
12
+VCCSA_BT_1
12
@
PR608
4.7_1206_5%~D
+VCCSA_SNUB
@
12
PC616
680P_0603_50V7K~D
1.05V_VTTPWRGD <49,58>
PC603
.1U_0603_16V7K~D
1 2
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
PL601
1 2
PC604
PC605
1 2
@
@
22U_0805_6.3V6M~D
0 0 0.9V
0 1 0.8V
1 0 0.725V
1 1 0.675V
output voltage adjustable network
VCCSA
TDC 4.2A
Peak Current 6A
OCP current 7.2A
1 2
22U_0805_6.3V6M~D
12
PC606
0.1U_0402_25V6K~D
PR610
100_0402_5%~D
PR611
@
0_0402_5%~D
1 2
PC608
PC607
1 2
22U_0805_6.3V6M~D
12
1 2
22U_0805_6.3V6M~D
12
PC609
PC610
22U_0805_6.3V6M~D
2200P_0402_50V7K~D
VCCSA_SENSE <11>
PC611
1 2
+VCCSA_P
1 2
22U_0805_6.3V6M~D
@
PJP602
+VCCSA_P
1 2
PAD-OPEN 4x4m
@
PJP603
PAD-OPEN1x1m
+VCC_SA
12
GNDA_VCCSA
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+VCC_SA
+VCC_SA
+VCC_SA
LA-7931
LA-7931
LA-7931
1
59 70Monday, July 23, 2012
59 70Monday, July 23, 2012
59 70Monday, July 23, 2012
1.0
1.0
1.0
of
Page 60
5
VCC_AXG_SENSE<11>
VSS_AXG_SENSE<11>
D D
4
PC703
@
12
330P_0402_50V7K~D
PC706
1 2
0.01U_0402_50V7K
PR702
4.32K_0402_1%~D
PR704
499_0402_1%~D
12
PC704
12
470P_0402_50V7K~D
12
PR701
2K_0402_1%
PR703
267K_0402_1%
3
PC701
330P_0402_50V7K~D
12
PC702
12
150P_0402_50V8F~D
PC705
1 2
68P_0402_50V8J~D
2
12
12
12
PR705
169K_0402_1%~D
VCC_core
TDC 75 A
Peak Current 97A
OCP current 116A
Load line 1.9
1
VSUMG+<61>
VSUMG-<61>
PR714
1 2
3.83K_0402_1%
C C
H_PROCHOT#<7,26,49,62>
+1.05V_RUN_VTT
PR737 54.9_0402_1%
PR743 75_0402_5%@
B B
PR745 130_0402_1%
0.1U_0402_25V6K~D
A A
12
PR706
2.61K_0402_1%
12
PH701
12
10KB_0402_5%_ERTJ0ER103J
PC718
VSUMG-<61>
.1U_0402_16V7K~D
PH702
470K_0402_5%_ TSM0B474J4702RE
12
PR717
27.4K_0402_1%
PR732
@
1 2
0_0402_5%~D
12
SCLK
12
ALERT#
12
SDA
PC740
12
12
12
VIDALERT_N<10>
PR708
11K_0402_1%
VIDSCLK<10>
VIDSOUT<10>
12
PC707
0.1U_0402_10V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
+5V_ALW
12
PC732
43P_0402_50V8J
12
12
PC709
0.015U_0402_16V7K
PC708 0.1U_0402_10V7K~D
12
12
1 2
PR722 0_0402_5%~D@
1 2
PR725 0_0402_5%~D@
1 2
PR727 0_0402_5%~D@
1 2
PR729 0_0402_5%~D@
IMVP_VR_ON<48>
PR733
1 2
3.83K_0402_1%
ISEN1G<61>
ISEN2G<61>
@
1 2
0_0402_5%~D
PC719
PC720
1.05V_0.8V_PWROK<17,49>
+5V_ALW
VSUM+
VSUM-
PR710
@
649_0402_1%~D
1 2
PR712
453_0402_1%~D
1 2
PR720
SCLK
ALERT#
SDA
VR_HOT#
PR730 0_0402_5%~D@
1 2
1 2
PR731 0_0402_5%~D@
12
PH703
470K_0402_5%_ TSM0B474J4702RE
PR735
27.4K_0402_1%
12
@
PC733 10P_0402_25V8J
COMP
PR740 0_0402_5%~D@
1 2
PC738
12
0.22U_0402_6.3V6K
PC739
10KB_0402_5%_ERTJ0ER103J
0.22U_0402_6.3V6K
PC742
0.22U_0402_6.3V6K
12
PR754 11K_0402_1%
12
12
12
PC750
VSUM-
PR753
2.61K_0402_1%
PH704
PC755
.1U_0402_16V7K~D
12
12
12
12
@
3300P_0402_50V7K~D
ISEN1G
ISEN2G
NTCG
VR_EN
NTC
12
12
0.01U_0402_25V7K~D
PC751
@
1 2
649_0402_1%~D
PC711
10
41
0.1U_0402_10V7K~D
PR760
1
2
3
4
5
6
7
8
9
PC752
PU702
ISUMPG
ISEN1G
ISEN2G
NTCG
SCLK
ALERT#
SDA
VR_HOT#
VR_ON
NTC
TP
12
40
11
ISEN3
0.1U_0402_10V7K~D
PR757
604_0402_1%
@
1 2
2200P_0402_25V7K~D
39
ISUMNG
ISEN2
PC756
PR707
@
1 2
IMVP_PWRGD
0_0402_5%~D
PWMG2 <61>
LGATE1G <61>
PHASE1G <61>
UGATE1G <61>
PGOODG
37
35
33
32
31
36
38
34
FBG
RTNG
COMPG
PWM2G
PGOODG
LGATE1G
PHASE1G
UGATE1G
ISEN212FB17ISUMP14ISEN3/FB2
COMP
PGOOD
ISUMN
RTN16ISEN1
18
19
15
13
20
@
PGOOD
COMP
ISEN1
12
BOOT1G <61>
BOOT1G
30
BOOT2
29
UGATE2
28
PHASE2
27
LGATE2
26
VCCP
25
VDD
24
PWM3
23
LGATE1
22
PHASE1
21
UGATE1
BOOT1
ISL95836HRTZ-T_TQFN40_5X5~D
BOOT1
PR734
0_0402_5%~D
1 2
PR736 1.91K_0402_1%
PC735
470P_0402_50V7K~D
PR744
12
499_0402_1%~D
PR748
12
3.48K_0402_1%~D
@
PC749
1 2
330P_0402_50V7K
1 2
PC753 0.01U_0402_50V7K
12
1 2
+5V_ALW
12
PR709
0_0603_5%~D
BOOT2
UGATE2
PHASE2
LGATE2
VCCP
PWM3
LGATE1
PHASE1
UGATE1
IMVP_PWRGD <48>
12
PC736
68P_0402_50V8J~D
PR749
12
267K_0402_1%
PR752
2K_0402_1%
1 2
VCCSENSE <10>
VSSSENSE <10>
12
PC710
1U_0603_10V6K~D
6
7
3
PWM3_1
4
9
ISL6208BCRZ-T_QFN8_2X2
PR713
0_0402_5%~D
@
1 2
1 2
12
PC722
+3.3V_RUN
12
PC741
12
150P_0402_50V8F~D
PC743
680P_0402_50V7K~D
BOOT1
2.2_0603_5%~D
LGATE1
PU701
UGATE
VCC
FCCM
BOOT
PWM
PHASE
LGATE
GND
TP
PR715
@
0_0402_5%~D
12
PC723
1U_0603_10V6K~D
UGATE2
PHASE2
BOOT2
2.2_0603_5%~D
LGATE2
PR750
5.76K_0402_1%
1 2
UGATE1
PHASE1
PR755
1 2
12
PC754
0.22U_0603_16V7K~D
2.2_0603_5%~D
BOOT3
0.22U_0603_16V7K~D
1
UGATE3
2
8
PHASE3
5
LGATE3
LGATE3
+5V_ALW
PR718
1 2
0_0603_5%~D
PR726
12
1_0402_1%~D
1U_0603_10V6K~D
PR738
1 2
12
PC734
0.22U_0603_16V7K~D
PQ705
CSD87351Q5D_SON8~D
2
3
4
PC796
56P_0402_50V8J~D
1 2
@
PR711
12
PC712
1 2
PQ701
CSD87351Q5D_SON8~D
2
3
4
PC792
56P_0402_50V8J~D
1 2
@
PQ703
CSD87351Q5D_SON8~D
2
3
4
PC794
56P_0402_50V8J~D
1 2
@
+VCC_PWR_SRC
1
8
+VCC_PWR_SRC
PQ702
CSD87351Q5D_SON8~D
UGATE3
PHASE3
1
LGATE3
7
6
5
8
+VCC_PWR_SRC
CSD87351Q5D_SON8~D
UGATE2
1
7
6
5
8
PQ706
CSD87351Q5D_SON8~D
2
UGATE1
3
PHASE1
4
LGATE1
7
6
5
1 2
2
3
4
PC791
56P_0402_50V8J~D
1 2
@
PQ704
2
3
PHASE2
4
LGATE2
PC793
56P_0402_50V8J~D
1 2
@
1
PC795
8
56P_0402_50V8J~D
@
+VCC_PWR_SRC
12
1
PC713
10U_0805_25V6K
7
6
5
8
1
PC727
10U_0805_25V6K
7
6
5
8
PR739
12
PC745
PC744
10U_0805_25V6K
10U_0805_25V6K
7
6
5
12
PR756
P1_SNUB
12
PC714
10U_0805_25V6K
12
PR721
P3_SNUB
12
12
12
P2_SNUB
12
12
4.7_1206_5%~D
PC757
680P_0603_50V7K~D
12
PC715
@
10U_0805_25V6K
4.7_1206_5%~D
VSUM+
PC721
680P_0603_50V7K~D
12
PC728
10U_0805_25V6K
ISEN2
4.7_1206_5%~D
10K_0603_1%~D
PC737
VSUM+
680P_0603_50V7K~D
12
PC746
@
10U_0805_25V6K
ISEN1
10K_0603_1%~D
VSUM+
12
12
12
PC716
PC717
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
PL701
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
PR716
1 2
ISEN3
10K_0603_1%~D
PC729
@
10U_0805_25V6K
PR741
1 2
PR746
1 2
3.65K_0603_1%
PR758
1 2
1 2
PR761
3.65K_0603_1%
VSUM-
P3_SW
PR724
1 2
3.65K_0603_1%
VSUM-
1_0402_5%
12
12
12
PC731
PC730
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
P2_SW
PR751
VSUM-
1_0402_5%
12
12
PC748
PC747
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
P1_SW
PR763
1_0402_5%
HCB4532VF-800T90_2P
PL710
1 2
12
PR728
12
1
+
PC724
2
PL702
12
12
PL703
12
12
+PWR_SRC
+VCC_CORE
PR719
@
12
ISEN1
10K_0402_1%~D
PR723
@
12
ISEN2
10K_0402_1%~D
1
+
PC725
2
100U_25V_M~D
100U_25V_M~D
+VCC_CORE
PR742
@
12
ISEN1
10K_0402_1%~D
PR747
@
12
10K_0402_1%~D
+VCC_CORE
PR759
@
12
ISEN2
10K_0402_1%~D
PR762
@
12
ISEN3
10K_0402_1%~D
PC726
ISEN3
1
+
2
100U_25V_M~D
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+VCC_CORE
+VCC_CORE
+VCC_CORE
LA-7931
LA-7931
LA-7931
1
60 70
60 70
60 70
1.0
1.0
1.0
of
Page 61
5
VCC_GFXCORE
TDC 38A
Peak Current 46A
OCP current 57.18A
Load line 3.9
D D
4
3
2
1
+VCC_PWR_SRC
PC761
0.1U_0603_25V7K~D
PL704
12
VSUMG+ <60>
ISEN2G <60>
12
12
PC762
2200P_0402_50V7K~D
+VCC_GFXCORE
PR768 1_0402_5%
12
VSUMG- <60>
PR769 10K_0402_1%~D
1 2
ISEN1G <60>
12
+5V_ALW
12
12
PC763
PR776
PWMG2<60>
C C
0_0603_5%~D
6
7
3
4
9
ISL6208BCRZ-T_QFN8_2X2
PU703
VCC
FCCM
PWM
GND
TP
1U_0603_10V6K~D
UGATE
BOOT
PHASE
LGATE
1
2
8
5
UGATE2G
PR764 4.7_0603_5%~D
BOOT2G
PHASE2G
LGATE2G
PQ707
CSD87351Q5D_SON8~D
12
1 2
PC764
0.22U_0603_16V7K~D
1 2
2
3
4
PC797
56P_0402_50V8J~D
@
1
7
6
5
8
12
PC759
PC758
10U_0805_25V6K
10U_0805_25V6K
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
GP2_SW
12
12
12
PR765
GP2_SNUB
PR767
PR766
4.7_1206_5%~D
12
3.65K_0603_1%
10K_0603_1%~D
PC765
680P_0603_50V7K~D
+VCC_PWR_SRC
12
12
PC766
PQ708
LGATE1G<60>
CSD87351Q5D_SON8~D
2
3
4
PC798
12
56P_0402_50V8J~D
@
1
8
UGATE1G<60>
PHASE1G<60>
B B
BOOT1G<60>
A A
PC771
0.22U_0603_16V7K~D
1 2
12
PR775
4.7_0603_5%~D
PC767
10U_0805_25V6K
10U_0805_25V6K
7
6
5
12
PR770
GP1_SNUB
4.7_1206_5%~D
12
PC772
680P_0603_50V7K~D
12
12
PC769
PC770
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
GP1_SW
PR772
PR771
1 2
1 2
3.65K_0603_1%
10K_0603_1%~D
VSUMG+ <60>
ISEN1G<60>
PL705
12
12
PR773
1_0402_5%
PR774
1 2
10K_0402_1%~D
+VCC_GFXCORE
ISEN2G <60>
VSUMG- <60>
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
+VCC_GFXCORE
+VCC_GFXCORE
+VCC_GFXCORE
LA-7931
LA-7931
LA-7931
1
61 70
61 70
61 70
of
of
1.0
1.0
1.0
Page 62
5
+DC_IN_SS
D D
2 1
PQ901 SI7149DP
5
ES2AA-13-FPD901@
1
2
3
4
PR902
@
0_0402_5%~D
1 2
DC_BLOCK_GC <63>
E2 AC_OK=17.7 Volt
PR913
TI bq24745 = 316K
Intersil ISL88731 = 226K
Maxim = 383K
+SDC_IN
MAX8731A_LDO
11@
PR913
PR914
49.9K_0402_1%~D
PC909
0.01U_0402_25V7K~D
GNDA_CHG
C C
0.1U_0402_10V7K~D
CHARGER_SMBCLK<49>
CHARGER_SMBDAT<49>
Vref
TI bq24747 = 3.3V
Intersil ISL88731C = 3.2V
VDDP
TI bq24747 = 6V
Intersil ISL88731C = 5.1V
1 2
226K_0402_1%~D
12
+5V_ALW
PC916
ACAV_IN<16,25,49,63>
12
GNDA_CHG
MAX8731_IINP<25>
12
MAX8731_REF
12
PR911
11@
PR912
22@
10K_0402_1%~D
10K_0402_5%~D
12
11@
PR916
15.8K_0402_1%~D
12
PR925
@
8.45K_0402_1%~D
+CHGR_DC_IN<63>
12
PR915
@
0_0402_5%~D
1 2
1 2
PR920
22@
200K_0402_5%~D
12
PR922
PC921
22@
4.7K_0402_5%~D
120P_0402_50VNPO~D
1 2
12
12
PC922
PC923
22@
11@
220P_0402_50V8J~D
0.01U_0402_25V7K~D
Maximum charging current is 7.2A
DYN_TUR_CURRENT_SET#
B B
150W
180W
DYN_TUR_CURRNT_SET#9>
A A
High
Low
2
G
PR943
12
287K_0402_1%
13
D
S
12
12
PR944
121K_0402_1%~D
SSM3K7002FU_SC70-3~D
+3.3V_ALW2
PR937
100K_0402_1%~D
12
PC941
100P_0402_50V8J~D
PQ909
MAX8731_IINP
+5V_ALW
PR939
20K_0402_1%~D
1 2
12
PC940
220P_0402_50V8J~D
Adapter Protection Circuit for Turbo Mode
CSS_GC<63>
+DOCK_PWR_BAR
+DC_IN_SS
PC920
22@
12
PC926
PC927
@
11@
0.01U_0402_25V7K~D
12
PC936
@
100P_0402_50V8J~D
4
PD902
2
3
BAT54CW_SOT323~D
PR909
@
1 2
1_0805_5%~D
GNDA_CHG
PC918
22@
12
2200P_0402_50V7K~D
1 2
56P_0402_50V8~D
12
PC924
22@
1U_0603_10V6K~D
0.01U_0402_25V7K~D
12
PC937
@
0.01U_0402_25V7K~D
5
+
6
-
+SDC_IN
PR903
@
0_0402_5%~D
1 2
1
PC907
0.1U_0805_50V7M~D
22@
1 2
7.5K_0402_5%~D
MAX8731_REF
PR924
22@
1 2
10K_0402_5%~D
12
GNDA_CHG
PR936
1.8M_0402_1%
1 2
8
PU902B
P
7
O
G
LM393DR_SO8~D
4
<26>
@
12
NTR4502PT1G_SOT23-3~D
0.1U_0402_25V6K~D
GNDA_CHG
12
+DCIN
MAX8731_IINP
PR921
12
PC928
@
0.1U_0402_10V7K~D
+5V_ALW
PR931
Iada=0~9.23A(180W)
1
2
EMC1700_SENSE_P
PC901
0.1U_0603_25V7K~D
13
D
2
G
PQ903
S
CSSP_1
100K_0402_5%~D
11@
12
PR905
10_0402_5%~D
PC904
1 2
1 2
11@
0.047U_0402_25V7K~D
1
PU901
22
DCIN
2
ACIN
13
ACOK
11
VDDSMB
10
SCL
9
SDA
14
NC
8
VICM
6
FBO
5
EAI
4
EAO
3
VREF
7
CE
12
GND
29
TP
ISL88731C_QFN28_5X5~D
11@
PR935
0_0402_5%~D
@
221K_0402_1%~D
1 2
61
2
DMN66D0LDW-7 2N_SOT363-6~D
ICREF
PQ908A
PR901
0.01_2512_1%~D
2
G
PR904
12
11@
PC905
1 2
27
28
ICOUT
CSSP
CSSN
BOOT
VDDP
UGATE
PHASE
LGATE
PGND
CSOP
CSON
3
4
3
EMC1700_SENSE_N<26>
13
D
PQ902
NTR4502PT1G_SOT23-3~D
S
CSSN_1
12
PR906
PR907
10_0402_5%~D
11@
100K_0402_1%~D
PC906
1 2
0.1U_0402_25V6K~D
ICOUT
26
PR917
2.2_0603_1%~D
25
1 2
BOOT
21
MAX8731A_LDO
24
PR919
11@
23
0_0603_5%~D
12
@
220P_0402_50V7K~D
20
19
18
17
15
1 2
VFB
VFB
16
NC
1 2
GNDA_CHG
H_PROCHOT# <7,26,49,60>
3
5
PQ908B
4
DMN66D0LDW-7 2N_SOT363-6~D
+PWR_SRC
PQ904A
SI3993CD
S
G
1
12
GNDA_CHG
11@
4.7_0603_5%~D
PC910
0.1U_0603_25V7K~D
12
PC917
PR926
100_0402_5%~D
PJP902
PAD-OPEN1x1m
PL901
1UH_PCMB053T-1R0MS_7A_20%
D
65
PQ904B
SI3993CD
S
12
G
3
@
PR908
100K_0402_1%~D
PR918
BOOT_D
12
1 2
12
PD903
PC911
22@
1 2
1U_0603_10V6K~D
BAT54HT1G_SOD323-2~D
CHG_UGATE
+VCHGR_B
CHG_LGATE
+VCHGR
MAX8731_REF
+DC_IN
PR932
232K_0402_1%~D
12
PR940
PC938
22.6K_0402_1%~D
100P_0402_50V8J~D
12
D
42
PR910
0_0402_5%~D
1 2
12
PC908
11@
1U_0603_10V6K~D
GNDA_CHG
PC919
@
3300P_0402_50V7K~D
PC999
@
56P_0402_50V8J~D
12
12
PR933
47K_0402_1%~D
12
12
PR941
42.2K_0402_1%~D
+3.3V_ALW
5
PU903
P
B
4
O
A
G
3
74AHC1G08GW AND~D
12
12
PC902
PC903
@
0.1U_0603_25V7K~D
47P_0402_50V8J~D
DK_CSS_GC <63>
5
PQ905
SIR472DP-T1-GE3_POWERPAK8-5
4
123
12
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
PQ906
5
4
123
1 2
PR930
1M_0402_1%~D
1 2
+5V_ALW
8
3
+
2
-
4
12
PC939
100P_0402_50V8J~D
PC942
0.1U_0402_25V4Z~D
12
1
2
PROCHOT_GATE <48>
To preset system to throtlle
switching from AC to DC
DOCK_DCIN_IS+ <46>
4.7_1206_5%~D
CHG_SNUB
1 2
12
1000P_0603_50V7K~D
SI7716ADN-T1-GE3_POWERPAK8-5
PU902A
P
1
O
G
LM393DR_SO8~D
PR945
100K_0402_5%~D
PQ910
2
+CHAGER_SRC
DOCK_DCIN_IS- <46>
PL902
PR929
PC925
PC933
22@
0.1U_0402_25V6K~D
1 2
GNDA_CHG
+3.3V_ALW
12
13
D
2
G
S
SSM3K7002FU_SC70-3~D
12
PC912
PC913
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
PR923
0.01_1206_1%~D
12
4
+VCHGR_L
3
12
PR927
11@
10_0402_5%~D
1 2
PC934
0.22U_0603_25V7K~D
11@
MAX8731_REF
12
PR934
10K_0402_1%~D
@
0_0402_5%~D
1 2
12
PR942
@
41.2K_0402_1%~D
ACAV_IN <16,25,49,63>
12
0_0402_5%
PR938
1
12
12
PC915
PC914
10U_0805_25V6K
10U_0805_25V6K
+VCHGR
1
2
12
PR928
PC929
@
0.1U_0603_25V7K~D
1 2
PC935
0.1U_0402_25V6K~D@
12
PC930
12
PC931
10U_0805_25V6K
GNDA_CHG
ACAV_IN_NB <48,49,63>
12
12
PC932
10U_0805_25V6K
10U_0805_25V6K
BQ24747
22@
PR913
22@
316k_0402_1%
PC934
22@
0.1U_0603_25V6
5
PR927
22@PU901
0_0402_5%
PR905
0_0402_5%
PR906
0_0402_5%
22@
PC905
0.1U_0402_25V6
4
22@
PR919
22@
22@
1 +-5% 0603
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Charger
Charger
Charger
LA-7931
LA-7931
LA-7931
1
62 70Monday, July 23, 2012
62 70Monday, July 23, 2012
62 70Monday, July 23, 2012
of
of
of
1.0
1.0
1.0
Page 63
5
+DOCK_PWR_BAR
D D
PQ1002
SI4835DDY-T1-E3_SO8~D
8
+VCHGR
C C
+DC_IN
PR1013 100K_0402_5%~D
+3.3V_ALW2
B B
A A
1 2
ACAV_DOCK_SRC#<46> DOCK_AC_OFF <46,48>
+SDC_IN
PR1015 0_0402_5%~D@
ACAV_IN<16,25,49,62>
+3.3V_ALW2
7
5
+DOCK_PWR_BAR
+DC_IN_SS
1 2
PR1011 47_0805_5%~D
SOFT_START_GC<53>
@
1 2
1 2
DC_BLOCK_GC<62>
PR1021
@
1 2
PR1022
@
0_0402_5%~D
1 2
5
0.1U_0603_50V4Z~D
PR1017
0_0402_5%~D
CD3301_SDC_IN
0_0402_5%~D
4
@
PR1007
@
0_0402_5%~D
1 2
1 2
PR1010 0_0402_5%~D@
+CHGR_DC_IN<62>
CD3301_DCIN
PC1006
ACAVDK_SRC
PC1007
0.1U_0603_25V7K~D
1
2
36
PR1006
0_0402_5%~D
1 2
12
ERC1
12
ACAVIN
P33ALW2
BLK_MOSFET_GC
DK_PWR_BAR
3301_DC_IN_SS
PU1001
1
DC_IN
2
SS_GC
3
ERC1
4
ACAVDK_SRC
5
GND
6
SDC_IN
7
DC_BLK_GC
8
ACAV_IN
9
P33ALW2
37
TP
CSS_GC<62>
DK_CSS_GC<62>
PC1008
PBATT+
33
35
36
34
NC
DC_IN_SS
CHARGERVR_DCIN
CSS_GC10DK_CSS_GC11ERC312ERC213GND14PWR_SRC
ERC3
ERC2
12
12
PC1009
@
0.1U_0402_25V4Z~D
0.047U_0603_25V7K~D
4
0_0402_5%~D
1 2
DSCHRG_MOSFET_GC
30
29
32
31
28
NC
GND
PBatt+
DK_PWRBAR
PBATT_OFF
BLK_MOSFET_GC
DK_AC_OFF_EN
ACAV_IN_NB
DSCHRG_MOSFET_GC
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS
SS_DCBLK_GC
EN_DK_PWRBAR17P33ALW
16
15
18
P33ALW
EN_DK_PWRBAR
STSTART_DCBLOCK_GC
3301_PWRSRC
4
PR1004
PR1008
0_0402_5%~D
@
P50ALW
GND
CD3301ARHHR
@
@
12
12
27
26
25
24
23
22
21
20
19
PR1025
@
0_0402_5%~D
1 2
PR1027
@
0_0402_5%~D
1 2
PR1029
0_0402_5%~D
1 2
PQ1003SI7149DP
1
2
3
4
PC1004
1U_0805_25V4Z~D
P50ALW
CD_PBATT_OFF
DK_AC_OFF
3301_ACAV_IN_NB
DK_AC_OFF_EN
SL_BAT_PRES#
12
5
PR1012
@
0_0402_5%~D
1 2
PR1016
@
0_0402_5%~D
1 2
PR1014
@
0_0402_5%~D
1 2
@
+3.3V_ALW
EN_DOCK_PWR_BAR <48>
1 2
1M_0402_5%~D
PR1028
@
+PWR_SRC
PR1001
330K_0402_5%~D
PBATT_IN_SS
+5V_ALW
SLICE_BAT_ON <48>
PR1019
@
0_0402_5%~D
1 2
BLKNG_MOSFET_GC
PR1023
@
0_0402_5%~D
1 2
PR1024
0_0402_5%~D
1 2
3
PD1001
2
3
PQ907 SI7149DP
5
1
PDS5100H-13_POWERDI5-3~D
1
2
3
4
PR1003
330K_0402_5%~D
1 2
12
PR1005
1K_1206_5%~D
12
PC1005
1U_0603_25V6-K~D
12
PC1001
0.47U_0805_25V7K~D
PR1002
0_0402_5%~D
2
@
12
STSTART_DCBLOCK_GC
2
3
PQ1004 SI7149DP
5
PD1002
PDS5100H-13_POWERDI5-3~D
GPIOInputfromNB
EmbeddedController
1 2
1 2
PR1020 0_0402_5%~D@
+NBDOCK_DC_IN_SS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
ACAV_IN_NB <48,49,62>
DOCK_AC_OFF_EC <48>
SLICE_BAT_PRES# <46,48,53>
1M_0402_5%~D
PR1018
2
1
1
1
2
3
4
12
@
0_0402_5%~D
PR1009
12
PC1002
2200P_0402_50V7K~D
+PWR_SRC
12
PC1003
0.1U_0603_25V7K~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Selector
Selector
Selector
LA-7931
LA-7931
LA-7931
63 70Monday, July 23, 2012
63 70Monday, July 23, 2012
63 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
Page 64
5
4
3
2
1
+VCC_CORE
1
PC1101
10U_0805_6.3VAM~D
2
D D
1
PC1106
10U_0805_6.3VAM~D
2
1
PC1102
10U_0805_6.3VAM~D
2
1
PC1107
10U_0805_6.3VAM~D
2
@
1
PC1148
10U_0805_6.3VAM~D
2
1
PC1108
10U_0805_6.3VAM~D
2
1
PC1104
10U_0805_6.3VAM~D
2
1
PC1109
10U_0805_6.3VAM~D
2
+VCC_CORE +VCC_GFXCORE
1
PC1105
10U_0805_6.3VAM~D
2
1
PC1110
10U_0805_6.3VAM~D
2
1
PC1111
10U_0805_6.3VAM~D
2
+VCC_GFXCORE
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
PC1113
PC1112
1
1
2
1
2
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
PC1114
PC1115
1
2
22U_0805_6.3V6M~D
PC1116
1
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
@
PC1118
PC1117
1
1
2
2
+VCC_CORE
PC1120
22U_0805_6.3V6M~D
1 2
PC1144
22U_0805_6.3V6M~D
1 2
C C
PC1161
22U_0805_6.3V6M~D
1 2
PC1169
22U_0805_6.3V6M~D
1 2
PC1121
22U_0805_6.3V6M~D
1 2
PC1145
22U_0805_6.3V6M~D
1 2
PC1162
22U_0805_6.3V6M~D
1 2
PC1170
22U_0805_6.3V6M~D
1 2
PC1122
22U_0805_6.3V6M~D
1 2
PC1146
22U_0805_6.3V6M~D
1 2
PC1163
22U_0805_6.3V6M~D
1 2
PC1123
22U_0805_6.3V6M~D
1 2
PC1147
22U_0805_6.3V6M~D
1 2
PC1164
22U_0805_6.3V6M~D
1 2
PC1124
22U_0805_6.3V6M~D
1 2
PC1103
@
22U_0805_6.3V6M~D
1 2
PC1165
22U_0805_6.3V6M~D
1 2
22U_0805_6.3V6M~D
PC1136
1
2
1
@
+
PC1157
2
470U_D2_2VM_R4.5M
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
PC1137
1
2
1
+
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
PC1138
1
2
PC1158
PC1139
1
2
1
+
PC1119
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
22U_0805_6.3V6M~D
PC1140
1
2
PC1141
1
2
Below is 458544_CRV_PDDG_0.5 Table 5-8.
5 x 22 µF (0805)
Socket Bottom
5 x (0805) no-stuff
sites
7 x 22 µF (0805)
Socket Top
2 x (0805) no-stuff
sites
+1.05V_RUN_VTT
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
1
2
PC1126
PC1125
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
@
@
1
1
2
PC1128
PC1127
2
22U_0805_6.3V6M~D
1
PC1149
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
@
1
1
2
1
2
PC1130
PC1129
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
PC1150
PC1151
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
1
2
22U_0805_6.3V6M~D
1
2
1
PC1132
PC1131
2
2
22U_0805_6.3V6M~D
1
1
@
PC1152
PC1153
2
2
1
+
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
PC1133
22U_0805_6.3V6M~D
PC1154
330U_X_2VM_R6M~D
PC1166
22U_0805_6.3V6M~D
1
1
@
PC1134
PC1135
2
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
1
@
PC1155
PC1156
2
2
330U_X_2VM_R6M~D
330U_X_2VM_R6M~D
1
1
+
2
PC1168
PC1167
+
2
+VCC_CORE
1
+
B B
A A
PC1173
2
470U_D2_2VM_R4.5M
@
1
+
PC1177
2
470U_D2_2VM_R4.5M
1
+
PC1174
2
470U_D2_2VM_R4.5M
@
1
+
PC1178
2
470U_D2_2VM_R4.5M
1
+
PC1175
2
470U_D2_2VM_R4.5M
1
+
PC1176
2
470U_D2_2VM_R4.5M
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
LA-7931
LA-7931
LA-7931
64 70Monday, July 23, 2012
64 70Monday, July 23, 2012
64 70Monday, July 23, 2012
1
1.0
1.0
1.0
Page 65
5
4
3
2
1
Version Change List ( P. I . R. List )
Page 1
Request
Item Issue DescriptionDate
Ow n er
1 PWR62 10/11 Intersil Remove Docking current sense voltage division Remove PR946、PR948 and PR947 X01
2 Change RTC battery connectorCompal10/14PWR53 X01Change to SP02000RO00
D D
3 Add control singnal to control S5 power consumptionCompal10/14PWR53 X01Add PR23 to connect PCH_ALW_ON singal
4 Change H_PROCHOT# voltage source of Compare reference Compal10/14PWR62 X01PR937 connect to 2VREF_6182
5 Change PQ5 Package for layout space Compal10/25PWR53 X01Change footprint from TO252 to SO8_5P
6 Change PC707 PC751 footprint from 0603 to 0402Compal11/01PWR60 X01Change PC707 PC751 footprint to 0402
7 Remove PJP702Compal11/01PWR61 Remove PJP702 X01
8 Low side MOSFET Gate induce voltageCompal11/07PWR54,55,57,58
,60,61,62
Reserve PC198,PC199,PC299,PC499,PC599,PC791,PC792,
PC793,PC794,PC795,PC796,PC797,PC798,PC999
9 Reserve 10u and 0.1u Cap with MXM_pwr_src Compal11/07PWR53 Reserve PC30 and PC31 X01
10 Reserve PD7 for ESD requirement Compal03/01PWR53 Reserve PD7 X03
11 Change 0 Ω footprint to R0402_0ohmCompal04/03PWR53,54,55,
56,57,58,
59,59,60,
61,62,63
PR1002,PR1004,PR1006,PR1007,PR1008,PR1009,PR1010,PR1012,
PR1014,PR1015,PR1016,PR1017,PR1019,PR1020,PR1021,PR1022,
PR1023,PR1024,PR1025,PR1027,PR1029,PR105,PR118,PR206,
PR214,PR226,PR23,PR307,PR311,PR404,PR504,PR509,PR510,PR6,
PR603,PR606,PR611,PR613,PR614,PR713,PR722,PR725,PR727,
PR729,PR731,PR734,PR902,PR903,PR910,PR915,PR935,PR938
12 Change PL601 Footprint for DFB issueCompalPWR59 Change PL601 footrpint to TAI-T_VMPI0703AR-1R0M-Z01_2P X0604/03
C C
13 PWR Compal Battery ESD protect with ESD diodie53 PD3.3 connect with PBATT1.7 X0604/03
14 Remove jump of co-lay with input chokeCompalPWR54,62 X06Remove PJP901 and PJP10104/03
Change PL710 Footprint for DFB issueCompalPWR6015 X07Change PL701 footrpint to KC_FBMA-L11-453215-121LMA90T_205/04
Change 0 Ω footprint to R0402_0ohm16 PR928Compal05/14PWR60 X07
Sol u t i o n D esc r i p t i on Rev.Page# Ti t l e
X01
X06
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 1
PWR_PIR 1
PWR_PIR 1
LA-7931
LA-7931
LA-7931
65 70Monday, July 23, 2012
65 70Monday, July 23, 2012
65 70Monday, July 23, 2012
1
1.0
1.0
1.0
Page 66
5
4
3
2
1
Version Change List ( P. I. R. List )
Page 1
Request
Item Issue DescriptionDate
Ow n er
1 16 HW 2011/09/01 COMPAL correct MXM LVDS signals. Swap CHA and CHB signals on JMXM1. 0.2(X00)
D D
2 51 HW 2011/09/01 COMPAL Add current limilt R for Breath LED. Add R956(374ohm). 0.2(X00)
3 46 HW 2011/09/04 COMPAL for layout routing easy.
4 51 HW 2011/09/06 Lite-on to meet LED min workable current(2mA).
Move D33,C702,CE6 from JDOCK1.146~148 to JDOCK1.149~151.
JDOCK1.146~148 change to dummy pin.
Change R934,R939,R942,R955,R941 from 2.2kohm to 1.2kohm.
R943 from 2.2kohm to 374ohm.
5 27 HW 2011/09/06 COMPAL Add MXM DDC signals pull up R. pop R1121,R1122. 0.2(X00)
6 45 HW 2011/09/09 COMPAL Add DOCK DP DDC signals control circuit. Add R2144~R2157,C1331,C1332,Q333~Q336,R2161~R2164,Q337. 0.3(X01)
7 41 HW 2011/09/14 COMPAL
modify JUSH1 pin define for meeting USH/B JUSH1 pin
define change.
change JUSH1 pin define. 0.3(X01)
8 50 HW 2011/09/19 COMPAL modify JBT1 pin define for meeting BT connector change. Swap JBT1 pin1~pin12 pin define to pin12~pin1. 0.3(X01)
9 46,28,50 ME 2011/09/27 COMPAL Change connector follow connector list 0913A. Change JDOCK1 to WD2F144WB5R400,JLVDS1 to 50398-04071-001,JBT1 to
50450-0127N-001.
10 52 HW 2011/09/27 COMPAL +3.3V_RUN boot leakage. Pop R929,Q69. 0.3(X01)
11 20,48,28 HW 2011/09/28 DELL Drop touch panel. Remove net "USBP13-,USBP13+,TOUCH_SCREEN_PD#" and L11,R429,R430,D86,R419,
C C
12 46 HW 2011/09/28 COMPAL Add pull-down R for DPC_GPU_HPD. Add R773(100K ohm). 0.3(X01)
13
14
15
16
34 HW
52 HW 2011/09/29 COMPAL Solve S4/S5 +MXM_PWR_SRC leakage in DC mode. Change R940 pin1 connect from +PWR_SRC_S to +PWR_SRC_MXM. 0.3(X01)
49,17,18 HW 2011/10/04 COMPAL Crystal EA.
17 HW 2011/10/12 COMPAL Debug component control for pop them until ST. Add JTAG@ for RH288,RH59,RH44,RH45,RH43,RH47~RH49. 0.3(X01)
17 48 HW 2011/10/12 COMPAL 0.3(X01)
18 51 HW 2011/10/12 COMPAL 0.3(X01)
19
20
B B
21 0.3(X01)50 HW 2011/10/13 COMPAL
22 0.3(X01)
28 HW 2011/10/12 COMPAL 0.3(X01)
34 HW 2011/10/12 COMPAL 0.3(X01)
14 ME 2011/10/13 COMPAL
38 HW23 2011/10/19 COMPAL
24 22 HW 2011/10/19 COMPAL
25 40 HW 2011/10/25 COMPAL
26 34 HW 2011/10/25 COMPAL
27 51 HW 2011/10/25 COMPAL
28 38,51 HW 2011/10/26 COMPAL
29 41 HW 2011/10/26 COMPAL TPM chip to new version chip due to OS Win8 supported
30 51 ME 2011/10/26 COMPAL screw hole change follow 1021A ME drawing. Change H5 to 3P2X6P2 and H18,H19,H23,H24 to 4P1.
31 51 HW 2011/10/28 COMPAL Solve Breath LED flicker when AC-in plug,follow E4
32 52 HW 2011/10/28 COMPAL For Inrush current issue. Change C1274 from 470pF to 2200pF for meeting OCP.
A A
2011/09/29 COMPAL Change the R518 value to meet the PS8336B input
high-level voltage.
Wireless switch needs to be pulled to ALW, Without it
being pulled to ALW rail AOAC will work incorrect.
Solve Breath LED flicker when AC-in plug and correct
Breath LED top and side view work behavior.
JLVDS1 connector change,then GND shield shift(different
from original).because JLVDS1 and JLVDS2 co-lay,we need
change pin define.
Choice DDC active buffer mode.and control switching Mode. Pop R68 and non-pop R58.
To meet intel spec: T235(power off)= min 40ns).
T08a(power on)= max 90ms.
Change connector follow connector list 1005A. Change JDIMM3 to 2-2013310-1.
LAN EA. Change T156 to SP050006P0L.
for solving dispaly ripples. 1/2 Change LH1 to 4.7uH inductor.
NEC_TOKIN shortage issue for the flood in Tailand. Change C323,C324 to SGA0000370L(Panasonic).
HDMI EA. pop R451~R456,R458,R459 and non-pop L19,L23,L24,L25.
improve BT_LED behaviour abnormal(BT_LED must dark)
in S3/S4/S5.
for ESD Hi-Pot fail. change JLOM1 "pin14 and pin15" from "GND_CHASSIS1 and GND_CHASSIS" to GND.
problem
solution.
JTS1.
Change R518 from 100k to 10kohm. 0.3(X01)
Change C743,C741 from 22pF to 39pF, CH2,CH3 from 15pF to 18pF,
CH18,CH19 from 12pF to 10pF.
Add R2158 let WIRELESS_ON#/OFF pull up to ALW, no stuff R766
Add Q327 and use"MASK_BASE_LEDS#" to control Breath LED top view.
use"SYS_LED_MASK#" to control Breath LED side view.
JLVDS2 pin41,42 change to EDP_LVDS_A3-,EDP_LVDS_A3+, pin43~pin46 change
to GND.
change U4 from RT9801AGE to RT9818A-44GU3,R1622 to 100kohm.add R2159.
remove R2129~R2134. pop R2142 and non-pop R1623.
change R938 PU from +3.3V_RUN to +3.3V_ALW.
change H5 to NPTH.
Change U39 TPM solution to new p/n: SA00004WQ10
Remove Q327 and modify EC code from PWM Output to GPIO input on ECE5048
(GPIOM3/PWM4).
Sol u t i o n D esc r i p t i on Rev.Page# Ti t l e
0.2(X00)
0.2(X00)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE_PIR 1
EE_PIR 1
EE_PIR 1
LA-7931P
LA-7931P
LA-7931P
66 70Monday, July 23, 2012
66 70Monday, July 23, 2012
66 70Monday, July 23, 2012
1
1.0
1.0
1.0
Page 67
5
4
3
2
1
Version Change List ( P. I. R. List )
Page 2
Request
Item Issue DescriptionDate
33 52 HW 2011/10/28 COMPAL For smart card detect issue.
D D
34 14 HW 2011/10/28 COMPAL For DFX issue.
35 47,46,32
40,29
HW 2011/10/28 COMPAL For ESD request.
Ow n er
Change C767 from 4700pF to 470pF for turning proper +3.3V_SUS timing
begin to +3.3V_RUN.
Change CD45 from 0603 size to 0402 for easy move to keep away battery
connector.
Change D97,D33,D91,D92 to non-pop. D14,D16 change main source(SC30000250L)
to SC300002F0L and D88,D89 change main source(SCA00000T0L) to SC300002F0L.
36 46 HW 2011/10/31 COMPAL EMI request,add 33ohm for DOCK DVI signals. Add R2160,R2165~R2179(33ohm) for DOCK DVI port A,B.
37 34 HW 2011/10/31 COMPAL EMI request,add reserve C(3.3pF) for HDMI signals. Add reserve C1333~C1340(3.3pF) for HDMI signals.
38 21 HW 2011/11/2 COMPAL PCH has internal pull up 20k ohm on (GPIO27) No stuff RH175
39 21 HW 2011/11/2 COMPAL Power saving RH362 change from 10K to 100K
40 22 HW 2011/11/2 COMPAL
41 49 HW 2011/11/2 COMPAL
42 52 HW 2011/11/2 COMPAL
43 33,46 HW 2011/11/2 COMPAL
44 45 HW 2011/11/3 COMPAL
45 16 HW 2011/11/3 COMPAL
46 49 HW 2011/11/3 COMPAL
C C
47 32 LAYOUT 2011/11/7 COMPAL
48 33 HW 2011/11/7 COMPAL
49 40 HW 2011/11/7 Parade
50 30 HW 2011/11/8 H.ELE
for solving dispaly ripples. 2/2 Change CH36 to 22uF_0805 size.
Change board ID to X01 Change R875 to 130K
Power saving R935 change from 20K to 100K
reduce layout via. MXM DP lane for Docking direct connect to JDOCK1.
remove double pull low R. remove R2144,R2154.
only 10-bits panel use. change R2095,R2096 to 6@ group.
SMBUS EA. change R838,R841 to 2Kohm for rise timing fail.
Add TEST point for JCRT PIN11. Add CRT_11 net and test point(T61) for JCRT1.11.
Add space for easy to layout. Remove R2081~R2088 and remove Net DPC_DOCK_LANE_P0~P3,DPC_DOCK_LANE_N0~N3.
USB3.0 EA fine tune(TX:EQ-->9.5dB,DE-->3.5dB;
RX:EQ-->7.5dB,DE-->5dB).
Vender suggested changed small size from 5.0*3.2mm to
3.2*2.5mm.
pop R22,R18,R30,R28 and change R2141 from 4.99kohm to 4.7kohm.
Change Y7 from SJ100006R00 to SJ10000CZ0L, C1225 from 10pF to 15pF,
C1226 from 10pF to 12pF.
51 30 HW 2011/11/9 compal for satisfy ME space limilt. Change C324 size from D2 to B2. 0.3(X01)
52 46 HW 2011/11/10 COMPAL Just reserve R for EMI team to test DOCK DVI signals. Change R2160,R2165~R2179 to 0ohm for DOCK DVI port A,B.
53 40 HW 2011/12/30 COMPAL sourcer request change USB PWR SW from TPS2560 (U45) to G547I2P81U (U642, U643)
54 Swap USB signal from port 8 to port 4 on JDOCK1.66 & JDOCK1.68EMI issue.COMPAL2011/12/30EMI46
55 Swap USB signal from port 4 to port 8 on JMINI1.36 & JMINI1.38EMI issue.COMPAL2011/12/30EMI42
56 add R2180 ~ R2184, R2189 ~ R2193 for SATA redriver(U26, U637) 2nd source
57 add R2185, R2186, D103 to SP_TPM_LPC_EN.Solve +3.3V_RUN Giltch in S5 when AC plugging in.COMPAL2012/01/02HW41
B B
2nd source.COMPAL2011/12/30HW35
and change R1206 from4.99K ohm to 5.1K ohm.
58 add R2187, R2188 on AUX signal.Prevent AUX swing overshoot.COMPAL2012/01/02HW30
59
COMPAL2012/01/02HW52
+3.3V_RUN.
60
change C1274 from 2200P to 3300P, and No stuff R2127Power sequencing meet 0.7V between +PCH_V5REF_RUN and
stuff R58.HDMI no voice issueCOMPAL2012/01/02HW34
61 2012/01/03 COMPAL Setup Volume mute LED control same as Volume up & down No stuff Q84B51 HW
62 2012/01/03 COMPAL EMI request add 33ohm for DOCK DVI signals. change R2160, R2165 ~ R2179 from 0 ohm to 33 ohm.46 HW
63 2012/01/03 COMPAL EMI request for HDMI. stuff L19, L23, L24, L25, No stuff R451~R456, R458, R45934 HW
64 2012/01/03 COMPAL change CAP from 3.3P to 12P (C12, C13, C21), and stuff.32 HW
EMI request for CRT.
Sol u t i o n D esc r i p t i on Rev.Page# Ti t l e
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
65 2012/01/03 COMPAL stuff L10, No stuff R427, R42828 HW
66 30,31 HW 2012/01/04 COMPAL RGB panel sequencing issue. change power rail from +3.3V_RUN to+3.3V_AVDD on R2039.1, R2040.1,
A A
EMI request for Webcam.
R2038.1, C1227.1, U631.3
Remove C1269, C1270
add L57
0.4(X01)
0.4(X01)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE_PIR 2
EE_PIR 2
EE_PIR 2
LA-7931P
LA-7931P
LA-7931P
67 70Monday, July 23, 2012
67 70Monday, July 23, 2012
67 70Monday, July 23, 2012
1
1.0
1.0
1.0
Page 68
5
4
3
2
1
Version Change List ( P. I. R. List )
Page 3
Request
Item Issue DescriptionDate
Ow n er
67 16 HW 2012/01/04 COMPAL Height limitation issue. change cap from SE142106M8L(1206) to SE00000QK0L(0805)
D D
68 40 HW 2012/01/05 COMPAL change main source. change main source from SLG55584A to MAX14618 on U2.
69 33 HW 2012/01/05 COMPAL Remove DMC function. Remove U14, R329~R335, R337, R338, R342~R345, R2091, R2092, C396,
C399~C401, C267, C269, C273~C278.
70 42 HW 2012/01/05 COMPAL Remove DMC function. Remove JMINI1, R493.
71 51 ME 2012/01/09 COMPAL update ME drawing. Remove H3.
72 40 ME 2012/01/09 COMPAL update ME drawing. change JUSB1, JUSB2 from FOX_UEA111Y1-C5BDA-7H to FOX_UEA111Y1-C1BD1-7H
73 17 ME 2012/01/09 COMPAL update ME drawing. change JSPI1 from HRS_FH12-16S-0P5SH(55)~D to TYCO_1-2041070-6~D.
74 25 ME 2012/01/09 COMPAL update ME drawing. change JFAN1, JFAN2 from ACES_50228-0047N-001 to ACES_50450-0067N-001.
75 30 HW 2012/01/10 COMPAL prevent current leakage. Change Pull up +3.3V_RUN to +3.3V_AVDD on R2036 and R2037.
76 49 HW 2012/01/10 COMPAL change Board ID to X02. change R875 to 62K ohm.
77 33 HW 2012/01/10 COMPAL prevent material shortage for Thai flood. change material from TC7SET04FU to NC7ST04P5X on U636.
C C
78 28 HW 2012/01/10 COMPAL prevent material shortage for Thai flood. change material from TC7SET04FU to M74VHC1GT125DF2G on U3.
79 19,20,25,
37,49,50,
51
80 35,43 HW 2012/01/10 COMPAL add X76 option for main source and 2nd source of SATA
HW 2012/01/10 COMPAL prevent material shortage for Thai flood. change material from TC7SH08FU to 74AHC1G08GW on U7, U10, U15, U50, U58,
redriver .
UC4, UH3.
add X761@ on R1201, R1202, R1206, R2136, R2139, R2140.
add X762@ on R2180 ~ R2184, R2189 ~ R2193.
81 25 HW 2012/01/11 COMPAL layout routing swap. change FAN conn from 4 pin to 6 pin, and swap pin 1, pin6 for JFAN1, JFAN2.
82 16 HW 2012/01/11 COMPAL For NVDIA request. add R2194, R2195 (No stuff) and pull up to +3.3V_MXM on JMXM1B.268,
JMXM1B.270
83 32 HW 2012/01/18 COMPAL EMI request. change CAP to 22P (C20,C22,C23) and 10P (C12, C13, C21), and all stuff.
84 46 HW
2012/01/20 COMPAL Solve dock detection issue. change R755 from 100K to 10K.
85 49 HW 2012/01/20 COMPAL Avoid material mixture with E3 project 5055 devices. change MEC5055 from SA00003TZ1L to SA00003TZ2L.
86 11,28,36
B B
44,52
HW 2012/01/20 COMPAL Change RC value at Gate of MOS Load SW to modify power
rail soft start timing.
RC73 from 100K to 330K; RC79 from 330K to 1M; CC71 from 0.1u to 0.022u
R412 from 100K to 470K; R1632 from 1M to 4.7M; C293 from 0.1u to 0.022u
R515 from 100K to 470K; R2126 from 1M to 4.7M; C416 from 0.1u to 0.022u
R731 from 100K to 470K; R1628 from 1M to 4.7M; C651 from 4700p to 220p
R737 from 100K to 470K; R1629 from 1M to 4.7M; C652 from 4700p to 220p
R917 from 100K to 470K; R1617 from 1M to 4.7M; C770 from 4700p to 220p
R930 from 100K to 470K; R1611 from 470K to 2.2M; C773 from 2200p to 100p
R2067 from 100K to 470K; C1272 from 2200p to 220p
R2069 from 100K to 470K; C1274 from 470p to 220p
Sol u t i o n D esc r i p t i on Rev.Page# Ti t l e
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
0.4(X01)
87 16 HW 2012/02/29 COMPAL For NVDIA request. No stuff RV29.
4088 add R2196 ~ R2197, change power rail from +3.3V_RUN to +USB3 on U638.9
2nd source.COMPAL2012/02/29HW
and U638.25
4089 add Q338 and No stuff.Reserve for samsung mobile issue.COMPAL2012/02/29HW
5190 change Q84, Q339 from DMN66D0LDW to SSM3K7002FU.change MOS to single package.COMPAL2012/03/01HW
2591 change FAN conn from ACES_50450-0067N-001 to ACES_50271-0040N-001 on
A A
change FAN conn.COMPAL2012/02/29HW
JFAN1, JFAN2
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE_PIR 3
EE_PIR 3
EE_PIR 3
LA-7931P
LA-7931P
LA-7931P
68 70Monday, July 23, 2012
68 70Monday, July 23, 2012
68 70Monday, July 23, 2012
1
1.0
1.0
1.0
Page 69
5
4
3
2
1
Version Change List ( P. I. R. List )
Page 4
Request
Item Issue DescriptionDate
Ow n er
92 40 HW 2012/03/01 COMPAL change main source. change main source from MAX14618 to SLG55584A on U2.
D D
93 35 HW COMPAL For SATA Gen2, Gen3 EA setting. stuff R1173, R1204 and No stuff R1206.
94 43 HW COMPAL For SATA Gen2, Gen3 EA setting. stuff R2135, R2138 and No stuff R2139.
95 31 HW COMPAL Meet RGB panel sequencing. stuff L56 and No stuff L57.
96 28 HW COMPAL change to new manufacturing technology. change from RB751V-40GTE to RB751VM-40TE on D53,D64,D66,D67,D69,D100,
97 29 HW COMPAL According to new EIA rule. Change U627 from PS8330BQFN48GTR-A0 to PS8330BQFN48GTR2-A0.
98 28 HW COMPAL Solve LVDS cable burn out issue. change JLVDS1.4 and JLVDS2.4 to NC.
1699 change RV29 to 750 ohm and stuff.Meet high level on DGPU_PEX_RST# for N14P.COMPALHW
40100 change JUSB1, JUSB2 from UEA111Y1-C1BD1-7H to AUSB0041-P001A.Update Conn list.COMPALME
2012/03/01
2012/03/01
2012/03/01
2012/03/01
2012/03/02
2012/03/05
2012/03/05
2012/03/05
D101.
stuff R71, R65, R67.Meet AMD HDMI 297 MHz EA setting.COMPAL34101 2012/03/05HW
HW
C C
2012/03/07 COMPAL ME request. add H27.103 51 ME
change power rail from +3.3V_RUN to +USB3 on R26.12nd source.COMPAL2012/03/0640102
2012/03/08 COMPAL layout space limitation. Remove RD12, RD13.104 12 HW
2012/03/08105 COMPAL layout space limitation. Remove RD21, RD22.13 HW
106 2012/03/08 COMPAL Solve LVDS cable burn out issue. add one test point on JLVDS1.4 and JLVDS2.428 HW
107 2012/03/1328 HW COMPAL Wrong CPN for prefix number. change CPN from SM010007O0L to SM070001I0L on L10.
108 2012/03/1311 HW COMPAL Solve backdrive (follow B4). change CPN from SB00000L800 to SB00000RV00 on QC3.
109 16 HW 2012/04/02 COMPAL Solve AUX signal pull to different power rail. Change power rail from +3.3V_RUN to +3.3V_AVDD.
EMI28110
7~52 HW111 COMPAL short all reserved 0 Ohm resister. RC24,RC27,RC17,RC18,RC25,RC68,RC69,RC83,RD1,RD2,RD7,RD14, R1157,R1158,
B B
2012/04/05
Reserve C1341, C1342 on LCD_SMBCLK and LCD_SMBDAT.EMI request.(RGB noise coupling to LVDS cable 224MHz)COMPAL2012/04/02
RD15,RD16,RD23,RD24,RD25,RD32,RD33,RD34,RD39,RD40,R1169,R1624,R1626
R1970,RH286,RH290,RH307,RH308,RH82,RH83,RH85,RH86,RH88,RH90,RH92,R2089,
RH93,RH95,RH96,RH280,RH281,RH359,RH113,RH323,RH116,RH117,R2090,R2105,R2142
RH320,RH120,RH121,RH122,RH334,RH343,RH335,RH336,RH338,RH339,RH341,RH356,
RH259,RH150,RH201,R1187,R551,R552,R2159,RC29,RC34,RC40,
R555,R1144,R702,R707,R709,R703,R724,R730,R713,R797,R771,R741,R815,RC9,RH1,
R1068,R867,R853,R855,R862,R1180,R1633,R781,R808,RH2,RH309,RH337,R2072,
R289,RH202,RH205,RH211.
Sol u t i o n D esc r i p t i on Rev.Page# Ti t l e
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.5(X01)
0.6(X02)
0.6(X02)
0.6(X02)
112 26 HW 2012/04/05 COMPAL Remove current sensor function. No stuff R1974,R1975,C16,C17,C361,C363.
113 25 HW 2012/04/09 COMPAL change VSET from 88 to 93 .
℃℃
change R406 from 953 ohm to 1.33K ohm.
114 49 HW 2012/04/09 COMPAL change Board ID to X03. change R875 from 62K ohm to 33K ohm.
115 29 HW 2012/04/09 COMPAL [DF543750]DP->HDMI/DP->S-DVI dongle no function on NV
HW
HW
A A
COMPAL2012/04/0942116 Add net name WiGi_RADIO_DIS#_R on JMINI4.32, net name BT_RADIO_DIS#_R on
COMPAL2012/04/0948 change net name from VOL_MUTE_LED# to WiGi_RADIO_DIS# on U46.A1
units.
Add WiGig card function.
Add WiGig card function.117
Add TMDS DDC PU schematic on DP port that include Q339, Q340,R2198~2201,
C1343.
JMINI4.51, and reserve R2204, R2205, D104, D105.
PU 100K ohm on net WiGi_RADIO_DIS# and BT_RADIO_DIS#.
0.6(X02)
0.6(X02)
0.6(X02)
0.6(X02)
0.6(X02)
0.6(X02)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE_PIR 4
EE_PIR 4
EE_PIR 4
LA-7931P
LA-7931P
LA-7931P
69 70Monday, July 23, 2012
69 70Monday, July 23, 2012
69 70Monday, July 23, 2012
1
1.0
1.0
1.0
Page 70
5
4
3
2
1
Version Change List ( P. I. R. List )
Page 5
Request
Item Issue DescriptionDate
Ow n er
51 2012/04/09 COMPAL Remove Q339 for WiGig card function usage. 118 HW Add WiGig card function.
D D
120 50 HW Add WiGig card function.
2012/04/09 COMPAL change net name from BT_RADIO_DIS# to BT_RADIO_DIS#_D on JBT1.6
Add WiGig card function.HW119
Remove net VOL_MUTE_LED on JIO1.100COMPAL2012/04/0947
Add R2206 and reserve D106 on net BT_RADIO_DIS#_D.
2012/04/09 COMPAL Reserve R1121, R1122.121 27 HW Solve +3.3V_MXM backdrive when disable RUN_GFX_ON.
2012/04/09 COMPAL122 44 HW change R716 to 47K ohm.for power saving in DC mode S3.
2012/04/11 COMPAL123 40 HW stuff R28 and R30.Solve kinston storage device re-distinguish issue.
124 2012/04/11 COMPAL16 HW update MXM conn PCB footprint. change footprint to JAE_MM70-314-310B1-1-_310P-S.
125 40 EMI 2012/04/16 COMPAL EMI request. change from DLW21SN900HQ2L to DLW21SN900SQ2L on L39, L41.
51126 Meet LED brightness spec.COMPAL2012/04/16HW change R943 from 374 ohm to 240 ohm.
C C
127 28 ME 2012/05/21 COMPAL ME request (DFX issue, cancel boss hole). change JLVDS2 from JAE_FI-M56S1-R1500 to JAE_FI-M56S1-R1500-DT.
change R956 from 374 ohm to 200 ohm.
change R955 from 1.2K ohm to 887 ohm.
change R934 from 1.2K ohm to 620 ohm.
change R939, R941 from 1.2K ohm to 680 ohm.
128 17 HW 2012/05/21 COMPAL Create X76 BOM for 2nd source. Main source is WINBOND, 2nd source is EON.
129 17 HW 2012/05/21 COMPAL change to new manufacturing technology. change p/n from W25Q64CVSSIG to W25Q64FVSSIG.
130 49 HW 2012/05/21 COMPAL change Board ID to A00. change R875 from 33K ohm to 8.2K ohm.
131 42,51 HW 2012/05/22 COMPAL add WiGi_BT LED function. add net name WiGi_BT_LED# on JMINI.46, and add R2207(No stuff).
132 7,16 HW 2012/05/31 COMPAL Dalmore 12" warm/cold boot shutdown issue. change main source from NXP to ON on U16, UC1, U634.
133 22 HW 2012/05/31 COMPAL TAIYO EOL, change to TAI-TECH. change part from SHI0110BJ0L to SHI0110BJ50 on LH8.
134 51 HW 2012/06/05 COMPAL Meet LED brightness spec. change R943 from 240 ohm to 510 ohm.
change R956 from 200 ohm to 340 ohm.
change R942 from 1.2K ohm to 806 ohm.
change R955 from 887 ohm to 300 ohm.
change R934 from 620 ohm to 680 ohm.
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DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE_PIR 4
EE_PIR 4
EE_PIR 4
LA-7931P
LA-7931P
LA-7931P
70 70Monday, July 23, 2012
70 70Monday, July 23, 2012
70 70Monday, July 23, 2012
1
1.0
1.0
1.0
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