Compal LA-7931P Schematics Rev1.0
A
B
C
D
E
MODEL NAME :
PCB NO :
BOM P/N :
1 1
LA-7931P ( DAA00002T00 )
4319FN31L01
4319FN31L02
QAR00
Compal Confidential
Vans 15
rPGAIvyBridge+FCBGAPCHPantherPoint+MXM typeAx1Ⅲ
Rev: 1.0 (A00)
2 2
CONN@ : ME connector
2012.06.07
@ : Nopop component
5@ : 6-bit LCD panel
6@ : 10-bit LCD panel
1@, 2@, 3@, 4@ : for TPM / TCM
3 3
MBType
SATARe‐driver
(U26,U637)
PS8520B
(SA00004WF00)
4 4
MB PCB
Part
Description
Number
DAA00002T00
power CKT: 05/17
PCB0FELA‐7931PREV0M/BDIS
MAX4951C
(SA00002EY1L)
A
Source
mainsource
2ndsource X7641231L02
PXDP@,JTAG@ : Total debug connector (pop them until ST)
BOMP/N
4319FN31L01 4319FN31L02
Include6‐bit Include10‐bit
1@TPM
3@
5@ 6@1@ 3@
PXDP@ PXDP@
JTAG@ JTAG@
X76P/N
X7641231L01
B
Page
35,43
USB3Re‐driver
(U638)
PS8720B
(SA00004UI00)
PS8720A
(SA00005PO00)
Source
mainsource
2ndsource X7641231L04
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
MBType
TPM
X76P/N
X7641231L03
C
Page
40
BOMP/N
ROMpart Source
U52(SA000039A2L)
U53(SA00003K80L)
main(Winbond)
U52(SA000046400)
U53(SA00004LI00)
D
2nd(EON) X7640631L03
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
X76P/N
X7640631L01
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
Page
17
LA-7931P
LA-7931P
LA-7931P
1.0
1.0
170Monday, July 23, 2012
170Monday, July 23, 2012
170Monday, July 23, 2012
E
1.0
A
&
LVDS6‐bit
LVDS10‐bit
&
eDPtoLVDS
1 1
LVDSPanel
P.28
Conn
DP1.2
Conn
P.29
CRTConn
Docking CRT
P.32
HDMI1.4a
Conn
P.34
Port 8
Docking DP1
Docking DP2
Port 3
2 2
IEEE1394
+
ExpressCard
(STDP4010)
P.30~P.31
LVDSMUX
(TS3DV20812)
DPRedriver
(PS8330B)
CRTSW
(MAX14885)
DP/HDMIDeMUX
(PS8336B)
IntelLewisville
(82579LM)
Cardreader
USB Port 10
SDXC1394
3 3
SIMCard
P.43
FreeFallSensor
(LNG3DMTR)
P.35
CurrentMonitor
(EMC1701)
4 4
P.26
Thermal
GUARDIANIII
EMC4002
P.25
On IO board
SATA Port 5
USB 2.0 Port 8
Docking DAI
Docking CRT
Docking LAN
USB3.0 Port 3
Docking LPC
Docking DP1
Docking DP2
A
LANswitch
(PI3L720)
RJ45
P.38
(10-bit panel output)
P.27
P.29
(10-bit panel output)
P.32
P.34
DP(DIS)
Port 7
P.37
P.37
Docking LAN
E‐Dock
LVDS (DIS)
LVDS
DP (DIS)
DP (DIS)
MiniCard‐3
PP
P.45
B
PEG x16 (DIS)
DP
DP_D
LVDS
DP_A
MXMConn.
TYPEA
CRT
DP_C
DP_B
PCIE BUS
Port 5
P.42
SMSCSIO
ECE5048
SATA Port 2
PCIE/SATAMUX
(PI2DBS212)
MiniCard‐2
WWAN/GPS
mSATA
USB Port 5
P.47
Port 6
P.43
P.43
BC BUS
MiniCard‐1
WLAN/WiGi
USB Port 4
ChinaTCM1.2
SSX44B
DiscreteTPM
AT97SC3204
SMSCKBC
Docking LPC
MEC5055
TPCONN
On IO board
DC‐IN
P.53
www.schematic-x.blogspot.com
B
LVDS
CRT
Port 2
C
P.16
P.42
P.41
P.41
P.48
KBCONN
C
D
Intel
IvyBridge
Processorr
PGA989Socket
35WDualCore
45WQuadCore
55WQCExtremeEdition
P.6~P.11
FDI x8
(DDRIII)
Memory Bus
Dual Channel
1.5V DDRIII
1333 /1600 MHz
DMI x4 gen 2
SATA3.0
204pinDDRIIISO‐DIMMx4
SATA Port 0
SATA Port 3
SATA Port 4
SATA2.0
LVDS
CRT
Intel
PantherPoint
PCH
BGA989Balls
8MB
P.17~P.24
W25X64ZE
USB3.0
USB2.0
HD Audio
P.17
USB Port 0
USB Port 1
USB Port 2
USB Port 6
USB Port 11
USB Port 12
USB Port 13
USB Port 7
SPI
W25Q32BV
4MB
P.17
On USH Board
LPC BUS
AudioCodec
92HD93
P.49
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
D
P.12~P.15
OC : 1866 MHz
SATA3.0Repeater
(PS8520B)
P.35
ODDConn.
P.36
USB/eSATAConn.
USB Port 9
P.39
USB3.0Repeater
(PS8710B)
USB3.0Repeater
(PS8710B)
P.40
P.40
USB2.0ConnLeftSide
USB2.0ConnLeftSide
BT4.0+LE
DigitalCamera
P.49
Touchscreen
P.28
P.28
BRCM5882
TPM1.2
FP_USB
HeadPhoneJack
ArrayMICJack
Int.Speaker
Speaker module
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
E
1stHDDConn.
USB2.0 port 0
USB3.0ConnRightSide
USBCharger
USB3.0ConnRightSide
USB2.0 port 1
On IO board
through LVDS Cable
RFID
TDA8034HN
SmartCard
Fingerprint
CONN
On IO board
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
LA-7931P
LA-7931P
LA-7931P
E
P.35
270Monday, July 23, 2012
270Monday, July 23, 2012
270Monday, July 23, 2012
P.40
P.40
1.0
1.0
1.0
5
4
3
2
1
POWER STATES
State
S0 (Full ON) / M0
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH ON ON ON OFF
D D
S4 (Suspend to DISK) / M1 ON ON OFF
S5 (SOFT OFF) / M1 ON ON OFFLOW LOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
SLP
S3#
S4#
HIGH
HIGH HIGH HIGH
LOW
LOW HIGH HIGHLOW
LOW
LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
S5#
S4
STATE#
SLP
M#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCH
PM TABLE
+15V_ALW
+5V_ALW
C C
State
S0
S3
S5 S4/AC
power
plane
+3.3V_ALW_PCH
+3.3V_RTC_LDO
ON
ON
+3.3V_SUS
+1.5V_MEM
ON ON
ON
OFF
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
OFFON
OFF
+3.3V_M +3.3V_M
+1.05V_M
ON
ON
ON
+1.05V_M
(M-OFF)
ON
OFF
OFF
SATA
SATA 0
SATA 1
SATA 2
SATA 3
SATA 4
SATA 5
DESTINATION
HDD 1
NA
mSATA
ODD
ESATA
Dock
USH
USB PORT#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
JUSB1 (Ext Right Side)
JUSB2 (Ext Right Side)
IO Board- JUSB1 (Ext Left Side)
Docking USB3.0
Docking USB 2.0
WWAN
IO Board- JUSB2 (Ext Left Side)
USH
WLAN
ESATA
Express Card
BT 4.0
Carmera
Touch Screen
DESTINATION
USB3.0
USB3.0
BIO
NA
S5 S4/AC don't exist
B B
A A
Stack up
OFFOFF
OFF
OFFOFF
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
NA
MINI CARD-1 WLAN/DMC
Express Card
NA
MINI CARD-3 (Pink Panther)
MINI CARD-2 WWAN/mSATA/GPS
10/100/1G LOM
DESTINATION
Lane 8 Cardreader
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Index and Config.
Index and Config.
Index and Config.
LA-7931P
LA-7931P
LA-7931P
370Monday, July 23, 2012
370Monday, July 23, 2012
370Monday, July 23, 2012
1
1.0
1.0
1.0
5
4
3
2
1
DOCK
D D
EN_INVPWR
RUN_GFX_ON
ADAPTER
PCH_ALW_ON
+PWR_SRC
BATTERY
CHARGER
C C
SI3456DDV
EN_LCDPWR
(Q18)
MXM_ENVDD
ENVDD_PCH
FDC654P
(Q21)
SI4835DDY
(Q186)
TP0610K
(PQ4)
LCD_VCC_TEST_EN
+LCDVDD
+BL_PWR_SRC
+MXM_PWR_SRC
+PWR_SRC_S
+1.8V_RUN
PWR_SHARE_EN#
TPS2560
(U45)
+5V_USB_PWR1
+5V_USB_PWR2
SY8033
(PU4)
SIO_SLP_S3#
Pop option
+5V_HDD
+5V_RUN
ALWON
SIO_SLP_S3#
MODC_EN
SI3456DDVSI3456DDV
(Q30)(Q27)
+5V_MOD
RT8205
(PU101)
+3.3V_ALW
+5V_ESATA_PWR
ALW_ON_3.3V#
+5V_ALW
ESATA_USB_PWR_EN#
TPS2560
(U48)
+5V_ALW_PCH
SSM3K7002FU
(QH4)
RUN_GFX_ON
+5V_RUN_ENABLE
+5V_MXM
SI4800BDY
(Q76)
DMN3030LSS
(Q329)
+5V_RUN
SYSON
RT8207
(PU151)
B B
SIO_SLP_A#
TPS51212
(PU5)
CPU_VTT_ON
TPS51212
(PU6)
1.05V_VTTPWRGD
TPS51461
(PU7)
1.05V_0.8V_PWROK
NVRAM_PWR_EN
SI3456DDV
(Q46)
MCARD_WWAN_PWREN
SI3456DDV
(Q40)
MCARD_MISC_PWREN
SI3456DDV
(Q44)
PCH_ALW_ON
SI3456DDV
(Q49)
SUS_ON
SI3456DDV
(Q54)
SIO_SLP_LAN#
SI3456DDV
SLG59M232VTR
(Q34) (U78)
SIO_SLP_A#
(Q58)
RUN_GFX_ON
SI3456DDV
(Q25)
SIO_SLP_S3#
SI3456DDV
+1.5V_MEM
+1.05V_M
SIO_SLP_S3#
SI4164
(Q63)
+1.05V_RUN_VTT
ISL95836
(PU702)
+VCC_SA
+3.3V_PCIE_NVM
+3.3V_PCIE_WWAN
+3.3V_PCIE_FLASH
+3.3V_ALW_PCH
Pop option
+3.3V_M
+3.3V_LAN+3.3V_SUS
LDO of 82579
(U31)
+3.3V_RUN
PMV65XP
+3.3V_M
CCD_OFF
+3V_MXM
(Q24)
+1.05V_RUN
+VCC_CORE
+VCC_GFXCORE
Pop option
+1.0V_LAN+1.05V_M
A A
SUSP#
+0.75V_DDR_VTT
SIO_SLP_S3#
AO4728L
(QC3)
+1.5V_CPU_VDDQ
5
SIO_SLP_S3#
NTGS4141
+1.5V_RUN
(Q59)
+VCCAFDI_VRM
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
+CAMERA_VDD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power Rail
Power Rail
Power Rail
LA-7931P
LA-7931P
LA-7931P
470Monday, July 23, 2012
470Monday, July 23, 2012
470Monday, July 23, 2012
1
1.0
1.0
1.0
5
4
3
2
1
SMBUS Address [0x9a]
H14
MEM_SMBCLK
C9
MEM_SMBDATA
3A
PCH
E14M16
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
1A
1A
1B
1B
C8
G12
LAN_SMBCLK
LAN_SMBDATA
2.2K
2.2K
B4
A3
B5
A4
+3.3V_ALW_PCH
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMBDAT
D D
C C
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
100 ohm
100 ohm
2N7002
2N7002
SMBUS Address [C8]
127
129
DOCKING
7
BATTERY
6
CONN
SMBUS Address [0x16]
SMBUS Address
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
U5
1
Current Monitor
10
U6
1
10
Current Monitor
12
14
JLVDS3
202
200
202
200
202
200
202
200
53
51
DIMM1
DIMM2
DIMM3
SMBUS Address [A0h]
A0h --> 1010 0000
SMBUS Address [A4h]
A4h --> 1010 0100
SMBUS Address [A4h]
A4h --> 1010 0100
DIMM4
XDP2
SMBUS Address [TBD]
10K
14
13
+3.3V_RUN
G Sensor
WWAN
SMBUS Address [TBD]
SMBUS Address [TBD]
SMBUS Address
SMB_ADM1032: 0x98
SMB_DIAG_DUMP: 0x04
SMB_DIAG_DUMP2: 0x05
SMB_BLACKTOP: 0x60
10K
30
32
A50
B53
USH_SMBCLK
USH_SMBDAT
1E
1E
2.2K
+3.3V_SUS
M9
L9
SMBUS Address [0xa4]
USH
2.2K
B B
MEC 5055
2B
2B
A49
B52
CARD_SMBCLK
CARD_SMBDAT
2.2K
2.2K
2.2K
B50
1G
1G
CHARGER_SMBCLK
A47
CHARGER_SMBDAT
2.2K
B7
A7
BAY_SMBDAT
BAY_SMBCLK
2D
2D
2.2K
4.7K
A A
5
B49
B48
GPU_SMBCLK
GPU_SMBDAT
2A
2A
4.7K
4
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
2N7002
2N7002
10
9
Charger
7
Express card
8
SMBUS Address [0x12]
SMBUS Address [TBD]
70
68
MXM
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SMBUS Address [0x30]
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SMBUS Bolck Diagram
SMBUS Bolck Diagram
SMBUS Bolck Diagram
LA-7931P
LA-7931P
LA-7931P
570Monday, July 23, 2012
570Monday, July 23, 2012
570Monday, July 23, 2012
1
of
of
of
1.0
1.0
1.0
5
4
3
2
1
PEG_CRX_GTX_C_P[0..15]
PEG_CRX_GTX_C_N[0..15]
JCPU1A
D D
C C
B B
DMI_CRX_PTX_N0<19>
DMI_CRX_PTX_N1<19>
DMI_CRX_PTX_N2<19>
DMI_CRX_PTX_N3<19>
DMI_CRX_PTX_P0<19>
DMI_CRX_PTX_P1<19>
DMI_CRX_PTX_P2<19>
DMI_CRX_PTX_P3<19>
DMI_CTX_PRX_N0<19>
DMI_CTX_PRX_N1<19>
DMI_CTX_PRX_N2<19>
DMI_CTX_PRX_N3<19>
DMI_CTX_PRX_P0<19>
DMI_CTX_PRX_P1<19>
DMI_CTX_PRX_P2<19>
DMI_CTX_PRX_P3<19>
FDI_CTX_PRX_N0<19>
FDI_CTX_PRX_N1<19>
FDI_CTX_PRX_N2<19>
FDI_CTX_PRX_N3<19>
FDI_CTX_PRX_N4<19>
FDI_CTX_PRX_N5<19>
FDI_CTX_PRX_N6<19>
FDI_CTX_PRX_N7<19>
FDI_CTX_PRX_P0<19>
FDI_CTX_PRX_P1<19>
FDI_CTX_PRX_P2<19>
FDI_CTX_PRX_P3<19>
FDI_CTX_PRX_P4<19>
FDI_CTX_PRX_P5<19>
FDI_CTX_PRX_P6<19>
FDI_CTX_PRX_P7<19>
FDI_FSYNC0<19>
FDI_FSYNC1<19>
FDI_INT<19>
FDI_LSYNC0<19>
FDI_LSYNC1<19>
(1)EDP_COMPIOuse4miltracetoRC1
(2)EDP_ICOMPOuse12miltoRC1
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
B27
B25
A25
B24
B28
B26
A24
B23
G21
E22
F21
D21
G22
D22
F20
C21
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
J18
J17
H20
J19
H17
A18
A17
B16
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15
CONN@
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
TYCO_2134146-3_IVYBRIDGE~D
DMI
Intel(R) FDI
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PCI EXPRESS* - GRAPHICS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
PEG_COMP
J21
H22
K33
PEG_CRX_GTX_N0
M35
PEG_CRX_GTX_N1
L34
PEG_CRX_GTX_N2
J35
PEG_CRX_GTX_N3
J32
PEG_CRX_GTX_N4
H34
PEG_CRX_GTX_N5
H31
PEG_CRX_GTX_N6
G33
PEG_CRX_GTX_N7
G30
PEG_CRX_GTX_N8
F35
PEG_CRX_GTX_N9
E34
PEG_CRX_GTX_N10
E32
PEG_CRX_GTX_N11
D33
PEG_CRX_GTX_N12
D31
PEG_CRX_GTX_N13
B33
PEG_CRX_GTX_N14
C32
PEG_CRX_GTX_N15
J33
PEG_CRX_GTX_P0
L35
PEG_CRX_GTX_P1
K34
PEG_CRX_GTX_P2
H35
PEG_CRX_GTX_P3
H32
PEG_CRX_GTX_P4
G34
PEG_CRX_GTX_P5
G31
PEG_CRX_GTX_P6
F33
PEG_CRX_GTX_P7
F30
PEG_CRX_GTX_P8
E35
PEG_CRX_GTX_P9
E33
PEG_CRX_GTX_P10
F32
PEG_CRX_GTX_P11
D34
PEG_CRX_GTX_P12
E31
PEG_CRX_GTX_P13
C33
PEG_CRX_GTX_P14
B32
PEG_CRX_GTX_P15
M29
PEG_CTX_GRX_C_N0
M32
PEG_CTX_GRX_C_N1
M31
PEG_CTX_GRX_C_N2
L32
PEG_CTX_GRX_C_N3
L29
PEG_CTX_GRX_C_N4
K31
PEG_CTX_GRX_C_N5
K28
PEG_CTX_GRX_C_N6
J30
PEG_CTX_GRX_C_N7
J28
PEG_CTX_GRX_C_N8
H29
PEG_CTX_GRX_C_N9
G27
PEG_CTX_GRX_C_N10
E29
PEG_CTX_GRX_C_N11
F27
PEG_CTX_GRX_C_N12
D28
PEG_CTX_GRX_C_N13
F26
PEG_CTX_GRX_C_N14
E25
PEG_CTX_GRX_C_N15
M28
PEG_CTX_GRX_C_P0
M33
PEG_CTX_GRX_C_P1
M30
PEG_CTX_GRX_C_P2
L31
PEG_CTX_GRX_C_P3
L28
PEG_CTX_GRX_C_P4
K30
PEG_CTX_GRX_C_P5
K27
PEG_CTX_GRX_C_P6
J29
PEG_CTX_GRX_C_P7
J27
PEG_CTX_GRX_C_P8
H28
PEG_CTX_GRX_C_P9
G28
PEG_CTX_GRX_C_P10
E28
PEG_CTX_GRX_C_P11
F28
PEG_CTX_GRX_C_P12
D27
PEG_CTX_GRX_C_P13
E26
PEG_CTX_GRX_C_P14
D25
PEG_CTX_GRX_C_P15
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
12
CC8 0.22U_0402_16V7K~D
12
CC9 0.22U_0402_16V7K~D
12
CC10 0.22U_0402_16V7K~D
12
CC1 0.22U_0402_16V7K~D
12
CC2 0.22U_0402_16V7K~D
12
CC11 0.22U_0402_16V7K~D
12
CC12 0.22U_0402_16V7K~D
12
CC3 0.22U_0402_16V7K~D
12
CC4 0.22U_0402_16V7K~D
12
CC13 0.22U_0402_16V7K~D
12
CC14 0.22U_0402_16V7K~D
12
CC5 0.22U_0402_16V7K~D
12
CC6 0.22U_0402_16V7K~D
12
CC15 0.22U_0402_16V7K~D
12
CC16 0.22U_0402_16V7K~D
12
CC7 0.22U_0402_16V7K~D
12
CC17 0.22U_0402_16V7K~D
12
CC18 0.22U_0402_16V7K~D
12
CC19 0.22U_0402_16V7K~D
12
CC20 0.22U_0402_16V7K~D
12
CC21 0.22U_0402_16V7K~D
12
CC22 0.22U_0402_16V7K~D
12
CC23 0.22U_0402_16V7K~D
12
CC24 0.22U_0402_16V7K~D
12
CC25 0.22U_0402_16V7K~D
12
CC26 0.22U_0402_16V7K~D
12
CC27 0.22U_0402_16V7K~D
12
CC28 0.22U_0402_16V7K~D
12
CC29 0.22U_0402_16V7K~D
12
CC30 0.22U_0402_16V7K~D
12
CC31 0.22U_0402_16V7K~D
12
CC32 0.22U_0402_16V7K~D
12
CC33 0.22U_0402_16V7K~D
12
CC34 0.22U_0402_16V7K~D
12
CC35 0.22U_0402_16V7K~D
12
CC36 0.22U_0402_16V7K~D
12
CC37 0.22U_0402_16V7K~D
12
CC38 0.22U_0402_16V7K~D
12
CC39 0.22U_0402_16V7K~D
12
CC40 0.22U_0402_16V7K~D
12
CC41 0.22U_0402_16V7K~D
12
CC42 0.22U_0402_16V7K~D
12
CC43 0.22U_0402_16V7K~D
12
CC44 0.22U_0402_16V7K~D
12
CC45 0.22U_0402_16V7K~D
12
CC46 0.22U_0402_16V7K~D
12
CC47 0.22U_0402_16V7K~D
12
CC48 0.22U_0402_16V7K~D
12
CC49 0.22U_0402_16V7K~D
12
CC50 0.22U_0402_16V7K~D
12
CC51 0.22U_0402_16V7K~D
12
CC52 0.22U_0402_16V7K~D
12
CC53 0.22U_0402_16V7K~D
12
CC54 0.22U_0402_16V7K~D
12
CC55 0.22U_0402_16V7K~D
12
CC56 0.22U_0402_16V7K~D
12
CC57 0.22U_0402_16V7K~D
12
CC58 0.22U_0402_16V7K~D
12
CC59 0.22U_0402_16V7K~D
12
CC60 0.22U_0402_16V7K~D
12
CC61 0.22U_0402_16V7K~D
12
CC62 0.22U_0402_16V7K~D
12
CC63 0.22U_0402_16V7K~D
12
CC64 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P[0..15] <16>
PEG_CRX_GTX_C_N[0..15] <16>
PEG_CTX_GRX_P[0..15] <16>
PEG_CTX_GRX_N[0..15] <16>
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_P15
PEG_CTX_GRX_N0
PEG_CTX_GRX_N1
PEG_CTX_GRX_N2
PEG_CTX_GRX_N3
PEG_CTX_GRX_N4
PEG_CTX_GRX_N5
PEG_CTX_GRX_N6
PEG_CTX_GRX_N7
PEG_CTX_GRX_N8
PEG_CTX_GRX_N9
PEG_CTX_GRX_N10
PEG_CTX_GRX_N11
PEG_CTX_GRX_N12
PEG_CTX_GRX_N13
PEG_CTX_GRX_N14
PEG_CTX_GRX_N15
PEG_CTX_GRX_P0
PEG_CTX_GRX_P1
PEG_CTX_GRX_P2
PEG_CTX_GRX_P3
PEG_CTX_GRX_P4
PEG_CTX_GRX_P5
PEG_CTX_GRX_P6
PEG_CTX_GRX_P7
PEG_CTX_GRX_P8
PEG_CTX_GRX_P9
PEG_CTX_GRX_P10
PEG_CTX_GRX_P11
PEG_CTX_GRX_P12
PEG_CTX_GRX_P13
PEG_CTX_GRX_P14
PEG_CTX_GRX_P15
CONN@
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
LinkCISOK
+1.05V_RUN_VTT +1.05V_RUN_VTT
RC1 24.9_0402_1%~D
12
eDPCompensation
eDP_COMPIOandICOMPOsignalsshouldbeshortednear
ballsandroutedwithtypicalimpedance<25mohms
A A
5
EDP_COMP
0722
1 2
RC2 24.9_0402_1%~D
PEGCompensation
PEG_ICOMPIandRCOMPOsignals
shouldbeshortedandroutedwith
‐maxlength=500mils
‐typicalimpedance=43mohms
PEG_ICOMPOsignalsshouldberoutedwith
‐maxlength=500mils
‐typicalimpedance=14.5mohms
PEG_COMP
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Ivy Bridge (1/6)
Ivy Bridge (1/6)
Ivy Bridge (1/6)
LA-7931P
LA-7931P
LA-7931P
670Monday, July 23, 2012
670Monday, July 23, 2012
670Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
5
4
3
2
1
FollowDGRev0.71SM_DRAMPWROKtopology
+3.3V_ALW_PCH
RUNPWROK<48,49>
D D
C C
B B
PM_DRAM_PWRGD<19>
+3.3V_ALW_PCH
+1.05V_RUN_VTT
RC11 56_0402_5%~D@
RC13 49.9_0402_1%~D@
RC16 62_0402_5%~D
H_PROCHOT#<26,49,60,62>
H_THERMTRIP#<25>
H_CPUPWRGD<21>
1 2
RC6 200_0402_5%~D
1 2
H_THERMTRIP#
1 2
1 2
H_CATERR#
H_PROCHOT#
CPU_DETECT#<48>
PECI_EC<49>
1 2
RC22 56_0402_5%~D
PlaceRC22nearCPU
1 2
RC24 0_0402_5%~D@
H_PM_SYNC<19>
1 2
RC27
@
BufferedresettoCPU
A A
PCH_PLTRST#<20>
1
2
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#_R
H_PM_SYNC
H_CPUPWRGD_R
0_0402_5%~D
VDDPWRGOOD_R
PCH_PLTRST#_R
+3.3V_RUN
5
1
P
NC
Y
2
A
G
SN74LVC1G07DCKR_SC70-5~D
3
CC65
1 2
0.1U_0402_16V4Z~D
5
B
4
VCC
Y
A
G
UC1
MC74VHC1G09DFT2G_SC70-5
3
RUN_ON_CPU1.5VS3#<11,52>
C26
AN34
AL33
AN33
AL32
AN32
AM34
AP33
V8
AR33
0.1U_0402_16V4Z~D
1
CC69
2
4
PCH_PLTRST#_BUF
UC2
Opendrainbuffer
5
+1.5V_CPU_VDDQ
12
200_0402_5%~D
39_0402_5%~D
12
13
D
2
G
S
JCPU1B
CONN@
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
+1.05V_RUN_VTT
75_0402_1%~D
12
RC49
1 2
RC51 43_0402_5%~D
RC4
VDDPWRGOOD
@
RC7
SSM3K7002FU_SC70-3~D
1 2
RC5 130_0402_5%~D
@
QC1
MISCTHERMALPWR MANAGEMENT
VDDPWRGOOD_R
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
BPM#[0]
BPM#[1]
BPM#[2]
JTAG & BPM
PCH_PLTRST#_R
4
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
BCLK
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
A28
CPU_DMI
A27
CPU_DMI#
A16
CPU_DPLL
A15
CPU_DPLL#
R8
DDR3_DRAMRST#_CPU
AK1
SM_RCOMP0
A5
SM_RCOMP1
A4
SM_RCOMP2
AP29
XDP_PRDY#
AP27
XDP_PREQ#
AR26
XDP_TCLK
AR27
XDP_TMS
AP30
XDP_TRST#
AR28
TDI
XDP_TDI_R
AP26
XDP_TDO_R
AL35
XDP_DBRESET#_R
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
XDP_TDO_R XDP_TDO
ForESDconcern,pleaseputnearCPU
H_CPUPWRGD
AvoidstubinthePWRGDpath
whileplacingresistorsRC27&RC46
+3.3V_ALW_PCH
1 2
RC3 1K_0402_5%~D@
+1.05V_RUN_VTT
PlacenearJXDP1
1 2
RC17 0_0402_5%~D@
1 2
RC18 0_0402_5%~D@
1 2
RC19 1K_0402_1%~D
1 2
RC21 1K_0402_1%~D
4.99K_0402_1%~D
12
RC23
DDR_HVREF_RST_PCH<18>
DDR_HVREF_RST_GATE<49>
RC29
@
1 2
0_0402_5%~D
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
1 2
RC34 0_0402_5%~D@
1 2
RC40 0_0402_5%~D@
1
2
0.1U_0402_16V4Z~D
CC66
T69PAD~D @
T70PAD~D @
T68PAD~D @
T67PAD~D @
T78PAD~D @
T77PAD~D @
T79PAD~D @
T80PAD~D @
SYS_PWROK_XDP
0.1U_0402_16V4Z~D
1
CC67
2
CLK_CPU_DMI <18>
CLK_CPU_DMI# <18>H_SNB_IVB#<21>
+1.05V_RUN_VTT
D
S
13
G
BSS138W-7-F_SOT323-3~D
2
1
CC68
0.047U_0402_16V4Z~D
2
RC25 0_0402_5%~D@
RC26 0_0402_5%~D@
XDP_DBRESET# <17,19>
XDP_TDIXDP_TDI_R
SIO_PWRBTN#_R<17,19>
CFG0<9>
SYS_PWROK<19,48>
QC2
DDR_HVREF_RST
1 2
1 2
H_CPUPWRGD H_CPUPWRGD_XDP
DDR3_DRAMRST# <12>
1 2
RC8 1K_0402_5%~D
1 2
RC9 0_0402_5%~D@
1 2
RC10 1K_0402_5%~D
1 2
RC12 0_0402_5%~D@
DDR_HVREF_RST <12>
Maxlength=500mils
Tracewidth=15mils
SM_RCOMP2
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RC4610K_0402_5%~D
3
SM_RCOMP1
SM_RCOMP0
1 2
1 2
1 2
2
+1.05V_RUN_VTT
JXDP1
CONN@
XDP_PREQ#
XDP_PRDY#
CFD_PWRBTN#_XDP
XDP_HOOK2
SYS_PWROK_XDP
CLK_XDP
CLK_XDP#
XDP_RST#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCLK
1
OBSFN_A0
2
OBSFN_A1
3
GND
4
OBSDATA_A[0]
5
OBSDATA_A[1]
6
GND
7
OBSDATA_A[2]
8
OBSDATA_A[3]
9
GND
10
HOOK0
11
HOOK1
12
HOOK2
13
HOOK3
14
HOOK4
15
HOOK5
16
VCCOBS_AB
17
HOOK6
18
HOOK7
19
GND
20
TDO
21
TRSTn
22
TDI
23
TMS
TCK124GND
25
GND
26
TCK0
MOLEX_52435-2671
GND
27
28
LinkCISOK
0722
XDP_RST#_R
RC20 1K_0402_5%~D
CLK_XDP
RH1 0_0402_5%~D@
CLK_XDP#
RH2 0_0402_5%~D@
CLK_XDP_ITP<9>
CLK_XDP_ITP#<9>
RC47200_0402_1%~D
RC4825.5_0402_1%~D
RC50140_0402_1%~D
RH3 0_0402_5%~D@
RH4 0_0402_5%~D@
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
12
1 2
1 2
1 2
1 2
PU/PDforJTAGsignals
XDP_DBRESET#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Ivy Bridge (2/6)
Ivy Bridge (2/6)
Ivy Bridge (2/6)
LA-7931P
LA-7931P
LA-7931P
RC281K_0402_5%~D
+1.05V_RUN_VTT
RC3151_0402_1%~D
RC3551_0402_1%~D
RC3851_0402_1%~D @
RC4251_0402_1%~D
RC4451_0402_1%~D
RC4551_0402_1%~D
1
PLTRST_XDP# <20>
CLK_CPU_ITP <18>
CLK_CPU_ITP# <18>
+3.3V_RUN
770Monday, July 23, 2012
770Monday, July 23, 2012
770Monday, July 23, 2012
of
1.0
1.0
1.0
5
4
3
2
1
D D
JCPU1C
CONN@
AB6
DDR_A_D[0..63]<12,13>
C C
B B
DDR_A_BS0<12,13>
DDR_A_BS1<12,13>
DDR_A_BS2<12,13>
DDR_A_CAS#<12,13>
DDR_A_RAS#<12,13>
DDR_A_WE#<12,13>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AD9
AF9
F10
AJ5
AJ6
AJ8
AJ9
AE8
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N8
N7
M9
N9
M7
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
SA_CK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CK[2]
SA_CLK#[2]
SA_CKE[2]
SA_CK[3]
SA_CLK#[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
DDR SYSTEM MEMORY A
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMM2
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMM2
M_CLK_DDR4
M_CLK_DDR#4
DDR_CKE4_DIMM1
M_CLK_DDR5
M_CLK_DDR#5
DDR_CKE5_DIMM1
DDR_CS0_DIMM2#
DDR_CS1_DIMM2#
DDR_CS4_DIMM1#
DDR_CS5_DIMM1#
M_ODT0
M_ODT1
M_ODT4
M_ODT5
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 <13>
M_CLK_DDR#0 <13>
DDR_CKE0_DIMM2 <13>
M_CLK_DDR1 <13>
M_CLK_DDR#1 <13>
DDR_CKE1_DIMM2 <13>
M_CLK_DDR4 <12>
M_CLK_DDR#4 <12>
DDR_CKE4_DIMM1 <12>
M_CLK_DDR5 <12>
M_CLK_DDR#5 <12>
DDR_CKE5_DIMM1 <12>
DDR_CS0_DIMM2# <13>
DDR_CS1_DIMM2# <13>
DDR_CS4_DIMM1# <12>
DDR_CS5_DIMM1# <12>
M_ODT0 <13>
M_ODT1 <13>
M_ODT4 <12>
M_ODT5 <12>
DDR_A_DQS#[0..7] <12,13>
DDR_A_DQS[0..7] <12,13>
DDR_A_MA[0..15] <12,13>
DDR_B_D[0..63]<14,15>
DDR_B_BS0<14,15>
DDR_B_BS1<14,15>
DDR_B_BS2<14,15>
DDR_B_CAS#<14,15>
DDR_B_RAS#<14,15>
DDR_B_WE#<14,15>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
AM5
AM6
AR3
AN3
AN2
AN1
AN9
AN8
AR6
AR5
AR9
AJ11
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
D10
K10
AP3
AP2
AP5
AT5
AT6
AP6
AT8
AT9
AA9
AA7
AB8
AB9
C9
C8
D9
D8
G4
G1
G5
G2
J10
M5
N4
N2
N1
M4
N5
M2
M1
R6
A7
A9
A8
F4
F1
F5
F2
J7
J8
K9
J9
K8
K7
JCPU1D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
CONN@
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMM4
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMM4
M_CLK_DDR6
M_CLK_DDR#6
DDR_CKE6_DIMM3
M_CLK_DDR7
M_CLK_DDR#7
DDR_CKE7_DIMM3
DDR_CS2_DIMM4#
DDR_CS3_DIMM4#
DDR_CS6_DIMM3#
DDR_CS7_DIMM3#
M_ODT2
M_ODT3
M_ODT6
M_ODT7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
SB_CK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CK[2]
SB_CLK#[2]
SB_CKE[2]
SB_CK[3]
SB_CLK#[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
M_CLK_DDR2 <15>
M_CLK_DDR#2 <15>
DDR_CKE2_DIMM4 <15>
M_CLK_DDR3 <15>
M_CLK_DDR#3 <15>
DDR_CKE3_DIMM4 <15>
M_CLK_DDR6 <14>
M_CLK_DDR#6 <14>
DDR_CKE6_DIMM3 <14>
M_CLK_DDR7 <14>
M_CLK_DDR#7 <14>
DDR_CKE7_DIMM3 <14>
DDR_CS2_DIMM4# <15>
DDR_CS3_DIMM4# <15>
DDR_CS6_DIMM3# <14>
DDR_CS7_DIMM3# <14>
M_ODT2 <15>
M_ODT3 <15>
M_ODT6 <14>
M_ODT7 <14>
DDR_B_DQS#[0..7] <14,15>
DDR_B_DQS[0..7] <14,15>
DDR_B_MA[0..15] <14,15>
TYCO_2134146-3_IVYBRIDGE~D
A A
LinkCISOK
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Ivy Bridge (3/6)
Ivy Bridge (3/6)
Ivy Bridge (3/6)
LA-7931P
LA-7931P
LA-7931P
870Monday, July 23, 2012
870Monday, July 23, 2012
870Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
5
4
3
2
1
CFGStrapsforProcessor
CFG2
D D
JCPU1E
CONN@
1K_0402_5%~D
12
@
RC52
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
KEY
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
CFG0<7>
T60 PAD~D@
T55 PAD~D@
T65 PAD~D@
T64 PAD~D@
T76 PAD~D@
T75 PAD~D@
T2 PAD~D@
T3 PAD~D@
+VCC_GFXCORE
1 2
RC54 49.9_0402_1%~D@
C C
1 2
RC56 49.9_0402_1%~D@
+VCC_CORE
1 2
RC57 49.9_0402_1%~D@
1 2
RC61 49.9_0402_1%~D@
B B
VAXG_VAL_SENSE
12
RC55
@
100_0402_1%~D
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
12
RC58
@
100_0402_1%~D
VSS_VAL_SNESE
T11 PAD~D@
T13 PAD~D@
T72 PAD~D@
T71 PAD~D@
T18PAD~D @
T24PAD~D @
T25PAD~D @
T26PAD~D @
T27PAD~D @
T29PAD~D @
T31PAD~D @
T33PAD~D @
T35PAD~D @
T37PAD~D @
T38PAD~D @
T39PAD~D @
T40PAD~D @
T41PAD~D @
T43PAD~D @
T45PAD~D @
T46PAD~D @
T47PAD~D @
T48PAD~D @
T49PAD~D @
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
VSS_VAL_SNESE
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
CFG
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RESERVED
RSVD_NCTF9
RSVD_NCTF10
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
T4 PAD~D@
T5 PAD~D@
T6 PAD~D@
T7 PAD~D@
T8 PAD~D@
T1 PAD~D@
T9 PAD~D@
T10 PAD~D@
T12 PAD~D@
T14 PAD~D@
T15 PAD~D@
T16 PAD~D@
T17 PAD~D@
T19 PAD~D@
T20 PAD~D@
T21 PAD~D@
T22 PAD~D@
T23 PAD~D@
T28 PAD~D@
T30 PAD~D@
T32 PAD~D@
T34 PAD~D@
T36 PAD~D@
T42 PAD~D@
T44 PAD~D@
CLK_XDP_ITP <7>
CLK_XDP_ITP# <7>
T50 PAD~D@
T51 PAD~D@
T52 PAD~D@
T53 PAD~D@
PEGStaticLaneReversal‐CFG2isforthe16x
1:(Default)NormalOperation;Lane#
definitionmatchessocketpinmapdefinition
CFG2
0:LaneReversed
CFG4
1K_0402_5%~D
12
@
RC53
DisplayPortPresenceStrap
1:Disabled;NoPhysicalDisplayPort
CFG4
attachedtoEmbeddedDisplayPort
0:Enabled;AnexternalDisplayPortdeviceis
connectedtotheEmbeddedDisplayPort
CFG6
CFG5
1K_0402_5%~D
@
RC60
1K_0402_5%~D
12
12
@
RC59
PCIEPortBifurcationStraps
11:(Default)x16‐Device1functions1and2disabled
10:x8,x8‐Device1function1enabled;function2
CFG[6:5]
disabled
01:Reserved‐(Device1function1disabled;function
2enabled)
00:x8,x4,x4‐Device1functions1and2enabled
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
CFG7
1K_0402_5%~D
12
@
RC62
PEGDEFERTRAINING
1:(Default)PEGTrainimmediately
A A
CFG7
followingxxRESETBdeassertion
0:PEGWaitforBIOSfortraining
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Ivy Bridge (4/6)
Ivy Bridge (4/6)
Ivy Bridge (4/6)
LA-7931P
LA-7931P
LA-7931P
970Monday, July 23, 2012
970Monday, July 23, 2012
970Monday, July 23, 2012
1
1.0
1.0
1.0
5
JCPU1F
4
CONN@
POWER
3
2
1
+VCC_CORE
97A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
D D
C C
B B
A A
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
CORE SUPPLY
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
PEG AND DDR
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
8.5A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
+1.05V_RUN_VTT
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
VCCSENSE_R
VSSSENSE_R
VIDSCLK <60>
PlaceRC68,RC69nearCPU
1 2
RC68 0_0402_5%~D@
1 2
RC69 0_0402_5%~D@
10_0402_1%~D
12
RC72
Note:PlacethePUresistorsclosetoCPU
RC63closetoCPU300‐1500mils
H_CPU_SVIDALRT#
+1.05V_RUN_VTT
12
RC65
130_0402_1%~D
12
+1.05V_RUN_VTT
RC7010_0402_1%
VTT_SENSE <58>
VSSIO_SENSE_R <58>
VIDSOUT <60>
RC66
@
1 2
100_0402_1%~D
1 2
RC64 43_0402_5%~D
CADNote:PlacethePU
resistorsclosetoCPU
RC65closetoCPU300‐1500mils
+VCC_CORE
12
RC67
100_0402_1%~D
12
RC71
100_0402_1%~D
+1.05V_RUN_VTT
12
VCCSENSE <60>
VSSSENSE <60>
RC63
75_0402_1%~D
VIDALERT_N <60>
SENSE LINES SVID
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
TYCO_2134146-3_IVYBRIDGE~D
LinkCISOK
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Ivy Bridge (5/6)
Ivy Bridge (5/6)
Ivy Bridge (5/6)
LA-7931P
LA-7931P
LA-7931P
10 70Monday, July 23, 2012
10 70Monday, July 23, 2012
10 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
5
4
3
2
1
+1.5V_CPU_VDDQSource
+3.3V_ALW2
100K_0402_5%~D
Solve300mW
12
RC76
PWRconsumption
2
issue.
RUN_ON_CPU1.5VS3#
DMN66D0LDW-7_SOT363-6~D
61
QC5A
D D
1 2
SIO_SLP_S3#<19,35,47,48,52,56>
CPU1.5V_S3_GATE<49>
RC82 0_0402_5%~D@
1 2
RC83 0_0402_5%~D@
+PWR_SRC_S
330K_0402_5%~D
12
RC73
3
5
4
+1.5V_MEM +1.5V_CPU_VDDQ
RUN_ON_CPU1.5VS3
DMN66D0LDW-7_SOT363-6~D
QC5B
Solve300mW
PWRconsumption
issue.
RUN_ON_CPU1.5VS3# <7,52>
+VCC_GFXCORE
C C
B B
1 2
1 2
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
RC87 1K_0402_5%~D@
RC88 1K_0402_5%~D@
33A
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
JCPU1G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
CONN@
POWER
VSSAXG_SENSE
SENSE
LINES
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
GRAPHICS
DDR3 -1.5V RAILS
VAXG_SENSE
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
AK35
AK34
AL1
B4
D1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
SA RAIL
VCCIO_SEL
H23
C22
C24
A19
+1.8V_RUN
10U_0603_6.3V6M~D
CC88
A A
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CC90
CC89
2
2
1.5A
B6
VCCPLL1
330U_D2_2.5VM_R6M~D
1
+
CC91
2
A6
VCCPLL2
A2
VCCPLL3
TYCO_2134146-3_IVYBRIDGE~D
1.8V RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
LinkCISOK
5
4
Solvebackdrive(followB4).
QC3
AO4304L_SO8
8
7
6
5
4
0.022U_0603_50V7~D
1M_0402_5%~D
12
RC79
1
CC71
2
+VCC_GFXCORE
100_0402_1%~D
12
RC84
100_0402_1%~D
12
RC86
+V_SM_VREF_CNT
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
Checkingagain
5A
1
2
6A
VCCP_PWRCTRL_R
1
2
3
1
2
1 2
RC85
@
100_0402_1%~D
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC75
1
2
10U_0603_6.3V6M~D
1
2
1 2
@
10U_0805_6.3V6M~D
20K_0402_5%~D
12
CC70
@
CC76
CC83
RC89
RC77
10U_0603_6.3V6M~D
CC77
1
2
10U_0603_6.3V6M~D
CC84
1
2
+1.5V_MEM
VCC_AXG_SENSE <60>
VSS_AXG_SENSE <60>
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC78
1
1
2
2
+VCC_SA
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC85
1
1
2
2
0_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+V_DDR_SMREF
1K_0402_1%~D
12
@
RC78
1K_0402_1%~D
12
@
RC80
+1.5V_CPU_VDDQ
330U_D2_2VM_R6M~D
10U_0603_6.3V6M~D
CC79
CC80
1
1
+
2
2
330U_D2_2VM_R6M~D
1
@
CC87
CC86
+
2
VCCSA_SENSE <59>
VCCSA_VID_0 <59>
VCCSA_VID_1 <59>
VCCP_PWRCTRL <58>
1 2
RC74 0_0402_5%~D@
QC4
@
NTR4503NT1G_SOT23-3~D
1
RUN_ON_CPU1.5VS3
CC72 0.1U_0402_10V7K~D
CC73 0.1U_0402_10V7K~D
CC74 0.1U_0402_10V7K~D
CC82 0.1U_0402_10V7K~D
CC81
12
12
12
12
2
3
+1.5V_CPU_VDDQ
1K_0402_1%~D
12
1K_0402_1%~D
12
2
RC75
+V_SM_VREF_CNT
RC81
6A
+1.5V_MEM
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AR25
AR22
AR19
AR16
AR13
AR10
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AJ25
CONN@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
AN7
VSS43
AN4
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
AK7
VSS78
AK4
VSS79
VSS80
TYCO_2134146-3_IVYBRIDGE~D
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
LinkCISOK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Ivy Bridge (6/6)
Ivy Bridge (6/6)
Ivy Bridge (6/6)
LA-7931P
LA-7931P
LA-7931P
11 70Monday, July 23, 2012
11 70Monday, July 23, 2012
11 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
5
4
3
2
1
AllVREFtracesshould
have10miltracewidth
PopulateRD1forIntelDDR3
D D
DDR_A_DQS#[0..7]<8,13>
DDR_A_D[0..63]<8,13>
DDR_A_DQS[0..7]<8,13>
DDR_A_MA[0..15]<8,13>
+1.5V_MEM
+1.5V_MEM
C C
B B
10U_0603_6.3V6M~D
1
2
DIMMSelect
A A
VREFDQmultiplemethodsM1
CD5
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1
2
CD9
CD15
DIMM10
DIMM2
DIMM3
DIMM4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD6
CD3
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD10
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD16
2
2
+3.3V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD4
2
2
10U_0603_6.3V6M~D
CD8
CD7
1
1
2
2
LayoutNote:
PlacenearJDIMM1.203,204
+0.75V_DDR_VTT
1
2
SA01SA1
0
0
1
1
0
1
CD11
CD17
0_0402_5%~D
0_0402_5%~D
+3.3V_RUN
1
2
1
2
DDR_CKE4_DIMM1<8>
M_CLK_DDR4<8>
M_CLK_DDR#4<8>
DDR_CS5_DIMM1#<8>
0.1U_0402_16V4Z~D
1
CD21
2
+DIMM1_VREF_DQ
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
1
CD1
CD2
2
DDR_A_BS2<8,13>
DDR_A_BS0<8,13>
DDR_A_WE#<8,13>
DDR_A_CAS#<8,13>
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
CD22
RD1
@
+V_DDR_REFA_M3
+V_DDR_REF
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_SX_2VY~D
@
1
CD12
CD13
1
2
10K_0402_5%~D
1 2
10K_0402_5%~D
1 2
2
@
RD9
DIMM1_SA0
DIMM1_SA1
RD11
CD14
+
1
2
1U_0402_6.3V6K~D
1
CD18
2
10K_0402_5%~D
RD8
1 2
10K_0402_5%~D
@
RD10
1 2
1 2
1 2
RD2
@
JDIMM1STDTypeH=5.2
DDR_A_D0
DDR_A_D4
DDR_A_D7
DDR_A_D6
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D15
DDR_A_D14
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D19
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D30
DDR_A_D31
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR4
M_CLK_DDR#4
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D44
DDR_A_D45
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D62
DDR_A_D63
DIMM1_SA0
DIMM1_SA1
+1.5V_MEM
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
VSS1849DQ22
51
DQ18
DQ1953VSS19
VSS2055DQ28
57
DQ24
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1~D
CONN@
VREF_CA
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ23
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
+1.5V_MEM
DDR_A_D5
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D12
DDR_A_D13
DDR3_DRAMRST#_R
DDR_A_D10
DDR_A_D11
DDR_A_D20
DDR_A_D21
DDR_A_D18
DDR_A_D22
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D27
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR5
M_CLK_DDR#5
DDR_A_BS1
DDR_A_RAS#
M_ODT4
M_ODT5
DDR_A_D32
DDR_A_D33
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D50
DDR_A_D51
DDR_A_D61
DDR_A_D60
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D58
DDR_A_D59
+0.75V_DDR_VTT
DDR_CKE5_DIMM1 <8>
M_CLK_DDR5 <8>
M_CLK_DDR#5 <8>
DDR_A_BS1 <8,13>
DDR_A_RAS# <8,13>
DDR_CS4_DIMM1# <8>
M_ODT4 <8>
M_ODT5 <8>
Remove0ohm,duetolayoutspacelimitation.
CPU
+DIMM1_VREF_CA
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
CD19
1
1
2
2
CD20
JDIMM3 (Ch B1 H=9.2 STD)
JDIMM1 (Ch A1 H=5.2 STD)
TOP
BOT
JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
+1.5V_MEM
1K_0402_1%~D
12
RD4
DDR3_DRAMRST#_R<13,14,15> DDR3_DRAMRST# <7>
+DIMM0_1_VREF_CPU
DDR_HVREF_RST<7>
+DIMM0_1_CA_CPU
DDR_HVREF_RST
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RD7
@
1 2
0_0402_5%~D
DDR_XDP_WAN_SMBDAT <13,14,15,17,18,35,43>
DDR_XDP_WAN_SMBCLK <13,14,15,17,18,35,43>
1 2
RD3 1K_0402_1%~D
1 2
RD5 0_0402_5%~D@
S
1 2
RD6 0_0402_5%~D@
S
+V_DDR_REF
D
13
QD1
G
BSS138-G_SOT23-3
2
D
13
QD2
G
BSS138-G_SOT23-3
2
+V_DDR_REFA_M3
+V_DDR_REFB_M3
LinkCISOK
0722
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-7931P
LA-7931P
LA-7931P
1
12 70Monday, July 23, 2012
12 70Monday, July 23, 2012
12 70Monday, July 23, 2012
of
of
of
1.0
1.0
1.0
5
4
3
2
1
JDIMM3 (Ch B1 H=9.2 STD)
AllVREFtracesshould
have10miltracewidth
1
+
2
+V_DDR_REFA_M3
+V_DDR_REF
330U_SX_2VY~D
CD36
DDR_A_DQS#[0..7]<8,12>
D D
+1.5V_MEM
+1.5V_MEM
10U_0603_6.3V6M~D
C C
1
2
DDR_A_D[0..63]<8,12>
DDR_A_DQS[0..7]<8,12>
DDR_A_MA[0..15]<8,12>
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD27
2
2
10U_0603_6.3V6M~D
CD30
CD29
1
1
2
2
1U_0402_6.3V6K~D
1
1
CD24
CD25
CD28
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD31
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD32
1
2
10U_0603_6.3V6M~D
@
CD34
CD33
CD35
1
1
2
2
RD14
@
1 2
1 2
RD15
@
0_0402_5%~D
0_0402_5%~D
+DIMM2_VREF_DQ
2.2U_0603_6.3V6K~D
CD26
1
1
2
2
DDR_CKE0_DIMM2<8>
DDR_A_BS2<8,12>
0.1U_0402_16V4Z~D
CD23
LayoutNote:
PlacenearJDIMM3.Pin203,204
M_CLK_DDR0<8>
M_CLK_DDR#0<8>
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD38
CD37
2
2
B B
DIMMSelect
+3.3V_RUN
1 2
SA0 SA1
0 DIMM1
1
DIMM2
00
1
1
0
1
A A
DIMM3
DIMM4
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD40
CD39
2
2
10K_0402_5%~D
10K_0402_5%~D
@
@
RD18
RD17
1 2
DIMM2_SA0
DIMM2_SA1
10K_0402_5%~D
10K_0402_5%~D
RD19
RD20
1 2
+3.3V_RUN
DDR_A_BS0<8,12>
DDR_A_WE#<8,12>
DDR_A_CAS#<8,12>
DDR_CS1_DIMM2#<8>
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
1
1
+0.75V_DDR_VTT +0.75V_DDR_VTT
CD44
CD43
2
2
JDIMM2REVTypeH=5.2
DDR_A_D5
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D12
DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D20
DDR_A_D21
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D22
DDR_A_D28
DDR_A_D29
DDR_A_D26
DDR_A_D27
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D61
DDR_A_D60
DDR_A_D58
DDR_A_D59
DIMM2_SA0
DIMM2_SA1
+1.5V_MEM
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
TYCO_2-2013290-1
CONN@
VREF_CA
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
DQ4
DQ5
DQ6
DQ7
DM1
DM2
DM4
DM6
SDA
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
CK1
104
106
108
BA1
110
112
114
S0#
116
118
120
122
NC2
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
SCL
204
206
G2
+1.5V_MEM
DDR_A_D0
DDR_A_D4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D7
DDR_A_D6
DDR_A_D8
DDR_A_D9
DDR_A_D15
DDR_A_D14
DDR_A_D16
DDR_A_D17
DDR_A_D19
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D34
DDR_A_D35
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
CPU
DDR3_DRAMRST#_R <12,14,15>
DDR_CKE1_DIMM2 <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>
DDR_A_BS1 <8,12>
DDR_A_RAS# <8,12>
DDR_CS0_DIMM2# <8>
M_ODT0 <8>
M_ODT1 <8>
Remove0ohm,duetolayoutspacelimitation.
LinkCISOK
0722
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
JDIMM1 (Ch A1 H=5.2 STD)
TOP
BOT
JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
+DIMM2_VREF_CA
2.2U_0603_6.3V6K~D
CD41
1
2
RD16
@
1 2
0_0402_5%~D
0.1U_0402_16V4Z~D
CD42
1
2
DDR_XDP_WAN_SMBDAT <12,14,15,17,18,35,43>
DDR_XDP_WAN_SMBCLK <12,14,15,17,18,35,43>
+V_DDR_REF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-7931P
LA-7931P
LA-7931P
1
1.0
1.0
13 70Monday, July 23, 2012
13 70Monday, July 23, 2012
13 70Monday, July 23, 2012
1.0
of
of
5
4
3
2
1
RD23
@
1 2
1 2
RD24
@
0_0402_5%~D
0_0402_5%~D
+V_DDR_REFB_M3
DDR_B_DQS#[0..7]<8,15>
D D
C C
DDR_B_D[0..63]<8,15>
DDR_B_DQS[0..7]<8,15>
DDR_B_MA[0..15]<8,15>
+1.5V_MEM
1
2
10U_0603_6.3V6M~D
CD51
+1.5V_MEM
1
2
10U_0603_6.3V6M~D
CD52
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD47
CD48
2
10U_0603_6.3V6M~D
CD53
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD50
CD49
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD55
CD54
CD56
1
1
2
2
+V_DDR_REF
DFX issue solution.
AllVREFtracesshould
have10miltracewidth
10U_0603_6.3V6M~D
330U_SX_2VY~D
@
1
CD58
CD57
1
+
2
2
LayoutNote:
PlacenearJDIMM3.Pin203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
B B
1
CD59
2
DIMMSelect
SA0 SA1
0 DIMM1
1
A A
1
001
0
1
5
1
2
DIMM2
DIMM3
DIMM4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD60
CD61
CD62
2
2
+3.3V_RUN
10K_0402_5%~D
10K_0402_5%~D
RD27
RD26
1 2
1 2
DIMM3_SA0
DIMM3_SA1
10K_0402_5%~D
10K_0402_5%~D
@
@
RD29
RD28
1 2
1 2
4
+DIMM3_VREF_DQ
0.1U_0402_16V4Z~D
2.2U_0402_6.3V6M~D
CD45
1
1
2
2
DDR_CKE6_DIMM3<8>
DDR_B_BS2<8,15>
M_CLK_DDR6<8>
M_CLK_DDR#6<8>
DDR_B_BS0<8,15>
DDR_B_WE#<8,15>
DDR_B_CAS#<8,15>
DDR_CS7_DIMM3#<8>
+3.3V_RUN
0.1U_0402_16V4Z~D
1
CD65
2
CD46
JDIMM3STDTypeH=9.2
JDIMM3
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013310-1~D
LinkCISOK_1006
follow connector list 1005A.
2.2U_0603_6.3V6K~D
1
CD66
2
DDR_B_D4
DDR_B_D5
DDR_B_D2
DDR_B_D3
DDR_B_D12
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR6
M_CLK_DDR#6
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D62
DDR_B_D63
DIMM3_SA0
DIMM3_SA1
+0.75V_DDR_VTT
CONN@
VREF_CA
EVENT#
3
+1.5V_MEM+1.5V_MEM
2
4
DQ4
6
DQ5
8
VSS3
10
12
DQS0
14
VSS6
16
DQ6
18
DQ7
20
VSS8
22
DQ12
24
DQ13
26
VSS10
28
DM1
30
32
34
DQ14
36
DQ15
38
40
DQ20
42
DQ21
44
46
DM2
48
VSS17
50
DQ22
52
DQ23
54
VSS19
56
DQ28
58
DQ29
60
VSS21
62
64
DQS3
66
68
DQ30
70
DQ31
72
74
CKE1
76
VDD2
78
A15
80
A14
82
VDD4
84
A11
86
A7
88
VDD6
90
A6
92
A4
94
VDD8
96
A2
98
A0
100
102
CK1
104
CK1#
106
VDD12
108
BA1
110
RAS#
112
VDD14
114
S0#
116
ODT0
118
VDD16
120
ODT1
122
NC2
124
VDD18
126
128
VSS28
130
DQ36
132
DQ37
134
VSS30
136
DM4
138
VSS31
140
DQ38
142
DQ39
144
VSS33
146
DQ44
148
DQ45
150
VSS35
152
DQS#5
154
DQS5
156
VSS38
158
DQ46
160
DQ47
162
VSS40
164
DQ52
166
DQ53
168
VSS42
170
DM6
172
VSS43
174
DQ54
176
DQ55
178
VSS45
180
DQ60
182
DQ61
184
VSS47
186
DQS#7
188
DQS7
190
VSS50
192
DQ62
194
DQ63
196
VSS52
198
200
SDA
202
SCL
204
VTT2
206
G2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR3_DRAMRST#_R
DDR_B_D10
DDR_B_D11
DDR_B_D20
DDR_B_D21
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR7
M_CLK_DDR#7
DDR_B_BS1
DDR_B_RAS#
M_ODT6
M_ODT7
DDR_B_D32
DDR_B_D33
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D42
DDR_B_D43
DDR_B_D52
DDR_B_D53
DDR_B_D50
DDR_B_D51
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D58
DDR_B_D59
+0.75V_DDR_VTT
DDR3_DRAMRST#_R <12,13,15>
DDR_CKE7_DIMM3 <8>
M_CLK_DDR7 <8>
M_CLK_DDR#7 <8>
DDR_B_BS1 <8,15>
DDR_B_RAS# <8,15>
DDR_CS6_DIMM3# <8>
M_ODT6 <8>
M_ODT7 <8>
DDR_XDP_WAN_SMBDAT <12,13,15,17,18,35,43>
DDR_XDP_WAN_SMBCLK <12,13,15,17,18,35,43>
Dueto+PWR_SRCtracewidthnearbyH16wasn’t
enough,wehavetoincreaseit.soremoveRD30&RD31.
+DIMM3_VREF_CA
2.2U_0603_6.3V6K~D
CD63
1
1
2
2
CPU
0.1U_0402_16V4Z~D
CD64
2
RD25
@
1 2
JDIMM3 (Ch B1 H=9.2 STD)
JDIMM1 (Ch A1 H=5.2 STD)
TOP
BOT
JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
0_0402_5%~D
+V_DDR_REF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT3
DDRIII-SODIMM SLOT3
DDRIII-SODIMM SLOT3
LA-7931P
LA-7931P
LA-7931P
1
14 70Monday, July 23, 2012
14 70Monday, July 23, 2012
14 70Monday, July 23, 2012
of
of
1.0
1.0
1.0
5
4
3
2
1
AllVREFtracesshould
have10miltracewidth
DDR_B_DQS#[0..7]<8,14>
+1.5V_MEM
1
2
DDR_B_D[0..63]<8,14>
DDR_B_DQS[0..7]<8,14>
10U_0603_6.3V6M~D
DDR_B_MA[0..15]<8,14>
CD73
+1.5V_MEM
1
2
10U_0603_6.3V6M~D
CD74
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD68
CD67
2
10U_0603_6.3V6M~D
CD75
1
1
2
2
1U_0402_6.3V6K~D
1
1
CD69
CD70
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD77
CD76
CD78
1
1
2
2
D D
C C
+V_DDR_REFB_M3
+V_DDR_REF
10U_0603_6.3V6M~D
330U_SX_2VY~D
@
1
CD80
CD79
1
+
2
2
RD32
@
1 2
1 2
RD33
@
0_0402_5%~D
0_0402_5%~D
+DIMM4_VREF_DQ
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
CD71
1
1
2
2
DDR_CKE2_DIMM4<8>
DDR_B_BS2<8,14>
CD72
LayoutNote:
PlacenearJDIMM3.Pin203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1
2
CD83
+3.3V_RUN
1 2
1 2
1U_0402_6.3V6K~D
1
CD84
2
10K_0402_5%~D
10K_0402_5%~D
RD36
@
RD35
1 2
DIMM4_SA0
DIMM4_SA1
10K_0402_5%~D
10K_0402_5%~D
@
RD38
RD37
1 2
4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD82
CD81
2
B B
2
DIMMSelect
SA0 SA1
0 DIMM1
1
00
DIMM2
1
1
A A
DIMM3
0
1
DIMM4
5
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8,14>
DDR_B_WE#<8,14>
DDR_B_CAS#<8,14>
DDR_CS3_DIMM4#<8>
+3.3V_RUN
1
2
0.1U_0402_16V4Z~D
1
CD87
2
JDIMM4STDTypeH=5.2
CONN@
JDIMM4
VREF_DQ1VSS1
3
VSS2
DDR_B_D0
DDR_B_D1
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D20
DDR_B_D21
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D52
DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D60
DDR_B_D61
DDR_B_D58
DDR_B_D59
DIMM4_SA0
DIMM4_SA1
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
CD88
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1~D
VREF_CA
LinkCISOK
0722
3
+1.5V_MEM+1.5V_MEM
2
4
DQ4
6
DQ5
8
VSS3
10
DQS#0
12
DQS0
14
VSS6
16
DQ6
18
DQ7
20
VSS8
22
DQ12
24
DQ13
26
VSS10
28
DM1
30
32
34
DQ14
36
DQ15
38
40
DQ20
42
DQ21
44
46
DM2
48
VSS17
50
DQ22
52
DQ23
54
VSS19
56
DQ28
58
DQ29
60
VSS21
62
64
DQS3
66
68
DQ30
70
DQ31
72
74
CKE1
76
VDD2
78
A15
80
A14
82
VDD4
84
A11
86
A7
88
VDD6
90
A6
92
A4
94
VDD8
96
A2
98
A0
100
VDD10
102
CK1
104
CK1#
106
VDD12
108
BA1
110
RAS#
112
VDD14
114
S0#
116
ODT0
118
VDD16
120
ODT1
122
NC2
124
VDD18
126
128
VSS28
130
DQ36
132
DQ37
134
VSS30
136
DM4
138
VSS31
140
DQ38
142
DQ39
144
VSS33
146
DQ44
148
DQ45
150
VSS35
152
DQS#5
154
DQS5
156
VSS38
158
DQ46
160
DQ47
162
VSS40
164
DQ52
166
DQ53
168
VSS42
170
DM6
172
VSS43
174
DQ54
176
DQ55
178
VSS45
180
DQ60
182
DQ61
184
VSS47
186
DQS#7
188
DQS7
190
VSS50
192
DQ62
194
DQ63
196
VSS52
198
EVENT#
200
SDA
202
SCL
204
VTT2
206
G2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D34
DDR_B_D35
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
DIMM4_SMBDAT
DIMM4_SMBCLK
+0.75V_DDR_VTT
CPU
DDR3_DRAMRST#_R <12,13,14>
DDR_CKE3_DIMM4 <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8,14>
DDR_B_RAS# <8,14>
DDR_CS2_DIMM4# <8>
M_ODT2 <8>
M_ODT3 <8>
RD39 0_0402_5%~D@
RD40 0_0402_5%~D@
1 2
1 2
+DIMM4_VREF_CA
1
2
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
CD85
CD86
1
2
2
JDIMM3 (Ch B1 H=9.2 STD)
JDIMM1 (Ch A1 H=5.2 STD)
TOP
BOT
JDIMM2 (Ch A0 H=5.2 REV) JDIMM4 (Ch B0 H=5.2 STD)
RD34
@
1 2
0_0402_5%~D
DDR_XDP_WAN_SMBDAT <12,13,14,17,18,35,43>
DDR_XDP_WAN_SMBCLK <12,13,14,17,18,35,43>
+V_DDR_REF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM SLOT4
DDRIII-SODIMM SLOT4
DDRIII-SODIMM SLOT4
LA-7931P
LA-7931P
LA-7931P
1
1.0
1.0
15 70Monday, July 23, 2012
15 70Monday, July 23, 2012
15 70Monday, July 23, 2012
1.0
of
of
5
+MXM_PWR_SRC
+5V_MXM
PEG_CRX_GTX_C_P[0..15]
PEG_CRX_GTX_C_N[0..15]
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
JMXM1A
1
PWR_SRC
3
PWR_SRC
5
PWR_SRC
7
PWR_SRC
9
PWR_SRC
11
PWR_SRC
13
PWR_SRC
15
PWR_SRC
17
PWR_SRC
19
GND
21
GND
23
GND
25
GND
27
GND
29
GND
31
GND
33
GND
35
GND
37
5V
39
5V
41
5V
43
5V
45
5V
47
GND
49
GND
51
GND
53
GND
55
PEX_STD_SW#
57
VGA_DISABLE#
59
PNL_PWR_EN
61
PNL_BL_EN
63
PNL_BL_PWM
65
HDMI_CEC
67
DVI_HPD
69
LVDS_DDC_DAT
71
LVDS_DDC_CLK
73
GND
75
OEM
77
OEM
79
OEM
81
OEM
83
GND
85
PEX_RX15#
87
PEX_RX15
89
GND
91
PEX_RX14#
93
PEX_RX14
95
GND
97
PEX_RX13#
99
PEX_RX13
101
GND
103
PEX_RX12#
105
PEX_RX12
107
GND
109
PEX_RX11#
111
PEX_RX11
113
GND
115
PEX_RX10#
117
PEX_RX10
119
GND
121
PEX_RX9#
123
PEX_RX9
125
GND
127
PEX_RX8#
129
PEX_RX8
131
GND
133
PEX_RX7#
135
PEX_RX7
137
GND
139
PEX_RX6#
141
PEX_RX6
143
GND
145
PEX_RX5#
147
PEX_RX5
149
GND
151
PEX_RX4#
153
PEX_RX4
155
GND
157
PEX_RX3#
159
PEX_RX3
161
GND
JAE_MM70-314-310B1-1-R300
PEG_CRX_GTX_C_P[0..15]<6>
PEG_CRX_GTX_C_N[0..15]<6>
PEG_CTX_GRX_P[0..15]<6>
PEG_CTX_GRX_N[0..15]<6>
D D
+5V_MXM
10U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
C328
1
1
C7
2
2
100mil(2.5A, 5VIA)
1 2
R1970 0_0402_5%~D@
1 2
R1971 0_0402_5%~D@
MXM_ENVDD<28>
C C
B B
MXM_PANEL_BKEN<28>
MXM_BIA_PWM<28>
MXM_LVDS_DDC_DAT<27>
MXM_LVDS_DDC_CLK<27>
PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P15
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_P3
CONN@
E1 E2
E3 E4
+3.3V_MXM
1 2
R3 4.3K_0402_5%@
1 2
R5 4.3K_0402_5%@
1 2
R8 10K_0402_5%~D
1 2
R7 10K_0402_5%~D
Heightlimitationissue.
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT_R#
WAKE#
PWR_GOOD
PWR_EN
RSVD
RSVD
RSVD
RSVD
PWR_LEVEL
TH_OVERT#
TH_ALERT#
TH_PWM
GPIO0
GPIO1
GPIO2
SMB_DAT
SMB_CLK
GND
OEM
OEM
OEM
OEM
GND
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
LinkCISOK
0722
+3.3V_ALW +3.3V_RUN
0.1U_0402_10V7K~D
+3.3V_MXM
1
C90
RV29
750_0402_1%~D
DGPU_PEX_RST#
MeethighlevelforDGPU_PEX_RST#
onN14P
A A
MXM_DPC_HPD
MXM_MB_DP_HPD
DPC_GPU_HPD
2
1 2
4
Y
DV2
2 1
RB751VM-40TE-17_SOD323-2~D
DV3
2 1
RB751VM-40TE-17_SOD323-2~D
DV4
2 1
RB751VM-40TE-17_SOD323-2~D
5
100K_0402_5%~D
12
R36
5
1
B
VCC
2
A
G
U16
3
MC74VHC1G09DFT2G_SC70-5
DGPU_HOLD_RST# <21>
PLTRST_GPU# <20>
MXM_DP_HDMI_HPD <48>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
DGPU_PWROK<21,48>
DPC_GPU_HPD_GATE
4
MXM_CRT_DDC_DAT
MXM_CRT_DDC_CLK
DGPU_PWR_GOOD
MXM_CLK_REQ#
400mil(10A)
10U_0805_25V6K~D
1
C2
2
1 2
R1972 0_0402_5%~D@
DGPU_PWR_GOOD
MXM_PWR_LEVEL
MXM_OVERT#
MXM_ALERT#
GPU_SMBDAT_R
GPU_SMBCLK_R
SYSTEM
PEG_CTX_GRX_N15
PEG_CTX_GRX_P15
PEG_CTX_GRX_N14
PEG_CTX_GRX_P14
PEG_CTX_GRX_N13
PEG_CTX_GRX_P13
PEG_CTX_GRX_N12
PEG_CTX_GRX_P12
PEG_CTX_GRX_N11
PEG_CTX_GRX_P11
PEG_CTX_GRX_N10
PEG_CTX_GRX_P10
PEG_CTX_GRX_N9
PEG_CTX_GRX_P9
PEG_CTX_GRX_N8
PEG_CTX_GRX_P8
PEG_CTX_GRX_N7
PEG_CTX_GRX_P7
PEG_CTX_GRX_N6
PEG_CTX_GRX_P6
PEG_CTX_GRX_N5
PEG_CTX_GRX_P5
PEG_CTX_GRX_N4
PEG_CTX_GRX_P4
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
74AHC1G08GW_SOT353-5~D
C1330
100K_0402_5%~D
@
R758
1 2
4
680P_0603_50V7K~D
1
C3
2
0.1U_0402_10V7K~D
C91
U8
0.1U_0402_10V7K~D
1
2
4
+MXM_PWR_SRC
68P_0402_50V8J~D
0.1U_0603_25V7K~D
1
1
C4
2
2
+3.3V_RUN
1
2
5
P
IN1
4
O
IN2
G
3
+3.3V_MXM
5
1
P
IN1
O
2
IN2
G
U641
3
74AHC1G08GW_SOT353-5~D
C1
MXM_PRESENTR# <21>
PCIE_WAKE# <42,43,47,49>
DGPU_PWR_EN <48>
LVDS_Upper/even
HDMI/DockingDP
MUX
1
DGPU_PWR_GOOD
2
DGPU_PWR_EN
DGPU_PWROK
DPC_GPU_HPD <46>
MBDP
3
+3.3V_MXM
10K_0402_5%~D
R4
MXM_ALERT#
CLK_PCIE_VGA#<18>
CLK_PCIE_VGA<18>
2011/09/01 change.
MXM_LVDS_BCLK-<27>
MXM_LVDS_BCLK+<27>
MXM_LVDS_B2-<27>
MXM_LVDS_B2+<27>
MXM_LVDS_B1-<27>
MXM_LVDS_B1+<27>
MXM_LVDS_B0-<27>
MXM_LVDS_B0+<27>
MXM_DPC_N0<34>
MXM_DPC_P0<34>
MXM_DPC_N1<34>
MXM_DPC_P1<34>
MXM_DPC_N2<34>
MXM_DPC_P2<34>
MXM_DPC_N3<34>
MXM_DPC_P3<34>
MXM_DPC_AUX#<34,45>
MXM_DPC_AUX<34,45>
MXM_MB_DP_N0<29>
MXM_MB_DP_P0<29>
MXM_MB_DP_N1<29>
MXM_MB_DP_P1<29>
MXM_MB_DP_N2<29>
MXM_MB_DP_P2<29>
MXM_MB_DP_N3<29>
MXM_MB_DP_P3<29>
MXM_MB_DP_AUX#<29>
MXM_MB_DP_AUX<29>
MXM_PRESENTL#<21>
C1328
MXM_DPC_HPD_GATE
100K_0402_5%~D
@
R2124
1 2
DYN_TURB_GPU_PWR_ALRT#<26,49>
3
2
+3.3V_MXM
4.7K_0402_5%~D
4.7K_0402_5%~D
12
12
@
PEX_TX2#
PEX_TX2
PEX_TX1#
PEX_TX1
PEX_TX0#
PEX_TX0
PEX_RST#
VGA_DDC_DAT
VGA_DDC_CLK
VGA_VSYNC
VGA_HSYNC
VGA_RED
VGA_GREEN
VGA_BLUE
LVDS_LCLK#
LVDS_LCLK
LVDS_LTX3#
LVDS_LTX3
LVDS_LTX2#
LVDS_LTX2
LVDS_LTX1#
LVDS_LTX1
LVDS_LTX0#
LVDS_LTX0
DP_D_L0#
DP_D_L0
DP_D_L1#
DP_D_L1
DP_D_L2#
DP_D_L2
DP_D_L3#
DP_D_L3
DP_D_AUX#
DP_D_AUX
DP_C_HPD
DP_D_HPD
RSVD
RSVD
RSVD
DP_B_L0#
DP_B_L0
DP_B_L1#
DP_B_L1
DP_B_L2#
DP_B_L2
DP_B_L3#
DP_B_L3
DP_B_AUX#
DP_B_AUX
DP_B_HPD
DP_A_HPD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3V3
3V3
GND
R1
DMN66D0LDW-7_SOT363-6~D
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270
272
274
276
278
280
282
284
286
288
290
292
294
296
298
300
302
304
306
308
312
12
G
2
13
D
S
Q5
SSM3K7002FU_SC70-3~D
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P0
CLK_PCIE_VGA#
CLK_PCIE_VGA
MXM_LVDS_BCLKMXM_LVDS_BCLK+
MXM_LVDS_B2MXM_LVDS_B2+
MXM_LVDS_B1MXM_LVDS_B1+
MXM_LVDS_B0MXM_LVDS_B0+
MXM_DPC_N0
MXM_DPC_P0
MXM_DPC_N1
MXM_DPC_P1
MXM_DPC_N2
MXM_DPC_P2
MXM_DPC_N3
MXM_DPC_P3
MXM_DPC_AUX#
MXM_DPC_AUX
MXM_MB_DP_N0
MXM_MB_DP_P0
MXM_MB_DP_N1
MXM_MB_DP_P1
MXM_MB_DP_N2
MXM_MB_DP_P2
MXM_MB_DP_N3
MXM_MB_DP_P3
MXM_MB_DP_AUX#
MXM_MB_DP_AUX
MXM_PRESENTL#
DGPU_ALERT# <48>
JMXM1B
CONN@
163
GND
165
PEX_RX2#
167
PEX_RX2
169
GND
171
PEX_RX1#
173
PEX_RX1
175
GND
177
PEX_RX0#
179
PEX_RX0
181
GND
183
PEX_REFCLK#
185
PEX_REFCLK
187
GND
189
RSVD
191
RSVD
193
RSVD
195
RSVD
197
RSVD
199
LVDS_UCLK#
201
LVDS_UCLK
203
GND
205
LVDS_UTX3#
207
LVDS_UTX3
209
GND
211
LVDS_UTX2#
213
LVDS_UTX2
215
GND
217
LVDS_UTX1#
219
LVDS_UTX1
221
GND
223
LVDS_UTX0#
225
LVDS_UTX0
227
GND
229
DP_C_L0#
231
DP_C_L0
233
GND
235
DP_C_L1#
237
DP_C_L1
239
GND
241
DP_C_L2#
243
DP_C_L2
245
GND
247
DP_C_L3#
249
DP_C_L3
251
GND
253
DP_C_AUX#
255
DP_C_AUX
257
RSVD
259
RSVD
261
RSVD
263
RSVD
265
RSVD
267
RSVD
269
RSVD
271
RSVD
273
RSVD
275
RSVD
277
RSVD
279
RSVD
281
GND
283
DP_A_L0#
285
DP_A_L0
287
GND
289
DP_A_L1#
291
DP_A_L1
293
GND
295
DP_A_L2#
297
DP_A_L2
299
GND
301
DP_A_L3#
303
DP_A_L3
305
GND
307
DP_A_AUX#
309
DP_A_AUX
310
PRSNT_L#
311
GND
JAE_MM70-314-310B1-1-R300
GPU_SMBDAT_R
GPU_SMBCLK_R
PEX_CLK_REQ#
LinkCISOK
+3.3V_MXM
+3.3V_MXM
0.1U_0402_10V7K~D
1
2
5
1
DGPU_PWROK
P
IN1
4
O
2
MXM_DPC_HPD <34>
IN2
G
U640
3
74AHC1G08GW_SOT353-5~D
+3.3V_MXM
MXM_PWR_LEVEL
D102
RB751VM-40TE-17_SOD323-2~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_ALW
100K_0402_5%~D
12
R2063
4
Y
@
21
MXM_MB_DP_HPD_GATE
0.1U_0402_10V7K~D
1
C1264
2
5
1
B
VCC
2
A
G
U634
3
MC74VHC1G09DFT2G_SC70-5
2
0.1U_0402_10V7K~D
1
C1329
2
4
U639
74AHC1G08GW_SOT353-5~D
ACAV_IN <25,49,62,63>
GPU_PWR_LEVEL <48>
O
+3.3V_MXM
@
R2
5
DMN66D0LDW-7_SOT363-6~D
3
4
Q295B
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
MXM_CLK_REQ#
DGPU_PEX_RST#
MXM_CRT_VSYNC
MXM_CRT_HSYNC
MXM_CRT_RED
MXM_CRT_GRN
MXM_CRT_BLU
MXM_LVDS_ACLKMXM_LVDS_ACLK+
MXM_LVDS_A2MXM_LVDS_A2+
MXM_LVDS_A1MXM_LVDS_A1+
MXM_LVDS_A0MXM_LVDS_A0+
MXM_EDP_TX0MXM_EDP_TX0+
MXM_EDP_TX1MXM_EDP_TX1+
MXM_EDP_C_AUXMXM_EDP_C_AUX+
MXM_DPC_HPD_GATE
MXM_EDP_HPD
1 2
R2194 0_0402_5%~D@
1 2
R2195 0_0402_5%~D@
MXM_DPB_N0
MXM_DPB_P0
MXM_DPB_N1
MXM_DPB_P1
MXM_DPB_N2
MXM_DPB_P2
MXM_DPB_N3
MXM_DPB_P3
MXM_DPB_AUX#
MXM_DPB_AUX
DPC_GPU_HPD_GATE
MXM_MB_DP_HPD_GATE
40mil(1A)
2
Q295A
+3.3V_MXM
61
C1297 0.1U_0402_10V6K~D6@
C1298 0.1U_0402_10V6K~D6@
GPU_SMBDAT <49>
GPU_SMBCLK <49>
MXM_CRT_DDC_DAT <32>
MXM_CRT_DDC_CLK <32>
MXM_CRT_VSYNC <32>
MXM_CRT_HSYNC <32>
MXM_CRT_RED <32>
MXM_CRT_GRN <32>
MXM_CRT_BLU <32>
MXM_LVDS_ACLK- <27>
MXM_LVDS_ACLK+ <27>
MXM_LVDS_A2- <27>
MXM_LVDS_A2+ <27>
MXM_LVDS_A1- <27>
MXM_LVDS_A1+ <27>
MXM_LVDS_A0- <27>
MXM_LVDS_A0+ <27>
MXM_EDP_TX0- <30>
MXM_EDP_TX0+ <30>
MXM_EDP_TX1- <30>
MXM_EDP_TX1+ <30>
1 2
1 2
MXM_EDP_HPD <30>
+3.3V_MXM
MXM_DPB_N0 <46>
MXM_DPB_P0 <46>
MXM_DPB_N1 <46>
MXM_DPB_P1 <46>
MXM_DPB_N2 <46>
MXM_DPB_P2 <46>
MXM_DPB_N3 <46>
MXM_DPB_P3 <46>
MXM_DPB_AUX# <33>
MXM_DPB_AUX <33>
changefrom+3.3V_RUNto+3.3V_AVDD.
MXM_EDP_AUX-
MXM_EDP_AUX+
change to 6@ for only 10-bit panel use.
5
1
DGPU_PWROK
P
IN1
2
MXM_MB_DP_HPD <29>
IN2
G
3
+3.3V_MXM
10K_0402_5%~D
R10
MXM_OVERT#
+3.3V_ALW
12
G
2
13
D
S
Q4
SSM3K7002FU_SC70-3~D
10K_0402_5%~D
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MXM3
MXM3
MXM3
LA-7931P
LA-7931P
LA-7931P
1
2011/09/01 change.
LVDS_Lower/odd
MXM_EDP_AUX- <30>
MXM_EDP_AUX+ <30>
ForNVDIArequest.
DMC/DockingDP
MUX
R2095
6@
1 2
1 2
R2096
6@
+3.3V_MXM
10U_0603_6.3V6M~D
1
2
R11
DGPU_THERMTRIP# <25>
1
CRT
100K_0402_5%~D
100K_0402_5%~D
0.1U_0402_16V4Z~D
1
C332
C8
2
16 70Monday, July 23, 2012
16 70Monday, July 23, 2012
16 70Monday, July 23, 2012
of
eDP
+3.3V_AVDD
1.0
1.0
1.0
5
+3.3V_ALW_PCH
12
RH66
1K_0402_1%~D
PCH_AZ_SYNC
12
D D
C C
B B
RH282
100K_0402_5%~D
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
+RTC_CELL
12
RH38
330K_0402_1%~D
PCH_INTVRMEN
12
@
330K_0402_1%~D
INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable Internal VRs
Low - Enable External VRs
1 2
RH31 1M_0402_5%~D
PCH_AZ_SYNCissampled
attherisingedgeofRSMRST#pin.
SosignalshouldbePUtotheALWAYSrail.
@
RH39
Shunt
Open
ME_CLR1
TPM setting
Shunt Clear ME RTC Registers
Keep ME RTC Registers
Open
PCH_AZ_CODEC_SDOUT<47>
PCH_AZ_CODEC_SYNC<47>
PCH_AZ_CODEC_RST#<47>
PCH_AZ_CODEC_BITCLK<47>
CMOS settingCMOS_CLR1
Clear CMOS
Keep CMOS
27P_0402_50V8J~D
1
@
ME1 SHORT PADS~D
@
CH101
RH22 20K_0402_5%~D
+RTC_CELL
RH23 20K_0402_5%~D
RH11 1M_0402_5%~D
2
1
2
1 2
CH5 1U_0402_6.3V6K~D
+3.3V_ALW_PCH
12
JTAG@
RH288
0_0603_5%~D
+3.3V_ALW_PCH_JTAG
1 2
RH29 33_0402_5%~D
RH27 33_0402_5%~D
RH41 33_0402_5%~D
RH25 33_0402_5%~D
1
2
+5V_RUN
G
2
S
PCH_AZ_SDOUT
1 2
PCH_AZ_SYNC_Q
1 2
PCH_AZ_RST#
1 2
PCH_AZ_BITCLK
QH7
SSM3K7002FU_SC70-3~D
13
PCH_AZ_SYNCPCH_AZ_SYNC_Q
D
SLP_ME_CSW_DEV#<21,48>
PCH_GPIO35<21>
1 2
1 2
1 2
INTELHDA_SYNCisolationcircuit
A A
1 2
SPI_PCH_CS0# SPI_PCH_CS0#_R
R963 47_0402_5%~D
1 2
SPI_PCH_DIN SPI_DIN64
R894 33_0402_5%~D
SPI_WP#_SEL<48>
1 2
R898 0_0402_5%~D@
5
R890
3.3K_0402_5%~D
SPI_WP#_SEL_R
12
200 MIL SO8
64Mb Flash ROM
U52
X76@
1
/CS
2
DO
3
/WP
GND4DIO
CreateX76BOMfor2ndsource.
USB_OC0#_R<20>
USB_OC1#_R<20>
USB_OC2#<20>
USB_OC3#<20,47>
USB_OC4#_R<20>
USB_OC5#<20>
USB_OC6#<20>
SIO_EXT_SMI#<20,49>
PCH_GPIO36<21>
PCH_GPIO37<21>
PCH_GPIO16<21>
TEMP_ALERT#<21,48>
PCH_GPIO15<21>
SIO_EXT_SCI#_R<21>
PCH_RSMRST#_Q<19,50>
Crystal EA.
1
@
CMOS1 SHORT PADS~D
CH4
CMOS place near DIMM
U52
U53
+3.3V_SPI
8
VCC
7
/HOLD
6
CLK
5
W25Q64FVSSIG_SO8~D
4
Pop them until ST.
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
SLP_ME_CSW_DEV#
PCH_GPIO35
HDD_DET#_R
BBS_BIT0_R
PCH_GPIO36
PCH_GPIO37
PCH_GPIO16
TEMP_ALERT#
PCH_GPIO15
SIO_EXT_SCI#_R
PCH_RSMRST#_Q RSMRST#_XDP
CH2
18P_0402_50V8J~D
12
12
CH3
18P_0402_50V8J~D
12
PCH_RTCX2_R PCH_RTCX2
2
1
2
1 2
1U_0402_6.3V6K~D
+3.3V_ALW_PCH
ME_FWP<48>
12
RH59 51_0402_1%~DJTAG@
12
RH44 200_0402_1%~DJTAG@
12
RH45 200_0402_1%~DJTAG@
12
RH43 200_0402_1%~DJTAG@
Pop them until ST.
1 2
RH51 33_0402_5%~DPXDP@
1 2
RH7 33_0402_5%~DPXDP@
1 2
RH16 33_0402_5%~DPXDP@
1 2
RH5 33_0402_5%~DPXDP@
1 2
RH6 33_0402_5%~DPXDP@
1 2
RH14 33_0402_5%~DPXDP@
1 2
RH8 33_0402_5%~DPXDP@
1 2
RH9 33_0402_5%~DPXDP@
1 2
RH10 33_0402_5%~DPXDP@
1 2
RH12 33_0402_5%~DPXDP@
1 2
RH13 33_0402_5%~DPXDP@
1 2
RH26 33_0402_5%~DPXDP@
1 2
RH20 33_0402_5%~DPXDP@
1 2
RH34 33_0402_5%~DPXDP@
1 2
RH17 33_0402_5%~DPXDP@
1 2
RH18 33_0402_5%~DPXDP@
1 2
RH19 33_0402_5%~DPXDP@
1 2
RH53 33_0402_5%~DPXDP@
1 2
RH24 1K_0402_1%~DPXDP@
PCH_RTCX1
YH1
32.768KHZ_12.5PF_Q13FC1350000~D
1 2
RH286 0_0402_5%~D@
SPKR<47>
PCH_AZ_CODEC_SDIN0<47>
1 2
RH287 1K_0402_1%~D@
1 2
RH50 1K_0402_1%~D
100_0402_1%~DJTAG@
100_0402_1%~DJTAG@
12
12
12
RH48
RH49
12
100_0402_1%~DJTAG@
RH47
BIOS ROM Select Component
SPI_HOLD#
SPI_PCH_CLK
SPI_PCH_DO
X76(2nd)
X7640631L03
EON
SA000046400
(EN25Q64-104HIP)
SA00004LI00
(EN25Q32B-104HIP)
X76(Main)
X7640631L01
WINBOND
SA000039A2L
(W25Q64FVSSIG)
SA00003K80L
(W25Q32BVSSIG)
12
3.3K_0402_5%~D
1 2
SPI_CLK64
R899 33_0402_5%~D
1 2
SPI_DO64
R901 33_0402_5%~D
4
C787
1 2
0.1U_0402_25V6K~D
R891
3
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17
RH15
10M_0402_5%~D
PCH_RTCRST#
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_SDOUT
PCH_GPIO33
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
A20
C20
D20
G22
K22
C17
N34
K34
E34
G34
C34
A34
A36
C36
N32
Y14
SPI_PCH_CS1# SPI_PCH_CS1#_R
SPI_PCH_DIN SPI_DIN32
SPI_WP#_SEL_R
@
33_0402_5%~D
SPI_CLK32
@
33_0402_5%~D
SPI_CLK64
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DDR_XDP_WAN_SMBDAT<12,13,14,15,18,35,43>
DDR_XDP_WAN_SMBCLK<12,13,14,15,18,35,43>
UH4A
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
BD82PPSM-QNHN-A0_BGA989~D
1 2
R936 47_0402_5%~D
1 2
R895 33_0402_5%~D
R2065
R2066
12
12
C1265
@
10P_0402_50V8J~D
1 2
C1266
@
10P_0402_50V8J~D
1 2
Pop them until ST.
+3.3V_ALW_PCH
1.05V_0.8V_PWROK<49,60>
SIO_PWRBTN#_R<7,19>
RH284 0_0402_5%~DPXDP@
RH285 0_0402_5%~D
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
FWH4 / LFRAME#
LDRQ1# / GPIO23
RTCIHDA
SATA 6G
SATA
SATAICOMPO
SATAICOMPI
JTAG
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATA0GP / GPIO21
SPI
SATA1GP / GPIO19
200 MIL SO8
32Mb Flash ROM
U53
1
CS#
2
DO
3
WP#
4
GND
W25Q32BVSSIG_SO8~D
CreateX76BOMfor2ndsource.
0.1U_0402_25V6K~D
PXDP@
1
CH1
2
RH283 1K_0402_1%~DPXDP@
1 2
1 2
RH21 0_0402_5%~D
PXDP@
1 2
DDR_XDP_WAN_SMBDAT_R2
1 2
DDR_XDP_WAN_SMBCLK_R2
PXDP@
C38
A38
B37
C37
D36
E36
LDRQ0#
K36
V5
SERIRQ
AM3
SATA0RXN
AM1
SATA0RXP
AP7
SATA0TXN
AP5
SATA0TXP
AM10
SATA1RXN
AM8
SATA1RXP
AP11
SATA1TXN
AP10
SATA1TXP
AD7
SATA2RXN
AD5
SATA2RXP
AH5
SATA2TXN
AH4
SATA2TXP
AB8
SATA3RXN
AB10
SATA3RXP
AF3
SATA3TXN
AF1
SATA3TXP
Y7
SATA4RXN
Y5
SATA4RXP
AD3
SATA4TXN
AD1
SATA4TXP
Y3
SATA5RXN
Y1
SATA5RXP
AB3
SATA5TXN
AB1
SATA5TXP
Y11
Y10
AB12
AB13
AH1
P3
SATALED#
V14
P1
X76@
VCC
HOLD#
CLK
DI
2
1.05V_0.8V_PWROK_R
PCH_PWRBTN#_XDP
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
LPC_LDRQ1#
IRQ_SERIRQ
SATA_COMP
SATA3_COMP
RBIAS_SATA3
SATA_ACT#
HDD_DET#_R
BBS_BIT0_R
+3.3V_SPI
8
7
6
5
SPI_DO32
2
+3.3V_ALW_PCH
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
LPC_LAD0 <41,42,48,49>
LPC_LAD1 <41,42,48,49>
LPC_LAD2 <41,42,48,49>
LPC_LAD3 <41,42,48,49>
LPC_LFRAME# <41,42,48,49>
LPC_LDRQ1# <48>
IRQ_SERIRQ <41,48,49>
PSATA_PRX_DTX_N0_C <35>
PSATA_PRX_DTX_P0_C <35>
PSATA_PTX_DRX_N0_C <35>
PSATA_PTX_DRX_P0_C <35>
SATA_NVRAM_PRX_DTX_N2_C <43>
SATA_NVRAM_PRX_DTX_P2_C <43>
SATA_NVRAM_PTX_DRX_N2_C <43>
SATA_NVRAM_PTX_DRX_P2_C <43>
SATA_ODD_PRX_DTX_N3_C <36>
SATA_ODD_PRX_DTX_P3_C <36>
SATA_ODD_PTX_DRX_N3_C <36>
SATA_ODD_PTX_DRX_P3_C <36>
ESATA_PRX_DTX_N4_C <39>
ESATA_PRX_DTX_P4_C <39>
ESATA_PTX_DRX_N4_C <39>
ESATA_PTX_DRX_P4_C <39>
SATA_PRX_DKTX_N5_C <46>
SATA_PRX_DKTX_P5_C <46>
SATA_PTX_DKRX_N5_C <46>
SATA_PTX_DKRX_P5_C <46>
1 2
RH40 37.4_0402_1%~D
1 2
RH42 49.9_0402_1%~D
1 2
RH46 750_0402_1%~D
SATA_ACT# <51>
RH290 0_0402_5%~D@
+3.3V_SPI
C788
1 2
0.1U_0402_25V6K~D
1 2
R897 33_0402_5%~D
1 2
R900 33_0402_5%~D
1
JXDP2
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A CONN@
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
GND17
2
4
XDP_FN16
6
XDP_FN17
8
10
XDP_FN8
12
XDP_FN9
14
16
XDP_FN10
18
XDP_FN11
20
22
24
26
28
XDP_FN12
30
XDP_FN13
32
34
XDP_FN14
36
XDP_FN15
38
40
42
44
46
RSMRST#_XDP
48
XDP_DBRESET#
50
52
PCH_JTAG_TDO
TD0
54
56
PCH_JTAG_TDI
TDI
58
PCH_JTAG_TMSPCH_JTAG_TCK
TMS
60
LinkCISOK
0722
+1.05V_RUN
+1.05V_RUN
1 2
SPI_HOLD#
SPI_PCH_CLKSPI_CLK32
SPI_PCH_DO
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
PCH_GPIO33
IRQ_SERIRQ
BBS_BIT0_R
HDD1_DET#
SPKR
No Reboot Strap
SPKR
HDD1
NVRAM
ODD
E-SATA
DOCK
HDD1_DET# <35>
12
SPI_PCH_CS1#
PCH_SPI_CS1#
RH3450_0402_5%~D
12
SPI_PCH_DO
PCH_SPI_DO
RH3460_0402_5%~D
12
SPI_PCH_DIN
PCH_SPI_DIN
RH3470_0402_5%~D
12
SPI_PCH_CLK
PCH_SPI_CLK
RH3480_0402_5%~D
12
SPI_PCH_CS0#
PCH_SPI_CS0#
RH3490_0402_5%~D
+3.3V_M
12
RH3500_0402_5%~D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PCH (1/8)
PCH (1/8)
PCH (1/8)
LA-7931P
LA-7931P
LA-7931P
1
Low = Default
High = No Reboot
Followconnlist1223A.
LinkCISOK
0109
+3.3V_ALW_PCH
XDP_DBRESET# <7,19>
1 2
RH355100K_0402_5%~D
1 2
RH288.2K_0402_5%~D
1 2
RH524.7K_0402_5%~D
1 2
RH3010K_0402_5%~D
1 2
RH3510K_0402_5%~D @
CONN@
JSPI1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
GND
18
GND
TYCO_1-2041070-6~D
17 70Monday, July 23, 2012
17 70Monday, July 23, 2012
17 70Monday, July 23, 2012
+3.3V_RUN
+3.3V_RUN
of
1.0
1.0
1.0
5
D D
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5
PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
PCIE_PRX_MMITX_N8
PCIE_PRX_MMITX_P8
PCIE_PTX_MMIRX_N8
PCIE_PTX_MMIRX_P8
RH307 0_0402_5%~D@
RH308 0_0402_5%~D@
RH81 10K_0402_5%~D
RH82 0_0402_5%~D@
RH83 0_0402_5%~D@
RH85 0_0402_5%~D@
RH86 0_0402_5%~D@
1 2
RH87 10K_0402_5%~D
RH88 0_0402_5%~D@
RH90 0_0402_5%~D@
RH152 10K_0402_5%~D
RH92 0_0402_5%~D@
RH93 0_0402_5%~D@
RH94 10K_0402_5%~D
RH95 0_0402_5%~D@
RH96 0_0402_5%~D@
RH97 10K_0402_5%~D
1 2
RH98 10K_0402_5%~D
1 2
RH368 10K_0402_5%~D
1 2
RH369 10K_0402_5%~D
1 2
RH280 0_0402_5%~D@
1 2
RH281 0_0402_5%~D@
WWAN/
NVRAM (Mini Card 2)--->
WLAN (Mini Card 1)--->
EXPRESS Card--->
PP (Mini Card 3)--->
C C
10/100/1G LAN --->
MMI --->
WWAN/
NVRAM (Mini Card 2)--->
10/100/1G LAN --->
MMI --->
B B
PP (Mini Card 3)--->
Express card--->
WLAN (Mini Card 1)--->
A A
PCIEREQpowerrail:
Suspend:034567
PCIE_PTX_WANRX_N1<43>
PCIE_PTX_WANRX_P1<43>
PCIE_PTX_WLANRX_N2<42>
PCIE_PTX_WLANRX_P2<42>
PCIE_PTX_EXPRX_N3<47>
PCIE_PTX_EXPRX_P3<47>
PCIE_PRX_WPANTX_N5<42>
PCIE_PRX_WPANTX_P5<42>
PCIE_PTX_WPANRX_N5<42>
PCIE_PTX_WPANRX_P5<42>
PCIE_PTX_GLANRX_N7<37>
PCIE_PTX_GLANRX_P7<37>
PCIE_PTX_MMIRX_N8<47>
PCIE_PTX_MMIRX_P8<47>
PCIE_PRX_WANTX_N1<43>
PCIE_PRX_WANTX_P1<43>
PCIE_PRX_WLANTX_N2<42>
PCIE_PRX_WLANTX_P2<42>
PCIE_PRX_EXPTX_N3<47>
PCIE_PRX_EXPTX_P3<47>
PCIE_PRX_GLANTX_N7<37>
PCIE_PRX_GLANTX_P7<37>
PCIE_PRX_MMITX_N8<47>
PCIE_PRX_MMITX_P8<47>
CLK_PCIE_MINI1#<43>
CLK_PCIE_MINI1<43>
+3.3V_ALW_PCH
MINI1CLK_REQ#<43>
CLK_PCIE_LAN#<37>
CLK_PCIE_LAN<37>
LANCLK_REQ#<37>
CLK_PCIE_CARD#<47>
CLK_PCIE_CARD<47>
+3.3V_RUN
CARDCLK_REQ#<47>
CLK_PCIE_MINI3#<42>
CLK_PCIE_MINI3<42>
+3.3V_ALW_PCH
MINI3CLK_REQ#<42>
CLK_PCIE_EXP#<47>
CLK_PCIE_EXP<47>
+3.3V_ALW_PCH
EXPCLK_REQ#<47>
CLK_PCIE_MINI2#<42>
CLK_PCIE_MINI2<42>
+3.3V_ALW_PCH
MINI2CLK_REQ#<42>
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
CLK_CPU_ITP#<7>
CLK_CPU_ITP<7>
Core:12
5
4
MEM_SMBCLK
MEM_SMBDATA
BG34
BJ34
AV32
AU32
BE34
BF34
BB32
AY32
BG36
BJ36
AV34
AU34
BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
4
PCIE_MINI1#
PCIE_MINI1
MINI1CLK_REQ#
PCIE_LAN#
PCIE_LAN
LANCLK_REQ#
PCIE_CARD#
PCIE_CARD
CARDCLK_REQ#
PCIE_MINI3#
PCIE_MINI3
MINI3CLK_REQ#
PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#
PCIE_MINI2#
PCIE_MINI2
MINI2CLK_REQ#
PEG_B_CLKRQ#
PCIECLKRQ6#
PCIECLKRQ7#
CLK_BCLK_ITP#
AB49
AB47
AA48
AA47
AB42
AB40
AK14
AK13
+3.3V_RUN
6 1
5
DMN66D0LDW-7_SOT363-6~D
3
4
DMN66D0LDW-7_SOT363-6~D
UH4B
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
BD82PPSM-QNHN-A0_BGA989~D
2
QH5A
QH5B
PCI-E*
3
DDR_XDP_WAN_SMBCLK <12,13,14,15,17,35,43>
DDR_XDP_WAN_SMBDAT <12,13,14,15,17,35,43>
E12
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
Link
CLOCKS
FLEX CLOCKS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA
PCH_GPIO74
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
GFX_CLK_REQ#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
CLK_PCI_LOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
PCI_TPM_TCM
SIO_14M
CLK_80H
JETWAY_14MCLK_BCLK_ITP
RH100 90.9_0402_1%~D
RH311 22_0402_5%~D
RH313 22_0402_5%~D
RH314 22_0402_5%~D
RH315 22_0402_5%~D@
2
DDR_HVREF_RST_PCH <7>
LAN_SMBCLK <37>
LAN_SMBDATA <37>
SML1_SMBCLK <49>
SML1_SMBDATA <49>
PCH_CL_CLK1 <42>
PCH_CL_DATA1 <42>
PCH_CL_RST1# <42>
CLK_PCIE_VGA# <16>
CLK_PCIE_VGA <16>
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
CLK_PCI_LOOPBACK <20>
1 2
12
12
12
12
2
SML1_SMBCLK
+3.3V_ALW_PCH
RUN_GFX_ON<48,52>
SML1_SMBDATA
DDR_HVREF_RST_PCH
PCH_GPIO74
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
LAN_SMBCLK
LAN_SMBDATA
RH80
10K_0402_5%~D
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
13
D
2
SSM3K7002FU_SC70-3~D
G
S
1 2
1 2
RH74 10K_0402_5%~D
RH75 10K_0402_5%~D
1 2
RH91 10K_0402_5%~D
1 2
1 2
RH76 10K_0402_5%~D
RH77 10K_0402_5%~D
1 2
1 2
RH78 10K_0402_5%~D
RH79 10K_0402_5%~D
1 2
RH183 10K_0402_5%~D
CLOCK TERMINATION for FCIM and need close to PCH
12
+1.05V_RUN
CLK_PCI_TPM_TCM <41>
CLK_SIO_14M <48>
PCLK_80H <42>
JETWAY_CLK14M <41>
RH309 0_0402_5%~D@
RH99
1M_0402_5%~D
25MHZ_10PF_Q22FA2380049900~D
3
CH18
4
2
1
10P_0402_50V8J~D
YH2
OUT
GND
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (2/8)
PCH (2/8)
PCH (2/8)
LA-7931P
LA-7931P
LA-7931P
1
GFX_CLK_REQ#
QH2
12
1
IN
2
GND
1
+3.3V_ALW_PCH
12
RH2982.2K_0402_5%~D
12
RH2992.2K_0402_5%~D
RH3001K_0402_1%~D
RH30110K_0402_5%~D
RH3022.2K_0402_5%~D
RH3032.2K_0402_5%~D
RH30410K_0402_5%~D
+3.3V_LAN
RH3052.2K_0402_5%~D
RH3062.2K_0402_5%~D
18 70Monday, July 23, 2012
18 70Monday, July 23, 2012
18 70Monday, July 23, 2012
Crystal EA.
10P_0402_50V8J~D
2
CH19
1
of
of
of
1.0
1.0
1.0
5
4
3
2
1
+3.3V_ALW_PCH
D D
+3.3V_RUN
C C
XDP_DBRESET#<7,17>
PM_DRAM_PWRGD<7>
PCH_RSMRST#_Q<17,50>
ME_SUS_PWR_ACK<49>
SIO_PWRBTN#_R<7,17>
SIO_PWRBTN#<49>
+3.3V_ALW_PCH
SIO_SLP_A#<48,52,57>
PM_APWROK<49>
SYS_PWROK<7,48>
RESET_OUT#<49>
AC_PRESENT<49>
B B
A A
1 2
RH318 10K_0402_5%~D@
1 2
RH144 10K_0402_5%~D
1 2
RH142 10K_0402_5%~D
1 2
RH319 10K_0402_5%~D@
1 2
RH140 10K_0402_5%~D
1 2
RH137 8.2K_0402_5%~D
+1.05V_RUN
RH111 49.9_0402_1%~D
RH112 750_0402_1%~D
SUSACK#<48> PCH_DPWROK <48>
74AHC1G08GW_SOT353-5~D
RH114 0_0402_5%~D@
RH359 0_0402_5%~D@
RH116 0_0402_5%~D@
RH117 0_0402_5%~D@
RH320 0_0402_5%~D@
RH120 0_0402_5%~D@
RH121 0_0402_5%~D@
RH122 0_0402_5%~D@
RH139 8.2K_0402_5%~D
5
DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>
1 2
1 2
RH367 0_0402_5%~D@
SUS_STAT#/LPCPD#
ME_SUS_PWR_ACK
PCH_PCIE_WAKE#
SIO_SLP_LAN#
PCH_RI# PCH_CRT_DDC_CLK
CLKRUN#
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_COMP_R
RBIAS_CPY
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_ALW2
UC4
1
IN1
2
IN2
1 2
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PM_DRAM_PWRGD_R
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SIO_PWRBTN#_R
AC_PRESENT
PCH_BATLOW#
PCH_RI#
CH112
1 2
5
0.1U_0402_25V6K~D
P
4
PM_APWROK_R
O
G
3
preventmaterialshortageforThaiflood.
BC24
BE20
BG18
BG20
BE24
BC20
BJ18
BJ20
AW24
AW20
BB18
AV18
AY24
AY20
AY18
AU18
BJ24
BG25
BH21
C12
K3
P12
L22
L10
B13
C21
K16
E20
H20
E10
A10
PCH_DPWROK PCH_RSMRST#_R
ME_SUS_PWR_ACK_R SUSACK#_R
UH4C
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP
DMI_IRCOMP
DMI2RBIAS
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#
ACPRESENT / GPIO31
BATLOW# / GPIO72
RI#
BD82PPSM-QNHN-A0_BGA989~D
4
1 2
RH113 0_0402_5%~D@
1 2
RH321 0_0402_5%~D@
1 2
RH323 0_0402_5%~D@
DMI
FDI
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
SLP_LAN# / GPIO29
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SYS_PWROKRESET_OUT#
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
H_PM_SYNC
SIO_SLP_LAN#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+RTC_CELL
330K_0402_1%~D
RH127
1 2
DSWODVREN
330K_0402_1%~D
@
RH129
1 2
FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>
FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>
FDI_INT <6>
FDI_FSYNC0 <6>
FDI_FSYNC1 <6>
FDI_LSYNC0 <6>
FDI_LSYNC1 <6>
PCH_PCIE_WAKE# <49>
CLKRUN# <41,48,49>
T56 PAD~D@
T57 PAD~D@
T58 PAD~D@
SIO_SLP_S5# <49>
T59 PAD~D@
SIO_SLP_S4# <48,52,55>
SIO_SLP_S3# <11,35,47,48,52,56>
SIO_SLP_A# <48,52,57>
T62 PAD~D@
SIO_SLP_SUS# <48>
T63 PAD~D@
H_PM_SYNC <7>
SIO_SLP_LAN# <37,48>
3
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
Disabled
PANEL_BKEN_PCH<28>
LDDC_CLK_PCH<27>
LDDC_DATA_PCH<27>
Minimumspeacingof20milsforLVD_IBG
LCD_ACLK-_PCH<27>
LCD_ACLK+_PCH<27>
LCD_BCLK-_PCH<27>
LCD_BCLK+_PCH<27>
PCH_CRT_BLU<32>
PCH_CRT_GRN<32>
PCH_CRT_RED<32>
PCH_CRT_DDC_CLK<32>
PCH_CRT_DDC_DAT<32>
PCH_CRT_HSYNC<32>
PCH_CRT_VSYNC<32>
1 2
1 2
1 2
1 2
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH
RH131 150_0402_1%~D
RH132 150_0402_1%~D
RH133 150_0402_1%~D
RH134 100K_0402_5%~D
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
LOW: RH129 STUFFED,
RH127 UNSTUFFED
PANEL_BKEN_PCH
1 2
ENVDD_PCH
BIA_PWM_PCH
LDDC_CLK_PCH
LDDC_DATA_PCH
LVD_IBG
LCD_ACLK-_PCH
LCD_ACLK+_PCH
LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH
LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH
LCD_BCLK-_PCH
LCD_BCLK+_PCH
LCD_B0-_PCH
LCD_B1-_PCH
LCD_B2-_PCH
LCD_B0+_PCH
LCD_B1+_PCH
LCD_B2+_PCH
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
1K_0402_0.5%~D
12
RH126
2
ENVDD_PCH<28,48>
BIA_PWM_PCH<28>
RH344 2.37K_0402_1%~D
LCD_A0-_PCH<27>
LCD_A1-_PCH<27>
LCD_A2-_PCH<27>
LCD_A0+_PCH<27>
LCD_A1+_PCH<27>
LCD_A2+_PCH<27>
LCD_B0-_PCH<27>
LCD_B1-_PCH<27>
LCD_B2-_PCH<27>
LCD_B0+_PCH<27>
LCD_B1+_PCH<27>
LCD_B2+_PCH<27>
1 2
RH123 20_0402_1%~D
1 2
RH124 20_0402_1%~D
HSYNC
VSYNC
CRT_IREF
MAX14885EETL has internal 3K pu for
PCH_CRT_DDC_CLK and PCH_CRT_DDC_DAT
+3.3V_RUN
12
RH3172.2K_0402_5%~D @
PCH_CRT_DDC_DAT
1 2
RH3162.2K_0402_5%~D @
Intel request DDPB can not support eDP
UH4D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
BD82PPSM-QNHN-A0_BGA989~D
LVDS
CRT
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (3/8)
PCH (3/8)
PCH (3/8)
LA-7931P
LA-7931P
LA-7931P
1
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
1.0
1.0
19 70Monday, July 23, 2012
19 70Monday, July 23, 2012
19 70Monday, July 23, 2012
1.0
of
of
of
5
4
3
2
1
UH4E
+3.3V_RUN
1 2
RH324 8.2K_0402_5%~D
1 2
D D
C C
RH325 8.2K_0402_5%~D
1 2
RH326 8.2K_0402_5%~D
1 2
RH329 8.2K_0402_5%~D
1 2
RH327 10K_0402_5%~D
1 2
RH330 10K_0402_5%~D
1 2
RH328 10K_0402_5%~D
1 2
RH332 10K_0402_5%~D
1 2
RH331 10K_0402_5%~D
1 2
RH360 10K_0402_5%~D
PCI_GNT3#
1K_0402_1%~D
@
12
RH333
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3
B B
Low = A16 swap
High = Default
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
LCD_CBL_DET#
PCH_GPIO54
PCH_GPIO3
CAM_MIC_CBL_DET#
PCH_GPIO52
PLTRST_GPU#<16>
PLTRST_USH#<41>
PLTRST_MMI#<47>
PLTRST_XDP#<7>
PLTRST_LAN#<37>
USB3RN1<40>
USB3RN2<40>
USB3RN4<46>
USB3RP1<40>
USB3RP2<40>
USB3RP4<46>
USB3TN1<40>
USB3TN2<40>
USB3TN4<46>
USB3TP1<40>
USB3TP2<40>
USB3TP4<46>
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
PCH_GPIO52
PCH_GPIO54
BBS_BIT1
PCI_GNT3#
LCD_CBL_DET#<28>
CAM_MIC_CBL_DET#<28>
1 2
RH343 0_0402_5%~D@
1 2
RH335 0_0402_5%~D@
1 2
RH336 0_0402_5%~D@
1 2
RH337 0_0402_5%~D@
1 2
RH338 0_0402_5%~D@
CLK_PCI_5048<48>
CLK_PCI_MEC<49>
CLK_PCI_DOCK<46>
CLK_PCI_LOOPBACK<18>
HDD_FALL_INT<35>
RH160 22_0402_5%~D
RH102 22_0402_5%~D
RH103 22_0402_5%~D
RH105 22_0402_5%~D
RH334 0_0402_5%~D@
12
12
12
12
LCD_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET# USB_OC2#
1 2
FFS_PCH_INT
T104PAD~D @
PCH_PLTRST#
PCI_5048
PCI_MEC
PCI_DOCK
PCI_LOOPBACKOUT
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3TP1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
BD82PPSM-QNHN-A0_BGA989~D
RSVD
USB30
PCI
USB
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
USBP12USBP12+
USBRBIAS
Route single-end 50-ohms and max 500-mils length.
Minimum spacing to other signals: 15 mils
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
USBP0- <40>
USBP0+ <40>
USBP1- <40>
USBP1+ <40>
USBP2- <47>
USBP2+ <47>
USBP3- <46>
USBP3+ <46>
USBP4- <46>
USBP4+ <46>
USBP5- <43>
USBP5+ <43>
USBP6- <47>
USBP6+ <47>
USBP7- <41>
USBP7+ <41>
USBP8- <42>
USBP8+ <42>
USBP9- <39>
USBP9+ <39>
USBP10- <47>
USBP10+ <47>
USBP11- <50>
USBP11+ <50>
USBP12- <28>
USBP12+ <28>
1 2
RH151
22.6_0402_1%~D
1 2
RH339 0_0402_5%~D@
1 2
RH341 0_0402_5%~D@
1 2
RH356 0_0402_5%~D@
SIO_EXT_SMI#
----->Right Side
----->Right Side
----->Left Side
----->MLK DOCK
----->DOCK
----->WWAN/UWB
----->Left Side
----->USH
----->WLAN/WIMAX
----->ESATA
----->Express Card
----->Blue Tooth
----->Camera
USB_OC0# <40>
USB_OC1# <47>
USB_OC2# <17>
USB_OC3# <17,47>
USB_OC4# <39>
USB_OC5# <17>
USB_OC6# <17>
SIO_EXT_SMI# <17,49>
USB_OC0#_R <17>
USB_OC1#_R <17>
USB_OC4#_R <17>
USB_OC0#_R
USB_OC1#_R
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
RPH1
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
RPH2
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
+3.3V_ALW_PCH
1 2
1 2
1 2
1 2
ForRFlayoutrequest
A A
PCH_PLTRST#<7>
5
CLK_PCI_5048
C132412P_0402_50V8J @
CLK_PCI_MEC
C132512P_0402_50V8J @
CLK_PCI_DOCK
C132612P_0402_50V8J @
CLK_PCI_LOOPBACK
C132712P_0402_50V8J @
74AHC1G08GW_SOT353-5~D
+3.3V_RUN
1
2
0.1U_0402_25V6K~D
5
UH3
P
IN1
O
IN2
G
3
CH102
1 2
4
PCH_PLTRST#_EC <41,42,43,47,48,49>
preventmaterialshortageforThaiflood.
4
Boot BIOS Strap
BBS_BIT1 Boot BIOS Location
*
SATA_SLPD
(BBS_BIT0)
00
01
10
11
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
LPC
Reserved (NAND)
PCI
SPI
BBS_BIT1
12
@
1K_0402_1%~D
RH342
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (4/8)
PCH (4/8)
PCH (4/8)
LA-7931P
LA-7931P
LA-7931P
20 70Monday, July 23, 2012
20 70Monday, July 23, 2012
20 70Monday, July 23, 2012
1
of
of
of
1.0
1.0
1.0
5
4
3
2
1
12
12
12
12
12
12
+3.3V_RUN
RH25610K_0402_5%~D
RH15810K_0402_5%~D
RH20310K_0402_5%~D
RH26310K_0402_5%~D
RH164100K_0402_5%~D
RH17110K_0402_5%~D @
RH1731K_0402_1%~D @
RH26610K_0402_5%~D
RH18110K_0402_5%~D
RH17810K_0402_5%~D
RH2698.2K_0402_5%~D
RH16310K_0402_5%~D
RH2728.2K_0402_5%~D
RH3618.2K_0402_5%~D @
RH362100K_0402_5%~D
+3.3V_ALW_PCH
RH54
4.7K_0402_5%~D
1 2
SLP_ME_CSW_DEV#
12
RH353
D D
Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)
@
1K_0402_1%~D
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE
ENABLED - HIGH DEFAULT
DISABLED - LOW
+3.3V_ALW_PCH
12
12
12
12
12
12
12
SIO_EXT_WAKE#
PCH_GPIO15
KB_DET#
PCH_GPIO27
PCH_GPIO36
PCH_GPIO37
PCH_GPIO17
PCH_GPIO16
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
C C
B B
RH177 10K_0402_5%~D
1 2
RH354 1K_0402_1%~D
RH170 10K_0402_5%~D
RH175 10K_0402_5%~D@
PCHhasinternalpullup20kohmon(GPIO27)
RH174 10K_0402_5%~D
RH172 10K_0402_5%~D
RH273 1K_0402_1%~D@
RH274 1K_0402_1%~D@
SIO_EXT_SCI#_R<17>
SIO_EXT_SCI#<49>
USH_DET#<41>
MXM_PRESENTL#<16>
SIO_EXT_WAKE#<48>
PM_LANPHY_ENABLE<37>
PCH_GPIO15<17>
PCH_GPIO16<17>
T107PAD~D@
SLP_ME_CSW_DEV#<17,48>
DGPU_HOLD_RST#<16>
PCH_GPIO35<17>
PCH_GPIO36<17>
PCH_GPIO37<17>
TEMP_ALERT#<17,48>
KB_DET#<50>
SIO_EXT_SCI#
FFS_INT2<35>
1 2
RH259 0_0402_5%~D@
USH_DET#
DP_MUX_PRIORITY
MXM_PRESENTL#
SIO_EXT_WAKE#
PM_LANPHY_ENABLE
PCH_GPIO15
PCH_GPIO16
PCH_GPIO17
PCH_GPIO22
PCH_GPIO24
PCH_GPIO27
SLP_ME_CSW_DEV#
DGPU_HOLD_RST#
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37
TPM_ID0
TPM_ID1
FFS_INT2
TEMP_ALERT#
KB_DET#
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
UH4F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
BD82PPSM-QNHN-A0_BGA989~D
GPIO
NCTF
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
CONTACTLESS_DET#
DGPU_PWROK
MXM_PRESENTR#
PCH_GPIO71
SIO_A20GATE
SIO_RCIN#
H_CPUPWRGD
PCH_THRMTRIP#_R
INIT3_3V#
DF_TVS
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
CONTACTLESS_DET# <41>
DGPU_PWROK <16,48>
MXM_PRESENTR# <16>
T109PAD~D @
SIO_A20GATE <49>
SIO_RCIN# <49>
H_CPUPWRGD <7>
T106PAD~D @
T108PAD~D @
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
RH262 56_0402_5%~D
0.1U_0402_25V6K~D
1
CH97
2
12
+1.05V_RUN_VTT
PLACE RH150 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)
+VCCDFTERM
2.2K_0402_5%~D
RH149
12
CONTACTLESS_DET#
SIO_A20GATE
SIO_RCIN#
SIO_EXT_SCI#
USH_DET#
PCH_GPIO36
PCH_GPIO37
TEMP_ALERT#
PCH_GPIO22
MXM_PRESENTL#
PCH_GPIO17
DP_MUX_PRIORITY
PCH_GPIO16
PCH_GPIO35
MXM_PRESENTR#
powerSaving.
RH149 need to close to CPU
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_RUN +3.3V_RUN
12
RH268
RH267
1@
10K_0402_5%~D
TPM_ID0
A A
1 2
RH270
10K_0402_5%~D
1 2
TPM_ID1
2@
20K_0402_5%~D
12
RH271
2.2K_0402_5%~D
3@
TCM
No TPM, No TCM
4@
TBD
TPM
TPM_ID1TPM_ID0
0
0
0
1
11
H_SNB_IVB#<7>
1 2
RH150 0_0402_5%~D@
DF_TVS
1 2
RH358 1K_0402_1%~D
DF_TVSDF_TVS_R
DMI & FDI Termination Voltage
Set to Vss when LOW
Set to Vcc when HIGH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (5/8)
PCH (5/8)
PCH (5/8)
LA-7931P
LA-7931P
LA-7931P
21 70Monday, July 23, 2012
21 70Monday, July 23, 2012
21 70Monday, July 23, 2012
1
1.0
1.0
1.0
of
of
of
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