Compal LA-7521P PCA70, LA-7522P PCA61 Schematic

A

1 1

B

C

D

E

PCA70/61

2 2

LA-7521P

Sugar Bay

REV 0.2

Schematic

3 3

LA-7522P REV 0.1

Intel Processor(Sandy Bridge) / PCH(Cougar Point)

Tuesday, April 12, 2011 Rev 0.2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

PCA70 LA-7521P M/B

164Tuesday, April 12, 2011

E

0.1

of

A

DDR3 VRAM
512M/1GB(GV)
1GB/2GB(GS)

1 1

HDMI(IFPE)

VGA Chip

NV N12P-GV
NV N12P-GS(default)

B

PCI-Express 16X

HDMI
(IFPC)

C

Intel CPU
Sandy Bridge
Desktop

LGA1155

D

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333 MT/s

E

204pin DDRIII-SO-DIMM X2

H1

2 ch. LVDS
Conn.

LVDS I/F

Scale

RTD2482D

FDI X8

2.7GT/s

DDPC

DMI X4

5GT/s

USB 2.0 X 6

USB-Port 0 USB-Port 1

USB-Port 2

0.3MP CAM (1.3M reserve)
w/ DMic & ALS

Touch Panel

L1

SPI ROM

HDMI IN conn.

2 2

D-sub IN conn.

HDMI OUT conn.

LAN

RJ45

RTL8111E 10/100/1G
PCIe Mini Card

WLAN
Card reader IC

conn.

3 3

(SD/MMC/SDHC)

CIR

SPI

HDMI
RGB

EC
ENE KB930

DDPD

Intel PCH
Cougar Point
H61

SATA port 0

SATA port 1

USB 2.0
PCI-E

PCIe 1x

3.5" SATA HDD Conn.

SATA ODD Conn.

TV Tuner Card
USB3.0 Controller

USB 3.0

USB-Port 3

ASM1042

PCIe 1x

PCIe 1x

FCBGA-942

JMB3853 in 1 CardReader

PCIe 1x

LPC BUS

USB 2.0 X2 (reserve)

USB 2.0
SATA port 4

HD Audio

5.1ch HDA Audio Codec

ALC663

USB-Port 4

USB-Port 5
& eSATA

D-Mic.

MIC Jack

H1L1

SPI ROM

SPI

LFEOUT

FRONT

HPOUT

SPDIFOUT

C C

SPK AMP

EUA2113

4 4

2.5mm jack
for 10W woofer

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

C

Compal Secret Data

Deciphered Date

C C

EUA2113

6W SPK *2
Conn

D

Date: Sheet

C C

HP/SPDIF JackSPK AMP

Title

Size Document Number Rev

Compal Electronics, Inc.

Block Diagram

PCA70 LA-7521P M/B

264Tuesday, April 12, 2011

E

of

0.1

5

PU16

TPS51212DSCR

Bead

D D

NCP5911MNTBG

PU6

+1.05VS_VCCIOP

PU11~PU15

VIN

TPS51212DSCR

PU9

TPS51212DSCR

+5VALWP

JDCIN1

B+

JUMP

8205_B+ PU2

RT8205EGQW

+3VALWP

+VGA_COREP

+CPU_CORE

+GFX_CORE

+1.05VSP

4

JUMP

JUMP

JUMP

JUMP

JUMP

JUMP

+VGA_CORE

+1.05VS_VCCIO

+1.05VS_VPCH

+5VALW

+3VALW

PU6

APL5930KAI

APL5610CI

AP4800BGM

+1.8VSP

PU5

+VCCSAP +VCCSA

+1.05VGS

U63

3

JUMP

AP4800BGM

Q61

+5VS

2

+CPU_CORE

+GFX_CORE

+1.8VS

+1.05VS_VCCIO

1.5V

+VCCSA

+12VS

+5VS

1

Intel Sandy Bridge

CPU

SATA HDD

JUMP

+1.8VS

+0.75VS

+1.8VS

+1.05VS_VPCH

+3VALW
+3VS

+5VALW
+5VS

+1.5VGS

+1.05VGS

+1.5VGS

+VGA_CORE

+3VGS

MOS

+5VS

SATA ODD

+12VS

+12VS

+5VS

+1.5V

+3VS

Audio codec

ALC663

FAN1

FAN2

FAN3

DDR3 SODIMM X 4

Intel Gougar Point

PCH

VRAM X 8

N12P-GT-A1

VGA

+3VS+5VS

+5VS

HDMI-OUT

Title

Size Docum e nt N u m be r Re v

Date: Sheet

+RTCVCC

Battery

Media card
controller

RTC

JMB385

+3VS

+3VS

Bluetooth

Compal Electronics, Inc.

Power Tree

PCA70 LA-7521P M/B

1

LVDS

ASM1442

+3VS

CAM

364Tuesday, April 12, 2011

+3VS

of

0.1

PU7

TPS51212DSCR

C C

PU3

TPS54331DR

+12VALWP

JUMP

+1.5VP

MOS

JUMP

+1.5VS

+1.5V

U65

AP4800BGM

+1.5VGS

Q60

AP4800BGM

+3VS

PU6

APL5930KAI

+0.75VP

JUMP

+0.75VS

+1.5V

PU19

APL5930KAI

+1.2VUSB

+12VALW

+12VS

B+

LCD

Converter

MOS

+3VS

AMP X 2
EUA2113

B B

+USB_VCCB

USB2.0 X 3

USB3.0 X 2

+USB_VCCA

+USB30_VCCA

+5VALW

HDMI-IN Mini Card x2

CRT-IN

A A

eSATA/USB

Conn.

+5VALW

U83

+3V_LAN

+USB_VCCC

5

U34

U33

U46

MOS

LAN

RTL8111E

+3VALW

SW&Power/B

Conn

+3VS

+3VALW

MOS

Scaler

U23

+1.2V_SCA

+3VS

+3VS1.5VS

+1.2VUSB+3V_SCA

USB3.0

ASM1042

4

EC

KB930

+3VALW

+5VALW

+3VS

+5VALW

+5VS

MOS

+LCDVDD

LVDS CONNRTD2482D

+3VALW

Scaler

3

CIR

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

MOS

B-CAS

+5VS

Touchscreen

Compal Secret Data

Deciphered Date

2

+5VS_L_BCAS

2010/10/1 2011/11/01

A

B

C

D

E

Voltage Rails

Power Plane Description
VIN
B+
+CPU_CORE

1 1

+VCCSA ON OFF OFFSystem Agent core voltage for CPU
+1.05VS_VCCIO 1.05V power rail for CPU
+1.05VS_VPCH 1.05V power rail for PCH
+0.75VS 0.75V power rail for DDR terminator
+1.5V
+1.5VS
+1.8VS 1.8V switched power rail
+3VALW 3.3V alwa y s on powe r ra il once AC plug in
+3V_LAN 3.3V power rail for LAN ON
+3VS
+3V_SCA 3.3V switched pow er rail for scaler O N
+1.2V_SCA N/AN/A
+1.2V_USB 1.2V power rail for USB3.0 O FFON OFF

+5VS 5V switched power rail OFF OFF

2 2

+RTCVCC RTC power
+3VGS ON OFF OFF

+1.05VGS
+1.5VGS
+12VALW 12V always on power rail once AC plug in
+12VS 5V switched power rail O FF O FF

Note : ON * m e a n s t h a t t hi s p ow e r pl a ne is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)
AC power rail for power circuit.
Core voltage for CPU

1.5V power rail for DDRIII

1.5V switched power rail

3.3V switched power rail

1.2V switched power rail for scaler ON

5V always on power rail once AC plug in+5VALW

5V switched power rail for panel+LCDVDD ON N/A N/A

3.3V power rail for GPU
Graphics power rail for GPU

1.05VS switched power rail for GPU

1.5VS power rail for GPU and VRAM

PCH SM Bus Address

HEX

Device

+3VS
+3VS

3 3

DDR(JDDRL2)
DDR(JDDRH1)

Address

1010 000X b
1010 010X b

S0 S3 S5
N/A

N/A
N/A
OFF
OFF

OFF
ON
OFF
OFF
ON
ON
OFF
N/A N/A

ONON

N/A
N/A
OFF

OFF

OFF
OFF
ON
OFF

N/A
ON
ON OFF+GFX _COR E Graphics voltage for CPU

ONONOFF
ON OFF OFF
ON OFF
ON OFF
ON
ON
ON

ON OFF

ON

ON ON ON

ON OFF OFF+VGA_CORE
ON OFF OFF
ON OFF OFF
ONONN/A N/A

EC SM Bus2 Address

DevicePower Power

Scaler

HEX Address

0000_0101b

USB Port Table

USB 2.0 USB 1.1 Port

UHCI0

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

EHCI2

UHCI5

UHCI6

SATA Port Table

Port Device

0

6G

3G

HDD

1

ODD

2

Disabled on H61

3

Disabled on H61

4

eSATA+USB Conn

5

NC

BOARD ID Table

Board
ID

0

*

1
2
3
4

PCB
Revision

0.1

0.2

Device

0

Co-lay w/USB30 PORT0

1

Co-lay w/USB30 PORT1

2

Touch Screen

3

Web Camera

4

eSATA+USB Conn

5

USB Conn 6

6

Disabled on H61

7

Disabled on H61

8

USB Conn 4

9

USB Conn 3

10

Mini Card(TV Tuner)

11

Blue Tooth

12

Disabled on H61

13

Disabled on H61

PCIE Port Table

1
2
3
4
5
6
7
8

DevicePort

NC
USB30
WLAN
TV
Card reader
LAN
Disabled on H61
Disabled on H61

BOM Structure Table

BTO Item BOM Structure

ME components CONN@

UMA Only UMA@

USB30 USB30@

D-sub IN VGAIN@
HDMI IN HDMIIN@
HDMI OUT HDMIO@
HDMI OUT from DIS HDMIOD@
HDMI OUT from UMA HDMIOU@
VGA w/o Senergy DISO@
BCAS TV@
VRAM select X76@
VRAM 1G Hynix
X7630488L01
VRAM 1G Samsung
X7630488L02

SKU IO Select

Unpop @

LA-7522P 8 Layer PCB 8LPCB@

GS@VGA-N12P-GS
GV@VGA-N12P-GV

DIS@DISCRETE ONLY

USB20@No USB30 SKU

X76_HY1G@

X76_SAM1G@
GPIO69_H@

GPIO69_L@
GPIO70_H@
GPIO70_L@
GPIO71_H@
GPIO71_L@

6LOCB@LA-7521P 6 Layer PCB

SKU ID(Project) Table

Project
_ID2

PCH SML1 Bus Address

HEX

AddressDevicePower

VGA Ext. thermal sensor

(defaulta)

SIGNAL

STATE

4 4

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S3#

HIGH HIGH HIGH

LOW

LOW LOW

A

SLP_S4#

HIGH

1001_1010b
1001_1110bVGA Int. thermal sensor

SLP_S5# +VALW

HIGHHIGHHIGH

HIGH

HIGH

LOWLOWLOW OFF

ON

ON

ON

ON

OFF

+VS

ON

ON

OFF

OFF

B

(GPIO69)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

Project
_ID1

(GPIO70)

00 0
0

0

01 1

10 0

Project

Project

_ID0
(GPIO71)

0

1

PCA70

1

0

PCA61

SKU

UMA

USB30 w/o HDMI
4319D588L03

DIS-Hynix

USB30 w/ HDMI
4319D588L04

UMA

USB30 w/ HDMI
4319D588L05

DIS-Hynix

USB30 w/ HDMI
4319D588L11

UMA

USB20 w/ HDMI
4319D588L12

10 1 X
11 0 X

2010/10/1 2011/11/01

C

Compal Secret Data

Deciphered Date

UMA@ USB30@ GPIO69_L@ GPIO70_L@ GPIO71_L@

GS@ DIS@ USB30@ VGAIN@ HDMIO@ HDMIOD@ DISO@
8LPCB@

8LPCB@

X76_HY1G@

GPIO69_L@ GPIO70_L@ GPIO71_H@

HDMIIN@

HDMIIN@UMA@ USB30@ VGAIN@ HDMIO@ HDMIOU@ DEBUG@

8LPCB@

GPIO69_L@ GPIO71_L@

GPIO70_H@

HDMIIN@GV@ DIS@ USB30@ VGAIN@ HDMIO@ HDMIOD@ DISO@

6LOCB@

GPIO69_L@ GPIO71_H@

GPIO70_H@

HDMIIN@UMA@ USB20@ VGAIN@ HDMIO@ HDMIOU@ DEBUG@

GPIO69_H@ GPIO70_L@

GPIO71_L@6LOCB@

X11 1

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Notes List

PCA70 LA-7521P M/B

464Tuesday, April 12, 2011

E

0.1

of

5

D D

PECI 10mil spacing and
Max Length < 15"

R12 follow CDB R42PR add
0ohm serial resistor

R14 follow CDB R34PR add
0ohm serial resistor

12

R1310K_0402_5%

C20.1U_0402_16V4Z

H_PECI
H_SNB_IVB#
H_PROCHOT#_R
H_PM_SYNC

H_PWRGOOD

+1.5V

1 2

C1591 0.1U_0402_16V4Z

1 2

C1592 0.1U_0402_16V4Z

1 2

C1593 0.1U_0402_16V4Z

1 2

ESD request Close to CPU as possible

C C

Place C2 close to CPU J40 as
close as possible.

C1594 0.1U_0402_16V4Z

1 2

+1.05VS_VCCIO

H_PROCHOT#[49]

R8 51_0402_5%

+1.05VS_VCCIO

12

H_THERMTRIP#[18]

4

H_SNB_IVB#[18]

H_PM_SYNC[15]

H_PWRGOOD[18]

T1PAD

R1070

@

1K_0402_5%

12

H_PECI[18,49]

R12 0_0402_5%@

12

1 2

R14 0_0402_5%

PM_DRAM_PWRGD_R

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

H_THERMTRIP#_R

H_PM_SYNC

H_PWRGOOD

BUF_CPU_RST#

JCPU1B

PROC_SELECT#

K32

PROC_SEL

AJ33

SKTOCC#

E37

CATERR#

J35

PECI

H34

PROCHOT#

G35

THERMTRIP#

E38

PM_SYNC

J40

UNCOREPWRGOOD

AJ19

SM_DRAMPWROK

F36

RESET#

Sandy Bridge_rPGA_Rev1p0

3

MISCTHERMALPWR MANAGEMENT

BCLK[0]

BCLK#[0]

BCLK_ITP

BCLK_ITP#

CLOCKS

SM_DRAMRST#

DDR3

MISC

PRDY#
PREQ#

TCK
TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]

JTAG & BPM

BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TDI

W2
W1

C40
D40

AW18

K38
K40

M40
L38
J39

L40
L39

E39

H40
H38
G38
G40
G39
F38
E40
F40

100 MHz

CLK_CPU_DMI
CLK_CPU_DMI#

120 MHz

CLK_BCLK_ITP
CLK_BCLK_ITP#

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI_R
XDP_TDO_R

XDP_DBRESET#_R

2

CLK_CPU_DMI [14]
CLK_CPU_DMI# [14]

CLK_BCLK_ITP [14]
CLK_BCLK_ITP# [14]

1

@

0.1U_0402_16V4Z

2

R23 0_0402_5%@

1 2

Close to CPU side

C3

SM_DRAMRST# [11,12]

XDP_DBRESET#

1

PU/PD for JTAG signals

XDP_TMS_R
XDP_TDI_R
XDP_TDO_R
XDP_TCK_R
XDP_TRST#_R

R1 51_0402_5%
R2 51_0402_5%
R3 51_0402_5%
R4 51_0402_5%
R6 51_0402_5%

R22 10K_0402_5%

12

+3VS

XDP_DBRESET# [15]

+1.05VS_VCCIO

12
12
12
12
12

12

R33
200_0402_5%

PM_DRAM_PWRGD_R

DRAMPWROK[15]

B B

SUSP[51,57]

2

G

1 2

R24

12

130_0402_5%

R35

@

39_0402_5%

13

D

Q1
SSM3K7002BF 1N SC59-3

@

S

1

C1
1000P_0402_50V7K

2

@

Change Buffered Reset to 1G07(Buffer with open-drain output) 10/7

+3VS

C6

0.1U_0402_16V4Z

A A

PLT_RST#[17,22,45,49]

PLT_RST#

C1612

0.1U_0402_16V4Z

5

1

2

5

1

NC

2

A

2

3

1

U2

P

4

Y

G

SN74LVC1G07DCKR_SC70-5

+1.05VS_VCCIO

12

R42
75_0402_5%

R43

BUFO_CPU_RST# BUF_CPU_RST#

43_0402_1%

1 2

4

12

R44
0_0402_5%

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_JTAG/XDP/FAN

PCA70 LA-7521P M/B

1

of

564Tuesday, April 12, 2011

0.1

5

D D

DMI_PTX_CRX_N0[15]
DMI_PTX_CRX_N1[15]
DMI_PTX_CRX_N2[15]
DMI_PTX_CRX_N3[15]

DMI_PTX_CRX_P0[15]
DMI_PTX_CRX_P1[15]
DMI_PTX_CRX_P2[15]
DMI_PTX_CRX_P3[15]

DMI_CTX_PRX_N0[15]
DMI_CTX_PRX_N1[15]
DMI_CTX_PRX_N2[15]
DMI_CTX_PRX_N3[15]

DMI_CTX_PRX_P0[15]
DMI_CTX_PRX_P1[15]
DMI_CTX_PRX_P2[15]
DMI_CTX_PRX_P3[15]

FDI_CTX_PRX_N0[15]
FDI_CTX_PRX_N1[15]
FDI_CTX_PRX_N2[15]

C C

+1.05VS_VCCIO

FDI_COMP signals should be shorted
near balls and routed with width

B B

10mils, length<250mils.

FDI_CTX_PRX_N3[15]
FDI_CTX_PRX_N4[15]
FDI_CTX_PRX_N5[15]
FDI_CTX_PRX_N6[15]
FDI_CTX_PRX_N7[15]

FDI_CTX_PRX_P0[15]
FDI_CTX_PRX_P1[15]
FDI_CTX_PRX_P2[15]
FDI_CTX_PRX_P3[15]
FDI_CTX_PRX_P4[15]
FDI_CTX_PRX_P5[15]
FDI_CTX_PRX_P6[15]
FDI_CTX_PRX_P7[15]

FDI_FSYNC0[15]
FDI_FSYNC1[15]

FDI_INT[15]
FDI_LSYNC0[15]

FDI_LSYNC1[15]

R46 24.9_0402_1%

1 2

7/20 PE_RX[0~3]/PE_RX#[0~3]
PE_TX[0~3] /PE_T X#[0~3] o nly
use on Server/Workstation.

Close to CPU

FDI_INT
FDI_FSYNC0
FDI_FSYNC1

A A

FDI_LSYNC0
FDI_LSYNC1

@

1 2

R47 1K_0402_5%

@

1 2

R48 1K_0402_5%

@

1 2

R49 1K_0402_5%

@

1 2

R50 1K_0402_5%

@

1 2

R51 1K_0402_5%

4

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT
FDI_LSYNC0

FDI_LSYNC1

FDI_COMP

JCPU1A

W4

DMI_RX#[0]

V4

DMI_RX#[1]

Y4

DMI_RX#[2]

AA5

DMI_RX#[3]

W5

DMI_RX[0]

V3

DMI_RX[1]

Y3

DMI_RX[2]

AA4

DMI_RX[3]

V6

DMI_TX#[0]

W8

DMI_TX#[1]

Y7

DMI_TX#[2]

AA8

DMI_TX#[3]

V7

DMI_TX[0]

W7

DMI_TX[1]

Y6

DMI_TX[2]

AA7

DMI_TX[3]

AC7

FDI_TX#[0]

AC3

FDI_TX#[1]

AD1

FDI_TX#[2]

AD3

FDI_TX#[3]

AD6

FDI_TX#[4]

AE8

FDI_TX#[5]

AF2

FDI_TX#[6]

AG1

FDI_TX#[7]

AC8

FDI_TX[0]

AC2

FDI_TX[1]

AD2

FDI_TX[2]

AD4

FDI_TX[3]

AD7

FDI_TX[4]

AE7

FDI_TX[5]

AF3

FDI_TX[6]

AG2

FDI_TX[7]

AC5

FDI_FSYNC[0]

AE5

FDI_FSYNC[1]

AG3

FDI_INT

AC4

FDI_LSYNC[0]

AE4

FDI_LSYNC[1]

AE2

FDI_COMPIO

AE1

FDI_ICOMPO

P3

PE_RX[0]

R2

PE_RX[1]

T4

PE_RX[2]

U2

PE_RX[3]

P4

PE_RX#[0]

R1

PE_RX#[1]

T3

PE_RX#[2]

U1

PE_RX#[3]

P8

PE_TX[0]

T7

PE_TX[1]

R6

PE_TX[2]

U5

PE_TX[3]

P7

PE_TX#[0]

T8

PE_TX#[1]

R5

PE_TX#[2]

U6

PE_TX#[3]

Sandy Bridge_rPGA_Rev1p0

PEG_COMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

DMI

Intel(R) FDI

PCI-EXPRESS

3

B4
B5
C4

PCIE_GTX_C_CRX_N15

B12

PCIE_GTX_C_CRX_N14

D11

PCIE_GTX_C_CRX_N13

C9

PCIE_GTX_C_CRX_N12

E9

PCIE_GTX_C_CRX_N11

B7

PCIE_GTX_C_CRX_N10

C5

PCIE_GTX_C_CRX_N9

A6

PCIE_GTX_C_CRX_N8

E1

PCIE_GTX_C_CRX_N7

F3

PCIE_GTX_C_CRX_N6

G1

PCIE_GTX_C_CRX_N5

H4

PCIE_GTX_C_CRX_N4

J2

PCIE_GTX_C_CRX_N3

K4

PCIE_GTX_C_CRX_N2

L2

PCIE_GTX_C_CRX_N1

M4

PCIE_GTX_C_CRX_N0

N2

PCIE_GTX_C_CRX_P15

B11

PCIE_GTX_C_CRX_P14

D12

PCIE_GTX_C_CRX_P13

C10

PCIE_GTX_C_CRX_P12

E10

PCIE_GTX_C_CRX_P11

B8

PCIE_GTX_C_CRX_P10

C6

PCIE_GTX_C_CRX_P9

A5

PCIE_GTX_C_CRX_P8

E2

PCIE_GTX_C_CRX_P7

F4

PCIE_GTX_C_CRX_P6

G2

PCIE_GTX_C_CRX_P5

H3

PCIE_GTX_C_CRX_P4

J1

PCIE_GTX_C_CRX_P3

K3

PCIE_GTX_C_CRX_P2

L1

PCIE_GTX_C_CRX_P1

M3

PCIE_GTX_C_CRX_P0

N1

PCIE_CTX_GRX_N15

C14

PCIE_CTX_GRX_N14

E13

PCIE_CTX_GRX_N13

G13

PCIE_CTX_GRX_N12

F11

PCIE_CTX_GRX_N11

J13

PCIE_CTX_GRX_N10

D7

PCIE_CTX_GRX_N9

C3

PCIE_CTX_GRX_N8

E5

PCIE_CTX_GRX_N7

F7

PCIE_CTX_GRX_N6

G9

PCIE_CTX_GRX_N5

G6

PCIE_CTX_GRX_N4

K8

PCIE_CTX_GRX_N3

J6

PCIE_CTX_GRX_N2

M7

PCIE_CTX_GRX_N1

L5

PCIE_CTX_GRX_N0

N6

PCIE_CTX_GRX_P15

C13

PCIE_CTX_GRX_P14

E14

PCIE_CTX_GRX_P13

G14

PCIE_CTX_GRX_P12

F12

PCIE_CTX_GRX_P11

J14

PCIE_CTX_GRX_P10

D8

PCIE_CTX_GRX_P9

D3

PCIE_CTX_GRX_P8

E6

PCIE_CTX_GRX_P7

F8

PCIE_CTX_GRX_P6

G10

PCIE_CTX_GRX_P5

G5

PCIE_CTX_GRX_P4

K7

PCIE_CTX_GRX_P3

J5

PCIE_CTX_GRX_P2

M8

PCIE_CTX_GRX_P1

L6

PCIE_CTX_GRX_P0

N5

PEG_ICOMPI and RCOMPO signals should be shorted and routed with

- max length = 500 mils

- typical imp e d a nce = 43 m ohm (4 mils/15mils)

Intel confirm
pull high is
correct

PEG_COMP

Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

+1.05VS_VCCIO

R45

24.9_0402_1%

C7 0.1U_0402_16V7KDIS@
C8 0.1U_0402_16V7KDIS@
C9 0.1U_0402_16V7KDIS@
C10 0.1U_0402_16V7KDIS@
C11 0.1U_0402_16V7KDIS@
C12 0.1U_0402_16V7KDIS@
C13 0.1U_0402_16V7KDIS@
C14 0.1U_0402_16V7KDIS@
C15 0.1U_0402_16V7KDIS@
C16 0.1U_0402_16V7KDIS@
C17 0.1U_0402_16V7KDIS@
C18 0.1U_0402_16V7KDIS@
C19 0.1U_0402_16V7KDIS@
C20 0.1U_0402_16V7KDIS@
C21 0.1U_0402_16V7KDIS@
C22 0.1U_0402_16V7KDIS@

C23 0.1U_0402_16V7KDIS@
C24 0.1U_0402_16V7KDIS@
C25 0.1U_0402_16V7KDIS@
C26 0.1U_0402_16V7KDIS@
C27 0.1U_0402_16V7KDIS@
C28 0.1U_0402_16V7KDIS@
C29 0.1U_0402_16V7KDIS@
C30 0.1U_0402_16V7KDIS@
C31 0.1U_0402_16V7KDIS@
C32 0.1U_0402_16V7KDIS@
C33 0.1U_0402_16V7KDIS@
C34 0.1U_0402_16V7KDIS@
C35 0.1U_0402_16V7KDIS@
C36 0.1U_0402_16V7KDIS@
C37 0.1U_0402_16V7KDIS@
C38 0.1U_0402_16V7KDIS@

PEG_ICOMPO signals should be routed with

- max length = 500 mils

- typical imp e d ance = 14.5 m ohm (12 mils/15mils)

12

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLETRACE TO R?
ROUTE B5 TO R? AS A SEPERATE TRACE

PCIE_GTX_C_CRX_N[0..15] [22]

PCIE_GTX_C_CRX_P[0..15] [22]

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

2

PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N10

PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P10

PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P0

1

PCIE_CTX_C_GRX_N[0..15] [22]

PCIE_CTX_C_GRX_P[0..15] [22]

Leverage LA-6831 and
LA6951(B520) used 1000P
connect to GND to
substitute for 1K ohm PD
resistor.

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_ DMI/PEG/FDI

PCA70 LA-7521P M/B

664Tuesday, April 12, 2011

1

of

0.1

5

DDR_A_D[0..63][11]

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6

D D

C C

DDR_A_BS0[11]

B B

DDR_A_BS1[11]
DDR_A_BS2[11]

DDR_A_CAS#[11]
DDR_A_RAS#[11]

DDR_A_WE#[11]

DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

JCPU1C

AJ3

SA_DQ[0]

AJ4

SA_DQ[1]

AL3

SA_DQ[2]

AL4

SA_DQ[3]

AJ2

SA_DQ[4]

AJ1

SA_DQ[5]

AL2

SA_DQ[6]

AL1

SA_DQ[7]

AN1

SA_DQ[8]

AN4

SA_DQ[9]

AR3

SA_DQ[10]

AR4

SA_DQ[11]

AN2

SA_DQ[12]

AN3

SA_DQ[13]

AR2

SA_DQ[14]

AR1

SA_DQ[15]

AV2

SA_DQ[16]

AW3

SA_DQ[17]

AV5

SA_DQ[18]

AW5

SA_DQ[19]

AU2

SA_DQ[20]

AU3

SA_DQ[21]

AU5

SA_DQ[22]

AY5

SA_DQ[23]

AY7

SA_DQ[24]

AU7

SA_DQ[25]

AV9

SA_DQ[26]

AU9

SA_DQ[27]

AV7

SA_DQ[28]

AW7

SA_DQ[29]

AW9

SA_DQ[30]

AY9

SA_DQ[31]

AU35

SA_DQ[32]

AW37

SA_DQ[33]

AU39

SA_DQ[34]

AU36

SA_DQ[35]

AW35

SA_DQ[36]

AY36

SA_DQ[37]

AU38

SA_DQ[38]

AU37

SA_DQ[39]

AR40

SA_DQ[40]

AR37

SA_DQ[41]

AN38

SA_DQ[42]

AN37

SA_DQ[43]

AR39

SA_DQ[44]

AR38

SA_DQ[45]

AN39

SA_DQ[46]

AN40

SA_DQ[47]

AL40

SA_DQ[48]

AL37

SA_DQ[49]

AJ38

SA_DQ[50]

AJ37

SA_DQ[51]

AL39

SA_DQ[52]

AL38

SA_DQ[53]

AJ39

SA_DQ[54]

AJ40

SA_DQ[55]

AG40

SA_DQ[56]

AG37

SA_DQ[57]

AE38

SA_DQ[58]

AE37

SA_DQ[59]

AG39

SA_DQ[60]

AG38

SA_DQ[61]

AE39

SA_DQ[62]

AE40

SA_DQ[63]

AY29

SA_BS[0]

AW28

SA_BS[1]

AV20

SA_BS[2]

AV30

SA_CAS#

AU28

SA_RAS#

AW29

SA_WE#

Sandy Bridge_rPGA_Rev1p0

DDR SYSTEM MEMORY A

4

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CK[2]
SA_CK#[2]

SA_CKE[2]

SA_CK[3]
SA_CK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]

SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS#[8]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_DQS[8]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_ECC_CB[0]
SA_ECC_CB[1]
SA_ECC_CB[2]
SA_ECC_CB[3]
SA_ECC_CB[4]
SA_ECC_CB[5]
SA_ECC_CB[6]
SA_ECC_CB[7]

3

DDR_B_D[0..63][12]

DDRA_CLK0

AY25

DDRA_CLK0#

AW25

DDRA_CKE0

AV19

DDRA_CLK1 DDRB_CLK1

AU24

DDRA_CLK1# DDRB_CLK1#

AU25

DDRA_CKE1 DDRB_CKE1

AT19

AW27
AY27
AU18

AV26
AW26
AV18

DDRA_SCS0# DDRB_SCS0#

AU29

DDRA_SCS1#

AV32
AW30
AU33

DDRA_ODT0 DDRB_ODT0

AV31

DDRA_ODT1

AU32
AU30
AW33

DDR_A_DQS#0

AK2

DDR_A_DQS#1

AP2

DDR_A_DQS#2

AV4

DDR_A_DQS#3

AW8

DDR_A_DQS#4

AV36

DDR_A_DQS#5

AP39

DDR_A_DQS#6

AK39

DDR_A_DQS#7

AF39
AV12

DDR_A_DQS0

AK3

DDR_A_DQS1

AP3

DDR_A_DQS2

AW4

DDR_A_DQS3

AV8

DDR_A_DQS4

AV37

DDR_A_DQS5

AP38

DDR_A_DQS6

AK38

DDR_A_DQS7

AF38
AV13

DDR_A_MA0

AV27

DDR_A_MA1

AY24

DDR_A_MA2

AW24

DDR_A_MA3

AW23

DDR_A_MA4

AV23

DDR_A_MA5

AT24

DDR_A_MA6

AT23

DDR_A_MA7

AU22

DDR_A_MA8

AV22

DDR_A_MA9

AT22

DDR_A_MA10

AV28

DDR_A_MA11

AU21

DDR_A_MA12

AT21

DDR_A_MA13

AW32

DDR_A_MA14

AU20

DDR_A_MA15

AT20

AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12

DDRA_CLK0 [11] DDRB_CLK0 [12]
DDRA_CLK0# [11]
DDRA_CKE0 [11] DDRB_CKE0 [12]

DDRA_CLK1 [11]
DDRA_CLK1# [11] DDRB_CLK1# [12]
DDRA_CKE1 [11]

DDRA_SCS0# [11]
DDRA_SCS1# [11] DDRB_SCS1# [12]

DDRA_ODT0 [11] DDRB_ODT0 [12]
DDRA_ODT1 [11] DDRB_ODT1 [12]

DDR_A_DQS#[0..7] [11]

DDR_A_DQS[0..7] [11]

DDR_A_MA[0..15] [11]

DDR_B_BS0[12]
DDR_B_BS1[12]
DDR_B_BS2[12]

DDR_B_CAS#[12]
DDR_B_RAS#[12]

DDR_B_WE#[12]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

AG7
AG8

AG5
AG6

AM7

AM10

AL10

AM6
AM9

AP7

AR7
AP10
AR10

AP6

AR6

AP9

AR9
AM12
AM13
AR13
AP13

AL12

AL13
AR12
AP12
AR28
AR29

AL28

AL29
AP28
AP29
AM28
AM29
AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34
AM32
AM31

AL35

AL32
AM34

AL31
AM35

AL34
AH35
AH34
AE34
AE35

AJ35

AJ34
AF33
AF35

AP23
AM24

AW17

AK25
AP24
AR25

AJ9
AJ8

AJ6
AJ7
AL7

AL6
AL9

2

JCPU1D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

Sandy Bridge_rPGA_Rev1p0

AL21

SB_CK[0]

AL22

SB_CK#[0]

AU16

SB_CKE[0]

AL20

SB_CK[1]

AK20

SB_CK#[1]

AY15

SB_CKE[1]

AL23

SB_CK[2]

AM22

SB_CK#[2]

AW15

SB_CKE[2]

AP21

SB_CK[3]

AN21

SB_CK#[3]

AV15

SB_CKE[3]

AN25

SB_CS#[0]

AN26

SB_CS#[1]

AL25

SB_CS#[2]

AT26

SB_CS#[3]

AL26

SB_ODT[0]

AP26

SB_ODT[1]

AM26

SB_ODT[2]

AK26

SB_ODT[3]

AH6

SB_DQS#[0]

AL8

SB_DQS#[1]

AP8

SB_DQS#[2]

AN12

SB_DQS#[3]

AN28

SB_DQS#[4]

AR33

SB_DQS#[5]

AM33

SB_DQS#[6]

AG34

SB_DQS#[7]

AN15

SB_DQS#[8]

AH7

SB_DQS[0]

AM8

SB_DQS[1]

AR8

SB_DQS[2]

AN13

SB_DQS[3]

AN29

SB_DQS[4]

AP33

SB_DQS[5]

AL33

SB_DQS[6]

AG35

SB_DQS[7]

DDR SYSTEM MEMORY B

SB_ECC_CB[0]
SB_ECC_CB[1]
SB_ECC_CB[2]
SB_ECC_CB[3]
SB_ECC_CB[4]
SB_ECC_CB[5]
SB_ECC_CB[6]
SB_ECC_CB[7]

SB_DQS[8]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AN16

AK24
AM20
AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17
AN23
AU17
AT18
AR26
AY16
AV16

AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15

DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

1

DDRB_CLK0# [12]

DDRB_CLK1 [12]
DDRB_CKE1 [12]

DDRB_SCS0# [12]

DDR_B_DQS#[0..7] [12]

DDR_B_DQS[0..7] [12]

DDR_B_MA[0..15] [12]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_DDR3

PCA70 LA-7521P M/B

764Tuesday, April 12, 2011

1

0.1

of

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120

5

POWER

CORE SUPPLY

VSS_SENSE_VCCIO

5

PEG AND DDR

VCC_SENSE

VCCIO_SENSE

VSSIO_SENSE

SENSE LINES SVID

8.5A

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VCCIO41
VCCIO42
VCCIO43
VCCIO44
VCCIO45

VIDALERT#

VIDSCLK

VIDSOUT

VSS_SENSE

VCC121

VCC122

VCC123

VCC124

VCC125

VCC126

VCC127

VCC128

VCC129

VCC130

VCC131

VCC132

VCC133

VCC134

VCC135

VCC136

VCC137

VCC138

VCC139

VCC140

VCC141

VCC142

VCC143

VCC144

VCC145

VCC146

VCC147

VCC148

VCC149

VCC150

VCC151

VCC152

VCC153

VCC154

VCC155

VCC156

VCC157

VCC158

VCC159

VCC160

VCC161

TOP Socket Cavity

22U_0805_6.3V6M

A11
A7

C39

AA3
AB8
AF8
AG33
AJ16
AJ17
AJ26
AJ28
AJ32
AK15
AK17

C43

AK19
AK21
AK23
AK27
AK29

22U_0805_6.3V6M

AK30
B9
D10
D6
E3
E4
G3
G4

C48

J3
J4

560U_2.5V_M

J7
J8
L3
L4
L7
M13
N3
N4
N7
R3
R4

HR's R52=130 ohm

R7
U3

SB CRB suggst 110ohm

U4
U7
V8
W3

R55 43_0402_1%

H_CPU_SVIDALRT#

A37

VR_SVID_CLK_R

C37

VR_SVID_DAT_R

B37

A36
B36

VCCIO_SENSE

AB4
AB3

12

R56
100_0402_1%

J24

+CPU_CORE
J25
J27

J28
J30
K15
K16
K18
K19
K21
K22
K24
K25
K27
K28
K30
L13
L14
L15
L16
L18
L19
L21
L22
L24
L25
L27
L28
L30
M14
M15
M16
M18
M19
M21
M22
M24
M25
M27
M28
M30

+CPU_CORE

D D

C C

B B

A A

JCPU1F

76A (Quad Core 65W)

A12
A13
A14
A15
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35

F15
F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
F31
F32
F33

F34
G15
G16
G18
G19
G21
G22
G24
G25
G27
G28
G30
G31
G32
G33
H13
H14
H15
H16
H18
H19
H21
H22
H24
H25
H27
H28
H30
H31
H32

J12

J15

J16

J18

J19

J21

J22

Sandy Bridge_rPGA_Rev1p0

4

22U_0805_6.3V6M

1

1

C40

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C44

2

2

1

+

C49

2

560U_2.5V_M

R52
110_0402_5%

1 2
1 2

1 2

R1037 0_0402_5%
R1038 0_0402_5%

4

1

C41

C42

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C46

C45

2

22U_0805_6.3V6M

1

+

C50

2

560U_2.5V_M

+1.05VS_VCCIO

90.9_0402_1%

12

@

R53

VCCSENSE [58]
VSSSENSE [ 58]

VCCIO_SENSE [54]

1

2

1

C47

2

22U_0805_6.3V6M

1

+

2

12

12

R54
75_0402_5%

+1.05VS_VCCIO

+1.05VS_VCCP Decoupling:
3X 560U (6m ohm), 9X 22U

1

2

Pull high resistor close to CPU
SVID signal 50 ohm impedance
spacing >12mil length 3-6"

VR_SVID_ALRT# [58]
VR_SVID_CLK [58]
VR_SVID_DAT [58]

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+CPU_CORE Decoupling:
5X 560U (4m ohm), 2X330U, 18X 22U

C51
560U_2.5V_M

330U_D2_2V_Y

22U_0805_6.3V6M

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

2

TOP Socket Edge

+CPU_CORE

1

+

2

C52
560U_2.5V_M

1

+

2

1

+

2

C53
560U_2.5V_M

C54
560U_2.5V_M

1

+

2

1

+

C59
560U_2.5V_M

2

Bottom Socket Edge

+CPU_CORE

1

1

C55

@

+

2

C56

@

330U_D2_2V_Y

1

+

+

C58
330U_D2_2VM_R6M

2

2 3

14 pcs in TOP and 4pcs in BOT Socket Cavity

+CPU_CORE

22U_0805_6.3V6M

1

1

C67

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C77

2

2

Sandy Bridge_POWER-1

1

C61

C60

2

22U_0805_6.3V6M

+CPU_CORE

22U_0805_6.3V6M

1

C70

C71

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C62

2

2

1

1

C72

2

2

22U_0805_6.3V6M

2

22U_0805_6.3V6M

1

C63

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C73

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C64

2

1

C74

2

Date: Sheet

C66

C65

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C75

C76

2

22U_0805_6.3V6M

Title

Size Docum ent Number Rev

Custom

Compal Electronics, Inc.

PCA70 LA-7521P M/B

C68

1

1

C69

2

22U_0805_6.3V6M

1

1

2

0.1

of

864Tuesday, April 12, 2011

5

4

3

2

1

+GFX_CORE Decoupling:
2X 470U (4m ohm), 12X 22U

Bottom

+GFX_CORE

Socket
Edge

D D

C80

@

330U_D2_2VM_R6M

Top Socket Cavity

22U_0805_6.3V6M

C82

UMA@

Bottom Socket Edge

22U_0805_6.3V6M

UMA@

C99

C C

Top Socket Edge

330U_D2_2VM_R6M

1

1

+

+

UMA@

C1588

2

2

330U_D2_2VM_R6M

22U_0805_6.3V6M

UMA@

1

1

C84

C83

UMA@

2

2

22U_0805_6.3V6M

UMA@

1

1

C100

2

2

22U_0805_6.3V6M

1

+

@

C78

2

UMA@

1

1

C85

2

2

22U_0805_6.3V6M

1

+

UMA@

C79

2

560U_2.5V_M

1

+

UMA@

C81
560U_2.5V_M

2

AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40

W33
W34
W35
W36
W37
W38

U33
U34
U35
U36
U37
U38
U39
U40

Y33
Y34
Y35
Y36
Y37
Y38

T33
T34
T35
T36
T37
T38
T39
T40

JCPU1G

35A

VCCAXG1
VCCAXG2
VCCAXG3
VCCAXG4
VCCAXG5
VCCAXG6
VCCAXG7
VCCAXG8
VCCAXG9
VCCAXG10
VCCAXG11
VCCAXG12
VCCAXG13
VCCAXG14
VCCAXG15
VCCAXG16
VCCAXG17
VCCAXG18
VCCAXG19
VCCAXG20
VCCAXG21
VCCAXG22
VCCAXG23
VCCAXG24
VCCAXG25
VCCAXG26
VCCAXG27
VCCAXG28
VCCAXG29
VCCAXG30
VCCAXG31
VCCAXG32
VCCAXG33
VCCAXG34
VCCAXG35
VCCAXG36
VCCAXG37
VCCAXG38
VCCAXG39
VCCAXG40
VCCAXG41
VCCAXG42
VCCAXG43
VCCAXG44

VCCPLL Decoupling:
1X 220U, 2X 10U

+1.8VS

B B

R65 0_0805_5%

+1.8VS_VCCPLL

12

C105

220U_6.3V_M

10U_0805_10V6K

1

1

+

C106

2

2

1

C107

@

2

10U_0805_10V6K

1.5A

AK11

VCCPLL1

AK12

VCCPLL2

Sandy Bridge_rPGA_Rev1p0

POWER

SENSE

VREFMISC DDR3 -1.5V RAILS

GRAPHICS

SA RAIL

1.8V RAIL

VCCAXG_SENSE
VSSAXG_SENSE

LINES

SM_VREF

4.75A

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23

8.8A

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9

VCCSA10
VCCSA11

VCCSA_SENSE

VCCSA_VID

FC_AH1
FC_AH4

L32
M32

+V_SM_VREF should
have 20 mil trace width

AJ22

AJ13
AJ14
AJ20
AJ23
AJ24
AR20
AR21
AR22
AR23
AR24
AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31
AY23
AY26
AY28

22U_0805_6.3V6M

TOP Socket Cavity

10U_0805_10V6K

H10
H11
H12
J10

C101

K10
K11
L11
L12
M10
M11
M12

T2
P34

AH1
AH4

+VREF_DQB_R
+VREF_DQA_R

C108 0.1U_0402_16V4Z

1

1

2

2

10U_0805_10V6K

C109 0.1U_0402_16V4Z

VCC_AXG_SENSE [58]
VSS_AXG_SENSE [58]

+1.5V

12

R61
100_0402_1%

+V_SM_VREF

C86

22U_0805_6.3V6M

C90

1

C102

2

1

0.1U_0402_16V4Z

2

1

1

C91

2

2

22U_0805_6.3V6M

10U_0805_10V6K

1

1

C103

@

2

2

22U_0805_6.3V6M

1

C92

2

C93

+VCCSA

1

+

2

12

R62
100_0402_1%

1

1

C94

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C95

1

1

C96

@

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C97

@

+VCCSA Decoupling:
1X 560U, 2X 10U

C104
560U_2.5V_M

VCCSA_SENSE [56]
VCCSAP_VID1 [56]

1

C98

@

2

22U_0805_6.3V6M

0

1

2

1

1 2
1 2

R66 0_0402_5%
R67 0_0402_5%

R66,R67 should place close to DIMM for

+VREF_DQB
+VREF_DQA

minimum stubs trace

330U_D2_2VM_R6M

1

+

C88

C87

2

330U_D2_2VM_R6M

+VCCSAVCCSA_VID1

0.925 V
(Default)

0.85 V

+1.5V

+1.5V Decoupling:

1

1

+

C89

2

3X 330U , 9X 22U

+

@

330U_D2_2VM_R6M

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_POWER-2

PCA70 LA-7521P M/B

964Tuesday, April 12, 2011

1

0.1

of

5

JCPU1H

A17

VSS1

A23

VSS2

A26

VSS3

A29

VSS4

A35

VSS5

AA33

VSS6

AA34

VSS7

AA35

VSS8

AA36

VSS9

AA37

VSS10

AA38

D D

C C

B B

A A

VSS11

AA6

VSS12

AB5

VSS13

AC1

VSS14

AC6

VSS15

AD33

VSS16

AD36

VSS17

AD38

VSS18

AD39

VSS19

AD40

VSS20

AD5

VSS21

AD8

VSS22

AE3

VSS23

AE33

VSS24

AE36

VSS25

AF1

VSS26

AF34

VSS27

AF36

VSS28

AF37

VSS29

AF40

VSS30

AF5

VSS31

AF6

VSS32

AF7

VSS33

AG36

VSS34

AH2

VSS35

AH3

VSS36

AH33

VSS37

AH36

VSS38

AH37

VSS39

AH38

VSS40

AH39

VSS41

AH40

VSS42

AH5

VSS43

AH8

VSS44

AJ12

VSS45

AJ15

VSS46

AJ18

VSS47

AJ21

VSS48

AJ25

VSS49

AJ27

VSS50

AJ36

VSS51

AJ5

VSS52

AK1

VSS53

AK10

VSS54

AK13

VSS55

AK14

VSS56

AK16

VSS57

AK22

VSS58

AK28

VSS59

AK31

VSS60

AK32

VSS61

AK33

VSS62

AK34

VSS63

AK35

VSS64

AK36

VSS65

AK37

VSS66

AK4

VSS67

AK40

VSS68

AK5

VSS69

AK6

VSS70

AK7

VSS71

AK8

VSS72

AK9

VSS73

AL11

VSS74

AL14

VSS75

AL17

VSS76

AL19

VSS77

AL24

VSS78

AL27

VSS79

AL30

VSS80

AL36

VSS81

AL5

VSS82

AM1

VSS83

AM11

VSS84

AM14

VSS85

AM17

VSS86

AM2

VSS87

AM21

VSS88

AM23

VSS89

AM25

VSS90

AM27

VSS91

AM3

VSS92

AM30

VSS93

AM36

VSS94

AM37

VSS95

AM38

VSS96

AM39

VSS97

AM4

VSS98

AM40

VSS99

AM5

VSS100

Sandy Bridge_rPGA_Rev1p0

VSS

VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200

AN10
AN11
AN14
AN17
AN19
AN22
AN24
AN27
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN5
AN6
AN7
AN8
AN9
AP1
AP11
AP14
AP17
AP22
AP25
AP27
AP30
AP36
AP37
AP4
AP40
AP5
AR11
AR14
AR17
AR18
AR19
AR27
AR30
AR36
AR5
AT1
AT10
AT12
AT13
AT15
AT16
AT17
AT2
AT25
AT27
AT28
AT29
AT3
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT4
AT40
AT5
AT6
AT7
AT8
AT9
AU1
AU15
AU26
AU34
AU4
AU6
AU8
AV10
AV11
AV14
AV17
AV3
AV35
AV38
AV6
AW10
AW11
AW14
AW16
AW36
AW6
AY11
AY14
AY18
AY35
AY4
AY6
AY8

B10
B13
B14
B17
B23
B26
B29
B32
B35
B38

B6
C11
C12
C17
C20
C23
C26
C29
C32
C35

C7
C8

D17

D2
D20
D23
D26
D29
D32
D37
D39

D4

D5

D9
E11
E12
E17
E20
E23
E26
E29
E32
E36

E7
E8

F1
F10
F13
F14
F17

F2
F20
F23
F26
F29
F35
F37
F39

F5

F6

F9
G11
G12
G17
G20
G23
G26
G29
G34

G7
G8
H1

H17

H2
H20
H23
H26
H29
H33
H35
H37
H39

H5

H6

H9

J11
J17
J20
J23
J26
J29
J32

K1
K12
K13
K14
K17

K2
K20
K23

4

JCPU1I

VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300

Sandy Bridge_rPGA_Rev1p0

VSS

VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4

K26
K29
K33
K35
K37
K39
K5
K6
L10
L17
L20
L23
L26
L29
L8
M1
M17
M2
M20
M23
M26
M29
M33
M35
M37
M39
M5
M6
M9
N8
P1
P2
P36
P38
P40
P5
P6
R33
R35
R37
R39
R8
T1
T5
T6
U8
V1
V2
V33
V34
V35
V36
V37
V38
V39
V40
V5
W6
Y5
Y8

A4
AV39
AY37
B3

T236PAD
T15 PAD

T16 PAD

T17 PAD
T18 PAD
T19 PAD
T20 PAD
T21 PAD
T22 PAD
T23 PAD
T24 PAD
T25 PAD
T26 PAD
T27 PAD

3

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6 CFG5
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

JCPU1E

H36

CFG[0]

J36

CFG[1]

J37

CFG[2]

K36

CFG[3]

L36

CFG[4]

N35

CFG[5]

L37

CFG[6]

M36

CFG[7]

J38

CFG[8]

L35

CFG[9]

M38

CFG[10]

N36

CFG[11]

N38

CFG[12]

N39

CFG[13]

N37

CFG[14]

N40

CFG[15]

G37

CFG[16]

G36

CFG[17]

AB6

RSVD1

AB7

RSVD2

AD37

RSVD3

AE6

RSVD4

AF4

RSVD5

AG4

RSVD6

AJ11

RSVD7

AJ29

RSVD8

AJ30

RSVD9

AJ31

RSVD10

AN20

RSVD11

AP20

RSVD12

AT11

RSVD13

AT14

RSVD14

AU10

RSVD15

AV34

RSVD16

AW34

RSVD17

AY10

RSVD18

C38

RSVD19

C39

RSVD20

D38

RSVD21

H7

RSVD22

H8

RSVD23

J33

RSVD24

J34

RSVD25

J9

RSVD26

K34

RSVD27

K9

RSVD28

L31

RSVD29

L33

RSVD30

L34

RSVD31

L9

RSVD32

M34

RSVD33

N33

RSVD34

N34

RSVD35

P35

RSVD36

P37

RSVD37

P39

RSVD38

R34

RSVD39

R36

RSVD40

R38

RSVD41

R40

RSVD42

J31

RSVD43

AD34

RSVD44

AD35

RSVD45

K31

RSVD46

Sandy Bridge_rPGA_Rev1p0

RESERVED

VCCIO_SEL

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4

NCTF1
NCTF2
NCTF3
NCTF4
NCTF5

2

CFG Straps for Processor

(CFG[17:0] internal pull high to VCCIO)

PEG Static x16 Lane Numbering Reversal.

CFG2

PEG Static x4 Lane Numbering Reversal.

CFG3

1: Normal Operation
0:Lane numbers Reversed

*

1: Normal Operation

*

0:Lane numbers Reversed

PCIE Port Bifurcation Straps

11: 1x16 PCI Express (Default)

*

CFG[6:5]

10: 2x8 PCI Express
01: Reserved
00: 1 x 8, 2 x 4 : PCI Express

A38
AU40
AW38
C2
D1

P33

AV1
AW2
AY3
B39

R1664

0_0402_5%

1 2

+5VS

1 2

1 2

CFG2

R70 1K_0402_1%

CFG3
CFG6

R1576
10K_0402_1%

R1577

5.1K_0402_1%

1 2

R71 1K_0402_1%@

1 2

R73 1K_0402_1%@

1 2

R74 1K_0402_1%@

1 2

VCCIO_SEL [54]

VCCIO_SEL

1

Reserve for PW

VCCIO

0

1

1.00V

1.05V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_GND/RSVD/CFG

PCA70 LA-7521P M/B

1

of

10 64Tuesday, April 12, 2011

0.1

5

DDR_A_DQS[0..7][7]

DDR_A_DQS#[0..7][7]

DDR_A_D[0..63][7]

D D

C C

Layout Note:
Place near JDDRL1

+1.5V

B B

A A

+

C143 390U_2.5V_M_R10

1 2

C145 10U_0805_6.3V6M

1 2

C147 10U_0805_6.3V6M

1 2

C149 10U_0805_6.3V6M

1 2

C151 10U_0805_6.3V6M

1 2

C152 10U_0805_6.3V6M

1 2

C153 10U_0805_6.3V6M

1 2

DDR_A_MA[0..15][7]

Layout Note:
Place near JDDRL1.203 and 204

+0.75VS

C134 10U_0805_6.3V6M

1 2

C135 1U_0402_6.3V6K

1 2

C136 1U_0402_6.3V6K

1 2

C139 1U_0402_6.3V6K

1 2

C140 1U_0402_6.3V6K

1 2

Layout Note : P la ce these 4 Caps near
Command and Control signals of JDDRL1

+1.5V

C144 0.1U_0402_16V4Z

1 2

C146 0.1U_0402_16V4Z

1 2

C148 0.1U_0402_16V4Z

1 2

C150 0.1U_0402_16V4Z

1 2

4

+1.5V

R91

1K_0402_1%

1 2

1K_0402_1%

3

CHA SO-DIMM 0(A0)

+0.75VS

12

R98
10K_0402_5%

+1.5V

JDDRL2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013290-1

CONN@

DQS#0

DQS0

DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3
DQ30

DQ31

VDD2

VDD4

VDD6

VDD8

VDD10

VDD12

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30
VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42
VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

+VREF_DQA

12

R93

2.2U_0603_6.3V6K

0.1U_0402_16V4Z
C114

1

2

Close to JDDRL.1

DDR_A_BS2[7]

DDRA_CLK0[7]
DDRA_CLK0#[7]

DDR_A_BS0[7]

DDR_A_WE#[7]

DDR_A_CAS#[7]

DDRA_SCS1#[7]

+3VS

2.2U_0603_6.3V6K
C154

+VREF_DQA
DDR_A_D0

DDR_A_D1

C115

1

2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDRA_CKE0 DDRA_CKE1

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1

DDRA_CLK0# DDRA_CLK1#
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_A_MA13

DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

R97 10K_0402_5%

1 2

0.1U_0402_16V4Z
C155

1

1

2

2

DQ4
DQ5

VSS3

VSS6

DQ6
DQ7

VSS8

DM1

DM2

CKE1

CK1

CK1#

RAS#

NC2

DM4

DM6

SDA
SCL

VTT2

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26
28

SM_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44
46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

74
76

DDR_A_MA15

78

A15
A14

A11

A7
A6

A4
A2

A0

BA1

S0#

G2

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

DDRA_CLK1DDRA_CLK0

102
104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDRA_SCS0#

114

DDRA_ODT0

116
118

DDRA_ODT1

120
122
124

+VREF_CAA

126
128

DDR_A_D36

130

DDR_A_D37

132
134
136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168
170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198

PM_SMBDATA

200

PM_SMBCLK

202
204

+0.75VS

206

2

SM_DRAMRST# [5,12]

DDRA_CKE1 [ 7 ]DDRA_CKE0[7]

DDRA_CLK1 [7]
DDRA_CLK1# [7]

DDR_A_BS1 [7]
DDR_A_RAS# [7]

DDRA_SCS0# [7]
DDRA_ODT0 [7]

DDRA_ODT1 [7]

2.2U_0603_6.3V6K

close to JDDRL1.126

PM_SMBDATA [12,14,40]
PM_SMBCLK [12,14,40]

1

+1.5V

12

R94
1K_0402_1%

12

R96

0.1U_0402_16V4Z

C137

C138

1

1

2

2

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMMA

PCA70 LA-7521P M/B

1

11 64Tuesday, April 12, 2011

0.1

of

A

DDR_B_DQS#[0..7][7]

DDR_B_DQS[0..7][7]

DDR_B_D[0..63][7]

DDR_B_MA[0..15][7]

1 1

2 2

Layout Note:
Place near JDDRL2.203 and 204

+0.75VS

C178 10U_0805_6.3V6M

1 2

C179 1U_0402_6.3V6K

1 2

C182 1U_0402_6.3V6K

1 2

C183 1U_0402_6.3V6K

1 2

C184 1U_0402_6.3V6K

1 2

3 3

Layout Note:
Place near JDDRL2

+1.5V

4 4

+

C187 390U_2.5V_M_R10

1 2

C189 10U_0805_6.3V6M

1 2

C191 10U_0805_6.3V6M

1 2

C193 10U_0805_6.3V6M

1 2

C195 10U_0805_6.3V6M

1 2

C196 10U_0805_6.3V6M

1 2

C197 10U_0805_6.3V6M

1 2

Layout Note : P la ce these 4 Caps near
Command and Control signals of JDDRL2

+1.5V

C188 0.1U_0402_16V4Z

1 2

C190 0.1U_0402_16V4Z

1 2

C192 0.1U_0402_16V4Z

1 2

C194 0.1U_0402_16V4Z

1 2

B

R101
1K_0402_1%

1 2

+1.5V

R103

1K_0402_1%

12

0.1U_0402_16V4Z

2.2U_0603_6.3V6K
C158

1

2

Close to JDDRL2.1

DDR_B_BS2[7]

DDRB_CLK0[7]

DDRB_CLK0#[7]

DDR_B_BS0[7] DDR_B_RAS# [7]

DDR_B_WE#[7]

DDR_B_CAS#[7]

DDRB_SCS1#[7]

+3VS

1

C198

2.2U_0603_6.3V6K

2

C

CHB SO-DIMM 0(A4)

+1.5V+VREF_DQB

JDDRH1

VREF_DQ1VSS1

3

DDR_B_D0
DDR_B_D1

C159

1

DDR_B_D2
DDR_B_D3

2

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
DDRB_CLK0 DDRB_CLK1

DDRB_CLK0# DDRB_CLK1#
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDRB_SCS1#

DDR_B_D37
DDR_B_D36

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54 DDR_B_D51
DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_D58 DDR_B_D62
DDR_B_D59

R107 10K_0402_5%

1 2

1 2

R108

+0.75VS +0.75VS

10K_0402_5%

1

C199

0.1U_0402_16V4Z

2

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013311-1
@

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

VSS12

DQ14
DQ15

VSS14

DQ20
DQ21

VSS16

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

VSS24

DQ30
DQ31

VSS26

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2

A15
A14

A11

BA1

S0#

D

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26
28

SM_DRAMRST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44
46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDRB_CKE1DDRB_CKE0

74
76

DDR_B_MA15

78

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6
A4

A2
A0

G2

DDR_B_MA4

92
94

DDR_B_MA2

96

DDR_B_MA0

98
100
102
104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDRB_SCS0#

114

DDRB_ODT0

116
118

DDRB_ODT1

120
122
124

+VREF_CAB

126
128

DDR_B_D32

130

DDR_B_D33

132
134
136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168
170
172

DDR_B_D50

174
176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190
192

DDR_B_D63

194
196
198

PM_SMBDATA

200

PM_SMBCLK

202
204

206

SM_DRAMRST# [5,11]

DDRB_CKE1 [7]DDRB_CKE0[7]

DDRB_CLK1 [7]
DDRB_CLK1# [7]

DDR_B_BS1 [7]

DDRB_SCS0# [7]
DDRB_ODT0 [7]

DDRB_ODT1 [7]

2.2U_0603_6.3V6K
C180

Close to JDDRL2.126

PM_SMBDATA [11,14,40]
PM_SMBCLK [11,14,40]

+1.5V

12

R104
1K_0402_1%

12

R106

0.1U_0402_16V4Z
C181

1

2

1K_0402_1%

1

2

E

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM B

PCA70 LA-7521P M/B

E

12 64Tuesday, April 12, 2011

0.1

of

5

+RTCVCC

CMOS Setting, near DDR Door

R111
20K_0402_5%

1 2

PCH_RTCRST#

RC Delay 18~25mS

iME Setting.

R115
20K_0402_5%

D D

*

C C

*

B B

RC Delay 18~25mS

Integrated SUS 1.05V VRM Enable

PCH_INTVRMEN

+RTCVCC

R122

1 2

+RTCVCC

R121

1 2

+3VS

1 2

R126 10K_0402_5%

+3VALW

1 2

R133 10K_0402_5%

PCH_SPKR

High = Enabled (N o Reboot)
Low = Disabled (Default)

+3VS

HDA_SYNC

This signal has a weak internal pull down
H=>On Die PLL is supplied by 1.5V (mobile)
L=>On Die PLL is supplied by 1.8V (DT)
Need to pull high for Huron River platform

AZ_SYNC_HD[47]

HDA_SDO

ME debug mode,
this signal has a weak internal pull down
Low = Disable (default)

*

High = Enable (flash descriptor security overide)

PCH_SPIDI
PCH_SPICLK
PCH_SPICS#
PCH_SPIDO

@

1 2

R131 1K_0402_5%

No mention on SB PDG
but HR mention on PDG
reserve for
Potential Leakage Concern

PWRME_CTRL#[49]

R143 0_0402_5%
R144 0_0402_5%
R145 0_0402_5%
R146 0_0402_5%

PCH_SRTCRST#

1 2

High - Enable Internal VRs
(must be always pulled high)

390K_0402_5%

1 2
1 2
1 2
1 2

PCH_INTVRMEN

1M_0402_5%

SM_INTRUDER#

PCH_GPIO33

PCH_GPIO13

+3VALW

1 2

R139 33_0402_5%

PWRME_CTRL# AZ_SDOUT

R129

1 2

R134 1K_0402_5%@

C203

1U_0402_6.3V6K

C205

1U_0402_6.3V6K

PCH_SPKR

R136 1K_0402_5%@

AZ_SYNC_R

1 2

DI
CLK
CS#
DO

JCOMS1 CONN@

1 2
1 2

JME1 CONN@

1 2
1 2

12

+5VS

G

2

@

Q2

13

D

S

BSS138LT1G_SOT23-3

1 2

R140 0_0402_5%

0_0402_5%@

32.768KHZ_12.5PF_Q13MC14610002

AZ_SYNC

4

12

C202 15P_0402_50V8J
Y1

2

OSC

NC

3

OSC

NC

12

C204 15P_0402_50V8J

AZ_BITCLK_HD[47]

AZ_RST_HD#[47]

+3VALW

AZ_SDOUT_HD[47]

1
4

R113

10M_0402_5%

1 2

R118 33_0402_5%

PCH_SPKR[47]

1 2

R120 33_0402_5%

AZ_SDIN0_HD[47]

@

R124 1K_0402_5%

1 2

R125 33_0402_5%

12

12

PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN

AZ_BITCLK
AZ_SYNC
PCH_SPKR
AZ_RST#

AZ_SDIN0_HD

AZ_SDOUT

PCH_GPIO33
PCH_GPIO13

PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO

PCH_SPICLK
PCH_SPICS#

PCH_SPIDI
PCH_SPIDO

3

U4A

BR39

RTCX1

BN39

RTCX2

BT41

RTCRST#

BN37

SRTCRST#

BM38

INTRUDER#

BN41

INTVRMEN

BU22

HDA_BCLK

BP23

HDA_SYNC

BE56

SPKR

BC22

HDA_RST#

BD22

HDA_SDIN0

BF22

HDA_SDIN1

BK22

HDA_SDIN2

BJ22

HDA_SDIN3

BT23

HDA_SDO

BC25

HDA_DOCK_EN# / GPIO33

BA25

HDA_DOCK_RST# / GPIO13

BA43

JTAG_TCK

BC50

JTAG_TMS

BC52

JTAG_TDI

BF47

JTAG_TDO

AR54

SPI_CLK

AT57

SPI_CS0#

AR56

SPI_CS1#

AU53

SPI_MOSI

AT55

SPI_MISO

BD82CPDS-QMZP-B0_FCBGA942

RTCIHDA

JTAG

SPI

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19

2

LPC_AD0

BK15

LPC_AD1

BJ17

LPC_AD2

BJ20

LPC_AD3

BG20

LPC_FRAME#

BG17
BK17

BA20

SERIRQ

AV52

SATA_PRX_C_DTX_N0

AC56

SATA_PRX_C_DTX_P0

AB55

SATA_PTX_DRX_N0

AE46

SATA_PTX_DRX_P0

AE44

SATA_PRX_C_DTX_N1

AA53

SATA_PRX_C_DTX_P1

AA56

SATA_PTX_DRX_N1

AG49

SATA_PTX_DRX_P1

AG47
AL50

AL49
AL56
AL53

SATA port2 and port3 are disabled on H61

AN46
AN44
AN56
AM55

SATA_PRX_C_DTX_N4

AN49

SATA_PRX_C_DTX_P4

AN50

SATA_PTX_DRX_N4

AT50

SATA_PTX_DRX_P4

AT49
AT46

AT44

Place R128 and R130 within 500

AV50
AV49

mils of the PCH. Avoid routing

AJ53

next to clock pins.

SATAICOMP

AJ55

AE52
AE54

AC52

BF57
BC54
AY52

SATA3_COMP

RBIAS_SATA3

SATA_LED#
CR_WAKE#
GPIO19

R128 37.4_0402_1%

R130 49.9_0402_1%

R132 750_0402_1%

LPC_AD0 [49]
LPC_AD1 [49]
LPC_AD2 [49]
LPC_AD3 [49]

LPC_FRAME# [49]

SERIRQ [ 49]

SATA_PRX_C_DTX_N0 [41]
SATA_PRX_C_DTX_P0 [41]

1 2

C206 0.01U_0402_25V7K

1 2

C207 0.01U_0402_25V7K

SATA_PRX_C_DTX_N1 [41]
SATA_PRX_C_DTX_P1 [41]

1 2

C208 0.01U_0402_25V7K
C209 0.01U_0402_25V7K

C1390 0.01U_0402_25V7K
C1391 0.01U_0402_25V7K

1 2

1 2

1 2

1 2

SATA_PRX_C_DTX_N4 [40]
SATA_PRX_C_DTX_P4 [40]

1 2

1 2

SATA_LED# [50]
CR_WAKE# [44]

+1.05VS_VPCH

+1.05VS_VPCH

12

12

1

SERIRQ

SATA_LED#

CR_WAKE#

GPIO19

SATA_PTX_C_DRX_N0 [41]
SATA_PTX_C_DRX_P0 [41]

SATA_PTX_C_DRX_N1 [41]
SATA_PTX_C_DRX_P1 [41]

R112 10K_0402_5%

R114 10K_0402_5%

R116 10K_0402_5%

R117 10K_0402_5%

HDD

12

12

12

1 2

ODD

for EMI

R137

SATA_PTX_C_DRX_N4 [40]
SATA_PTX_C_DRX_P4 [40]

+RTCVCC

D1

1

1

C210

DAN202UT106_SC70-3

0.1U_0402_16V4Z

2

+3VALW +3VALW+3VALW

R147
200_0402_5%

@

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI

R151
100_0402_1%

1 2

R154 51_0402_1%

12

R148
200_0402_5%

@

12

R152
100_0402_1%

PCH_JTAG_TCK

10_0402_5%

10P_0402_50V8J

R1039

1K_0402_5%

2
3

R149
200_0402_5%

@

1 2

R153
100_0402_1%

1 2

@

C214

@

+3VALW

12

CLK

12

1

2

+RTCBATT

+3VS

+3VS

+3VALW

4M Byte

CS#
DO

A A

U6

1

CS#

2

DO

HOLD#

3

WP#

4

GND

W25Q32BVSSIG_SO8

VCC

8
7
6

CLK

5

DI

1

C212

0.1U_0402_16V4Z

2

CLK
DI

Socket: SP07000F500/SP07000H900
Please close to U2 PCH

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

2

Title

Size Docum ent Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_HDA/JTAG/SATA/SPI/LPC

PCA70 LA-7521P M/B

1

of

13 64Tuesday, April 12, 2011

0.1

5

PCIE_PRX_C_USBTX_N2[45]

USB30

WLAN

D D

TV

Card reader

LAN

PCIE_PRX_C_USBTX_P2[45]
PCIE_PTX_C_USBRX_N2[45]
PCIE_PTX_C_USBRX_P2[45]

PCIE_PRX_WLANTX_N3[42]
PCIE_PRX_WLANTX_P3[42]
PCIE_PTX_C_WLANRX_N3[42]
PCIE_PTX_C_WLANRX_P3[42]

PCIE_PRX_TVTX_N4[42]
PCIE_PRX_TVTX_P4[42]
PCIE_PTX_C_TVRX_N4[42]
PCIE_PTX_C_TVRX_P4[42]

PCIE_PRX_C_RTX_N5[44]
PCIE_PRX_C_RTX_P5[44]
PCIE_PTX_C_CRRX_N5[44]
PCIE_PTX_C_CRRX_P5[44]

PCIE_PRX_C_LANTX_N6[43]
PCIE_PRX_C_LANTX_P6[43]
PCIE_PTX_C_LANRX_N6[43]
PCIE_PTX_C_LANRX_P6[43]

C218 0.1U_0402_16V7K

1 2

C219 0.1U_0402_16V7K

1 2

C226 0.1U_0402_16V7K

12

C227 0.1U_0402_16V7K

12

C222 0.1U_0402_16V7K

1 2

C223 0.1U_0402_16V7K

1 2

C224 0.1U_0402_16V7K

12

C225 0.1U_0402_16V7K

12

C220 0.1U_0402_16V7K

12

C221 0.1U_0402_16V7K

12

PCIE_PRX_C_USBTX_N2
PCIE_PRX_C_USBTX_P2
PCIE_PTX_USBRX_N2
PCIE_PTX_USBRX_P2

PCIE_PRX_WLANTX_N3
PCIE_PRX_WLANTX_P3
PCIE_PTX_WLANRX_N3
PCIE_PTX_WLANRX_P3

PCIE_PRX_TVTX_N4

PCIE_PRX_TVTX_P4
PCIE_PTX_TVRX_N4
PCIE_PTX_TVRX_P4

PCIE_PRX_C_RTX_N5
PCIE_PRX_C_RTX_P5
PCIE_PTX_CRRX_N5
PCIE_PTX_CRRX_P5

PCIE_PRX_C_LANTX_N6
PCIE_PRX_C_LANTX_P6
PCIE_PTX_LANRX_N6
PCIE_PTX_LANRX_P6

PCI-E port7 and port8 are disabled on H61

C C

R168 0_0402_5%
R169 0_0402_5%

USB30

WLAN

TV

Card Reader

LAN

B B

CLK_BCLK_ITP#[5]
CLK_BCLK_ITP[5]

+3VS

R200 10K_0402_5%

A A

1 2

CLK_USB30#[45]
CLK_USB30[45]

CLK_WLAN#[42]
CLK_WLAN[42]

CLKREQ_WLAN#[42]

CLK_TV#[42]
CLK_TV[42]

CLK_CR#[44]
CLK_CR[44]

CLKREQ_LAN#[43]

R7 0_0402_5%@
R5 0_0402_5%@

CLKREQ_WLAN#_R

CLK_LAN#[43]
CLK_LAN[43]

Close to PCH side

1 2
1 2

R190 0_0402_5%
R191 0_0402_5%

1 2
1 2

1 2

R192 0_0402_5%@
R178 0_0402_5%

1 2

1 2

R180 0_0402_5%

R184 0_0402_5%

1 2

1 2

R186 0_0402_5%
R172 0_0402_5%

R173 0_0402_5%

1 2

1 2

1 2

R175 0_0402_5%@

12
12

4

CLK_USB30#_R
CLK_USB30_R

CLK_WLAN#_R
CLK_WLAN_R

CLKREQ_WLAN#_R

CLK_TV#_R
CLK_TV_R

CLK_CR#_R
CLK_CR_R

CLK_LAN#_R
CLK_LAN_R

CLKREQ_LAN#_R

CLK_CPU_ITP#
CLK_CPU_ITP

U4B

J20

PERN1

L20

PERP1

F25

PETN1

F23

PETP1

P20

PERN2

R20

PERP2

C22

PETN2

A22

PETP2

H17

PERN3

J17

PERP3

E21

PETN3

B21

PETP3

P17

PERN4

M17

PERP4

F18

PETN4

E17

PETP4

N15

PERN5

M15

PERP5

B17

PETN5

C16

PETP5

J15

PERN6

L15

PERP6

A16

PETN6

B15

PETP6

J12

PERN7

H12

PERP7

F15

PETN7

F13

PETP7

H10

PERN8

J10

PERP8

B13

PETN8

D13

PETP8

AE6

CLKOUT_PCIE0N

AC6

CLKOUT_PCIE0P

AA5

CLKOUT_PCIE1N

W5

CLKOUT_PCIE1P

AB12

CLKOUT_PCIE2N

AB14

CLKOUT_PCIE2P

AV43

PCIECLKRQ2# / GPIO20

AB9

CLKOUT_PCIE3N

AB8

CLKOUT_PCIE3P

Y9

CLKOUT_PCIE4N

Y8

CLKOUT_PCIE4P

AF3

CLKOUT_PCIE5N

AG2

CLKOUT_PCIE5P

BL54

PCIECLKRQ5# / GPIO44

AE12

CLKOUT_PEG_B_N

AE11

CLKOUT_PEG_B_P

AB3

CLKOUT_PCIE6N

AA2

CLKOUT_PCIE6P

AV44

PCIECLKRQ6# / GPIO45

AE2

CLKOUT_PCIE7N

AF1

CLKOUT_PCIE7P

BP55

PCIECLKRQ7# / GPIO46

R52

CLKOUT_ITPXDP_N

N52

CLKOUT_ITPXDP_P

BD82CPDS-QMZP-B0_FCBGA942

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

CLKIN_GND1_N
CLKIN_GND1_P

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_GND0_N
CLKIN_GND0_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

3

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N
CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

PCH_GPIO11

BN49

PCH_SMBCLK

BT47

PCH_SMBDATA

BR49

PCH_GPIO60

BU49

PCH_SMLCLK0

BT51

PCH_SMLDATA0

BM50

PCH_GPIO74

BR46

PCH_SMLCLK1

BJ46

PCH_SMLDATA1

BK46

BA50

Control Link only for support Intel IAMT.

BF50

BF49

R165 0_0402_5%
R167 0_0402_5%

AG8
AG9

P31
R31

N56
M55

P33
R33

W53
V52

R27
P27

BD38
BF38

AF55
AG56

AN8

BD15

AJ3
AJ5

AL2

AT9
BA5
AW5
BA2

CLK_PCIE_VGA#_R
CLK_PCIE_VGA_R

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_DPLL#
CLK_DPLL

PCH_CLK_DMI#
PCH_CLK_DMI

CLKIN_GND0#
CLKIN_GND0

CLKIN_GND1#
CLKIN_GND1

CLK_DOT#
CLK_DOT

CLK_SATA#
CLK_SATA

CLK_14M_PCH

CLK_PCILOOP

PCH_X1
PCH_X2

XCLK_RCOMP

CLK_FLEX0
CLK_FLEX1
CLK_FLEX2
CLK_FLEX3

1 2
1 2

CLK_CPU_DMI# [5]
CLK_CPU_DMI [5]

T65 PAD
T66 PAD

CLK_PCILOOP [17]

1 2

R194 90.9_0402_1%

T252 PAD
T176 PAD
T177 PAD
T178 PAD

2

R155 2.2K_0402_5%

+3VALW +3VS

CLK_PCIE_VGA# [2 2 ]
CLK_PCIE_VGA [22]

12

R156 2.2K_0402_5%

12

PCH_SMBDATA

PCH_SMBCLK

PCH_SMLDATA1

PCH_SMLCLK1

3 4

R159 2.2K_0402_5%

12

R160 2.2K_0402_5%

12

VGA

6 1

5

Q4A
2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6
Q4B

6 1

2N7002KDWH_SOT363-6

5

3 4

PCH_GPIO11
PCH_GPIO60
PCH_GPIO74
PCH_SMLCLK0
PCH_SMLDATA0

Q5A

2N7002KDWH_SOT363-6
Q5B

2

2

1

R157 4.7K_0402_5%

R158 4.7K_0402_5%

PM_SMBDATA [11,12,40]

+3VS+3VALW

EC_SMB_DA2 [23,49,52]

EC_SMB_CK2 [23,49,52]

R161 10K_0402_5%

1 2

R162 2.2K_0402_5%
R163 10K_0402_5%
R164 2.2K_0402_5%
R166 2.2K_0402_5%

12

1 2

12
12

not using eDP level NC

From Clock Gen.

PCH_CLK_DMI#
PCH_CLK_DMI

CLKIN_GND1#
CLKIN_GND1

CLK_DOT#
CLK_DOT

CLK_SATA#
CLK_SATA

CLK_14M_PCH
CLKIN_GND0#

CLKIN_GND0

R174 10K_0402_5%

1 2

R176 10K_0402_5%

1 2

R177 10K_0402_5%

1 2

R179 10K_0402_5%

1 2

R181 10K_0402_5%

1 2

R182 10K_0402_5%

1 2

R183 10K_0402_5%

1 2

R185 10K_0402_5%

1 2

R187 10K_0402_5%

1 2

R188 10K_0402_5%

1 2

R189 10K_0402_5%

1 2

For EMI

+1.05VS_VPCH

CLK_PCILOOP

27P_0402_50V8J

@

12

R193 10_0402_5%

R198 1M_0402_5%

PCH_X1 PCH_X2

1 2

25MHZ_20PF_X5H025000DK1H

1

C229

2

C228 22P_0402_50V8J

12

Y2

PM_SMBCLK [11,12,40]

+3VALW

@

12

1

C230
27P_0402_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_PCI-E/SMBUS/CLK

PCA70 LA-7521P M/B

14 64Tuesday, April 12, 2011

1

0.1

of

5

4

3

2

1

DMI_CTX_PRX_N0[6]
DMI_CTX_PRX_N1[6]
DMI_CTX_PRX_N2[6]

+1.05VS_VPCH

PM_PWROK

DRAMPWROK[5]

SUSWARN#[49]

PBTN_OUT#[49]

+3VALW

DMI_CTX_PRX_N3[6]
DMI_CTX_PRX_P0[6]

DMI_CTX_PRX_P1[6]
DMI_CTX_PRX_P2[6]
DMI_CTX_PRX_P3[6]

DMI_PTX_CRX_N0[6]
DMI_PTX_CRX_N1[6]
DMI_PTX_CRX_N2[6]
DMI_PTX_CRX_N3[6]

DMI_PTX_CRX_P0[6]
DMI_PTX_CRX_P1[6]
DMI_PTX_CRX_P2[6]
DMI_PTX_CRX_P3[6]

1 2

R210 49.9_0402_1%

1 2

R212 750_0402_1%

R215 0_0402_5%@

1 2

R1063 0_0402_5%

@

1 2

R219 0_0402_5%

@

1 2

R1064 0_0402_5%

@

R220 10K_0402_5%

EC_SWI#[49]

+3VALW

D D

SYS_PWROK

C C

Stuff R137 if EC does not want to
involve in the handshake mechanism
for the DeepSX state entry and exit

B B

R204 10K_0402_5%
R205 10K_0402_5%
R206 10K_0402_5%

R208 10K_0402_5%
R209 10K_0402_5%

0.1U_0402_16V4Z

VGATE[49,58]

PM_PWROK[49]

12
12
12

12
12

1 2

C231

1
2

@

R217 0_0402_5%

SUSWARN#_R
EC_SWI#_R
PCH_GPIO72

PCH_RSMRST#
PM_PWROK

+3VS

U9

5

SN74AHC1G08DCKR_SC70-5

P

IN1

4

O

IN2

G

3

SUSWARN#_RSUSACK#

12

12

R211
10K_0402_5%

XDP_DBRESET#[5]

PCH_RSMRST#[49]

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_COMP

RBIAS_CPY

SUSACK#

XDP_DBRESET#

SYS_PWROK

1 2

PWROK_R

DRAMPWROK

PCH_RSMRST#_R

SUSWARN#_R

PBTN_OUT#_R

PCH_GPIO31

12

PCH_GPIO72

EC_SWI#_R

1 2

R1009 0_0402_5%

U4C

D33

DMI0RXN

A36

DMI1RXN

B37

DMI2RXN

E37

DMI3RXN

B33

DMI0RXP

B35

DMI1RXP

C36

DMI2RXP

F38

DMI3RXP

J36

DMI0TXN

P38

DMI1TXN

H38

DMI2TXN

M41

DMI3TXN

H36

DMI0TXP

R38

DMI1TXP

J38

DMI2TXP

P41

DMI3TXP

E31

DMI_ZCOMP

B31

DMI_IRCOMP

A32

DMI2RBIAS

BP45

SUSACK#

BE52

SYS_RESET#

BJ53

SYS_PWROK

BJ38

PWROK

BC46

APWROK

BG46

DRAMPWROK

BK38

RSMRST#

BU46

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

BT43

PWRBTN#

BG43

GPIO31

AV46

BATLOW# / GPIO72

BJ48

RI#

BD82CPDS-QMZP-B0_FCBGA942

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

F45
H41
C46
B45
B47
J43
M43

B43
F43
J41
D47
A46
C49
H43
P43

H46
B51
C52
E49
D51

BR42

BT37

BC44

BC56

BN54

BA47

BH50

BN52

BM53

BC41

BD43

F55

BH49

FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWVREN

PCH_DPWROK

PCIE_WAKE#

PM_CLKRUN#

SUS_STAT#

SUSCLK_P

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

FDI_CTX_PRX_N0

C42

FDI_CTX_PRX_N0 [6]
FDI_CTX_PRX_N1 [6]
FDI_CTX_PRX_N2 [6]
FDI_CTX_PRX_N3 [6]
FDI_CTX_PRX_N4 [6]
FDI_CTX_PRX_N5 [6]
FDI_CTX_PRX_N6 [6]
FDI_CTX_PRX_N7 [6]

FDI_CTX_PRX_P0 [6]
FDI_CTX_PRX_P1 [6]
FDI_CTX_PRX_P2 [6]
FDI_CTX_PRX_P3 [6]
FDI_CTX_PRX_P4 [6]
FDI_CTX_PRX_P5 [6]
FDI_CTX_PRX_P6 [6]
FDI_CTX_PRX_P7 [6]

FDI_INT [6]
FDI_FSYNC0 [6]
FDI_FSYNC1 [6]
FDI_LSYNC0 [6]
FDI_LSYNC1 [6]

PCIE_WAKE# [42,43,45]

T69 PAD

T253 PAD

PM_SLP_S5# [49]

PM_SLP_S4# [49]

PM_SLP_S3# [49]

T70 PAD

T71 PAD

H_PM_SYNC [5]

32.768 KHz

1 2

R207 0_0402_5%@

PCH_RSMRST#PCH_DPWROK

Stuff R222 if do not support DeepSX state

+RTCVCC

DSWVREN

DSWVREN - Internal Deep Sleep 1.05V regulator
H

：

*

LGDisable

PM_CLKRUN#

PCIE_WAKE#
PCH_GPIO29

PCH_GPIO29 default GPI
PU to +3VALW base on module design.

H_PM_SYNC

ESD request Close to U4.F55

R213 390K_0402_5%

1 2

Enable

@

R218 8.2K_0402_5%

R221 1K_0402_5%
R222 10K_0402_5%

1 2

C1595 0.1U_0402_16V4Z

1 2

1 2
1 2

+3VS

+3VALW

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_DMI/FDI/PM

PCA70 LA-7521P M/B

15 64Tuesday, April 12, 2011

1

0.1

of

5

NOTE:PCH adds support for panel power sequencing required for
embedded DisplayPort support. L_VDDEN, L_BKLTEN and L_BKLTCTL pins are
added on the PCH for panel power sequencing. It is important to note that a 6
layer board design may be required to access these pins on the PCH package
in a fully featured platform design.

UMA_ENBKL[49]

D D

C C

T73 PAD
T74 PAD

T229 PAD
T230 PAD
T231 PAD

T232 PAD
T233 PAD

T234 PAD
T235 PAD

T75 PAD
T76 PAD
T77 PAD
T78 PAD
T80 PAD
T82 PAD
T83 PAD
T84 PAD
T85 PAD
T86 PAD
T88 PAD
T89 PAD
T91 PAD
T93 PAD
T95 PAD
T97 PAD
T99 PAD
T101 PAD
T103 PAD
T105 PAD
T106 PAD
T107 PAD
T108 PAD
T109 PAD
T110 PAD
T111 PAD
T112 PAD
T113 PAD
T114 PAD
T115 PAD
T116 PAD
T117 PAD
T118 PAD
T119 PAD
T120 PAD
T121 PAD

R246 1K_0402_0.5%

For debug only

4

UMA_ENBKL
UMA_ENVDD
PCH_PWM

UMA_CRT_B
UMA_CRT_G
UMA_CRT_R

UMA_CRT_CLK
UMA_CRT_DATA

UMA_CRT_HSYNC
UMA_CRT_VSYNC

CRT_IREF

12

U4D

AG18

L_BKLTEN

AG17

L_VDD_EN

AG12

L_BKLTCTL

P22

TP1

L31

TP2

L33

TP3

M38

TP4

L36

TP5

Y18

TP6

Y17

TP7

AB18

TP8

AB17

TP9

BM46

TP10

BA27

TP11

BC49

TP12

AE49

TP13

AE41

TP14

AE43

TP15

AE50

TP16

BA36

TP17

AY36

TP18

Y14

TP19

Y12

TP20

H31

TP21

J27

TP22

J25

TP23

L22

TP24

J31

TP25

L27

TP26

L25

TP27

J22

TP28

C29

TP29

F28

TP30

C26

TP31

B25

TP32

E29

TP33

E27

TP34

B27

TP35

D25

TP36

AM1

CRT_BLUE

AN2

CRT_GREEN

AN6

CRT_RED

AW3

CRT_DDC_CLK

AW1

CRT_DDC_DATA

AR4

CRT_HSYNC

AR2

CRT_VSYNC

AT3

DAC_IREF

AM6

CRT_IRTN

BD82CPDS-QMZP-B0_FCBGA942

3

SDVO_INTN
SDVO_INTP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

U9
U8

U5
W3

T3
U2

AL15
AL17

R9
R8
T1

R12
R14
M12
M11
K8
H8
M3
L5

AL12
AL14

U12
U14
N2

J3
L2
G4
G2
F5
F3
E2
E4

AL9
AL8

R6
N6
M1

B5
D5
D7
C6
C9
B7
B11
E11

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

RSVD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DDPD_AUXP

UMA_HDMI_CLK
UMA_HDMI_DATA

DDPB_AUXN
DDPB_AUXP
HDMI_HPD

UMA_HDMI_TX2­UMA_HDMI_TX2+
UMA_HDMI_TX1­UMA_HDMI_TX1+
UMA_HDMI_TX0­UMA_HDMI_TX0+
UMA_HDMI_TXC­UMA_HDMI_TXC

PCH_HDMI_CLK
PCH_HDMI_DATA

DDPC_AUXN
DDPC_AUXP
DDPC_HDP

PCH_HDMIOUT_CLK
PCH_HDMIOUT_DATA

DDPD_AUXN
DDPD_AUXP
DDPD_HDP

T199PAD
T200PAD

T201PAD
T202PAD
T203PAD

T90PAD
T92PAD
T94PAD
T96PAD
T98PAD
T100PAD
T102PAD
T104PAD

T204PAD
T205PAD

DDPC_HDP [36]

T220PAD
T221PAD

DDPD_HDP [38]

2

PCH_HDMI_CLK [36]
PCH_HDMI_DATA [ 36]

PCH_HDMI_TX2- [36]
PCH_HDMI_TX2+ [36]
PCH_HDMI_TX1- [36]
PCH_HDMI_TX1+ [36]
PCH_HDMI_TX0- [36]
PCH_HDMI_TX0+ [36]
PCH_HDMI_CLK- [36]
PCH_HDMI_CLK+ [36]

PCH_HDMIOUT_CLK [3 8]
PCH_HDMIOUT_DATA [38]

PCH_HDMIOUT_TX2- [38]
PCH_HDMIOUT_TX2+ [38]
PCH_HDMIOUT_TX1- [38]
PCH_HDMIOUT_TX1+ [38]
PCH_HDMIOUT_TX0- [38]
PCH_HDMIOUT_TX0+ [38]
PCH_HDMIOUT_CLK- [38]
PCH_HDMIOUT_CLK+ [38]

R242 100K_0402_5%

DDPC_HDP

R243 100K_0402_5%

HDMI
(To Scale)

DDPD_HDP

R1586 100K_0402_5%

HDMI OUT
(To Conn.)

UMA@

DIS@

1 2

1 2

1

12

+3VS

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_CRT/LVDS/HDMI

PCA70 LA-7521P M/B

1

0.1

of

16 64Tuesday, April 12, 2011

5

4

3

2

1

PCI PU resistor

+3VS

R253 8.2K_0402_5%

1 2

R254 8.2K_0402_5%

1 2

R255 8.2K_0402_5%

1 2

R256 8.2K_0402_5%

1 2

R259 8.2K_0402_5%

1 2

R260 8.2K_0402_5%

1 2

R261 8.2K_0402_5%

D D

C C

1 2

R262 8.2K_0402_5%

1 2

R263 8.2K_0402_5%

1 2

R264 8.2K_0402_5%

1 2

R266 8.2K_0402_5%

1 2

R267 8.2K_0402_5%

1 2

R269 8.2K_0402_5%

1 2

+3VS

R270 8.2K_0402_5%

1 2

R271 8.2K_0402_5%

1 2

R272 8.2K_0402_5%

1 2

R276 8.2K_0402_5%

1 2

R277 8.2K_0402_5%

1 2

R278 8.2K_0402_5%

1 2

R279 8.2K_0402_5%

1 2

Intel confirm GPIO19 is correct.

Boot BIOS Strap

PCH_GNT1#

0
0
1

GPIO19 Boot BIOS Loaction

0
1
0

11

B B

For CR D3E wake up reserve

A A

PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#

PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PLOCK#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCH_REQ0#

DGPU_HOLD_RST#
PCH_GPIO52
DGPU_PWR_EN

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
CR_CPPE#

LPC

Reserved

PCI
SPI

CLK_PCILOOP[14]
CLK_PCI_EC[49]

R250

@

0_0402_5%

1 2

+3VS

U4E

BF15

AD0

BF17

AD1

BT7

AD2

BT13

AD3

BG12

AD4

BN11

AD5

BJ12

AD6

BU9

AD7

BR12

AD8

BJ3

AD9

BR9

AD10

BJ10

AD11

BM8

AD12

BF3

AD13

BN2

AD14

BE4

AD15

BE6

AD16

BG15

AD17

BC6

AD18

BT11

AD19

BA14

AD20

BL2

AD21

BC4

AD22

BL4

AD23

BC2

AD24

BM13

AD25

BA9

AD26

BF9

AD27

BA8

AD28

BF8

AD29

AV17

AD30

BK12

AD31

BN4

C/BE0#

BP7

C/BE1#

BG2

*

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCH_REQ0#

Have internal PU

PAD
PAD
PAD
PAD

T123PAD

PAD
PAD

R28122_0402_5%

R28222_0402_5%

PAD

DGPU_HOLD_RST#
PCH_GPIO52
DGPU_PWR_EN

PCH_GNT0#
PCH_GNT1#
PCH_GNT2#
PCH_GNT3#

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
CR_CPPE#

PCI_PME#
PCH_PLT_RST#

CLK_PCILOOP_R

CLK_PCI_EC_R

DGPU_HOLD_RST#[22]
DGPU_PWR_EN[26,60]

T195
T196
T197
T198

CR_CPPE#[44]

T179
T180

1 2

1 2

T181

C/BE2#

BP13

C/BE3#

BK10

PIRQA#

BJ5

PIRQB#

BM15

PIRQC#

BP5

PIRQD#

BG5

REQ0#

BT5

REQ1# / GPIO50

BK8

REQ2# / GPIO52

AV11

REQ3# / GPIO54

BA15

GNT0#

AV8

GNT1# / GPIO51

BU12

GNT2# / GPIO53

BE2

GNT3# / GPIO55

BN9

PIRQE# / GPIO2

AV9

PIRQF# / GPIO3

BT15

PIRQG# / GPIO4

BR4

PIRQH# / GPIO5

AV15

PME#

BK48

PLTRST#

AT11

CLKOUT_PCI0

AN14

CLKOUT_PCI1

AT12

CLKOUT_PCI2

AT17

CLKOUT_PCI3

AT14

CLKOUT_PCI4

BD82CPDS-QMZP-B0_FCBGA942

PCI

EHCI 1

EHCI 2

USB

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

SERR#

PCIRST#

PLOCK#

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PCI_DEVSEL#

BH9

PCI_FRAME#

BC11

PCI_IRDY#

BF11

PCI_TRDY#

BC8

PCI_STOP#

BC12

PAR

BH8

PCI_PERR#

BM3

PCI_SERR#

BR6

AV14

PCI_PLOCK#

BA17

USB20_N0

BF36

USB20_P0

BD36

USB20_N1

BC33

USB20_P1

BA33

USB20_N2

BM33

USB20_P2

BM35

USB20_N3

BT33

USB20_P3

BU32

USB20_N4

BR32

USB20_P4

BT31

USB20_N5

BN29

USB20_P5

BM30
BK33
BJ33

USB port6 and port7 are disabled on H61

BF31
BD31

USB20_N8

BN27

USB20_P8

BR29

USB20_N9

BR26

USB20_P9

BT27

USB20_N10

BK25

USB20_P10

BJ25

USB20_N11

BJ31

USB20_P11

BK31
BF27
BD27

USB port12 and port13 are disabled on H61

BJ27
BK27

USBBIAS

BP25

BM25

USB_OCI

BM43

USB_OC#1

BD41

USB_OC#2

BG41

USB_OC#3

BK43

USB_OC#4

BP43

USB_OC#5

BJ41

USB_OC#6

BT45

USB_OC#7

BM45

T122PAD

USB20_N0 [ 4 6]
USB20_P0 [46]
USB20_N1 [ 4 6]
USB20_P1 [46]
USB20_N2 [ 5 0]
USB20_P2 [50]
USB20_N3 [ 5 0]
USB20_P3 [50]
USB20_N4 [ 4 0]
USB20_P4 [40]
USB20_N5 [ 4 1]
USB20_P5 [41]

USB20_N8 [ 4 1]
USB20_P8 [41]
USB20_N9 [ 4 1]
USB20_P9 [41]
USB20_N10 [4 2]
USB20_P10 [42]

T254

PAD

T255

PAD

1 2

R280 22.6_0402_1%

USB_OCI [45,46]
USB_OC#2 [40,41]
USB_OC#4 [ 41]

Reserve for USB30 PORT0@ CONN2
Reserve for USB30 PORT1@ CONN1
Touch
Int. Camera
eSATA+USB
USB PORT5 CONN6

USB PORT8 CONN4
USB PORT9 CONN3
TV Tuner #1
Reserve

USB30 PORT 0,1
USB PORT 4,5
USB PORT 8,9

Layout Note:USB_BIAS WITH
LENGTH NO MORE THAN 500
MILS TO RESISTOR.

+3VS

PCH_PLT_RST#

NC7SZ08P5X_NL_SC70-5

+3VS

NC7SZ08P5X_NL_SC70-5

USB_OCI
USB_OC#1
USB_OC#4
USB_OC#2
USB_OC#3
USB_OC#5
USB_OC#6
USB_OC#7

1

2

5

U10

2

P

B

Y

1

A

G

3

100K_0402_5%

+3VS

1

2

5

2

P

B

Y

1

A

G

U57

3

100K_0402_5%

R283 10K_0402_5%
R284 10K_0402_5%
R285 10K_0402_5%
R286 10K_0402_5%
R287 10K_0402_5%
R288 10K_0402_5%
R1011 10K_0402_5%
R1012 10K_0402_5%

C1047

0.1U_0402_16V4Z

PLT_RST#

4

R257

C1048

0.1U_0402_16V4Z

4

R1067

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PLT_RST# [5,22,45,49]

12

PLT_A_RST# [42,43,44]

12

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_PCI/USB/NAND

PCA70 LA-7521P M/B

17 64Tuesday, April 12, 2011

1

0.1

of

1 2
1 2

5

12

PCH_GPIO15
PCH_GPIO12
PCH_GPIO57

+3VALW +3VS

R296 1K_0402_5%
R303 10K_0402_5%
R298 10K_0402_5%

GPIO8

Integrated Clock Chip Enable (Removed)
H: Disable

*

D D

L: Enable

+3VALW

12

R300
10K_0402_5%

EC_SMI#

R331
1K_0402_5%

@

1 2

Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable

+3VALW

C C

R325 10K_0402_5%

In Deep Sleep Power Well. Unmuxed.
Defaults to GPI.
Not used Weak pull-up 10k

-->Check list1.5 P402.
PD to GND for Huron River!!

12

PCH_GPIO27

to VccDSW3_3

Ω

GPIO28

On-Die PLL Voltage Regulator
H: Enable

*

L: Disable

+3VALW

12

R305
1K_0402_5%

PCH_GPIO28

R330

B B

1K_0402_5%

@

1 2

1 2

R1071 10K_0402_5%

1 2

R1072 10K_0402_5%

SATA2GP/GPIO36 & SATA3GP/GPIO37Sampled at
Rising edge of PWROK.Weak internal pull-down.
(weak internal pull-down is disabled
after PLTRST# de-asserts)
NOTE: This signal should NOT be
pulled high when strap is sampled

PCH_GPIO36
PCH_GPIO37

ISDBT_DET

+3VS

A A

R320
10K_0402_5%

1 2

R326
47K_0402_5%

@

1 2

ISDBT_DET

5

4

DGPU_HPD_INT#[38]

USB30_SMI#[45]

For OPT

VGA_PWROK[60]

4

1 2

R307 10K_0402_5%

1 2

R308 10K_0402_5%

1 2

R310 10K_0402_5%

1 2

R311 10K_0402_5%

1 2

R312 10K_0402_5%

1 2

R315 10K_0402_5%

1 2

R317 10K_0402_5%

1 2

R318 10K_0402_5%

1 2

R1068 10K_0402_5%

1 2

R319 10K_0402_5%

1 2

R321 10K_0402_5%
R1030 2.2K_0402_5%

12

1 2

R1647 0_0402_5%@

1 2

R1101 0_0402_5%

EC_SCI#[49]
EC_SMI#[49]

1 2

R1065 0_0402_5%

T126PAD

ISDBT_DET[42]

@

PCH_GPIO1
USB30_SMI#_R
EC_SCI#
EC_SMI#
PCH_GPIO12
PCH_GPIO15

PCH_GPIO16

VGA_PWROK_R
PCH_GPIO22

PCH_GPIO27
PCH_GPIO28
PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
ISDBT_DET
PCH_GPIO49
PCH_GPIO57

3

PCH_GPIO0
PCH_GPIO1
USB30_SMI#_R
EC_SCI#
PCH_GPIO16
VGA_PWROK_R
PCH_GPIO22
PCH_GPIO34
PCH_GPIO38
PCH_GPIO39
PCH_GPIO49
PCH_GPIO35

U4F

AW55

BMBUSY# / GPIO0

BR19

TACH1 / GPIO1

BA22

TACH2 / GPIO6

BR16

TACH3 / GPIO7

BP51

GPIO8

BK50

LAN_PHY_PWR_CTRL / GPIO12

BM55

GPIO15

AU56

SATA4GP / GPIO16

BT17

TACH0 / GPIO17

BA53

SCLOCK / GPIO22

BP53

GPIO24 / MEM_LED

BJ43

GPIO27

BJ55

GPIO28

BL56

STP_PCI# / GPIO34

BJ57

GPIO35 / NMI#

BB55

SATA2GP / GPIO36

BG53

SATA3GP / GPIO37

BE54

SLOAD / GPIO38

BF55

SDATAOUT0 / GPIO39

AW53

SDATAOUT1 / GPIO48

BA56

SATA5GP / GPIO49

BT53

GPIO57

A4

VSS_NCTF[1]

A6

VSS_NCTF[2]

B2

VSS_NCTF[3]

BM1

VSS_NCTF[4]

BM57

VSS_NCTF[5]

BP1

VSS_NCTF[6]

BP57

VSS_NCTF[7]

BT2

VSS_NCTF[8]

BU4

VSS_NCTF[9]

BU52

VSS_NCTF[10]

BU54

VSS_NCTF[11]

BU6

VSS_NCTF[12]

D1

VSS_NCTF[13]

F1

VSS_NCTF[14]

BD82CPDS-QMZP-B0_FCBGA942

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

Project ID GPIO700GPIO71GPIO69

SKU1
SKU2
SKU3
SKU4

x

0
0
0

1
x
x
x
x
x
x
x

TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

GPIO

NCTF

2010/10/1 2011/11/01

THRMTRIP#

CPU/MISC

INIT3_3V#

NC_1

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

PWM0
PWM1
PWM2
PWM3

DF_TVS

RESERVED [29]
RESERVED [28]
RESERVED [27]
RESERVED [26]
RESERVED [25]
RESERVED [24]
RESERVED [23]
RESERVED [22]
RESERVED [21]
RESERVED [20]
RESERVED [19]
RESERVED [18]
RESERVED [17]
RESERVED [16]
RESERVED [15]
RESERVED [14]
RESERVED [13]
RESERVED [12]
RESERVED [11]
RESERVED [10]

RESERVED [9]
RESERVED [8]
RESERVED [7]
RESERVED [6]
RESERVED [5]
RESERVED [4]
RESERVED [3]
RESERVED [2]
RESERVED [1]

Compal Secret Data

0

0

1

1

1

11

BT_LED#

BU16

PCH_GPIO69

BM18

PCH_GPIO70

BN17

PCH_GPIO71

BP15

GATEA20

BB57

PCH_PECI_R

H48

KB_RST#

BG56

H_PWRGOOD

D53
E56
BN56
AY20

A54
A52
F57
D57

BN21
BT21
BM20
BN19

BC43

SST

Internal Pull Down

R47
M48

K50
K49
AB46
G56
Y44
L53
AB50
Y50
K46
L56
J55
F53
H52
E52
AB49
AB44
U49
R44
U50
U46
U44
H50
Y41
R50
M50
M49
U43
J57

Deciphered Date

NV_CLE

2

00
0
1
1 1
00
00
1
1

0
1

@

1 2

R306 0_0402_5%

2

C1613

0.1U_0402_16V4Z

1

2

1

PROJECT ID TABLE

1
0

1
0
1
00
1

+3VS +3VS +3VS

12

GPIO69_H@

R1031
10K_0402_5%

PCH_GPIO69 PCH_GPIO70 PCH_GPIO71

12

GPIO69_L@

R1032
10K_0402_5%

12

12

GPIO70_H@

R1033
10K_0402_5%

GPIO70_L@

R1034
10K_0402_5%

12

GPIO71_H@

R1035
10K_0402_5%

12

GPIO71_L@

R1036
10K_0402_5%

0
1

+3VS

BT_LED# [49]

GATEA20 [49]
H_PECI [5, 49]
KB_RST# [49]
H_PWRGOOD [5]
H_THERMTRIP# [5]

BT_LED#PCH_GPIO0
GATEA20
KB_RST#

H_PWRGOOD
GATEA20

ESD request Close to U4.BB57

DMI & FDI Termination Voltage

Set to VCC when HIGH

NV_CLE

Set to VSS when LOW

R329 1K_0402_5%

Note:Place R329 close to U1.R47
and <=100 mils

ESD request Close to U4.R47

12

NV_CLE

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

C1598 0.1U_0402_16V4Z

Compal Electronics, Inc.

PCH_CPU/GPIO

PCA70 LA-7521P M/B

1 2

R297 10K_0402_5%

1 2

R299 10K_0402_5%

1 2

R301 10K_0402_5%

1 2

C1597 0.1U_0402_16V4Z

1 2

C1596 0.1U_0402_16V4Z

+1.8VS

12

R328

2.2K_0402_5%

C243

0.1U_0402_16V4Z

@

18 64Tuesday, April 12, 2011

H_SNB_IVB# [5]

of

1

2

1

0.1

5

+1.05VS_VPCH +1.05VS_VPCH

1

1

1

C258

C254

10U_0603_6.3V6M

2

D D

C C

+VCCSATAPLL

C305

@

10U_0603_6.3V6M

B B

1

2

Near U56

+VCCAPLLEXP

C251

@

10U_0603_6.3V6M

1

2

+1.05VS_VPCH

C304

1U_0402_6.3V6K

1

2

+1.05VS_VPCH

C252

@

1U_0402_6.3V6K

1

2

1 2

R337

@

0_0805_5%

+1.05VS_VPCH

R352 0_0603_5%@

+1.05VS_VPCH
+1.05VS_VPCH

+1.05VS_VPCH
+1.05VS_VPCH

+VCCP_VCCDMI

1

2

1 2

C255

1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCCP_VCCDMI

C253
1U_0402_6.3V6K

+1.05VS_VPCH

1U_0402_6.3V6K

This pin can be left as NC if
On-Die VR is enabled (Default)

L6 10UH_LB2012T100MR_20%@

1 2

L1 1UH_LB2012T1R0M_20%@
R342 0_0603_5%@
R348 0_0603_5%@

1 2

L3 10UH_LB2012T100MR_20%@

1

C256

1U_0402_6.3V6K

2

2

Note:+VCCP_VCCDMI trace need to be at
least 20 mils width with full VSS/VCC
reference plane)

1

C250

2

12

12

12

Near B53

+VCCAPLL_CPY_PCH

C275

@

A A

10U_0603_6.3V6M

C276

@

1U_0402_6.3V6K

1

1

2

2

Near A19

5

1

C257

1U_0402_6.3V6K

2

1

C306
1U_0402_6.3V6K

2

+VCCSATAPLL
+VCCDPLL_CPY
+VCCAPLLEXP
+1.05VS_VCCAPLL_FDI

C263 1U_0402_6.3V6K@

1 2

+VCCACLK
+VCCAPLL_CPY_PCH

C297

4

4

1U_0402_6.3V6K

1

Near Y20

2

U4G

F20

VCCIO_24

F30

VCCIO_25

V25

VCCIO_26

V27

VCCIO_27

V31

VCCIO_28

V33

VCCIO_29

Y24

VCCIO_30

Y26

VCCIO_31

Y30

VCCIO_32

Y32

VCCIO_33

Y34

VCCIO_34

AA34

VCCIO_22

AA36

VCCIO_23

V22

VCCIO_35

Y20

VCCIO_36

Y22

VCCIO_37

B41

VCCDMI_2

E41

VCCDMI_1

AL40

VCCIO_8

AN40

VCCIO_9

AN41

VCCIO_10

AG38

VCCIO_20

AG40

VCCIO_21

AG41

VCCIO_7

U56

VCCAPLLSATA

BA38

B53
C54

AL5
A19

PLL

VCCIO_19
VCCAPLLEXP
VCCAFDIPLL

VCCACLK
VCCAPLLDMI2

BD82CPDS-QMZP-B0_FCBGA942

3

POWER

1

C245

2

1U_0402_6.3V6K

C282

1U_0402_6.3V6K

1

2

Deciphered Date

1U_0402_6.3V6K

1

C246

C247

2

1U_0402_6.3V6K

C281

10U_0805_10V4Z

1

2

R367 0_0603_5%@

1 2

+1.05VS_VPCH

C308

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1 2

R353

@

0_0805_5%

+1.05VS_VPCH

1

2

Near AC20

C303

VCCASW_4
VCCASW_5
VCCASW_6
VCCASW_7
VCCASW_8
VCCASW_9

VCCASW_3
VCCASW_2
VCCASW_1

VCCIO_18

VCCSSC_1
VCCSSC_2

VCCIO_1
VCCIO_2
VCCIO_3

VCCIO_4
VCCIO_13
VCCIO_12
VCCIO_11
VCCIO_14

AC24
AC26
AC28
AC30
AC32
AE24
AE28
AE30
AE32
AE34
AE36
AG32
AG34
AJ32
AJ34
AJ36
AL32
AL34
AN32
AN34
AR32
AR34

AG24
AG26
AG28
AJ24
AJ26
AJ28
AL24
AL28
AN22
AN24
AN26
AN28
AR24
AR26
AR28
AR30
AR36
AR38
AU30
AU36

AU34
AV36
AU32

AE15
AE17
AG15
AJ20
AE40

AC20
AE20

AV24
AV26
AY25
AY27

V36
Y36
AJ38
Y28

C244
10U_0603_6.3V6M

+1.05VS_VCCASW

C284

+1.05VS_VCCDIFFCLKN

+1.05VS_VPCH

@

C259

10U_0603_6.3V6M

2010/10/1 2011/11/01

3

C283

1U_0402_6.3V6K

1

2

1

C299
1U_0402_6.3V6K

2

+1.05VS_VPCH

1

2

Near AJ20

1

2

1U_0402_6.3V6K

1

2

+1.05VS_SSCVCC

+1.05VS_VPCH

1

C260
1U_0402_6.3V6K

2

Compal Secret Data

VCCCORE_1
VCCCORE_2
VCCCORE_3
VCCCORE_4
VCCCORE_5
VCCCORE_6
VCCCORE_7
VCCCORE_8

VCCCORE_9
VCCCORE_10
VCCCORE_11
VCCCORE_12
VCCCORE_13
VCCCORE_14
VCCCORE_15
VCCCORE_16
VCCCORE_17
VCCCORE_18
VCCCORE_19
VCCCORE_20
VCCCORE_21
VCCCORE_22

VCCASW_10

VCCASW_11

VCCASW_12

VCCASW_13

VCCASW_14

VCCASW_15

VCCASW_16

VCCASW_17

VCCASW_18

VCCASW_19

VCCASW_20

VCCASW_21

VCCASW_22

VCCASW_23

VCCDIFFCLKN_1
VCCDIFFCLKN_2
VCCDIFFCLKN_3

VCCCLKDMI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2

+1.05VS_VPCH

+1.05VS_VPCH

1 2

1

R368

@

C307

1U_0402_6.3V6K

0_0603_5%

2

+1.05VS_VCCDIFFCLKN

1

C302

1U_0402_6.3V6K

Near AE15

2

2

1

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_SUS

VCC3_3

VCCADAC

VCCADPLLA

VCCADPLLB

VCCCORE

VCCDMI

VCCVRM 1.5

VCCSSC 1.05

VCCDIFFCLKN 1.05

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_POWER-1

PCA70 LA-7521P M/B

Voltage

1.05

5

5

3.3

3.3

1.05

1.05

1.05

1.05

1.05VCCIO

1.05VCCASW

3.3VCCSPI

3.3VCCDSW

1.8VCCDFTERM

3.3VCCRTC

3.3VCCSUS3_3

3.3 / 1.5VCCSusHDA

1.05VCCCLKDMI

1

S0 Iccmax
Current (A)

1mA

1mA

1mA

409mA

68mA

100mA

100mA

1600mA

57mA

4070mA

1610mA

20mA
3mA

200mA

6 uA

97mA

10mA

159mA

20mA

105mA

55mA

of

19 64Tuesday, April 12, 2011

0.1

5

4

3

2

1

POWER

VCCSUS3_3_11

VCCSUS3_3_10

V_PROC_IO_NCTF

DCPRTC_NCTF

VCCVRM_1
VCCVRM_4
VCCVRM_3
VCCVRM_2

VCCPNAND_01
VCCPNAND_02

VCC3_3_5
VCC3_3_6

USB

VCC3_3_2
VCC3_3_3
VCC3_3_4

VCC3_3_8
VCC3_3_1

VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS3_3_7
VCCSUS3_3_8

VCCSUS3_3_9

VCCSUS3_3_1

VCCDSW3_3

V_PROC_IO

DCPSUS_3
DCPSUS_1

VCCRTC
DCPRTC

DCPSUS_2

DCPSUSBYP

DCPSST

AJ1
R2
R54
R56

T55
T57

AL38
AN38

BC17
BD17
BD20

A12
AF57

BT35
AV30

AV32
AY31
AY33
BJ36
BK36
BM36

AT40
AU38

U31
AV40
D55

B56
A39

AA32
BU42
BR54

BT56
AT41

AV41
BA46

+VCCDSW

+V_CPU_IO
+VCCSUS

+RTCVCC
+VCCRTCEXT
+VCCSUS
+VCCDCPSUS
+VCCSST

Near BA46

0.1U_0402_10V7K

+VCCAFDI_VRM

Near T55

1 2

C285

0.1U_0402_10V7K

1

C296

0.1U_0402_10V7K

2

1

C278

0.1U_0402_10V7K

2

Near AV30 Near U31N ear BT35

C272 0.1U_0402_10V7K

C280 0.1U_0402_10V7K

+RTCVCC

C300

0.1U_0402_10V7K

C309

C262

0.1U_0402_10V7K

1

2

Near BD17Near BC17

1

C298

0.1U_0402_10V7K

2

Near A12

1

C288

2.2U_0603_10V6K

2

1 2

1 2

Near A39
Near BR54

1 2

1

1

2

2

R335

0_0603_5%

1 2

C286

0.1U_0402_10V7K

1

1

2

2

+3VS

1

2

Near AV40

C274

0.1U_0402_10V7K

@

0.1U_0402_10V7K

C279

0.1U_0402_10V7K

C290

+1.8VS

+1.8VS

+3VS

Near Al38

R350 0_0603_5%@

Connect VCCVRM to

--> 1.8V for DT

--> 1.5V for Mobile

+3VALW

1

1

C291

C289

1U_0402_6.3V6K

0.1U_0402_10V7K

2

2

1 2

C314

C313

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

2

2

C315

1U_0402_6.3V6K

C312

4.7U_0603_6.3V6K

1

2

+3VALW

1 2

@

1

0_0603_5%

2

@

1 2

0_0603_5%

+1.05VS_VPCH

R371

+1.05VS_VPCH

R373

B520 not connect?

BT25
AV28
AU20

AV20
AU22

AN52

BF1

U4J

V5REF
V5REF_SUS
VCCSUSHDA
VCC3_3_9

VCC3_3_10
VCC3_3_7

VCCSPI

+3VS_VCCSPI

1

2

+PCH_V5REF_RUN
+PCH_V5REF_SUS
+VCCSUSHDA

Near AU20

1

C287
1U_0402_6.3V6K

2

R374

@

0_0603_5%

D6
RB751V40_SC76-2

1 2

+3VALW

D5
RB751V40_SC76-2

1 2

1 2

0.1U_0402_16V4Z

1

C318

+3VALW

2

+PCH_V5REF_RUN

+PCH_V5REF_SUS

+3VS

R3430_0805_5%

12
12

R3440_0805_5% @

C264

1U_0402_6.3V6K

+3VS

D D

Intel suggest
100ohm+1uF

Near BF1

C C

+3VALW

PLACE REF5V CIRCUITRY NEAR PCH

C277
1U_0402_6.3V6K

PLACE REF5V CIRCUITRY NEAR PCH

C271
1U_0402_6.3V6K

R351
100_0402_5%

12

R1069
100_0402_5%

12

+5VS +3VS

12

+5VALW

12

Near BT25

B B

12

1

+

@

2

Layout Note:
Close to AT1< 100 mil

1

C249
1U_0402_6.3V6K

2

+VCCA_DAC
+1.05VS_VCCADPLLA
+1.05VS_VCCADPLLB

AT1
AB1
AC2

VCCADAC
VCCADPLLA
VCCADPLLB

+3VS

R332

1_0603_5%

C248

220U_6.3V_M

BD82CPDS-QMZP-B0_FCBGA942

+1.05VS_VPCH

A A

Layout Note:
Close to AB 1 , AC2< 100 mil
Filter no need if int. GFx diisabled

L6,L7 (10uH inductor, 120mA)

L4

10UH_LB2012T100MR_20%

1 2

L5

1 2

10UH_LB2012T100MR_20%

220U_B2_2.5VM_R15

C292

5

1

+

C294
1U_0402_6.3V6K

2

+1.05VS_VCCADPLLA

+1.05VS_VCCADPLLB

1

2

1

+

C293

2

220U_B2_2.5VM_R15

R360

@

0_0603_5%

1 2

1

C295
1U_0402_6.3V6K

2

0.1U_0402_10V7K

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

+RTCVCC

1

C317

2

Near BU42

Compal Secret Data

+RTCVCC

1

1U_0402_6.3V6K

2

Deciphered Date

C316

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_POWER-2

PCA70 LA-7521P M/B

1

20 64Tuesday, April 12, 2011

0.1

of

5

4

3

2

1

U4H

AE56

VSS[0]

BR36

VSS[1]

C12

VSS[2]

AY22

VSS[3]

A26

VSS[4]

A29

VSS[5]

A42

VSS[6]

A49

VSS[7]

A9

VSS[8]

AA20

VSS[9]

D D

C C

B B

A A

AA22

VSS[10]

AA24

VSS[11]

AA26

VSS[12]

AA28

VSS[13]

AA30

VSS[14]

AA38

VSS[15]

AB11

VSS[16]

AB15

VSS[17]

AB40

VSS[18]

AB41

VSS[19]

AB43

VSS[20]

AB47

VSS[21]

AB52

VSS[22]

AB57

VSS[23]

AB6

VSS[24]

AC22

VSS[25]

AC34

VSS[26]

AC36

VSS[27]

AC38

VSS[28]

AC4

VSS[29]

AC54

VSS[30]

AE14

VSS[31]

AE18

VSS[32]

AE22

VSS[33]

AE26

VSS[34]

AE38

VSS[35]

AE4

VSS[36]

AE47

VSS[37]

AE8

VSS[38]

AE9

VSS[39]

AF52

VSS[40]

AF6

VSS[41]

AG11

VSS[42]

AG14

VSS[43]

AG20

VSS[44]

AG22

VSS[45]

AG30

VSS[46]

AG36

VSS[47]

AG43

VSS[48]

AG44

VSS[49]

AG46

VSS[50]

AG5

VSS[51]

AG50

VSS[52]

AG53

VSS[53]

AH52

VSS[54]

AH6

VSS[55]

AJ22

VSS[56]

AJ30

VSS[57]

AJ57

VSS[58]

AK52

VSS[59]

AK6

VSS[60]

AL11

VSS[61]

AL18

VSS[62]

AL20

VSS[63]

AL22

VSS[64]

AL26

VSS[65]

AL30

VSS[66]

AL36

VSS[67]

AL41

VSS[68]

AL46

VSS[69]

AL47

VSS[70]

AM3

VSS[71]

AM52

VSS[72]

AM57

VSS[73]

AN11

VSS[74]

AN12

VSS[75]

AN15

VSS[76]

AN17

VSS[77]

AN18

VSS[78]

AN20

VSS[79]

BD82CPDS-QMZP-B0_FCBGA942

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AN30
AN36
AN4
AN43
AN47
AN54
AN9
AR20
AR22
AR52
AR6
AT15
AT18
AT43
AT47
AT52
AT6
AT8
AU24
AU26
AU28
AU5
AV12
AV18
AV22
AV34
AV38
AV47
AV6
AW57
AY38
AY6
B23
BA11
BA12
BA31
BA41
BA44
BA49
BB1
BB3
BB52
BB6
BC14
BC15
BC20
BC27
BC31
BC36
BC38
BC47
BC9
BD25
BD33
BF12
BF20
BF25
BF33
BF41
BF43
BF46
BF52
BF6
BG22
BG25
BG27
BG31
BG33
BG36
BG38
BH52
BH6
BJ1
BJ15
BK20
BK41
BK52
BK6
BM10

U4I

BM12

VSS[159]

BM16

VSS[160]

BM22

VSS[161]

BM23

VSS[162]

BM26

VSS[163]

BM28

VSS[164]

BM32

VSS[165]

BM40

VSS[166]

BM42

VSS[167]

BM48

VSS[168]

BM5

VSS[169]

BN31

VSS[170]

BN47

VSS[171]

BN6

VSS[172]

BP3

VSS[173]

BP33

VSS[174]

BP35

VSS[175]

BR22

VSS[176]

BR52

VSS[177]

BU19

VSS[178]

BU26

VSS[179]

BU29

VSS[180]

BU36

VSS[181]

BU39

VSS[182]

C19

VSS[183]

C32

VSS[184]

C39

VSS[185]

C4

VSS[186]

D15

VSS[187]

D23

VSS[188]

D3

VSS[189]

D35

VSS[190]

D43

VSS[191]

D45

VSS[192]

E19

VSS[193]

E39

VSS[194]

E54

VSS[195]

E6

VSS[196]

E9

VSS[197]

F10

VSS[198]

F12

VSS[199]

F16

VSS[200]

F22

VSS[201]

F26

VSS[202]

F32

VSS[203]

F33

VSS[204]

F35

VSS[205]

F36

VSS[206]

F40

VSS[207]

F42

VSS[208]

F46

VSS[209]

F48

VSS[210]

F50

VSS[211]

F8

VSS[212]

G54

VSS[213]

H15

VSS[214]

H20

VSS[215]

H22

VSS[216]

H25

VSS[217]

H27

VSS[218]

H33

VSS[219]

H6

VSS[220]

J1

VSS[221]

J33

VSS[222]

J46

VSS[223]

J48

VSS[224]

J5

VSS[225]

J53

VSS[226]

K52

VSS[227]

K6

VSS[228]

K9

VSS[229]

L12

VSS[230]

L17

VSS[231]

L38

VSS[232]

L41

VSS[233]

L43

VSS[234]

M20

VSS[235]

M22

VSS[236]

M25

VSS[237]

M27

VSS[238]

M31

VSS[239]

M33

VSS[240]

M36

VSS[241]

M46

VSS[242]

M52

VSS[243]

M57

VSS[244]

M6

VSS[245]

M8

VSS[246]

M9

VSS[247]

N4

VSS[248]

N54

VSS[249]

R11

VSS[250]

R15

VSS[251]

R17

VSS[252]

R22

VSS[253]

R4

VSS[254]

R41

VSS[255]

R43

VSS[256]

R46

VSS[257]

R49

VSS[258]

BD82CPDS-QMZP-B0_FCBGA942

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]

VSSADAC

T52
T6
U11
U15
U17
U20
U22
U25
U27
U33
U36
U38
U41
U47
U53
V20
V38
V6
W1
W55
W57
Y11
Y15
Y38
Y40
Y43
Y46
Y47
Y49
Y52
Y6
AL43
AL44
R36
P36
R25
P25

AU2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_GND

PCA70 LA-7521P M/B

21 64Tuesday, April 12, 2011

1

0.1

of

5

PCIE_CTX_C_GRX_P[0..15][6]

PCIE_CTX_C_GRX_N[0..15][6]

PCIE_GTX_C_CRX_P[0..15][6]

D D

C C

B B

A A

PLT_RST#[5,17,45,49]
DGPU_HOLD_RST#[17]

PCIE_GTX_C_CRX_N[0..15][6]

NC7SZ08P5X_NL_SC70-5

5

+1.05VGS

XTALIN XTAL_OUT

27MHZ_16PF_X5H027000FG1H

1

C1120
18P_0402_50V8J

DIS@

2

+3VS

5

2

P

B

1

A

G

3

DIS@

PCIE_CTX_C_GRX_P[0..15]

PCIE_CTX_C_GRX_N[0..15]

PCIE_GTX_C_CRX_P[0..15]

PCIE_GTX_C_CRX_N[0..15]

PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10

PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15

L69
BLM18PG330SN1D_0603

DIS@

1 2

C1121

DIS@

18P_0402_50V8J

R1625

100_0402_1%

1 2

DIS@

R1626
100K_0402_5%

DIS@

2

1

2

C1107
10U_0603_6.3V6M

DIS@

1

@

1 2

R1130 10M_0402_5%

Y8

1 2

DIS@

U95

4

Y

12

DIS@

10U_0603_6.3V6M

C1108

DIS@

1

2

1

2

PLTRST_VGA#

4

C1105 0.1U_0402_10V7KDIS@

1 2

C1106 0.1U_0402_10V7KDIS@

1 2

C1103 0.1U_0402_10V7KDIS@

1 2

C1104 0.1U_0402_10V7KDIS@

1 2

C1101 0.1U_0402_10V7KDIS@

1 2

C1102 0.1U_0402_10V7KDIS@

1 2

C1099 0.1U_0402_10V7KDIS@

1 2

C1100 0.1U_0402_10V7KDIS@

1 2

C1097 0.1U_0402_10V7KDIS@

1 2

C1098 0.1U_0402_10V7KDIS@

1 2

C1095 0.1U_0402_10V7KDIS@

1 2

C1096 0.1U_0402_10V7KDIS@

1 2

C1093 0.1U_0402_10V7KDIS@

1 2

C1094 0.1U_0402_10V7KDIS@

1 2

C1091 0.1U_0402_10V7KDIS@

1 2

C1092 0.1U_0402_10V7KDIS@

1 2

C1089 0.1U_0402_10V7KDIS@

1 2

C1090 0.1U_0402_10V7KDIS@

1 2

C1087 0.1U_0402_10V7KDIS@

1 2

C1088 0.1U_0402_10V7KDIS@

1 2

C1085 0.1U_0402_10V7KDIS@

1 2

C1086 0.1U_0402_10V7KDIS@

1 2

C1083 0.1U_0402_10V7KDIS@

1 2

C1084 0.1U_0402_10V7KDIS@

1 2

C1081 0.1U_0402_10V7KDIS@

1 2

C1082 0.1U_0402_10V7KDIS@

1 2

C1079 0.1U_0402_10V7KDIS@

1 2

C1080 0.1U_0402_10V7KDIS@

1 2

C1077 0.1U_0402_10V7KDIS@

1 2

C1078 0.1U_0402_10V7KDIS@

1 2

C1075 0.1U_0402_10V7KDIS@

1 2

C1076 0.1U_0402_10V7KDIS@

1 2

PCI-Express Gen2 x16 Interface

CLK_PCIE_VGA[14]

0.1U_0402_16V4Z
C1109

+3VGS

LVDS

CRT

CRT

4

1

2

200_0402_1%

0.1U_0402_16V4Z
C1110

DIS@

CLK_PCIE_VGA#[14]

+3VGS

R1110

DIS@

0.1U_0402_16V4Z
C1111

DIS@

1

1

2

2

SMB_CLK_GPU[23]

SMB_DATA_GPU[23]

(Reserve for debug)

R1109 100K_0402_5%DIS@

1 2

150mA

0.1U_0402_16V4Z
C1112

DIS@

1 2
1 2

1 2
1 2

1 2
1 2

1 2

PLTRST_VGA#

R1117
10K_0402_5%

DIS@

R1116
10K_0402_5%

DIS@

12
12

1 2

R1113

2.49K_0402_1%

DIS@

3

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15

PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P11PCIE_GTX_C_CRX_P11
PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15

CLK_REQ_GPU#

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

+PLLVDD

XTALIN
XTAL_OUT

XTALOUT

12

XTALSSIN

12

VGA_EDID_CLK

R11192.2K_0402_5% DIS@

VGA_EDID_DATA

R11202.2K_0402_5% DIS@

I2CB_SCL

R11222.2K_0402_5% DIS@

I2CB_SDA

R11232.2K_0402_5% DIS@

VGA_CRT_CLK

R11242.2K_0402_5% DIS@

VGA_CRT_DATA

R11252.2K_0402_5% DIS@

HDCP_SCL

R11262.2K_0402_5% DIS@

HDCP_SDA

R11282.2K_0402_5% DIS@

Security Cla ssification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

U58A

AP17

PEX_RX0

AN17

PEX_RX0_N

AN19

PEX_RX1

AP19

PEX_RX1_N

AR19

PEX_RX2

AR20

PEX_RX2_N

AP20

PEX_RX3

AN20

PEX_RX3_N

AN22

PEX_RX4

AP22

PEX_RX4_N

AR22

PEX_RX5

AR23

PEX_RX5_N

AP23

PEX_RX6

AN23

PEX_RX6_N

AN25

PEX_RX7

AP25

PEX_RX7_N

AR25

PEX_RX8

AR26

PEX_RX8_N

AP26

PEX_RX9

AN26

PEX_RX9_N

AN28

PEX_RX10

AP28

PEX_RX10_N

AR28

PEX_RX11

AR29

PEX_RX11_N

AP29

PEX_RX12

AN29

PEX_RX12_N

AN31

PEX_RX13

AP31

PEX_RX13_N

AR31

PEX_RX14

AR32

PEX_RX14_N

AR34

PEX_RX15

AP34

PEX_RX15_N

AL17

PEX_TX0

AM17

PEX_TX0_N

AM18

PEX_TX1

AM19

PEX_TX1_N

AL19

PEX_TX2

AK19

PEX_TX2_N

AL20

PEX_TX3

AM20

PEX_TX3_N

AM21

PEX_TX4

AM22

PEX_TX4_N

AL22

PEX_TX5

AK22

PEX_TX5_N

AL23

PEX_TX6

AM23

PEX_TX6_N

AM24

PEX_TX7

AM25

PEX_TX7_N

AL25

PEX_TX8

AK25

PEX_TX8_N

AL26

PEX_TX9

AM26

PEX_TX9_N

AM27

PEX_TX10

AM28

PEX_TX10_N

AL28

PEX_TX11

AK28

PEX_TX11_N

AK29

PEX_TX12

AL29

PEX_TX12_N

AM29

PEX_TX13

AM30

PEX_TX13_N

AM31

PEX_TX14

AM32

PEX_TX14_N

AN32

PEX_TX15

AP32

PEX_TX15_N

AR16

PEX_REFCLK

AR17

PEX_REFCLK_N

AR13

PEX_CLKREQ_N

AJ17

PEX_TSTCLK_OUT

AJ18

PEX_TSTCLK_OUT_N

AM16

PEX_RST_N

AG21

PEX_TERMP

60mA

AE9

PLLVDD

45mA

AF9

SP_PLLVDD

45mA

AD9

VID_PLLVDD

B1

XTAL_IN

B2

XTAL_OUT

D1

XTAL_OUTBUFF

D2

XTAL_SSIN

E2

I2CS_SCL

E1

I2CS_SDA

E3

I2CC_SCL

E4

I2CC_SDA

G3

I2CB_SCL

G2

I2CB_SDA

G1

I2CA_SCL

G4

I2CA_SDA

F6

I2CH_SCL

G6

I2CH_SDA

N12P-GS-A1_BGA_973P GS@

2009/01/01 2010/01/01

3

Part 1 of 7

GPIO

DVO

PCI EXPRESS

MIOA_HSYNC_NC
MIOA_VSYNC_NC

MIOB_HSYNC_NC
MIOB_VSYNC_NC

MIOA_CLKIN_NC

MIOA_CLKOUT_NC

MIOB_CLKIN_NC

MIOB_CLKOUT_NC

MIOA_CLKOUT_NC_N
MIOB_CLKOUT_NC_N

MIOACAL_PD_VDDQ_NC

MIOACAL_PU_GND_NC

MIOBCAL_PD_VDDQ_NC

MIOBCAL_PU_GND_NC

CLK

DACs

I2C

Compal Secret Data

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24

MIOA_D0_NC
MIOA_D1_NC
MIOA_D2_NC
MIOA_D3_NC
MIOA_D4_NC
MIOA_D5_NC
MIOA_D6_NC
MIOA_D7_NC
MIOA_D8_NC

MIOA_D9_NC
MIOA_D10_NC
MIOA_D11_NC
MIOA_D12_NC
MIOA_D13_NC
MIOA_D14_NC

MIOB_D0_NC

MIOB_D1_NC

MIOB_D2_NC

MIOB_D3_NC

MIOB_D4_NC

MIOB_D5_NC

MIOB_D6_NC

MIOB_D7_NC

MIOB_D8_NC

MIOB_D9_NC
MIOBD_10_NC
MIOB_D11_NC
MIOB_D12_NC
MIOB_D13_NC
MIOB_D14_NC

MIOA_DE_NC

MIOA_CTL3_NC

MIOA_VREF_NC

MIOB_DE_NC

MIOB_CTL3_NC

MIOB_VREF_NC

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

DACA_VDD
DACA_VREF
DACA_RSET

DACB_RED

DACB_GREEN

DACB_BLUE

DACB_HSYNC

DACB_VSYNC

DACB_VDD
DACB_VREF
DACB_RSET

Deciphered Date

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
M7

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

N3
L3

W1
W2

N2
P5
N5

Y5
W3
AF1

N4
R4

AE1
V4

T4
W4

U5
T5

AA7
AA6

AM15
AM14
AL14

AM13
AL13

AJ12
AK12
AK13

AK4
AL4
AJ4

AM1
AM2

AG7
AK6
AH7

2

VGA_SHDMI_HPD
VGA_LCD_PWM
VGA_ENVDD
VGA_BKOFF#_R

GPU_VID0
GPU_VID1

OVERTEMP ALERT

AC DETECT

1 2

R1111 10K_0402_5%DIS@

1 2

R1112 10K_0402_5%DIS@

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_CRT_HSYNC
VGA_CRT_VSYNC

+DACA_VDD
+DACA_VREF
DACA_RSET

+DACB_VDD

2

R1520 100K_0402_5%

R1108 10K_0402_5%

120mA

12

DIS@

R1127
10K_0402_5%

DIS@

VGA_SHDMI_HPD [36 ]
VGA_LCD_PWM [35]
VGA_ENVDD [3 5 ]
VGA_BKOFF#_R [49]

GPU_VID0 [60]
GPU_VID1 [60]

1 2

THERM#_VGA_R [ 23]

1 2

VGA_HDMIOUT_HPD [38]

R1114
150_0402_1%

DIS@

1 2
1 2
1 2

R1118

T214

150_0402_1%

T215

DIS@

124_0402_1%

0.1U_0402_16V4Z

R1121

1

C1118

DIS@

1

2

2

12

Date: Sheet

1

R1517 100K_0402_5%DIS@
R1518 100K_0402_5%DIS@
R1519 100K_0402_5%DIS@
R1650 10K_0402_5%DIS@
R1651 10K_0402_5%DIS@
R1652 10K_0402_5%DIS@

1 2
1 2
1 2
1 2
1 2
1 2

DIS@

DIS@

+3VGS

+3VGS

VGA_SHDMI_HPD
GPU_VID0
GPU_VID1
VGA_LCD_PWM
VGA_ENVDD
VGA_BKOFF#_R

GPIO Description

I/OGPIO USAGE

ACTIVE

GPIO0

IN

GPIO1

IN

GPIO2

OUT

GPIO3

OUT

OUT

GPIO4

OUT

GPIO5

OUT

GPIO6

OUT

GPIO7

IN/OUT

GPIO8

OUT

GPIO9

OUT

GPIO10

OUT

GPIO11

IN

GPIO12

OUT

GPIO13

OUT

GPIO14

IN

GPIO15

IN

GPIO16

IN

GPIO17

IN

GPIO18

IN

GPIO19

IN

GPIO20

IN

GPIO21

IN

GPIO22

IN

GPIO23

IN

GPIO24

R1115
150_0402_1%

DIS@

0.1U_0402_16V4Z
C1114

DIS@

1

2

Title

Size Doc ument N u mber Re v

Close to GPU
(Reserve for debug)

L70
MMZ1608D301BT_0603

DIS@

1U_0402_6.3V6K

0.1U_0402_16V4Z
C1119

DIS@

C1115

DIS@

DIS@

1

1

2

2

Compal Electronics, Inc.

VGA_PCIE/DAC/GPIO

PCA70 LA-7521P M/B

N/A

N/A

HIGH

HIGH

HIGH

HIGH

HIGH

HIGH

LOW

LOW

HIGH

HIGH

N/A

LOW

HIGH

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

1 2

4.7U_0603_6.3V6K
C1116

1

IFPAB HOTPLUG DETECT

IFPC HOTPLUG DETECT

PANEL BACKLIGHT PWM

PANEL POWER ENABLE

PANEL BACKLIGHT ENABLE

NVVDD ALTV0

NVVDD ALTV1

FBVDDQ ALTV

OVERTEMP ALERT

THERMAL ALERT

FB_VREF CONTROL

RESERVED

AC DETECT

LOAD STEP DOWN

LOAD STEP UP

IFPE HOTPLUG DETECT

FAN PWM OUT

FAN TACH IN

RESERVED

IFPD HOTPLUG DETECT

RESERVED

IFPF HOTPLUG DETECT

RESERVED

RESERVED

RESERVED

+3VGS

4.7U_0603_6.3V6K
C1117

DIS@

1

2

of

22 64Tuesday, April 12, 2011

0.1

5

Display Interface Support

LinkA

LinkB

D D

LinkC

LinkD

LinkE

LinkF

C C

B B

A A

LVDS(Single Link or Dual Link
with IFPB)

LVDS(Dual Link with IFPA)

Display Port/HDMI

Display Port/eDP
Display Port/DVI(Single Link

or Dual Link with IFPF))/HDMI
Display Port/DVI(Dual Link with IFPE)

To HDMI OUT

+3VGS

VGA_SHDMI_ECLK[36]

VGA_SHDMI_EDATA[36]

+3VGS

To HDMI OUT

VGA_HDMI_ECLK[38]

VGA_HDMI_EDATA[38]

VGA_SHDMI_ETXD2+[36]

VGA_SHDMI_ETXD2-[36]

VGA_SHDMI_ETXD1+[36]

VGA_SHDMI_ETXD1-[36]

VGA_SHDMI_ETXD0+[36]

VGA_SHDMI_ETXD0-[36]

VGA_SHDMI_ETXC+[36]

VGA_SHDMI_ETXC-[36]

VGA_HDMI_ETXD2+[38]

VGA_HDMI_ETXD2-[38]

VGA_HDMI_ETXD1+[38]

VGA_HDMI_ETXD1-[38]

VGA_HDMI_ETXD0+[38]

VGA_HDMI_ETXD0-[38]

VGA_HDMI_ETXC+[38]

VGA_HDMI_ETXC-[38]

R1578 2.2K_0402_5% DIS@

1 2

R1579 2.2K_0402_5% DIS@

1 2

R1138 2.2K_0402_5% DIS@

1 2

R1139 2.2K_0402_5% DIS@

1 2

+3VGS

R1144
10K_0402_5%

DIS@

1 2

STRAP0[33]
STRAP1[33]
STRAP2[33]

4

U58D

AM11

IFPA_TXC

AM12

IFPA_TXC_N

AM8

IFPA_TXD0

AL8

IFPA_TXD0_N

AM10

IFPA_TXD1

AM9

IFPA_TXD1_N

AK10

IFPA_TXD2

AL10

IFPA_TXD2_N

AK11

IFPA_TXD3

AL11

IFPA_TXD3_N

AP13

IFPB_TXC

AN13

IFPB_TXC_N

AN8

IFPB_TXD4

AP8

IFPB_TXD4_N

AP10

IFPB_TXD5

AN10

IFPB_TXD5_N

AR11

IFPB_TXD6

AR10

IFPB_TXD6_N

AN11

IFPB_TXD7

AP11

IFPB_TXD7_N

AM7

IFPC_L0

AM6

IFPC_L0_N

AL5

IFPC_L1

AM5

IFPC_L1_N

AM3

IFPC_L2

AM4

IFPC_L2_N

AP1

IFPC_L3

AR2

IFPC_L3_N

AR8

IFPD_L0

AR7

IFPD_L0_N

AP7

IFPD_L1

AN7

IFPD_L1_N

AN5

IFPD_L2

AP5

IFPD_L2_N

AR5

IFPD_L3

AR4

IFPD_L3_N

AH6

IFPE_L0

AH5

IFPE_L0_N

AH4

IFPE_L1

AG4

IFPE_L1_N

AF4

IFPE_L2

AF5

IFPE_L2_N

AE6

IFPE_L3

AE5

IFPE_L3_N

AL2

IFPF_L0

AL3

IFPF_L0_N

AJ3

IFPF_L1

AJ2

IFPF_L1_N

AJ1

IFPF_L2

AH1

IFPF_L2_N

AH2

IFPF_L3

AH3

IFPF_L3_N

AP2

IFPC_AUX_I2CW_SCL

AN3

IFPC_AUX_I2CW_SDA_N

AP4

IFPD_AUX_I2CX_SCL

AN4

IFPD_AUX_I2CX_SDA_N

AE4

IFPE_AUX_I2CY_SCL

AD4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

A4

BUFRST_N

AB5

CEC

W5

STRAP0

W7

STRAP1

V7

STRAP2

N12P-GS-A1_BGA_973P GS@

Part 4 of 7

Channel A Channel B

NC

VDD_SENSE_0

LVDS/TMDS

VDD_SENSE_1
VDD_SENSE_2

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

TEST

TESTMODE

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SCLK

GENERAL

NC/SPDIF_NC
MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GND

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

ROM_SO

THERMDP
THERMDN

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29

ROM_SI

3

For GB2-128 & GB2b-128 colayout....

A2
A7
B7
C5

STRAP4

C7
D5
D6

STRAP3

D7
E5

VPGOOD

E7
F4
G5
H32
J25
J26

STRAP_REF2

P6
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AF6
AG6
AG20
AJ5
AK15
AL7

D35
P7
AD20

AD19
E35
R7

TESTMODE

AP35
AP14
AN14
AN16
AR14
AP16

R1141 10K_0402_5%

ROM_CS#

C3

ROM_SI

D3

ROM_SO

C4

ROM_SCLK

D4

if unuse this pin , pull down 36k

R1627 36K_0402_1%DIS@

A5

R1143 40.2K_0402_1%DIS@

N9

R1145 40.2K_0402_1%DIS@

M9

THERM_D+

B5

THERM_D-

B4

1 2

R1643 10K_0402_5%

1 2

R1646 40.2K_0402_1%

1 2

DIS@

12
1 2
1 2

STRAP4 [33]

STRAP3 [33]

GV@

GV@

VGA_SENSE [60]

GND_SENSE [60]

T216
T217
T218
T219

ROM_SI [33]
ROM_SO [33]
ROM_SCLK [33]

External VGA Thermal Sensor

Address: 0x9A H

THERM_D+

THERM_D-

12

R1140
10K_0402_5%

DIS@

C1122 0.1U_0402_16V4Z@

C1123
2200P_0402_50V7K

12

1 2

@

2

+3VGS

U60

1

VDD
D+

SDATA

ALERT#

D­THERM#4GND

@

2.2K_0402_5%

SMB_CLK_GPU

SMB_DATA_GPU

SCLK

R1135

DIS@

2
3

ADM1032ARMZ-2REEL_MSOP8

8
7
6
5

+3VGS

1 2

R1136

2.2K_0402_5%

DIS@

1 2

SMB_CLK_GPU
SMB_DATA_GPU

5

34

Q75B

DIS@

2N7002KDWH_SOT363-6

+3VGS

Reserve VBIOS for NV suggest (1Mbit)

+3VGS

12

R379

10K_0402_5%

R754 4.7K _0402_5%
R750 4.7K _0402_5%

+3VGS

1 2
1 2

@

@

@

ROM_CS#
SPI_HOLD#_VGA

1

Internal Thermal Sensor
Address: 0x9E H

SMB_CLK_GPU [22]
SMB_DATA_GPU [22]

1 2

R1134
100K_0402_5%

2

61

Q75A

DIS@

2N7002KDWH_SOT363-6

1
3
7
4

THERM#_VGA_R [22]

+3VGS

DIS@

EC_SMB_CK2 [ 14,49,52]

EC_SMB_DA2 [ 14,49,52]

0.1U_0402_16V4Z

U54

CE#

VDD

WP#

SCK
HOLD#
VSS

MX25L1005AMC-12G_SOP8

@

SO

SI

To VGA

C1447

8
6
5
2

@

+3VGS

ROM_SCLKSPI_WP#_VGA
ROM_SI
ROM_SO

To EC

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/01 2010/01/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

VGA_LVDS/HDMI/THERM/eDP

PCA70 LA-7521P M/B

1

23 64Tuesday, Apri l 12, 2011

0.1

5

4

3

2

1

C1127

C1132

C1138

C1143

C1148

22U_0603_6.3V6M

2

DIS@

1

0.01U_0402_25V7K

DIS@

1

2

0.022U_0402_25V7K

DIS@

1

2

0.047U_0402_25V6K

DIS@

1

2

0.022U_0402_25V7K

DIS@

1

2

+VGA_CORE

1

C1128

+

2

C1133

1

2

C1139

1

2

C1144

1

2

C1149

1

2

330U_2.5V_M_R17

DIS@

C1129

0.01U_0402_25V7K

DIS@

C1134

0.022U_0402_25V7K
C1140

DIS@

0.1U_0402_16V7K
C1145

DIS@

1U_0402_6.3V6K

DIS@

C1150

1

DIS@

+

2

DIS@

1

2

DIS@

1

2

DIS@

1

2

1

DIS@

2

330U_2.5V_M_R17

C1130

0.01U_0402_25V7K
C1135

1

2

0.022U_0402_25V7K
C1141

0.1U_0402_16V7K
C1146

4.7U_0603_6.3V6K

2

C1151

1

0.01U_0402_25V7K

DIS@

C1136

10U_0603_6.3V6M

DIS@

C1152

10U_0603_6.3V6M

2

DIS@

1

C1153

DIS@

1

2

22U_0805_6.3V6M

C1154

+VGA_CORE

D D

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

+VGA_CORE+VGA_CORE

41A for N12P-GS

U58G

AB11

VDD_0

AB13

VDD_1

AB15

VDD_2

AB17

VDD_3

AB19

VDD_4

AB21

VDD_5

AB23

VDD_6

AB25

VDD_7

AC11

VDD_8

AC12

C C

B B

AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24

M12
M14
M16
M18
M20
M22
M24

VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28

L11

VDD_29

L12

VDD_30

L13

VDD_31

L14

VDD_32

L15

VDD_33

L16

VDD_34

L17

VDD_35

L18

VDD_36

L19

VDD_37

L20

VDD_38

L21

VDD_39

L22

VDD_40

L23

VDD_41

L24

VDD_42

L25

VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50

P11

VDD_51

P13

VDD_52

P15

VDD_53

P17

VDD_54

P19

VDD_55

Part 7 of 7

POWER

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98

VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

2

1

+VGA_CORE

1

2

+VGA_CORE

1

2

+VGA_CORE

1

2

+VGA_CORE

1

2

DIS@

DIS@

DIS@

DIS@

DIS@

22U_0603_6.3V6M

2

C1126

1

0.01U_0402_25V7K
C1131

1

2

0.01U_0402_25V7K
C1137

1

2

0.047U_0402_25V6K
C1142

1

2

0.022U_0402_25V7K
C1147

1

2

22U_0603_6.3V6M

DIS@

0.01U_0402_25V7K

DIS@

0.01U_0402_25V7K

DIS@

0.047U_0402_25V6K

DIS@

0.022U_0402_25V7K

DIS@

N12P-GS-A1_BGA_973P GS@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

Compal Secre t Da t a

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

VGA_VGA CORE

PCA70 LA-7521P M/B

24 64Tuesday, April 12, 2011

1

of

0.1

5

+1.5VGS

D D

+1.5VGS

DIS@

1

2

+3VGS

L74

DIS@

BLM18PG181SN1D_0603

C C

+1.05VGS

B B

BLM18PG181SN1D_0603

12

4.7U_0603_6.3V6K

1

1

C1208

DIS@

2

2

close to Pin AJ9 close to Pin AC6

L75

DISO@

12

4.7U_0603_6.3V6K

1

1

DISO@

C1214

2

2

0.1U_0402_16V4Z
C1176

0.1U_0402_16V4Z

DIS@

1U_0402_6.3V6K

DISO@

1

2

1

2

C1209

C1215

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1158

C1179

C1212

DIS@
@

DIS@

1

2

1

2

12

12

OPT@

1U_0402_6.3V6K

C1156

DIS@

0.1U_0402_16V4Z
C1180

DIS@

10K_0402_5%

OPT@

R1628

R1629 10K_0402_5%DIS@

1 2

R1146 1K_0402_1%DIS@

1 2

R1631 10K_0402_5%DIS@

1 2

R1147

1 2

R1654

1 2

R1148

1 2

R1655

1 2

R1149

1 2

10K_0402_5%

R1635

1

C1157

DIS@

0.1U_0402_16V4Z
C1177

DIS@

1U_0402_6.3V6K

DIS@

C1210

1

2

0.1U_0402_16V4Z

1

DISO@

C1216

2

1

C1155

DIS@

DIS@

2

2

0.1U_0402_16V4Z

DIS@

C1178

DIS@

1

1

2

2

+IFPC_PLLVDD

0.1U_0402_16V4Z

DIS@

DIS@

C1211

1

1

2

2

+IFPC_IOVDD

0.1U_0402_16V4Z

1

DISO@

C1217

2

1

DIS@

2

DIS@

1

2

4

0.1U_0402_16V4Z
C1159

0.1U_0402_16V4Z
C1181

1K_0402_1%DIS@

1K_0402_1%
1K_0402_1%

1K_0402_1%

1K_0402_1%DIS@

0.1U_0402_16V4Z
C1182

DIS@

1

2

+IFPC_PLLVDD

+IFPC_IOVDD

+IFPEF_PLLVDD

+IFPE_IOVDD

7.2A

285mA

285mA

U58E

J23

FBVDDQ_0

J24

FBVDDQ_1

J29

FBVDDQ_2

AA27

FBVDDQ_3

AA29

FBVDDQ_4

AA31

FBVDDQ_5

AB27

FBVDDQ_6

AB29

FBVDDQ_7

AC27

FBVDDQ_8

AD27

FBVDDQ_9

AE27

FBVDDQ_10

AJ28

FBVDDQ_11

B18

FBVDDQ_12

E21

FBVDDQ_13

G17

FBVDDQ_14

G18

FBVDDQ_15

G22

FBVDDQ_16

G8

FBVDDQ_17

G9

FBVDDQ_18

H29

FBVDDQ_19

J14

FBVDDQ_20

J15

FBVDDQ_21

J16

FBVDDQ_22

J17

FBVDDQ_23

J20

FBVDDQ_24

J21

FBVDDQ_25

J22

FBVDDQ_26

N27

FBVDDQ_27

P27

FBVDDQ_28

R27

FBVDDQ_29

T27

FBVDDQ_30

U27

FBVDDQ_31

U29

FBVDDQ_32

V27

FBVDDQ_33

V29

FBVDDQ_34

V34

FBVDDQ_35

W27

FBVDDQ_36

Y27

FBVDDQ_37

AK9

IFPAB_PLLVDD

AJ11

IFPAB_RSET

AG9

IFPA_IOVDD

AG10

IFPB_IOVDD

220mA

AJ9

IFPC_PLLVDD

AK7

IFPC_RSET

285mA

AJ8

IFPC_IOVDD

220mA

AC6

IFPD_PLLVDD

AB6

IFPD_RSET

285mA

AK8

IFPD_IOVDD

220mA

AJ6

IFPEF_PLLVDD

AL1

IFPEF_RSET

AE7

IFPE_IOVDD

AD7

IFPF_IOVDD

N12P-GS-A1_BGA_973P GS@

Part 5 of 7

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

POWER

PEX_PLLVDD

PEX_SVDD_3V3

PEX_SVDD_3V3_NC

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

MIOA_VDDQ_NC_0
MIOA_VDDQ_NC_1
MIOA_VDDQ_NC_2
MIOA_VDDQ_NC_3

MIOB_VDDQ_NC_0
MIOB_VDDQ_NC_1
MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3

3

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

AK16
AK17
AK21
AK24
AK27

AG14

AG19
F7

J10
J11
J12
J13
J9

P9
R9
T9
U9

AA9
AB9
W9
Y9

R1633
10K_0402_5%

DIS@

2500mA

120mA

120mA

120mA

+PEX_PLLVDD

+PEX_SVDD_3V3

12

12

R1634
10K_0402_5%

DIS@

2

0.1U_0402_16V4Z

1

C1161

DIS@

2

0.1U_0402_16V4Z

1

DIS@

C1169

2

0.1U_0402_16V4Z

1

DIS@

C1200

2

0.1U_0402_16V4Z

1

DIS@

2

0.1U_0402_16V4Z

1

DIS@

2

0.1U_0402_16V4Z

1

DIS@

2

C1162

C1170

C1201

1U_0402_6.3V6K

1

DIS@

2

1U_0402_6.3V6K

1

DIS@

2

0.1U_0402_16V4Z

1

DIS@

2

0.1U_0402_16V4Z

DIS@

1

2

0.1U_0402_16V4Z

1

DIS@

2

C1163

C1171

C1183

C1193

C1202

1

2

1

2

1

2

1

2

1

2

1U_0402_6.3V6K

DIS@

1U_0402_6.3V6K

DIS@

4.7U_0603_6.3V6K

DIS@

4.7U_0603_6.3V6K

DIS@

1U_0402_6.3V6K

DIS@

4.7U_0603_6.3V6K

1

C1164

DIS@

2

4.7U_0603_6.3V6K

1

DIS@

C1172

2

L71

1U_0402_6.3V6K

C1185

1

DIS@

2

DIS@

R1630 0_0603_5%
R1653 0_0603_5%@

1U_0402_6.3V6K

C1194

1

DIS@

2

4.7U_0603_6.3V6K

1

DIS@

C1203

2

10U_0603_6.3V6M

1

C1166

DIS@

C1165

2

10U_0603_6.3V6M

1

DIS@

C1173

MBC1608121YZF_0603

C1187

C1186

C1204

C1174

2

@

R1632
0_0603_5%

1 2

12

DIS@

12
12

1

DIS@

2

1

DIS@

2

1

22U_0805_6.3V6M

C1167

22U_0805_6.3V6M

C1175

+1.05VGS

+3VGS
+1.05VGS

+3VGS

+1.05VGS

+1.05VGS

+3VGS

L77

BLM18PG181SN1D_0603

+1.05VGS

L76

A A

BLM18PG181SN1D_0603

close to Pin AK8 close to Pin AJ8

DISO@

12

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

DISO@

DISO@

C1228

C1229

1

1

2

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

DISO@

C1223

C1222

5

1

1

2

2

12

DISO@

1

2

DISO@

1

2

0.1U_0402_16V4Z

DISO@

C1230

1

2

0.1U_0402_16V4Z

DISO@

C1224

1

2

close to Pin AE7close to Pin AD7

DISO@

1U_0402_6.3V6K

DISO@

C1231

C1225

DISO@

1

2

+IFPE_IOVDD

DISO@

1

2

0.1U_0402_16V4Z

C1213

C1226

12

OPT@

12

OPT@

10K_0402_5%

R1636

10K_0402_5%

R1637

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

Compal Secre t Da t a

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

VGA_POWER

PCA70 LA-7521P M/B

25 64Tuesday, April 12, 2011

1

of

0.1

+IFPEF_PLLVDD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5

4

3

2

1

U58F

B3

GND_0

B6

GND_1

B9

GND_2

B12

GND_3

B15

GND_4

B21

GND_5

B24

GND_6

B27

GND_7

B30

GND_8

B33

D D

C C

B B

A A

GND_9

C2

GND_10

C34

GND_11

E6

GND_12

E9

GND_13

E12

GND_14

E15

GND_15

E18

GND_16

E24

GND_17

E27

GND_18

E30

GND_19

F2

GND_20

F31

GND_21

F34

GND_22

F5

GND_23

J2

GND_24

J5

GND_25

J31

GND_26

J34

GND_27

K9

GND_28

L9

GND_29

M2

GND_30

M5

GND_31

M11

GND_32

M13

GND_33

M15

GND_34

M17

GND_35

M19

GND_36

M21

GND_37

M23

GND_38

M25

GND_39

M31

GND_40

M34

GND_41

N11

GND_42

N12

GND_43

N13

GND_44

N14

GND_45

N15

GND_46

N16

GND_47

N17

GND_48

N18

GND_49

N19

GND_50

N20

GND_51

N21

GND_52

N22

GND_53

N23

GND_54

N24

GND_55

N25

GND_56

P12

GND_57

P14

GND_58

P16

GND_59

P18

GND_60

P20

GND_61

P22

GND_62

P24

GND_63

R2

GND_64

R5

GND_65

R31

GND_66

R34

GND_67

T11

GND_68

T13

GND_69

T15

GND_70

T17

GND_71

T19

GND_72

T21

GND_73

T23

GND_74

T25

GND_75

U11

GND_76

U12

GND_77

U13

GND_78

U14

GND_79

U15

GND_80

U16

GND_81

U17

GND_82

U18

GND_83

U19

GND_84

U20

GND_85

U21

GND_86

U22

GND_87

U23

GND_88

U24

GND_89

U25

GND_90

V2

GND_91

V5

GND_92

V9

GND_93

V12

GND_94

V14

GND_95

V16

GND_96

N12P-GS-A1_BGA_973P GS@

Part 6 of 7

GND

GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33

+3VS

DGPU_PWR_EN

DGPU_PWR_EN#

SI2301BDS-T1-E3_SOT23-3

R1153
20K_0402_5%

DIS@

5

+12VS

5

+3.3VS TO +3.3VGS

+3VS

DIS@

R1154

49.9K_0402_1%

DIS@

1 2

34

Q77B
2N7002KDWH_SOT363-6

DIS@

1

C1244
10U_0805_10V6K

DIS@

2

AP4800BGM-HF_SO8

R1164
150K_0402_1%

DIS@

1 2

1 2

34

Q85B
2N7002KDWH_SOT363-6

DIS@

S

Q76

G

2

1

2

+1.5V TO +1.5VGS

+1.5V +1.5VGS

U65

8

D

7

D

6

D

5

D

DIS@

R1165
0_0402_5%

DIS@

+3VGS

D

13

C1237

0.1U_0603_25V7K

DIS@

1

S

2

S

3

S

4

G

1

C1247

0.1U_0603_25V7K

DIS@

2

1

2

1

2

C1232
10U_0603_6.3V6M

DIS@

C1245
10U_0805_10V6K

DIS@

1

C1233
1U_0603_10V6K

DIS@

2

1

C1246
1U_0603_10V6K

DIS@

2

12

R1151
470_0603_5%

DIS@

61

DGPU_PWR_EN#

2

Q77A
2N7002KDWH_SOT363-6

DIS@

12

R1163
470_0603_5%

DIS@

61

DGPU_PWR_EN#

2

Q85A
2N7002KDWH_SOT363-6

DIS@

DGPU_PWR_EN#

DGPU_PWR_EN[17,60]

1

2

+12VS

5

C1234
10U_0805_10V6K

DIS@

12

34

0.1U_0603_25V7K

+1.05VS_VC CIO TO +1.05VGS

+1.05VS_VPCH +1.05VGS

U63

8

S

D

7

S

D

6

S

D

5

G

D

AP4800BGM-HF_SO8

DIS@

R1155
10K_0402_5%

DIS@

1 2

Q89B
2N7002KDWH_SOT363-6

DIS@

DGPU_PWR_EN

C1243

DIS@

R1156
0_0402_5%

DIS@

2

1

2

+3VALW

IN

Power Sequence of N12P_GS/GE,N12M_GE

DGPU_PWR_EN

PEX_VDD

NVVDD

IFPAB_IOVDD

FBVDDQ

1
2

1

C1235

3

10U_0805_10V6K

4

DIS@

2

1

C1238

0.1U_0603_25V7K

DIS@

2

12

R1160

100K_0402_5%

DIS@

DGPU_PWR_EN#

1

OUT

Q84

DTC124EKAT146_SC59-3

DIS@

GND

3

VDD33

1

C1236
1U_0603_10V6K

DIS@

2

12

R1152
470_0603_5%

DIS@

61

DGPU_PWR_EN#

2

Q89A
2N7002KDWH_SOT363-6

DIS@

+3VGS

+1.05VGS

+VGA_CORE

+1.8VGS

+1.5VGS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

Compal Secre t Da t a

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

VGA_GND/POWER

PCA70 LA-7521P M/B

26 64Tuesday, April 12, 2011

1

0.1

of

5

4

3

2

1

U58B

MDA[0..63][ 29,30]

D D

C C

+1.5VGS

12

R1166

1.1K_0402_1%

@

12

R1167

1.1K_0402_1%

@

MDA[0..63]

12mil

+FB_VREF

1

C1248

0.01U_0402_25V7K

@

2

200mA

B B

DIS@

R1168 60.4_0402_1%

+1.5VGS

R1169 10K_0402_5%

+1.05VGS

L78

1 2

BLM18PG330SN1D_0603

2

C1249
10U_0603_6.3V6M

DIS@

1

DIS@

2

1

10U_0603_6.3V6M

C1250

DIS@

1

2

1U_0402_6.3V6K

DIS@

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8

MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

+FB_AVDD0

+FB_AVDD1

+FB_VREF

12
12

DIS@

1

C1251

2

L32

N33

L33
N34
N35
P35
P33
P34
K35
K33
K34
H33

G34
G33

E34
E33

G31

F30

G30
G32

K30
K32
H30
K31

L31

L30

M32

N30

M30

P31
R32
R30

AG30
AG32

AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31

AM33

AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33

AL35
AM34
AM35

AF33

AE32

AF34

AE35

AE34

AE33

AB32

AC35
AG27

AF27

100mA

J19
J18

J27
T30
T29

+FB_AVDD0

C1252

0.1U_0402_16V4Z

DIS@

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FB_DLLAVDD_0
FB_PLLAVDD_0

FB_DLLAVDD_1
FB_PLLAVDD_1

FB_VREF_NC
FBA_DEBUG0
FBA_DEBUG1

N12P-GS-A1_BGA_973P GS@

Part 2 of 7

MEMORY INTERFACE

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0

A

FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_WCK0

FBA_WCK0_N

FBA_WCK1

FBA_WCK1_N

FBA_WCK2

FBA_WCK2_N

FBA_WCK3

FBA_WCK3_N

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

U30
V30
U31
V32
T35
U33
W32
W33
W31
W34
U34
U35
U32
T34
T33
W30
AB30
AA30
AB31
AA32
AB33
Y32
Y33
AB34
AB35
Y35
W35
Y34
Y31
Y30
W29
Y29

P32
H34
J30
P30
AF32
AL32
AL34
AF35

L35
G35
H31
N32
AD32
AJ31
AJ35
AC34

L34
H35
J32
N31
AE31
AJ32
AJ34
AC33

P29
R29
L29
M29
AG29
AH29
AD29
AE29

T32
T31

AC31
AC30

CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15

CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

CMDA0 [29]
CMDA2 [29]

CMDA3 [29]
CMDA4 [29,30]
CMDA5 [29,30]
CMDA6 [29,30]
CMDA7 [29,30]
CMDA8 [29,30]
CMDA9 [29,30]
CMDA10 [29,30]
CMDA11 [29,30]
CMDA12 [29,30]
CMDA13 [29,30]
CMDA14 [29,30]
CMDA15 [29,30]
CMDA16 [30]

CMDA18 [30]
CMDA19 [30]
CMDA20 [29,30]
CMDA21 [29,30]
CMDA22 [29,30]
CMDA23 [29,30]
CMDA24 [29,30]
CMDA25 [29,30]
CMDA26 [29,30]
CMDA27 [29,30]
CMDA28 [29,30]
CMDA29 [29,30]
CMDA30 [29,30]

DQMA0 [29]
DQMA1 [29]
DQMA2 [29]
DQMA3 [29]
DQMA4 [30]
DQMA5 [30]
DQMA6 [30]
DQMA7 [30]

DQSA#0 [29]
DQSA#1 [29]
DQSA#2 [29]
DQSA#3 [29]
DQSA#4 [30]
DQSA#5 [30]
DQSA#6 [30]
DQSA#7 [30]

DQSA0 [29]
DQSA1 [29]
DQSA2 [29]
DQSA3 [29]
DQSA4 [30]
DQSA5 [30]
DQSA6 [30]
DQSA7 [30]

CLKA0 [29]
CLKA0# [29]

CLKA1 [30]
CLKA1# [30]

A A

+1.05VGS

BLM18PG330SN1D_0603

2

C1253
10U_0603_6.3V6M

DIS@

1

L79

1 2

DIS@

DIS@

2

1

5

10U_0603_6.3V6M

C1254

1

2

1U_0402_6.3V6K

DIS@

C1255

+FB_AVDD1

1

C1256

0.1U_0402_16V4Z

DIS@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

Compal Secre t Da t a

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

VGA_MEM Interface A

PCA70 LA-7521P M/B

27 64Tuesday, April 12, 2011

1

of

0.1

5

4

3

2

1

MDB[0..63][31,32]

MDB0
MDB1
MDB2
MDB3

12
12

MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

DIS@

MDB4
MDB5
MDB6
MDB7
MDB8
MDB9

DIS@

D D

C C

B B

R1170 40.2_0402_1% DIS@

+1.5VGS

1 2

R1171 40.2_0402_1% DIS@

1 2

R1172 60.4_0402_1% DIS@

1 2

R1173 60.4_0402_1%

+1.5VGS

R1174 10K_0402_5%

MDB[0..63]

U58C

B13

FBC_D0

D13

FBC_D1

A13

FBC_D2

A14

FBC_D3

C16

FBC_D4

B16

FBC_D5

A17

FBC_D6

D16

FBC_D7

C13

FBC_D8

B11

FBC_D9

C11

FBC_D10

A11

FBC_D11

C10

FBC_D12

C8

FBC_D13

B8

FBC_D14

A8

FBC_D15

E8

FBC_D16

F8

FBC_D17

F10

FBC_D18

F9

FBC_D19

F12

FBC_D20

D8

FBC_D21

D11

FBC_D22

E11

FBC_D23

D12

FBC_D24

E13

FBC_D25

F13

FBC_D26

F14

FBC_D27

F15

FBC_D28

E16

FBC_D29

F16

FBC_D30

F17

FBC_D31

D29

FBC_D32

F27

FBC_D33

F28

FBC_D34

E28

FBC_D35

D26

FBC_D36

F25

FBC_D37

D24

FBC_D38

E25

FBC_D39

E32

FBC_D40

F32

FBC_D41

D33

FBC_D42

E31

FBC_D43

C33

FBC_D44

F29

FBC_D45

D30

FBC_D46

E29

FBC_D47

B29

FBC_D48

C31

FBC_D49

C29

FBC_D50

B31

FBC_D51

C32

FBC_D52

B32

FBC_D53

B35

FBC_D54

B34

FBC_D55

A29

FBC_D56

B28

FBC_D57

A28

FBC_D58

C28

FBC_D59

C26

FBC_D60

D25

FBC_D61

B25

FBC_D62

A25

FBC_D63

K27

FBCAL_PD_VDDQ

L27

FBCAL_PU_GND

M27

FBCAL_TERM_GND

G19

FBC_DEBUG0

G16

FBB_DEBUG1

N12P-GS-A1_BGA_973P GS@

Part 3 of 7

MEMORY INTERFACE C

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FBC_WCK0

FBC_WCK0_N

FBC_WCK1

FBC_WCK1_N

FBC_WCK2

FBC_WCK2_N

FBC_WCK3

FBC_WCK3_N

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

F18
E19
D18
C17
F19
C19
B17
E20
B19
D20
A19
D19
C20
F20
B20
G21
F22
F24
F23
C25
C23
F21
E22
D21
A23
D22
B23
C22
B22
A22
A20
G20

A16
D10
F11
D15
D27
D34
A34
D28

B14
B10
D9
E14
F26
D31
A31
A26

C14
A10
E10
D14
E26
D32
A32
B26

G14
G15
G11
G12
G27
G28
G24
G25

E17
D17

D23
E23

CMDB4
CMDB5
CMDB6
CMDB7
CMDB8
CMDB9
CMDB10
CMDB11
CMDB12
CMDB13
CMDB14
CMDB15

CMDB21
CMDB22
CMDB23
CMDB24
CMDB25
CMDB26
CMDB27
CMDB28
CMDB29
CMDB30

DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7

DQSB#0
DQSB#1
DQSB#2
DQSB#3
DQSB#4
DQSB#5
DQSB#6
DQSB#7

DQSB0
DQSB1
DQSB2
DQSB3
DQSB4
DQSB5
DQSB6
DQSB7

CMDB0 [31]
CMDB2 [31]

CMDB3 [31]
CMDB4 [31,32]
CMDB5 [31,32]
CMDB6 [31,32]
CMDB7 [31,32]
CMDB8 [31,32]
CMDB9 [31,32]
CMDB10 [31,32]
CMDB11 [31,32]
CMDB12 [31,32]
CMDB13 [31,32]
CMDB14 [31,32]
CMDB15 [31,32]
CMDB16 [32]

CMDB18 [32]
CMDB19 [32]
CMDB20 [31,32]
CMDB21 [31,32]
CMDB22 [31,32]
CMDB23 [31,32]
CMDB24 [31,32]
CMDB25 [31,32]
CMDB26 [31,32]
CMDB27 [31,32]
CMDB28 [31,32]
CMDB29 [31,32]
CMDB30 [31,32]

DQMB0 [31]
DQMB1 [31]
DQMB2 [31]
DQMB3 [31]
DQMB4 [32]
DQMB5 [32]
DQMB6 [32]
DQMB7 [32]

DQSB#0 [31]
DQSB#1 [31]
DQSB#2 [31]
DQSB#3 [31]
DQSB#4 [32]
DQSB#5 [32]
DQSB#6 [32]
DQSB#7 [32]

DQSB0 [31]
DQSB1 [31]
DQSB2 [31]
DQSB3 [31]
DQSB4 [32]
DQSB5 [32]
DQSB6 [32]
DQSB7 [32]

CLKB0 [31]
CLKB0# [31]

CLKB1 [32]
CLKB1# [32]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

Compal Secre t Da t a

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

VGA_MEM Interface C

PCA70 LA-7521P M/B

28 64Tuesday, April 12, 2011

1

of

0.1

5

4

3

2

1

DATA Bus

A8

A7
A2
A11
A5
A0
CAS#CMD15
BA1
A9

BA0
BA2
A3

A4
A13
WE#
A1
A10
A12

RAS#

A6

RST
A14
A15

MDA[0..63] [27,30]

CMDA[30..0] [27,30]
DQMA[7..0] [27 , 30 ]

DQSA[7..0] [27,30]
DQSA#[7..0] [27,30]

32..63

A8

A6
A1
A9

A4
A12
CAS#

A3
A11

CS0#_H

BA0
A15
BA1

CS1#_H
ODT_H

A5
A14
A10

A2
WE#

A0

RAS#

A7

CKE_H

RST
A13
BA2

29 64Tuesday, April 12, 2011

1

0.1

of

Memory Partition A - Lower 32 bits

+1.5VGS

12

R1175

1.1K_0402_1%

DIS@

D D

R1176

1.1K_0402_1%

DIS@

+1.5VGS

R1177

1.1K_0402_1%

DIS@

R1178

1.1K_0402_1%

C C

DIS@

B B

12

R1182
160_0402_1%

@

A A

12

12

12

CLKA0

CLKA0#

+FBA_VREFCA0

1

C1257

0.01U_0402_25V7K

2

DIS@

+FBA_VREFDQ0

1

C1258

0.01U_0402_25V7K

2

DIS@

1 2

1 2

0.01U_0402_25V7K

5

10K_0402_5%

DIS@

80.6_0402_1%
R1181

DIS@

80.6_0402_1%
R1183

2

C1259

@

1

R1184

DIS@

CLKA0[27]
CLKA0#[27]

DQSA0[27]
DQSA3[27]

DQMA0[ 27]
DQMA3[ 27]

DQSA#0[27]
DQSA#3[27]

12

243_0402_1%

1

2

+FBA_VREFCA0
+FBA_VREFDQ0

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA30

CMDA29
CMDA13
CMDA27

CLKA0
CLKA0#
CMDA3

CMDA0
CMDA2
CMDA11
CMDA15
CMDA28

DQSA0
DQSA3

DQMA0
DQMA3

DQSA#0
DQSA#3

CMDA20

12

R1185

DIS@

1U_0402_6.3V6K

C1260

DIS@

1

2

M8

H1
N3

P7
P3
N2
P8
P2
R8
R2
T8
R3

L7
R7
N7
T3
T7

M7

M2

N8

M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

J1

L1

J9

L9

1U_0402_6.3V6K

C1261

DIS@

DIS@

1

2

U66

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

X76@

0.1U_0402_16V4Z
C1262

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C1263

DIS@

1

1

DIS@

2

2

4

U67

MDA1

E3

MDA5

F7

MDA0

F2

MDA3

F8

MDA4

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C1264

1

2

Group0

MDA7
MDA2
MDA6

MDA29
MDA26
MDA30
MDA24
MDA27

Group3

MDA25
MDA31
MDA28

+1.5VGS +1.5VGS

1 2

1 2

DQSA2[27]
DQSA1[27]

DQMA2[ 27]
DQMA1[ 27]

DQSA#2[27]
DQSA#1[27]

243_0402_1%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1266

DIS@

C1265

DIS@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATIO N. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMEN T EX CEPT AS AUTH ORIZ ED B Y CO MPAL ELE CTRONICS, INC. NEI THER THIS SHEE T NOR THE INFORMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R1179
10K_0402_5%

DIS@

R1180
10K_0402_5%

DIS@

R1186

DIS@

+1.5VGS+1.5VGS

1U_0402_6.3V6K

1

DIS@

2

+FBA_VREFCA0
+FBA_VREFDQ0

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA30

CMDA29
CMDA13
CMDA27

CLKA0
CLKA0#
CMDA3

CMDA0
CMDA2
CMDA11
CMDA15
CMDA28

DQSA2
DQSA1

DQMA2
DQMA1

DQSA#2
DQSA#1

CMDA20

12

1U_0402_6.3V6K

1

C1268

DIS@

C1267

2

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

64Mx1664Mx16

96-BALL

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

X76@

0.1U_0402_16V4Z

1

1

C1269

DIS@

2

2

2009/01/01 2010/01/01

3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1270

DIS@

DIS@

2

Compal Secret Data

MDA22

E3

MDA19

F7

MDA23

F2

MDA16

F8

MDA20

H3

MDA18

H8

MDA21

G2

MDA17

H7

MDA14

D7

MDA9

C3

MDA12

C8

MDA11

C2

MDA13

A7

MDA8

A2

MDA15

B8

MDA10

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

0.1U_0402_16V4Z

1

C1272

DIS@

C1271

2

Deciphered Date

1

2

0.1U_0402_16V4Z

DIS@

Group2

Group1

C1273

GB2-128

Mode E - Mirror Mode Mapping

Address

CMD3
CMD8
CMD2
CMD21
CMD24
CMD23
CMD26
CMD7

CMD13
CMD4
CMD18
CMD29
CMD27
CMD6
CMD17
CMD19
CMD22
CMD12
CMD28
CMD10
CMD25
CMD9
CMD1
CMD11
CMD0
CMD5
CMD16
CMD20
CMD14
CMD30

Title

Size Document Number R ev

2

Date: Sheet

Compal Electronics, Inc.

0..31
CKE_L

CS0#_L

CS1#_L

ODT_L

VGA_VRAM_A Lower

PCA70 LA-7521P M/B

5

4

3

2

1

Memory Partition A - Upper 32 bits

MDA[0..63] [27,29]

+1.5VGS

12

R1188

1.1K_0402_1%

D D

DIS@

+FBA_VREFCA1

12

1

12

12

C1274

0.01U_0402_25V7K

DIS@

2

+FBA_VREFDQ1

1

C1275

0.01U_0402_25V7K

DIS@

2

1 2

1 2

DIS@

80.6_0402_1%
R1193

DIS@

80.6_0402_1%
R1195

0.01U_0402_25V7K

C1276

@

CLKA1[27]
CLKA1#[27]

R1187

1.1K_0402_1%

DIS@

+1.5VGS +1.5VGS +1.5VGS

R1189

1.1K_0402_1%

DIS@

R1190

C C

1.1K_0402_1%

DIS@

B B

CLKA1

12

R1194
160_0402_1%

@

A A

CLKA1#

+FBA_VREFCA1
+FBA_VREFDQ1

CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA27

CMDA29
CMDA6
CMDA30

CLKA1
CLKA1#
CMDA16

CMDA19
CMDA18
CMDA11
CMDA15
CMDA25

DQSA4[27]
DQSA5[27] DQSA6[27]

DQMA4[ 27]
DQMA5[ 27] DQMA6[2 7]

DQSA#4[27]
DQSA#5[27] DQSA#6[27]

243_0402_1%

2

1

DQSA4
DQSA5

DQMA4
DQMA5

DQSA#4
DQSA#5

CMDA20 CMDA20

12

R1196

DIS@

+1.5VGS +1.5VGS

1U_0402_6.3V6K

DIS@

1

2

C1277

M8

H1
N3

P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

M7

M2

N8

M3

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3

B7

T2
L8

J1
L1
J9
L9

1U_0402_6.3V6K

C1278

DIS@

1

2

U68

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

X76@

1

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1279

DIS@

C1280

DIS@

1

2

MDA38

E3

MDA33

F7

MDA39

F2

MDA32

F8

MDA37

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

0.1U_0402_16V4Z

1

C1281

DIS@

2

MDA34
MDA36
MDA35

MDA41
MDA45
MDA42
MDA44
MDA43
MDA46
MDA40
MDA47

1

2

Group4

Group5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1282

DIS@

C1283

DIS@

2

R1191
10K_0402_5%

DIS@

1 2

1 2

R1192
10K_0402_5%

DIS@

DQSA7[27]

DQMA7[2 7]

DQSA#7[27]

R1197

243_0402_1%

DIS@

1

2

+FBA_VREFCA1
+FBA_VREFDQ1

CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA27

CMDA29
CMDA6

CLKA1
CLKA1#
CMDA16

CMDA19
CMDA18
CMDA11
CMDA15
CMDA25

DQSA7
DQSA6

DQMA7
DQMA6

DQSA#7
DQSA#6

12

1U_0402_6.3V6K

1

C1284

DIS@

2

DIS@

CMDA30

1U_0402_6.3V6K

C1285

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

0.1U_0402_16V4Z

1

DIS@

2

U69

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

64Mx1664Mx16

96-BALL

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

X76@

1

C1286

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1288

DIS@

C1287

DIS@

2

MDA56

E3

MDA57

F7

MDA58

F2

MDA59

F8

MDA60

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

MDA61
MDA62
MDA63

MDA51
MDA52
MDA48
MDA53
MDA49
MDA54
MDA50
MDA55

Group7

Mode E - Mirror Mode Mapping

Group6

Address

CMD3
CMD8
CMD2
CMD21
CMD24
CMD23
CMD26
CMD7

CMD13
CMD4
CMD18
CMD29
CMD27
CMD6
CMD17
CMD19
CMD22
CMD12
CMD28
CMD10
CMD25
CMD9
CMD1
CMD11
CMD0
CMD5
CMD16

1

DIS@

2

C1289

C1290

DIS@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CMD20
CMD14
CMD30

CMDA[30..0] [27,29]
DQMA[7..0] [27 , 29 ]
DQSA[7..0] [27,29]
DQSA#[7..0] [27,29]

GB2-128

DATA Bus

0..31
CKE_L

A8

CS0#_L

A7
A2
A11
A5
A0
CAS#CMD15
BA1
A9

BA0
BA2
A3

A4
A13
WE#
A1
A10
A12

CS1#_L

RAS#

ODT_L

A6

RST
A14
A15

32..63

A8

A6
A1
A9

A4
A12
CAS#

A3
A11

CS0#_H

BA0
A15
BA1

CS1#_H
ODT_H

A5
A14
A10

A2
WE#

A0

RAS#

A7

CKE_H

RST
A13
BA2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATIO N. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMEN T EX CEPT AS AUTH ORIZ ED B Y CO MPAL ELE CTRONICS, INC. NEI THER THIS SHEE T NOR THE INFORMATIO N IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number R ev

2

Date: Sheet

Compal Electronics, Inc.

VGA_VRAM_A Upper

PCA70 LA-7521P M/B

30 64Tuesday, April 12, 2011

1

0.1

of

5

4

3

2

1

Memory Partition C - Lower 32 bits

+1.5VGS

C1301

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

1U_0402_6.3V6K

1

C1302

GS@

2

U70

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

64Mx1664Mx16

96-BALL

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

X76@

1

GS@

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1303

C1304

GS@

2

MDB16

E3

MDB17

F7

MDB19

F2

MDB18

F8

MDB20

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

0.1U_0402_16V4Z

1

GS@

2

MDB21
MDB22
MDB23

MDB13
MDB9
MDB14
MDB11
MDB12
MDB8
MDB15
MDB10

C1305

Group2

Mode E - Mirror Mode Mapping

Group1

0.1U_0402_16V4Z
C1306

0.1U_0402_16V4Z

1

C1307

GS@

2

1

GS@

2

Address

CMD3
CMD8
CMD2
CMD21
CMD24
CMD23
CMD26
CMD7

CMD13
CMD4
CMD18
CMD29
CMD27
CMD6
CMD17
CMD19
CMD22
CMD12
CMD28
CMD10
CMD25
CMD9
CMD1
CMD11
CMD0
CMD5
CMD16
CMD20
CMD14
CMD30

GB2-128

0..31
CKE_L

A8

CS0#_L

A7
A2
A11
A5
A0
CAS#CMD15
BA1
A9

BA0
BA2
A3

A4
A13
WE#
A1
A10
A12

CS1#_L

RAS#

ODT_L

A6

RST
A14
A15

12

R1198

1.1K_0402_1%

D D

GS@

+FBA_VREFCA2

12

12

12

1 2

GS@

1 2

GS@

1

C1291

0.01U_0402_25V7K

2

GS@

+FBA_VREFDQ2

1

C1292

0.01U_0402_25V7K

2

GS@

R1204 80.6_0402_1%

R1206 80.6_0402_1%

0.01U_0402_25V7K

R1207

10K_0402_5%

GS@

2

C1293

@

1

12

R1199

1.1K_0402_1%

GS@

+1.5VGS

R1200

1.1K_0402_1%

GS@

R1201

C C

1.1K_0402_1%

GS@

B B

CLKB0

12

R1205
160_0402_1%

@

CLKB0#

A A

CLKB0[28]
CLKB0#[28]

DQSB0[28]
DQSB3[28]

DQMB0[ 28]
DQMB3[ 28]

DQSB#0[28]
DQSB#3[28]

R1208

243_0402_1%

GS@

+FBA_VREFCA2

+FBA_VREFDQ2

CMDB7
CMDB10
CMDB24
CMDB6
CMDB22
CMDB26
CMDB5
CMDB21
CMDB8
CMDB4
CMDB25
CMDB23
CMDB9
CMDB12
CMDB14
CMDB30

CMDB29
CMDB13
CMDB27

CLKB0
CLKB0#
CMDB3

CMDB0
CMDB2
CMDB11
CMDB15
CMDB28

DQSB0
DQSB3

DQMB0
DQMB3

DQSB#0
DQSB#3

CMDB20

12

1

GS@

2

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3

L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

1U_0402_6.3V6K

1U_0402_6.3V6K

C1294

1

GS@

2

U71

GS@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1296

C1297

1

GS@

2

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

X76@

C1295

1

2

MDB3

E3

MDB5

F7

MDB2

F2

MDB4

F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

GS@

2

Group0

MDB1
MDB6
MDB0
MDB7

MDB31
MDB25
MDB29
MDB24
MDB28

Group3

MDB26
MDB30
MDB27

+1.5VGS +1.5VGS

R1202
10K_0402_5%

GS@

R1203
10K_0402_5%

GS@

0.1U_0402_16V4Z

1

C1298

GS@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1300

C1299

GS@

2

12

12

DQSB2[28]
DQSB1[28]

DQMB2[ 28]
DQMB1[ 28]

DQSB#2[28]
DQSB#1[28]

R1209

243_0402_1%

GS@

+FBA_VREFCA2

+FBA_VREFDQ2

CMDB7
CMDB10
CMDB24
CMDB6
CMDB22
CMDB26
CMDB5
CMDB21
CMDB8
CMDB4
CMDB25
CMDB23
CMDB9
CMDB12
CMDB14
CMDB30

CMDB29
CMDB13
CMDB27

CLKB0
CLKB0#
CMDB3

CMDB0
CMDB2
CMDB11
CMDB15
CMDB28

DQSB2
DQSB1

DQMB2
DQMB1

DQSB#2
DQSB#1

CMDB20

12

+1.5VGS+1.5VGS

1U_0402_6.3V6K

1

GS@

2

MDB[0..63] [28,32]

CMDB[30..0] [28,32]
DQMB[7..0] [28 , 32 ]
DQSB[7..0] [28,32]
DQSB#[7..0] [28,32]

DATA Bus

32..63

A8

A6
A1
A9
A4
A12
CAS#
A3
A11

CS0#_H

BA0
A15
BA1

CS1#_H
ODT_H

A5
A14
A10
A2
WE#
A0

RAS#

A7

CKE_H

RST
A13
BA2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATIO N. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMEN T EX CEPT AS AUTH ORIZ ED B Y CO MPAL ELE CTRONICS, INC. NEI THER THIS SHEE T NOR THE INFORMATIO N IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number R ev

Custom

2

Date: Sheet

Compal Electronics, Inc.

VGA_VRAM_C Lower

PCA70 LA-7521P M/B

31 64Tuesday, April 12, 2011

1

0.1

of

5

4

3

2

1

Memory Partition C - Upper 32 bits

MDB[0..63] [28,31]

+1.5VGS

R1211

GS@

R1210

GS@

R1212

GS@

R1213

GS@

CLKB1

CLKB1#

12

12

+1.5VGS

12

12

+FBA_VREFCA3

1

2

+FBA_VREFDQ3

1

2

1 2

GS@

1 2

GS@

C1308

0.01U_0402_25V7K

GS@

C1309

0.01U_0402_25V7K

GS@

80.6_0402_1%
R1217

80.6_0402_1%
R1218

0.01U_0402_25V7K

C1310

@

5

2

1

D D

1.1K_0402_1%

1.1K_0402_1%

1.1K_0402_1%

C C

1.1K_0402_1%

B B

A A

12

R1216
160_0402_1%

@

+FBA_VREFCA3
+FBA_VREFDQ3

CMDB9
CMDB24
CMDB10
CMDB13
CMDB26
CMDB22
CMDB21
CMDB5
CMDB8
CMDB23
CMDB28
CMDB4
CMDB7
CMDB14
CMDB12
CMDB27

CMDB29
CMDB6
CMDB30

R1219

GS@

CLKB1
CLKB1#
CMDB16

CMDB19
CMDB18
CMDB11
CMDB15
CMDB25

DQSB4
DQSB5

DQMB4
DQMB5

DQSB#4
DQSB#5

CMDB20

12

1U_0402_6.3V6K

C1312

1

GS@

2

CLKB1[28]
CLKB1#[28]

DQSB4[28]
DQSB5[28] DQSB6[28]

DQMB4[2 8]
DQMB5[2 8] DQMB6[2 8]

DQSB#4[28]
DQSB#5[28] DQSB#6[28]

243_0402_1%

U73

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4W1G1646G-BC11_FBGA96

X76@

1U_0402_6.3V6K

C1313

1

1

GS@

2

2

+1.5VGS

1

C1311

+

330U_2.5V_M_R17

GS@

2

4

96-BALL
SDRAM DDR3

0.1U_0402_16V4Z
C1314

GS@

R1214
10K_0402_5%

GS@

R1215
10K_0402_5%

GS@

DQSB7[28]

DQMB7[2 8]

DQSB#7[28]

R1220

243_0402_1%

GS@

+1.5VGS+1.5VGS

1

2

+FBA_VREFCA3
+FBA_VREFDQ3

CMDB9
CMDB24
CMDB10
CMDB13
CMDB26
CMDB22
CMDB21
CMDB5
CMDB8
CMDB23
CMDB28
CMDB4
CMDB7
CMDB14
CMDB12
CMDB27

CMDB29
CMDB6
CMDB30

CLKB1
CLKB1#
CMDB16

CMDB19
CMDB18
CMDB11
CMDB15
CMDB25

DQSB7
DQSB6

DQMB7
DQMB6

DQSB#7
DQSB#6

CMDB20

12

1U_0402_6.3V6K

1

C1319

GS@

GS@

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_0402_16V4Z
C1315

1

GS@

2

MDB35

F7

MDB36

F2

MDB34

F8

MDB38

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

+1.5VGS +1.5VGS

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

0.1U_0402_16V4Z

1

1

C1316

GS@

2

2

MDB32
MDB39
MDB33

MDB41
MDB46
MDB42
MDB47
MDB44
MDB45
MDB40
MDB43

GS@

Group4

Group5

1 2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1317

C1318

GS@

2

MDB37

E3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATIO N. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMEN T EX CEPT AS AUTH ORIZ ED B Y CO MPAL ELE CTRONICS, INC. NEI THER THIS SHEE T NOR THE INFORMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

U72

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4W1G1646G-BC11_FBGA96

X76@

0.1U_0402_16V4Z

1U_0402_6.3V6K

1

C1321

C1320

GS@

2

Compal Secret Data

64Mx1664Mx16

96-BALL
SDRAM DDR3

0.1U_0402_16V4Z

1

C1322

GS@

2

Deciphered Date

1

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

GS@

MDB63

E3

MDB57

F7

MDB61

F2

MDB59

F8

MDB60

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

MDB56
MDB62
MDB58

MDB48
MDB55
MDB49
MDB52
MDB51
MDB54
MDB50
MDB53

Group7

Mode E - Mirror Mode Mapping

Group6

Address

CMD3
CMD8
CMD2
CMD21
CMD24
CMD23
CMD26
CMD7

CMD13
CMD4
CMD18
CMD29
CMD27
CMD6
CMD17
CMD19
CMD22
CMD12
CMD28
CMD10
CMD25
CMD9
CMD1
CMD11
CMD0
CMD5
CMD16

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1323

C1324

0.1U_0402_16V4Z

1

C1325

GS@

2

Title

Size Document Number R ev

Custom

2

Date: Sheet

1

GS@

2

CMD20
CMD14
CMD30

Compal Electronics, Inc.

PCA70 LA-7521P M/B

CMDB[30..0] [28,31]
DQMB[7..0] [28 , 31 ]
DQSB[7..0] [28,31]
DQSB#[7..0] [28,31]

GB2-128

DATA Bus

0..31
CKE_L

A8

CS0#_L

A7
A2
A11
A5
A0
CAS#CMD15
BA1
A9

BA0
BA2
A3

A4
A13
WE#
A1
A10
A12

CS1#_L

RAS#

ODT_L

A6

RST
A14
A15

VGA_VRAM_C Upper

1

32..63

A8

A6
A1
A9

A4
A12
CAS#

A3
A11

CS0#_H

BA0
A15
BA1

CS1#_H
ODT_H

A5
A14
A10

A2
WE#

A0

RAS#

A7

CKE_H

RST
A13
BA2

32 64Tuesday, April 12, 2011

of

0.1

5

+3VGS

R1221

45.3K_0402_1%

DIS@

D D

STRAP0[23]
STRAP1[23]
STRAP2[23]

1 2

R1224

45.3K_0402_1%

@

1 2

R1222

34.8K_0402_1%

@

1 2

R1235

4.99K_0402_1%

DIS@

1 2

R869

45.3K_0402_1%

1 2

R1226

24.9K_0402_1%

GS@

1 2

4

Resistor Values

5K
10K
15K
20K
25K
30K
35K
45K

Pull-up to +3VGS

1000
1001
1010
1011
1100
1101
1110
1111

+3VGS

3

Pull-down to Gnd

0000
0001
0010
0011
0100
0101
0110
0111

Physical
Strapping pin

GS

ROM_SO

ROM_SCLK

GV FB[1] FB[0]
GS
GV

ROM_SI
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

2

Power
Rail

Logical
Strapping Bit3

XCLK_417

Logical
Strapping Bit2

FB_0_BAR_SIZE

Logical
Strapping Bit1

+3VGS

+3VGS

+3VGS

PCI_DEVID[4]

SUB_VENDOR

SLOT_CLK_CFG
PCI_DEVID[5]

RAMCFG[1]RAMCFG[3] RAMCFG[2]
+3VGS USER[3]
+3VGS

3GIO_PADCFG[3]

+3VGS

PCI_DEVID[3]

+3VGS

SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

+3VGS

RESERVED RESERVED

PCIE_MAX_SPEED DP_PLL_VDD33V

1

Logical
Strapping Bit0

VGA_DEVICESMB_ALT_ADDR

PEX_PLL_EN_TERM

RAMCFG[0]
USER[0]USER[1]USER[2]
3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]
PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

0010
R453
PD 15K
0011
R378
PD 20K
0010
R378
PD 15K
0011
R378
PD 20K
0110
R378
PD 35K

1 2

1 2

+3VGS

1 2

1 2

R1641
10K_0402_5%

@

R1644
20K_0402_5%

GV@

R1642
15K_0402_1%

GV@

R1645
15K_0402_5%

@

0001
R1231
PD 10K
0001
R1231
PD 10K
1001
R1228
PU 10K
1001
R1228
PU 10K

R1228
PU 10K

1010
R1229
PU 15K
1010
R1229
PU 15K
1000
R1229
PU 5K
1000
R1229
PU 5K
1000Hynix (0x6)
R1229
PU 5K

SUB_VENDOR

No VBIOS ROM ( Default)

0

1

BIOS ROM is present

FB_0_BAR_SIZE

0

256MB (Default)

1

Reserved

XCLK_417

0

1

User [3:0]

1000-1100

3GIO_PADCFG[3:0]

0000

0110

RESERVED

Notebook Default

SLOT_CLOCK_CFG

0

GPU and MCH don't share a common reference clock

1

GPU and MCH share a common reference clock (Default)

SMBUS_ALT_ADDR

0x9E (Default)

0

1

0x9C (Multi-GPU usage)

PCIE_MAX_SPEED

1

Default

Package

N12P-GS

N12P-GV-B 0x1050

GB2-128

GB2b-128 (..0101 0000)

DeviceID

0x0DF4

VGA_DEVICE

0

1

DP_PLL_VDD33V

0

277MHz (Default)

Reserved

1111

EDID is used
1920x1080

Customer defined

PEX_PLL_EN_TERM

Disable (Default)

0

1

Enable

3D Device

VGA Device (Default)

Default

PCI_DEVID[5..0]GPU

(..1111 0100)

R1226

4.99K_0402_1%

GV@

+3VGS

C C

ROM_SI[23]

ROM_SO[23]

ROM_SCLK[23]

R378
15K_0402_1%

X76@

R378

34.8K_0402_1%

X76@

B B

GPU

N12P-GS

N12P-GS

N12P-GV

N12P-GV

N12P-GV

A A

R1227

4.99K_0402_1%

@

1 2

1 2

Frenq. strap3 strap4

64M* 16* 8

900 MHz

1GB
64M* 16* 8

900 MHz

1GB
64M* 16* 4

900 MHz

512MB
64M* 16* 4

900 MHz

512MB
128M* 16* 4

800 MHz

1GB

R1228
10K_0402_1%

GV@

1 2

R1231
10K_0402_1%

GS@

1 2

Memory Config
Hynix (0x2)

H5TQ1G63DFR-11C
SA000041S60
Samsung (0x3)
K4W1G1646G-BC11
SA00004GS30
Hynix (0x2)
H5TQ1G63DFR-11C
SA000041S60
Samsung (0x3)
K4W1G1646G-BC11
SA00004GS30

H5TQ2G63BFR-12C
SA00003VS30

R1229
15K_0402_1%

GS@

1 2

R1229

4.99K_0402_1%

GV@

R1232
15K_0402_1%

@

1 2

strap0 strap1 strap2 ROM_SI ROM_SO ROM_SCLKMemory Size

0000

1111

R1235

R1221

PD 5K

PU 45K

0000

1111

R1235

R1221

PD 5K

PU 45K

0000

1111

R1235

R1221

PD 5K

PU 45K

0000

1111

R1235

R1221

PD 5K

PU 45K

0000

1111 1010 1001

R1235

R1221

PD 5K

PU 45K

0100
R1226
PD 25K
0100
R1226
PD 25K
0000
R1226
PD 5K
0000
R1226
PD 5K
0000
R1226
PD 5K

STRAP4[23]

STRAP3[23]

1010
R1642
PU 15K
1010
R1642
PU 15K

R1642
PU 15K

NC

NC

NC

NC

0011
R1644
PD 20K
0011
R1644
PD 20K
0011
R1644
PD 20K

STRAP4

STRAP3

Security Clas s if i cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/01 2010/01/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

VGA_MSIC

PCA70 LA-7521P M/B

33 64Tuesday, April 12, 2011

1

0.1

of

5

pre-MP Scaler power soft start

C522

0.1U_0402_16V4Z

SCALER_ON#[49]

PVT change to KBC control

D D

C C

B B

A A

for EUP S5 over 1W

+3V_SCA

58mA

1

C533

10U_0603_6.3V6M

To AMP Input

To HP Out

To EC ADC

+1.2V_SCA

12

R531
0_0402_5%

+1.2V_SCA_ADC

C538

1

10U_0603_6.3V6M

2

S_LINE_OUTL[48]
S_LINE_OUTR[48]
S_HP_OUT_L[47]
S_HP_OUT_R[47]

S_ENVDD[49]
+3V_SCA

CRT_DDC_CLK_IN[40]
CRT_DDC_DAT_IN[40]

2

INTERNAL
HDMI

0.1U_0402_16V4Z

+3V_SCA

C539

1

0.1U_0402_16V4Z

2

+3V_SCA

C534

1

0.1U_0402_16V4Z

2

+3V_SCA

EXTERNAL
HDMI-IN

C537

1 2

EXTERNAL
D-Sub-IN

+AD_VDD

+3V_SCA
AD1[49]
AD2[49]

R545 4.7K_0402_5%@

1 2

R1047 4.7K_0402_5%

1 2

R1048 4.7K_0402_5%

1 2

5

1 2

R505 100_0402_1%

C525 1U_0402_6.3V6K

1 2

+3V_SCA_R

L29

1 2

BLM18PG181SN1D_0603

C1056

1

@

0.1U_0402_16V4Z

2

R521 6.2K_0402_5%

1 2

R523 6.2K_0402_5%@

HDMI_C_TX0-[36]
HDMI_C_TX0+[36]
HDMI_C_TX1-[36]
HDMI_C_TX1+[36]
HDMI_C_TX2-[36]
HDMI_C_TX2+[36]
HDMI_C_CLK+[36]
HDMI_C_CLK-[36]

1 2

HDMI_D0-[37]
HDMI_D0+[37]
HDMI_D1-[37]
HDMI_D1+[37]
HDMI_D2-[37]
HDMI_D2+[37]
HDMI_CK+[37]
HDMI_CK-[37]

TMDS_REXT
HDMI_C_TX0­HDMI_C_TX0+
HDMI_C_TX1­HDMI_C_TX1+
HDMI_C_TX2­HDMI_C_TX2+
HDMI_C_CLK+
HDMI_C_CLK-

0.67mA

VGA_VSYNC_IIN[40]
VGA_HSYNC_IN[40]

VGA_GND_BLUE[40]
VGA_BLUE_IN[40]
VGA_GND_GREEN[40]
VGA_GREEN_IN[40]
VGA_SOG[40]
VGA_GND_RED[40]
VGA_RED_IN[40]

C540

10U_0603_6.3V6M

EESDA
EESCL

+1.2V_SCA

C544

T170
T171

1 2

S_LINE_OUTL_R
S_LINE_OUTR_R
S_HP_OUT_L_R
S_HP_OUT_R_R

R539 4.7K_0402_5%

1 2

R540 0_0402_5%@

1 2

R542 0_0402_5%@

1 2

0.1U_0402_16V4Z

+3VALW

12

1

R504
10K_0402_5%

2

G

2

PMV65XP 1P SOT23 TMOS

+3V_SCA

116mA

C529

1

2

1
2
3
4
5
6
7
8

9
10
11

HDMI_D0-

12

HDMI_D0+

13

HDMI_D1-

14

HDMI_D1+

15

HDMI_D2-

16

HDMI_D2+

17

HDMI_CK+

18

HDMI_CK-

19
20

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

38
39
40
41
42
43
44
45
46
47
48

+AD_VDD

49
50

AD1_R

51

AD2_R

52
53
54

S_ENVDD

55
56
57
58
59
60

1

2

S

12

Q46

D

1 3

C530

1

10U_0603_6.3V6M

1U_0402_6.3V6K

2

U25

DP_VDD/TMDS_VDD
TMDS_REXT
LANE0P/RX2P_0
LANE0N/RX2N_0
LANE1P/RX1P_0
LANE1N/RX1N_0
LANE2P/RX0P_0
LANE2N/RX0N_0
LANE3P/RXCP_0
LANE3N/RXCN_0
DP_GND/TMDS_GND
LANE0P/RX2P_1
LANE0N/RX2N_1
LANE1P/RX1P_1
LANE1N/RX1N_1
LANE2P/RX0P_1
LANE2N/RX0N_1
LANE3P/RXCP_1
LANE3N/RXCN_1
DP_VDD/TMDS_VDD2

AVS0
AHS0
ADC_VDD
B0­B0+
G0­G0+
SOG0
R0­R0+
GPI/B1- / V8_7
GPI/B1+ / V8_6
GPI/G1- / V8_5
GPI/G1+ / V8_4
GPI/SOG1 / V8_3
GPI/R1-/V8_2
GPI/R1+/V8_1

ADC_GND
GPI/V8_0/AHS1
VCLK/AVS1
V8_7/GPIO
LINE_INL/V8_6/IICSCL/GPIO
LINE_INR/V8_5/IICSDA/GPIO
SPDIF3/AUDIO_REF/V8_4/WS/GPIO
AUDIO_SOUTL/V8_3/SCK/GPIO
AUDIO_SOUTR/V8_2/MCK/GPIO
AUDIO_HOUTL/V8_1/SD0/GPIO
AUDIO_HOUTR/V8 _0/PWM0/GPIO
LS_ADC_VDD
A-ADC0/VCLK/GPIO
A-ADC1/GPIO
A-ADC2/GPIO
A-ADC3/GPIO
A-ADC4/GPIO
TCON[0][5]/BADC0/PWM1/PWM5/GPIO
TCON[1][4]/B-ADC1/IICSCL/GPIO
TCON[9][11]/B-ADC2/IICSDA/GPIO
TCON[7][10]/DDCSCL1/GPIO
TCON[3][5]/DDCSDA1/GPIO
VCCK

RTD2472D-GR_LQFP128_20X14

4

+3V_SCA_R +3V_SCA_R+1.2V_SCA

R506

@

0_0805_5%

C531

C532

1

1

1U_0402_6.3V6K

0.1U_0402_16V4Z

2

2

HDMI-Port0

HDMI-Port1

DVT add test point
for Scalar dubug.

R551

@

0_0402_5%

1 2

+3V_SCA

0.1U_0402_16V4Z

4

+3V TO +1.2VALW

151mA

L28

1 2

BLM18PG181SN1D_0603

C526

10U_0603_6.3V6M

62

84

106

PVCC

PVCC

PVCC

PGND

107

88mA

1

C546

2

+1.2V_SCA_L

R507

20_0402_1%

C527

4.7U_0603_10V6K

1

1

1 2

2

2

ABLU4/SPDIF1/SD1/TCON[ 7][3]/GPIO/IICSCL/BB1P

ABLU3/SPDIF2/SD2/TCON[ 9][11]/GPIO/IICSDA/BB1N

ABLU2/SPDIF3/SD3/TCON[10][8]/GPIO/PWM1/PWM5/BCLKP

ABLU1/ GPIO/ABLU7/TXO3+_8b/TXO4+_10b/BG3P

ABLU0/ GPIO/ABLU6/TXO3-_8b/TXO4-_10b/BG3N

AGRN7/GPIO/ABLU5/TXOC+_8b/TXO3+_10b/BG2P

AGRN6/GPIO/ABLU4/TXOC-_8b/TXO3-_10b/BG2N

AGRN5/GPIO/ABLU3/TXO2+_8b/TXOC+_10b/BG1P

AGRN4/GPIO/ABLU2/TXO2-_8b/TXOC-_10b/BG1N

AGRN3/GPIO/AGRN7/TXO1+_8b/TXO2+_10b/BR3P

AGRN2/GPIO/AGRN6/TXO1-_8b/TXO2-_10b/BR3N

AGRN1/GPIO/AGRN5/TXO0+_8b/TXO1+_10b/BR2P

AGRN0/GPIO/AGRN4/TXO0-_8b/TXO1-_10b/BR2N

SD2/SPDIF2/TCON[8]/GPIO/IICSCL/PWM1/AR3N

SD1/SPDIF1/TCON[5]/GPIO/IRQ/IICSDA/AR2P

R515
100_0402_1%

1 2

SD0/SPDIF0/TCON[0][7]/GPIO/IrDA

WS/TCON[7][1]/GPIO/PWM1/BB3P
ABLU7/SCK/TCON[4][2]/GPIO/BB3N
ABLU6/MCK/TCON[5][9]/GPIO/BB2P

ABLU5/SD0/SPDIF0/TCON[13][3]/GPIO/BB2N

TCON[6][12]/GPIO/PWM3/BCLKN

ARED7/AGRN3/TXE3+_8b/TXO0+_10b/BR1P

ARED6/AGRN2/TXE3-_8b/TXO0-_10b/BR1N
ARED5/ARED7/TXEC+_8b/TXE4+_10b/AB3P
ARED4/ARED6/TXEC-_8b/TXE4+_10b/AB3N
ARED3/ARED5/TXE2+_8b/TXE3+_10b/AB2P

ARED2/ARED4/TXE2-_8b/TXE3-_10b/AB2N

ARED1/ARED3/TXE1+_8b/TXEC+_10b/AB1P

ARED0/ARED2/TXE1-_8b/TXEC-_10b/AB1N

DENA/TXE0+_8b/TXE2+_10b/ACLKP

DHS/TXE0-_8b/TXE2-_10b/ACLKN

DCLK/GPIO/PWM0/TXE1+_10b/AG3P

DVS/GPIO/PWM1/TXE1-_10b/AG3N

GPIO/PWM2/TXE0+_10b/AG2P

GPIO/PWM3/TCON[11][6]/TXE0-_10b/AG2N

GPIO/PWM4/TCON[12][3]/AG1P

SD3/ SPDIF3/TCON[10]/GPIO/PWM0/AR3P

SD0 / SPDIF0 / TCON[9] / GPIO / AR2N

SD0/SPDIF0/TCON[4]/GPIO/SPDIF1

SD1/ SPDIF1/TCON[9]/GPIO/WS

SD2/SPDIF2/TCON[1][11]/GPIO/IrDA/SCK

SD3/SPDIF3/TCON[13]/GPIO/VCLK/MCK

For Port1
For Port0

PGND

PGND

61

85

+AD_VDD

1

C547
10U_0603_6.3V6M

2

C524
1U_0402_6.3V6K

12

TCON[1][8]/PWM2/GPIO

VCCK

GPIO/PWM5/TCON[0]/AG1N

MCK/TCON[7]/GPIO/AR1P
SCK/TCON[3]/GPIO/AR1N

WS/TCON[6]/GPIO/SDT

SPI_SCLK/SeriesData

SI/MCU_SCLK

SO/SCSB

CEB/IRQB

GPIO/PWM5/SPDIF1

DDCSCL3/GPIO/AUX-CH_P1
DDCSDA3/GPIO/AUX-CH_N1
DDCSDA2/GPIO/AUX-CH_N0

DDCSCL2/GPIO/AUX-CH_P0

CEC/GPIO/PWM1/SPDIF2

VCCK

RESETB

Thermal pad

3

600mA

U23

1

SHDN

2

IN

3

OUT

4

SET

G9141P11U_SO8

+1.2VALW=1+R533/R535

63
64

S_AMP_PD#

65
66
67

PNL_STAT

68

HDMI_CABLE_DET#_D

69

S_DIS/UMA

70

VGA_IN_DET#_D

71

PNL_STAT2

72
73

TXE3+

74

TXE3-

75

TXEC+

76

TXEC-

77

TXE2+

78

TXE2-

79

TXE1+

80

TXE1-

81

TXE0+

82

TXE0-

83

TXO3+

86

TXO3-

87

TXOC+

88

TXOC-

89

TXO2+

90

TXO2-

91

TXO1+

92

TXO1-

93

TXO0+

94

TXO0-

95
96
97
98
99
100

S_BKOFF

101

S_INVT_PWM

102

LED1

103

LED2

104
105

FLASH_WP

108

I2C_INT_SCR_R

109
110

WP_PRO

111

HDCP_CLK

112

HDCP_DAT

113

HDMI_TV_HPD

114
115
116
117
118
119
120
121
122
123
124
125
126
127

XO

128

XI

129

S_CLK
SDIN
SDOUT

CE

HDMI_TV_SCLK_R
HDMI_TV_SDATA_R
S_HDMI_DATA_R
S_HDMI_CLK_R

S_RESETB

XO

XI

8

GND

7

GND

6

GND

5

GND

MP for S5 HDMI_IN no function.

+3V_SCA

+3VALW

R5184.7K_0402_5%

R5194.7K_0402_5%

R5204.7K_0402_5%

R5174.7K_0402_5%

R5164.7K_0402_5%

12

12

R10414.7K_0402_5%

R10404.7K_0402_5%

T207
T208

TXE3+ [35]
TXE3- [35]
TXEC+ [35]
TXEC- [35]
TXE2+ [35]
TXE2- [35]
TXE1+ [35]
TXE1- [35]
TXE0+ [35]
TXE0- [35]
TXO3+ [35]
TXO3- [35]
TXOC+ [35]
TXOC- [35]
TXO2+ [35]
TXO2- [35]
TXO1+ [35]
TXO1- [35]
TXO0+ [35]
TXO0- [35]

T168
T169

R534 0_0402_5%@

1 2

R536 0_0402_5%@

1 2

R537 0_0402_5%@

1 2

HDMI_TV_HPD [37]

R538 4.7K_0402_5%

1 2

R541 75_0402_1%
R543 75_0402_1%

R544 0_0402_5%

1 2

R546 0_0402_5%

1 2

T172

@

12

12

12

D9 RB751V40_SC76-2

12
12

D37 RB751V40_SC76-2

LVDS

R532 4.7K_0402_5%

1 2

+1.2V_SCA

+3V_SCA

12

C542

1 2

change to 75 ohm for HDCP protect.

0.1U_0402_16V4Z

2

R1045

@

4.7K_0402_5%

CE
SDOUT
FLASH_WP

4.7K_0402_5%

12

12

R10424.7K_0402_5%

DVT add Pull high for PNL_STAT,
HDMI_CABLE_DET

To AMP SPK Enable pin

VGA_IN_DET# [4 0,49]
PNL_STAT2 [49]

+1.2V_SCA

C536

1

0.1U_0402_16V4Z

2

+3V_SCA

S_INVT_PWM [35]

I2C_INT_SCR [49]

EC_SMB_CK1 [49]
EC_SMB_DA1 [49]

HDMI_TV_SCLK [37]
HDMI_TV_SDATA [37]
S_HDMI_DATA [36]
S_HDMI_CLK [36]

R547

1

4.7K_0402_5%

C543

@

10U_0603_6.3V6M

2

close to U55( Scaler)

C545 22P_0402_50V8J

12

12

R552
1M_0402_5%

@

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

C548 22P_0402_50V8J

Compal Secret Data

Deciphered Date

R550

560_0402_5%

1 2

Y4
27MHZ_16PF_X5H027000FG1H

2 1

2

1

C523

0.1U_0402_16V4Z

8

VCC

7
6

CLK

5

DI(IO0)

C528

10PF_0402_50V9

For EMI

R513

+3V_SCA

12

12

12

R1046

@

4.7K_0402_5%
R508 22_0402_5%

R509 22_0402_5%
R510 0_0402_5%

1 2
1 2
1 2

12

R514

4.7K_0402_5%

U24

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25X10BVSNIG_SO8

HOLD#(IO3)

FOR Scalar Firmware Code

HDMI_STAT [49]
HP_DET# [47,49]
S_AMP_PD# [49]

PNL_STAT [47,48,49]

HDMI_CABLE_DET# [37,49]

HDMI_STAT
High: OSD OFF
Low : OSD ON

0.1U_0402_16V4Z

1

A0

2

A1

3

A2

4

GND

AT24C16AN-10SI-2.7_SO8

+3VS

C535

1 2

VCC

SDA

S_DIS/UMA

PVT for DIS/UMA FW control.
Mode

PC
HDMI
VGA

+3V_SCA

U26

8
7

WP

6

SCL

5

R525 10K_0402_5%
R527 10K_0402_5%

PNL_STAT

+3V_SCA

MP change from 0ohm for EMI

12

R526

4.7K_0402_5%
R528 47_0402_5%

1 2
1 2

1 2

FOR OSD/HDCP Parameter Value

R1053

4.7K_0402_5%

1 2

HDMI Port0 HPD

1

C541

@

0.1U_0402_16V4Z

2

HDMI-IN
PCH

12

+3V_SCA

XO

XI

S_BKOFF

Title

Size Document Number Rev

Date: Sheet

HDMI_HPD_LS [36]

+3V_SCA

12

R1073

4.7K_0402_5%

SSM3K7002B F 1N SC59-3

+3V_SCA

12

R548

4.7K_0402_5%

S_BKOFF#

13

D

Q31

2

G

S

Compal Electronics, Inc.

Scaler RTD2472/82D

PCA70 LA-7521P M/B

1

+3V_SCA

1

2

1 2
1 2

R511 22_0402_5%

1

R512 22_0402_5%

@

2

DIS@

12

+3V_SCA

UMA@

12

PNL_STAT2
0
1
0

R529 0_0402_5%

R530 0_0402_5%

34 64Tuesday, April 12, 2011

C1055

1

@

0.1U_0402_16V4Z

2

S_CLKS_CLK_R
SDIN

0
0
1

WP_PRO

EESCL

EESDA

S_BKOFF# [ 49]

of

0.1

5

TXEC+[34]

TXEC-[34]

TXE0+[34]

TXE0-[34]

TXE1+[34]

TXE1-[34]

D D

C C

TXE2+[34]

TXE2-[34]

TXE3+[34]

TXE3-[34]

TXOC+[34]

TXOC-[34]

TXO0+[34]

TXO0-[34]

TXO1+[34]

TXO1-[34]

TXO2+[34]

TXO2-[34]

TXO3+[34]

TXO3-[34]

TXEC+
TXEC-

TXE0+
TXE0-

TXE1+
TXE1-

TXE2+
TXE2-

TXE3+
TXE3-

TXOC+
TXOC-

TXO0+
TXO0-

TXO1+
TXO1-

TXO2+
TXO2-

TXO3+
TXO3-

4

+LCDVDD

C553

0.1U_0402_16V4Z
680P_0402_50V7K

For Scaler LVDS Conn.

JLVDS1

2

TXO0+
TXO1+
TXO2+
TXOC­TXO3-

TXE1+
TXE2­TXEC­TXE3-

1

1

C552

2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

ACES_50255-03001-001

CONN@

11
13
15
17
19
21
23
25
27
29

31

3

1

1

3

3

5

5

7

7

9

9

11
13
15
17
19
21
23
25
27
29

31

TXO0­TXO1­TXO2­TXOC+
TXO3+

TXE0+TXE0­TXE1­TXE2+
TXEC+
TXE3+

1

C554

0.1U_0402_16V4Z

2

VGA

+LCDVDD

EC

EC_ENVDD[49]

VGA_ENVDD[22]

2

100_0805_5%

2N7002KDWH_SOT363-6

1 2

R567 0_0402_5%

1 2

R1044 0_0402_5%

@

+LCDVDD +5VALW

12

R555

61

Q32A

2

5

12

2N7002KDWH_SOT363-6

R570
100K_0402_5%

1

R556
1M_0402_5%

1 2

PVT change from 100k to 1.5M for EA.

R563

1 2

1.5M_0402_5%

34

Q32B

2

C549
1000P_0402_50V7K

1

4.7U_0603_10V6K

+5VALW

G

2

1 3

1

C550

2

120mil

S

PMV65XP 1P SOT23 TMOS
Q33

D

120mil

+LCDVDD

1

C551

0.1U_0402_16V4Z

2

B B

Converter

INVPWR_B+ B+

FBMA-L11-201209-221LMA30T_0805

12

C556

R586 0_0402_5%

BKOFF#[4 9]

EC

Scaler

A A

VGA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

S_INVT_PWM[34]

EC

INVT_PWM[49]

VGA_LCD_PWM[22]

2010/10/1 2011/11/01

3

1 2

R591 0_0402_5%

1 2

R594 0_0402_5%@

1 2

R1050 0_0402_5%@

1 2

Compal Secret Data

Deciphered Date

LCD_BKOFF#

12

R1049
100K_0402_5%

LCD_PWM

2

680P_0402_50V7K

C557

@

680P_0402_50V7K

Title

Size Document Number Re v

Custom

Date: Sheet

L30

1 2

463mA

LCD_PWM
LCD_BKOFF#

1

2

1

C555
680P_0402_50V7K

2

JCON1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

GND1

14

GND2

ACES_50224-01201-001

CONN@

Compal Electronics, Inc.

LVDS

PCA70 LA-7521P M/B

35 64Tuesday, April 12, 2011

1

0.1

of

A

B

C

D

E

F

G

H

1 1

2 2

DIS only

VGA_SHDMI_ETXC+[23]
VGA_SHDMI_ETXC-[23]

VGA_SHDMI_ETXD0+[23]
VGA_SHDMI_ETXD0-[23]

VGA_SHDMI_ETXD1+[23]
VGA_SHDMI_ETXD1-[23]

VGA_SHDMI_ETXD2+[23]
VGA_SHDMI_ETXD2-[23]

UMA only

VGA_SHDMI_ETXC+
VGA_SHDMI_ETXC-

VGA_SHDMI_ETXD0+
VGA_SHDMI_ETXD0-

VGA_SHDMI_ETXD1+
VGA_SHDMI_ETXD1-

VGA_SHDMI_ETXD2+
VGA_SHDMI_ETXD2-

C1556 0.1U_0402_10V7KDIS@

1 2

C1557 0.1U_0402_10V7KDIS@

1 2

C1558 0.1U_0402_10V7KDIS@

1 2

C1559 0.1U_0402_10V7KDIS@

1 2

C1560 0.1U_0402_10V7KDIS@

1 2

C1561 0.1U_0402_10V7KDIS@

1 2

C1562 0.1U_0402_10V7KDIS@

1 2

C1563 0.1U_0402_10V7KDIS@

1 2

HDMI_C_CLK+
HDMI_C_CLK-

HDMI_C_TX0+
HDMI_C_TX0-

HDMI_C_TX1+
HDMI_C_TX1-

HDMI_C_TX2+
HDMI_C_TX2-

HDMI_C_CLK+ [ 3 4 ]
HDMI_C_CLK- [34]

HDMI_C_TX0+ [34]

HDMI_C_TX0- [34]

HDMI_C_TX1+ [34]

HDMI_C_TX1- [34]

HDMI_C_TX2+ [34]

HDMI_C_TX2- [34]

INTEL use 680 Ohm for terminationn NV use 499 Ohm for terminationn

UMA@

PCH_HDMI_CLK+[16]
PCH_HDMI_CLK-[16]

PCH_HDMI_TX0+[16]
PCH_HDMI_TX0-[16]

PCH_HDMI_TX1+[16]
PCH_HDMI_TX1-[16]

PCH_HDMI_TX2+[16]
PCH_HDMI_TX2-[16]

PCH_HDMI_CLK+
PCH_HDMI_CLK-

PCH_HDMI_TX0+
PCH_HDMI_TX0-

PCH_HDMI_TX1+
PCH_HDMI_TX1-

PCH_HDMI_TX2+
PCH_HDMI_TX2-

C1564 0.1U_0402_10V7KUMA@

1 2

C1565 0.1U_0402_10V7KUMA@

1 2

C1566 0.1U_0402_10V7KUMA@

1 2

C1567 0.1U_0402_10V7KUMA@

1 2

C1568 0.1U_0402_10V7KUMA@

1 2

C1569 0.1U_0402_10V7KUMA@

1 2

C1570 0.1U_0402_10V7KUMA@

1 2

C1571 0.1U_0402_10V7KUMA@

1 2

HDMI_C_CLK+
HDMI_C_CLK-

HDMI_C_TX0+
HDMI_C_TX0-

HDMI_C_TX1+
HDMI_C_TX1-

HDMI_C_TX2+
HDMI_C_TX2-

R635 680_0402_5%

R636 680_0402_5%

UMA@

R637 680_0402_5%

UMA@

R638 680_0402_5%

UMA@

R639 680_0402_5%

UMA@

R640 680_0402_5%

UMA@

R642 680_0402_5%

UMA@

R643 680_0402_5%

UMA@

SSM3K7002BF 1N SC59-3

Q36

UMA@

+3VS

13

D

2

G

S

DIS@

R642
499_0402_5%

DIS@

R635
499_0402_5%

DIS@

R643
499_0402_5%

DIS@

R636
499_0402_5%

DIS@

R639
499_0402_5%

DIS@

R637
499_0402_5%

DIS@

R640
499_0402_5%

DIS@

R638
499_0402_5%

pull down for HDMI 1.3 standard, remove in PVT phase.

+3VS+3VS +5VS

12

12

R617

UMA@

2.2K_0402_5%

PCH_HDMI_DATA[16]

3 3

VGA_SHDMI_EDATA[23]

PCH_HDMI_CLK[1 6]

VGA_SHDMI_ECLK[23]

PCH_HDMI_DATA

PCH_HDMI_CLK

R618

UMA@

2.2K_0402_5%

R1580 0_0402_5%UMA@

1 2
1 2

R1581 0_0402_5%DIS@

R1582 0_0402_5%UMA@

1 2
1 2

R1583 0_0402_5%DIS@

5

4

R619

4.7K_0402_5%

2

61

Q35A
2N7002KDW_SOT363-6

3

Q35B
2N7002KDW_SOT363-6

1 2

1 2

R620

4.7K_0402_5%

S_HDMI_DATA

S_HDMI_CLK

S_HDMI_DATA [34]

S_HDMI_CLK [34]

DDPC_HDP[16]

VGA_SHDMI_HPD[22]

4 4

A

B

C

VGA_SHDMI_HPD

UMA@

DIS@

1 2

R641
0_0402_5%

1 2

R1584
0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

D

2010/10/1 2011/11/01

E

HDMI_HPD_LSDDPC_HDP

Compal Secret Data

Deciphered Date

HDMI_HPD_LS [34]

F

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

HDMI Level Shift Scaler

PCA70 LA-7521P M/B

G

of

36 64Tuesday, April 12, 2011

H

0.1

A

B

C

D

E

1 1

R673
0_0402_5%

HDMIIN@

1

4

1

4

1

4

1

4

1 2

1

4

1 2

R677
0_0402_5%

HDMIIN@

1 2

1

4

1 2

R681
0_0402_5%

HDMIIN@

1 2

1

4

1 2

R684
0_0402_5%

HDMIIN@

1 2

1

4

1 2

R685
0_0402_5%

HDMIIN@

L34

WCM-2012-900T_0805

@

2

2

3

3

R676
0_0402_5%

HDMIIN@

L35

WCM-2012-900T_0805

@

2

2

3

3

R678
0_0402_5%

HDMIIN@

L36

WCM-2012-900T_0805

@

2

2

3

3

R683
0_0402_5%

HDMIIN@

L37

WCM-2012-900T_0805

@

2

2

3

3

HDMI_CK+[34]

HDMI_CK-[34]

HDMI_D0+[34]

2 2

HDMI_D0-[34]

HDMI_D1+[34]

HDMI_D1-[34]

HDMI_D2+[34]

3 3

HDMI_D2-[34]

HDMI_R_CK+

HDMI_R_CK-

HDMI_R_D0+

HDMI_R_D0-

HDMI_R_D1+

HDMI_R_D1-

HDMI_R_D2+

HDMI_R_D2-

HDMI_R_CK­HDMI_R_CK+
HDMI_R_D0­HDMI_R_D0+

HDMI_R_D1­HDMI_R_D1+
HDMI_R_D2­HDMI_R_D2+

D18

1

1

2

2

4

4
5

3

3

8

YSCLAMP0524P_SLP2510P8-10-9

HDMIIN@

D19

1

1

2

2

4

4
5

3

3

8

YSCLAMP0524P_SLP2510P8-10-9

HDMIIN@

10
9
7
65

10
9
7
65

HDMI_R_CK-

9

HDMI_R_CK+

8

HDMI_R_D0-

7

HDMI_R_D0+

6

HDMI_R_D1-

9

HDMI_R_D1+

8

HDMI_R_D2-

7

HDMI_R_D2+

6

HDMI_TV_HPD[34]

+HDMI_EDID_5V

R679

4.7K_0402_5%

HDMIIN@

HDMI_TV_SDATA[34]
HDMI_TV_SCLK[34]

PJDLC05C_SOT23-3

HDMIIN@

(Cj=5pF)

PJDLC05C_SOT23-3

HDMIIN@

HDMI_TV_HPD

R680

4.7K_0402_5%

HDMIIN@

D20

D21

+HDMI_EDID_5V

12

R674
1K_0402_1%

HDMIIN@

1

C580

0.1U_0402_16V4Z

HDMIIN@

2

2

3

1

HDMI_TV_HPD

HDMI_CABLE_DET#

2

3

1

+5VALW

+HDMI_5V_IN

HDMI_TV_SDATA
HDMI_TV_SCLK
HDMI_TV_HPD

HDMI_R_CK­HDMI_R_CK+
HDMI_R_D0­HDMI_R_D0+
HDMI_R_D1­HDMI_R_D1+
HDMI_R_D2­HDMI_R_D2+

D15
RB491D_SOT23

HDMIIN@

2 1

+HDMI_EDID_5V

1

C581

0.1U_0402_16V4Z

HDMIIN@

2

F2

1.1A_6V_SMD1812P110TF

HDMIIN@

HDMI-in Connector

JHDMI1

18

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

DDC/CEC_GND

SUYIN_100042GR019M12RZR

CONN@

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

13
14

2
5
8
11
20
21
22
23
17

HDMI_CABLE_DET#

D16
RB491D_SOT23

HDMIIN@

21

21

+HDMI_5V_IN

DVT Scaler request

HDMI_CABLE_DET# [34,49]

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

HDMI-IN

PCA70 LA-7521P M/B

37 64Tuesday, April 12, 2011

E

0.1

of

A

B

C

D

E

F

G

H

DIS only

C1572 0.1U_0402_10V7KHDMIOD@

VGA_HDMI_ETXD2+[23]
VGA_HDMI_ETXD2-[23]

VGA_HDMI_ETXD1+[23]
VGA_HDMI_ETXD1-[23]

1 1

VGA_HDMI_ETXC+[23]
VGA_HDMI_ETXC-[23]

VGA_HDMI_ETXD0+[23]
VGA_HDMI_ETXD0-[23]

1 2

C1573 0.1U_0402_10V7KHDMIOD@

1 2

C1574 0.1U_0402_10V7KHDMIOD@

1 2

C1575 0.1U_0402_10V7KHDMIOD@

1 2

C1576 0.1U_0402_10V7KHDMIOD@

1 2

C1577 0.1U_0402_10V7KHDMIOD@

1 2

C1578 0.1U_0402_10V7KHDMIOD@

1 2

C1579 0.1U_0402_10V7KHDMIOD@

1 2

HDMIOUT_TX2+
HDMIOUT_TX2-

HDMIOUT_TX1+
HDMIOUT_TX1-

HDMIOUT_CLK+
HDMIOUT_CLK-

HDMIOUT_TX0+
HDMIOUT_TX0-

HDMIOUT_TX2+ [39]
HDMIOUT_TX2- [39]

HDMIOUT_TX1+ [39]
HDMIOUT_TX1- [39]

HDMIOUT_CLK+ [39]
HDMIOUT_CLK- [39]

HDMIOUT_TX0+ [39]
HDMIOUT_TX0- [39]

NV use 499 Ohm for terminationn

UMA only

PCH_HDMIOUT_TX2+[16]
PCH_HDMIOUT_TX2-[16]

PCH_HDMIOUT_TX1+[16]
PCH_HDMIOUT_TX1-[16]

PCH_HDMIOUT_CLK+[16]
PCH_HDMIOUT_CLK-[16]

PCH_HDMIOUT_TX0+[16]
PCH_HDMIOUT_TX0-[16]

2 2

PCH_HDMIOUT_DATA[16]

VGA_HDMI_EDATA[23]

PCH_HDMIOUT_CLK[16]

VGA_HDMI_ECLK[23]

PCH_HDMIOUT_TX2+
PCH_HDMIOUT_TX2-

PCH_HDMIOUT_TX1+
PCH_HDMIOUT_TX1-

PCH_HDMIOUT_CLK+
PCH_HDMIOUT_CLK-

PCH_HDMIOUT_TX0+
PCH_HDMIOUT_TX0-

R1486

2.2K_0402_5%

HDMIOU@

PCH_HDMIOUT_DATA

PCH_HDMIOUT_CLK

+3VS

12

C1580 0.1U_0402_10V7KHDMIOU@
C1581 0.1U_0402_10V7KHDMIOU@

C1582 0.1U_0402_10V7KHDMIOU@
C1583 0.1U_0402_10V7KHDMIOU@

C1584 0.1U_0402_10V7KHDMIOU@
C1585 0.1U_0402_10V7KHDMIOU@

C1586 0.1U_0402_10V7KHDMIOU@
C1587 0.1U_0402_10V7KHDMIOU@

12

R1487

2.2K_0402_5%

HDMIOU@

R1494 0_0402_5%HDMIOU@
R1498 0_0402_5%HDMIOD@

R1508 0_0402_5%HDMIOU@
R1512 0_0402_5%HDMIOD@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

4

INTEL use 680 Ohm for terminationn

HDMIOUT_TX2+
HDMIOUT_TX2-

HDMIOUT_TX1+
HDMIOUT_TX1-

HDMIOUT_CLK+
HDMIOUT_CLK-

HDMIOUT_TX0+
HDMIOUT_TX0-

+3VS +HDMIOUT_EDID_5V

2

61

Q94A
2N7002KDW_SOT363-6

5

HDMIO@

3

Q94B
2N7002KDW_SOT363-6

HDMIO@

R1587 680_0402_5%

HDMIOU@
HDMIOU@

R1588 680_0402_5%
R1589 680_0402_5%

HDMIOU@
HDMIOU@

R1590 680_0402_5%
R1591 680_0402_5%

HDMIOU@
HDMIOU@

R1592 680_0402_5%
R1593 680_0402_5%

HDMIOU@
HDMIOU@

R1594 680_0402_5%

SSM3K7002BF 1N SC59-3

HDMIO@

pull down for HDMI 1.3 standard, remove in PVT phase.

12

12

R1463

2.2K_0402_5%

HDMIO@

R1464

2.2K_0402_5%

HDMIO@

HDMIOUT_SDATA

HDMIOUT_SCLK

+3VS

13

D

Q93

2

G

S

HDMIOUT_SDATA [39]

HDMIOUT_SCLK [3 9 ]

HDMIOD@

R1593
499_0402_5%

HDMIOD@

R1587
499_0402_5%

HDMIOD@

R1594
499_0402_5%

HDMIOD@

R1588
499_0402_5%

HDMIOD@

R1591
499_0402_5%

HDMIOD@

R1589
499_0402_5%

HDMIOD@

R1592
499_0402_5%

HDMIOD@

R1590
499_0402_5%

3 3

UMA onlyDIS only

+3VGS

C

Q95

MMBT3904_SOT23-3

HDMIOD@

VGA_HDMIOUT_HPD[22]

4 4

A

B

B

E

3 1

R1597
10K_0402_5%

HDMIOD@

1 2

R1595

1 2

2

100K_0402_5%

HDMIOD@

C

HDMIOUT_HPD_R

2

G

1 3

D

S

Q96
SSM3K7002F_SC59-3

HDMIOD@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

D

2010/10/1 2011/11/01

E

DDPD_HDP[16]DGPU_HPD_INT#[18]

Compal Secret Data

Deciphered Date

F

R1596

1M_0402_5%

HDMIOU@

SSM3K7002F_SC59-3

HDMIOU@

12

Q97

+3VS

G

2

HDMIOUT_HPD_R

13

D

S

R1598

100K_0402_5%

HDMIOU@

Title

Size Document Number Re v

Custom

Date: Sheet

1

12

C1529

HDMIOU@

2

220P_0402_25V8J

Compal Electronics, Inc.

PCA70 LA-7521P M/B

G

HDMIOUT_HPD_R [39]

HDMI-OUT Level Shift

0.1

of

38 64Tuesday, April 12, 2011

H

A

B

C

D

E

D55
RB491D_SOT23

1 1

2 2

3 3

4 4

HDMIOUT_TX2+[38]
HDMIOUT_TX2-[38]

HDMIOUT_TX1+[38]
HDMIOUT_TX1-[38]

HDMIOUT_CLK+[38]
HDMIOUT_CLK-[3 8]

HDMIOUT_TX0+[38]
HDMIOUT_TX0-[38]

HDMIOUT_CLK+

HDMIOUT_CLK-

HDMIOUT_TX0+

HDMIOUT_TX0-

HDMIOUT_TX1+

HDMIOUT_TX1-

HDMIOUT_TX2+

HDMIOUT_TX2-

1

1

4

4

1

1

4

4

1

1

4

4

1

1

4

4

R1465
0_0402_5%

@

1 2

1 2

R1467
0_0402_5%

@

1 2

1 2

R1469
0_0402_5%

@

1 2

1 2

R1471
0_0402_5%

@

1 2

1 2

R1472
0_0402_5%

@

HDMIOUT_TX2+
HDMIOUT_TX2-

HDMIOUT_TX1+
HDMIOUT_TX1-

HDMIOUT_CLK+
HDMIOUT_CLK-

HDMIOUT_TX0+
HDMIOUT_TX0-

L92

WCM-2012-900T_0805

HDMIO@

2

2

3

3

R1466
0_0402_5%

@

L93

WCM-2012-900T_0805

HDMIO@

2

2

3

3

R1468
0_0402_5%

@

L94

WCM-2012-900T_0805

HDMIO@

2

2

3

3

R1470
0_0402_5%

@

L95

WCM-2012-900T_0805

HDMIO@

2

2

3

3

HDMIOUT_R_CK+

HDMIOUT_R_CK-

HDMIOUT_R_D0+

HDMIOUT_R_D0-

HDMIOUT_R_D1+

HDMIOUT_R_D1-

HDMIOUT_R_D2+

HDMIOUT_R_D2-

+5VS

HDMIOUT_SDATA[38]

HDMIOUT_SCLK[38]

HDMIOUT_HPD_R[38]

PJDLC05C_SOT23-3

(Cj=5pF)

HDMIOUT_R_CK-

HDMIOUT_R_CK+

HDMIOUT_R_D0­HDMIOUT_R_D0+

HDMIOUT_R_D1­HDMIOUT_R_D1+
HDMIOUT_R_D2­HDMIOUT_R_D2+

1
2
4
5
3

1
2
4
5
3

HDMIO@

2 1

1.1A_6V_SMD1812P110TF

2

3

D56

HDMIO@

1

D57

1
2
4

3

8

YSCLAMP0524P_SLP2510P8-10-9

HDMIO@

D59

1
2
4

3

8

YSCLAMP0524P_SLP2510P8-10-9

HDMIO@

10

9

HDMIOUT_R_CK+

9

8

7

7

HDMIOUT_R_D0+

65

6

10

9

9

8

7

7

65

6

HDMIOUT_R_CK-

HDMIOUT_R_D0-

HDMIOUT_R_D1­HDMIOUT_R_D1+
HDMIOUT_R_D2­HDMIOUT_R_D2+

+HDMIOUT_EDID_5V

F1

21

HDMIO@

+HDMIOUT_EDID_5V

HDMIOUT_SDATA
HDMIOUT_SCLK
HDMIOUT_HPD_R

HDMIOUT_R_CK-

HDMIOUT_R_CK+

HDMIOUT_R_D0­HDMIOUT_R_D0+
HDMIOUT_R_D1­HDMIOUT_R_D1+
HDMIOUT_R_D2­HDMIOUT_R_D2+

1

C1434

0.1U_0402_16V4Z

HDMIO@

2

HDMI-OUT Connector

JHDMI2

18

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

DDC/CEC_GND

SUYIN_100042GR019M12RZR

CONN@

PJDLC05C_SOT23-3

D58

HDMIO@

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

HDMIOUT_HPD_R

2

3

1

13
14

2
5
8
11
20
21
22
23
17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

HDMI-OUT

PCA70 LA-7521P M/B

39 64Tuesday, April 12, 2011

E

0.1

of

A

R647 4.7K_0402_5%

T256 PAD

3

1

+VGA_5V

1

C574

0.1U_0402_16V4Z

2

1 2
1 2

R648 4.7K_0402_5%

2

D10
PSOT24C_SOT23-3

VGAIN@

+VGA_5V

1 1

2 2

JCRT1

16

G

17

G

CH_13-12201527CP

CONN@

+VGA_5V_IN

D13

VGAIN@

PSOT24C_SOT23-3

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

+5VALW

2

3

1

VGA_DDC_DAT_IN

VGA_DDC_CLK_IN

1

C569

VGAIN@

100P_0402_50V8J

2

D11

RB491D_SOT23

2 1

2 1

D12

RB491D_SOT23

NC_CRT

RED_IN

GREEN_IN

JVGA_HS

BLUE_IN

JVGA_VS

VGA_IN_DET# [34,49]

VGAIN@

VGAIN@

Scaler FW update

R1614 4.7K_0402_5%@

+3VS

SCFW_UPDATE#[49]

3 3

1 2

R1615 0_0402_5%

Q107

@

SSM3K7002BF 1N SC59-3

12

13

D

2

G

S

PM_SMBDATA[11,12,14]

PM_SMBCLK[11,12,14]

B

VGA_DDC_CLK_IN
VGA_DDC_DAT_IN

1 2

R653 100_0402_1%

1 2

R650 100_0402_1%

VGAIN@

R1616 100K_0402_5%

2

Q100A 2N7002KDWH_SOT363-6

5

Q100B 2N7002KDWH_SOT363-6

34

CRT_DDC_DAT_IN [34]

CRT_DDC_CLK_IN [34]

12

CRT_DDC_DAT_IN

61

CRT_DDC_CLK_IN

+3VS

+3VS

+3VS

1 2

C565

0.1U_0402_25V6

VGAIN@

GREEN_IN

1 2

C571

0.1U_0402_25V6

VGAIN@

BLUE_IN

1 2

C576

0.1U_0402_25V6

VGAIN@

C

U28

2
3

BAV99_SOT23-3

VGAIN@

U29

2
3

BAV99_SOT23-3

VGAIN@

U30

2
3

BAV99_SOT23-3

VGAIN@

1

1

1

JVGA_HS

JVGA_VS

L31

VGAIN@

1 2

FCM1608KF-110T05 0603

VGAIN@

75_0402_1%

L32

VGAIN@

1 2

FCM1608KF-110T05 0603

VGAIN@

75_0402_1%

L33

VGAIN@

1 2

FCM1608KF-110T05 0603

VGAIN@

75_0402_1%

2

3

PSOT24C_SOT23-3

1

D

R645

VGAIN@

12

VGAIN@

VGAIN@

12

R670
2K_0402_5%

100_0603_1%

1 2

R649
100_0603_1%

1 2

R651

VGAIN@

1K_0402_5%

1 2

R654

VGAIN@

100_0603_1%

1 2

R656

VGAIN@

100_0603_1%

1 2

R657

VGAIN@

100_0603_1%

1 2

R659

VGAIN@

100_0603_1%

1 2

100_0402_1%

1 2

100_0402_1%

1 2

VGAIN@

RED_IN_B

12

R646

R655

R658

D14

1

C564
5P_0402_50V8C

2

GREEN_IN_B GREEN_IN_R

12

1

C570
5P_0402_50V8C

2

BLUE_IN_B

12

1

C575
5P_0402_50V8C

2

R669

VGAIN@

2K_0402_5%

VGAIN@

VGAIN@

VGAIN@

VGA_GNDG

BLUE_IN_R

VGA_GNDB

R666

VGAIN@

VGAIN@

R668

C578

22P_0402_50V8J

RED_IN_RRED_IN

VGA_GNDR

VGA_SOG_R

VGAIN@

C563

VGAIN@

0.047U_0402_16V7K

1 2

C566

VGAIN@

0.047U_0402_16V7K

1 2

C567

VGAIN@

0.022U_0402_25V7K

1 2

C568

VGAIN@

0.047U_0402_16V7K

1 2

C572

VGAIN@

0.047U_0402_16V7K

1 2

C573

VGAIN@

0.047U_0402_16V7K

1 2

C577

VGAIN@

0.047U_0402_16V7K

1 2

1

1

C579

22P_0402_50V8J

2

2

12

R652

@

1M_0402_5%

VGA_GREEN_IN [34]

VGA_GND_GREEN [34]

VGA_BLUE_IN [ 34]

VGA_GND_BLUE [3 4]

VGA_HSYNC_IN [34]

VGA_VSYNC_IIN [34]

VGAIN@

E

VGA_RED_IN [34]

VGA_GND_RED [34]

VGA_SOG [34]

+USB_VCCC

1 2

+3VALW

+5VALW +USB_VCCC

2.5A

R1414

100K_0402_5%

1 2

USB1_EN#

4 4

U83

1

GND

2

VIN
VIN3VOUT

4

EN

1

AP2301SG-13 SO 8P

C1396

4.7U_0603_10V6K

2

+USB_VCCC

150U_B2_6.3VM_R35M

1

+

2

C1394

VOUT
VOUT

FLG

1

2

8
7
6
5

C1395

0.1U_0402_25V6

W=60mils

12

C1393 1000P_0402_50V7K

USB_OC#2 [17,41]USB1_EN#[41,49]

1

C1397

4.7U_0603_10V6K

2

For EMI

USB20_N4[17]

USB20_P4[17]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Place closely JUSB5.1

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

R695 0_0402_5% @
L41

1

1

4

4

WCM-2012-900T_0805

1 2

R696 0_0402_5% @

2

2

3

3

2010/10/1 2011/11/01

C

USB20_N4_R
USB20_P4_R

2

3

D25
PJDLC05C_SOT23-3

1

Compal Secret Data

Deciphered Date

SATA_PRX_C_DTX_P4[13]
SATA_PRX_C_DTX_N4[13]

SATA_PTX_C_DRX_P4[13]
SATA_PTX_C_DRX_N4[13]

D

C1399 0.01U_0402_25V7K
C1398 0.01U_0402_25V7K

Title

Size Document Number Re v

Date: Sheet

SATA_PRX_DTX_P4

1 2

SATA_PRX_DTX_N4

1 2

Compal Electronics, Inc.

CRT-IN Connector

Custom

PCA70 LA-7521P M/B

JSATA1

10

B+

1

VBUS

9

B-

2

D-

4

GND

3

D+

6

A+

5

GND

7

A-

TAIWI_EU091-117CRL-TW

CONN@

40 64Tuesday, April 12, 2011

E

GND
GND
GND
GND
GND
GND

8
11
12
13
14
15

0.1

of

5

4

3

2

1

SATA HDD Conn. SATA ODD Conn

+5VS

D D

C C

+12VS

JHDD1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

GND1

14

GND2

ACES_50224-01201-001

CONN@

USB1_EN#[40,49]

Place closely JHDD SATA CONN.

1.2A

1

C582
10U_0805_10V4Z

2

1

C586
10U_0805_25V6K

2

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

1

C583

0.1U_0402_16V4Z

2

1

C587

0.1U_0402_25V6

2

+12VS

+3VALW

R688
100K_0402_5%

1 2

USB1_EN#

1

C584

0.1U_0402_16V4Z

2

1

C588

0.1U_0402_25V6

2

C591 0.01U_0402_25V7K

1 2

C593 0.01U_0402_25V7K

1 2

Close to JHDD

+5VALW

2.5A

U34

1

GND

VOUT

2

VOUT

VIN
VIN3VOUT

4

FLG

EN

1

AP2301SG-13 SO 8P

C1074

4.7U_0603_10V6K

2

1

C585

0.1U_0402_16V4Z

2

1

C589

0.1U_0402_25V6

2

SATA_PTX_C_DRX_P0 [13]
SATA_PTX_C_DRX_N0 [13]

SATA_PRX_C_DTX_N0 [13]

SATA_PRX_C_DTX_P0 [13]

W=60mils

+USB_VCCB

8

C603 1000P_0402_50V7K

7
6
5

1

C606

4.7U_0603_10V6K

2

For EMI

12

USB_OC#2 [17,40]

USB1_EN#

+5VALW

1

C1073

4.7U_0603_10V6K

2

+5VS

JODD1

GND1

GND2

ACES_50224-01001-001

CONN@

2.5A

U33

1

GND

VOUT

2

VOUT

VIN
VIN3VOUT

4

FLG

EN

AP2301SG-13 SO 8P

1

C594
10U_0805_10V4Z

2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11
12

+USB_VCCA

8
7
6
5

1.1A

W=60mils

Place components closely ODD CONN.

1

C595
10U_0805_10V4Z

2

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

+5VS+5VS

For EMI

12

C599 1000P_0402_50V7K

1

2

USB_OC#4 [17]

C602

4.7U_0603_10V6K

1

C596
1U_0603_10V6K

2

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

C5900.01U_0402_25V7K

1 2
1 2

C5920.01U_0402_25V7K

1

@

2

Near CONN side.

C597

0.1U_0402_16V4Z

SATA_PTX_C_DRX_P1 [13]

SATA_PTX_C_DRX_N1 [13]

SATA_PRX_C_DTX_N1 [13]
SATA_PRX_C_DTX_P1 [13]

1

C598

0.1U_0402_16V4Z

2

R689 0_0402_5%

@

1 2

L38

USB20_N5[17]

B B

A A

USB20_P5[17]

1

1

4

4

WCM-2012-900T_0805

@

1 2

R690 0_0402_5%

USB20_N5_R

2

2

USB20_P5_R

3

3

2

3

PJDLC05C_SOT23-3

1

+USB_VCCB

D22

JUSB6

1

VCC

2

D-

3

D+

GND

4

GND

GND

ACON_UAS2C-4K1921

CONN@

5
6

150U_B2_6.3VM_R35M

Place closely JUSB3.1

+USB_VCCB

1

+

C604

2

1

C1067

0.1U_0402_25V6

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

Place C669,C670 closely USB CONN.

USB20_N9[17]

USB20_P9[17]

USB20_N8[17]

USB20_P8[17]

2010/10/1 2011/11/01

3

R691 0_0402_5%

@

1 2

L39

1

1

4

4

WCM-2012-900T_0805

@

1 2

R693 0_0402_5%

R692 0_0402_5%

@

1 2

L40

1

1

4

4

WCM-2012-900T_0805

@

1 2

R694 0_0402_5%

Compal Secret Data

Deciphered Date

+USB_VCCA

USB20_N9_R

2

2

USB20_P9_R

3

3

2

3

D23

PJDLC05C_SOT23-3

1

+USB_VCCA

USB20_N8_R

2

2

USB20_P8_R

3

3

2

2

3

PJDLC05C_SOT23-3

1

JUSB3

1

VCC

2

D-

3

D+

4

GND

ACON_UAS2C-4K1921

CONN@

JUSB4

1

VCC

2

D-

3

D+

4

GND

ACON_UAS2C-4K1921

CONN@

D24

Title

Size Document Number Re v

Date: Sheet

5

GND

6

GND

5

GND

6

GND

Compal Electronics, Inc.

SATA-HDD/ODD/USB

PCA70 LA-7521P M/B

+USB_VCCA

1

1

+

2

C1068

0.1U_0402_25V6

2

C600

150U_B2_6.3VM_R35M

Place closely JUSB6.1

+USB_VCCA

1

1

+

2

C1070

0.1U_0402_25V6

2

C601

150U_B2_6.3VM_R35M

Place closely JUSB4.1

41 64Tuesday, April 12, 2011

1

0.1

of

+3VS

0.1U_0402_16V4Z

1

C609

C610

2

0.01U_0402_25V7K

+1.5VS +1.5VS_WLAN

1 2

R714

@

0_0603_5%

For AW-NE139H

0.1U_0402_16V4Z

1

@

C613

2

0.01U_0402_25V7K

B-CAS Circuit

BCPWON

TV@

10K_0402_5%

40 mils

1

C611

2

4.7U_0603_10V6K

@

C614

TV@

100K_0402_5%

12

R723

For SED

1

2

1

1

@

C615

2

2

4.7U_0603_10V6K

+5VALW

12

R721

13

D

Q39

2

G

S

SSM3K7002BF 1N SC59-3

TV@

12

C612
47P_0402_50V8J

@

PCIE_WAKE#[15,43,45]

For SED

12

C616

47P_0402_50V8J

@

R722

47K_0402_5%

TV@

0.01U_0402_25V7K

Slot 1 Half PCIe Mini Card-WLAN/ WiMax

R698 0_0603_5%@

JWLAN1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

BELLW_80003-1021

1 2

FBMA-L11-201209-221LMA30T_0805

1

1

C629

TV@

1U_0402_6.3V6K

2

2

PCIE_PRX_WLANTX_N3[14]
PCIE_PRX_WLANTX_P3[14]

TV@

1

C619

0.1U_0402_16V7K

2

12

1

TV@

C627

2

R724

TV@

2.2K_0402_5%

T182PAD @
T183PAD @

CLKREQ_WLAN#[14]

CLK_WLAN#[14]
CLK_WLAN[14]

PCIE_PTX_C_WLANRX_N3[14]
PCIE_PTX_C_WLANRX_P3[14]

WLAN/ WiFi

+3VS

E51_TXD[49]

E51_RXD[49]

Debug card using

+5VS

Inrush current = 0A

S

G

Q38

2

AO3413_SOT23-3

D

1 3

12

1

C630

4.7U_0603_6.3V6K

2

1 2

1 2

R709 0_0603_5%

R716 0_0402_5%@

1 2
1 2

R717 0_0402_5%@

TV@

+5VS_L_BCAS

0.1U_0402_16V4Z

TV@

BT_COEX1
BT_COEX2

+5VS_BCAS +5VS_L_BCAS

C628

TV@

GND2

CONN@

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

L42

+1.5VS_WLAN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

TV@

+3VS

PLT_A_RST#

WL_OFF# [49]
PLT_A_RST# [17,43,44]

+3VS

WLAN_LED# [49]

1 2

R1098
100K_0402_5%

+3VS

Debug card using

Add BCCDET pull down

BCCDET

R718 470_0402_5%

Mini Card Slot 2---TV tuner Currecnt: 3.3 : 1000mA, 1.5: 500mA

C607 39P_0402_50V8J

JMINI1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

BELLW_80003-8041

1

2

CONN@

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

SIM_VCC
SIM_DATA
SIM_CLK
SIM_RESET
COMMON

R702
R704

PLT_A_RST#

+3VS_MINI_R

USB20_N10_R
USB20_P10_R

CPLGP1
TMPTU1_SXP_R

C623

0.01U_0402_16V7K

1 2
1 2

+1.5VS

1

2

@

1 2

1 2
1 2

1 2

C608 39P_0402_50V8J

0_0402_5%
0_0402_5%

R705 0_0402_5%@

R707 0_0402_5%
R708 0_0402_5%

R713 0_0402_5%

@

C624

0.1U_0402_16V4Z

PCIE_PTX_C_TVRX_N4[14]
PCIE_PTX_C_TVRX_P4[14]

E51_TXD[49]

E51_RXD[49]

@

1 2

R697 0_0603_5%@

PCIE_WAKE#[15,43,45]

T173PAD @

CLK_TV#[14]
CLK_TV[14]

0_0402_5%

BCRSTM

1 2

R701

@

PCIE_PRX_TVTX_N4[14]
PCIE_PRX_TVTX_P4[14]

+3VS

R715

@

1 2

R1440

1 2

R1441

1 2

+3VS

Max 2.38W Max 0.5A

1

C626

0.1U_0402_16V7K

2

1 2

XBCLKM
BCCDET

0_0402_5%
0_0402_5%
0_0402_5%

39P_0402_50V8J

0.01U_0402_16V7K

1

C620

2

TV_CLKREQ#

SIM_DET
BCPWON

TMPTU2_SXP_R

1

C617

2

4.7U_0603_6.3V6K

1

C621

2

0.1U_0402_16V4Z

C622

1 2
1 2

1

2

ISDBT_DET [18]

USB20_N10 [17]
USB20_P10 [17]

TMPTU1_SXP [49]TMPTU2_SXP[49]

1

C618
39P_0402_50V8J

2

1

C625

2

4.7U_0603_6.3V6K

+3VS
+1.5VS

+5VS_L_BCAS

CPLGP1

R736

TV@

1 2

10K_0402_5%

+5VS_L_BCAS

1

IN1

BCRSTM

2

IN2

SN74AHC1G08DCKR_SC70-5

1

IN1

XBCLKM

2

IN2

SN74AHC1G08DCKR_SC70-5

R737
10K_0402_5%

13

D

Q41

2

SSM3K7002BF 1N SC59-3

G

S

TV@

5

U35

TV@

P

B_R_BCRST

4

O

G

3

5

U36

TV@

P

B_R_XBCCLK

4

O

G

3

12

TV@

TV@

1 2

R728 100_0402_5%

TV@

1 2

R733 100_0402_5%

+5VS_L_BCAS

1 2

R735

31

E

10K_0402_5%

Q40

TV@

2

B

BCW68GLT1G PNP SOT23-3

C

1 2

R738

1.5K_0402_5%

B_BCRST

B_XBCCLK

TV@

BCIO

TV@

COMMON BCIO

B_BCRST SIM_RESET

B_XBCCLK SIM_CLK

BCIO SIM_DATA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

@

1 2

R727 0_0402_5%

@

1 2

R730 0_0402_5%

@

1 2

R732 0_0402_5%

@

1 2

R734 0_0402_5%

2010/10/1 2011/11/01

SIM_VCC

R725 0_0603_5%

+5VS

R726 0_0603_5%

Compal Secret Data

Deciphered Date

@

1 2

1 2

+VCC_SIM

+VCC_SIM

SIM_DET

R729 0_0402_5%

1 2

1 2

R731 0_0402_5%

JSIM1

4

GND

5

VPP

6

DET2

I/O

7

DET

LCN_CAF98-06206-S100

CONN@

Title

Size Document Number Re v

Date: Sheet

PCIe-WLAN/TV_B-CAS

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

VCC
RST
CLK

GND0
GND1

20mA Max

1
2
3

8
9

+VCC_SIMDET1
SIM_RESET
SIM_CLKSIM_DATA

of

42 64

0.1

5

1 2

R1014 0_0402_5%@

+LAN_VDDREG

R748 2.49K_0402_1%

PCIE_PRX_LANTX_P6
PCIE_PRX_LANTX_N6
PCIE_PTX_C_LANRX_P6

PCIE_PTX_C_LANRX_N6

CLK_LAN
CLK_LAN#

LAN_X1
LAN_X2

PCIE_WAKE#
ISOLATE#

1 2

C631 0.1U_0402_16V7K

PCIE_PRX_C_LANTX_P6[14]

PCIE_PRX_C_LANTX_N6[14]

D D

+3V_LAN

R741 10K_0402_5%

1 2

+3VS

RTL8105E

C C

Pin14
Pin15
Pin38

CLKREQ_LAN#

1 2

R742 1K_0402_5%

R743

15K_0402_5%

Pin26 assert Low,
RTL8111E will
be isolated with
PCIe I/F bus

RTL8111E

NC

NC
NC 10K ohm PD
NC

1K ohm PU

1 2

C632 0.1U_0402_16V7K

1 2

PCIE_PTX_C_LANRX_P6[14]
PCIE_PTX_C_LANRX_N6[14]

CLKREQ_LAN#[14]

PLT_A_RST#[17,42,44]

+3V_LAN

PLT_A_RST#

CLK_LAN[14]
CLK_LAN#[14]

PCIE_WAKE#[15,42,45]

R744 10K_0402_5%

1 2
1 2

R745 1K_0402_5%

PLT_RST#_LAN

LAN_SMBDATA

LAN_SMBALERT

ENSWREG

4

U37

22

HSOP

23

HSON

17

HSIP

18

HSIN

16

CLKREQB

25

PERSTB

19

REFCLK_P

20

REFCLK_N

43

CKXTAL1

44

CKXTAL2

28

LANWAKEB

26

ISOLATEB

14

NC/SMBCLK

15

NC/SMBDATA

38

GPO/SMBALERT

33

ENSWREG

34

VDDREG

35

VDDREG

46

RSET

24

GND

49

PGND

RTL8111E-VL-CGT_QFN48_6X6

LED3/EEDO

LED1/EESK

LED0

EECS

EEDI

MDIP0
MDIN0
MDIP1
MDIN1

NC/MDIP2

NC/MDIN2

NC/MDIP3

NC/MDIN3

DVDD10
DVDD10
DVDD10

DVDD33
DVDD33

AVDD33
AVDD33
AVDD33
AVDD33

EVDD10
AVDD10

AVDD10
AVDD10
AVDD10

REGOUT

31
37
40

30
32

1
2
4
5
7
8
10
11

13
29
41

27
39

12
42
47
48

21
3

6
9
45

36

LAN_EECS

R739 10K_0402_5%

LAN_EEDI

R740 10K_0402_5%

LAN_MDI0+
LAN_MDI0­LAN_MDI1+
LAN_MDI1­LAN_MDI2+
LAN_MDI2­LAN_MDI3+
LAN_MDI3-

+LAN_VDD10

+3V_LAN

+3V_LAN

+LAN_EVDD10
+LAN_VDD10

+LAN_REGOUT

60 mils

3

1 2
1 2

Layout Note: L46 must be
within 200mil to Pin36,
C705 & C706 must be within
200mil to L46

1 2

2.2UH +-5% NLC252018T-2R2J-N

4.7U_0603_6.3V6K

2

1

Power ( Decoupling Cap. )

+3V_LAN

C688, C690, C692, C694 close to Pin 27,39,47,48
C696, C698 close to Pin 12,42

1 2

C633 0.1U_0402_16V4Z

1 2

C635 0.1U_0402_16V4Z

1 2

C637 0.1U_0402_16V4Z

1 2

C639 0.1U_0402_16V4Z

1 2

C641 0.1U_0402_16V4Z

1 2

C643 0.1U_0402_16V4Z

SPEC:

3.3V, 70mA (Max)

1.05V, 300mA (Max)

+3V_LAN + LA N_VDDREG +LAN_EVDD10+LAN_VDD10

1 2

R746 0_0603_5%

+LAN_VDD10

L43

1

1

2

C651

0.1U_0402_16V4Z

2

C650

4.7U_0603_6.3V6K

1

C646

2

Close to Pin 34,35

+LAN_VDD10

1

C647

0.1U_0402_16V4Z

2

C689, C691,C693 close to pin 13,29,45, respectively
C695 close to pin 3, respectively
C697,C699,C700 close to pin 6,9,41, respectively

1 2

C634 0.1U_0402_16V4Z

1 2

C636 0.1U_0402_16V4Z

1 2

C638 0.1U_0402_16V4Z

1 2

C640 0.1U_0402_16V4Z

1 2

C642 0.1U_0402_16V4Z

1 2

C644 0.1U_0402_16V4Z

1 2

C645 0.1U_0402_16V4Z

1 2

R747 0_0603_5%

1U_0402_6.3V6K

C648

1

1

C649

0.1U_0402_16V4Z

2

2

Close to Pin 21

Crystal

1

C657
27P_0402_50V8J

2

1 2

LAN_X1

Y5

25MHZ_20PF_X5H025000DK1H

LAN_X2

1

C658
27P_0402_50V8J

2

EMI surge solution for CCC (China Compulsory Certification).

LAN_MDI0­LAN_MDI0+

D51

1
2
3
4

10

1

10

LAN_MDI1+

9

2

9

8

3

8

LAN_MDI1-

7

4

7

6

556

GND

RCLAMP3304N.TCT_SLP2626P10-10

11

LAN_MDI2­LAN_MDI2+

D52

1
2
3
4

10

1

10

LAN_MDI3+

9

2

9

8

3

8

LAN_MDI3-

7

4

7

6

556

GND

RCLAMP3304N.TCT_SLP2626P10-10

11

20mil

D53 B88069X9231T203_4P5X3P2-2

MCT1
MCT2
MCT3
MCT4

1 2

D54 B88069X9231T203_4P5X3P2-2

1 2

D63 B88069X9231T203_4P5X3P2-2

1 2

D64 B88069X9231T203_4P5X3P2-2

1 2

Footprint need update

+3V_LAN

B B

ENSWREG

12

R751
0_0402_5%

12

R753
0_0402_5%

@

WOL circuit (Connect +3V_LAN to +3VALW)

100K_0402_5%

WOL_EN#[49]

A A

+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

R751

R753

R758

5

RTL8105E-VC
RTL8111E-VB
PWM Mode

0 ohm
(Pull High)

12

RTL8105E-VC

LDO Mode

NC

NC 0 ohm

R759 47K_0402_5%

(Pull Down)

C662

0.1U_0402_16V7K

1 2

C663

0.01U_0402_25V7K

+3VALW+3VALW

1

2

G

2

2

PMV65XP 1P SOT23 TMOS

1

C664

4.7U_0603_10V6K

@

Vgs=-4.5V,Id=3A,Rds<97mohm

S

Q42

D

1 3

1

2

+3V_LAN

4

1

C665
1U_0402_6.3V6K

2

LAN_MDI3­LAN_MDI3+

LAN_MDI2­LAN_MDI2+

LAN_MDI1­LAN_MDI1+

LAN_MDI0­LAN_MDI0+

Place C719 colse

C666

to LAN chip

0.01U_0402_25V7K

U38

1

TCT1

MCT1

2

TD1+

MX1+

3

TD1-

MX1-

4

TCT2

MCT2

5

TD2+

MX2+

TD2-6MX2-

7

TCT3

MCT3

8

TD3+

MX3+

9

TD3-

MX3-

10

TCT4

MCT4

11

TD4+

MX4+

12

TD4-

1

2

MX4-

LG-2446S-1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

MCT1

24

RJ45_MIDI3-

23

RJ45_MIDI3+

22

MCT2

21

RJ45_MIDI2-

20

RJ45_MIDI2+

19

MCT3

18

RJ45_MIDI1-

17

RJ45_MIDI1+

16

MCT4

15

RJ45_MIDI0-

14

RJ45_MIDI0+

13

2010/10/1 2011/11/01

MCT1

1 2

C656 1000P_0402_50V7K

MCT2

1 2

C659 1000P_0402_50V7K

MCT3

1 2

C660 1000P_0402_50V7K

MCT4

1 2

C661 1000P_0402_50V7K

Compal Secret Data

Deciphered Date

1 2

R752 75_0805_1%

1 2

R755 75_0805_1%

1 2

R756 75_0805_1%

1 2

R757 75_0805_1%

2

RJ45_MIDI3­RJ45_MIDI3+
RJ45_MIDI1­RJ45_MIDI2­RJ45_MIDI2+
RJ45_MIDI1+
RJ45_MIDI0­RJ45_MIDI0+

RJ45_GND LANGND

C1607
1000P_1808_3KV7K

LAN Conn.

JLAN1

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SANTA_130455-1

CONN@

1 2

1

2

C1608

0.1U_0402_16V4Z

Title

Size Document Number Re v

Custom

Date: Sheet

C1609

4.7U_0603_6.3V6K

Compal Electronics, Inc.

PCIe-LAN-RTL8111E

GND
GND

1

2

C1610

0.1U_0402_16V4Z

9
10

1

2

1

1

2

C1611

4.7U_0603_6.3V6K

of

43 64Tuesday, April 12, 2011

0.1

5

+3VS

40mil

0.1U_0402_16V4Z

1

1

C670

C671

2

2

0.1U_0402_16V4Z

D D

PCIE_PTX_C_CRRX_N5[14]
PCIE_PTX_C_CRRX_P5[14]

PCIE_PRX_C_RTX_N5[14]

PCIE_PRX_C_RTX_P5[14]

C C

C670 close to pin19,20
C671 close to pin 44

1 2

C678 0.1U_0402_16V7K

1 2

C679 0.1U_0402_16V7K

PLT_A_RST#[17,42,43]

CR_WAKE#[13]

CLK_CR#[14]

CLK_CR[14]

15mil

1 2

R767 9.1K_0603_5%

R770 100_0402_5%

1 2

C682

0.1U_0402_10V7K

D26

RB751V-40_SOD323-2

+3VS_CR

21

1 2

R771

@

0_0805_5%

PCIE_PTX_C_CRRX_N5
PCIE_PTX_C_CRRX_P5

PCIE_PRX_RTX_N5
PCIE_PRX_RTX_P5

PLT_RST#_CR

1

2

XDCD2#
XDCD1#_MSCD#
XDCD0#_SDCD#

MC_PWREN#

APREXT

CPPE#

15mil

40 mil

4

U43

3

APCLKN

4

APCLKP

9

APRXN

8

APRXP

11

APTXN

12

APTXP

7

APREXT

39

SEEDAT

1

XRSTN

2

XTEST

13

CPPE_N

14

CR1_CD2N

15

CR1_CD1N

16

CR1_CD0N/WAKEN

17

CR1_PCTLN

21

CR1_LEDN

JMB385-LGEZ0C_LQFP48_7X7

JMB385

APVDD

APV18

DV33
DV33
DV33
DV18
DV18

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

APGND

GND
GND
GND
GND

10U_0603_6.3V6M

5
10

19
20
44
18
37

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

34

NC

35

NC

36

NC

30

NC

38

NC

6
24

31
32
33

+1.8VS_APVDD

40mil

C672

1

2

C672 close to pin 18
C673 close to pin 37

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
XDCE_SDCLK_MSCLK_R
XDWP_SDWP
XD_CLE

XD_ALE

3

1

1

C673

C674

0.1U_0402_16V4Z

2

2

0.1U_0402_16V4Z

+1.8VS_APVDD

+3VS

+1.8VS_APVDD

R769 22_0402_5%

0.1U_0402_16V4Z

1

1

C675

C676

2

2

1000P_0402_50V7K

C674 close to pin 10
C675~C677 close to pin 5

XDCE_SDCLK_MSCLK

1 2

C677
10U_0603_6.3V6M

1

2

1

C680

@

22P_0402_50V8J

2

2

XDWP_SDWP

SDCMD_MSBS_XDWE#

XD_CLE

XDCD2#

XDCD1#_MSCD#

XDCD0#_SDCD#

XD_ALE

XDCD0#_SDCD#

1 2

R760 10K_0402_5%

1 2

R762 1K_0402_5%

1 2

R763 10K_0402_5%

1 2

R764 1K_0402_5%

1 2

R765 1K_0402_5%

1 2

R766 1K_0402_5%

1 2

R768 200K_0402_5%

1 2

C683 0.1U_0402_10V7K@

1

+3VS_CR

+3VS

3 IN 1 Card Reader CONN

+3VS_CR

R772 0_0402_5%@

CR_CPPE#[1 7]

B B

1 2

CPPE#

0.1U_0402_16V4Z

1

1

C687

C688

0.1U_0402_16V4Z

XDCE_SDCLK_MSCLK SDCLK

2

C686

2

10U_0603_6.3V6M

1

2

SDDAT0XD_SD_MS_D0

R7840_0402_5%

12

SDDAT1XD_SD_MS_D1

R7850_0402_5%

12

SDDAT2XD_SD_MS_D2

R7730_0402_5%

12

SDDAT3XD_SD_MS_D3

R7740_0402_5%

12

SDCDXDCD0#_SDCD#

R7870_0402_5%

12

SDWPXDWP_SDWP

R7860_0402_5%

12

SDCMDSDCMD_MSBS_XDWE#

R7760_0402_5%

12

R7810_0402_5%

12

All DATA spacing=8mil, CLK spacing=15mil

JSD1

4

VDD

7

DAT0

8

DAT1

9

DAT2

1

DAT3

11

CD

10

WP

2

CMD

5

CLK

3

VSS1

6

VSS2

TAITW_PSDBTC-09GLBS1N14N0

CONN@

GND
GND

12
13

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

JMB385 Media Card Controller

PCA70 LA-7521P M/B

1

of

44 64Tuesday, April 12, 2011

0.1

+3VS

R808 4.7K_0402_5%USB30@

1 2

R809 4.7K_0402_5%@

1 2

R811 4.7K_0402_5%@

1 2

R818 4.7K_0402_5%@

1 2

R821 4.7K_0402_5%@

1 2

R823 4.7K_0402_5%@

1 2

R825 4.7K_0402_5%@

1 2

R826 4.7K_0402_5%USB30@

1 2

R827 4.7K_0402_5%@

1 2

R828 4.7K_0402_5%USB30@

1 2

R829 4.7K_0402_5%@

D D

1 2

5

USB_PESEL
USB_PEPWRDET
USB_TEST_EN

USB_GPIO1
USB30_SMI#
USB_GPIO2
USB_PESEL
USB_PEPWRDET
CLKREQ_USB30#
USB_TEST_EN
USB_GPIO0

USB_PEPWRDET
For WAKE Function

D3 Hot
D3 Cold @

R809 R826

Mount

update PEPWRDET at D3
hot mode pull low

USB_PESEL

Other applaction

Express Card/Mini Card@@

USB30_SMI#[18]

T184 PAD @

C C

PCIE_WAKE#[15,42,43]
USB_PPON_A[46]

USB_OCI[1 7,46]

PLT_RST#[5,17,22,49]

+3VS

B B

4.7K_0402_5%

0.1U_0402_16V4Z

R843

USB30@

USB_SPICS#

C707

USB30@

12

2

1

U45

1

CS#

3

WP#

7

HOLD#

4

GND

MX25L5121EMC-20G SOP 8P

USB30@

R808 R825
Mount

R1017 0_0402_5%

1 2

R834 4.7K_0402_5%

+3VS

R835 0_0402_5%

1 2

C698

U2DN_B[46]

U2DP_B[4 6]

U2DN_A[46]

U2DP_A[4 6]

+1.2VUSB

+3VS

4.7K_0402_5%

SCLK

+3VS

VCC

SO

R840 4.7K_0402_5%@
R1018

1

2

USB30@

SI

R838
R1665 0_0402_5%USB30@

USB30@

1 2

C1614

0.1U_0402_16V4Z

R844

8
6
5
2

Mount

USB30@

12

USB30@
USB30@

USB30@

12

1U_0402_6.3V6K

USB30@

1 2

0_0402_5%

1 2

R839 0_0402_5%

12

0_0402_5%

USB30@

1

C700

0.1U_0402_16V4Z

@

2

12

USB_SPISCK
USB_SPISI
USB_SPISO

2

C708

0.1U_0402_16V4Z

USB30@

1

USB_GPIO1
USB30_SMI#
USB_GPIO2
USB_PESEL
USB_PEPWRDET
CLKREQ_USB30#

USB_SPISCK
USB_SPISI
USB_SPICS#
USB_SPISO

USB_PORST#USB_PORST#_R

T174PAD @
T175PAD @

U2DN_B
U2DP_B
+USB_3V3
+USB_1V2
U2DN_A
U2DP_A

USB_PPON_A

USB_OCI
PLT_RST#_USB30
USB_TEST_EN

4

USB_PPON_A
USB_OCI

USB_PE_REXT
USB_UREXT

USB30_XT1

15P_0402_50V8J

USB30_XT2

ASM1042

(TQFN 64)

+3VS

Mount

U44

1

GPIO1

2

SMI#

3

GPIO2

4

PE_SEL

5

PE_PWRDET

6

PE_CLKREQ#

7

VCC33_1

8

SPI_CLK

9

SPI_DO

10

SPI_CS#

11

SPI_DI

12

GND1

13

PORST#

14

UART_RX

15

UART_TX

16

VCC12_1

17

U2DN_B

18

U2DP_B

19

VSUS33_1

20

VSUS12_1

21

U2DN_A

22

U2DP_A

23

VSUS33_2

24

PE_WAKE#

25

PPON_A

26

PPON_B

27

OCI_A#

28

OCI_B#

29

PE_RST#

30

TEST_EN

31

VCC33_2

32

VCC12_2

ASM1042_TQFN64_9X9

USB30@

@

R810 100K_0402_5% @

1 2

R814 4.7K_0402_5% @

1 2

R822 12.1K_0402_1% USB30@

1 2

R824 12.1K_0402_1% USB30@

1 2

C690 22P_0402_50V8J

2

USB30@

C691

VCC12_3
PE_REXT

PE_CLKN
PE_CLKP
VCC12_4

VDD12U_2

U3RXN_A
U3RXP_A

U3TXN_A
U3TXP_A

U3TXN_B
U3TXP_B

U3RXN_B
U3RXP_B

VDD12U_1

VSUS12_2

Y6
20MHZ_12PF_X5H020000FC1H-X

USB30@

1

1 2

C692 22P_0402_50V8J

+1.2VUSB+1.2VUSB

64

GPIO0

63

GND3

62
61
60

VCC33P

59

PE_TXN

58

PE_TXP

57

GNDA3

56

PE_RXN

55

PE_RXP

54

VDD12P

53

XI

52

XO

51
50
49
48
47
46
45

GNDA2

44
43
42

UREXT

41

VCC33U

40
39
38

GNDA1

37
36
35
34
33

GND2

65

GND4

3

12

@

12

@

USB_GPIO0

USB_PE_REXT
+VDD33U
PCIE_DTX_PRX_N2
PCIE_DTX_PRX_P2

USB30_XT1
USB30_XT2

U3RXDN_A
U3RXDP_A

U3TXDN_A_C
U3TXDP_A_C
USB_UREXT

U3TXDN_B_C
U3TXDP_B_C

U3RXDN_B
U3RXDP_B
+VDD12U
+USB_1V2

+3VS

+1.2VUSB

1 2

R815

2.2K_0402_5%

USB30@

+3VS +5VS

R830 10K_0402_5%

1 2

C693 0.1U_0402_16V4Z

1 2

Close to ASM1042

+VDD33U

C696 0.1U_0402_16V7K USB30@

12

C697 0.1U_0402_16V7K USB30@

12

+VDD12U

CLK_USB30# [14 ]
CLK_USB30 [1 4 ]

+VDD12U

U3RXDN_A [4 6 ]
U3RXDP_A [46]

U3TXDN_A_C [46]
U3TXDP_A_C [46]

+VDD33U

U3TXDN_B_C [46]
U3TXDP_B_C [46]

U3RXDN_B [4 6 ]
U3RXDP_B [46]

+VDD12U

R816

2.2K_0402_5%

@

1 2

USB30@

@

R817

2.2K_0402_5%

USB30@

1 2

C

Q45

2

B

MMBT3904_SOT23-3

E

USB30@

3 1

PCIE_PRX_C_USBTX_N2 [14]
PCIE_PRX_C_USBTX_P2 [14]

PCIE_PTX_C_USBRX_N2 [14]
PCIE_PTX_C_USBRX_P2 [14]

2

2

G

USB_PORST#_R

13

D

Q43
SSM3K7002FU_SC70-3

USB30@

S

Power Sequence

1

+VDD12U

1 2

+1.2VUSB

FBMA-L11-201209-221LMA30T_0805

A A

+3VS

FBMA-L11-201209-221LMA30T_0805

L45

USB30@

1 2

L46

USB30@

1

2

+VDD33U

1

2

5

C718

0.1U_0402_16V4Z

USB30@

+VDD33U

C730

0.1U_0402_16V4Z

USB30@

1

2

1

2

+VDD12U

C715

0.1U_0402_16V4Z

USB30@

C727

0.1U_0402_16V4Z

USB30@

1

2

C716

0.1U_0402_16V4Z

USB30@

+1.2VUSB

1

2

+3VS

1

2

C725

0.1U_0402_16V4Z

USB30@

C735

0.1U_0402_16V4Z

USB30@

1

2

1

2

0.1U_0402_16V4Z

USB30@

0.1U_0402_16V4Z

USB30@

C720

0.1U_0402_16V4Z

USB30@

1

2

C732

0.1U_0402_16V4Z

USB30@

1

2

4

C722

0.1U_0402_16V4Z

USB30@

C721

1

2

C733

USB30@

1

2

0.1U_0402_16V4Z

USB30@

1

2

C734

0.1U_0402_16V4Z

C724

0.1U_0402_16V4Z

USB30@

C723

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

USB3.0

PCA70 LA-7521P M/B

1

0.2

of

45 64Tuesday, April 12, 2011

5

For USB2.0 ESD diode

USB20_N1_L USB20_P1_L

+USB30_VCCA

D D

For USB3.0 ESD diode

U3TXDP_A_R
U3TXDN_A_R
U3RXDP_A_R_0 U3RXDP_A_R_0
U3RXDN_A_R_0

C C

For USB2.0 ESD diode

+USB30_VCCA

For USB3.0 ESD diode

U3TXDP_B_R U3TXDP_B_R
U3TXDN_B_R
U3RXDP_B_R_1
U3RXDN_B_R_1 U3RXDN_B_R_1

B B

D27

6
5
4

PJUSB208H_SOT23-6

D38

1

1

2

2

4

4
5

3

3

8

YSCLAMP0524P_SLP2510P8-10-9

USB30@

D28

6
5
4

PJUSB208H_SOT23-6

D39

1

1

2

2

4

4
5

3

3

8

YSCLAMP0524P_SLP2510P8-10-9

USB30@

USB_PPON_A[45]

I/O4
REF2
I/O3

I/O4
REF2
I/O3

REF1

REF1

I/O1

I/O2

I/O1

I/O2

1
2
3

10

9

9

8

7

7

65

6

1
2
3

10

9

9

8

7

7

65

6

USB_PPON_A

U3TXDP_A_R
U3TXDN_A_R

U3RXDN_A_R_0

U3TXDN_B_R
U3RXDP_B_R_1

USB20_P0_LUSB20_N 0_L

+3VALW

R1020

100K_0402_5%

2

G

1 2

12

USB_PPON_A#

13

D

Q49
SSM3K7002FU_SC70-3

USB30@

S

R1019
0_0402_5%

USB20@

4

R880 0_0402_5%USB20@

USB20_N1[17]

U2DN_A[45]

USB20_P1[17]

U2DP_A[4 5]

U3RXDN_A[45]

U3RXDP_A[45]

U3TXDN_A_C[45]

U3TXDP_A_C[45]

1 2

R881 0_0402_5%USB30@

1 2

R882 0_0402_5%USB20@

1 2

R883 0_0402_5%USB30@

1 2

Layout placement as
close as possable

C767 0.1U_0402_16V7KUSB30@

12

C768 0.1U_0402_16V7KUSB30@

12

USB20_N1_R

USB20_P1_R

U3TXDP_A USB20_N1_L

must to close to JUSB1

R892 0_0402_5%USB20@

USB20_N0[17]

U2DN_B[45]

USB20_P0[17]

U2DP_B[4 5]

U3RXDN_B[45]

U3RXDP_B[45]

U3TXDN_B_C[45]

U3TXDP_B_C[45]

1 2

R893 0_0402_5%USB30@

1 2

R894 0_0402_5%USB20@

1 2

R895 0_0402_5%USB30@

1 2

Layout placement as
close as possable

C769 0.1U_0402_16V7KUSB30@

C770 0.1U_0402_16V7KUSB30@

12

12

USB20_N0_R

USB20_P0_R

U3TXDN_B

U3TXDP_B

must to close to JUSB2

USB2_EN# [49]

+5VALW

1

2

C713
1U_0603_10V6K

3

1 2

R879 0_0402_5% @

L49

1

1

4

4

WCM-2012-900T_0805

USB30@

1 2

R884 0_0402_5% @

1 2

R885 0_0402_5% @

L50

USB30@

4

4

1

1

WCM-2012-900T_0805

1 2

R888 0_0402_5% @

1 2

R889 0_0402_5% @
L51

USB30@

4

4

1

1

WCM-2012-900T_0805

1 2

R890 0_0402_5% @

1 2

R891 0_0402_5% @

L52

1

1

4

4

WCM-2012-900T_0805

USB30@

1 2

R896 0_0402_5% @

1 2

R897 0_0402_5% @
L53

USB30@

4

4

1

1

WCM-2012-900T_0805

1 2

R900 0_0402_5% @

1 2

R901 0_0402_5% @
L54

USB30@

4

4

1

1

WCM-2012-900T_0805

1 2

R902 0_0402_5% @

2.5A

U46

1

GND

VOUT

2

VOUT

VIN

USB_PPON_A# USB_OCI

VIN3VOUT

4

EN

RT9715BGS_SO8

FLG

2

3

3

2

3

2

2

3

3

2

2

3

3

2

3

2

2

3

3

2

3

2

8
7
6
5

USB20_N1_L

USB20_P1_L

U3RXDN_A_R_0

U3RXDP_A_R_0

USB20_N0_L

USB20_P0_L

U3RXDN_B_R_1

U3RXDP_B_R_1

3

2

USB_OCI[17,45]

U3TXDN_A_RU3TXDN_A

U3TXDP_A_R

U3TXDN_B_R

U3TXDP_B_R

W=60mils

+USB30_VCCA

+USB30_VCCA

+USB30_VCCA

@

1

2

W=60mils

W=60mils

C710

4.7U_0805_10V4Z

1

2

C711

0.1U_0402_16V4Z

2

USB3.0 Port A
Connector

9
1
8
2
7
3
6
4
5

USB3.0 Port B
Connector

9
1
8
2
7
3
6
4
5

C712

1000P_0402_50V7K

1

2

JUSB1

SSTX+
VBUS
SSTX­D­GND

GND

D+

GND

SSRX+

GND

GND

GND

SSRX-

OCTEK_USB-09EAEB

CONN@

JUSB2

SSTX+

VBUS

SSTX-

D-

GND

GND

D+

GND

SSRX+

GND

GND

GND

SSRX-

OCTEK_USB-09EAEB

CONN@

1

+USB30_VCCA

1

10
11
12
13

150U_B2_6.3VM_R35M

C765

2

Place closely JUSB1.1

USB2.0 Connector
Co-lay with JUSB1
When USB30 not used

+USB30_VCCA

USB20_P1_L

10
11
12
13

150U_B2_6.3VM_R35M

JUSB7

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

OCTEK_USB-04APEB

CONN@

+USB30_VCCA

1

C766

2

Place closely JUSB2.1

USB2.0 Connector
Co-lay with JUSB2
When USB30 not used

+USB30_VCCA

USB20_N0_L
USB20_P0_L

JUSB8

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

OCTEK_USB-04APEB

CONN@

+

+

1

C1071

0.1U_0402_25V6

2

1

C1072

0.1U_0402_25V6

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

USB3.0 CONN

Size Document Number Re v

2

Date: Sheet

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

46 64

1

0.1

of

A

+5VS

1

1

C1449

2

0.1U_0402_16V4Z

1 1

2

B

L97

@

1 2

FBMA-L11-160808-800LMT_0603

60mil 40mil

C1450

0.1U_0402_16V4Z

U86

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

(output = 300 mA)

5

4

C

4.75V

@

1 2

C1451

0.01U_0402_25V7K

+AVDD_HDA

C1452

10U_0805_10V6K

(Place close to PIN25)

C1457

10U_0805_10V6K

+AVDD_HDA +3VS_VDD

(Place close to PIN38)

1

2

1

2

D

+3VS

1

C1453

0.1U_0402_16V7K

2

1

C1458

0.1U_0402_16V7K

2

+3VS_VDD

L98

MBK1608121YZF_0603

12

E

15mil40mil

10U_0805_10V6K

(Place close to PIN1)

10U_0805_10V6K

(Place close to PIN9)

C1454

C1459

@

1

2

1

2

1

C1455

0.1U_0402_16V7K

2

1

C1460

0.1U_0402_16V7K

2

F

EC Beep

EC_BEEP#[49]

PCH_SPKR[13]

PCI Beep

G

1 2

R1521 47K_0402_5%

1 2

R1522 47K_0402_5%

4.7K_0402_5%

Change to AGND for
high frequency noise
issue

R852

1

12

2

C1456

0.1U_0402_16V4Z

H

MONO_INMONO_IN_1

1 2

C1448 0.1U_0402_16V4Z

38

U87

AVDD125AVDD2

14

LINE2-L

15

LINE2-R

16

MIC2_L

17

MIC2_R

For ESD and EMI

2 2

AZ_RST_HD#[13]

INT_DMIC_CLK[50]

3 3

Place close to Codec

+3VS

R1530

@

4.7K_0402_5%

C1470

@

0.01U_0402_25V7K

L114

1 2

C1471

@

27P_0402_50V8J

For EMI

C1481 0.1U_0402_16V4Z<EMI>

1 2

C1482 0.1U_0402_16V4Z<EMI>

1 2

1 2

R1540 0_0603_5%

1 2

R1542 0_0603_5%

1 2

R1543 0_0603_5%

1 2

R1659 0_0603_5%

1 2

R1660 0_0603_5%@

1 2

R1661 0_0603_5%@

12

1

2

FBMA-L10-160808-301LMT_2P

1

2

CODEC_MUTE#[49]

MIC1_L
MIC1_R

AZ_SYNC_HD[13]
AZ_SDOUT_HD[13]

HP_DET#
WOOFER_DET#_Q

C1461

2.2U_0805_25V6K

C1464

2.2U_0805_25V6K

1 2

C1465 4.7U_0805_25V6-K

1 2

C1467 4.7U_0805_25V6-K

INT_DMIC_DATA[50]

MONO_IN

INT_DMIC_CLK_R

R153320K_0402_1%
R15345.1K_0402_1%

1 2

R163810K_0402_1%

1 2

EAPD[49]

1 2

1 2

12

MIC1_L_C
MIC1_R_C

CBP
CBN

SENSEAMIC_SENSE#
SENSEB

3

GPIO1

29

CBP

30

CBN

31

CPVEE

21

MIC1_L

22

MIC1_R

12

PCBEEP-IN

11

RESET#

10

SYNC

5

SDATA_OUT

45

SPDIFO2

46

DMIC_CLK1/2

13

SENSE A

34

SENSE B

47

EAPD

48

SPDIFO1

2

GPIO0/DMIC_DATA1/2

4

DVSS

7

DVSS

ALC663-GR_LQFP48_7X7

GND GNDA

Sense Pin Impedance Codec Sign als

SENSE A 20K

5.1K
10K

39.2K

4 4

SENSE B

5.1K

10K

20K

39.2K

A

MIC1 (PIN 21, 22)

FRONT (PIN 35, 36)
LINE1 (PIN 23, 24)
SURR (PIN 39, 41)

HP-OUT (PIN 32, 33)

LFE (PIN 44)
LFE+HP-OUT10K//5.1K
MIC2 (PIN 16, 17)
LINE2 (PIN 14, 15)

Q104
SSM3K7002BF 1N SC59-3

D

WOOFER_DET#_Q

WOOFER_PD#[48,49]

B

S

13

G

2

C

1

9

DVDD

DVDD_IO

35

FRONT_L

36

FRONT_R

39

SURR_L

41

SURR_R

33

HPOUT-L

32

HPOUT-R

43

CENTER

44

LFE

6

BITCLK

8

SDATA_IN

23

LINE1-L

24

LINE1-R

VREF

JDREF

MONO-OUT

AVSS1
AVSS2

S_HP_OUT_L[34]

S_HP_OUT_R[34]

19
20
18
28
27
40
37
26

42

PNL_STAT[34,48,49]

MIC2-VREFO
LINE2-VREFO
LINE1-VREFO

MIC1-VREFO

0:PC MODE
1:HDMI MODE

R1523

1 2

10mil

+VREF

R1535

20K_0402_1%

HP_LEFT

HP_RIGHT

Issued Date

0_0402_5%

1 2
1 2

R1524

0_0402_5%

0_0402_5%

1 2

C1466

1 2

12

0.1U_0402_16V7K

12

@

1U_0603_25V6K

HP_LEFT
HP_RIGHT

R1527

22P_0402_50V8J

1 2

R1531

33_0402_5%

+MIC1_VREFO

1

1

C1474

2

2

C1473

2.2U_0603_6.3V6K

C1603
1U_0603_25V6K

U97

C1604

9
2

7
4

1
5

V+

NC1
NO1

COM1
NC2
NO2

COM2
IN1

GND

IN2

TS5A23157RSER_QFN10_2X1P5

2010/10/1 2011/11/01

AMP_LEFT [48]
AMP_RIGHT [48]

AMP_WOOFER [48]

AZ_BITCLK_HD [13]

AZ_SDIN0_HD [13]

+5VALW

12

R1666
0_0402_5%

1 2

8

HP_L

10

HP_R

6
3

E

MIC1_L M IC1_L_R1
MIC1_R

Compal Secret Data

AMP_LEFT_L
AMP_LEFT_R

AMP_WOOFER_R

R1639 22_0402_5%@

HDA_SDIN0_AUDIO

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

D

+MIC1_VREFO

CH751H-40PT_SOD323-2

R1525

4.7K_0402_5%

R1528 1K_0402_5%
R1529 1K_0402_5%

HP_MUTE[49]

C1479 2.2U_0603_6.3V6K

1 2
1 2

C1478 2.2U_0603_6.3V6K

Deciphered Date

21

D65

12

12

MIC1_R_R1

12

BLM15AG121SN1D_L0402_2P

HP_L_0 PL

D67

PJDLC05C_SOT23-3

F

21

D66
CH751H-40PT_SOD323-2

12

R1526

4.7K_0402_5%

BLM15AG121SN1D_L0402_2P

L100

1 2

L101

1 2

D60

PJDLC05C_SOT23-3

R1545
100_0402_5%

@

R1546
100_0402_5%

@

R1537

56.2_0603_1%

HP_L_1

1 2

HP_R_1

1 2

2

R1536

56.2_0603_1%

3

1

MIC_SENSE#

MIC JACK

JMIC1

6

C1469

220P_0402_50V7K

2

B

E

@

Q92
BC847B_SOT23-3

1

1

C1477
330P_0402_50V7K

2

2

PRHP_R_0

HP_DET#

1
2

3
4
5

SINGA_2SJ-0960-D11

CONN@

PL
PR

C

3 1

HP JACK

JHP1

6
1
2

3
4
5

SINGA_2SJ-0960-D11

CONN@

of

47 64

H

MIC1_L_R
MIC1_R_R

2

3

1

1

C1468

220P_0402_50V7K

2

2

1

C

@

Q91

2

B

BC847B_SOT23-3

E

3 1

C1476

330P_0402_50V7K

L103
FBMA-L11-160808-700LMT_2P

1 2
1 2

L102
FBMA-L11-160808-700LMT_2P

HP_DET#[34,49]

Title

Size Document Number Re v

Date: Sheet

HDA-ALC272/HP/MIC

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

G

0.1

5

R1547 10_0603_5%

1U_0603_25V6K

C1507

0

1

1

2

S_LINE_OUTL[ 34]

S_LINE_OUTR[34]

PNL_STAT[34, 47,49]

1 2

1

C1551

0.1U_0402_16V7K

2

AMP_LEFT[47]

AMP_RIGHT[47]

+12VALW

L106
FBMA-L11-160808-121LMA30T_0805

1 2

C1499

220U_16V_M

1

+

2

AV(inv)

20dB

26dB

32dB

36dB

+12VALW

C1550

10U_1206_25V6M

Close to U94
Pin8

D D

0:PC MODE
1:HDMI MODE

+12V1_PVCC

C1506

1U_0603_25V6K

12

12

Close to U90
Pin27,28

C C

GAIN1 GAIN0

0

0

10

11

TPA3113 for Speaker TPA3113 for Woofer

+12VALW +12VALW

@

R1556
100K_0402_1%

1 2

R1561

B B

100K_0402_1%

1 2

+12V2_PVCC

1U_0603_25V6K

12

A A

@

R1557
100K_0402_1%

1 2

GIN1GIN0

R1562
100K_0402_1%

1 2

C1526

1U_0603_25V6K

C1525

12

Close to U91
Pin27,28

+12VALW

L111
FBMA-L11-160808-121LMA30T_0805

1 2

C1517

220U_16V_M

1

+

2

1U_0603_25V6K

12

5

12

C1487
1U_0603_25V6K

12

C1590

@

1U_0603_25V6K

Close to U90
Pin15,16

INPUT
IMPEDANCE

60Kohm

30Kohm

15Kohm

9Kohm

@

R1558
100K_0402_1%

1 2

R1563
100K_0402_1%

1 2

+12V2_PVCC

C1519

1U_0603_25V6K

C1518

12

+12V1_AVCC

NC1
NO1

COM1
NC2
NO2

COM2
IN1

GND

IN2

+12V1_PVCC

C1500

12

S_LINE_OUTL[ 34]

S_LINE_OUTR[34]

@

R1559
100K_0402_1%

GIN1_WGIN0_W

R1564
100K_0402_1%

12

8

V+

10

6
3

C1501

1U_0603_25V6K

AMP_WOOFER[47]

WOOFER_PD#[47,49]

C1589
1U_0603_25V6K

U96

9
2

7
4

1
5

TS5A23157RSER_QFN10_2X1P5

1U_0603_25V6K

12

1 2

1 2

Close to U91
Pin15,16

+5VALW

R1663
0_0402_5%

1 2

AMP_L

+3VALW

AMP_PD#[ 49]

C1546

0.22U_0402_10V6K

1 2

1 2

C1547

0.22U_0402_10V6K

+12VALW

R1565 10_0603_5%

SWOOFER

+3VALW

4

C1490 0.22U_0402_10V6K

1 2

C1491 0.22U_0402_10V6K

1 2

AMP_R

C1494 0.22U_0402_10V6K

1 2

C1497 0.22U_0402_10V6K

1 2

R1551
100K_0402_5%

@

1 2

R1552
0_0402_5%

1 2

R1667
100K_0402_5%

1 2

1 2

R1668
100K_0402_5%

1 2

12

C1511
1U_0603_25V6K

C1514 0.22U_0402_10V6K

1 2

C1515 0.22U_0402_10V6K

1 2

C1516 0.22U_0402_10V6K

1 2

R1567
100K_0402_5%

@

1 2

R1569
0_0402_5%

1 2

4

+12V1_AVCC
+12V1_PVCC

AMP_L_C

AMP_R_C

GIN0
GIN1

AMP_PD#_R

12

R1554
100K_0402_5%

0.033U_0402_16V7K

1 2
1 2

GIN0_W

AMP_PD1#_R

R1572
100K_0402_5%

R1618

16.2K_0402_1%

1 2

AMP_W

R1617

1.91K_0402_1%

1 2

+12V2_AVCC
+12V2_PVCC

C1605 0.22U_0402_10V6K

C1606 0.22U_0402_10V6K

12

U90

7

AVCC

15

PVCCR

16

PVCCR

27

PVCCL

28

PVCCL

3

LINP

4

LINN

12

RINP

11

RINN

5

GAIN0

6

GAIN1

1

SD#

2

FAULT#

13

NC

29

GND

TPA3113D2PWPR_HTSSOP28

C1544 0.1U_0402_16V7K

1 2

C1554

0.1U_0402_16V7K

C1548

1 2

R1621
10K_0402_1%

@

U91

7

AVCC

15

PVCCR

16

PVCCR

27

PVCCL

28

PVCCL

3

LINP

4

LINN

12

RINP

11

RINN

5

GAIN0

6

GAIN1

1

SD#

2

FAULT#

13

NC

29

GND

TPA3113D2PWPR_HTSSOP28

+12VALW

1 2

3

+IN

12

2

-IN

1 2

R1622
0_0402_5%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

26

BSPL

25

OUTPL

23

OUTNL

22

BSNL

17

BSPR

18

OUTPR

20

OUTNR

21

BSNR

14

PBTL

10

PLIMIT

9

GVDD

24

PGND

19

PGND

8

AGND

8

P

1

1 2

OUT

G

U94A
TLV272IDR SOIC 8P

4

26

BSPL

25

OUTPL

23

OUTNL

22

BSNL

17

BSPR

18

OUTPR

20

OUTNR

21

BSNR

14

PBTL

10

PLIMIT

9

GVDD

24

PGND

19

PGND

8

AGND

3

BSPL

BSNL

BSPR

BSNR

PLIMIT

+GVDD

R1619

2.05K_0402_1%

@

PLIMIT_WGI N1_W

+GVDD1

3

C1484

0.22U_0603_25V7K

1 2

OUTPL
OUTNL

C1489

1 2

0.22U_0603_25V7K
C1492

0.22U_0603_25V7K

1 2

OUTPR
OUTNR

1 2

C1498

0.22U_0603_25V7K

+GVDD

12

0.01U_0402_25V7K

R1624
0_0402_5%

1 2

+GVDD1

1U_0603_25V6K

12

2010/04/14 2011/04/14

+GVDD

12

R1549

28.7K_0402_1%

1U_0603_25V6K

1 2

C1523

@

1U_0603_25V6K

12

C1503

12

C1502

C1545 0.22U_0603_25V7K

R1620

22.6K_0402_1%

OUTR_W

12

R1553
10K_0402_1%

1 2

5
6

1

C1549

2

OUTL_W SPKW-

BSPL_W

BSPR_W

+12V2_AVCC

R1568

1 2

20.5K_0402_1%

C1524

1U_0603_25V6K

12

R1570
10K_0402_1%

Compal Secret Data

OUTPL

OUTPR

OUTNR

+IN

7

OUT

-IN

U94B
TLV272IDR SOIC 8P

2

C1510

0.47U_0603_16V7K

1

2

C1520

0.47U_0603_16V7K

1

+GVDD1

Deciphered Date

SWOOFER

5A/120ohm/100MHz

1

C1512

470P_0805_50V8J

2
12

R1566

10_1206_5%

5A/120ohm/100MHz

1

C1521

470P_0805_50V8J

2
12

R1571

10_1206_5%

D68

1

PJSOT24CH_SOT23-3

2

L104
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

1

C1485
470P_0805_50V8J

2

12

R1548
10_1206_5%

L105
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

1

C1495
470P_0805_50V8J

2

12

R1550
10_1206_5%

L107
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

1

C1504
470P_0805_50V8J

2

12

R1555
10_1206_5%

L108
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

1

C1508
470P_0805_50V8J

2

12

R1560
10_1206_5%

L110
HCB2012KF-121T50_0805

1 2

L113
HCB2012KF-121T50_0805

1 2

WOOFER_ID[49]

3

2

2

1

C1513
1000P_0603_50V7K

2

SPKW+

1

C1522
1000P_0603_50V7K

2

+3VALW

1

SPKL+

1

C1486
1000P_0603_50V7K

2

SPKL-OUTNL

1

C1496
1000P_0603_50V7K

2

SPKR+

1

C1505
1000P_0603_50V7K

2

Speaker Conn.

1

2

SPKR+
SPKR­SPKL+
SPKL-

3

1

BSPL

C1615 1000P_0603_50V7K@

BSNL

C1616 1000P_0603_50V7K@

BSPR

C1617 1000P_0603_50V7K@

BSNR

C1618 1000P_0603_50V7K@

D61
PJSOT24CH_SOT23-3

3

2

D62
PJSOT24CH_SOT23-3

1 2
1 2
1 2
1 2

EMI request Close to U4.BB57

SPKR-

1

C1509
1000P_0603_50V7K

2

+3VALW

R1657
1M_0402_5%

WOOFER_DET

R1640 10K_0402_5%

1 2

WOOFER_ID

Title

Size Document Number Rev

Custom
Date: Sheet

WOOFER_DET
SPKW+

SPKW-

Compal Electronics, Inc.

AMP & Audio Jack

PCA70 LA-7521P M/B

R1658
10K_0402_1%

1 2

1 2

13

D

Q106

2

SSM3K7002BF 1N SC59-3

G

S

2

3

D69

1

PJSOT24CH_SOT23-3

Woofer Conn.

JWOFER1

5
4

3
2
1
7

6

SINGA_2SJ2270-000111

CONN@

1

WOOFER_DETWOOFER_ID

JSPK1

1

1

2

2

3

3

4

4

5

G1

6

G2

ACES_50228-00471-001

CONN@

WOOFER_DET# [49]

of

48

64Tuesday, April 12, 2011

1.0

5

1 2

C1599 0.1U_0402_16V4Z

ESD request Close to U51.1

D D

10_0402_5%

22P_0402_50V8J

+3VALW

R945
47K_0402_5%

C818 0.1U_0402_16V4Z

to avoid EC entry ENE test mode

R949 47K_0402_5%
R950 47K_0402_5%

C C

VGA_BKOFF#_R[22]

VGA

+3VALW

+3VS

UMA_ENBKL[16]

1 2
1 2
1 2
1 2

R955 2.2K_0402_5%
R956 2.2K_0402_5%
R957 2.2K_0402_5%
R958 2.2K_0402_5%

1 2

R961 100K_0402_5%

1 2

10M_0402_5%

1

C824

2

18P_0402_50V8J

32.768KHZ_12.5PF_Q13MC14610002

PCH

B B

A A

GATEA20

For EMI

CLK_PCI_EC

12

R941

@

1

C817

@

2

ECRST#

12

12

R1051 0_0402_5%

DIS@

1 2

@

1 2

R1052 0_0402_5%

E51_TXD

R962

CRY2CRY1

1

Y7

OSC4OSC

NC3NC

2

5

+3VALW

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

1

C825

2

18P_0402_50V8J

0.1U_0402_16V4Z

1 2
1 2

0.1U_0402_16V4Z

1

C810

HP_DET#[34,47]

WOOFER_DET#[4 8]

CODEC_MUTE#[47]

VCCSA_PG[56]

EC_ENVDD[35]

WLAN_LED#[42]
BT_LED#[18]

WOOFER_PD#[47,48]
SCFW_UPDATE#[40]

SUSWARN#[15]

INVT_PWM[35]
FAN_SPEED1[51]
FAN_SPEED2[51]

E51_TXD[42]

E51_RXD[42]

ON/OFF[50]

PWR_ON_LED[50]

S_ENVDD[34]

1

C811

2

2

GATEA20[18]
KB_RST#[18]
SERIRQ[13]

LPC_FRAME#[13]

LPC_AD3[13]
LPC_AD2[13]
LPC_AD1[13]
LPC_AD0[13]

CLK_PCI_EC[17]

PLT_RST#[5,17,22,45]

EC_SCI#[18]

EC_SMB_CK1[34]
EC_SMB_DA1[34]
EC_SMB_CK2[14,23,52]
EC_SMB_DA2[14,23,52]

PM_SLP_S3#[15]
PM_SLP_S5#[15]

EC_SMI#[18]

WOOFER_ID[48]

0.1U_0402_16V4Z

1

C812

2

0.1U_0402_16V4Z

HP_DET#_EC

T224
T225
T226
T227

T228

WOOFER_DET#
CODEC_MUTE#

EC_ENVDD
WLAN_LED#
BT_LED#

WOOFER_PD#
VGA_UMA_BKOFF#
SCFW_UPDATE#

PM_SLP_S3#
EC_SMI#

SUSWARN#
INVT_PWM
FAN_SPEED1
FAN_SPEED2
E51_TXD
E51_RXD
ON/OFF

1 2

R959 0_0402_5%@

4

1

C813

2

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#

KSI4
KSI5
KSI6
KSI7

KSO1
KSO2
KSO3

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PWR_ON_LED

S_ENVDD_R

CRY1
CRY2

4

2

C814

1

1000P_0402_50V7K

U51

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LPC_FRAME#/LFRAME#

5

LPC_AD3/LAD3

7

LPC_AD2/LAD2

8

LPC_AD1/LAD1

10

LPC_AD0/LAD0

12

CLK_PCI_EC/PCICLK

13

PCIRST#/GPIO05

37

EC_RST#/ECRST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/SCL0/GPIO44

78

EC_SMB_DA1/SDA0/GPIO45

79

EC_SMB_CK2/SCL1/GPIO46

80

EC_SMB_DA2/SDA1/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

SUS_PWR_DN_ACK/GPIO0D

25

INVT_PWM/PWM2/GPIO11

28

FAN_SPEED1/FANFB0/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLK1

123

XCLK0

+3VALW

2

C815
1000P_0402_50V7K

1

Int. K/B
Matrix

3

+3VALW

C809

1 2

0.1U_0402_16V4Z

9

22

VCC

VCC

LPC & MISC

PS2 Interface

SM Bus

GND

11

67

33

96

111

125

VCC

VCC

VCC

VCC

AVCC

PWM0/GPIO0F

PWM Output

DA Output

SPI Device I/F

SPI Flash ROM

GPIO

GND

24

BEEP#/PWM1/GPIO10

ACOFF/FANPWM1/GPIO13

BATT_TEMP/AD0/GPI38

BATT_OVP/AD1/GPI39

AD Input

DAC_BRIG/DA0/GPO3C
EN_DFAN1/DA1/GPO3D

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B
CAP_INT#/PSCLK2/GPIO4C

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

WOL_EN/SDICLK/GPXIOA01

ME_EN/SDIMOSI/GPXIOA02

LID_SW#/GPXIOD00

GPIO

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04

EC_SWI#/GPXIOA06

ICH_PWROK/GPXIOA07

GPO

RF_OFF#/GPXIOA09

PM_SLP_S4#/GPXIOD01

GPI

EC_THERM#/GPXIOD04

PBTN_OUT#/GPXIOD06

EC_PME#/GPXIOD07

GND

AGND

GND

GND

KB930QF-A1_LQFP128_14X14

35

69

94

113

FANPWM0/GPIO12

ADP_I/AD2/GPI3A

AD3/GPI3B

AD4/GPI42
AD5/GPI43

IREF/DA2/GPO3E

DA3/GPO3F

PSDAT2/GPIO4D

SDICS#/GPXIOA00

SPIDI/MISO

SPIDO/MOSI

SPICLK/GPIO58

SPICS#

GPIO40

H_PECI/GPIO41

FSTCHG/GPIO50

PWR_LED#/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXIOA05

BKOFF#/GPXIOA08

GPXIOA10
GPXIOA11

ENBKL/GPXIOD02

EAPD/GPXIOD03

SUSP#/GPXIOD05

V18R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

HP_MUTE

21

EC_BEEP#

23
26
27

63
64
65

AD_BID

66
75
76

EN_DFAN1

68

EN_DFAN2

70
71
72

83

USB1_EN#

84
85

H_PROCHOT#_EC

86

PNL_STAT

87

HDMI_STAT

88

VGATE

97

WOL_EN#

98

PWRME_CTRL#

99

SCALER_ON#

109

EC_SI_SPI_SO

119

EC_SO_SPI_SI

120

SPI_CLK

126

SPI_CS#

128

R1103 10K_0402_5%

73

EC_PECI

74

I2C_INT_SCR

89
90
91
92
93

SYSON

95

VR_ON

121
127

PCH_RSMRST#

100
101
102
103

PM_PWROK

104

BKOFF#

105
106
107
108

110

S_BKOFF#

112
114

HDMI_CABLE_DET#

115

SUSP#

116

PBTN_OUT#

117
118

+EC_V18R

124

2010/10/1 2011/11/01

HP de-pop for scaler output.

HP_MUTE [47]
EC_BEEP# [47]

TMPTU2_SXP [42]
AD1_KBC [50]

TMPTU1_SXP [42]

EN_DFAN1 [51]
EN_DFAN2 [51]
AD2 [34]
AD1 [34]

R1662
0_0402_5%

1 2

R954 43_0402_1%

1

C821

4.7U_0603_10V6K

2

AMP_PD#AMP_PD#_EC0

USB1_EN# [40,41]

PNL_STAT [34,47,48]

HDMI_STAT [34]

VGATE [15,58]

WOL_EN# [43]

PWRME_CTRL# [13]

SCALER_ON# [34]

12
1 2

PCH_RSMRST# [15]

EC_SWI# [15]

PM_PWROK [15]

BKOFF# [35]

WL_OFF# [42]
USB2_EN# [46]

CPU_OT [52,53]

PM_SLP_S4# [15]
S_BKOFF# [34]
EAPD [ 47]

HDMI_CABLE_DET# [34,37]

SUSP# [51,54,55,56,57]
PBTN_OUT# [15]

I2C_INT_SCR [34]
S_AMP_PD# [34]

VGA_IN_DET# [34,40]

SYSON [57]
VR_ON [58]

PNL_STAT2 [34]

Compal Secret Data

Deciphered Date

+3VALW

2

AMP_PD# [48]

CIR_IN [50]

H_PECI [5, 18]

2

VR_HOT#[58]

C822

0.1U_0402_16V4Z

1

R940

0_0402_5%

H_PROCHOT#_EC

2N7002K_SOT23

SYSON
SUSP#
VR_ON

12

13

D

2

G

Q57

S

TV tuner
temperature

TMPTU1_SXP

TMPTU2_SXP

R942 10K_0402_5%

1 2

R943 10K_0402_5%

1 2

R944 4.7K_0402_5%

1 2

R946 10K_0402_5%
R948 10K_0402_5%

+3VALW

Ra

AD_BID

Rb

VR_ON

C1600 0.1U_0402_16V4Z

100K_0402_5%

1 2

R953

8.2K_0603_1%

1 2

1 2

12
12

R951

12

C816
47P_0402_50V8J

+3VS

H_PROCHOT# [5]

ESD request Close to U51.121

EC_PECI

1 2

C1601 0.1U_0402_16V4Z

ESD request Close to U51.74

+3VALW

SPI Flash (256KB)

20mils

1

2

SPI_CS#
SPI_CLK
EC_SO_SPI_SI EC_SI_SPI_SO

SPI_CLK

U52

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

EN25F20-100GCP SOP 8P

R964

1 2

10_0402_5%

4

VSS

2

Q

1 2

C823 10P_0402_50V8J

For EMI

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

LPC-EC-KB930

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

1

of

49 64

0.1

5

Power Button

R967 100K_0402_5%

D33

D D

TOP side
For debug
BTM side

SW3

SMT1-05-A_4P

5

6

3
4

1
2

CIR

C C

CIR_IN[49]

1000P_0402_50V7K

ON/OFFBTN#

1

C826

0.1U_0402_25V6

2

@

For EMI request

+3VALW

2

C829

@

1

2

1

3

BAV70W_SOT323-3

PVT EMI request.

1 2

JCIR1

1

1

2

2

3

3

4

4

5

G1

6

G2

ACES_50228-00471-001

CONN@

+3VALW

4

ON/OFF [49]

Touchscreen

USB20_N2[17]
USB20_P2[17]

+5VS

C1555

0.1U_0402_16V7K

3

USB20_N2
USB20_P2

1

2

+5VS

JTCS1

1

6

1

GND

2

2

3

3

4

4

5

7

5

GND

ACES_50224-00501-001

CONN@

D40

@

6

I/O1

I/O4

5

REF1

REF2

4

I/O2

I/O3

PJUSB208H_SOT23-6

2

Screw Hole

H1

H_3P3

@

1

H10

H_3P3

@

1

H19

H_4P5

@

1

USB20_P2USB20_N2

1
2
3

H28

1

H_3P8N

@

H2

H11

H20

H29

1

1

1

1

H_3P3

@

H_3P3

@

H_4P5

@

H_3P8N

@

H3

H12

H21

H30

1

1

1

1

H_3P3

@

H_3P3

@

H_3P8

@

H_3P8N

@

H5

1

H14

1

H23

1

H_3P3

@

H_4P5

@

H_4P3X3P8

@

H6

H15

1

1

H_3P3

@

H_4P5

@

H4

H_3P3

@

1

PCB Fedical Mark PAD

H7

H16

1

1

H_3P3

@

H_4P5

@

1

H9

H8

1

H17

1

FD1

@

1

H_3P3

@

H_4P5

@

@

FD2

H_3P3

@

1

H18

H_4P5

@

1

FD3

FD4

@

@

1

1

1

ISPD

ZZZ1

6LPCB@

PCB LA-7521P

U66

X76@

ZZZ4

8LPCB@

PCB LA-7522P

U67

X76@

U58

GV@

N12P-GV-B-A1_FCBGA_973P

U68

X76@

U69

X76@

H5TQ1G63DFR-11C

U70

X76@

H5TQ1G63DFR-11C

CAP Button/B Connector

B B

JSW1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

G11119

10

G12

10

ACES_50228-01071-001

CONN@

12

C1064 1000P_0402_50V7K@

12

C1062 470P_0402_50V7K

12

C1602 470P_0402_50V7K

12

+3VALW

+3VS

+3VALW

AD1_KBC[49]

SATA_LED#[13]

PWR_ON_LED[49]

A A

SATA_LED#
PWR_ON_LED
ON/OFFBTN#

SATA_LED#

ON/OFFBTN#
PWR_ON_LED

Reserve for EMI.

5

4

CAM

+3VS +3VS_CAM

R973

@

0_0603_5%

1 2

1

2

1U_0402_6.3V6K

C827

C828

0.1U_0402_16V7K

+3VS

ZZZ2

+3VS_CAM

JCAM1

1

USB20_N3[17]

1

2

USB20_P3[17]

INT_DMIC_CLK[47]

INT_DMIC_DATA[47]

USB20_N3 USB20_P3

@

6

I/O4

5

REF2

4

I/O3

PJUSB208H_SOT23-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

USB20_N3
USB20_P3
INT_DMIC_CLK
INT_DMIC_DATA

D41

1

I/O1

2

REF1

INT_DMIC_CLKIN T _ DMIC_DATA

3

I/O2

2010/10/1 2011/11/01

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_50228-0067N-001

CONN@

Compal Secret Data

Deciphered Date

1st 2nd

X76

Part Number = X7 630488L01

X76_HY1G@

2

H5TQ1G63DFR-11C

U71

X76@

H5TQ1G63DFR-11C

ZZZ3

H5TQ1G63DFR-11C

U72

X76@

H5TQ1G63DFR-11C

H5TQ1G63DFR-11C

U73

X76@

H5TQ1G63DFR-11C

X76

Part Number = X7 630488L02

X76_SAM1G@

Title

Size Document Number Re v

Date: Sheet

PWR/Cap./TP/LED/LP/LS/Screw

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

1

of

50 64

0.1

A

+3VALW TO +3VS

+3VALW +3VS

Q60

8
7
6

1 1

5

AP4800BGM-HF_SO8

1

C8404.7U_0603_10V6K

2

1

S

D

2

S

D

3

S

D

4

G

D

1

2

0.022U_0402_25V7K

Vgs=10V,Id=9A,Rds=18.5mohm Vgs=10V,Id=9A,Rds=18.5mohm

C832

C841

1

2

1U_0402_6.3V6K

12

R985

330K_0402_5%

1

C833

4.7U_0603_10V6K

2

R982

1 2

47K_0402_5%

61

Q64A
2N7002KDWH_SOT363-6

+12VALW

SUSP

2

R979

1 2
34

Q64B
2N7002KDWH_SOT363-6

5

470_0805_5%

B

+5VALW TO +5VS

+5VALW

Q61

8
7
6
5

AP4800BGM-HF_SO8

1

C8424.7U_0603_10V6K

2

1

S

D

2

S

D

3

S

D

4

G

D

1

12

C843

R986

200K_0402_5%

2

0.01U_0402_25V7K

+5VS

1

2

@

C

4.7U_0603_10V6K

C834
1U_0603_10V6K

R983

1 2

47K_0402_5%

61

Q65A
2N7002KDWH_SOT363-6

2

C835

1

2

SUSP

+12VALW

R980

1 2
34

Q65B
2N7002KDWH_SOT363-6

5

470_0805_5%

D

+12V1 TO +12VS (PMOS)

Vgs=20V,Id=15A,Rds=7mohm

+12VALW

Q105

2

Q74A

1
2
3
4

12

61

+5VS

For EMI

2

C838

@

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+12VALW

2

C839

@

1

R1028

20K_0402_5%

SUSP#

2N7002KDWH_SOT363-6

S
S
S
G

AO4423_SO8

C1006

1

2

8

D

7

D

6

D

5

D

0.1U_0603_25V7K

1U_0603_25V6K

+12VS

C1005

E

12

R1027
470_0603_5%

1 2

34

SUSP

5

Q74B
2N7002KDWH_SOT363-6

+1.5V to +1.5VS

+1.5V

3 1

AP2301GN-HF_SOT23-3

1.5VS_GATE

R984
100K_0402_5%

1 2

47K_0402_5%

61

1

2

R987

1 2

C844

4.7U_0603_10V6K

2 2

2N7002KDWH_SOT363-6

SUSP#

+5VALW

2

Q66A

Q62

C837

2

1

C845

0.1U_0402_25V6

2

+1.5VS

1

4.7U_0603_10V6K

2

1

C836

1U_0402_6.3V6K

2

2N7002KDWH_SOT363-6

R981

Q66B

470_0805_5%

1 2
34

SUSP

5

Discharge circuit

+1.05VS_VPCH

3 3

R1604
470_0805_5%

1 2

Q98

13

D

SSM3K7002BF 1N SC59-3

SUSP

2

G

S

+0.75VS

D

S

R991

22_0805_5%

1 2

13

G

Q68
SSM3K7002BF 1N SC59-3

2

+1.05VS_VCCIO

R992
470_0805_5%

1 2

13

D

S

Q71
SSM3K7002BF 1N SC59-3

SUSPSUSP

2

G

+1.8VS

D

S

R978
470_0805_5%

1 2

13

G

Q63
SSM3K7002BF 1N SC59-3

SUSP

2

FAN Control Circuit

R88
143K_0402_1%

20mil

EN_DFAN1[49]

C112
10U_0805_10V6K

R1601
143K_0402_1%

20mil

EN_DFAN2[49]

C1533
10U_0805_10V6K

+FAN1

+FAN2

+12VS

1

2

+12VS

1

2

1 2

R89
100K_0402_5%

1 2

1 2

R1602
100K_0402_5%

1 2

1

VOUT

2

VIN

3

VEN

4

VSET

1

VOUT

2

VIN

3

VEN

4

VSET

4.7U_0805_25V6-K

U3

GND
GND
GND
GND

Thermal Pad

G9941F11U_SO8

4.7U_0805_25V6-K

U92

GND
GND
GND
GND

Thermal Pad

G9941F11U_SO8

12

C110

5
6
7
8
9

C1531

5
6
7
8
9

12

+FAN1

2

C111
1000P_0402_50V7K

@

1

+FAN2

2

C1532
1000P_0402_50V7K

@

1

20mil

20mil

1A

1A

1
2
3

4
5

R90 10K_0402_5%

1

C113

0.01U_0402_25V7K

@

2

1
2
3

4
5

R1603 10K_0402_5%

1

C1534

0.01U_0402_25V7K

@

2

JFAN1

1
2
3

GND

GND

ACES_50273-0030N-001

CONN@

12

+3VS

FAN_SPEED1 [49]

JFAN2

1

2

3

GND

GND

ACES_50273-0030N-001

CONN@

12

+3VS

FAN_SPEED2 [49]

+5VALW

4 4

SUSP[5, 57]

SSM3K7002BF 1N SC59-3

SUSP#[49,54,55,56,57]

A

SUSP

B

R990
100K_0402_5%

1 2

Q73

13

D

2

G

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

C

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

DC-DC INTERFACE

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

E

of

51 64

0.1

A

B

C

D

B+

1 1

CONN@

ACES_88299-0610

8

GND

7

GND

6

6

5

5

4

4

3

3

2

2

1

1

JDCIN1

DC_IN_S1

12

PC113

0.1U_0402_25V6

12

PC2

220P_0402_50V7K

PL1

SMB3025500YA_2P

1 2

12

PC3

100P_0402_50V8J

12

PC4

100P_0402_50V8J

12

12

PC114

0.1U_0402_25V6

PC5
220P_0402_50V7K

PR153

1
2

0.01_2512_1%

4

VIN-VIN+

3

CPU_OT[49,53]

VL

PC1

.1U_0402_16V7K

12

PR2

@

@

PU1

1

VCC

2

GND

3

OT1

4

OT2

G718TM1U_SOT23-8

@

TMSNS1
RHYST1
TMSNS2
RHYST2

8
7
6
5

10K_0402_1%

1 2

12

PR1

20.5K_0402_1%

@

PR3

9.53K_0402_1%

@

1 2

12

PH1

@

100K_0402_1%_NCP15WF104F03RC

2 2

VIN+

3 3

PR834 0_0402_5%

+3VS

PR836
0_0402_5%

@

1 2

VIN_A1

PR831
0_0402_5%

1 2

12

PR830 0_0402_5%

1

PC805

2

0.1U_0402_16V7K
PR838 0_0402_5%

PR832
0_0402_5%

1 2

VIN_A0

PR841
0_0402_5%

@

1 2

1 2

1 2

PC806

1

2

+3VS

0.1U_0402_16V7K

PU803

1

VIN+

2

VIN-

3

GND

4

VS

HPA00900AIDCNR_SOT23-8

SDA

SCL

A1
A0

VIN_A1

8

VIN_A0VIN-

7

EC_SMB_DA2

6

EC_SMB_CK2

5

EC_SMB_DA2 [14,23,49]

EC_SMB_CK2 [14,23,49]

Current sense solution 2

JBATT1

Ventura for CPU side
slave address : 1000001
please placemnet near R-sense

+RTCBATT

1

+

2

-

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Re v

Tuesday, April 12, 2011

Date: Sheet

LOTES_AAA-BAT-054-K01

CONN@

Compal Electronics, Inc.

P51_PWR_DC-IN

PCA70 LA-7521P M/B

D

52 64

0.1

of

5

4

3

2

1

2VREF_8205

D D

PR10

13K_0402_1%

1 2

PR12

20K_0402_1%

1 2

8205_B+

PJ8

12

2

JUMP_43X118@

PC76

1U_0603_25V6K

112

12

PC7

2200P_0402_50V7K

+3VALWP

12

PC8

10U_1206_25V6M

SIS412DN-T1-GE3_POWERPAK8-5

PL2

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

1

+

PC14

2

330U_6.3V_M

5

PQ26

12

PR19

@

4.7_1206_5%

12

PC16

@

680P_0603_50V7K

4

123

5

4

SI7716ADN-T1-GE3_POWERPAK8-5
PQ25

123

CPU_OT[49,52]

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)

+5VALWP
Ipeak=7.376A ; 1.2Ipeak=8.85A; Imax=5.16A
f=300KHz, L=4.7UH,Rentrip=174k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vlimit=10*(10^-6)*174Kohm/10=0.174V
Ilimit=0.174/(18m*1.2)~0.174/(15m)=8.055~11.6A
Iocp=9.361~12.906A (9.361>8.85 -> OK)

1 2

PC12

.1U_0402_16V7K

PR24

1 2

0_0402_5%

@

B+

C C

B B

+3.3VALWP
Ipeak=5.71A ; 1.2Ipeak=6.852A; Imax=3.997A
f=375KHz, L=4.7UH
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-3.3)*(3.3/19)/(375KHz*4.7UH)=0.773A
Vlimit=10*10^-6*110Kohm/10=0.11V
Ilimit=0.11/(18m*1.2)~0.11/(15m)=6.34A~9.13A

A A

Iocp=7.113A~10.073A (7.113A>6.852A -> ok) -DVT-

PC10

4.7U_0805_10V6K

+3VLP

12

PR17

1 2

0_0603_5%

PR21

499K_0402_1%

1 2

B+

PR22

110K_0402_1%

BST_3V

UG_3V

LX_3V

LG_3V

12

100K_0402_1%

PR15

1 2

25

7
8

9
10
11
12

12

PC18

1U_0402_6.3V6K

PU2

P PAD

VO2
VREG3
BOOT2
UGATE2
PHASE2
LGATE2

2VREF_8205

PC6

FB3

ENTRIP2

6

13

8205_B+

12

1U_0603_10V6K

5

FB2

ENTRIP2

SKIPSEL

EN

14

4

TONSEL

15

3

REF

VIN16GND

12

2

17

12

PC20

0.1U_0603_25V7K

FB5

1

FB1

ENTRIP1

PGOOD

BOOT1
UGATE1
PHASE1

LGATE1

NC18VREG5

PC19

PR11

30K_0402_1%

1 2

PR13

20K_0402_1%

1 2

PR16

174K_0402_1%

ENTRIP1

1 2

24

VO1

23

BST_5V

22

UG_5V

21

LX_5V

20

LG_5V

19

RT8205EGQW_WQFN24_4X4

VL

4.7U_0805_10V6K

+3VALWP

12

PR18

0_0603_5%

1 2

8205_B+

12

PC11

2200P_0402_50V7K

PR202
10K_0402_1%

SPOK [61]

PC13
.1U_0402_16V7K

BST5ABST3A

1 2

SI7716ADN-T1-GE3_POWERPAK8-5

12

PC9

10U_1206_25V6M

+3VALWP +3VALW

5

4

SIS412DN-T1-GE3_POWERPAK8-5

123

5

4

PQ7

123

PJ402

2

112

JUMP_43X118@

PJ403

2

112

JUMP_43X118@

PQ2

PL3

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

12

PR20

@

4.7_1206_5%

12

@

PC17

680P_0603_50V7K

PC15

330U_6.3V_M

+5VALW+5VALWP

1

2

+5VALWP

+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

2

Date: Sheet

Compal Electronics, Inc.

P52-PWR-+3VALW/+5VALW

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

1

of

53 64

0.1

5

4

3

2

1

+1.05Vin_VCCIO

PC37

4.7U_0805_25V6-K

12

PC38

1 2

12

4.7U_0805_25V6-K

PR42

0_0402_5%

PR45

10_0402_5%

D D

PC39

UG_VCCIO
SW_VCCIO

LG_VCCIO

VCCIO_SEL [10]

PR38

1 2

0_0603_5%

12

1 2

0.22U_0603_25V7K

+5VALW

PC41
1U_0603_6.3V6M

PU6

1

VBST

PR39

PR40

SUSP#[49,51,55,56,57]

C C

B B

1 2

0_0402_5%

PC40

0.1U_0402_16V7K

102K_0402_1%

12

1 2

PR46

11.8K_0402_1%

1 2

EN_VCCIO

FB_VCCIO

RF_VCCIO

12

PR43

470K_0402_5%

PR44

5.1K_0402_1%

TRIP_VCCIO

12

2
3
4
5

TPS51212DSCR_SON10_3X3

1 2

13

D

PQ40

S

SSM3K7002FU_SC70-3

PGOOD
TRIP
EN
VFB
RF

PR165
75K_0402_1%

2

G

DRVH

V5IN

DRVL

BST_VCCIO

10
9
8

SW

7
6
11

TP

5

PQ5

4

TPCA8065-H_PPAK56-8-5

123

12

12

PQ6

3 5

241

TPCA8059-H_SOP-ADV8-5

VCCIO_SELECT +VCCIO

0

1

1.05V

1.0UH_PCMC104T-1R0MN_20A_20%

1 2

PR41

@

4.7_1206_5%

PC44

@

680P_0603_50V7K

1V

PL6

12

PC36

4.7U_0805_25V6-K

Vtrip range ==> 0.2V ~ 3V
<Vo=1.05V> VFB=0.7V

V=0.7*(1+5.1K/10.1958K)=1.05V
Fsw=290KHz

Cout ESR=10m ohm Rdson(max)=4.8 mohm Rdson(typ)=3.8 mohm.
Ipeak=17.3A, Imax=12.11A, Iocp=1.2*Ipeak=20.76A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=3.42A
=>1/2Delta I=1.71A
Vtrip=Itrip*Rtrip, Iocp=Vtrip/(8*Rds(on))
Iocpmax=((102K*11uA)/(8*0.0038))+1.71A=38.617A
Iocpmin=((102K*9uA)/(8*0.0048))+1.71A=25.616A
Iocp=25.616A~38.617A

PJ31

2

JUMP_43X118

@

112

B+

+1.05VS_VCCIOP

1

+

PC42

2

560U_2.5V_M

12

VCCIO_SENSE [8]

(17A,680mils ,Via NO.=34)

PJ5

+1.05VS_VCCIOP

A A

+1.05VSP

5

@

2

JUMP_43X118
PJ7

@

2

JUMP_43X118
PJ10

@

2

JUMP_43X118

PJ12

@

2

JUMP_43X118

112

112

112

112

+1.05VS_VCCIO

+1.05VS_VPCH

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2009/11/13 2009/04/28

Compal Secret Data

Deciphered Date

<Vo=1.0V> VFB=0.7V
V=0.7*(1+5.1K/11.8K)=1.0V
Fsw=290KHz

Cout ESR=10m ohm Rdson(max)=4.8 mohm Rdson(typ)=3.8 mohm.
Ipeak=17.3A, Imax=12.11A, Iocp=1.2*Ipeak=20.76A
Delta I=((19-1.0)*(1.0/19))/(L*Fsw)=3.266A
=>1/2Delta I=1.633A
Vtrip=Itrip*Rtrip, Iocp=Vtrip/(8*Rds(on))
Iocpmax=((102K*11uA)/(8*0.0038))+1.633A=38.54A
Iocpmin=((102K*9uA)/(8*0.0048))+1.633A=25.539A
Iocp=25.539A~38.54A

Compal Electronics, Inc.

Title

Size Document Number Re v

2

Date: Sheet

PCA60/70 LA-7001P M/B

Tuesday, April 12, 2011

+1.05VSP

1

of

54 64

0.1

5

D D

Maho@

Maho@

PR156

SUSP#[49,51,54,56,57]

C C

1 2

0_0402_5%

Maho@

PC146

0.1U_0402_16V7K

1 2

78.7K_0402_1%

12

1 2

PR157

PR170

10.2K_0402_1%

Maho@

EN_1.05V

FB_1.05V

RF_1.05V

12

Maho@

PR169

470K_0402_5%

PR166

5.1K_0402_1%

Maho@

TRIP_1.05V

12

4

PU9

Maho@

1

VBST

PGOOD

2

TRIP

DRVH

3

EN

4
5

SW

V5IN

VFB

DRVL

RF

TP

TPS51212DSCR_SON10_3X3

3

+1.05Vin

786

5

PL15

1 2

Maho@

Maho@

Maho@

Maho@

PC145

UG_1.05V
SW_1.05V

LG_1.05V

PR167

1 2

0_0603_5%

12

1 2

0.22U_0603_25V7K

+5VALW

PC144
1U_0603_6.3V6M

Maho@

BST_1.05V

10
9
8
7
6
11

4

578

3 6

PQ38

Maho@

AO4406AL_SO8

123

PQ39

Maho@

241

AO4456_SO8

1.0UH_PCMC104T-1R0MN_20A_20%

12

PR164

@

4.7_1206_5%

12

PC134

@

680P_0603_50V7K

PC148

4.7U_0805_25V6-K

12

PC147

Maho@

2

12

4.7U_0805_25V6-K

Maho@

PC136

4.7U_0805_25V6-K

1

PJ34

@

2

112

JUMP_43X118

12

B+

+1.05VSP

Maho@

1

+

PC135

2

330U_6.3V_M

Vtrip range ==> 0.2V ~ 3V
<Vo=1.05V> VFB=0.7V

V=0.7*(1+5.1K/10.2K)=1.05V
Fsw=290KHz

Cout ESR=10m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=7.3A, Imax=5.11A, Iocp=1.2*Ipeak=8.76A
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=3.42A
=>1/2Delta I=1.71A
Vtrip=Itrip*Rtrip, Iocp=Vtrip/(8*Rds(on))

B B

Iocpmax=((78.7K*11uA)/(8*0.0045))+1.71A=25.75A
Iocpmin=((78.7K*9uA)/(8*0.0056*1.3))+1.71A=13.871A
Iocp=13.871A~25.75A

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

2

Date: Sheet

Compal Electronics, Inc.

P54_PWR-+1.05VSP

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

1

of

55 64

0.1

5

4

3

2

1

+3VALW

Ipeak=1.26A, Imax=0.882A

Vo=0.8(1+Rt/Rb)=1.827 V

1

PJ6

PC63

1 2

1

2

2

12

12

@

PC52
.1U_0402_16V7K

JUMP_43X79@

D D

4.7U_0805_6.3V6K

PR25

0_0402_5%

SUSP#[49,51,54,55,57]

C C

1 2

47K_0402_5%@

PR70

+5VALW

PU4

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

FB=0.8V

12

PC27
1U_0402_6.3V6K

3

VOUT

4

VOUT

2

FB

GND

1

APL5930KAI-TRG_SO8

12

PR47

1.54K_0402_1%

12

PR82

1.2K_0402_1%

12

PC43

0.01U_0402_25V7K

+1.8VSP

12

PC58

22U_0805_6.3V6M

+1.8VSP +1.8VS

@

PJ27

2

112

JUMP_43X79

3.3A,140mils ,Via NO.= 7

Ipeak=8.8A

PC30

+5VALW

PR26

SUSP#[49,51,54,55,57]

1 2

0_0402_5%

12

PC31

.1U_0402_16V7K

@

PU5

1

EN

VCC

2

GND

DRV

FB3POK

APL5610CI-TRG_SOT23-6

6
5

1 2

4

10K_0402_1%

PR27

4.7U_0805_10V6K

12

+3VALW

VCCSA_PG [4 9]

4

786

5

IRF8736TRPBF_SO8

PQ3

123

12

PC28

4.7U_0805_6.3V6K

12

PJ30

2

JUMP_43X118

@

PC29

4.7U_0805_6.3V6K

+1.05VS_VCCIO

112

Imax=6.2A
Toatal Capacitor ??u
ESR=15mohm
Vout=0.8(1+Rt/Rb)

B B

1

PC33

1 2

47P_0402_50V8J
PR29

1 2

+3VALW

+3VALW

12

10K_0402_1%
PR34

12

PR37
1K_0402_1%

PR36

1 2

10K_0402_1%

A A

VCCSAP_VID1[9]

PQ4B

5

G

12

PC35
.1U_0402_16V7K

12

10K_0402_1%
PR33

PR35

1 2

34

10K_0402_1%

D

DMN66D0LDW-7_SOT363-6

S

12

PC34
.1U_0402_16V7K

12

49.9K_0402_1%
PR31

61

D

PQ4A

2

G

DMN66D0LDW-7_SOT363-6

S

4.7K_0402_1%

12

75K_0402_1%
PR32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

12

PR28

0_0402_5%

10_0402_5%

2

PR30

12

VCCSA_VID +VCCSAP

0

1

3

0.925V

0.85V

2010/01/25 2009/04/28

Compal Secret Data

+

PC32
330U_6.3V_M

Deciphered Date

+VCCSAP

VCCSA_SENSE [9]

2

PJ3

@

2

+VCCSAP +VCCSA

112

JUMP_43X118

(6A,240mils ,Via NO.= 12)

Title

Size Document Number Re v

Custom

Date: Sheet

+VCCSA/+1.8VSP

PCA60/70 LA-7001P M/B

1

of

56 64Tuesday, April 12, 2011

0.1

5

4

3

2

1

+1.5Vin

PC46

4.7U_0805_25V6-K

6
5
9

8
7

12

PU19

VCNTL
VIN
VIN

EN
POK

PC47

4.7U_0805_25V6-K

2

12

12

PC48

4.7U_0805_25V6-K

Vtrip range ==> 0.2V ~ 3V

Ipeak=10.24A Imax=7.168A
Iocp >=1.2*Ipeak=12.288A

<Vo=1.5V> VFB=0.7V
Vo=VFB*(1+Rtop/Rdown)=1.505V
Fsw=290 KHz
Cout ESR=15m ohm Rdson(max)=5.6m ohm, Rdson(typ)=4.5 mohm

Delta I=((19-1.5)*(1.5/19))/(1u*290 K)=4.764 A
=>1/2DeltaI=2.382A
Vtrip=Itrip*Rtrip, Iocp=Vtrip/(8*Rds(on))
Iocpmax=((76.8K*11uA)/(8*0.0045))+2.382A=25.848A
Iocpmin=((76.8K*9uA)/(8*0.0056*1.3))+2.382A=14.25A
Iocp=14.25A~25.48A

3

VOUT

4

VOUT

2

FB

GND

APL5930KAI-TRG_SO8

1

D D

PC49

UG_1.5V
SW_1.5V

LG_1.5V

PR48

1 2

0_0603_5%

12

1 2

0.22U_0603_25V7K

+5VALW

PC51
1U_0603_6.3V6M

PR214

@

0_0402_5%

SUSP#

SUSP#[49,51,54,55,56]

SYSON[49]

C C

1 2

PR50

1 2

0_0402_5%

PC50

0.1U_0402_16V7K

PR53

10K_0402_1%

1 2

1 2

143K_0402_1%

12

PR49

EN_1.5V

FB_1.5V

RF_1.5V

12

PR52
470K_0402_5%

PR54

1 2

11.5K_0402_1%

TRIP_1.5V

PU7

1

VBST

PGOOD

2

TRIP

DRVH

3

EN

4
5

V5IN

VFB

DRVL

RF

TPS51212DSCR_SON10_3X3

BST_1.5V

10
9
8

SW

7
6
11

TP

+1.5VP

4

PQ9

4

PJ20
JUMP_43X118

112

PJ23
JUMP_43X118

112

5

PQ8

SIS412DN-T1-GE3_POWERPAK8-5

123

5

FDMC7692S_MLP8-5

123

2

2

+1.5V

1.0UH_PCMC104T-1R0MN_20A_20%

1 2

12

PR51

4.7_1206_5%

12

PC54

680P_0603_50V7K

PL7

12

PC45

4.7U_0805_25V6-K

(12A,480mils ,Via NO.= 24)

PR210

0_0402_5%

+1.5V

1

PJ38

1

JUMP_43X79

@

2

2

12

PC161

4.7U_0805_6.3V6K

12

12

PR213

PC162

47K_0402_5%@

0.1U_0603_25V7K

@

Compal Secret Data

Deciphered Date

+5VALW

12

PC160
1U_0402_6.3V6K

+1.5V

B B

4.7U_0805_6.3V6K

PR56

0_0402_5%

SUSP[5,51]

1 2

PC61

0.1U_0402_16V7K

1

PJ33

1

JUMP_43X79

2

2

12

PC55

13

D

2

G

12

PQ10

S

SSM3K7002FU_SC70-3

PR55

1K_0402_1%

PR59

1K_0402_1%

12

12

PC59

0.1U_0402_16V7K

12

PU8

1

VIN

2

GND

3

VREF

4

VOUT

APL5336KAI-TRL_SOP8P8

+0.75VP

12

PC60
10U_0805_6.3V6M

VCNTL

8

NC

7

NC

6
5

NC

9

TP

+3VALW

12

PC56
1U_0603_6.3V6M

SUSP#

SUSP#[49,51,54,55,56]

1 2

Imax=1.4A
Ipeak=2A

A A

@

PJ9

2

+0.75VP +0.75VS

(2A,80mils ,Via NO.= 4)

5

112

JUMP_43X79

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/01/25 2009/04/28

3

PJ32

2

112

JUMP_43X118

B+

+1.5VP

1

+

PC53
330U_6.3V_M

2

Imax=0.39A
Ipeak=0.558A

12

12

PR212

12K_0402_1%

12

PR211

24K_0402_1%

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

1.5VP/+1.2VALWP/+0.75VS

PCA60/70 LA-7001P M/B

PC158

0.01U_0402_25V7K

1

+1.2VUSB

12

PC159

22U_0805_6.3V6M

of

57 64Tuesday, April 12, 2011

0.1

A

1 1

VSSSENSE[8]

VCCSENSE[8]

+CPU_CORE

2 2

TSENSE

12

12

PR96

8.25K_0402_1%

8.25K_0402_1%

12

PR103

UMA@

DIS@

PC81

0.1U_0402_25V6

+5VALW

TSENSEATSENSEA

12

PC84

0.1U_0402_25V6

UMA@

1 2

PC807 0.1U_0402_16V4Z

PH3

1 2

100K_0402_1%_NCP15WF104F03RC

PH4

1 2

UMA@

PR103

100K_0402_1%_NCP15WF104F03RC

3 3

0_0402_5%

VR_ON_R

100_0402_1%

1 2

PR99 2.2_0603_5%

Vin

PR102 1K_0402_1%

PR107

DIS@

0_0402_5%

VSS_AXG_SENSE[9]

VCC_AXG_SENSE[9]

+GFX_CORE

ESD request Close to PU10.9

4 4

PR85

100_0402_1%

1 2

1 2

PR87

1 2

+1.05VS_VCCIO
+1.05VS_VCCIO

B

0_0402_5%
PR86

1 2

PR89 0_0402_5%

1 2

PR93 54.9_0402_1%

+1.05VS_VCCIO

+3VS

VR_ON[49]

1 2

PC82 1U_0603_6.3V6M

1 2

PC83 0.01U_0402_50V7K

UMA@

PR107
100_0402_1%

1 2

1 2

PR113
100_0402_1%

UMA@

1 2

47_0402_1%

VR_HOT#[ 49]

PR88 51_0402_5%

1 2

PR92 110_0402_1%

1 2
1 2
1 2

PR94 75_0402_1%

1 2

PR97 10K_0402_1%

1 2

PR98 0_0402_5%

PR108

0_0402_5%

1 2

0_0402_5%

PR175

1 2

PR112
0_0402_5%

UMA@

PR67

PR73
1K_0402_1%

12

PC77
1000P_0402_50V8-J

VR_SVID_DAT[8]
VR_SVID_CLK[8]

VR_SVID_ALRT#[8]

VGATE[15, 49]

PR100 9.09K_0402_1%

12

12

PC87
1000P_0402_50V8-J

DIS@

UMA@

C

PC66

220P_0402_50V8J

1 2

5.49K_0402_1%

12

1 2

2.8K_0402_1%
PR79

TSENSE

VR_ON_R

1 2

TSENSEA

GFX OCP:42A

1 2

PR68

1 2

10P_0402_50V8J

1 2

412_0402_1%

12

12

412_0402_1%

12

PC67

1000P_0402_50V7K

1 2

PC69

4700P_0402_25V7K

PR77

1 2

1.5K_0402_1%

PC73

PR80

4700P_0402_25V7K

DIFFOUT

53

PU10

1

VSP

FLAG / GND

2

TSENSE

3

VR_HOT#

4

SDIO

5

SCLK

6

ALERT#

7

VR_RDY

8

VR_RDYA

9

ENABLE

10

VCC

11

ROSC

12

VRMP

13

TSENSEA

PR109
887_0402_1%

UMA@

UMA@

PR114

4700P_0402_25V7K

1 2

PR116

1 2

1.24K_0402_1%

UMA@

PC93
4700P_0402_25V7K

UMA@

PR69

95W@

36.5K_0402_1%

220K_0402_5%_ERTJ0EV224J

PR69 24K_0402_1%

1 2

PC71

DIFFOUT

49

52

50

51

FB

VSN

TRBST

DIFFOUT

95W@

NCP6151S52MNR2G_QFN52_6X6

NCP6131S52MNR2G_QFN52_6X6

FBA16VSNA

15

14

FBA

DIFFOUTA

PC88

12

UMA@

PC89

12

PR176 0_0402_5%DIS@

FBA

PR126

UMA@

D

CPU CORE OCP: 90A-----65W
136A----95W

CSSUM

PR63 75K_0402_1%

48

COMP

65W@

18

2200P_0402_50V7K

4.02K_0402_1%

220P_0402_50V8J

47_0402_1%

PU10

47

ILIM

COMPA19DIFFOUTA17VSPA

UMA@

12

1 2

PR115

UMA@

PC95

1 2

UMA@

1 2

DIFFOUTA

CSCOMP

12

65W@

PR71

PC72

1500P_0402_50V7K

CSCOMP

CSSUM

45

44

46

CSSUM

DROOP

CSCOMP

CSCOMPA

DROOPA21IOUTA

ILIMA20TRBSTA

22

CSCOMOA

UMA@

UMA@

1 2

10P_0402_50V8J

PC90

1 2

26.7K_0402_1%

PR117

1 2

PR125 1K_0402_1%UMA@

220K_0402_5%_ERTJ0EV224J

DIS@

0_0402_5%

1 2

1 2

12

1 2

PR121

1K_0402_1%

43

IOUT

23

PR120

UMA@

PH2

12

PC92 820P_0402_50V7K

1K_0402_1%

12
12

PR72

10_0402_1%

PR74 4.7K_0402_1%

8.2K_0402_1%

65W@

PC75

PR83 24K_0402_1%

1000P_0402_50V8-J

1 2

CSREF

41

40

42

CSP4

CSN4

CSN2

CSREF

CSP2
CSN3
CSP3
CSN1
CSP1

DRON

PWM1/ADDR

PWM3/IMAX

PWM2/VBOOT

PWM4

PWMA/IMAXA

VBOOTA

CSSUMA

CSPA25CSNA

24

26

CSSUMA

12

PC86

0.047U_0402_16V7K
24K_0402_1%UMA@

UMA@

.1U_0402_16V7K

UMA@

PR122

10_0402_1%

1 2

PR121 1.82K_0402_1%UMA@

3.3K_0402_1%

PR127

75K_0402_1%

CSCOMOA

PH5

UMA@

PR64 165K_0402_1%

1 2

PC65 470P_0402_50V7K

1 2

PC68 1200P_0402_50V7K

820P_0402_50V7K

1 2

12

PC70

PR78

12

PC74

0.1U_0402_25V6K

1 2

1 2

PR184
0_0402_5%

65W@

1 2

39
38
37
36
35
34
33
32
31
30
29
28
27

1 2

PR179

0_0402_5%

DIS@

1 2

PC85
1000P_0402_50V8-J

1 2

UMA@

12

UMA@

0_0402_5%
PR178

DIS@

1 2

PR111

PR110 6.98K_0402_1%

12

12

PC91

PC94

820P_0402_50V7K

12

1 2

PR124

12

UMA@

UMA@

UMA@

PR128

12

165K_0402_1%

12

1 2

680P_0402_50V7K

1 2

1200P_0402_50V7K

UMA@

PR177

1 2

0_0402_5%

DIS@

E

12

PC133

12

0.047U_0402_16V7K

95W@

PR185

0_0402_5%

1 2

65W@

12

0.047U_0402_16V7K
PC79

PR91 6.98K_ 0402_1%

DRVON [59]

DIS@

12

PR1010_0402_5%

PR104
10K_0402_1% UMA@

CSNA_A

UMA@

UMA@

CSNA_A

39.2K_0603_1%

CSSUMA C SPA

12

PC97

UMA@

PC98

PR62

12

95.3K_0603_1%
PR65

12

95.3K_0603_1%
PR66

12

95.3K_0603_1%
PR152

12

95.3K_0603_1%

95W@

12

PR75 10_0402_1%

12

10_0402_1%

PR76

12

10_0402_1%

PR81

PR154

95W@

95W@

6.98K_0402_1%
PR151

1 2

0_0402_5% 95W@

1 2

PR171

12

0.047U_0402_16V7K
PC78

1 2

PR90 6.98K _0402_1%

1 2

12

PC80

0.047U_0402_16V7K
PR95 6.98K_0402_1%

+5VALW

PR180

0_0402_5%

1 2

UMA@

CSPA

PR111

DIS@

0_0402_5%

PR129

12

UMA@

CSP1

CSP2
CSP3

CSP4

CSN1
CSN2
CSN3

12

10_0402_1%

CSP4

CSN2

CSP2

CSN3

CSP3

CSN1

CSP1

1 2

PWM1 [59]
PWM3 [59]
PWM2 [59]

IMAX

PWMA [59]

CSNA [59]

CSPA [59]

Iout_MAX=35A

CSN4

CSP4 [59]

CSN4 [59]

95W@

0_0402_5%

1 2

F

CSN1 [59]

CSP1 [59]

PR181

PR83

95W@

24.3K_0402_1%

CSN3 [59]

CSP3 [59]

65W CPU IMAX=75A

95W CPU IMAX=112A

CSN2 [59]

CSP2 [59]

PWM4 [59]

G

PWM3

VCORE
VBOOT
SET AT
0V

VCORE
VBOOT
SET AT
0V

PWM
ADDRESS

65W@

12

PR119

10K_0402_1%

PWM2 PWMA

95W@

12

PR105

10K_0402_1%

PWM1

12

PR118
10K_0402_1%

V_GT
IMAX SET
AT 35A

VCORE
IMAX SET
AT 112A

IMAX

VCORE
IMAX SET
AT 75A

H

95W@

88.7K_0402_1%

12

PR106

27.4K_0402_1%

UMA@

PR119

12

65W@

59K_0402_1%
PR174

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

E

2010/01/25 2009/04/28

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

Size Docum e nt N u m be r Re v

C

Date: Sheet

G

CPU_CORE_1

PCA60/70 LA-7001P M/B

58 64Tuesday, April 12, 2011

H

of

0.1

5

4

3

2

1

VIN

VIN

PR132

D D

65W@

2.74K_0402_1%

PWM1[58] PWM2[58]

95W@

PR132 4.02K_0402_1%

+5VALW

1 2

12

PR133

2.2_0603_1%

PR130

2.2_0603_1%

12

DRVON [58]

12

PC107
1U_0603_25V6K

1
2
3
4

PC99

1 2

0.22U_0603_25V7K

PU11

BST

FLAG

PWM

DRVH

EN

SW

VCC

GND

DRVL

NCP5911MNTBG_DFN8-9

TPCA8065-H_PPAK56-8-5

9

DH_CPU1

8

LX_CPU1

7
6

DL_CPU1

5

PQ12

PQ16

5

4

123

5

4

123

4

DH_CPU1

PQ17

4

TPCA8059-H_PPAK56-8-5

TPCA8065-H_PPAK56-8-5

5

PQ13

@

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

123

5

PR173

1 2

123

TPCA8059-H_PPAK56-8-5

12

12

PC100

PL8

1
2

CSP1[58] CSN1[58]

4.7_1206_5%

PC150

1U_0603_25V6K

12

PC101

10U_1206_25V6M

4
3

12

PC102
10U_1206_25V6M

+CPU_CORE

DRVON[58]

65W@

2.74K_0402_1%

95W@

PR134 4.02K_0402_1%

+5VALW

PR134

12

PR135

2.2_0603_1%

PR131

2.2_0603_1%

1 2

12

12

PC103

1 2

0.22U_0603_25V7K

PU12

1

BST

2

PWM

3

EN

4

VCC

NCP5911MNTBG_DFN8-9

PC108
1U_0603_25V6K

FLAG

DRVH

GND

DRVL

TPCA8065-H_PPAK56-8-5

PQ14

9

DH_CPU2

8

LX_CPU2

7

SW

6

DL_CPU2

5

4

PQ18

4

5

123

5

123

TPCA8059-H_PPAK56-8-5

TPCA8065-H_PPAK56-8-5

5

PQ15

@

4

DH_CPU2

123

5

PQ19

4

123

TPCA8059-H_PPAK56-8-5

12

12

PC105

PC104

1U_0603_25V6K

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1
2

4
3

PL9

PR172

1 2

4.7_1206_5%

CSP2[58] CSN2[58]

12

12

PC106
10U_1206_25V6M

10U_1206_25V6M

+CPU_CORE

PC149

C C

VIN

1000P_0603_50V7K

1000P_0603_50V7K

PR137

5

123

5

123

1

+

PC126

68U_25V_M

2

VIN

95W@

TPCA8065-H_PPAK56-8-5
PQ36

5

@

12

12

12

PC130

PC129

4

DH_CPU4

123

5

PQ29

4

1 2

TPCA8059-H_PPAK56-8-5

123

TPCA8059-H_PPAK56-8-5

12

95W@

1U_0603_25V6K

10U_1206_25V6M

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1
2

4
3

+CPU_CORE

PL11

95W@

PR183

95W@

4.7_1206_5%

CSP4[58] CSN4[58]

PC152

95W@

1000P_0603_50V7K

1

+

PC153

68U_25V_M

2

Title

Size Document Number Re v

Custom

Date: Sheet

VIN

Compal Electronics, Inc.

CPU_CORE_2

59 64Tuesday, April 12, 2011

1

PC118
10U_1206_25V6M

of

0.1

TPCA8065-H_PPAK56-8-5

65W@

2.74K_0402_1%

PWM3[58]

95W@

+5VALW

2.2_0603_1%

DRVON [58]

PR137

PR138

2.2_0603_1%

1 2

4.02K_0402_1%

12

12

PR136

12

PC109

1 2

0.22U_0603_25V7K

PU13

1

BST

2

PWM

3

EN

4

VCC

NCP5911MNTBG_DFN8-9

PC117
1U_0603_25V6K

FLAG

DRVH

GND

DRVL

TPCA8065-H_PPAK56-8-5

9

DH_CPU3

8

LX_CPU3

7

SW

6

DL_CPU3

5

PQ20

PQ22

5

4

123

5

4

123

B B

5

PQ21

@

PC110

4

DH_CPU3

PQ23

5

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

123

4

PR182

1 2

TPCA8059-H_PPAK56-8-5

123

4.7_1206_5%

TPCA8059-H_PPAK56-8-5

CSP3[58] CSN3[58]

12

PC151

1000P_0603_50V7K

12

1
2

1U_0603_25V6K

PL10

12

PC111

10U_1206_25V6M

4
3

12

PC112
10U_1206_25V6M

+CPU_CORE

PWM4[58]

95W@

PR149 4.02K_0402_1%

+5VALW

PR150

2.2_0603_1%

DRVON [58]

95W@

95W@

12

2.2_0603_1%

1 2

12

PR148

12

95W@

PC132
1U_0603_25V6K

95W@

PC131

1 2

0.22U_0603_25V7K

PU14

1

BST

FLAG

2

PWM

DRVH

3

EN

SW

4

VCC

GND

DRVL

NCP5911MNTBG_DFN8-9

95W@

TPCA8065-H_PPAK56-8-5

9

DH_CPU4

8

LX_CPU4

7
6

DL_CPU4

5

PQ37

95W@

4

PQ34

4

95W@

VIN

PC119

UMA@

UMA@

PR142

2.2_0603_1%

49.9_0402_1%

12

PR144

2.2_0603_1%

UMA@

1 2

12

12

PWMA[58]

PR143

UMA@

+5VALW

A A

DRVON [58]

1 2

PU15

1

BST

2

PWM

3

EN

4

VCC

NCP5911MNTBG_DFN8-9
PC127
1U_0603_25V6K

0.22U_0603_25V7K

9

FLAG

8

DRVH

7

SW

6

GND

5

DRVL

UMA@

DH_GFX
LX_GFX

DL_GFX

UMA@

5

PQ28

PQ30

5

UMA@

4

4

UMA@

UMA@

123

TPCA8065-H_PPAK56-8-5

PQ31

5

5

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

4

CSPA[58]

UMA@

4

123

TPCA8059-H_PPAK56-8-5

CSNA[58]

123

TPCA8059-H_PPAK56-8-5

PC120

1
2

12

PL13

12

PC121

1U_0603_25V6K

12

PC122
10U_1206_25V6M

10U_1206_25V6M

4

+GFX_CORE

3

UMA@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

B+

10U_1206_25V6M

2010/01/25 2009/04/28

3

HCB4532KF-800T90_1812

PL12

1 2

HCB4532KF-800T90_1812

PL14

1 2

12

PC123

Compal Secret Data

Deciphered Date

1

+

PC124

68U_25V_M

2

1

+

PC125

68U_25V_M

2

2

5

4

3

2

1

DIS@

PR160

0_0402_5%

10_0402_5%

PR58

HCB4532KF-800T90_1812

DIS@

PL21

1

+

PC141

2

560U_2.5V_M

DIS@

ESR=10m ohm

DIS@

12

12

1

+

2

VGA_SENSE [23]

PC143

DIS@

B+

+VGA_CORE

560U_2.5V_M

+VGA_Vin

+3VS

0.22U_0603_25V7K

12

PC62
1U_0603_6.3V6M

DIS@

PR228

DIS@

10K_0402_1%

TPCA8065-H_PPAK56-8-5

DIS@

PC57

1 2

+5VALW

TPCA8057-H_PPAK56-8-5

GPU_VID1 [22]

PQ11

DIS@

PQ32

PQ33

4

UG_VGA

PQ35

4

DIS@

5

TPCA8065-H_PPAK56-8-5

DIS@

123

5

123

TPCA8057-H_PPAK56-8-5

0.36UH_MMD-12CE-R36M-M1L_34A_20%

12

12

5

4

123

5

4

123

DIS@

Vtrip range ==> 0.2V ~ 3V
VFB=0.7V

V=0.7*(1+Rtop/Rbottom)
Fsw=350KHz

Cout ESR=12m ohm Rdson(max)=3.2 mohm Rdson(typ)=2.6 mohm.
Ipeak=41.02A, Imax=28.714A, Iocp=43A
Delta I=((19-0.9)*(0.9/19))/(L*Fsw)=6.8A
=>1/2Delta I=3.4A
choose Rcs=75K
Iocpmax=((75K*11uA)/0.0013)+3.4A=75.52A
Iocpmin=((75K*9uA)/(0.0016*1.35))+3.4A=48.42A
Iocp=48.42A~75.52A

GPU_VID1

D D

VGA_PWROK[18]

PR60

PR163

12

PR61

16K_0402_1%

12

82K_0402_1%

1 2

53.6K_0402_1%

DIS@

FB_VGA

12

PR162
470K_0402_5%

PR57

2.87K_0402_1%

DIS@

1 2

DIS@

12

PR231

PQ47A

DMN66D0LDW-7_SOT363-6

DIS@

61

D

S

DIS@

PR158

DGPU_PWR_EN[17,26]

C C

GND_SENSE[23]

B B

1 2

150K_0402_1%

DIS@

PC140

0.1U_0402_16V7K

DIS@

10_0402_5%

(Default)

TRIP_VGA

EN_VGA

RF_VGA

DIS@

12

G

DIS@

13.3K_0402_1%

DIS@

2

12

12

DIS@

DIS@

10K_0402_1%

10K_0402_1%

PR235
100K_0402_5%

DIS@

PU16

1

VBST

PGOOD

2

TRIP

DRVH

3

EN

4
5

PR225

SW

V5IN

VFB

DRVL

RF

TP

TPS51212DSCR_SON10_3X3

DIS@

12

DIS@

34

D

5

PQ47B

G

S

DMN66D0LDW-7_SOT363-6

+3VS

12

PR234

PR233

12

DIS@

PC178

4700P_0402_16V7K

10
9
8
7
6
11

DIS@

12

10K_0402_1%

BST_VGA

UG_VGA
SW_VGA

LG_VGA

PR226

DIS@

PC177

4700P_0402_16V7K

GPU_VID0 [22]

DIS@

PR161

1 2

2.2_0603_5%

+3VS

12

12

12

12

12

PC139

PC137

10U_1206_25V6M

DIS@

1 2

DIS@

PR159

@

4.7_1206_5%

PC138

@

680P_0603_50V7K

10U_1206_25V6M

PL20

DIS@

PC142

10U_1206_25V6M

DIS@

1 2

N12P-GS Performance Mode

GPU_VID0

NVIDIA/N12P-GS

0 0 0.825V
0

1

0.85

01

0.975

1

1

1.00

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/01/25 2009/04/28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

2

Date: Sheet

VGA_CORE

PCA60/70 LA-7001P M/B

1

0.1

of

60 64Tuesday, April 12, 2011

5

4

3

2

1

D D

C C

PJ11

+12V_B+

112

JUMP_43X79

@

SPOK[53]

2

12

PC22

0.1U_0603_25V7K

PR842 0_0402_5%

1 2

12

12

PC23

4.7U_0805_25V6-K

PC24

4.7U_0805_25V6-K

12V_EN_R

12

PC115

470P_0402_50V7K

B+

PR146

0_0603_5%

1 2

BOOT_12V

PU3

1

BOOT

2

VIN

3

EN

4

SS

TPS54331DR_SO8

12

PC64

0.01U_0402_16V7K

VFB=0.8V

BOOT_12V_1

GND

COMP

VSENSE

PH

PC21

0.1U_0603_25V7K

1 2

8
7
6
5

FB_12V

PR145

2.1K_0402_1%

PH_12V

10UH_PCMB063T-100MS_4A_20%

12

PD1

S SCH DIO SX34 SMA

PC26

15P_0402_50V8J

1 2

1 2

PC116

180P_0402_50V8J

1 2

12

PR141

30K_0402_1%

PL4

1 2

1 2

PR140

226K_0402_1%

Imax=1.862A
Ipeak=2.66A

1

+

PC25

2

100U_25V_M

12

PC128

330P_0402_50V7K

+12VALWP

PJ13

@

+12VALWP +12VALW

2

JUMP_43X118

112

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

2

Date: Sheet

Compal Electronics, Inc.

P60_PWR-+12V

PCA70 LA-7521P M/B

Tuesday, April 12, 2011

1

of

61 64

0.1

NO DATE PAGE MODIFICATION LIST PURPOSE

----------------------------------------------------------------------------------------------------------------------------------------

2010/09/301 Modify OCP setting value

P48~49 Change PR39 to 118k ohm

Change PR49 to 95.3k ohm

2 2010/10/01 P48 Remove reserved 1.05VP power rail

PC124,PC125 change to 220u_25V

3 2010/10/28 P50

4 2010/10/28 P49

5 2010/10/28 P49

2010/10/286 P49

Remove PC126

Remove PR70, PR82, PR84, PR171, PR172, PR173,
PR174, PC76

PR62, PR65, PR66 change to 90.9K_0603_1%
PC72 change to 1500P_0402_50V

PR129 change to 39.2K_0603_1%
PR117 change to 25.5k_0402_1%

Because VCCIO will not be changeable voltage on
Sandy Bridge platform. We don't need another 1.05V
for PCH

Modify for input cap

Remove forth phase related components

Change for correct droop setting

Change for correct GT droop setting

PC92 change to 220P_0402_50V

7 2011/01/27 P58 update Net name "IMAX " update after vender review layout

2011/01/27

8

2011/01/27

9

10 2011/02/09 P52

P61

P59

change PC25 part number to SF000004S00

change PC124/125/126/153 part number from
SF000004L00 to SF000004M00

material shoretage

material shoretage

add "@" at BOM structure of PR836 and PR841 change for EC

11 2011/02/16 P53 change PU2 part number to SA00004NY00 change for part EOL

P602011/03/0712

change PR60 from 75Kohm to 53.6Kohm change for OCP setting point

2011/03/07 P57 change PR49 from 76.8Kohm to 143Kohm change for OCP setting point

13 2011/03/25 P60 change BOM structure PQ11 from @ to DIS@ for Thermal team concern

P602011/03/3014

Remove VGA_core Jump for impedence concern

change PR153 from 15m ohm to 10m ohm for Inrush concernP522011/03/3015

2011/03/3016 P59

2011/03/3017

18 2011/04/06 P52

change PC124/125/126/153 part number from
SF000004M00 to SF000004T00

change PC101/102/105/106/111/112/118/121/122/123/130/137/139/142
part number from SE142106K80 to SE142106M80

Remove JDCIN1 pin.7 and pin.8 from GND Layout modification

19 2011/04/08 P58 add PC807 at PU10.9 for ESD request

change PR68=5.49Kohm, PC67=1nF, PR62=PR65=PR66=PR152=95.3Kohm, PC65=470pF,
PC69=10pF, PC66=220pF, PR80=1.5kohm, PR79=2.8kohm, PR129=39.2Kohm, PC88=2.2nF,
PC97=680pF, PC90=10pF, PC95=220pF, PR116=1.24kohm, PR109=887ohm, PC92=820pF

20 2011/04/08 change PC141/PC143 part number to SF000002P00

P60

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Rev

Date: Sheet

Compal Electronics, Inc.

Power PIR

PCA70 LA-7521P M/B

of

62 64Tuesd ay, Apr il 12, 2011

0.1

5

4

3

2

1

HW PIR (Product Improve Record)

NWQAA LA-6062P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2009/12/30
NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------------------------

D D

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DR AWING IS TH E PROPRIETARY PR OPERTY OF COMPAL ELECTRON ICS, INC . AND CON TAINS CON FIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF TH E COMPETENT DI VISION O F R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC . NEITHER THIS SHEET NO R THE INF ORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITH OUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRON ICS, INC .

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

2

Date: Sheet

HW-PIR

PCA70 LA-7521P M/B

1

0.1

of

63 64Tuesday, April 12, 2011

5

4

3

2

1

0.885V

5V

112A

0.95V

+VGA_COREP

+1.5VP

+1.05VS_VCCIOP

(Maho Bay)

+3VALWP

+5VALWP

+12VALWP

B+

NPC6151(95W/UMA)

19V

Adapter

D D

B+

19V

NPC6131(65W/DIS)

B+

TPS51212

B+

TPS51212

B+

TPS51212

B+ +1.05VS_VSP

TPS51212
(Maho Bay)

B+

RT8205L

0.975V

35.32A

1.5V

10.24A

1.05V

17.3A

1.05V

7.3A

3.3V

5.71A

7.37A

C C

B+

B+

TPS54331

Converter

12V

2.66A

35A

+CPU_CORE

+GFX_CORE

1.5V

1.5V

APL5930

1.05V

3.3V

APL5336

1.2V

0.558A

0.75V

APL5610

APL5930

+1.2VUSB

+0.75VP

2A

0.925V

+VCCSAP

8.8A

1.8V

+1.8VSP

1.26A

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIET ARY PROPERTY O F COMPAL ELEC TRONI CS, INC. AND CONTAINS CONFIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHE R THIS SHEET NOR THE INFORMATI ON IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRONIC S, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

2011/11/012010/10/28

2

Title

Power Rail

Size Document Number Rev

Date: Sheet

1

of

64 64Tue s d a y , Ap r il 12, 2011

0.1