Compal LA-7521P PCA70, LA-7522P PCA61 Schematic

A

1 1

B

C

D

E

PCA70/61

2 2

LA-7521P

Sugar Bay

REV 0.2

Schematic

3 3

LA-7522P REV 0.1

Intel Processor(Sandy Bridge) / PCH(Cougar Point)

Tuesday, April 12, 2011 Rev 0.2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

PCA70 LA-7521P M/B

164Tuesday, April 12, 2011

E

0.1

of

A

DDR3 VRAM
512M/1GB(GV)
1GB/2GB(GS)

1 1

HDMI(IFPE)

VGA Chip

NV N12P-GV
NV N12P-GS(default)

B

PCI-Express 16X

HDMI
(IFPC)

C

Intel CPU
Sandy Bridge
Desktop

LGA1155

D

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333 MT/s

E

204pin DDRIII-SO-DIMM X2

H1

2 ch. LVDS
Conn.

LVDS I/F

Scale

RTD2482D

FDI X8

2.7GT/s

DDPC

DMI X4

5GT/s

USB 2.0 X 6

USB-Port 0 USB-Port 1

USB-Port 2

0.3MP CAM (1.3M reserve)
w/ DMic & ALS

Touch Panel

L1

SPI ROM

HDMI IN conn.

2 2

D-sub IN conn.

HDMI OUT conn.

LAN

RJ45

RTL8111E 10/100/1G
PCIe Mini Card

WLAN
Card reader IC

conn.

3 3

(SD/MMC/SDHC)

CIR

SPI

HDMI
RGB

EC
ENE KB930

DDPD

Intel PCH
Cougar Point
H61

SATA port 0

SATA port 1

USB 2.0
PCI-E

PCIe 1x

3.5" SATA HDD Conn.

SATA ODD Conn.

TV Tuner Card
USB3.0 Controller

USB 3.0

USB-Port 3

ASM1042

PCIe 1x

PCIe 1x

FCBGA-942

JMB3853 in 1 CardReader

PCIe 1x

LPC BUS

USB 2.0 X2 (reserve)

USB 2.0
SATA port 4

HD Audio

5.1ch HDA Audio Codec

ALC663

USB-Port 4

USB-Port 5
& eSATA

D-Mic.

MIC Jack

H1L1

SPI ROM

SPI

LFEOUT

FRONT

HPOUT

SPDIFOUT

C C

SPK AMP

EUA2113

4 4

2.5mm jack
for 10W woofer

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

C

Compal Secret Data

Deciphered Date

C C

EUA2113

6W SPK *2
Conn

D

Date: Sheet

C C

HP/SPDIF JackSPK AMP

Title

Size Document Number Rev

Compal Electronics, Inc.

Block Diagram

PCA70 LA-7521P M/B

264Tuesday, April 12, 2011

E

of

0.1

5

PU16

TPS51212DSCR

Bead

D D

NCP5911MNTBG

PU6

+1.05VS_VCCIOP

PU11~PU15

VIN

TPS51212DSCR

PU9

TPS51212DSCR

+5VALWP

JDCIN1

B+

JUMP

8205_B+ PU2

RT8205EGQW

+3VALWP

+VGA_COREP

+CPU_CORE

+GFX_CORE

+1.05VSP

4

JUMP

JUMP

JUMP

JUMP

JUMP

JUMP

+VGA_CORE

+1.05VS_VCCIO

+1.05VS_VPCH

+5VALW

+3VALW

PU6

APL5930KAI

APL5610CI

AP4800BGM

+1.8VSP

PU5

+VCCSAP +VCCSA

+1.05VGS

U63

3

JUMP

AP4800BGM

Q61

+5VS

2

+CPU_CORE

+GFX_CORE

+1.8VS

+1.05VS_VCCIO

1.5V

+VCCSA

+12VS

+5VS

1

Intel Sandy Bridge

CPU

SATA HDD

JUMP

+1.8VS

+0.75VS

+1.8VS

+1.05VS_VPCH

+3VALW
+3VS

+5VALW
+5VS

+1.5VGS

+1.05VGS

+1.5VGS

+VGA_CORE

+3VGS

MOS

+5VS

SATA ODD

+12VS

+12VS

+5VS

+1.5V

+3VS

Audio codec

ALC663

FAN1

FAN2

FAN3

DDR3 SODIMM X 4

Intel Gougar Point

PCH

VRAM X 8

N12P-GT-A1

VGA

+3VS+5VS

+5VS

HDMI-OUT

Title

Size Docum e nt N u m be r Re v

Date: Sheet

+RTCVCC

Battery

Media card
controller

RTC

JMB385

+3VS

+3VS

Bluetooth

Compal Electronics, Inc.

Power Tree

PCA70 LA-7521P M/B

1

LVDS

ASM1442

+3VS

CAM

364Tuesday, April 12, 2011

+3VS

of

0.1

PU7

TPS51212DSCR

C C

PU3

TPS54331DR

+12VALWP

JUMP

+1.5VP

MOS

JUMP

+1.5VS

+1.5V

U65

AP4800BGM

+1.5VGS

Q60

AP4800BGM

+3VS

PU6

APL5930KAI

+0.75VP

JUMP

+0.75VS

+1.5V

PU19

APL5930KAI

+1.2VUSB

+12VALW

+12VS

B+

LCD

Converter

MOS

+3VS

AMP X 2
EUA2113

B B

+USB_VCCB

USB2.0 X 3

USB3.0 X 2

+USB_VCCA

+USB30_VCCA

+5VALW

HDMI-IN Mini Card x2

CRT-IN

A A

eSATA/USB

Conn.

+5VALW

U83

+3V_LAN

+USB_VCCC

5

U34

U33

U46

MOS

LAN

RTL8111E

+3VALW

SW&Power/B

Conn

+3VS

+3VALW

MOS

Scaler

U23

+1.2V_SCA

+3VS

+3VS1.5VS

+1.2VUSB+3V_SCA

USB3.0

ASM1042

4

EC

KB930

+3VALW

+5VALW

+3VS

+5VALW

+5VS

MOS

+LCDVDD

LVDS CONNRTD2482D

+3VALW

Scaler

3

CIR

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

MOS

B-CAS

+5VS

Touchscreen

Compal Secret Data

Deciphered Date

2

+5VS_L_BCAS

2010/10/1 2011/11/01

A

B

C

D

E

Voltage Rails

Power Plane Description
VIN
B+
+CPU_CORE

1 1

+VCCSA ON OFF OFFSystem Agent core voltage for CPU
+1.05VS_VCCIO 1.05V power rail for CPU
+1.05VS_VPCH 1.05V power rail for PCH
+0.75VS 0.75V power rail for DDR terminator
+1.5V
+1.5VS
+1.8VS 1.8V switched power rail
+3VALW 3.3V alwa y s on powe r ra il once AC plug in
+3V_LAN 3.3V power rail for LAN ON
+3VS
+3V_SCA 3.3V switched pow er rail for scaler O N
+1.2V_SCA N/AN/A
+1.2V_USB 1.2V power rail for USB3.0 O FFON OFF

+5VS 5V switched power rail OFF OFF

2 2

+RTCVCC RTC power
+3VGS ON OFF OFF

+1.05VGS
+1.5VGS
+12VALW 12V always on power rail once AC plug in
+12VS 5V switched power rail O FF O FF

Note : ON * m e a n s t h a t t hi s p ow e r pl a ne is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)
AC power rail for power circuit.
Core voltage for CPU

1.5V power rail for DDRIII

1.5V switched power rail

3.3V switched power rail

1.2V switched power rail for scaler ON

5V always on power rail once AC plug in+5VALW

5V switched power rail for panel+LCDVDD ON N/A N/A

3.3V power rail for GPU
Graphics power rail for GPU

1.05VS switched power rail for GPU

1.5VS power rail for GPU and VRAM

PCH SM Bus Address

HEX

Device

+3VS
+3VS

3 3

DDR(JDDRL2)
DDR(JDDRH1)

Address

1010 000X b
1010 010X b

S0 S3 S5
N/A

N/A
N/A
OFF
OFF

OFF
ON
OFF
OFF
ON
ON
OFF
N/A N/A

ONON

N/A
N/A
OFF

OFF

OFF
OFF
ON
OFF

N/A
ON
ON OFF+GFX _COR E Graphics voltage for CPU

ONONOFF
ON OFF OFF
ON OFF
ON OFF
ON
ON
ON

ON OFF

ON

ON ON ON

ON OFF OFF+VGA_CORE
ON OFF OFF
ON OFF OFF
ONONN/A N/A

EC SM Bus2 Address

DevicePower Power

Scaler

HEX Address

0000_0101b

USB Port Table

USB 2.0 USB 1.1 Port

UHCI0

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

EHCI2

UHCI5

UHCI6

SATA Port Table

Port Device

0

6G

3G

HDD

1

ODD

2

Disabled on H61

3

Disabled on H61

4

eSATA+USB Conn

5

NC

BOARD ID Table

Board
ID

0

*

1
2
3
4

PCB
Revision

0.1

0.2

Device

0

Co-lay w/USB30 PORT0

1

Co-lay w/USB30 PORT1

2

Touch Screen

3

Web Camera

4

eSATA+USB Conn

5

USB Conn 6

6

Disabled on H61

7

Disabled on H61

8

USB Conn 4

9

USB Conn 3

10

Mini Card(TV Tuner)

11

Blue Tooth

12

Disabled on H61

13

Disabled on H61

PCIE Port Table

1
2
3
4
5
6
7
8

DevicePort

NC
USB30
WLAN
TV
Card reader
LAN
Disabled on H61
Disabled on H61

BOM Structure Table

BTO Item BOM Structure

ME components CONN@

UMA Only UMA@

USB30 USB30@

D-sub IN VGAIN@
HDMI IN HDMIIN@
HDMI OUT HDMIO@
HDMI OUT from DIS HDMIOD@
HDMI OUT from UMA HDMIOU@
VGA w/o Senergy DISO@
BCAS TV@
VRAM select X76@
VRAM 1G Hynix
X7630488L01
VRAM 1G Samsung
X7630488L02

SKU IO Select

Unpop @

LA-7522P 8 Layer PCB 8LPCB@

GS@VGA-N12P-GS
GV@VGA-N12P-GV

DIS@DISCRETE ONLY

USB20@No USB30 SKU

X76_HY1G@

X76_SAM1G@
GPIO69_H@

GPIO69_L@
GPIO70_H@
GPIO70_L@
GPIO71_H@
GPIO71_L@

6LOCB@LA-7521P 6 Layer PCB

SKU ID(Project) Table

Project
_ID2

PCH SML1 Bus Address

HEX

AddressDevicePower

VGA Ext. thermal sensor

(defaulta)

SIGNAL

STATE

4 4

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S3#

HIGH HIGH HIGH

LOW

LOW LOW

A

SLP_S4#

HIGH

1001_1010b
1001_1110bVGA Int. thermal sensor

SLP_S5# +VALW

HIGHHIGHHIGH

HIGH

HIGH

LOWLOWLOW OFF

ON

ON

ON

ON

OFF

+VS

ON

ON

OFF

OFF

B

(GPIO69)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

Project
_ID1

(GPIO70)

00 0
0

0

01 1

10 0

Project

Project

_ID0
(GPIO71)

0

1

PCA70

1

0

PCA61

SKU

UMA

USB30 w/o HDMI
4319D588L03

DIS-Hynix

USB30 w/ HDMI
4319D588L04

UMA

USB30 w/ HDMI
4319D588L05

DIS-Hynix

USB30 w/ HDMI
4319D588L11

UMA

USB20 w/ HDMI
4319D588L12

10 1 X
11 0 X

2010/10/1 2011/11/01

C

Compal Secret Data

Deciphered Date

UMA@ USB30@ GPIO69_L@ GPIO70_L@ GPIO71_L@

GS@ DIS@ USB30@ VGAIN@ HDMIO@ HDMIOD@ DISO@
8LPCB@

8LPCB@

X76_HY1G@

GPIO69_L@ GPIO70_L@ GPIO71_H@

HDMIIN@

HDMIIN@UMA@ USB30@ VGAIN@ HDMIO@ HDMIOU@ DEBUG@

8LPCB@

GPIO69_L@ GPIO71_L@

GPIO70_H@

HDMIIN@GV@ DIS@ USB30@ VGAIN@ HDMIO@ HDMIOD@ DISO@

6LOCB@

GPIO69_L@ GPIO71_H@

GPIO70_H@

HDMIIN@UMA@ USB20@ VGAIN@ HDMIO@ HDMIOU@ DEBUG@

GPIO69_H@ GPIO70_L@

GPIO71_L@6LOCB@

X11 1

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Notes List

PCA70 LA-7521P M/B

464Tuesday, April 12, 2011

E

0.1

of

5

D D

PECI 10mil spacing and
Max Length < 15"

R12 follow CDB R42PR add
0ohm serial resistor

R14 follow CDB R34PR add
0ohm serial resistor

12

R1310K_0402_5%

C20.1U_0402_16V4Z

H_PECI
H_SNB_IVB#
H_PROCHOT#_R
H_PM_SYNC

H_PWRGOOD

+1.5V

1 2

C1591 0.1U_0402_16V4Z

1 2

C1592 0.1U_0402_16V4Z

1 2

C1593 0.1U_0402_16V4Z

1 2

ESD request Close to CPU as possible

C C

Place C2 close to CPU J40 as
close as possible.

C1594 0.1U_0402_16V4Z

1 2

+1.05VS_VCCIO

H_PROCHOT#[49]

R8 51_0402_5%

+1.05VS_VCCIO

12

H_THERMTRIP#[18]

4

H_SNB_IVB#[18]

H_PM_SYNC[15]

H_PWRGOOD[18]

T1PAD

R1070

@

1K_0402_5%

12

H_PECI[18,49]

R12 0_0402_5%@

12

1 2

R14 0_0402_5%

PM_DRAM_PWRGD_R

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

H_THERMTRIP#_R

H_PM_SYNC

H_PWRGOOD

BUF_CPU_RST#

JCPU1B

PROC_SELECT#

K32

PROC_SEL

AJ33

SKTOCC#

E37

CATERR#

J35

PECI

H34

PROCHOT#

G35

THERMTRIP#

E38

PM_SYNC

J40

UNCOREPWRGOOD

AJ19

SM_DRAMPWROK

F36

RESET#

Sandy Bridge_rPGA_Rev1p0

3

MISCTHERMALPWR MANAGEMENT

BCLK[0]

BCLK#[0]

BCLK_ITP

BCLK_ITP#

CLOCKS

SM_DRAMRST#

DDR3

MISC

PRDY#
PREQ#

TCK
TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]

JTAG & BPM

BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TDI

W2
W1

C40
D40

AW18

K38
K40

M40
L38
J39

L40
L39

E39

H40
H38
G38
G40
G39
F38
E40
F40

100 MHz

CLK_CPU_DMI
CLK_CPU_DMI#

120 MHz

CLK_BCLK_ITP
CLK_BCLK_ITP#

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI_R
XDP_TDO_R

XDP_DBRESET#_R

2

CLK_CPU_DMI [14]
CLK_CPU_DMI# [14]

CLK_BCLK_ITP [14]
CLK_BCLK_ITP# [14]

1

@

0.1U_0402_16V4Z

2

R23 0_0402_5%@

1 2

Close to CPU side

C3

SM_DRAMRST# [11,12]

XDP_DBRESET#

1

PU/PD for JTAG signals

XDP_TMS_R
XDP_TDI_R
XDP_TDO_R
XDP_TCK_R
XDP_TRST#_R

R1 51_0402_5%
R2 51_0402_5%
R3 51_0402_5%
R4 51_0402_5%
R6 51_0402_5%

R22 10K_0402_5%

12

+3VS

XDP_DBRESET# [15]

+1.05VS_VCCIO

12
12
12
12
12

12

R33
200_0402_5%

PM_DRAM_PWRGD_R

DRAMPWROK[15]

B B

SUSP[51,57]

2

G

1 2

R24

12

130_0402_5%

R35

@

39_0402_5%

13

D

Q1
SSM3K7002BF 1N SC59-3

@

S

1

C1
1000P_0402_50V7K

2

@

Change Buffered Reset to 1G07(Buffer with open-drain output) 10/7

+3VS

C6

0.1U_0402_16V4Z

A A

PLT_RST#[17,22,45,49]

PLT_RST#

C1612

0.1U_0402_16V4Z

5

1

2

5

1

NC

2

A

2

3

1

U2

P

4

Y

G

SN74LVC1G07DCKR_SC70-5

+1.05VS_VCCIO

12

R42
75_0402_5%

R43

BUFO_CPU_RST# BUF_CPU_RST#

43_0402_1%

1 2

4

12

R44
0_0402_5%

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_JTAG/XDP/FAN

PCA70 LA-7521P M/B

1

of

564Tuesday, April 12, 2011

0.1

5

D D

DMI_PTX_CRX_N0[15]
DMI_PTX_CRX_N1[15]
DMI_PTX_CRX_N2[15]
DMI_PTX_CRX_N3[15]

DMI_PTX_CRX_P0[15]
DMI_PTX_CRX_P1[15]
DMI_PTX_CRX_P2[15]
DMI_PTX_CRX_P3[15]

DMI_CTX_PRX_N0[15]
DMI_CTX_PRX_N1[15]
DMI_CTX_PRX_N2[15]
DMI_CTX_PRX_N3[15]

DMI_CTX_PRX_P0[15]
DMI_CTX_PRX_P1[15]
DMI_CTX_PRX_P2[15]
DMI_CTX_PRX_P3[15]

FDI_CTX_PRX_N0[15]
FDI_CTX_PRX_N1[15]
FDI_CTX_PRX_N2[15]

C C

+1.05VS_VCCIO

FDI_COMP signals should be shorted
near balls and routed with width

B B

10mils, length<250mils.

FDI_CTX_PRX_N3[15]
FDI_CTX_PRX_N4[15]
FDI_CTX_PRX_N5[15]
FDI_CTX_PRX_N6[15]
FDI_CTX_PRX_N7[15]

FDI_CTX_PRX_P0[15]
FDI_CTX_PRX_P1[15]
FDI_CTX_PRX_P2[15]
FDI_CTX_PRX_P3[15]
FDI_CTX_PRX_P4[15]
FDI_CTX_PRX_P5[15]
FDI_CTX_PRX_P6[15]
FDI_CTX_PRX_P7[15]

FDI_FSYNC0[15]
FDI_FSYNC1[15]

FDI_INT[15]
FDI_LSYNC0[15]

FDI_LSYNC1[15]

R46 24.9_0402_1%

1 2

7/20 PE_RX[0~3]/PE_RX#[0~3]
PE_TX[0~3] /PE_T X#[0~3] o nly
use on Server/Workstation.

Close to CPU

FDI_INT
FDI_FSYNC0
FDI_FSYNC1

A A

FDI_LSYNC0
FDI_LSYNC1

@

1 2

R47 1K_0402_5%

@

1 2

R48 1K_0402_5%

@

1 2

R49 1K_0402_5%

@

1 2

R50 1K_0402_5%

@

1 2

R51 1K_0402_5%

4

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT
FDI_LSYNC0

FDI_LSYNC1

FDI_COMP

JCPU1A

W4

DMI_RX#[0]

V4

DMI_RX#[1]

Y4

DMI_RX#[2]

AA5

DMI_RX#[3]

W5

DMI_RX[0]

V3

DMI_RX[1]

Y3

DMI_RX[2]

AA4

DMI_RX[3]

V6

DMI_TX#[0]

W8

DMI_TX#[1]

Y7

DMI_TX#[2]

AA8

DMI_TX#[3]

V7

DMI_TX[0]

W7

DMI_TX[1]

Y6

DMI_TX[2]

AA7

DMI_TX[3]

AC7

FDI_TX#[0]

AC3

FDI_TX#[1]

AD1

FDI_TX#[2]

AD3

FDI_TX#[3]

AD6

FDI_TX#[4]

AE8

FDI_TX#[5]

AF2

FDI_TX#[6]

AG1

FDI_TX#[7]

AC8

FDI_TX[0]

AC2

FDI_TX[1]

AD2

FDI_TX[2]

AD4

FDI_TX[3]

AD7

FDI_TX[4]

AE7

FDI_TX[5]

AF3

FDI_TX[6]

AG2

FDI_TX[7]

AC5

FDI_FSYNC[0]

AE5

FDI_FSYNC[1]

AG3

FDI_INT

AC4

FDI_LSYNC[0]

AE4

FDI_LSYNC[1]

AE2

FDI_COMPIO

AE1

FDI_ICOMPO

P3

PE_RX[0]

R2

PE_RX[1]

T4

PE_RX[2]

U2

PE_RX[3]

P4

PE_RX#[0]

R1

PE_RX#[1]

T3

PE_RX#[2]

U1

PE_RX#[3]

P8

PE_TX[0]

T7

PE_TX[1]

R6

PE_TX[2]

U5

PE_TX[3]

P7

PE_TX#[0]

T8

PE_TX#[1]

R5

PE_TX#[2]

U6

PE_TX#[3]

Sandy Bridge_rPGA_Rev1p0

PEG_COMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

DMI

Intel(R) FDI

PCI-EXPRESS

3

B4
B5
C4

PCIE_GTX_C_CRX_N15

B12

PCIE_GTX_C_CRX_N14

D11

PCIE_GTX_C_CRX_N13

C9

PCIE_GTX_C_CRX_N12

E9

PCIE_GTX_C_CRX_N11

B7

PCIE_GTX_C_CRX_N10

C5

PCIE_GTX_C_CRX_N9

A6

PCIE_GTX_C_CRX_N8

E1

PCIE_GTX_C_CRX_N7

F3

PCIE_GTX_C_CRX_N6

G1

PCIE_GTX_C_CRX_N5

H4

PCIE_GTX_C_CRX_N4

J2

PCIE_GTX_C_CRX_N3

K4

PCIE_GTX_C_CRX_N2

L2

PCIE_GTX_C_CRX_N1

M4

PCIE_GTX_C_CRX_N0

N2

PCIE_GTX_C_CRX_P15

B11

PCIE_GTX_C_CRX_P14

D12

PCIE_GTX_C_CRX_P13

C10

PCIE_GTX_C_CRX_P12

E10

PCIE_GTX_C_CRX_P11

B8

PCIE_GTX_C_CRX_P10

C6

PCIE_GTX_C_CRX_P9

A5

PCIE_GTX_C_CRX_P8

E2

PCIE_GTX_C_CRX_P7

F4

PCIE_GTX_C_CRX_P6

G2

PCIE_GTX_C_CRX_P5

H3

PCIE_GTX_C_CRX_P4

J1

PCIE_GTX_C_CRX_P3

K3

PCIE_GTX_C_CRX_P2

L1

PCIE_GTX_C_CRX_P1

M3

PCIE_GTX_C_CRX_P0

N1

PCIE_CTX_GRX_N15

C14

PCIE_CTX_GRX_N14

E13

PCIE_CTX_GRX_N13

G13

PCIE_CTX_GRX_N12

F11

PCIE_CTX_GRX_N11

J13

PCIE_CTX_GRX_N10

D7

PCIE_CTX_GRX_N9

C3

PCIE_CTX_GRX_N8

E5

PCIE_CTX_GRX_N7

F7

PCIE_CTX_GRX_N6

G9

PCIE_CTX_GRX_N5

G6

PCIE_CTX_GRX_N4

K8

PCIE_CTX_GRX_N3

J6

PCIE_CTX_GRX_N2

M7

PCIE_CTX_GRX_N1

L5

PCIE_CTX_GRX_N0

N6

PCIE_CTX_GRX_P15

C13

PCIE_CTX_GRX_P14

E14

PCIE_CTX_GRX_P13

G14

PCIE_CTX_GRX_P12

F12

PCIE_CTX_GRX_P11

J14

PCIE_CTX_GRX_P10

D8

PCIE_CTX_GRX_P9

D3

PCIE_CTX_GRX_P8

E6

PCIE_CTX_GRX_P7

F8

PCIE_CTX_GRX_P6

G10

PCIE_CTX_GRX_P5

G5

PCIE_CTX_GRX_P4

K7

PCIE_CTX_GRX_P3

J5

PCIE_CTX_GRX_P2

M8

PCIE_CTX_GRX_P1

L6

PCIE_CTX_GRX_P0

N5

PEG_ICOMPI and RCOMPO signals should be shorted and routed with

- max length = 500 mils

- typical imp e d a nce = 43 m ohm (4 mils/15mils)

Intel confirm
pull high is
correct

PEG_COMP

Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

+1.05VS_VCCIO

R45

24.9_0402_1%

C7 0.1U_0402_16V7KDIS@
C8 0.1U_0402_16V7KDIS@
C9 0.1U_0402_16V7KDIS@
C10 0.1U_0402_16V7KDIS@
C11 0.1U_0402_16V7KDIS@
C12 0.1U_0402_16V7KDIS@
C13 0.1U_0402_16V7KDIS@
C14 0.1U_0402_16V7KDIS@
C15 0.1U_0402_16V7KDIS@
C16 0.1U_0402_16V7KDIS@
C17 0.1U_0402_16V7KDIS@
C18 0.1U_0402_16V7KDIS@
C19 0.1U_0402_16V7KDIS@
C20 0.1U_0402_16V7KDIS@
C21 0.1U_0402_16V7KDIS@
C22 0.1U_0402_16V7KDIS@

C23 0.1U_0402_16V7KDIS@
C24 0.1U_0402_16V7KDIS@
C25 0.1U_0402_16V7KDIS@
C26 0.1U_0402_16V7KDIS@
C27 0.1U_0402_16V7KDIS@
C28 0.1U_0402_16V7KDIS@
C29 0.1U_0402_16V7KDIS@
C30 0.1U_0402_16V7KDIS@
C31 0.1U_0402_16V7KDIS@
C32 0.1U_0402_16V7KDIS@
C33 0.1U_0402_16V7KDIS@
C34 0.1U_0402_16V7KDIS@
C35 0.1U_0402_16V7KDIS@
C36 0.1U_0402_16V7KDIS@
C37 0.1U_0402_16V7KDIS@
C38 0.1U_0402_16V7KDIS@

PEG_ICOMPO signals should be routed with

- max length = 500 mils

- typical imp e d ance = 14.5 m ohm (12 mils/15mils)

12

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLETRACE TO R?
ROUTE B5 TO R? AS A SEPERATE TRACE

PCIE_GTX_C_CRX_N[0..15] [22]

PCIE_GTX_C_CRX_P[0..15] [22]

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

2

PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N10

PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P10

PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P0

1

PCIE_CTX_C_GRX_N[0..15] [22]

PCIE_CTX_C_GRX_P[0..15] [22]

Leverage LA-6831 and
LA6951(B520) used 1000P
connect to GND to
substitute for 1K ohm PD
resistor.

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_ DMI/PEG/FDI

PCA70 LA-7521P M/B

664Tuesday, April 12, 2011

1

of

0.1

5

DDR_A_D[0..63][11]

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6

D D

C C

DDR_A_BS0[11]

B B

DDR_A_BS1[11]
DDR_A_BS2[11]

DDR_A_CAS#[11]
DDR_A_RAS#[11]

DDR_A_WE#[11]

DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

JCPU1C

AJ3

SA_DQ[0]

AJ4

SA_DQ[1]

AL3

SA_DQ[2]

AL4

SA_DQ[3]

AJ2

SA_DQ[4]

AJ1

SA_DQ[5]

AL2

SA_DQ[6]

AL1

SA_DQ[7]

AN1

SA_DQ[8]

AN4

SA_DQ[9]

AR3

SA_DQ[10]

AR4

SA_DQ[11]

AN2

SA_DQ[12]

AN3

SA_DQ[13]

AR2

SA_DQ[14]

AR1

SA_DQ[15]

AV2

SA_DQ[16]

AW3

SA_DQ[17]

AV5

SA_DQ[18]

AW5

SA_DQ[19]

AU2

SA_DQ[20]

AU3

SA_DQ[21]

AU5

SA_DQ[22]

AY5

SA_DQ[23]

AY7

SA_DQ[24]

AU7

SA_DQ[25]

AV9

SA_DQ[26]

AU9

SA_DQ[27]

AV7

SA_DQ[28]

AW7

SA_DQ[29]

AW9

SA_DQ[30]

AY9

SA_DQ[31]

AU35

SA_DQ[32]

AW37

SA_DQ[33]

AU39

SA_DQ[34]

AU36

SA_DQ[35]

AW35

SA_DQ[36]

AY36

SA_DQ[37]

AU38

SA_DQ[38]

AU37

SA_DQ[39]

AR40

SA_DQ[40]

AR37

SA_DQ[41]

AN38

SA_DQ[42]

AN37

SA_DQ[43]

AR39

SA_DQ[44]

AR38

SA_DQ[45]

AN39

SA_DQ[46]

AN40

SA_DQ[47]

AL40

SA_DQ[48]

AL37

SA_DQ[49]

AJ38

SA_DQ[50]

AJ37

SA_DQ[51]

AL39

SA_DQ[52]

AL38

SA_DQ[53]

AJ39

SA_DQ[54]

AJ40

SA_DQ[55]

AG40

SA_DQ[56]

AG37

SA_DQ[57]

AE38

SA_DQ[58]

AE37

SA_DQ[59]

AG39

SA_DQ[60]

AG38

SA_DQ[61]

AE39

SA_DQ[62]

AE40

SA_DQ[63]

AY29

SA_BS[0]

AW28

SA_BS[1]

AV20

SA_BS[2]

AV30

SA_CAS#

AU28

SA_RAS#

AW29

SA_WE#

Sandy Bridge_rPGA_Rev1p0

DDR SYSTEM MEMORY A

4

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CK[2]
SA_CK#[2]

SA_CKE[2]

SA_CK[3]
SA_CK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]

SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS#[8]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_DQS[8]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_ECC_CB[0]
SA_ECC_CB[1]
SA_ECC_CB[2]
SA_ECC_CB[3]
SA_ECC_CB[4]
SA_ECC_CB[5]
SA_ECC_CB[6]
SA_ECC_CB[7]

3

DDR_B_D[0..63][12]

DDRA_CLK0

AY25

DDRA_CLK0#

AW25

DDRA_CKE0

AV19

DDRA_CLK1 DDRB_CLK1

AU24

DDRA_CLK1# DDRB_CLK1#

AU25

DDRA_CKE1 DDRB_CKE1

AT19

AW27
AY27
AU18

AV26
AW26
AV18

DDRA_SCS0# DDRB_SCS0#

AU29

DDRA_SCS1#

AV32
AW30
AU33

DDRA_ODT0 DDRB_ODT0

AV31

DDRA_ODT1

AU32
AU30
AW33

DDR_A_DQS#0

AK2

DDR_A_DQS#1

AP2

DDR_A_DQS#2

AV4

DDR_A_DQS#3

AW8

DDR_A_DQS#4

AV36

DDR_A_DQS#5

AP39

DDR_A_DQS#6

AK39

DDR_A_DQS#7

AF39
AV12

DDR_A_DQS0

AK3

DDR_A_DQS1

AP3

DDR_A_DQS2

AW4

DDR_A_DQS3

AV8

DDR_A_DQS4

AV37

DDR_A_DQS5

AP38

DDR_A_DQS6

AK38

DDR_A_DQS7

AF38
AV13

DDR_A_MA0

AV27

DDR_A_MA1

AY24

DDR_A_MA2

AW24

DDR_A_MA3

AW23

DDR_A_MA4

AV23

DDR_A_MA5

AT24

DDR_A_MA6

AT23

DDR_A_MA7

AU22

DDR_A_MA8

AV22

DDR_A_MA9

AT22

DDR_A_MA10

AV28

DDR_A_MA11

AU21

DDR_A_MA12

AT21

DDR_A_MA13

AW32

DDR_A_MA14

AU20

DDR_A_MA15

AT20

AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12

DDRA_CLK0 [11] DDRB_CLK0 [12]
DDRA_CLK0# [11]
DDRA_CKE0 [11] DDRB_CKE0 [12]

DDRA_CLK1 [11]
DDRA_CLK1# [11] DDRB_CLK1# [12]
DDRA_CKE1 [11]

DDRA_SCS0# [11]
DDRA_SCS1# [11] DDRB_SCS1# [12]

DDRA_ODT0 [11] DDRB_ODT0 [12]
DDRA_ODT1 [11] DDRB_ODT1 [12]

DDR_A_DQS#[0..7] [11]

DDR_A_DQS[0..7] [11]

DDR_A_MA[0..15] [11]

DDR_B_BS0[12]
DDR_B_BS1[12]
DDR_B_BS2[12]

DDR_B_CAS#[12]
DDR_B_RAS#[12]

DDR_B_WE#[12]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

AG7
AG8

AG5
AG6

AM7

AM10

AL10

AM6
AM9

AP7

AR7
AP10
AR10

AP6

AR6

AP9

AR9
AM12
AM13
AR13
AP13

AL12

AL13
AR12
AP12
AR28
AR29

AL28

AL29
AP28
AP29
AM28
AM29
AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34
AM32
AM31

AL35

AL32
AM34

AL31
AM35

AL34
AH35
AH34
AE34
AE35

AJ35

AJ34
AF33
AF35

AP23
AM24

AW17

AK25
AP24
AR25

AJ9
AJ8

AJ6
AJ7
AL7

AL6
AL9

2

JCPU1D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

Sandy Bridge_rPGA_Rev1p0

AL21

SB_CK[0]

AL22

SB_CK#[0]

AU16

SB_CKE[0]

AL20

SB_CK[1]

AK20

SB_CK#[1]

AY15

SB_CKE[1]

AL23

SB_CK[2]

AM22

SB_CK#[2]

AW15

SB_CKE[2]

AP21

SB_CK[3]

AN21

SB_CK#[3]

AV15

SB_CKE[3]

AN25

SB_CS#[0]

AN26

SB_CS#[1]

AL25

SB_CS#[2]

AT26

SB_CS#[3]

AL26

SB_ODT[0]

AP26

SB_ODT[1]

AM26

SB_ODT[2]

AK26

SB_ODT[3]

AH6

SB_DQS#[0]

AL8

SB_DQS#[1]

AP8

SB_DQS#[2]

AN12

SB_DQS#[3]

AN28

SB_DQS#[4]

AR33

SB_DQS#[5]

AM33

SB_DQS#[6]

AG34

SB_DQS#[7]

AN15

SB_DQS#[8]

AH7

SB_DQS[0]

AM8

SB_DQS[1]

AR8

SB_DQS[2]

AN13

SB_DQS[3]

AN29

SB_DQS[4]

AP33

SB_DQS[5]

AL33

SB_DQS[6]

AG35

SB_DQS[7]

DDR SYSTEM MEMORY B

SB_ECC_CB[0]
SB_ECC_CB[1]
SB_ECC_CB[2]
SB_ECC_CB[3]
SB_ECC_CB[4]
SB_ECC_CB[5]
SB_ECC_CB[6]
SB_ECC_CB[7]

SB_DQS[8]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AN16

AK24
AM20
AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17
AN23
AU17
AT18
AR26
AY16
AV16

AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15

DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

1

DDRB_CLK0# [12]

DDRB_CLK1 [12]
DDRB_CKE1 [12]

DDRB_SCS0# [12]

DDR_B_DQS#[0..7] [12]

DDR_B_DQS[0..7] [12]

DDR_B_MA[0..15] [12]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_DDR3

PCA70 LA-7521P M/B

764Tuesday, April 12, 2011

1

0.1

of

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120

5

POWER

CORE SUPPLY

VSS_SENSE_VCCIO

5

PEG AND DDR

VCC_SENSE

VCCIO_SENSE

VSSIO_SENSE

SENSE LINES SVID

8.5A

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VCCIO41
VCCIO42
VCCIO43
VCCIO44
VCCIO45

VIDALERT#

VIDSCLK

VIDSOUT

VSS_SENSE

VCC121

VCC122

VCC123

VCC124

VCC125

VCC126

VCC127

VCC128

VCC129

VCC130

VCC131

VCC132

VCC133

VCC134

VCC135

VCC136

VCC137

VCC138

VCC139

VCC140

VCC141

VCC142

VCC143

VCC144

VCC145

VCC146

VCC147

VCC148

VCC149

VCC150

VCC151

VCC152

VCC153

VCC154

VCC155

VCC156

VCC157

VCC158

VCC159

VCC160

VCC161

TOP Socket Cavity

22U_0805_6.3V6M

A11
A7

C39

AA3
AB8
AF8
AG33
AJ16
AJ17
AJ26
AJ28
AJ32
AK15
AK17

C43

AK19
AK21
AK23
AK27
AK29

22U_0805_6.3V6M

AK30
B9
D10
D6
E3
E4
G3
G4

C48

J3
J4

560U_2.5V_M

J7
J8
L3
L4
L7
M13
N3
N4
N7
R3
R4

HR's R52=130 ohm

R7
U3

SB CRB suggst 110ohm

U4
U7
V8
W3

R55 43_0402_1%

H_CPU_SVIDALRT#

A37

VR_SVID_CLK_R

C37

VR_SVID_DAT_R

B37

A36
B36

VCCIO_SENSE

AB4
AB3

12

R56
100_0402_1%

J24

+CPU_CORE
J25
J27

J28
J30
K15
K16
K18
K19
K21
K22
K24
K25
K27
K28
K30
L13
L14
L15
L16
L18
L19
L21
L22
L24
L25
L27
L28
L30
M14
M15
M16
M18
M19
M21
M22
M24
M25
M27
M28
M30

+CPU_CORE

D D

C C

B B

A A

JCPU1F

76A (Quad Core 65W)

A12
A13
A14
A15
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35

F15
F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
F31
F32
F33

F34
G15
G16
G18
G19
G21
G22
G24
G25
G27
G28
G30
G31
G32
G33
H13
H14
H15
H16
H18
H19
H21
H22
H24
H25
H27
H28
H30
H31
H32

J12

J15

J16

J18

J19

J21

J22

Sandy Bridge_rPGA_Rev1p0

4

22U_0805_6.3V6M

1

1

C40

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C44

2

2

1

+

C49

2

560U_2.5V_M

R52
110_0402_5%

1 2
1 2

1 2

R1037 0_0402_5%
R1038 0_0402_5%

4

1

C41

C42

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C46

C45

2

22U_0805_6.3V6M

1

+

C50

2

560U_2.5V_M

+1.05VS_VCCIO

90.9_0402_1%

12

@

R53

VCCSENSE [58]
VSSSENSE [ 58]

VCCIO_SENSE [54]

1

2

1

C47

2

22U_0805_6.3V6M

1

+

2

12

12

R54
75_0402_5%

+1.05VS_VCCIO

+1.05VS_VCCP Decoupling:
3X 560U (6m ohm), 9X 22U

1

2

Pull high resistor close to CPU
SVID signal 50 ohm impedance
spacing >12mil length 3-6"

VR_SVID_ALRT# [58]
VR_SVID_CLK [58]
VR_SVID_DAT [58]

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+CPU_CORE Decoupling:
5X 560U (4m ohm), 2X330U, 18X 22U

C51
560U_2.5V_M

330U_D2_2V_Y

22U_0805_6.3V6M

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

2

TOP Socket Edge

+CPU_CORE

1

+

2

C52
560U_2.5V_M

1

+

2

1

+

2

C53
560U_2.5V_M

C54
560U_2.5V_M

1

+

2

1

+

C59
560U_2.5V_M

2

Bottom Socket Edge

+CPU_CORE

1

1

C55

@

+

2

C56

@

330U_D2_2V_Y

1

+

+

C58
330U_D2_2VM_R6M

2

2 3

14 pcs in TOP and 4pcs in BOT Socket Cavity

+CPU_CORE

22U_0805_6.3V6M

1

1

C67

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C77

2

2

Sandy Bridge_POWER-1

1

C61

C60

2

22U_0805_6.3V6M

+CPU_CORE

22U_0805_6.3V6M

1

C70

C71

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C62

2

2

1

1

C72

2

2

22U_0805_6.3V6M

2

22U_0805_6.3V6M

1

C63

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C73

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C64

2

1

C74

2

Date: Sheet

C66

C65

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C75

C76

2

22U_0805_6.3V6M

Title

Size Docum ent Number Rev

Custom

Compal Electronics, Inc.

PCA70 LA-7521P M/B

C68

1

1

C69

2

22U_0805_6.3V6M

1

1

2

0.1

of

864Tuesday, April 12, 2011

5

4

3

2

1

+GFX_CORE Decoupling:
2X 470U (4m ohm), 12X 22U

Bottom

+GFX_CORE

Socket
Edge

D D

C80

@

330U_D2_2VM_R6M

Top Socket Cavity

22U_0805_6.3V6M

C82

UMA@

Bottom Socket Edge

22U_0805_6.3V6M

UMA@

C99

C C

Top Socket Edge

330U_D2_2VM_R6M

1

1

+

+

UMA@

C1588

2

2

330U_D2_2VM_R6M

22U_0805_6.3V6M

UMA@

1

1

C84

C83

UMA@

2

2

22U_0805_6.3V6M

UMA@

1

1

C100

2

2

22U_0805_6.3V6M

1

+

@

C78

2

UMA@

1

1

C85

2

2

22U_0805_6.3V6M

1

+

UMA@

C79

2

560U_2.5V_M

1

+

UMA@

C81
560U_2.5V_M

2

AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40

W33
W34
W35
W36
W37
W38

U33
U34
U35
U36
U37
U38
U39
U40

Y33
Y34
Y35
Y36
Y37
Y38

T33
T34
T35
T36
T37
T38
T39
T40

JCPU1G

35A

VCCAXG1
VCCAXG2
VCCAXG3
VCCAXG4
VCCAXG5
VCCAXG6
VCCAXG7
VCCAXG8
VCCAXG9
VCCAXG10
VCCAXG11
VCCAXG12
VCCAXG13
VCCAXG14
VCCAXG15
VCCAXG16
VCCAXG17
VCCAXG18
VCCAXG19
VCCAXG20
VCCAXG21
VCCAXG22
VCCAXG23
VCCAXG24
VCCAXG25
VCCAXG26
VCCAXG27
VCCAXG28
VCCAXG29
VCCAXG30
VCCAXG31
VCCAXG32
VCCAXG33
VCCAXG34
VCCAXG35
VCCAXG36
VCCAXG37
VCCAXG38
VCCAXG39
VCCAXG40
VCCAXG41
VCCAXG42
VCCAXG43
VCCAXG44

VCCPLL Decoupling:
1X 220U, 2X 10U

+1.8VS

B B

R65 0_0805_5%

+1.8VS_VCCPLL

12

C105

220U_6.3V_M

10U_0805_10V6K

1

1

+

C106

2

2

1

C107

@

2

10U_0805_10V6K

1.5A

AK11

VCCPLL1

AK12

VCCPLL2

Sandy Bridge_rPGA_Rev1p0

POWER

SENSE

VREFMISC DDR3 -1.5V RAILS

GRAPHICS

SA RAIL

1.8V RAIL

VCCAXG_SENSE
VSSAXG_SENSE

LINES

SM_VREF

4.75A

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23

8.8A

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9

VCCSA10
VCCSA11

VCCSA_SENSE

VCCSA_VID

FC_AH1
FC_AH4

L32
M32

+V_SM_VREF should
have 20 mil trace width

AJ22

AJ13
AJ14
AJ20
AJ23
AJ24
AR20
AR21
AR22
AR23
AR24
AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31
AY23
AY26
AY28

22U_0805_6.3V6M

TOP Socket Cavity

10U_0805_10V6K

H10
H11
H12
J10

C101

K10
K11
L11
L12
M10
M11
M12

T2
P34

AH1
AH4

+VREF_DQB_R
+VREF_DQA_R

C108 0.1U_0402_16V4Z

1

1

2

2

10U_0805_10V6K

C109 0.1U_0402_16V4Z

VCC_AXG_SENSE [58]
VSS_AXG_SENSE [58]

+1.5V

12

R61
100_0402_1%

+V_SM_VREF

C86

22U_0805_6.3V6M

C90

1

C102

2

1

0.1U_0402_16V4Z

2

1

1

C91

2

2

22U_0805_6.3V6M

10U_0805_10V6K

1

1

C103

@

2

2

22U_0805_6.3V6M

1

C92

2

C93

+VCCSA

1

+

2

12

R62
100_0402_1%

1

1

C94

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C95

1

1

C96

@

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C97

@

+VCCSA Decoupling:
1X 560U, 2X 10U

C104
560U_2.5V_M

VCCSA_SENSE [56]
VCCSAP_VID1 [56]

1

C98

@

2

22U_0805_6.3V6M

0

1

2

1

1 2
1 2

R66 0_0402_5%
R67 0_0402_5%

R66,R67 should place close to DIMM for

+VREF_DQB
+VREF_DQA

minimum stubs trace

330U_D2_2VM_R6M

1

+

C88

C87

2

330U_D2_2VM_R6M

+VCCSAVCCSA_VID1

0.925 V
(Default)

0.85 V

+1.5V

+1.5V Decoupling:

1

1

+

C89

2

3X 330U , 9X 22U

+

@

330U_D2_2VM_R6M

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_POWER-2

PCA70 LA-7521P M/B

964Tuesday, April 12, 2011

1

0.1

of

5

JCPU1H

A17

VSS1

A23

VSS2

A26

VSS3

A29

VSS4

A35

VSS5

AA33

VSS6

AA34

VSS7

AA35

VSS8

AA36

VSS9

AA37

VSS10

AA38

D D

C C

B B

A A

VSS11

AA6

VSS12

AB5

VSS13

AC1

VSS14

AC6

VSS15

AD33

VSS16

AD36

VSS17

AD38

VSS18

AD39

VSS19

AD40

VSS20

AD5

VSS21

AD8

VSS22

AE3

VSS23

AE33

VSS24

AE36

VSS25

AF1

VSS26

AF34

VSS27

AF36

VSS28

AF37

VSS29

AF40

VSS30

AF5

VSS31

AF6

VSS32

AF7

VSS33

AG36

VSS34

AH2

VSS35

AH3

VSS36

AH33

VSS37

AH36

VSS38

AH37

VSS39

AH38

VSS40

AH39

VSS41

AH40

VSS42

AH5

VSS43

AH8

VSS44

AJ12

VSS45

AJ15

VSS46

AJ18

VSS47

AJ21

VSS48

AJ25

VSS49

AJ27

VSS50

AJ36

VSS51

AJ5

VSS52

AK1

VSS53

AK10

VSS54

AK13

VSS55

AK14

VSS56

AK16

VSS57

AK22

VSS58

AK28

VSS59

AK31

VSS60

AK32

VSS61

AK33

VSS62

AK34

VSS63

AK35

VSS64

AK36

VSS65

AK37

VSS66

AK4

VSS67

AK40

VSS68

AK5

VSS69

AK6

VSS70

AK7

VSS71

AK8

VSS72

AK9

VSS73

AL11

VSS74

AL14

VSS75

AL17

VSS76

AL19

VSS77

AL24

VSS78

AL27

VSS79

AL30

VSS80

AL36

VSS81

AL5

VSS82

AM1

VSS83

AM11

VSS84

AM14

VSS85

AM17

VSS86

AM2

VSS87

AM21

VSS88

AM23

VSS89

AM25

VSS90

AM27

VSS91

AM3

VSS92

AM30

VSS93

AM36

VSS94

AM37

VSS95

AM38

VSS96

AM39

VSS97

AM4

VSS98

AM40

VSS99

AM5

VSS100

Sandy Bridge_rPGA_Rev1p0

VSS

VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200

AN10
AN11
AN14
AN17
AN19
AN22
AN24
AN27
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN5
AN6
AN7
AN8
AN9
AP1
AP11
AP14
AP17
AP22
AP25
AP27
AP30
AP36
AP37
AP4
AP40
AP5
AR11
AR14
AR17
AR18
AR19
AR27
AR30
AR36
AR5
AT1
AT10
AT12
AT13
AT15
AT16
AT17
AT2
AT25
AT27
AT28
AT29
AT3
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT4
AT40
AT5
AT6
AT7
AT8
AT9
AU1
AU15
AU26
AU34
AU4
AU6
AU8
AV10
AV11
AV14
AV17
AV3
AV35
AV38
AV6
AW10
AW11
AW14
AW16
AW36
AW6
AY11
AY14
AY18
AY35
AY4
AY6
AY8

B10
B13
B14
B17
B23
B26
B29
B32
B35
B38

B6
C11
C12
C17
C20
C23
C26
C29
C32
C35

C7
C8

D17

D2
D20
D23
D26
D29
D32
D37
D39

D4

D5

D9
E11
E12
E17
E20
E23
E26
E29
E32
E36

E7
E8

F1
F10
F13
F14
F17

F2
F20
F23
F26
F29
F35
F37
F39

F5

F6

F9
G11
G12
G17
G20
G23
G26
G29
G34

G7
G8
H1

H17

H2
H20
H23
H26
H29
H33
H35
H37
H39

H5

H6

H9

J11
J17
J20
J23
J26
J29
J32

K1
K12
K13
K14
K17

K2
K20
K23

4

JCPU1I

VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300

Sandy Bridge_rPGA_Rev1p0

VSS

VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4

K26
K29
K33
K35
K37
K39
K5
K6
L10
L17
L20
L23
L26
L29
L8
M1
M17
M2
M20
M23
M26
M29
M33
M35
M37
M39
M5
M6
M9
N8
P1
P2
P36
P38
P40
P5
P6
R33
R35
R37
R39
R8
T1
T5
T6
U8
V1
V2
V33
V34
V35
V36
V37
V38
V39
V40
V5
W6
Y5
Y8

A4
AV39
AY37
B3

T236PAD
T15 PAD

T16 PAD

T17 PAD
T18 PAD
T19 PAD
T20 PAD
T21 PAD
T22 PAD
T23 PAD
T24 PAD
T25 PAD
T26 PAD
T27 PAD

3

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6 CFG5
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

JCPU1E

H36

CFG[0]

J36

CFG[1]

J37

CFG[2]

K36

CFG[3]

L36

CFG[4]

N35

CFG[5]

L37

CFG[6]

M36

CFG[7]

J38

CFG[8]

L35

CFG[9]

M38

CFG[10]

N36

CFG[11]

N38

CFG[12]

N39

CFG[13]

N37

CFG[14]

N40

CFG[15]

G37

CFG[16]

G36

CFG[17]

AB6

RSVD1

AB7

RSVD2

AD37

RSVD3

AE6

RSVD4

AF4

RSVD5

AG4

RSVD6

AJ11

RSVD7

AJ29

RSVD8

AJ30

RSVD9

AJ31

RSVD10

AN20

RSVD11

AP20

RSVD12

AT11

RSVD13

AT14

RSVD14

AU10

RSVD15

AV34

RSVD16

AW34

RSVD17

AY10

RSVD18

C38

RSVD19

C39

RSVD20

D38

RSVD21

H7

RSVD22

H8

RSVD23

J33

RSVD24

J34

RSVD25

J9

RSVD26

K34

RSVD27

K9

RSVD28

L31

RSVD29

L33

RSVD30

L34

RSVD31

L9

RSVD32

M34

RSVD33

N33

RSVD34

N34

RSVD35

P35

RSVD36

P37

RSVD37

P39

RSVD38

R34

RSVD39

R36

RSVD40

R38

RSVD41

R40

RSVD42

J31

RSVD43

AD34

RSVD44

AD35

RSVD45

K31

RSVD46

Sandy Bridge_rPGA_Rev1p0

RESERVED

VCCIO_SEL

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4

NCTF1
NCTF2
NCTF3
NCTF4
NCTF5

2

CFG Straps for Processor

(CFG[17:0] internal pull high to VCCIO)

PEG Static x16 Lane Numbering Reversal.

CFG2

PEG Static x4 Lane Numbering Reversal.

CFG3

1: Normal Operation
0:Lane numbers Reversed

*

1: Normal Operation

*

0:Lane numbers Reversed

PCIE Port Bifurcation Straps

11: 1x16 PCI Express (Default)

*

CFG[6:5]

10: 2x8 PCI Express
01: Reserved
00: 1 x 8, 2 x 4 : PCI Express

A38
AU40
AW38
C2
D1

P33

AV1
AW2
AY3
B39

R1664

0_0402_5%

1 2

+5VS

1 2

1 2

CFG2

R70 1K_0402_1%

CFG3
CFG6

R1576
10K_0402_1%

R1577

5.1K_0402_1%

1 2

R71 1K_0402_1%@

1 2

R73 1K_0402_1%@

1 2

R74 1K_0402_1%@

1 2

VCCIO_SEL [54]

VCCIO_SEL

1

Reserve for PW

VCCIO

0

1

1.00V

1.05V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_GND/RSVD/CFG

PCA70 LA-7521P M/B

1

of

10 64Tuesday, April 12, 2011

0.1

5

DDR_A_DQS[0..7][7]

DDR_A_DQS#[0..7][7]

DDR_A_D[0..63][7]

D D

C C

Layout Note:
Place near JDDRL1

+1.5V

B B

A A

+

C143 390U_2.5V_M_R10

1 2

C145 10U_0805_6.3V6M

1 2

C147 10U_0805_6.3V6M

1 2

C149 10U_0805_6.3V6M

1 2

C151 10U_0805_6.3V6M

1 2

C152 10U_0805_6.3V6M

1 2

C153 10U_0805_6.3V6M

1 2

DDR_A_MA[0..15][7]

Layout Note:
Place near JDDRL1.203 and 204

+0.75VS

C134 10U_0805_6.3V6M

1 2

C135 1U_0402_6.3V6K

1 2

C136 1U_0402_6.3V6K

1 2

C139 1U_0402_6.3V6K

1 2

C140 1U_0402_6.3V6K

1 2

Layout Note : P la ce these 4 Caps near
Command and Control signals of JDDRL1

+1.5V

C144 0.1U_0402_16V4Z

1 2

C146 0.1U_0402_16V4Z

1 2

C148 0.1U_0402_16V4Z

1 2

C150 0.1U_0402_16V4Z

1 2

4

+1.5V

R91

1K_0402_1%

1 2

1K_0402_1%

3

CHA SO-DIMM 0(A0)

+0.75VS

12

R98
10K_0402_5%

+1.5V

JDDRL2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013290-1

CONN@

DQS#0

DQS0

DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3
DQ30

DQ31

VDD2

VDD4

VDD6

VDD8

VDD10

VDD12

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30
VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42
VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

+VREF_DQA

12

R93

2.2U_0603_6.3V6K

0.1U_0402_16V4Z
C114

1

2

Close to JDDRL.1

DDR_A_BS2[7]

DDRA_CLK0[7]
DDRA_CLK0#[7]

DDR_A_BS0[7]

DDR_A_WE#[7]

DDR_A_CAS#[7]

DDRA_SCS1#[7]

+3VS

2.2U_0603_6.3V6K
C154

+VREF_DQA
DDR_A_D0

DDR_A_D1

C115

1

2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDRA_CKE0 DDRA_CKE1

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1

DDRA_CLK0# DDRA_CLK1#
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_A_MA13

DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

R97 10K_0402_5%

1 2

0.1U_0402_16V4Z
C155

1

1

2

2

DQ4
DQ5

VSS3

VSS6

DQ6
DQ7

VSS8

DM1

DM2

CKE1

CK1

CK1#

RAS#

NC2

DM4

DM6

SDA
SCL

VTT2

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26
28

SM_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44
46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

74
76

DDR_A_MA15

78

A15
A14

A11

A7
A6

A4
A2

A0

BA1

S0#

G2

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

DDRA_CLK1DDRA_CLK0

102
104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDRA_SCS0#

114

DDRA_ODT0

116
118

DDRA_ODT1

120
122
124

+VREF_CAA

126
128

DDR_A_D36

130

DDR_A_D37

132
134
136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168
170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198

PM_SMBDATA

200

PM_SMBCLK

202
204

+0.75VS

206

2

SM_DRAMRST# [5,12]

DDRA_CKE1 [ 7 ]DDRA_CKE0[7]

DDRA_CLK1 [7]
DDRA_CLK1# [7]

DDR_A_BS1 [7]
DDR_A_RAS# [7]

DDRA_SCS0# [7]
DDRA_ODT0 [7]

DDRA_ODT1 [7]

2.2U_0603_6.3V6K

close to JDDRL1.126

PM_SMBDATA [12,14,40]
PM_SMBCLK [12,14,40]

1

+1.5V

12

R94
1K_0402_1%

12

R96

0.1U_0402_16V4Z

C137

C138

1

1

2

2

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMMA

PCA70 LA-7521P M/B

1

11 64Tuesday, April 12, 2011

0.1

of

A

DDR_B_DQS#[0..7][7]

DDR_B_DQS[0..7][7]

DDR_B_D[0..63][7]

DDR_B_MA[0..15][7]

1 1

2 2

Layout Note:
Place near JDDRL2.203 and 204

+0.75VS

C178 10U_0805_6.3V6M

1 2

C179 1U_0402_6.3V6K

1 2

C182 1U_0402_6.3V6K

1 2

C183 1U_0402_6.3V6K

1 2

C184 1U_0402_6.3V6K

1 2

3 3

Layout Note:
Place near JDDRL2

+1.5V

4 4

+

C187 390U_2.5V_M_R10

1 2

C189 10U_0805_6.3V6M

1 2

C191 10U_0805_6.3V6M

1 2

C193 10U_0805_6.3V6M

1 2

C195 10U_0805_6.3V6M

1 2

C196 10U_0805_6.3V6M

1 2

C197 10U_0805_6.3V6M

1 2

Layout Note : P la ce these 4 Caps near
Command and Control signals of JDDRL2

+1.5V

C188 0.1U_0402_16V4Z

1 2

C190 0.1U_0402_16V4Z

1 2

C192 0.1U_0402_16V4Z

1 2

C194 0.1U_0402_16V4Z

1 2

B

R101
1K_0402_1%

1 2

+1.5V

R103

1K_0402_1%

12

0.1U_0402_16V4Z

2.2U_0603_6.3V6K
C158

1

2

Close to JDDRL2.1

DDR_B_BS2[7]

DDRB_CLK0[7]

DDRB_CLK0#[7]

DDR_B_BS0[7] DDR_B_RAS# [7]

DDR_B_WE#[7]

DDR_B_CAS#[7]

DDRB_SCS1#[7]

+3VS

1

C198

2.2U_0603_6.3V6K

2

C

CHB SO-DIMM 0(A4)

+1.5V+VREF_DQB

JDDRH1

VREF_DQ1VSS1

3

DDR_B_D0
DDR_B_D1

C159

1

DDR_B_D2
DDR_B_D3

2

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
DDRB_CLK0 DDRB_CLK1

DDRB_CLK0# DDRB_CLK1#
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDRB_SCS1#

DDR_B_D37
DDR_B_D36

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54 DDR_B_D51
DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_D58 DDR_B_D62
DDR_B_D59

R107 10K_0402_5%

1 2

1 2

R108

+0.75VS +0.75VS

10K_0402_5%

1

C199

0.1U_0402_16V4Z

2

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013311-1
@

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

VSS12

DQ14
DQ15

VSS14

DQ20
DQ21

VSS16

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

VSS24

DQ30
DQ31

VSS26

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2

A15
A14

A11

BA1

S0#

D

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26
28

SM_DRAMRST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44
46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDRB_CKE1DDRB_CKE0

74
76

DDR_B_MA15

78

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6
A4

A2
A0

G2

DDR_B_MA4

92
94

DDR_B_MA2

96

DDR_B_MA0

98
100
102
104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDRB_SCS0#

114

DDRB_ODT0

116
118

DDRB_ODT1

120
122
124

+VREF_CAB

126
128

DDR_B_D32

130

DDR_B_D33

132
134
136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168
170
172

DDR_B_D50

174
176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190
192

DDR_B_D63

194
196
198

PM_SMBDATA

200

PM_SMBCLK

202
204

206

SM_DRAMRST# [5,11]

DDRB_CKE1 [7]DDRB_CKE0[7]

DDRB_CLK1 [7]
DDRB_CLK1# [7]

DDR_B_BS1 [7]

DDRB_SCS0# [7]
DDRB_ODT0 [7]

DDRB_ODT1 [7]

2.2U_0603_6.3V6K
C180

Close to JDDRL2.126

PM_SMBDATA [11,14,40]
PM_SMBCLK [11,14,40]

+1.5V

12

R104
1K_0402_1%

12

R106

0.1U_0402_16V4Z
C181

1

2

1K_0402_1%

1

2

E

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/10/1 2011/11/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM B

PCA70 LA-7521P M/B

E

12 64Tuesday, April 12, 2011

0.1

of

5

+RTCVCC

CMOS Setting, near DDR Door

R111
20K_0402_5%

1 2

PCH_RTCRST#

RC Delay 18~25mS

iME Setting.

R115
20K_0402_5%

D D

*

C C

*

B B

RC Delay 18~25mS

Integrated SUS 1.05V VRM Enable

PCH_INTVRMEN

+RTCVCC

R122

1 2

+RTCVCC

R121

1 2

+3VS

1 2

R126 10K_0402_5%

+3VALW

1 2

R133 10K_0402_5%

PCH_SPKR

High = Enabled (N o Reboot)
Low = Disabled (Default)

+3VS

HDA_SYNC

This signal has a weak internal pull down
H=>On Die PLL is supplied by 1.5V (mobile)
L=>On Die PLL is supplied by 1.8V (DT)
Need to pull high for Huron River platform

AZ_SYNC_HD[47]

HDA_SDO

ME debug mode,
this signal has a weak internal pull down
Low = Disable (default)

*

High = Enable (flash descriptor security overide)

PCH_SPIDI
PCH_SPICLK
PCH_SPICS#
PCH_SPIDO

@

1 2

R131 1K_0402_5%

No mention on SB PDG
but HR mention on PDG
reserve for
Potential Leakage Concern

PWRME_CTRL#[49]

R143 0_0402_5%
R144 0_0402_5%
R145 0_0402_5%
R146 0_0402_5%

PCH_SRTCRST#

1 2

High - Enable Internal VRs
(must be always pulled high)

390K_0402_5%

1 2
1 2
1 2
1 2

PCH_INTVRMEN

1M_0402_5%

SM_INTRUDER#

PCH_GPIO33

PCH_GPIO13

+3VALW

1 2

R139 33_0402_5%

PWRME_CTRL# AZ_SDOUT

R129

1 2

R134 1K_0402_5%@

C203

1U_0402_6.3V6K

C205

1U_0402_6.3V6K

PCH_SPKR

R136 1K_0402_5%@

AZ_SYNC_R

1 2

DI
CLK
CS#
DO

JCOMS1 CONN@

1 2
1 2

JME1 CONN@

1 2
1 2

12

+5VS

G

2

@

Q2

13

D

S

BSS138LT1G_SOT23-3

1 2

R140 0_0402_5%

0_0402_5%@

32.768KHZ_12.5PF_Q13MC14610002

AZ_SYNC

4

12

C202 15P_0402_50V8J
Y1

2

OSC

NC

3

OSC

NC

12

C204 15P_0402_50V8J

AZ_BITCLK_HD[47]

AZ_RST_HD#[47]

+3VALW

AZ_SDOUT_HD[47]

1
4

R113

10M_0402_5%

1 2

R118 33_0402_5%

PCH_SPKR[47]

1 2

R120 33_0402_5%

AZ_SDIN0_HD[47]

@

R124 1K_0402_5%

1 2

R125 33_0402_5%

12

12

PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN

AZ_BITCLK
AZ_SYNC
PCH_SPKR
AZ_RST#

AZ_SDIN0_HD

AZ_SDOUT

PCH_GPIO33
PCH_GPIO13

PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO

PCH_SPICLK
PCH_SPICS#

PCH_SPIDI
PCH_SPIDO

3

U4A

BR39

RTCX1

BN39

RTCX2

BT41

RTCRST#

BN37

SRTCRST#

BM38

INTRUDER#

BN41

INTVRMEN

BU22

HDA_BCLK

BP23

HDA_SYNC

BE56

SPKR

BC22

HDA_RST#

BD22

HDA_SDIN0

BF22

HDA_SDIN1

BK22

HDA_SDIN2

BJ22

HDA_SDIN3

BT23

HDA_SDO

BC25

HDA_DOCK_EN# / GPIO33

BA25

HDA_DOCK_RST# / GPIO13

BA43

JTAG_TCK

BC50

JTAG_TMS

BC52

JTAG_TDI

BF47

JTAG_TDO

AR54

SPI_CLK

AT57

SPI_CS0#

AR56

SPI_CS1#

AU53

SPI_MOSI

AT55

SPI_MISO

BD82CPDS-QMZP-B0_FCBGA942

RTCIHDA

JTAG

SPI

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19

2

LPC_AD0

BK15

LPC_AD1

BJ17

LPC_AD2

BJ20

LPC_AD3

BG20

LPC_FRAME#

BG17
BK17

BA20

SERIRQ

AV52

SATA_PRX_C_DTX_N0

AC56

SATA_PRX_C_DTX_P0

AB55

SATA_PTX_DRX_N0

AE46

SATA_PTX_DRX_P0

AE44

SATA_PRX_C_DTX_N1

AA53

SATA_PRX_C_DTX_P1

AA56

SATA_PTX_DRX_N1

AG49

SATA_PTX_DRX_P1

AG47
AL50

AL49
AL56
AL53

SATA port2 and port3 are disabled on H61

AN46
AN44
AN56
AM55

SATA_PRX_C_DTX_N4

AN49

SATA_PRX_C_DTX_P4

AN50

SATA_PTX_DRX_N4

AT50

SATA_PTX_DRX_P4

AT49
AT46

AT44

Place R128 and R130 within 500

AV50
AV49

mils of the PCH. Avoid routing

AJ53

next to clock pins.

SATAICOMP

AJ55

AE52
AE54

AC52

BF57
BC54
AY52

SATA3_COMP

RBIAS_SATA3

SATA_LED#
CR_WAKE#
GPIO19

R128 37.4_0402_1%

R130 49.9_0402_1%

R132 750_0402_1%

LPC_AD0 [49]
LPC_AD1 [49]
LPC_AD2 [49]
LPC_AD3 [49]

LPC_FRAME# [49]

SERIRQ [ 49]

SATA_PRX_C_DTX_N0 [41]
SATA_PRX_C_DTX_P0 [41]

1 2

C206 0.01U_0402_25V7K

1 2

C207 0.01U_0402_25V7K

SATA_PRX_C_DTX_N1 [41]
SATA_PRX_C_DTX_P1 [41]

1 2

C208 0.01U_0402_25V7K
C209 0.01U_0402_25V7K

C1390 0.01U_0402_25V7K
C1391 0.01U_0402_25V7K

1 2

1 2

1 2

1 2

SATA_PRX_C_DTX_N4 [40]
SATA_PRX_C_DTX_P4 [40]

1 2

1 2

SATA_LED# [50]
CR_WAKE# [44]

+1.05VS_VPCH

+1.05VS_VPCH

12

12

1

SERIRQ

SATA_LED#

CR_WAKE#

GPIO19

SATA_PTX_C_DRX_N0 [41]
SATA_PTX_C_DRX_P0 [41]

SATA_PTX_C_DRX_N1 [41]
SATA_PTX_C_DRX_P1 [41]

R112 10K_0402_5%

R114 10K_0402_5%

R116 10K_0402_5%

R117 10K_0402_5%

HDD

12

12

12

1 2

ODD

for EMI

R137

SATA_PTX_C_DRX_N4 [40]
SATA_PTX_C_DRX_P4 [40]

+RTCVCC

D1

1

1

C210

DAN202UT106_SC70-3

0.1U_0402_16V4Z

2

+3VALW +3VALW+3VALW

R147
200_0402_5%

@

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI

R151
100_0402_1%

1 2

R154 51_0402_1%

12

R148
200_0402_5%

@

12

R152
100_0402_1%

PCH_JTAG_TCK

10_0402_5%

10P_0402_50V8J

R1039

1K_0402_5%

2
3

R149
200_0402_5%

@

1 2

R153
100_0402_1%

1 2

@

C214

@

+3VALW

12

CLK

12

1

2

+RTCBATT

+3VS

+3VS

+3VALW

4M Byte

CS#
DO

A A

U6

1

CS#

2

DO

HOLD#

3

WP#

4

GND

W25Q32BVSSIG_SO8

VCC

8
7
6

CLK

5

DI

1

C212

0.1U_0402_16V4Z

2

CLK
DI

Socket: SP07000F500/SP07000H900
Please close to U2 PCH

5

4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

2

Title

Size Docum ent Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_HDA/JTAG/SATA/SPI/LPC

PCA70 LA-7521P M/B

1

of

13 64Tuesday, April 12, 2011

0.1

5

PCIE_PRX_C_USBTX_N2[45]

USB30

WLAN

D D

TV

Card reader

LAN

PCIE_PRX_C_USBTX_P2[45]
PCIE_PTX_C_USBRX_N2[45]
PCIE_PTX_C_USBRX_P2[45]

PCIE_PRX_WLANTX_N3[42]
PCIE_PRX_WLANTX_P3[42]
PCIE_PTX_C_WLANRX_N3[42]
PCIE_PTX_C_WLANRX_P3[42]

PCIE_PRX_TVTX_N4[42]
PCIE_PRX_TVTX_P4[42]
PCIE_PTX_C_TVRX_N4[42]
PCIE_PTX_C_TVRX_P4[42]

PCIE_PRX_C_RTX_N5[44]
PCIE_PRX_C_RTX_P5[44]
PCIE_PTX_C_CRRX_N5[44]
PCIE_PTX_C_CRRX_P5[44]

PCIE_PRX_C_LANTX_N6[43]
PCIE_PRX_C_LANTX_P6[43]
PCIE_PTX_C_LANRX_N6[43]
PCIE_PTX_C_LANRX_P6[43]

C218 0.1U_0402_16V7K

1 2

C219 0.1U_0402_16V7K

1 2

C226 0.1U_0402_16V7K

12

C227 0.1U_0402_16V7K

12

C222 0.1U_0402_16V7K

1 2

C223 0.1U_0402_16V7K

1 2

C224 0.1U_0402_16V7K

12

C225 0.1U_0402_16V7K

12

C220 0.1U_0402_16V7K

12

C221 0.1U_0402_16V7K

12

PCIE_PRX_C_USBTX_N2
PCIE_PRX_C_USBTX_P2
PCIE_PTX_USBRX_N2
PCIE_PTX_USBRX_P2

PCIE_PRX_WLANTX_N3
PCIE_PRX_WLANTX_P3
PCIE_PTX_WLANRX_N3
PCIE_PTX_WLANRX_P3

PCIE_PRX_TVTX_N4

PCIE_PRX_TVTX_P4
PCIE_PTX_TVRX_N4
PCIE_PTX_TVRX_P4

PCIE_PRX_C_RTX_N5
PCIE_PRX_C_RTX_P5
PCIE_PTX_CRRX_N5
PCIE_PTX_CRRX_P5

PCIE_PRX_C_LANTX_N6
PCIE_PRX_C_LANTX_P6
PCIE_PTX_LANRX_N6
PCIE_PTX_LANRX_P6

PCI-E port7 and port8 are disabled on H61

C C

R168 0_0402_5%
R169 0_0402_5%

USB30

WLAN

TV

Card Reader

LAN

B B

CLK_BCLK_ITP#[5]
CLK_BCLK_ITP[5]

+3VS

R200 10K_0402_5%

A A

1 2

CLK_USB30#[45]
CLK_USB30[45]

CLK_WLAN#[42]
CLK_WLAN[42]

CLKREQ_WLAN#[42]

CLK_TV#[42]
CLK_TV[42]

CLK_CR#[44]
CLK_CR[44]

CLKREQ_LAN#[43]

R7 0_0402_5%@
R5 0_0402_5%@

CLKREQ_WLAN#_R

CLK_LAN#[43]
CLK_LAN[43]

Close to PCH side

1 2
1 2

R190 0_0402_5%
R191 0_0402_5%

1 2
1 2

1 2

R192 0_0402_5%@
R178 0_0402_5%

1 2

1 2

R180 0_0402_5%

R184 0_0402_5%

1 2

1 2

R186 0_0402_5%
R172 0_0402_5%

R173 0_0402_5%

1 2

1 2

1 2

R175 0_0402_5%@

12
12

4

CLK_USB30#_R
CLK_USB30_R

CLK_WLAN#_R
CLK_WLAN_R

CLKREQ_WLAN#_R

CLK_TV#_R
CLK_TV_R

CLK_CR#_R
CLK_CR_R

CLK_LAN#_R
CLK_LAN_R

CLKREQ_LAN#_R

CLK_CPU_ITP#
CLK_CPU_ITP

U4B

J20

PERN1

L20

PERP1

F25

PETN1

F23

PETP1

P20

PERN2

R20

PERP2

C22

PETN2

A22

PETP2

H17

PERN3

J17

PERP3

E21

PETN3

B21

PETP3

P17

PERN4

M17

PERP4

F18

PETN4

E17

PETP4

N15

PERN5

M15

PERP5

B17

PETN5

C16

PETP5

J15

PERN6

L15

PERP6

A16

PETN6

B15

PETP6

J12

PERN7

H12

PERP7

F15

PETN7

F13

PETP7

H10

PERN8

J10

PERP8

B13

PETN8

D13

PETP8

AE6

CLKOUT_PCIE0N

AC6

CLKOUT_PCIE0P

AA5

CLKOUT_PCIE1N

W5

CLKOUT_PCIE1P

AB12

CLKOUT_PCIE2N

AB14

CLKOUT_PCIE2P

AV43

PCIECLKRQ2# / GPIO20

AB9

CLKOUT_PCIE3N

AB8

CLKOUT_PCIE3P

Y9

CLKOUT_PCIE4N

Y8

CLKOUT_PCIE4P

AF3

CLKOUT_PCIE5N

AG2

CLKOUT_PCIE5P

BL54

PCIECLKRQ5# / GPIO44

AE12

CLKOUT_PEG_B_N

AE11

CLKOUT_PEG_B_P

AB3

CLKOUT_PCIE6N

AA2

CLKOUT_PCIE6P

AV44

PCIECLKRQ6# / GPIO45

AE2

CLKOUT_PCIE7N

AF1

CLKOUT_PCIE7P

BP55

PCIECLKRQ7# / GPIO46

R52

CLKOUT_ITPXDP_N

N52

CLKOUT_ITPXDP_P

BD82CPDS-QMZP-B0_FCBGA942

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

CLKIN_GND1_N
CLKIN_GND1_P

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_GND0_N
CLKIN_GND0_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

3

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N
CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

PCH_GPIO11

BN49

PCH_SMBCLK

BT47

PCH_SMBDATA

BR49

PCH_GPIO60

BU49

PCH_SMLCLK0

BT51

PCH_SMLDATA0

BM50

PCH_GPIO74

BR46

PCH_SMLCLK1

BJ46

PCH_SMLDATA1

BK46

BA50

Control Link only for support Intel IAMT.

BF50

BF49

R165 0_0402_5%
R167 0_0402_5%

AG8
AG9

P31
R31

N56
M55

P33
R33

W53
V52

R27
P27

BD38
BF38

AF55
AG56

AN8

BD15

AJ3
AJ5

AL2

AT9
BA5
AW5
BA2

CLK_PCIE_VGA#_R
CLK_PCIE_VGA_R

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_DPLL#
CLK_DPLL

PCH_CLK_DMI#
PCH_CLK_DMI

CLKIN_GND0#
CLKIN_GND0

CLKIN_GND1#
CLKIN_GND1

CLK_DOT#
CLK_DOT

CLK_SATA#
CLK_SATA

CLK_14M_PCH

CLK_PCILOOP

PCH_X1
PCH_X2

XCLK_RCOMP

CLK_FLEX0
CLK_FLEX1
CLK_FLEX2
CLK_FLEX3

1 2
1 2

CLK_CPU_DMI# [5]
CLK_CPU_DMI [5]

T65 PAD
T66 PAD

CLK_PCILOOP [17]

1 2

R194 90.9_0402_1%

T252 PAD
T176 PAD
T177 PAD
T178 PAD

2

R155 2.2K_0402_5%

+3VALW +3VS

CLK_PCIE_VGA# [2 2 ]
CLK_PCIE_VGA [22]

12

R156 2.2K_0402_5%

12

PCH_SMBDATA

PCH_SMBCLK

PCH_SMLDATA1

PCH_SMLCLK1

3 4

R159 2.2K_0402_5%

12

R160 2.2K_0402_5%

12

VGA

6 1

5

Q4A
2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6
Q4B

6 1

2N7002KDWH_SOT363-6

5

3 4

PCH_GPIO11
PCH_GPIO60
PCH_GPIO74
PCH_SMLCLK0
PCH_SMLDATA0

Q5A

2N7002KDWH_SOT363-6
Q5B

2

2

1

R157 4.7K_0402_5%

R158 4.7K_0402_5%

PM_SMBDATA [11,12,40]

+3VS+3VALW

EC_SMB_DA2 [23,49,52]

EC_SMB_CK2 [23,49,52]

R161 10K_0402_5%

1 2

R162 2.2K_0402_5%
R163 10K_0402_5%
R164 2.2K_0402_5%
R166 2.2K_0402_5%

12

1 2

12
12

not using eDP level NC

From Clock Gen.

PCH_CLK_DMI#
PCH_CLK_DMI

CLKIN_GND1#
CLKIN_GND1

CLK_DOT#
CLK_DOT

CLK_SATA#
CLK_SATA

CLK_14M_PCH
CLKIN_GND0#

CLKIN_GND0

R174 10K_0402_5%

1 2

R176 10K_0402_5%

1 2

R177 10K_0402_5%

1 2

R179 10K_0402_5%

1 2

R181 10K_0402_5%

1 2

R182 10K_0402_5%

1 2

R183 10K_0402_5%

1 2

R185 10K_0402_5%

1 2

R187 10K_0402_5%

1 2

R188 10K_0402_5%

1 2

R189 10K_0402_5%

1 2

For EMI

+1.05VS_VPCH

CLK_PCILOOP

27P_0402_50V8J

@

12

R193 10_0402_5%

R198 1M_0402_5%

PCH_X1 PCH_X2

1 2

25MHZ_20PF_X5H025000DK1H

1

C229

2

C228 22P_0402_50V8J

12

Y2

PM_SMBCLK [11,12,40]

+3VALW

@

12

1

C230
27P_0402_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_PCI-E/SMBUS/CLK

PCA70 LA-7521P M/B

14 64Tuesday, April 12, 2011

1

0.1

of

5

4

3

2

1

DMI_CTX_PRX_N0[6]
DMI_CTX_PRX_N1[6]
DMI_CTX_PRX_N2[6]

+1.05VS_VPCH

PM_PWROK

DRAMPWROK[5]

SUSWARN#[49]

PBTN_OUT#[49]

+3VALW

DMI_CTX_PRX_N3[6]
DMI_CTX_PRX_P0[6]

DMI_CTX_PRX_P1[6]
DMI_CTX_PRX_P2[6]
DMI_CTX_PRX_P3[6]

DMI_PTX_CRX_N0[6]
DMI_PTX_CRX_N1[6]
DMI_PTX_CRX_N2[6]
DMI_PTX_CRX_N3[6]

DMI_PTX_CRX_P0[6]
DMI_PTX_CRX_P1[6]
DMI_PTX_CRX_P2[6]
DMI_PTX_CRX_P3[6]

1 2

R210 49.9_0402_1%

1 2

R212 750_0402_1%

R215 0_0402_5%@

1 2

R1063 0_0402_5%

@

1 2

R219 0_0402_5%

@

1 2

R1064 0_0402_5%

@

R220 10K_0402_5%

EC_SWI#[49]

+3VALW

D D

SYS_PWROK

C C

Stuff R137 if EC does not want to
involve in the handshake mechanism
for the DeepSX state entry and exit

B B

R204 10K_0402_5%
R205 10K_0402_5%
R206 10K_0402_5%

R208 10K_0402_5%
R209 10K_0402_5%

0.1U_0402_16V4Z

VGATE[49,58]

PM_PWROK[49]

12
12
12

12
12

1 2

C231

1
2

@

R217 0_0402_5%

SUSWARN#_R
EC_SWI#_R
PCH_GPIO72

PCH_RSMRST#
PM_PWROK

+3VS

U9

5

SN74AHC1G08DCKR_SC70-5

P

IN1

4

O

IN2

G

3

SUSWARN#_RSUSACK#

12

12

R211
10K_0402_5%

XDP_DBRESET#[5]

PCH_RSMRST#[49]

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_COMP

RBIAS_CPY

SUSACK#

XDP_DBRESET#

SYS_PWROK

1 2

PWROK_R

DRAMPWROK

PCH_RSMRST#_R

SUSWARN#_R

PBTN_OUT#_R

PCH_GPIO31

12

PCH_GPIO72

EC_SWI#_R

1 2

R1009 0_0402_5%

U4C

D33

DMI0RXN

A36

DMI1RXN

B37

DMI2RXN

E37

DMI3RXN

B33

DMI0RXP

B35

DMI1RXP

C36

DMI2RXP

F38

DMI3RXP

J36

DMI0TXN

P38

DMI1TXN

H38

DMI2TXN

M41

DMI3TXN

H36

DMI0TXP

R38

DMI1TXP

J38

DMI2TXP

P41

DMI3TXP

E31

DMI_ZCOMP

B31

DMI_IRCOMP

A32

DMI2RBIAS

BP45

SUSACK#

BE52

SYS_RESET#

BJ53

SYS_PWROK

BJ38

PWROK

BC46

APWROK

BG46

DRAMPWROK

BK38

RSMRST#

BU46

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

BT43

PWRBTN#

BG43

GPIO31

AV46

BATLOW# / GPIO72

BJ48

RI#

BD82CPDS-QMZP-B0_FCBGA942

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

F45
H41
C46
B45
B47
J43
M43

B43
F43
J41
D47
A46
C49
H43
P43

H46
B51
C52
E49
D51

BR42

BT37

BC44

BC56

BN54

BA47

BH50

BN52

BM53

BC41

BD43

F55

BH49

FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWVREN

PCH_DPWROK

PCIE_WAKE#

PM_CLKRUN#

SUS_STAT#

SUSCLK_P

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

FDI_CTX_PRX_N0

C42

FDI_CTX_PRX_N0 [6]
FDI_CTX_PRX_N1 [6]
FDI_CTX_PRX_N2 [6]
FDI_CTX_PRX_N3 [6]
FDI_CTX_PRX_N4 [6]
FDI_CTX_PRX_N5 [6]
FDI_CTX_PRX_N6 [6]
FDI_CTX_PRX_N7 [6]

FDI_CTX_PRX_P0 [6]
FDI_CTX_PRX_P1 [6]
FDI_CTX_PRX_P2 [6]
FDI_CTX_PRX_P3 [6]
FDI_CTX_PRX_P4 [6]
FDI_CTX_PRX_P5 [6]
FDI_CTX_PRX_P6 [6]
FDI_CTX_PRX_P7 [6]

FDI_INT [6]
FDI_FSYNC0 [6]
FDI_FSYNC1 [6]
FDI_LSYNC0 [6]
FDI_LSYNC1 [6]

PCIE_WAKE# [42,43,45]

T69 PAD

T253 PAD

PM_SLP_S5# [49]

PM_SLP_S4# [49]

PM_SLP_S3# [49]

T70 PAD

T71 PAD

H_PM_SYNC [5]

32.768 KHz

1 2

R207 0_0402_5%@

PCH_RSMRST#PCH_DPWROK

Stuff R222 if do not support DeepSX state

+RTCVCC

DSWVREN

DSWVREN - Internal Deep Sleep 1.05V regulator
H

：

*

LGDisable

PM_CLKRUN#

PCIE_WAKE#
PCH_GPIO29

PCH_GPIO29 default GPI
PU to +3VALW base on module design.

H_PM_SYNC

ESD request Close to U4.F55

R213 390K_0402_5%

1 2

Enable

@

R218 8.2K_0402_5%

R221 1K_0402_5%
R222 10K_0402_5%

1 2

C1595 0.1U_0402_16V4Z

1 2

1 2
1 2

+3VS

+3VALW

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_DMI/FDI/PM

PCA70 LA-7521P M/B

15 64Tuesday, April 12, 2011

1

0.1

of

5

NOTE:PCH adds support for panel power sequencing required for
embedded DisplayPort support. L_VDDEN, L_BKLTEN and L_BKLTCTL pins are
added on the PCH for panel power sequencing. It is important to note that a 6
layer board design may be required to access these pins on the PCH package
in a fully featured platform design.

UMA_ENBKL[49]

D D

C C

T73 PAD
T74 PAD

T229 PAD
T230 PAD
T231 PAD

T232 PAD
T233 PAD

T234 PAD
T235 PAD

T75 PAD
T76 PAD
T77 PAD
T78 PAD
T80 PAD
T82 PAD
T83 PAD
T84 PAD
T85 PAD
T86 PAD
T88 PAD
T89 PAD
T91 PAD
T93 PAD
T95 PAD
T97 PAD
T99 PAD
T101 PAD
T103 PAD
T105 PAD
T106 PAD
T107 PAD
T108 PAD
T109 PAD
T110 PAD
T111 PAD
T112 PAD
T113 PAD
T114 PAD
T115 PAD
T116 PAD
T117 PAD
T118 PAD
T119 PAD
T120 PAD
T121 PAD

R246 1K_0402_0.5%

For debug only

4

UMA_ENBKL
UMA_ENVDD
PCH_PWM

UMA_CRT_B
UMA_CRT_G
UMA_CRT_R

UMA_CRT_CLK
UMA_CRT_DATA

UMA_CRT_HSYNC
UMA_CRT_VSYNC

CRT_IREF

12

U4D

AG18

L_BKLTEN

AG17

L_VDD_EN

AG12

L_BKLTCTL

P22

TP1

L31

TP2

L33

TP3

M38

TP4

L36

TP5

Y18

TP6

Y17

TP7

AB18

TP8

AB17

TP9

BM46

TP10

BA27

TP11

BC49

TP12

AE49

TP13

AE41

TP14

AE43

TP15

AE50

TP16

BA36

TP17

AY36

TP18

Y14

TP19

Y12

TP20

H31

TP21

J27

TP22

J25

TP23

L22

TP24

J31

TP25

L27

TP26

L25

TP27

J22

TP28

C29

TP29

F28

TP30

C26

TP31

B25

TP32

E29

TP33

E27

TP34

B27

TP35

D25

TP36

AM1

CRT_BLUE

AN2

CRT_GREEN

AN6

CRT_RED

AW3

CRT_DDC_CLK

AW1

CRT_DDC_DATA

AR4

CRT_HSYNC

AR2

CRT_VSYNC

AT3

DAC_IREF

AM6

CRT_IRTN

BD82CPDS-QMZP-B0_FCBGA942

3

SDVO_INTN
SDVO_INTP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

U9
U8

U5
W3

T3
U2

AL15
AL17

R9
R8
T1

R12
R14
M12
M11
K8
H8
M3
L5

AL12
AL14

U12
U14
N2

J3
L2
G4
G2
F5
F3
E2
E4

AL9
AL8

R6
N6
M1

B5
D5
D7
C6
C9
B7
B11
E11

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

RSVD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DDPD_AUXP

UMA_HDMI_CLK
UMA_HDMI_DATA

DDPB_AUXN
DDPB_AUXP
HDMI_HPD

UMA_HDMI_TX2­UMA_HDMI_TX2+
UMA_HDMI_TX1­UMA_HDMI_TX1+
UMA_HDMI_TX0­UMA_HDMI_TX0+
UMA_HDMI_TXC­UMA_HDMI_TXC

PCH_HDMI_CLK
PCH_HDMI_DATA

DDPC_AUXN
DDPC_AUXP
DDPC_HDP

PCH_HDMIOUT_CLK
PCH_HDMIOUT_DATA

DDPD_AUXN
DDPD_AUXP
DDPD_HDP

T199PAD
T200PAD

T201PAD
T202PAD
T203PAD

T90PAD
T92PAD
T94PAD
T96PAD
T98PAD
T100PAD
T102PAD
T104PAD

T204PAD
T205PAD

DDPC_HDP [36]

T220PAD
T221PAD

DDPD_HDP [38]

2

PCH_HDMI_CLK [36]
PCH_HDMI_DATA [ 36]

PCH_HDMI_TX2- [36]
PCH_HDMI_TX2+ [36]
PCH_HDMI_TX1- [36]
PCH_HDMI_TX1+ [36]
PCH_HDMI_TX0- [36]
PCH_HDMI_TX0+ [36]
PCH_HDMI_CLK- [36]
PCH_HDMI_CLK+ [36]

PCH_HDMIOUT_CLK [3 8]
PCH_HDMIOUT_DATA [38]

PCH_HDMIOUT_TX2- [38]
PCH_HDMIOUT_TX2+ [38]
PCH_HDMIOUT_TX1- [38]
PCH_HDMIOUT_TX1+ [38]
PCH_HDMIOUT_TX0- [38]
PCH_HDMIOUT_TX0+ [38]
PCH_HDMIOUT_CLK- [38]
PCH_HDMIOUT_CLK+ [38]

R242 100K_0402_5%

DDPC_HDP

R243 100K_0402_5%

HDMI
(To Scale)

DDPD_HDP

R1586 100K_0402_5%

HDMI OUT
(To Conn.)

UMA@

DIS@

1 2

1 2

1

12

+3VS

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_CRT/LVDS/HDMI

PCA70 LA-7521P M/B

1

0.1

of

16 64Tuesday, April 12, 2011

5

4

3

2

1

PCI PU resistor

+3VS

R253 8.2K_0402_5%

1 2

R254 8.2K_0402_5%

1 2

R255 8.2K_0402_5%

1 2

R256 8.2K_0402_5%

1 2

R259 8.2K_0402_5%

1 2

R260 8.2K_0402_5%

1 2

R261 8.2K_0402_5%

D D

C C

1 2

R262 8.2K_0402_5%

1 2

R263 8.2K_0402_5%

1 2

R264 8.2K_0402_5%

1 2

R266 8.2K_0402_5%

1 2

R267 8.2K_0402_5%

1 2

R269 8.2K_0402_5%

1 2

+3VS

R270 8.2K_0402_5%

1 2

R271 8.2K_0402_5%

1 2

R272 8.2K_0402_5%

1 2

R276 8.2K_0402_5%

1 2

R277 8.2K_0402_5%

1 2

R278 8.2K_0402_5%

1 2

R279 8.2K_0402_5%

1 2

Intel confirm GPIO19 is correct.

Boot BIOS Strap

PCH_GNT1#

0
0
1

GPIO19 Boot BIOS Loaction

0
1
0

11

B B

For CR D3E wake up reserve

A A

PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#

PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_PLOCK#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCH_REQ0#

DGPU_HOLD_RST#
PCH_GPIO52
DGPU_PWR_EN

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
CR_CPPE#

LPC

Reserved

PCI
SPI

CLK_PCILOOP[14]
CLK_PCI_EC[49]

R250

@

0_0402_5%

1 2

+3VS

U4E

BF15

AD0

BF17

AD1

BT7

AD2

BT13

AD3

BG12

AD4

BN11

AD5

BJ12

AD6

BU9

AD7

BR12

AD8

BJ3

AD9

BR9

AD10

BJ10

AD11

BM8

AD12

BF3

AD13

BN2

AD14

BE4

AD15

BE6

AD16

BG15

AD17

BC6

AD18

BT11

AD19

BA14

AD20

BL2

AD21

BC4

AD22

BL4

AD23

BC2

AD24

BM13

AD25

BA9

AD26

BF9

AD27

BA8

AD28

BF8

AD29

AV17

AD30

BK12

AD31

BN4

C/BE0#

BP7

C/BE1#

BG2

*

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCH_REQ0#

Have internal PU

PAD
PAD
PAD
PAD

T123PAD

PAD
PAD

R28122_0402_5%

R28222_0402_5%

PAD

DGPU_HOLD_RST#
PCH_GPIO52
DGPU_PWR_EN

PCH_GNT0#
PCH_GNT1#
PCH_GNT2#
PCH_GNT3#

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
CR_CPPE#

PCI_PME#
PCH_PLT_RST#

CLK_PCILOOP_R

CLK_PCI_EC_R

DGPU_HOLD_RST#[22]
DGPU_PWR_EN[26,60]

T195
T196
T197
T198

CR_CPPE#[44]

T179
T180

1 2

1 2

T181

C/BE2#

BP13

C/BE3#

BK10

PIRQA#

BJ5

PIRQB#

BM15

PIRQC#

BP5

PIRQD#

BG5

REQ0#

BT5

REQ1# / GPIO50

BK8

REQ2# / GPIO52

AV11

REQ3# / GPIO54

BA15

GNT0#

AV8

GNT1# / GPIO51

BU12

GNT2# / GPIO53

BE2

GNT3# / GPIO55

BN9

PIRQE# / GPIO2

AV9

PIRQF# / GPIO3

BT15

PIRQG# / GPIO4

BR4

PIRQH# / GPIO5

AV15

PME#

BK48

PLTRST#

AT11

CLKOUT_PCI0

AN14

CLKOUT_PCI1

AT12

CLKOUT_PCI2

AT17

CLKOUT_PCI3

AT14

CLKOUT_PCI4

BD82CPDS-QMZP-B0_FCBGA942

PCI

EHCI 1

EHCI 2

USB

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

SERR#

PCIRST#

PLOCK#

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PCI_DEVSEL#

BH9

PCI_FRAME#

BC11

PCI_IRDY#

BF11

PCI_TRDY#

BC8

PCI_STOP#

BC12

PAR

BH8

PCI_PERR#

BM3

PCI_SERR#

BR6

AV14

PCI_PLOCK#

BA17

USB20_N0

BF36

USB20_P0

BD36

USB20_N1

BC33

USB20_P1

BA33

USB20_N2

BM33

USB20_P2

BM35

USB20_N3

BT33

USB20_P3

BU32

USB20_N4

BR32

USB20_P4

BT31

USB20_N5

BN29

USB20_P5

BM30
BK33
BJ33

USB port6 and port7 are disabled on H61

BF31
BD31

USB20_N8

BN27

USB20_P8

BR29

USB20_N9

BR26

USB20_P9

BT27

USB20_N10

BK25

USB20_P10

BJ25

USB20_N11

BJ31

USB20_P11

BK31
BF27
BD27

USB port12 and port13 are disabled on H61

BJ27
BK27

USBBIAS

BP25

BM25

USB_OCI

BM43

USB_OC#1

BD41

USB_OC#2

BG41

USB_OC#3

BK43

USB_OC#4

BP43

USB_OC#5

BJ41

USB_OC#6

BT45

USB_OC#7

BM45

T122PAD

USB20_N0 [ 4 6]
USB20_P0 [46]
USB20_N1 [ 4 6]
USB20_P1 [46]
USB20_N2 [ 5 0]
USB20_P2 [50]
USB20_N3 [ 5 0]
USB20_P3 [50]
USB20_N4 [ 4 0]
USB20_P4 [40]
USB20_N5 [ 4 1]
USB20_P5 [41]

USB20_N8 [ 4 1]
USB20_P8 [41]
USB20_N9 [ 4 1]
USB20_P9 [41]
USB20_N10 [4 2]
USB20_P10 [42]

T254

PAD

T255

PAD

1 2

R280 22.6_0402_1%

USB_OCI [45,46]
USB_OC#2 [40,41]
USB_OC#4 [ 41]

Reserve for USB30 PORT0@ CONN2
Reserve for USB30 PORT1@ CONN1
Touch
Int. Camera
eSATA+USB
USB PORT5 CONN6

USB PORT8 CONN4
USB PORT9 CONN3
TV Tuner #1
Reserve

USB30 PORT 0,1
USB PORT 4,5
USB PORT 8,9

Layout Note:USB_BIAS WITH
LENGTH NO MORE THAN 500
MILS TO RESISTOR.

+3VS

PCH_PLT_RST#

NC7SZ08P5X_NL_SC70-5

+3VS

NC7SZ08P5X_NL_SC70-5

USB_OCI
USB_OC#1
USB_OC#4
USB_OC#2
USB_OC#3
USB_OC#5
USB_OC#6
USB_OC#7

1

2

5

U10

2

P

B

Y

1

A

G

3

100K_0402_5%

+3VS

1

2

5

2

P

B

Y

1

A

G

U57

3

100K_0402_5%

R283 10K_0402_5%
R284 10K_0402_5%
R285 10K_0402_5%
R286 10K_0402_5%
R287 10K_0402_5%
R288 10K_0402_5%
R1011 10K_0402_5%
R1012 10K_0402_5%

C1047

0.1U_0402_16V4Z

PLT_RST#

4

R257

C1048

0.1U_0402_16V4Z

4

R1067

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PLT_RST# [5,22,45,49]

12

PLT_A_RST# [42,43,44]

12

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2010/10/1 2011/11/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_PCI/USB/NAND

PCA70 LA-7521P M/B

17 64Tuesday, April 12, 2011

1

0.1

of

1 2
1 2

5

12

PCH_GPIO15
PCH_GPIO12
PCH_GPIO57

+3VALW +3VS

R296 1K_0402_5%
R303 10K_0402_5%
R298 10K_0402_5%

GPIO8

Integrated Clock Chip Enable (Removed)
H: Disable

*

D D

L: Enable

+3VALW

12

R300
10K_0402_5%

EC_SMI#

R331
1K_0402_5%

@

1 2

Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable

+3VALW

C C

R325 10K_0402_5%

In Deep Sleep Power Well. Unmuxed.
Defaults to GPI.
Not used Weak pull-up 10k

-->Check list1.5 P402.
PD to GND for Huron River!!

12

PCH_GPIO27

to VccDSW3_3

Ω

GPIO28

On-Die PLL Voltage Regulator
H: Enable

*

L: Disable

+3VALW

12

R305
1K_0402_5%

PCH_GPIO28

R330

B B

1K_0402_5%

@

1 2

1 2

R1071 10K_0402_5%

1 2

R1072 10K_0402_5%

SATA2GP/GPIO36 & SATA3GP/GPIO37Sampled at
Rising edge of PWROK.Weak internal pull-down.
(weak internal pull-down is disabled
after PLTRST# de-asserts)
NOTE: This signal should NOT be
pulled high when strap is sampled

PCH_GPIO36
PCH_GPIO37

ISDBT_DET

+3VS

A A

R320
10K_0402_5%

1 2

R326
47K_0402_5%

@

1 2

ISDBT_DET

5

4

DGPU_HPD_INT#[38]

USB30_SMI#[45]

For OPT

VGA_PWROK[60]

4

1 2

R307 10K_0402_5%

1 2

R308 10K_0402_5%

1 2

R310 10K_0402_5%

1 2

R311 10K_0402_5%

1 2

R312 10K_0402_5%

1 2

R315 10K_0402_5%

1 2

R317 10K_0402_5%

1 2

R318 10K_0402_5%

1 2

R1068 10K_0402_5%

1 2

R319 10K_0402_5%

1 2

R321 10K_0402_5%
R1030 2.2K_0402_5%

12

1 2

R1647 0_0402_5%@

1 2

R1101 0_0402_5%

EC_SCI#[49]
EC_SMI#[49]

1 2

R1065 0_0402_5%

T126PAD

ISDBT_DET[42]

@

PCH_GPIO1
USB30_SMI#_R
EC_SCI#
EC_SMI#
PCH_GPIO12
PCH_GPIO15

PCH_GPIO16

VGA_PWROK_R
PCH_GPIO22

PCH_GPIO27
PCH_GPIO28
PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
ISDBT_DET
PCH_GPIO49
PCH_GPIO57

3

PCH_GPIO0
PCH_GPIO1
USB30_SMI#_R
EC_SCI#
PCH_GPIO16
VGA_PWROK_R
PCH_GPIO22
PCH_GPIO34
PCH_GPIO38
PCH_GPIO39
PCH_GPIO49
PCH_GPIO35

U4F

AW55

BMBUSY# / GPIO0

BR19

TACH1 / GPIO1

BA22

TACH2 / GPIO6

BR16

TACH3 / GPIO7

BP51

GPIO8

BK50

LAN_PHY_PWR_CTRL / GPIO12

BM55

GPIO15

AU56

SATA4GP / GPIO16

BT17

TACH0 / GPIO17

BA53

SCLOCK / GPIO22

BP53

GPIO24 / MEM_LED

BJ43

GPIO27

BJ55

GPIO28

BL56

STP_PCI# / GPIO34

BJ57

GPIO35 / NMI#

BB55

SATA2GP / GPIO36

BG53

SATA3GP / GPIO37

BE54

SLOAD / GPIO38

BF55

SDATAOUT0 / GPIO39

AW53

SDATAOUT1 / GPIO48

BA56

SATA5GP / GPIO49

BT53

GPIO57

A4

VSS_NCTF[1]

A6

VSS_NCTF[2]

B2

VSS_NCTF[3]

BM1

VSS_NCTF[4]

BM57

VSS_NCTF[5]

BP1

VSS_NCTF[6]

BP57

VSS_NCTF[7]

BT2

VSS_NCTF[8]

BU4

VSS_NCTF[9]

BU52

VSS_NCTF[10]

BU54

VSS_NCTF[11]

BU6

VSS_NCTF[12]

D1

VSS_NCTF[13]

F1

VSS_NCTF[14]

BD82CPDS-QMZP-B0_FCBGA942

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

Project ID GPIO700GPIO71GPIO69

SKU1
SKU2
SKU3
SKU4

x

0
0
0

1
x
x
x
x
x
x
x

TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

GPIO

NCTF

2010/10/1 2011/11/01

THRMTRIP#

CPU/MISC

INIT3_3V#

NC_1

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

PWM0
PWM1
PWM2
PWM3

DF_TVS

RESERVED [29]
RESERVED [28]
RESERVED [27]
RESERVED [26]
RESERVED [25]
RESERVED [24]
RESERVED [23]
RESERVED [22]
RESERVED [21]
RESERVED [20]
RESERVED [19]
RESERVED [18]
RESERVED [17]
RESERVED [16]
RESERVED [15]
RESERVED [14]
RESERVED [13]
RESERVED [12]
RESERVED [11]
RESERVED [10]

RESERVED [9]
RESERVED [8]
RESERVED [7]
RESERVED [6]
RESERVED [5]
RESERVED [4]
RESERVED [3]
RESERVED [2]
RESERVED [1]

Compal Secret Data

0

0

1

1

1

11

BT_LED#

BU16

PCH_GPIO69

BM18

PCH_GPIO70

BN17

PCH_GPIO71

BP15

GATEA20

BB57

PCH_PECI_R

H48

KB_RST#

BG56

H_PWRGOOD

D53
E56
BN56
AY20

A54
A52
F57
D57

BN21
BT21
BM20
BN19

BC43

SST

Internal Pull Down

R47
M48

K50
K49
AB46
G56
Y44
L53
AB50
Y50
K46
L56
J55
F53
H52
E52
AB49
AB44
U49
R44
U50
U46
U44
H50
Y41
R50
M50
M49
U43
J57

Deciphered Date

NV_CLE

2

00
0
1
1 1
00
00
1
1

0
1

@

1 2

R306 0_0402_5%

2

C1613

0.1U_0402_16V4Z

1

2

1

PROJECT ID TABLE

1
0

1
0
1
00
1

+3VS +3VS +3VS

12

GPIO69_H@

R1031
10K_0402_5%

PCH_GPIO69 PCH_GPIO70 PCH_GPIO71

12

GPIO69_L@

R1032
10K_0402_5%

12

12

GPIO70_H@

R1033
10K_0402_5%

GPIO70_L@

R1034
10K_0402_5%

12

GPIO71_H@

R1035
10K_0402_5%

12

GPIO71_L@

R1036
10K_0402_5%

0
1

+3VS

BT_LED# [49]

GATEA20 [49]
H_PECI [5, 49]
KB_RST# [49]
H_PWRGOOD [5]
H_THERMTRIP# [5]

BT_LED#PCH_GPIO0
GATEA20
KB_RST#

H_PWRGOOD
GATEA20

ESD request Close to U4.BB57

DMI & FDI Termination Voltage

Set to VCC when HIGH

NV_CLE

Set to VSS when LOW

R329 1K_0402_5%

Note:Place R329 close to U1.R47
and <=100 mils

ESD request Close to U4.R47

12

NV_CLE

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

C1598 0.1U_0402_16V4Z

Compal Electronics, Inc.

PCH_CPU/GPIO

PCA70 LA-7521P M/B

1 2

R297 10K_0402_5%

1 2

R299 10K_0402_5%

1 2

R301 10K_0402_5%

1 2

C1597 0.1U_0402_16V4Z

1 2

C1596 0.1U_0402_16V4Z

+1.8VS

12

R328

2.2K_0402_5%

C243

0.1U_0402_16V4Z

@

18 64Tuesday, April 12, 2011

H_SNB_IVB# [5]

of

1

2

1

0.1

5

+1.05VS_VPCH +1.05VS_VPCH

1

1

1

C258

C254

10U_0603_6.3V6M

2

D D

C C

+VCCSATAPLL

C305

@

10U_0603_6.3V6M

B B

1

2

Near U56

+VCCAPLLEXP

C251

@

10U_0603_6.3V6M

1

2

+1.05VS_VPCH

C304

1U_0402_6.3V6K

1

2

+1.05VS_VPCH

C252

@

1U_0402_6.3V6K

1

2

1 2

R337

@

0_0805_5%

+1.05VS_VPCH

R352 0_0603_5%@

+1.05VS_VPCH
+1.05VS_VPCH

+1.05VS_VPCH
+1.05VS_VPCH

+VCCP_VCCDMI

1

2

1 2

C255

1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCCP_VCCDMI

C253
1U_0402_6.3V6K

+1.05VS_VPCH

1U_0402_6.3V6K

This pin can be left as NC if
On-Die VR is enabled (Default)

L6 10UH_LB2012T100MR_20%@

1 2

L1 1UH_LB2012T1R0M_20%@
R342 0_0603_5%@
R348 0_0603_5%@

1 2

L3 10UH_LB2012T100MR_20%@

1

C256

1U_0402_6.3V6K

2

2

Note:+VCCP_VCCDMI trace need to be at
least 20 mils width with full VSS/VCC
reference plane)

1

C250

2

12

12

12

Near B53

+VCCAPLL_CPY_PCH

C275

@

A A

10U_0603_6.3V6M

C276

@

1U_0402_6.3V6K

1

1

2

2

Near A19

5

1

C257

1U_0402_6.3V6K

2

1

C306
1U_0402_6.3V6K

2

+VCCSATAPLL
+VCCDPLL_CPY
+VCCAPLLEXP
+1.05VS_VCCAPLL_FDI

C263 1U_0402_6.3V6K@

1 2

+VCCACLK
+VCCAPLL_CPY_PCH

C297

4

4

1U_0402_6.3V6K

1

Near Y20

2

U4G

F20

VCCIO_24

F30

VCCIO_25

V25

VCCIO_26

V27

VCCIO_27

V31

VCCIO_28

V33

VCCIO_29

Y24

VCCIO_30

Y26

VCCIO_31

Y30

VCCIO_32

Y32

VCCIO_33

Y34

VCCIO_34

AA34

VCCIO_22

AA36

VCCIO_23

V22

VCCIO_35

Y20

VCCIO_36

Y22

VCCIO_37

B41

VCCDMI_2

E41

VCCDMI_1

AL40

VCCIO_8

AN40

VCCIO_9

AN41

VCCIO_10

AG38

VCCIO_20

AG40

VCCIO_21

AG41

VCCIO_7

U56

VCCAPLLSATA

BA38

B53
C54

AL5
A19

PLL

VCCIO_19
VCCAPLLEXP
VCCAFDIPLL

VCCACLK
VCCAPLLDMI2

BD82CPDS-QMZP-B0_FCBGA942

3

POWER

1

C245

2

1U_0402_6.3V6K

C282

1U_0402_6.3V6K

1

2

Deciphered Date

1U_0402_6.3V6K

1

C246

C247

2

1U_0402_6.3V6K

C281

10U_0805_10V4Z

1

2

R367 0_0603_5%@

1 2

+1.05VS_VPCH

C308

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1 2

R353

@

0_0805_5%

+1.05VS_VPCH

1

2

Near AC20

C303

VCCASW_4
VCCASW_5
VCCASW_6
VCCASW_7
VCCASW_8
VCCASW_9

VCCASW_3
VCCASW_2
VCCASW_1

VCCIO_18

VCCSSC_1
VCCSSC_2

VCCIO_1
VCCIO_2
VCCIO_3

VCCIO_4
VCCIO_13
VCCIO_12
VCCIO_11
VCCIO_14

AC24
AC26
AC28
AC30
AC32
AE24
AE28
AE30
AE32
AE34
AE36
AG32
AG34
AJ32
AJ34
AJ36
AL32
AL34
AN32
AN34
AR32
AR34

AG24
AG26
AG28
AJ24
AJ26
AJ28
AL24
AL28
AN22
AN24
AN26
AN28
AR24
AR26
AR28
AR30
AR36
AR38
AU30
AU36

AU34
AV36
AU32

AE15
AE17
AG15
AJ20
AE40

AC20
AE20

AV24
AV26
AY25
AY27

V36
Y36
AJ38
Y28

C244
10U_0603_6.3V6M

+1.05VS_VCCASW

C284

+1.05VS_VCCDIFFCLKN

+1.05VS_VPCH

@

C259

10U_0603_6.3V6M

2010/10/1 2011/11/01

3

C283

1U_0402_6.3V6K

1

2

1

C299
1U_0402_6.3V6K

2

+1.05VS_VPCH

1

2

Near AJ20

1

2

1U_0402_6.3V6K

1

2

+1.05VS_SSCVCC

+1.05VS_VPCH

1

C260
1U_0402_6.3V6K

2

Compal Secret Data

VCCCORE_1
VCCCORE_2
VCCCORE_3
VCCCORE_4
VCCCORE_5
VCCCORE_6
VCCCORE_7
VCCCORE_8

VCCCORE_9
VCCCORE_10
VCCCORE_11
VCCCORE_12
VCCCORE_13
VCCCORE_14
VCCCORE_15
VCCCORE_16
VCCCORE_17
VCCCORE_18
VCCCORE_19
VCCCORE_20
VCCCORE_21
VCCCORE_22

VCCASW_10

VCCASW_11

VCCASW_12

VCCASW_13

VCCASW_14

VCCASW_15

VCCASW_16

VCCASW_17

VCCASW_18

VCCASW_19

VCCASW_20

VCCASW_21

VCCASW_22

VCCASW_23

VCCDIFFCLKN_1
VCCDIFFCLKN_2
VCCDIFFCLKN_3

VCCCLKDMI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2

+1.05VS_VPCH

+1.05VS_VPCH

1 2

1

R368

@

C307

1U_0402_6.3V6K

0_0603_5%

2

+1.05VS_VCCDIFFCLKN

1

C302

1U_0402_6.3V6K

Near AE15

2

2

1

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_SUS

VCC3_3

VCCADAC

VCCADPLLA

VCCADPLLB

VCCCORE

VCCDMI

VCCVRM 1.5

VCCSSC 1.05

VCCDIFFCLKN 1.05

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_POWER-1

PCA70 LA-7521P M/B

Voltage

1.05

5

5

3.3

3.3

1.05

1.05

1.05

1.05

1.05VCCIO

1.05VCCASW

3.3VCCSPI

3.3VCCDSW

1.8VCCDFTERM

3.3VCCRTC

3.3VCCSUS3_3

3.3 / 1.5VCCSusHDA

1.05VCCCLKDMI

1

S0 Iccmax
Current (A)

1mA

1mA

1mA

409mA

68mA

100mA

100mA

1600mA

57mA

4070mA

1610mA

20mA
3mA

200mA

6 uA

97mA

10mA

159mA

20mA

105mA

55mA

of

19 64Tuesday, April 12, 2011

0.1

5

4

3

2

1

POWER

VCCSUS3_3_11

VCCSUS3_3_10

V_PROC_IO_NCTF

DCPRTC_NCTF

VCCVRM_1
VCCVRM_4
VCCVRM_3
VCCVRM_2

VCCPNAND_01
VCCPNAND_02

VCC3_3_5
VCC3_3_6

USB

VCC3_3_2
VCC3_3_3
VCC3_3_4

VCC3_3_8
VCC3_3_1

VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
VCCSUS3_3_5
VCCSUS3_3_6
VCCSUS3_3_7
VCCSUS3_3_8

VCCSUS3_3_9

VCCSUS3_3_1

VCCDSW3_3

V_PROC_IO

DCPSUS_3
DCPSUS_1

VCCRTC
DCPRTC

DCPSUS_2

DCPSUSBYP

DCPSST

AJ1
R2
R54
R56

T55
T57

AL38
AN38

BC17
BD17
BD20

A12
AF57

BT35
AV30

AV32
AY31
AY33
BJ36
BK36
BM36

AT40
AU38

U31
AV40
D55

B56
A39

AA32
BU42
BR54

BT56
AT41

AV41
BA46

+VCCDSW

+V_CPU_IO
+VCCSUS

+RTCVCC
+VCCRTCEXT
+VCCSUS
+VCCDCPSUS
+VCCSST

Near BA46

0.1U_0402_10V7K

+VCCAFDI_VRM

Near T55

1 2

C285

0.1U_0402_10V7K

1

C296

0.1U_0402_10V7K

2

1

C278

0.1U_0402_10V7K

2

Near AV30 Near U31N ear BT35

C272 0.1U_0402_10V7K

C280 0.1U_0402_10V7K

+RTCVCC

C300

0.1U_0402_10V7K

C309

C262

0.1U_0402_10V7K

1

2

Near BD17Near BC17

1

C298

0.1U_0402_10V7K

2

Near A12

1

C288

2.2U_0603_10V6K

2

1 2

1 2

Near A39
Near BR54

1 2

1

1

2

2

R335

0_0603_5%

1 2

C286

0.1U_0402_10V7K

1

1

2

2

+3VS

1

2

Near AV40

C274

0.1U_0402_10V7K

@

0.1U_0402_10V7K

C279

0.1U_0402_10V7K

C290

+1.8VS

+1.8VS

+3VS

Near Al38

R350 0_0603_5%@

Connect VCCVRM to

--> 1.8V for DT

--> 1.5V for Mobile

+3VALW

1

1

C291

C289

1U_0402_6.3V6K

0.1U_0402_10V7K

2

2

1 2

C314

C313

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

2

2

C315

1U_0402_6.3V6K

C312

4.7U_0603_6.3V6K

1

2

+3VALW

1 2

@

1

0_0603_5%

2

@

1 2

0_0603_5%

+1.05VS_VPCH

R371

+1.05VS_VPCH

R373

B520 not connect?

BT25
AV28
AU20

AV20
AU22

AN52

BF1

U4J

V5REF
V5REF_SUS
VCCSUSHDA
VCC3_3_9

VCC3_3_10
VCC3_3_7

VCCSPI

+3VS_VCCSPI

1

2

+PCH_V5REF_RUN
+PCH_V5REF_SUS
+VCCSUSHDA

Near AU20

1

C287
1U_0402_6.3V6K

2

R374

@

0_0603_5%

D6
RB751V40_SC76-2

1 2

+3VALW

D5
RB751V40_SC76-2

1 2

1 2

0.1U_0402_16V4Z

1

C318

+3VALW

2

+PCH_V5REF_RUN

+PCH_V5REF_SUS

+3VS

R3430_0805_5%

12
12

R3440_0805_5% @

C264

1U_0402_6.3V6K

+3VS

D D

Intel suggest
100ohm+1uF

Near BF1

C C

+3VALW

PLACE REF5V CIRCUITRY NEAR PCH

C277
1U_0402_6.3V6K

PLACE REF5V CIRCUITRY NEAR PCH

C271
1U_0402_6.3V6K

R351
100_0402_5%

12

R1069
100_0402_5%

12

+5VS +3VS

12

+5VALW

12

Near BT25

B B

12

1

+

@

2

Layout Note:
Close to AT1< 100 mil

1

C249
1U_0402_6.3V6K

2

+VCCA_DAC
+1.05VS_VCCADPLLA
+1.05VS_VCCADPLLB

AT1
AB1
AC2

VCCADAC
VCCADPLLA
VCCADPLLB

+3VS

R332

1_0603_5%

C248

220U_6.3V_M

BD82CPDS-QMZP-B0_FCBGA942

+1.05VS_VPCH

A A

Layout Note:
Close to AB 1 , AC2< 100 mil
Filter no need if int. GFx diisabled

L6,L7 (10uH inductor, 120mA)

L4

10UH_LB2012T100MR_20%

1 2

L5

1 2

10UH_LB2012T100MR_20%

220U_B2_2.5VM_R15

C292

5

1

+

C294
1U_0402_6.3V6K

2

+1.05VS_VCCADPLLA

+1.05VS_VCCADPLLB

1

2

1

+

C293

2

220U_B2_2.5VM_R15

R360

@

0_0603_5%

1 2

1

C295
1U_0402_6.3V6K

2

0.1U_0402_10V7K

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/10/1 2011/11/01

+RTCVCC

1

C317

2

Near BU42

Compal Secret Data

+RTCVCC

1

1U_0402_6.3V6K

2

Deciphered Date

C316

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PCH_POWER-2

PCA70 LA-7521P M/B

1

20 64Tuesday, April 12, 2011

0.1

of