Compal LA-7451P PLW00, XPS 14z Schematic

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-7451P

TBD TBD

PLW00

Dell/Compal Confidential

Schematic Document

2 2

Breitling (Huron River)

Sandy Bridge(BGA) + Cougar Point(standard)

DISCRETE VGA N12P-GV-S-A1 (optimus)

3 3

4 4

2011-07-12

Rev: 1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-7451P

1 49Thursday, July 28, 2011

1.0

Compal Confidential

Project Code : PLW00

FFS

ile Name : LA-7451P

1 1

Intel

P.28

Fan Control

P.30

CPU XDP Conn.

P.6

Sandy Bridge

Memory Bus (DDRIII)

Dual Channel

1.5V DDRIII 1066/1333 MHz

mini DP Conn.

DisplayPort

GPU N12P-GV-S

P.30~41

PEG x16 (DIS)

Processor

17W /35W CULV/SV

BGA 1023

P.5~10

DI x8

(UMA)

100MHz

2.7GT/s

LVDS

2 2

Conn.

P.21

HDMI Conn.

HDMI

P.39

LVDS

DMI x4F

100MHz 5GB/s

SATA3.0

SATA1.0

204pin DDRIII SO-DIMM x2

BANK 0, 1, 2, 3

Port 0

SATA HDD Conn.

Port 2

SATA ODD Conn.

P.11,12

P.28

Intel

PCI-E x1

Port 6

USB 3.0/2.0 Host Ctrl.

P.27

USB 3.0/2.0

3 3

Combo Conns x2

P.27

Card Reader

RTS5209

7 in 1 Socket

Port 4

Mini Card-1 WLAN (Half)

P.23

Port 3 Port 1

USB[x] port4

LAN(GbE)

AR8151-BL1A

P.22

RJ45

P.22

Cougar Point

PCH

BGA 989 Balls

P13~20

USB2.0

HD Audio

Port 3

Port 4

Port 2

Digital Camera

Mini Card-1 (WLAN)

( Half )

P.21

P.32

W/ BT 2.1 /3.0 combo

USB 2.0

P.26

SPI

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

4 4

Power Circuit DC/DC

P.13

P.29

P.33

P.49~59

SPI ROM

P.13 P.31

Touch Pad Int.KBD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LPC Bus

Port 5

ENE KB930

BIOS ROM

P.35

2010/12/20 2011/12/20

P.29 P.31

Compal Secret Data

Deciphered Date

Mini Card-2 (WWAN)

( Full )

Audio Codec ALC259-GR

SIM Card

P.24

Audio Jack x2

( HeadPhone X1, MIC )

Digital MIC

P.32

Int. Speaker

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-7451P

2 49Thursday, July 28, 2011

1.0

Compal Confidential

Project Code : PLW00 File Name : LA-7451P

1 1

LA-7451P M/B

Camera

30 pin

Wire

LCD Panel

INVERTER

7 pin

FFC

2 2

WLAN

12 pin

HDD

FFC

4 pin

Touch Pad

FFC

4 pin

Wire

3 pin

LS-7451P

FFC

4pin

LS-7453P

POWER BUTTON/BALS/B

Led x 1

3 3

LID

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

1.0

3 49Thursday, July 28, 2011

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SML0CLK PCH PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

MEM_SMBCLK MEM_SMBDATA

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5% 18K +/- 5% 3

3K +/- 5%

56K +/- 5%

100K +/- 5% 200K +/- 5%

SOURCE

KB930

PCH

AD_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

BATT SODIMM

V typ

AD_BID

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

SODIMM

max

0 V 0.155 V

FFS

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

VGA Thermal Sensor

EC AD3

0x00-0x0C 0x0D-0x1C 0

x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF

XDP

Charger

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

Link

PCB Revision

0.1

0.2

0.3

0.4

0.5

PCH

USB PORT#

DESTINATION

None

JUSB1 (2.0 Ext UP Side)

one

CAMERA

JMINI1 (WLAN)

JMINI2 (WWAN)

None

CLKOUT

1 1

PCI0

PCI1

PCI2

PCI3

PCI4

CLK

DESTINATION

PCH_LOOPBACK

EC LPC

None

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7 None

CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

10/100/1G LAN

MINI CARD-2 WWAN

MINI CARD-1 WLAN

CARD READER

None

USB 3.0

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0None

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

DESTINATION

HDD

ODD

None

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Secret Data

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

None

DESTINATION

10/100/1G LAN

None

MINI CARD-1 WLAN

CARD READER

None

USB 3.0

None

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-7451P

4 49Thursday, July 28, 2011

1.0

UCPU1A

D D

C C

B B

DMI_CRX_PTX_N0<15> DMI_CRX_PTX_N1<15> DMI_CRX_PTX_N2<15> DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15> DMI_CRX_PTX_P1<15> DMI_CRX_PTX_P2<15> DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15> DMI_CTX_PRX_N1<15> DMI_CTX_PRX_N2<15> DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15> DMI_CTX_PRX_P1<15> DMI_CTX_PRX_P2<15> DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15> FDI_CTX_PRX_N1<15> FDI_CTX_PRX_N2<15> FDI_CTX_PRX_N3<15> FDI_CTX_PRX_N4<15> FDI_CTX_PRX_N5<15> FDI_CTX_PRX_N6<15> FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15> FDI_CTX_PRX_P1<15> FDI_CTX_PRX_P2<15> FDI_CTX_PRX_P3<15> FDI_CTX_PRX_P4<15> FDI_CTX_PRX_P5<15> FDI_CTX_PRX_P6<15> FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15> FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15> FDI_LSYNC1<15>

+VCCP

1 2

RC36 24.9_0402_1%RC36 24.9_0402_1%

RC129

10K_0402_5%

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

+EDP_COM

DMI_RX#[0]

DMI_RX#[1]

DMI_RX#[2]

P10

DMI_RX#[3]

DMI_RX[0]

DMI_RX[1]

DMI_RX[2]

P11

DMI_RX[3]

DMI_TX#[0]

DMI_TX#[1]

DMI_TX#[2]

DMI_TX#[3]

DMI_TX[0]

DMI_TX[1]

DMI_TX[2]

DMI_TX[3]

FDI0_TX#[0]

W11

FDI0_TX#[1]

FDI0_TX#[2]

AA6

FDI0_TX#[3]

FDI1_TX#[0]

FDI1_TX#[1]

FDI1_TX#[2]

AC9

FDI1_TX#[3]

FDI0_TX[0]

W10

FDI0_TX[1]

FDI0_TX[2]

AA7

FDI0_TX[3]

FDI1_TX[0]

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

SANDY-BRIDGE_BGA1023~D

i5@

DMI Intel(R) FDI DP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS -- GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

+VCCP

RC2

24.9_0402_1%

G3 G1 G4

PEG_GTX_C_HRX_N15

H22

PEG_GTX_C_HRX_N14

J21

PEG_GTX_C_HRX_N13

B22

PEG_GTX_C_HRX_N12

D21

PEG_GTX_C_HRX_N11

A19

PEG_GTX_C_HRX_N10

D17

PEG_GTX_C_HRX_N9

B14

PEG_GTX_C_HRX_N8

D13

PEG_GTX_C_HRX_N7

A11

PEG_GTX_C_HRX_N6

B10

PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P15

K22

PEG_GTX_C_HRX_P14

K19

PEG_GTX_C_HRX_P13

C21

PEG_GTX_C_HRX_P12

D19

PEG_GTX_C_HRX_P11

C19

PEG_GTX_C_HRX_P10

D16

PEG_GTX_C_HRX_P9

C13

PEG_GTX_C_HRX_P8

D12

PEG_GTX_C_HRX_P7

C11

PEG_GTX_C_HRX_P6

PEG_GTX_C_HRX_P5

PEG_GTX_C_HRX_P4

PEG_GTX_C_HRX_P3

PEG_GTX_C_HRX_P2

PEG_GTX_C_HRX_P1

PEG_GTX_C_HRX_P0

PEG_HTX_GRX_N15

G22

PEG_HTX_GRX_N14

C23

PEG_HTX_GRX_N13

D23

PEG_HTX_GRX_N12

F21

PEG_HTX_GRX_N11

H19

PEG_HTX_GRX_N10

C17

PEG_HTX_GRX_N9

K15

PEG_HTX_GRX_N8

F17

PEG_HTX_GRX_N7

F14

PEG_HTX_GRX_N6

A15

PEG_HTX_GRX_N5

J14

PEG_HTX_GRX_N4

H13

PEG_HTX_GRX_N3

M10

PEG_HTX_GRX_N2

F10

PEG_HTX_GRX_N1

PEG_HTX_GRX_N0

PEG_HTX_GRX_P15

F22

PEG_HTX_GRX_P14

A23

PEG_HTX_GRX_P13

D24

PEG_HTX_GRX_P12

E21

PEG_HTX_GRX_P11

G19

PEG_HTX_GRX_P10

B18

PEG_HTX_GRX_P9

K17

PEG_HTX_GRX_P8

G17

PEG_HTX_GRX_P7

E14

PEG_HTX_GRX_P6

C15

PEG_HTX_GRX_P5

K13

PEG_HTX_GRX_P4

G13

PEG_HTX_GRX_P3

K10

PEG_HTX_GRX_P2

G10

PEG_HTX_GRX_P1

PEG_HTX_GRX_P0

Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)

PEG_COMP

CC185 0.1U_0402_10V7K~DCC185 0.1U_0402_10V7K~D

1 2

CC186 0.1U_0402_10V7K~DCC186 0.1U_0402_10V7K~D

1 2

CC187 0.1U_0402_10V7K~DCC187 0.1U_0402_10V7K~D

1 2

CC188 0.1U_0402_10V7K~DCC188 0.1U_0402_10V7K~D

1 2

CC189 0.1U_0402_10V7K~DCC189 0.1U_0402_10V7K~D

1 2

CC190 0.1U_0402_10V7K~DCC190 0.1U_0402_10V7K~D

1 2

CC191 0.1U_0402_10V7K~DCC191 0.1U_0402_10V7K~D

1 2

CC192 0.1U_0402_10V7K~DCC192 0.1U_0402_10V7K~D

1 2

CC193 0.1U_0402_10V7K~DCC193 0.1U_0402_10V7K~D

1 2

CC194 0.1U_0402_10V7K~DCC194 0.1U_0402_10V7K~D

1 2

CC195 0.1U_0402_10V7K~DCC195 0.1U_0402_10V7K~D

1 2

CC196 0.1U_0402_10V7K~DCC196 0.1U_0402_10V7K~D

1 2

CC197 0.1U_0402_10V7K~DCC197 0.1U_0402_10V7K~D

1 2

CC198 0.1U_0402_10V7K~DCC198 0.1U_0402_10V7K~D

1 2

CC199 0.1U_0402_10V7K~DCC199 0.1U_0402_10V7K~D

1 2

CC200 0.1U_0402_10V7K~DCC200 0.1U_0402_10V7K~D

1 2

CC201 0.1U_0402_10V7K~DCC201 0.1U_0402_10V7K~D

1 2

CC202 0.1U_0402_10V7K~DCC202 0.1U_0402_10V7K~D

1 2

CC203 0.1U_0402_10V7K~DCC203 0.1U_0402_10V7K~D

1 2

CC204 0.1U_0402_10V7K~DCC204 0.1U_0402_10V7K~D

1 2

CC205 0.1U_0402_10V7K~DCC205 0.1U_0402_10V7K~D

1 2

CC206 0.1U_0402_10V7K~DCC206 0.1U_0402_10V7K~D

1 2

CC207 0.1U_0402_10V7K~DCC207 0.1U_0402_10V7K~D

1 2

CC208 0.1U_0402_10V7K~DCC208 0.1U_0402_10V7K~D

1 2

CC209 0.1U_0402_10V7K~DCC209 0.1U_0402_10V7K~D

1 2

CC210 0.1U_0402_10V7K~DCC210 0.1U_0402_10V7K~D

1 2

CC211 0.1U_0402_10V7K~DCC211 0.1U_0402_10V7K~D

1 2

CC212 0.1U_0402_10V7K~DCC212 0.1U_0402_10V7K~D

1 2

CC213 0.1U_0402_10V7K~DCC213 0.1U_0402_10V7K~D

1 2

CC214 0.1U_0402_10V7K~DCC214 0.1U_0402_10V7K~D

1 2

CC215 0.1U_0402_10V7K~DCC215 0.1U_0402_10V7K~D

1 2

CC216 0.1U_0402_10V7K~DCC216 0.1U_0402_10V7K~D

1 2

PEG_ICOMPI and RCOMPO signals should be short ed and routed with - max leng th = 500 mils - typical impeda nce = 43 mohms PEG_ICOMPO sign als should be r outed with - ma x length = 500 mils

- typical imped ance = 14.5 moh ms

PEG_GTX_C_HRX_N15 <34> PEG_GTX_C_HRX_N14 <34> PEG_GTX_C_HRX_N13 <34> PEG_GTX_C_HRX_N12 <34> PEG_GTX_C_HRX_N11 <34> PEG_GTX_C_HRX_N10 <34> PEG_GTX_C_HRX_N9 <34> PEG_GTX_C_HRX_N8 <34> PEG_GTX_C_HRX_N7 <34> PEG_GTX_C_HRX_N6 <34> PEG_GTX_C_HRX_N5 <34> PEG_GTX_C_HRX_N4 <34> PEG_GTX_C_HRX_N3 <34> PEG_GTX_C_HRX_N2 <34> PEG_GTX_C_HRX_N1 <34> PEG_GTX_C_HRX_N0 <34>

PEG_GTX_C_HRX_P15 <34> PEG_GTX_C_HRX_P14 <34> PEG_GTX_C_HRX_P13 <34> PEG_GTX_C_HRX_P12 <34> PEG_GTX_C_HRX_P11 <34> PEG_GTX_C_HRX_P10 <34> PEG_GTX_C_HRX_P9 <34> PEG_GTX_C_HRX_P8 <34> PEG_GTX_C_HRX_P7 <34> PEG_GTX_C_HRX_P6 <34> PEG_GTX_C_HRX_P5 <34> PEG_GTX_C_HRX_P4 <34> PEG_GTX_C_HRX_P3 <34> PEG_GTX_C_HRX_P2 <34> PEG_GTX_C_HRX_P1 <34> PEG_GTX_C_HRX_P0 <34>

PEG_HTX_C_GRX_N15 <34> PEG_HTX_C_GRX_N14 <34> PEG_HTX_C_GRX_N13 <34> PEG_HTX_C_GRX_N12 <34> PEG_HTX_C_GRX_N11 <34> PEG_HTX_C_GRX_N10 <34> PEG_HTX_C_GRX_N9 <34> PEG_HTX_C_GRX_N8 <34> PEG_HTX_C_GRX_N7 <34> PEG_HTX_C_GRX_N6 <34> PEG_HTX_C_GRX_N5 <34> PEG_HTX_C_GRX_N4 <34> PEG_HTX_C_GRX_N3 <34> PEG_HTX_C_GRX_N2 <34> PEG_HTX_C_GRX_N1 <34> PEG_HTX_C_GRX_N0 <34>

PEG_HTX_C_GRX_P15 <34> PEG_HTX_C_GRX_P14 <34> PEG_HTX_C_GRX_P13 <34> PEG_HTX_C_GRX_P12 <34> PEG_HTX_C_GRX_P11 <34> PEG_HTX_C_GRX_P10 <34> PEG_HTX_C_GRX_P9 <34> PEG_HTX_C_GRX_P8 <34> PEG_HTX_C_GRX_P7 <34> PEG_HTX_C_GRX_P6 <34> PEG_HTX_C_GRX_P5 <34> PEG_HTX_C_GRX_P4 <34> PEG_HTX_C_GRX_P3 <34> PEG_HTX_C_GRX_P2 <34> PEG_HTX_C_GRX_P1 <34> PEG_HTX_C_GRX_P0 <34>

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

VSS[208]

E25

VSS[209]

E29

VSS[210]

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G48

VSS[221]

G51

VSS[222]

VSS[223]

G61

VSS[224]

H10

VSS[225]

H14

VSS[226]

H17

VSS[227]

H21

VSS[228]

VSS[229]

H53

VSS[230]

H58

VSS[231]

VSS[232]

J49

VSS[233]

J55

VSS[234]

K11

VSS[235]

K21

VSS[236]

K51

VSS[237]

VSS[238]

L16

VSS[239]

L20

VSS[240]

L22

VSS[241]

L26

VSS[242]

L30

VSS[243]

L34

VSS[244]

L38

VSS[245]

L43

VSS[246]

L48

VSS[247]

L61

VSS[248]

M11

VSS[249]

M15

VSS[250]

SANDY-BRIDGE_BGA1023~D

i5@

VSS

NCTF

VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-7451P

5 49Thursday, July 28, 2011

1.0

XDP_PREQ# XDP_PRDY#

XDP_BPM#0

RC35 0_0402_5%

XDP_BPM#1

D D

CFG0<8>

PCH_JTAG_TDO<13>

PCH_JTAG_TDI<13>

PCH_JTAG_TMS<13>

PCH_JTAG_TCK<13>

RC43

62_0402_5%

H_CPUPWRGD

+VCCP

PBTN_OUT#<15,26>

VGATE<15,26,48>

CLK_CPU_ITP<14>

CLK_CPU_ITP#<14>

The resistor for HOOK2 shoul d be placed such tha t the stub is very sm all on CFG0 net

C C

PROC_DETECT (Processor Detect): pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present

B B

H_PROCHOT#<26>

A A

1 2

1 2 1 2 1 2 1 2

0_0402_5% @

RC114 0_0402_5%@RC114 0_0402_5%@

XDP_BPM#2

RC117 0_0402_5%@RC117 0_0402_5%@

XDP_BPM#3

RC115 0_0402_5%@RC115 0_0402_5%@

1K_0402_5%~D

RC22

RC22 RC230_0402_5%~D @ RC230_0402_5%~D @ RC71K_0402_5%~D RC71K_0402_5%~D RC260_0402_5%~D @ RC260_0402_5%~D @

1K_0402_5%

RC25

1 2

RC121 10K_0402_5%

H_PECI<17,26>

H_THERMTRIP#<17>

H_PM_SYNC<15>

H_CPUPWRGD<17>

12 12

H_CPUPWRGD_XDP CFD_PWRBTN#_X DP CFG0_R SYS_PWROK_XDP CLK_CPU_ITP CLK_CPU_ITP#

XDP_RST#_RPLT_RST#

XDP_DBRESET#

XDP_TDO

RC280_0402_5% @ RC280_0402_5% @

XDP_TRST# XDP_TDI

RC310_0402_5% @ RC310_0402_5% @

XDP_TMS

RC290_0402_5% @ RC290_0402_5% @

XDP_TCK1

RC30

XDP_TCK

H_SNB_IVB#<17>

T1PAD~D @T1PAD~D @

RC41

1 2

56_0402_5%

RC49

1 2

0_0402_5%

RC53

1 2

0_0402_5%

RC57

1 2

130_0402_1%

+VCCP

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#

@RC49

H_PM_SYNC_R

@RC53

H_CPUPWRGD_R

VDDPWRGOOD_RVDDPWRGOOD

BUF_CPU_RST#

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

ACES_87152-26051

@ JXDP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

F49

C57

C49

A48

C45

D45

C48

B46

BE45

D44

JXDP

G1 G2

27 28

UCPU1B

PROC_SELECT#

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWR OK

RESET#

+VCCP

0.1U_0402_16V4Z~D

Place near JXDP1

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

CC67

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISC

CC66

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TDI

SYS_PWROK<15>

PCH_PWROK<15,26>

PM_DRAM_PWR GD<15>

+3V_PCH

J3 H2

AG3 AG1

N59 N58

AT30

BF44 BE43 BG43

CLK_CPU_DMI_R

CLK_CPU_DMI#_R

CLK_CPU_DPLL_R CLK_CPU_DPLL#_R

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

RC37 0_0402_5%

RC37 0_0402_5% RC38 0_0402_5%

RC38 0_0402_5%

RC39 1K_0402_5%RC39 1K_0402_5% RC40 1K_0402_5%RC40 1K_0402_5%

DDR3 Compensation Signals

XDP_PRDY#

N53

XDP_PREQ#

N55

XDP_TCK

L56

XDP_TMS

L55

XDP_TRST#

J58

XDP_TDI_R

M60

XDP_TDO_R

L59

XDP_DBRESET#_R

K58

XDP_BPM#0_R

G58

XDP_BPM#1_R

E55

XDP_BPM#2_R

E59

XDP_BPM#3_R

G55

XDP_BPM#4_R

G59

XDP_BPM#5_R

H60

XDP_BPM#6_R

J59

XDP_BPM#7_R

J61

RC50 0_0402_5%

1 2

RC51 0_0402_5%

1 2

@ @

RC56

1 2

RC59 0_0402_5%

1 2

RC61 0_0402_5%

1 2

RC62 0_0402_5%

1 2

RC63 0_0402_5%

1 2

RC64 0_0402_5%

1 2

RC65 0_0402_5%

1 2

RC66 0_0402_5%

1 2

RC67 0_0402_5%

1 2

@ @

RC127

RC128

RC4

1 2

1 2 1 2

@ @

@ 1 2 1 2

H_DRAMRST# <7>

1 2 1 2 1 2

@RC56

0_0402_5%

0_0402_5%~D

@RC128

0_0402_5%~D

1 2

RC11 0_0402_5%

200_0402_1%

RUN_ON_CPU1.5VS3#<10,28>

PLT_RST#<16,22,26,27,30,33>

RC55140_0402_1% RC55140_0402_1% RC5825.5_0402_1% RC5825.5_0402_1% RC60200_0402_1% RC60200_0402_1%

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 CFG12 CFG13 CFG14 CFG15

+3VS

10K_0402_5%

D_PWG

CLK_CPU_DMI <14> CLK_CPU_DMI# <14>

+VCCP

XDP_DBRESET# <15>

CFG12 <8> CFG13 <8> CFG14 <8> CFG15 <8>

RC6

UC1

VCC

A GND3Y

MC74VHC1G09DFT2G_SC70-5

RUN_ON_CPU1.5VS3#

1 2

+3VALW

0.1U_0402_16V4Z~D

CC65

RC19

RC19 39_0402_1%

39_0402_1%

1 2

+3VS

UC2

VCC A GND3Y

SN74LVC1G07DCKR_SC70-5~D

BUFO_CPU_RST# BUF_CPU_RST#

PU/PD for JTAG signals

XDP_TMS

XDP_TDI_R

XDP_PREQ#

XDP_TDO

XDP_TCK

XDP_TRST#

XDP_DBRESET#

H_CPUPWRGD_R

XDP_DBRESET#

+1.5V_CPU_VDDQ

RC8

RC8 200_0402_1%

200_0402_1%

VDDPWRGOOD

RC8 CRB 1.1K

CHECK LIST 0.7 --> 4.75K INTEL recommand 1.1K PDG 0.71 rev -- >200

QC1

QC1 2N7002_SOT23

2N7002_SOT23

0.1U_0402_16V4Z~D

+VCCP

CC68

RC32

RC32 75_0402_5%

75_0402_5%

RC33

1 2

43_0402_1%

CC70

1 2

0.047U_0402_16V4Z~D

RC34

RC34 0_0402_5%

0_0402_5%

RC4551_0402_5% RC4551_0402_5%

RC4651_0402_5% RC4651_0402_5%

RC4751_0402_5% @ RC4751_0402_5% @

RC4851_0402_5% RC4851_0402_5%

RC5251_0402_5% RC5251_0402_5%

RC5451_0402_5% RC5451_0402_5%

+3VS

RC421K_0402_5% RC421K_0402_5%

RC4410K_0402_5% RC4410K_0402_5%

+VCCP

SANDY-BRIDGE_BGA1023~D

i5@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

LA-7451P

6 49Thursday, July 28, 2011

1.0

UCPU1C

DDR_A_D[0..63]<11>

D D

C C

DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>

B B

A A

DDR_A_CAS#<11> DDR_A_RAS#<11> DDR_A_WE#<11>

H_DRAMRST#<6>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

H_DRAMRST#

4.99K_0402_1%~D

UCPU1C

AG6

AJ6

AP11

AL6

AJ10

AJ8 AL8 AL7

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

SANDY-BRIDGE_BGA1023~D

i5@

RC77

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

BSS138_SOT23

DDR SYSTEM MEMORY A

1 2

RC74 0_0402_5%~D

QC2

DDR3_DRAMRST#_R

DRAMRST_CNTRL

CC69

0.047U_0402_16V4Z~D

SA_CLK#[0]

SA_CLK#[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

M_CLK_DDR0

AU36

SA_CLK[0]

SA_CKE[0]

SA_CLK[1]

SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

+1.5V

M_CLK_DDR#0

AV36

DDR_CKE0_DIMMA

AY26

M_CLK_DDR1

AT40

M_CLK_DDR#1

AU40

DDR_CKE1_DIMMA

BB26

DDR_CS0_DIMMA#

BB40

DDR_CS1_DIMMA#

BC41

M_ODT0

AY40

M_ODT1

BA41

DDR_A_DQS#0

AL11

DDR_A_DQS#1

AR8

DDR_A_DQS#2

AV11

DDR_A_DQS#3

AT17

DDR_A_DQS#4

AV45

DDR_A_DQS#5

AY51

DDR_A_DQS#6

AT55

DDR_A_DQS#7

AK55

DDR_A_DQS0

AJ11

DDR_A_DQS1

AR10

DDR_A_DQS2

AY11

DDR_A_DQS3

AU17

DDR_A_DQS4

AW45

DDR_A_DQS5

AV51

DDR_A_DQS6

AT56

DDR_A_DQS7

AK54

DDR_A_MA0

BG35

DDR_A_MA1

BB34

DDR_A_MA2

BE35

DDR_A_MA3

BD35

DDR_A_MA4

AT34

DDR_A_MA5

AU34

DDR_A_MA6

BB32

DDR_A_MA7

AT32

DDR_A_MA8

AY32

DDR_A_MA9

AV32

DDR_A_MA10

BE37

DDR_A_MA11

BA30

DDR_A_MA12

BC30

DDR_A_MA13

AW41

DDR_A_MA14

AY28

DDR_A_MA15

AU26

RC75

RC75 1K_0402_5%~D

1K_0402_5%~D

1 2

RC76 1K_0402_5%RC76 1K_0402_5%

DG 1.0 Figure 61 RC76=1K

1 2

RC72 0_0402_5%~D

1 2

RC73 0_0402_5%~D

M_CLK_DDR0 <11> M_CLK_DDR#0 <11> DDR_CKE0_DIMMA <11>

M_CLK_DDR1 <11> M_CLK_DDR#1 <11> DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA# <11> DDR_CS1_DIMMA# <11>

M_ODT0 <11> M_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR3_DRAMRST# <11,12>

DRAMRST_CNTRL_PCH <14>

DRAMRST_CNTRL_EC <26>

DDR_B_D[0..63]<12>

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12> DDR_B_WE#<12>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/20 2011/12/20

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

Compal Secret Data

Deciphered Date

UCPU1D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

SANDY-BRIDGE_BGA1023~D

i5@

M_CLK_DDR2

BA34

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

Title

Size Document Number Rev

Date: Sheet

M_CLK_DDR#2

AY34

DDR_CKE2_DIMMB

AR22

M_CLK_DDR3

BA36

M_CLK_DDR#3

BB36

DDR_CKE3_DIMMB

BF27

DDR_CS2_DIMMB#

BE41

DDR_CS3_DIMMB#

BE47

M_ODT2

AT43

M_ODT3

BG47

DDR_B_DQS#0

AL3

DDR_B_DQS#1

AV3

DDR_B_DQS#2

BG11

DDR_B_DQS#3

BD17

DDR_B_DQS#4

BG51

DDR_B_DQS#5

BA59

DDR_B_DQS#6

AT60

DDR_B_DQS#7

AK59

DDR_B_DQS0

AM2

DDR_B_DQS1

AV1

DDR_B_DQS2

BE11

DDR_B_DQS3

BD18

DDR_B_DQS4

BE51

DDR_B_DQS5

BA61

DDR_B_DQS6

AR59

DDR_B_DQS7

AK61

DDR_B_MA0

BF32

DDR_B_MA1

BE33

DDR_B_MA2

BD33

DDR_B_MA3

AU30

DDR_B_MA4

BD30

DDR_B_MA5

AV30

DDR_B_MA6

BG30

DDR_B_MA7

BD29

DDR_B_MA8

BE30

DDR_B_MA9

BE28

DDR_B_MA10

BD43

DDR_B_MA11

AT28

DDR_B_MA12

AV28

DDR_B_MA13

BD46

DDR_B_MA14

AT26

DDR_B_MA15

AU22

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

LA-7451P

M_CLK_DDR2 <12> M_CLK_DDR#2 <12> DDR_CKE2_DIMMB <12>

M_CLK_DDR3 <12> M_CLK_DDR#3 <12> DDR_CKE3_DIMMB <12>

DDR_CS2_DIMMB# <12> DDR_CS3_DIMMB# <12>

M_ODT2 <12> M_ODT3 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

7 49Thursday, July 28, 2011

1.0

CFG Straps for Processor

CFG2

RC78

CFG6

CFG5

RC87

@RC87

RC78 1K_0402_1%~D

1K_0402_1%~D

RC81

RC81 1K_0402_1%~D@

1K_0402_1%~D@

@RC86

RC86 1K_0402_1%~D

1K_0402_1%~D

UCPU1E

D D

+VCC_CORE

RC80

@RC80

50_0402_1%

+VCC_GFXCORE_AXG

C C

RC84

1K_0402_1%

INTEL 12/28 rec ommand to add 1k pull down

B B

RC79

@RC79

50_0402_1%

RC85

RC85 1K_0402_1%

1K_0402_1%

CFG0<6>

CFG12<6> CFG13<6> CFG14<6> CFG15<6>

1 2

RC91 50_0402_1%@RC91 50_0402_1%@

1 2

RC90 50_0402_1%

+V_DDR_REFA_R +V_DDR_REFB_R

CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

CFG12 CFG13 CFG14 CFG15

VCC_VAL_SENSE VSS_VAL_SENSE

VCC_AXG_VAL_SENSE

VSS_AXG_VAL_SENSE

T19PAD~D @T19PAD~D @

T25PAD~D @T25PAD~D @ T26PAD~D @T26PAD~D @

T28PAD~D @T28PAD~D @RC84

T33PAD~D @T33PAD~D @

T35PAD~D @T35PAD~D @

T42PAD~D @T42PAD~D @ T36 PAD~D@T36 PAD~D@ T43PAD~D @T43PAD~D @

T46PAD~D @T46PAD~D @

UCPU1E

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

SANDY-BRIDGE_BGA1023~D

i5@

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1 DC_TEST_BD1

RSVD28 RSVD29

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Nor mal Operation; Lane #

CFG2

definition matc hes socket pin map definition

0:Lane Reversed

CFG4

Display Port Presence Strap

1 : Disabled; N o Physical Disp lay Port

CFG4

T21 PAD~D@T21 PAD~D@

T22 PAD~D@T22 PAD~D@ T23 PAD~D@T23 PAD~D@

T24 PAD~D@T24 PAD~D@ T29 PAD~D@T29 PAD~D@

T31 PAD~D@T31 PAD~D@

T48 PAD~D@T48 PAD~D@

attached to Emb edded Display P ort

0 : Enabled; An external Displ ay Port device is connected to th e Embedded Disp lay Port

1K_0402_1%~D

PCIE Port Bifurcation Straps

11: (Default) x 16 - Device 1 f unctions 1 and 2 disabled

CFG[6:5]

10: x8, x8 - De vice 1 function 1 enabled ; fu nction 2 disabled 01: Reserved - (Device 1 funct ion 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functi ons 1 and 2 ena bled

CFG7

RC89

@RC89

1K_0402_1%~D

PEG DEFER TRAINING

1: (Default) PE G Train immedia tely

CFG7

following xxRES ETB de assertio n

0: PEG Wait for BIOS for train ing

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

LA-7451P

8 49Thursday, July 28, 2011

1.0

UCPU1F

53A

2.2U_0402_6.3V6M

C792

2.2U_0402_6.3V6M

C808

UCPU1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

2.2U_0402_6.3V6M

C793

2.2U_0402_6.3V6M

SANDY-BRIDGE_BGA1023~D

i5@

18A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

CORE SUPPLY

POWER

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

PEG AND DDRSENSE LINES SVID QUIET RAILS

VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

VCCP_PWRCTRL_R

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

2010/12/20 2011/12/20

+1.05VS_VCCPQ

C722 1U_0402_6.3V6KC722 1U_0402_6.3V6K

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

VCCSENSE_R VSSSENSE_R

VCCIO_SENSE_R VSSIO_SENSE

choose low or high

1 2

10U_0603_6.3V6M

C54

C53

1U_0402_6.3V6K

C68

C69

1U_0402_6.3V6K

C508

C503

1U_0402_6.3V6K

C529

C649

Cap quantity follow 43890_HR_CHKLST_Rev07

+VCCP

R862

1 2

0_0805_5%

10K_0402_5%

1 2

+VCCP

R891

1 2

0_0805_5%

R108 0_0402_5%

1 2

R109 0_0402_5%

1 2

@ @

R112 0_0402_5%

1 2

R870

R870 10_0402_1%

10_0402_1%

Compal Secret Data

Deciphered Date

R101

10U_0603_6.3V6M

C55

1U_0402_6.3V6K

C70

1U_0402_6.3V6K

C527

1U_0402_6.3V6K

C721

+VCCP

10U_0603_6.3V6M

C56

C57

1U_0402_6.3V6K

R102

R102 130_0402_5%

130_0402_5%

C72

C71

1U_0402_6.3V6K

C505

C507

1U_0402_6.3V6K

C646

C648

R814

R814 75_0402_5%

75_0402_5%

Voltage selection for VCCIO: For Huron River platforms, this pin must be pulled high on the motherboard.

VCCP_PWRCTRL

1 2

R104 43_0402_1%R104 43_0402_1%

1 2

R105 0_0402_5%

1 2

R106 0_0402_5%

@ @

VCCIO_SENSE <46>

VSSIO_SENSE <46>

+VCCP

10U_0603_6.3V6M

C58

1U_0402_6.3V6K

C73

1U_0402_6.3V6K

C509

1U_0402_6.3V6K

C655

R103

R103 75_0402_5%

75_0402_5%

10U_0603_6.3V6M

C60

C59

1U_0402_6.3V6K

C74

C75

1U_0402_6.3V6K

C136

C506

1U_0402_6.3V6K

C528

C647

330U_D2_2V_Y

C83

VR_SVID_ALRT# <48> VR_SVID_CLK <48> VR_SVID_DAT <48>

1 2

R107 100_0402_1%R107 100_0402_1%

R111

Place the PU

100_0402_1%

resistors close to VR

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Date: Sheet of

SV type CPU

D D

+VCC_CORE

C87

22U_0805_6.3V6M

C87

22U_0805_6.3V6M

C88

22U_0805_6.3V6M

C88

C86

22U_0805_6.3V6M

C86

22U_0805_6.3V6M

C C

C91

22U_0805_6.3V6M

C91

22U_0805_6.3V6M

C96

22U_0805_6.3V6M

C96

22U_0805_6.3V6M

C101

B B

+VCC_CORE

2.2U_0402_6.3V6M

C780

C779

+VCC_CORE

2.2U_0402_6.3V6M

C794

C795

A A

+VCC_CORE

2.2U_0402_6.3V6M

C809

2.2U_0402_6.3V6M

C810

C811

High-Frequency Decoupling

2.2U_0402_6.3V6M

C782

C781

2.2U_0402_6.3V6M

C797

C796

2.2U_0402_6.3V6M

C812

C813

22U_0805_6.3V6M

C92

22U_0805_6.3V6M

C92

22U_0805_6.3V6M

C97

22U_0805_6.3V6M

C97

22U_0805_6.3V6M

C102

2.2U_0402_6.3V6M

C783

2.2U_0402_6.3V6M

C798

C799

0.1U_0402_16V4Z~D

CC71

22U_0805_6.3V6M

C93

22U_0805_6.3V6M

C93

22U_0805_6.3V6M

C98

22U_0805_6.3V6M

C98

22U_0805_6.3V6M

C103

2.2U_0402_6.3V6M

C784

C785

2.2U_0402_6.3V6M

C800

C801

0.1U_0402_16V4Z~D

CC73

CC72

C90

22U_0805_6.3V6M

C90

22U_0805_6.3V6M

C672

22U_0805_6.3V6M

C672

C89

C94

C99

C104

330U_D2_2V_Y

C105

2.2U_0402_6.3V6M

C787

C786

2.2U_0402_6.3V6M

C802

0.1U_0402_16V4Z~D

CC74

22U_0805_6.3V6M

C95

22U_0805_6.3V6M

C95

22U_0805_6.3V6M

C100

22U_0805_6.3V6M

C100

22U_0805_6.3V6M

330U_D2_2V_Y

C106

2.2U_0402_6.3V6M

C788

C789

2.2U_0402_6.3V6M

C803

C804

CC75

C670

22U_0805_6.3V6M

C670

22U_0805_6.3V6M

C762

C761

22U_0805_6.3V6M

C761

22U_0805_6.3V6M

C764

C763

22U_0805_6.3V6M

C763

22U_0805_6.3V6M

330U_D2_2V_Y

2.2U_0402_6.3V6M

330U_D2_2V_Y

C107

C108

2.2U_0402_6.3V6M

C790

C791

C805

2.2U_0402_6.3V6M

C807

C806

+1.05V

+VCCP

10U_0603_6.3V6M

C62

C61

1U_0402_6.3V6K

C76

1U_0402_6.3V6K

C504

330U_D2_2V_Y

C84

+VCC_CORE

Place the PU resistors close to CPU

VCCSENSE <48> VSSSENSE <48>

Compal Electronics, Inc.

1.0

9 49Thursday, July 28, 2011

1.0

22U_0805_6.3V6M

C118

C113

22U_0805_6.3V6M

C116

C115

0.1U_0402_16V4Z~D

CC77

CC78

1U_0402_6.3V6K

C842

C843

R934 0_0402_5%

1 2

R935 0_0402_5%

1 2

10U_0603_6.3V6M

C143

C144

1U_0402_6.3V6K

C846

+1.5V+1.5V_CPU_VDDQ

Can connect to GND if motherboard only‧‧‧‧

supports external graphics and if GFX VR is not

tuffed in a common motherboard design,

VAXG can be left floating in a common‧‧‧‧ motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed

26A

AA46

+1.8VS_VCCPLL

C141

1U_0402_6.3V6K

C141

1U_0402_6.3V6K

10U_0603_6.3V6M

C765

1U_0402_6.3V6K

C850

AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61

U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

G45

BB3 BC1 BC4

N16 N20

N22 P17 P20

R16 R18 R21 U15 V16 V17 V18 V21 W20

1U_0402_6.3V6K

22U_0805_6.3V6M

C125

C121

22U_0805_6.3V6M

C123

C117

0.1U_0402_16V4Z~D

CC79

CC80

1U_0402_6.3V6K

C844

C845

@ @

C140

1U_0402_6.3V6K

C140

1U_0402_6.3V6K

C139

10U_0603_6.3V6M

C139

10U_0603_6.3V6M

+VCCSA

10U_0603_6.3V6M

C146

C145

1U_0402_6.3V6K

C847

C849

C848

UCPU1G

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

F45

VAXG_SENSE VSSAXG_SENSE

VCCPLL[1] VCCPLL[2] VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16]

SANDY-BRIDGE_BGA1023~D

i5@

D D

+VCC_GFXCORE_AXG

C C

330U_D2_2V_Y

C131

C109 0.1U_0402_10V7KC109 0.1U_0402_10V7K

C110 0.1U_0402_10V7KC110 0.1U_0402_10V7K

22U_0805_6.3V6M

C111

C112

22U_0805_6.3V6M

C114

C122

330U_D2_2V_Y

0.1U_0402_16V4Z~D

C132

CC76

Vaxg

1U_0402_6.3V6K

C836

C835

B B

A A

1U_0402_6.3V6K

C838

C837

C839

C840

C841

+1.8VS

330U_D2_2V_Y

C841

R122

0_0805_5%

1 2

+VCCSA

C142

VCC_AXG_SENSE<48> VSS_AXG_SENSE<48>

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

SM_VREF

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22]

DDR3 - 1.5V RAILS

POWER

VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

AY43

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+V_SM_VREF_CNT

Dell open

VCCSA_SENSE

VCCSA_VID0 VCCSA_VID1

C824

1 2

1U_0402_6.3V6K

C825

CPU1.5V_S3_GATE<26>

1U_0402_6.3V6K

C723

1 2

R124 0_0402_5%@R124 0_0402_5%@

1U_0402_6.3V6K

C827

C826

SUSP#<26,28,46>

+1.5V_CPU_VDDQ

VCCSA_SENSE <47>

VCCSA_SEL <47>

1U_0402_6.3V6K

C828

C829

R863

R863 10K_0402_5%

10K_0402_5%

1U_0402_6.3V6K

RC104

@RC104

1 2

0_0402_5%~D

RC107

1 2

0_0402_5%~D

C830

+V_SM_VREF should have 20 mil trace width

0.1U_0402_16V4Z

1U_0402_6.3V6K

C831

RUN_ON_CPU1.5VS3

C126

1U_0402_6.3V6K

C833

C832

C834

RC102

RC102 100K_0402_5%~D

100K_0402_5%~D

RUN_ON_CPU1.5VS3#

QC6A

QC6A 2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

VID[0] VID[1] 2011 2012 0 0 0.90 V Yes Yes 0 1 0.80 V Yes Yes 1 0 0.725 V No Yes 1 1 0.675 V No Yes

AP2302GN-HF_SOT23-3~D

R123

@R123

0_0402_5%

10U_0603_6.3V6M

C135

10U_0603_6.3V6M

C147

10U_0603_6.3V6M

C133

C124

C127

+1.5V_CPU_VDDQ

R113

R113 100_0402_1%

100_0402_1%

R115

R115 100_0402_1%

100_0402_1%

+1.5V_CPU_VDDQ

10U_0603_6.3V6M

C130

C130 C134

C134

C129

330U_D2_2V_Y

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

RC101

RC101 100K_0402_5%~D

100K_0402_5%~D

RUN_ON_CPU1.5VS3

QC6B

2N7002DW-7-F_SOT363-6~D

RUN_ON_CPU1.5VS3# <6,28>

Security Classification

Issued Date

THIS SHEET OF ENGINEERIN G DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERIN G DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

QC3

AO4728L_SO8~D

8 7 6 5

1 2

CC138

RC103

20K_0402_5%~D

10U_0805_10V4Z~D

20K_0402_5%~D

Compal Secret Data

Deciphered Date

0.1U_0603_50V_X7R

CC139

RC105

330K_0402_1%

2010/12/20 2011/12/20

C128

B+_BIAS+3VALW

+V_SM_VREF

10U_0603_6.3V6M

UCPU1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

VSS[12]

AA1

VSS[13]

AA13

VSS[14]

AA50

VSS[15]

AA51

VSS[16]

AA52

VSS[17]

AA53

VSS[18]

AA55

VSS[19]

AA56

VSS[20]

AA8

VSS[21]

AB16

VSS[22]

AB18

VSS[23]

AB21

VSS[24]

AB48

VSS[25]

AB61

VSS[26]

AC10

VSS[27]

AC14

VSS[28]

AC46

VSS[29]

AC6

VSS[30]

AD17

VSS[31]

AD20

VSS[32]

AD4

VSS[33]

AD61

VSS[34]

AE13

VSS[35]

AE8

VSS[36]

AF1

VSS[37]

AF17

VSS[38]

AF21

VSS[39]

AF47

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AF51

VSS[43]

AF52

VSS[44]

AF53

VSS[45]

AF55

VSS[46]

AF56

VSS[47]

AF58

VSS[48]

AF59

VSS[49]

AG10

VSS[50]

AG14

VSS[51]

AG18

VSS[52]

AG47

VSS[53]

AG52

VSS[54]

AG61

VSS[55]

AG7

VSS[56]

AH4

VSS[57]

AH58

VSS[58]

AJ13

VSS[59]

AJ16

VSS[60]

AJ20

VSS[61]

AJ22

VSS[62]

AJ26

VSS[63]

AJ30

VSS[64]

AJ34

VSS[65]

AJ38

VSS[66]

AJ42

VSS[67]

AJ45

VSS[68]

AJ48

VSS[69]

AJ7

VSS[70]

AK1

VSS[71]

AK52

VSS[72]

AL10

VSS[73]

AL13

VSS[74]

AL17

VSS[75]

AL21

VSS[76]

AL25

VSS[77]

AL28

VSS[78]

AL33

VSS[79]

AL36

VSS[80]

AL40

VSS[81]

AL43

VSS[82]

AL47

VSS[83]

AL61

VSS[84]

AM13

VSS[85]

AM20

VSS[86]

AM22

VSS[87]

AM26

VSS[88]

AM30

VSS[89]

AM34

VSS[90]

SANDY-BRIDGE_BGA1023~D

AM38

VSS[91]

AM4

VSS[92]

AM42

VSS[93]

AM45

VSS[94]

AM48

VSS[95]

AM58

VSS[96]

AN1

VSS[97]

AN21

VSS[98]

AN25

VSS[99]

AN28

VSS[100]

AN33

VSS[101]

AN36

VSS[102]

AN40

VSS[103]

AN43

VSS[104]

AN47

VSS[105]

AN50

VSS[106]

AN54

VSS[107]

AP10

VSS[108]

AP51

VSS[109]

AP55

VSS[110]

AP7

VSS[111]

AR13

VSS[112]

AR17

VSS[113]

AR21

VSS[114]

AR41

VSS[115]

AR48

VSS[116]

AR61

VSS[117]

AR7

VSS[118]

AT14

VSS[119]

AT19

VSS[120]

AT36

VSS[121]

AT4

VSS[122]

AT45

VSS[123]

VSS

Title

Size Document Number Rev

Custom

Date: Sheet of

AT52

VSS[124]

AT58

VSS[125]

AU1

VSS[126]

AU11

VSS[127]

AU28

VSS[128]

AU32

VSS[129]

AU51

VSS[130]

AU7

VSS[131]

AV17

VSS[132]

AV21

VSS[133]

AV22

VSS[134]

AV34

VSS[135]

AV40

VSS[136]

AV48

VSS[137]

AV55

VSS[138]

AW13

VSS[139]

AW43

VSS[140]

AW61

VSS[141]

AW7

VSS[142]

AY14

VSS[143]

AY19

VSS[144]

AY30

VSS[145]

AY36

VSS[146]

AY4

VSS[147]

AY41

VSS[148]

AY45

VSS[149]

AY49

VSS[150]

AY55

VSS[151]

AY58

VSS[152]

AY9

VSS[153]

BA1

VSS[154]

BA11

VSS[155]

BA17

VSS[156]

BA21

VSS[157]

BA26

VSS[158]

BA32

VSS[159]

BA48

VSS[160]

BA51

VSS[161]

BB53

VSS[162]

BC13

VSS[163]

BC5

VSS[164]

BC57

VSS[165]

BD12

VSS[166]

BD16

VSS[167]

BD19

VSS[168]

BD23

VSS[169]

BD27

VSS[170]

BD32

VSS[171]

BD36

VSS[172]

BD40

VSS[173]

BD44

VSS[174]

BD48

VSS[175]

BD52

VSS[176]

BD56

VSS[177]

BD8

VSS[178]

BE5

VSS[179]

BG13

VSS[180]

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

1.0

10 49Thursday, July 28, 2011

+1.5V

CD6

10U_0603_6.3V6M~D

CD11

1U_0402_6.3V6K~D

CD20

RD1

RD1 1K_0402_1%~D

1K_0402_1%~D

+V_DDR_REFA

RD3

RD3 1K_0402_1%~D

1K_0402_1%~D

All VREF traces should have 10 mil trace width

10U_0603_6.3V6M~D

CD12

CD13

DDR_A_DQS#[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_MA[0..15]<7>

D D

Layout Note: Place near JDIMM1

+1.5V

1U_0402_6.3V6K~D

CD3

+1.5V

10U_0603_6.3V6M~D

C C

B B

CD7

CD8

Layout Note: Place near JDIMM1.203,204

+0.75VS

1U_0402_6.3V6K~D

CD17

1U_0402_6.3V6K~D

CD4

CD5

10U_0603_6.3V6M~D

CD9

CD10

1U_0402_6.3V6K~D

CD19

CD18

+V_DDR_REFA

RD2 0_0402_5%~D

1 2

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

CD1

DDR_CKE0_DIMMA<7> DDR_CKE1_DIMMA <7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

+3VS

CD21

+DIMM0_VREF

DDR_A_D0 DDR_A_D1

CD2

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

1 2

RD6 10K_0402_5%~DR D6 10K_0402_5%~D

1 2

RD7 10K_0402_5%~DR D7 10K_0402_5%~D CD22

CD22

+0.75VS

+1.5V

JDIMM1

VREF_DQ1VSS1

VSS2

DQ0

DQ1 VSS49DQS#0

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2 DQS247VSS17 VSS1849DQ22

DQ18 DQ1953VSS19 VSS2055DQ28

DQ24 DQ2559VSS21 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3 A12/BC#83A11

VDD5

VDD7

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

BELLW_80011-1021

DR3

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

DQ23

DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

+1.5V

DDR_A_D4

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A6 A4

A2 A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PCH_SMBDATA PCH_SMBCLK

+0.75VS

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

PCH_SMBDATA <12,14,23> PCH_SMBCLK <12,14, 23>

+VREF_CA

2.2U_0603_6.3V6K~D

DDR3_DRAMRST# <7, 12>

+1.5V

RD4

RD4 1K_0402_1%~D

1K_0402_1%~D

0.1U_0402_16V7K~D

CD15

RD5

RD5 1K_0402_1%~D

1K_0402_1%~D

CD16

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMA

LA-7451P

11 49Thursday, July 28, 2011

1.0

+1.5V

RD15

RD15 1K_0402_1%~D

1K_0402_1%~D

+V_DDR_REFB

DDR_B_DQS#[0..7]<7>

DDR_B_DQS[0..7]<7>

D D

C C

B B

DDR_B_D[0..63]<7>

DDR_B_MA[0..15]<7>

+1.5V

1U_0402_6.3V6K~D

+1.5V

10U_0603_6.3V6M~D

CD32

Layout Note: Place near JDIMMB.203,204

+0.75VS

CD29

CD28

10U_0603_6.3V6M~D

CD33

CD34

1U_0402_6.3V6K~D

CD42

CD43

Layout Note: Place near JDIMMB

1U_0402_6.3V6K~D

CD31

CD30

10U_0603_6.3V6M~D

CD36

CD35

1U_0402_6.3V6K~D

CD44

10U_0603_6.3V6M~D

CD38

CD37

CD45

RD16

RD16 1K_0402_1%~D

1K_0402_1%~D

330U_SX_2VY~D

CD39

+V_DDR_REFB

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

All VREF traces should have 10 mil trace width

+3VS

RD14 0_0402_5%~D

1 2

2.2U_0603_6.3V6K~D

CD27

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

RD19

10K_0402_5%~D

+1.5V

0.1U_0402_16V7K~D

10K_0402_5%~D

+DIMM1_VREF

DDR_B_D0 DDR_B_D1

CD26

DDR_B_D2

DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

RD20

+0.75VS

CD46

JDIMM2

VREF_DQ1VSS1

VSS2

DQ0

DQ1 VSS49DQS#0

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9 VSS925VSS10

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2 DQS247VSS17 VSS1849DQ22

DQ18 DQ1953VSS19 VSS2055DQ28

DQ24 DQ2559VSS21 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3 A12/BC#83A11

VDD5

VDD7

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

DDR3

CD47

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

DQ14 DQ15

DQ20 DQ21

DQ23

DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A6 A4

A2 A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

TYCO_2-2013843-1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

+1.5V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PCH_SMBDATA PCH_SMBCLK

+0.75VS

DDR3_DRAMRST# <7, 11>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

CD40

PCH_SMBDATA <11,14,23> PCH_SMBCLK <11,14,23>

RD17

RD17 1K_0402_1%~D

1K_0402_1%~D

CD41

+1.5V

RD18

RD18 1K_0402_1%~D

1K_0402_1%~D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMB

LA-7451P

12 49Thursday, July 28, 2011

1.0

PCH_RTCX1

32.768KHZ_12.5PF_Q13MC14610002

CH3

CH3 18P_0402_50V8J~D

18P_0402_50V8J~D

1 2

RH27 33_0402_5%

1 2

RH28 33_0402_5%

1 2

RH33 33_0402_5%

1 2

RH275 1M_0402_5%~DRH275 1M_0402_5%~D

HDA_SDO<26>

RH39

@RH39

200_0402_5%

RH45

RH45 100_0402_1%~D

100_0402_1%~D

1 2

RH53 51_0402_5%

PCH_SPI_WP#

PCH_SPI_HOLD#

RH256

1 2

33_0402_5%

CH98

10P_0402_50V8J~D

PCH_RTCX2

+RTCVCC

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R

1 2

RH24 0_0402_5%~DRH24 0_0402_5%~D

1 2

RH30 33_0402_5%

RH40

@RH40

200_0402_5%

RH46

100_0402_1%~D

+3V_PCH

RH267

RH267 10K_0402_5%~D

10K_0402_5%~D

DP_PCH_HPD

RH268

RH268 100K_0402_5%~D

100K_0402_5%~D

1 2

PCH_SPI_CLK_R

PCH_SPI_CLK

+RTCVCC

RH11

CH4

1U_0603_10V4Z

1 2

RH25 20K_0402_5%~DRH25 20K_0402_5%~D

1 2

RH23 20K_0402_5%~DRH23 20K_0402_5%~D

CH5

1U_0603_10V4Z

+5VS

QH1BSS138_SOT23

1 2

RH36 0_0402_5%~D

HDA_SDOUT

1M_0402_5%~D

CMOS

CLRP1

CLRP2

ME CMOS

HDA_SPKR<31>

HDA_SDIN0<31>

DP_PCH_HPD<32>

PCH_JTAG_TCK<6>

PCH_JTAG_TMS<6>

PCH_JTAG_TDI<6>

PCH_JTAG_TDO<6>

close to UH1

1 2

RH58 0_0402_5%~D

1 2

RH60 33_0402_5%RH60 33_0402_5%

SM_INTRUDER#

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

DP_PCH_HPD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

RH255 0_0402_5%~D

PCH_SPI_CLK

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

+3V_PCH

RH57

@ RH57

3.3K_0402_5%

1 2

PCH_SPI_CS#_RPCH_SPI_CS#

PCH_SPI_WP#

1 2

SHORT PADS

CLP1 & CLP2 place near DIMM

HDA_SYNC

PCH_SPI_CLK_R

PCH_SPI_SO PCH_SPI_SO_R

1 2

RH2 10M_0402_5%RH2 10M_0402_5%

18P_0402_50V8J~D

CH2

OSC4OSC

YH1

D D

C C

B B

A A

YH1

NC3NC

far away hot spot

HDA_BITCLK_AUDIO<31>

HDA_RST_AUDIO#<31>

HDA_SYNC_AUDIO<31>

HDA_SDOUT_AUDIO<31>

+3V_PCH +3V_PCH+3V_PCH

RH38

@RH38

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

RH44

100_0402_1%~D

PCH_JTAG_TCK

+3V_PCH

1 2

RH54 3.3K_0402_5%RH54 3.3K_0402_5%

1 2

RH56 3.3K_0402_5%RH56 3.3K_0402_5%

CH94

22P_0402_50V8J~D

Reserve for EMI please close t o U48

Reserve for RF please close to UH1

HDA_SDOUT

CH103 10P_0402_50V8J~D

HDA_BIT_CLK

CH97 10P_0402_50V8J~D

Reserve for RF please close to UH1

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

Y14

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

CougarPoint_Rev_1p0

SA00003P42L

RTCIHDA

JTAG

SPI

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA

SATA3RCOMPO

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI ROM FOR ME ( 4MByte )

U48

/CS

/WP

GND4DIO

W25Q32BVSSIG_SO8~D

SPI BIOS Pinout

(1)CS# (5)DIO (2)DO (6)CLK (3)WP# (7)HOLD # (4)GND (8)VCC

W25X32

VCC

/HOLD

PCH_SPI_HOLD#

PCH_SPI_CLK_R

CLK

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA 6G

SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

C38 A38 B37 C37

D36

E36 K36

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

V14

1 2

RH63 33_0402_5%RH63 33_0402_5%

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

SERIRQ

SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

SATA_PTX_DRX_N2 SATA_PTX_DRX_P2

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

PCH_GPIO21

BBS_BIT0_R

PCH_SPI_SIPCH_SPI_SI_R

LPC_AD0 <26> LPC_AD1 <26> LPC_AD2 <26> LPC_AD3 <26>

LPC_FRAME# <26>

SERIRQ <26>

CH91 0.01U_0402_16V7K~DCH91 0.01U_0402_16V7K~D

1 2

CH90 0.01U_0402_16V7K~DCH90 0.01U_0402_16V7K~D

1 2

CH92 0.01U_0402_16V7K~DCH92 0.01U_0402_16V7K~D

1 2

CH93 0.01U_0402_16V7K~DCH93 0.01U_0402_16V7K~D

1 2

10K_0402_5%~D

CH6

0.1U_0402_16V7K~D

+1.05VS_VCC_SATA

+1.05VS_SATA3

Security Classification

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

1 2

RH41 37.4_0402_1%RH41 37.4_0402_1%

1 2

RH43 49.9_0402_1%RH43 49.9_0402_1%

1 2

RH48 750_0402_1%~D

RH276

+3V_PCH

+3VS

Issued Date

SATA_PRX_DTX_N1 <23> SATA_PRX_DTX_P1 <23> SATA_PTX_DRX_N1_C <23> SATA_PTX_DRX_P1_C <23>

SATA_PRX_DTX_N2 <23> SATA_PRX_DTX_P2 <23> SATA_PTX_DRX_N2_RP <23> SATA_PTX_DRX_P2_RP <23>

HDD1

ODD

PCH_INTVRMEN

INTVRMEN

H：Integrated VRM enable

：

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

RTC Battery

+RTCVCC

W=20mils

CH95

CH95 1U_0603_10V4Z

1U_0603_10V4Z

Compal Secret Data

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

RH31 330K_0402_5%RH31 330K_0402_5%

RH34 330K_0402_5%@RH34 330K_0402_5%@

Integrated VRM disable

SERIRQ

+RTCVCC

HDA_SYNC

This signal has a weak interna l pull-down

n Die PLL VR is supplied by

1.5V when smapl ed high

1.8V when sampl ed low Needs to be pul led High for Hu ron River platf rom

HDA_SYNC

RH52 1K_0402_5%~D RH52 1K_0402_5%~D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

LA-7451P

RH29 10K_0402_5%~DRH29 10K_0402_5%~D

PCH_GPIO21

RH32 10K_0402_5%~DRH32 10K_0402_5%~D

PCH_SATALED#PCH_INTVRMEN

RH35 10K_0402_5%~DRH35 10K_0402_5%~D

HDA_SPKR

RH37 1K_0402_5%~D@RH37 1K_0402_5%~D@

HDA_SDOUT

RH42 1K_0402_5%~D@RH42 1K_0402_5%~D@

Low = Disabled

High = Enabled

LOW=Default HIGH=No Reboot

+3V_PCH

+3VS

+3V_PCH

1.0

13 49Thursday, July 28, 2011

1.0

PCIE_PRX_GLANTX_N3<22>

10/100/1G LAN --->

D D

MiniWLAN (Mini Card 1)--->

CARD_READER --->

USB 3.0 --->

PCIE_PRX_GLANTX_P3<22> PCIE_PTX_GLANRX_N3<22> PCIE_PTX_GLANRX_P3<22>

PCIE_PRX_WLANTX_N1<27> PCIE_PRX_WLANTX_P1<27> PCIE_PTX_WLANRX_N1<27> PCIE_PTX_WLANRX_P1<27>

PCIE_PRX_CARDTX_N4<33> PCIE_PRX_CARDTX_P4<33> PCIE_PTX_CARDRX_N4<33> PCIE_PTX_CARDRX_P4<33>

PCIE_PRX_USB3TX_N6<30> PCIE_PRX_USB3TX_P6<30> PCIE_PTX_USB3RX_N6<30> PCIE_PTX_USB3RX_P6<30>

CH9 0.1U_0402_10V7K~DCH9 0.1U_0402_10V7K~D

1 2

CH14 0.1U_0402_10V7K~DCH14 0.1U_0402_10V7K~D

1 2

CH11 0.1U_0402_10V7K~DCH11 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D

1 2

CH12 0.1U_0402_10V7K~DCH12 0.1U_0402_10V7K~D

1 2

CH13 0.1U_0402_10V7K~DCH13 0.1U_0402_10V7K~D

1 2

CH19 0.1U_0402_10V7K~DCH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~DCH20 0.1U_0402_10V7K~D

1 2

Reserve for EMI please close t o UH1

C C

Reserve for EMI please close t o UH1

10/100/1G LAN --->

MiniWLAN (Mini Card 1)--->

Card Reader --->

B B

USB 3.0 --->

XTAL25_IN

RH1171M_0402_5%~D RH1171M_0402_5%~D

YH2

25MHZ_18PF_1Y725000CE1A~D

1 2

22P_0402_50V8J~D

CH23

A A

CH24

XTAL25_OUT

CLK_CPU_ITP#<6> CLK_CPU_ITP<6>

22P_0402_50V8J~D

+3V_PCH

CLK_PCIE_LAN#<22> CLK_PCIE_LAN<22>

LANCLK_REQ#<22>

+3VS

CLK_PCIE_MINI1#<27> CLK_PCIE_MINI1<27>

MINI1CLK_REQ#<27>

CLK_PCIE_CD#<33> CLK_PCIE_CD<33>

CDCLK_REQ#<33>

+3V_PCH

CLK_PCIE_USB30#<30> CLK_PCIE_USB30<30>

+3V_PCH

USB30_CLKREQ#<30>

+3V_PCH

CLK_CPU_ITP# CLK_CPU_ITP

RH91 10K_0402_5%~DRH91 10K_0402_5%~D

RH93 0_0402_5%~D

RH93 0_0402_5%~D RH94 0_0402_5%~D

RH94 0_0402_5%~D

RH95 10K_0402_5%~D

+3VS

RH100 10K_0402_5%~DRH100 10K_0402_5%~D

RH101 0_0402_5%~D

RH101 0_0402_5%~D RH102 0_0402_5%~D@RH102 0_0402_5%~D@ RH103 10K_0402_5%~DRH103 10K_0402_5%~D

+3V_PCH

RH104 0_0402_5%~D

RH104 0_0402_5%~D RH106 0_0402_5%~D@RH106 0_0402_5%~D@ RH107 10K_0402_5%~DRH107 10K_0402_5%~D

+3V_PCH

RH110 10K_0402_5%~DRH110 10K_0402_5%~D

RH112 10K_0402_5%~DRH112 10K_0402_5%~D

RH114 0_0402_5%~D

RH114 0_0402_5%~D RH115 0_0402_5%~D@RH115 0_0402_5%~D@ RH116 10K_0402_5%~DRH116 10K_0402_5%~D

RH118 10K_0402_5%~DRH118 10K_0402_5%~D

RH119 0_0402_5%~D

RH119 0_0402_5%~D RH120 0_0402_5%~D

RH120 0_0402_5%~D

1 2

1 2 1 2

@ @

1 2

@ @

12 12 12

12 12

PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3 PCIE_PTX_GLANRX_N3_C PCIE_PTX_GLANRX_P3_C

PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1 PCIE_PTX_WLANRX_N1_C PCIE_PTX_WLANRX_P1_C

PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4 PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C

PCIE_PRX_USB3TX_N6 PCIE_PRX_USB3TX_P6 PCIE_PTX_USB3RX_N6_C PCIE_PTX_USB3RX_P6_C

T81PAD~D @T81PAD~D @ T82PAD~D @T82PAD~D @

PCIECLKREQ0#

PCIE_LAN# PCIE_LAN

LANCLK_REQ#

PCIE_MINI1# PCIE_MINI1

MINI1CLK_REQ#

PCIE_CD# PCIE_CD

CDCLK_REQ#

PEG_B_CLKREQ#

PCIE_USB30# PCIE_USB30

USB30_CLKREQ#

GPIO46

CLK_BCLK_ITP# CLK_BCLK_ITPCLK_BCLK_ITP

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CougarPoint_Rev_1p0

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

PCH_LID_SW_IN#

E12

SMBCLK

H14

SMBDATA

DRAMRST_CNTRL_PCH

A12

SML0CLK

SML0DATA

G12

C13

SML1CLK

E14

SML1DATA

M16

T11

No support iAMT

P10

PEG_A_CLKRQ#

M10

CLK_PEG_VGA#

AB37

CLK_PEG_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12 AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

KB_DET#

K43

DMC_PCH_DET#

F47

BT_DET#

H47

CAM_DET#

K49

CAM_DET#

DMC_PCH_DET#

BT_DET#

KB_DET#

MEMORY

Total device

1 2

RH113 90.9_0402_1%RH113 90.9_0402_1%

1 2

RH166 10K_0402_5%~DRH166 10K_0402_5%~D

1 2

RH109 10K_0402_5%~DRH109 10K_0402_5%~D

1 2

RH108 10K_0402_5%~DRH108 10K_0402_5%~D

R1791 100K_0402_5%~DR1791 100K_0402_5%~D

EC_LID_OUT#

1 2

RH680_0402_5%~D@RH680_0402_5%~D

1 2

RH710_0402_5%~D@RH710_0402_5%~D

DRAMRST_CNTRL_PCH <7>

20090512 a

dd double mosfet prevent

ATI M92 electric leakage

+3V_PCH

RH141

RH141 10K_0402_5%~D

10K_0402_5%~D

1 2

CLK_PEG_VGA# <34> CLK_PEG_VGA <34>

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

CLK_PCI_LPBACK <16>

KB_DET# <24>

DMC_PCH_DET#

BT_DET#

CAM_DET# <21>

PEG_A_CLKRQ# <34>

+1.05VS_VCCDIFFCLKN

+3VS

EC_LID_OUT# <26>

LID_SW_IN# <21,26>

SMBCLK

SMBDATA

6 1

DMN66D0LDW-7_SOT363-6~D

SML1CLK

DMN66D0LDW-7_SOT363-6~D

SML1DATA

CLK_PEG_VGA# CLK_PEG_VGA

+3VS

2.2K_0402_5%~D

QH3A

DMN66D0LDW-7_SOT363-6~D

6 1

DMN66D0LDW-7_SOT363-6~D

QH4A

+3VS

QH3B

QH4B

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

LID_SW_IN#

DRAMRST_CNTRL_PCH

CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen else, please pl ace close to P CH

RH85 10K_0402_5%~DRH85 10K_0402_5%~D

1 2

RH87 10K_0402_5%~DRH87 10K_0402_5%~D

1 2

+3VS

RH98

1 2

RH67 2.2K_0402_5%~DRH67 2.2K_0402_5%~D

1 2

RH69 2.2K_0402_5%~DRH69 2.2K_0402_5%~D

1 2

RH70 2.2K_0402_5%~D

1 2

RH72 2.2K_0402_5%~D

1 2

RH73 2.2K_0402_5%~DRH73 2.2K_0402_5%~D

1 2

RH74 2.2K_0402_5%~DRH74 2.2K_0402_5%~D

1 2

R1790 10K_0402_5%~D

1 2

RH75 1K_0402_5%~D

RH76 10K_0402_5%~DRH76 10K_0402_5%~D

1 2

RH78 10K_0402_5%~DRH78 10K_0402_5%~D

1 2

RH77 10K_0402_5%~DRH77 10K_0402_5%~D

1 2

RH79 10K_0402_5%~DRH79 10K_0402_5%~D

1 2

RH80 10K_0402_5%~DRH80 10K_0402_5%~D

1 2

RH81 10K_0402_5%~DRH81 10K_0402_5%~D

1 2

RH82 10K_0402_5%~DRH82 10K_0402_5%~D

1 2

RH83 10K_0402_5%~DRH83 10K_0402_5%~D

1 2

RH84 10K_0402_5%~DRH84 10K_0402_5%~D

1 2

RH99

2.2K_0402_5%~D

1 2

PCH_SMBCLK <11,12,23>

PCH_SMBDATA <11,12,23>

PCH_SMLCLK <26,35>

PCH_SMLDATA <26,35>

+3V_PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/20 2011/12/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-7451P

14 49Thursday, July 28, 2011

1.0

Compal Electronics, Inc.

UH1C

DMI_CTX_PRX_N0<5> DMI_CTX_PRX_N1<5> DMI_CTX_PRX_N2<5> DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5> DMI_CTX_PRX_P1<5> DMI_CTX_PRX_P2<5> DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>

D D

XDP_DBRESET#<6>

C C

PM_DRAM_PWRGD<6>

SUSWARN# SUSACK#_R

B B

GPIO72

RI#

WAKE#

AC_PRESENT

SUSWARN#

PCH_RSMRST#

SYS_PWROK

PM_PWROK_R

A A

DMI_CRX_PTX_N1<5> DMI_CRX_PTX_N2<5> DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5> DMI_CRX_PTX_P1<5> DMI_CRX_PTX_P2<5> DMI_CRX_PTX_P3<5>

+VCCP

RH124 49.9_0402_1%RH124 49.9_0402_1%

RH125 750_0402_1%~DRH125 750_0402_1%~D

4mil width and place within 500mil of the PCH

SUSACK#<26>

PCH_PWROK

PCH_APWROK<26>

PCH_RSMRST#<26>

SUSWARN# SUSWARN#_R

PBTN_OUT#<6,26>

AC_PRESENT< 26>

1 2

RH139 0_0402_5%~D

near UH1

RH143 10K_0402_5%~ DRH143 10K_0402_5%~ D

1 2

RH145 10K_0402_5%~ DRH145 10K_0402_5%~ D

1 2

RH146 10K_0402_5%~ D@RH146 10K_0402_5%~D@

1 2

RH150 10K_0402_5%~ D@RH150 10K_0402_5%~D@

1 2

RH154 10K_0402_5%~ DRH154 10K_0402_5%~ D

1 2

RH159 10K_0402_5%~ DRH159 10K_0402_5%~ D

1 2

RH272 10K_0402_5%~ DRH272 10K_0402_5%~ D

1 2

RH129 100K_0402_5 %~DRH129 10 0K_0402_5%~D

1 2

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

1 2

RH127 0_0402_5%~D@ RH127 0_0402_5%~D@

RH273 0_0402_5%~D

RH130 0_0402_5%~D

RH131 0_0402_5%~D

RH133 0_0402_5%~D

RH134 0_0402_5%~D

RH135 0_0402_5%~D

RH137 0_0402_5%~D

PCH_RSMRST#_R

DMI_IRCOMP

RBIAS_CPY

1 2

XDP_DBRESET#

1 2

PM_DRAM_PWRGD

PCH_RSMRST#_R

1 2

GPIO72

+3V_PCH

100P_0402_50V8J~D

SUSACK#_R

SYS_PWROK

PM_PWROK_R

PBTN_OUT#_R

AC_PRESENT_R

RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

CougarPoint_Rev_1p0

C294

DSWODVREN

RH147 330K_0402_5%RH147 330K_0402_5%

RH151 330K_0402_5%@RH151 330K_0402_5%@

DSWODVREN - On Die DSW VR Enable

H：Enable

L：Disable

PCH_PWROK<6,26>

VGATE<6,2 6,48>

FDI_CTX_PRX_N0

BJ14

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

System Power Management

PCH_PWROK

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

+RTCVCC

CH96

0.1U_0402_16V7K~D

IN1

IN2

+3VS

FDI_CTX_PRX_N1

AY14

FDI_CTX_PRX_N2

BE14

FDI_CTX_PRX_N3

BH13

FDI_CTX_PRX_N4

BC12

FDI_CTX_PRX_N5

BJ12

FDI_CTX_PRX_N6

BG10

FDI_CTX_PRX_N7

BG9

FDI_CTX_PRX_P0

BG14

FDI_CTX_PRX_P1

BB14

FDI_CTX_PRX_P2

BF14

FDI_CTX_PRX_P3

BG13

FDI_CTX_PRX_P4

BE12

FDI_CTX_PRX_P5

BG12

FDI_CTX_PRX_P6

BJ10

FDI_CTX_PRX_P7

BH9

FDI_INT

AW16

FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSWODVREN

A18

PCH_DPWROK

E22

WAKE#

N14

D10

G10

G16

AP14

K14

VCC

GND

1 2

PM_CLKRUN#

SUS_STAT#

SUSCLK

RH132 0_0402_5%~D

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

UH7

SYS_PWROK

OUT

MC74VHC1G08DFT2G_SC70-5

FDI_CTX_PRX_N0 <5> FDI_CTX_PRX_N1 <5> FDI_CTX_PRX_N2 <5> FDI_CTX_PRX_N3 <5> FDI_CTX_PRX_N4 <5> FDI_CTX_PRX_N5 <5> FDI_CTX_PRX_N6 <5> FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 < 5> FDI_CTX_PRX_P1 < 5> FDI_CTX_PRX_P2 < 5> FDI_CTX_PRX_P3 < 5> FDI_CTX_PRX_P4 < 5> FDI_CTX_PRX_P5 < 5> FDI_CTX_PRX_P6 < 5> FDI_CTX_PRX_P7 < 5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

RH126 0_0402_5%~D

1 2

RH128 0_0402_5%~D

If not using integrated LAN,signal may be left as NC.

T76 PAD~DT76 PAD~ D

T77 PAD~DT77 PAD~ D

H_PM_SYNC <6>

PCH_RSMRST#_R

PCH_DPWROK <26>

PCIE_WAKE# <22,26,27>

SUSCLK_R <26>

PM_SLP_S5# <26>

PM_SLP_S4# <26>

PM_SLP_S3# <26>

SUSCLK

Reserve for RF please close to UH1

SYS_PWROK <6>

ENBKL<26>

VGA_LVDDEN<21,26>

VGA_PWM<21>

LVDS_DDC_CLK<21>

LVDS_DDC_DATA<21>

LVDS_ACLK-<21> LVDS_ACLK+<21>

LVDS_A0-<21> LVDS_A1-<21> LVDS_A2-<21>

LVDS_A0+<21> LVDS_A1+<21> LVDS_A2+<21>

Can be left NC when IAMT is not support on the platfrom

CH102

10P_0402_50V8J~D

+3VS

1 2

RH155 2.2K_0402_5%~DRH155 2.2K_0402_5%~D

1 2

RH157 2.2K_0402_5%~DRH157 2.2K_0402_5%~D

1 2

RH248 8.2K_0402_5%~D@RH248 8.2K_04 02_5%~D@

+3VS

RV169 2.2K_04 02_5%~DRV169 2.2K_04 02_5%~D

1 2

RV170 2.2K_04 02_5%~DRV170 2.2K_04 02_5%~D

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/20 2011/12/20

ENBKL

LVDS_DDC_CLK LVDS_DDC_DATA

T203PAD~D T203PAD~D

LVDS_ACLKLVDS_ACLK+

LVDS_A0LVDS_A1LVDS_A2-

LVDS_A0+ LVDS_A1+ LVDS_A2+

RH140

1K_0402_0.5%~D

CTRL_CLK

CTRL_DATA

PM_CLKRUN#

CTRL_CLK CTRL_DATA

LVDS_IBG

CRT_IREF

LVDS_DDC_CLK LVDS_DDC_DATA

Compal Secret Data

Deciphered Date

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

CougarPoint_Rev_1p0

LVDS

CRT

+3VS

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DMC

AP43 AP45

AM42 AM40

AP39

SDVO_INTN

AP40

SDVO_INTP

SDVO_SCLK

P38

SDVO_SDATA

M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

RH167 10K_0402_5%~DRH167 10K_0402_5%~ D

RH144 2.37K_0402_1%~DRH14 4 2.37K_0402_1%~D

RH168 100K_0402_5%~DRH168 100K_0402_5%~D

RH183 100K_0402_5%~DRH183 100K_0402_5%~D

RH158 100K_0402_5%~DRH158 100K_0402_5%~D

RH123 100K_0402_5%~DRH123 100K_0402_5%~ D

PCH_DPB_HPD

AT40

PCH_DPB_N0

AV42

PCH_DPB_P0

AV40

PCH_DPB_N1

AV45

PCH_DPB_P1

AV46

PCH_DPB_N2

AU48

PCH_DPB_P2

AU47

PCH_DPB_N3

AV47

PCH_DPB_P3

AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

1 2

Title

Size Document Number Rev

Date: Sheet

PCH_DPC_HPD

PCH_DPD_HPD

PM_CLKRUN#

LVDS_IBG

PCH_DPC_HPD

PCH_DPD_HPD

VGA_LVDDEN

ENBKL

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-7451P

R983

1 2

2.2K_0402_5%

R984

1 2

2.2K_0402_5%

PCH_DPB_HPD <17,29>

PCH_DPB_N0 <29> PCH_DPB_P0 <29> PCH_DPB_N1 <29> PCH_DPB_P1 <29> PCH_DPB_N2 <29> PCH_DPB_P2 <29> PCH_DPB_N3 <29> PCH_DPB_P3 <29>

SDVO_SCLK <29> SDVO_SDATA < 29>

HDMI D2

HDMI D1

HDMI D0

HDMI CLK

15 49Thursday, July 28, 2011

1.0

D D

C C

B B

A A

+3V_PCH

1 2

RH269

RH269 10K_0402_5%~D

10K_0402_5%~D

CARD_HPLUG

RH264

RH264 100K_0402_5%~D

100K_0402_5%~D

CLK_PCI_LPBACK<14>

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST# DGPU_SELECT#

T165P AD~D @T165PAD~D @ T166P AD~D @T166PAD~D @ T204P AD~D @T204PAD~D @

+3VS

CLK_PCI1

DGPU_PWR_EN

WWAN_RADIO_OFF#

BT_RADIO_DIS# WL_OFF#

FFS_INT1 ODD_DA# DP_CBL_DET CARD_HPLUG

PCH_PLTRST#

CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4

DGPU_PWR_EN<28,34,37,50>

WWAN_RADIO_OFF#<27>

BT_RADIO_DIS#<27>

WL_OFF#<27>

FFS_INT1<23>

ODD_DA#<23>

CARD_HPLUG<33>

T123P AD~D @T123PAD~D @

CLK_PCI_LPBACK

CLK_PCI_LPC<26>

CLK_PCI_LPC

WL_OFF# PCI_PIRQB# PCI_PIRQD# PCI_PIRQC#

DGPU_SELECT# DGPU_PWR_EN FFS_INT1

BT_RADIO_DIS#

PCI_PIRQA#

DP_CBL_DET

ODD_DA#

DGPU_HOLD_RST#

RH164 22_0402_5%RH164 22_0402_5% RH165 22_0402_5%

RH165 22_0402_5%

1 2

RPH3

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RPH4

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RPH5

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RH173 10K_0402_5%~D

1 2

CH99

10P_0402_50V8J~D

Reserve for RF please close to UH1

BG26

BJ26

BH25

BJ16

BG16

AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20

AY16

BG46

BE28 BC30 BE32

BJ32 BC28 BE30 BF32

BG32

AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

H49 H43 J48 K42 H40

CougarPoint_Rev_1p0

10K_0402_5%~D

PLT_RST#<6,22,26,27,30,33>

UH1E

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54

GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55

PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

RH169

+3VS

1 2

RSVD

PCI

USB

RH171

RH171 100K_0402_5%~D

100K_0402_5%~D

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25

RSVD26 RSVD27

RSVD28 RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

+3VS

UH5

IN1

IN2

SN74AHC1G08DCKR_SC70-5

CH101

ODD_DA#

0.1U_0402_16V7K~D

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5 AV10

AT8

AY5 BA2

AT12 BF3

C24 A24

USB20_N1

C25

USB20_P1

B25 C26 A26

USB20_N3

K28

USB20_P3

H28

USB20_N4

E28

USB20_P4

D28

USB20_N5

C28

USB20_P5

A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USBRBIAS

C33

B33

USB_OC2#

A14

USB_OC1#

K20

1.5VDDR_VID0

B17

1.5VDDR_VID1

C16

USB_OC0#

L16

USB_OC5#

A16

USB_OC6#

D14

USB3_SMI#

C14

PCH_PLTRST#

USB20_N1 <23> USB20_P1 <23>

USB20_N3 <21> USB20_P3 <21> USB20_N4 <27> USB20_P4 <27> USB20_N5 <27> USB20_P5 <27>

Within 500 mils

1 2

RH163 22.6_0402_1%RH163 22.6_0402_1%

USB PORT1

Camera

Mini Card(WLAN)

Mini Card(WWAN)

USB_OC2# <23>

(For USB Port 9)

USB3_SMI# <30>

+3VS

UH6

SN74AHC1G08DCKR_SC70-5

Compal Secret Data

RH170

PLTRST_VGA#<34>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

100_0402_5%~D

RH172

100K_0402_5%~D

2010/12/20 2011/12/20

DGPU_HOLD_RST#

10K_0402_5%~D

Deciphered Date

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

RH160 1K_0402_5%~D@ RH160 1K_0402_5%~D@

1 2

USB_OC0# USB_OC2# USB3_SMI# USB_OC5#

USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1 USB_OC6#

1 2

RH265 0_0402_5%~D@ RH265 0_0402_5%~D@

1 2

RH266 0_0402_5%~D

RH179

1 2

RPH1

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%~D

RPH2

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%~D

DGPU_PWROK

PCH_PLTRST#

+1.8VS

+3V_PCH

DGPU_PWROK <17,50>

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

LA-7451P

16 49Thursday, July 28, 2011

1.0

+ 36 hidden pages