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LA-7441P PBL80
Schematic
59 pgs2.03 Mb2
Schematic
60 pgs1.52 Mb1

Compal LA-7441P PBL80, K93SV, X93SV Schematic

5
D D
4
3
2
1
Compal Confidential
C C
PBL80 Project
LA-7441P
B B
SchematicREV 0.1
Intel Sandy Bridge/Cougar Point
N12P-GV/GS-Optimus Only
2011-01-21
A A
5
4
Rev. 0.1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
Friday, January 21, 2011
Friday, January 21, 2011
Friday, January 21, 2011
1
1 58
1 58
1 58
0.1
0.1
0.1
5
Compal Confidential
Model Name : PBL80
File Name : LA-7441PR01
4
3
2
1
D D
PEG(DIS)
PCI-E 2.0x16 5GT/s PER LANE100MHz
133MHz
Mobile
Sandy Bridge
CPU
Dual Core/Quad Core
N12P GV/N12P GS Optimus Only 128*16 1GB/2GB
64*16 512MB/1GB
page 14~25
CRT
page 26
Socket-rPGA989
37.5mm*37.5mm
DMI X4
page 5,6,7,8,9,10,11
FDI X8
LVDS Conn.
page 27
C C
PCI-Express x 8 (PCIE2.0 2.5GT/s)
port 4
USB 3.0 conn x1
PCIe port 4
page 45
PCIeMini Card WLAN & BT Combo
port 2 port 1
USB port 13
PCIe port 2
page 39
HDMI Conn.
page 28
100MHz
RTL8105E 10/100M RTL8111E 1G
PCIe port 1
page 40
RJ45
ODD/B
B B
USB/B
page 38
page 39
page 40
TouchPad & Card Reader & LED/B
page 39
Intel Cougar Point
PCBGA989
page 29,30,31,32,33 ,34,35,36,37
ENE KB930
Touch Pad
page 39
25mm*25mm
LPC BUS
33MHz
page 43
Int.KBD
page 44
Fan Control
page 5
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1066/1333
USB Left X 1 (Co lay with USB3.0 Conn)
USB port 4
page 39
USB
5V 480Mbps
SATA port 0
5V 1.5GHz(150MB/s)
SATA port 1
5V 1.5GHz(150MB/s)
SATA port 2
5V 1.5GHz(150MB/s)
USB/B Right X 3
USB port 0,1,2
HD Audio
Bus switch
BIOS ROM
page 41
page 41
page 39
SATA HDD/ 3.5"
SATA HDD/ 2.5"
SATA ODD
204pin DDRIII-SO-DIMM X4
BANK 0, 1, 2, 3
Int. Camera 0.3M RTS5129 3IN1
USB port 10
page 38
page 38
page 38
3.3V 24.576MHz/48Mhz
page 27
page 12,13
USB port 11
HDA Codec
ALC269
page 42
MIC CONN
page 42
HP CONN
page 42
SPK CONN
page 39
page 42
EC ROM
Power/B
page 44
page 44
RTC CKT.
page 29
CPU XDP
A A
DC/DC Interface CKT.
page 46
Power Circuit DC/DC
page 47~58
5
page 5
PCH XDP
page 29
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
2 58Friday, January 21, 2011
2 58Friday, January 21, 2011
2 58Friday, January 21, 2011
0.1
0.1
0.1
5
4
3
2
1
(ipeak=10A imax=7A
B+
+5VALW
D D
RT8205EGQW
+5VALW
+5VALW
+3VALW
+3VALW
C C
DRVON
AP4800BGM
SY8033BDBC
SY8035DBC
P-CHANNEL
AO3413
AP4800BGM
NCP5911MNTBG
SUSP#
TPS40210DRCR
SUSP
SUSP#
SUSP#
WOL_EN#
SUSP
SUSP#
P-CHANNEL
AO-3413
P-CHANNEL
AO-3413
TPS51218DSCR +VGA_CORE
DESIGN CURRENT 10A
DESIGN CURRENT 6A
DESIGN CURRENT 2A
DESIGN CURRENT 6A
ipeak=6A imax=4.2A
DESIGN CURRENT 170mA
DESIGN CURRENT 1.6A
DGPU_PWR_EN#
DESIGN CURRENT 700mA
VGA_ENVDD
DESIGN CURRENT 3A
Ipeak=94A, Imax(TDP)=56A
DESIGN CURRENT 2A
DESIGN CURRENT 35A
+5VALWP
+5VS
+1.8VSP
+VCCSAP
+3VALWP
+3V_LAN
+3VS
+3VS_DGPU
+LCD_VDD
+CPU_CORE
+12VS
+5VALW(PJP305,PJP306) +5VALW_PCH(PJ334)
+1.8VS(PJP401)
+VCCSA(PJP801)
+3VALW(PJP303)
+3V_EC(R715)
+3VALW_PCH(J1)
SUSP#
RT8209BGQW
B B
+1.05VS_VCCP
SYSON
RT8209BGQW
+1.5V
+1.5V
+1.5V
A A
+1.5V
5
N-CHANNEL
SI4856ADY
N-CHANNEL
SI4856ADY
APL5336KAI-TRL
TPCA8059
4
N-CHANNEL
AO3416
SUSP
RUN_ON_CPU1.5VS3
SUSP
VGA_PWROK#
DGPU_PWR_EN#
DESIGN CURRENT 18A
+1.05VS_VCCP
+1.05VS_PCH(JP2)
DESIGN CURRENT 3.66A
Ipeak = 30A Imax= 21A
DESIGN CURRENT 600mA
DESIGN CURRENT 10A
DESIGN CURRENT 2A
DESIGN CURRENT 11A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.05VS_DGPU
+1.5VP
+1.5V(PJP501,PJP502.PJP503)
+1.5VS
+1.5V_CPU
+0.75VSP
+0.75VS(PJP601)
+VRAM_1.5VS
Compal Secret Data
Compal Secret Data
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Power Map
Power Map
Power Map
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
3 58Friday, January 21, 2011
3 58Friday, January 21, 2011
3 58Friday, January 21, 2011
0.1
0.1
0.1
5
Voltage Rails
power
D D
C C
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
plane
State
S0
S1
S3
S5 S4/AC
( O MEANS ON X MEANS OFF )
+RTCVCC
O
O
O
O
O
O
B+
O
O
O
O
O
X
+5VL
+3VL
O
O
O
O
O
X
+5VALW
+3VALW
+5VALW_PCH
+3VALW_PCH
+3V_LAN
+3V_EC
+VSB
PCH SM Bus Address
HEX
Power
+3VS
B B
+3VS
+3VS
Device
DDR SO-DIMMA1
DDR SO-DIMMB1
WLAN
Address
1010 0000 bA0 H
1010 0010 bA0 HDDR SO-DIMMA2+3VS
1010 0100 bA4 H
1010 0110 bA0 HDDR SO-DIMMB2+3VS
4
+1.5V
+5VS
+3VS
+1.8VS
+1.5VS
+1.05VS_VCCP
+0.75VS
+CPU_CORE
+VGA_CORE
+GFX_CORE
+VCCSA
+VRAM_1.5VS
+3VS_DGPU
+1.05VS_DGPU
+12VS
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
G3 LOW LOWLOW
Function
description
O
O
O
O
X
X
O
X X
X
X X
OO
OO
X
X
explain
BTO
Function
description
explain
BTO
Function
description
explain
BTO
Function
description
explain
BTO
3
SIGNAL
SLP_S3# SLP_S4# SLP_S5#
HIGH HIGHHIGH
HIGH HIGHHIGH
LOW
LOW LOW
Samsung 64bits
VRAM
8PCS@ N12PGS@
Crisis recovery
BUS SWITCH
BUS SWITCH
Debug@
USB3.0/2.0 Colay
USB3.0
USB3.0
USB3@
SATA path
PCH
PCH
SATA@
PD 20K PD 15K PD 45.3K PD 34.8K
USB2.0
USB2.0
USB2@
Repeater
Repeater
SATARP@
HIGH
HIGH
HIGH
LOW LOWLOW
VRAM
Hynix 64bits
HDMI
HDMI
HDMI
HDMI@
WLAN+BT(BT pin 51)
WLAN+BT(BT pin 51)
BT@
SATA3.0 Repeater Chip
MAXIM
MAX4951
MAXIM@
SN75LVCP601
Samsung 128bits
TI
TI@
2
Hynix 128bits
WLAN+BT
WLAN+BT(BT pin 5)
WLAN+BT(BT pin 5)
COMBO@
SATA Preemphasis
Preemphasis
Enable
DEN@
Strap pin
N12P-GSVRAM
Disable
NDEN@
GPU
N12P-GV
Strap pinStrap pin Strap pin Strap pin Strap pin
N12PGV@
LAN
Giga LAN
Strap pin
8111E@
SATA Equalization
Equalization
Maximum
EQ@
1
Board ID
Adaptor
Adaptor
90W@, 120W@
10/100M LAN
Strap pin
8105E@
Normal
NEQ@
EC SM Bus1 Address
Device Address Address
+3VL
A A
HEX HEX
16 H
0001 0110 bSmart Battery
5
PowerPower
+3VS
+3VS
EC SM Bus2 Address
Device
96 H
1001 0110 bPCH
VGA Thermal Sensor 1001 1010 b
9A H
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
4 58Friday, January 21, 2011
4 58Friday, January 21, 2011
4 58Friday, January 21, 2011
0.1
0.1
0.1
5
4
3
2
1
Support Dual Core/ Quad Core
JCPUB
JCPUB
C1
C1
@
@
H_PWRGOOD
12
220P_0402_25V8J
220P_0402_25V8J
D D
C2
C2
@
@
H_PROCHOT#
12
220P_0402_25V8J
220P_0402_25V8J
H_SNB_IVB#<33>
@
@
@
1 2
1 2
TP_SKTOCC#
H_CATERR#
H_PECI
H_PROCHOT#_R
H_THERMTRIP#_R
T1 PAD@T1 PAD
T2 PAD
T2 PAD
H_PECI<34,43>
H_PROCHOT#<43>
H_THERMTRIP#<34>
R6 56_0402_5%R6 56_0402_5%
R10 0_0402_5%R10 0_0402_5%
AN34
AL33
AN33
AL32
AN32
C26
SNB_IVB#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
BCLK
BCLK#
A28 A27
A16 A15
R8
AK1 A5 A4
R3
R3
1 2
R4
R4
1 2
H_DRAMRST#
SM_RCOMP_0
R7 140_0402_1%R7 140_0402_1%
SM_RCOMP_1
R8 25.5_0402_1%R8 25.5_0402_1%
SM_RCOMP_2
R9 200_0402_1%R9 200_0402_1%
1K_0402_5%
1K_0402_5% 1K_0402_5%
1K_0402_5%
from DDR
H_DRAMRST# <7>
12 12 12
CLK_CPU_DMI <30> CLK_CPU_DMI# <30>
+1.05VS_VCCP
eDP
DDR3 Compensation Signals Layout Note:Please these
resistors near Processor
If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistor
PRDY#
PREQ#
+1.05VS_VCCP
C C
Follow DG 0.71
DRAMPWROK<31>
B B
CHANGE U5 TO OPEN DRAIN MOS,OUTPUT=1.5V
Processor Pullups
R17 62_0402_5%R17 62_0402_5%
R23 10K_0402_5%R23 10K_0402_5%
PWROK<31>
12
12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
R37 0_0402_5%R37 0_0402_5%
H_PROCHOT#
H_PWRGOOD
1
C3
C3
2
1
2
+3VALW
U1
U1 74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
5
P
B
4
O
A
G
3
SUSP<46,53>
H_PM_SYNC<31>
H_PWRGOOD<34>
FIT 1.5V POWER PLANE OF CPU
PM_SYS_PWRGD_BUF
12
13
D
SUSP
D
2
G
G
S
S
+1.5V_CPU
@
@
R38
R38 39_0402_5%
39_0402_5%
@
@
Q1
Q1 2N7002_SOT23
2N7002_SOT23
12
R36
R36 200_0402_5%
200_0402_5%
H_PWRGOOD
PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF
1 2
R22 130_0402_5%R22 130_0402_5%
BUF_CPU_RST#
XDP Connector
Buffered reset to CPU
+3VS
1
C6
C6
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
5
U3
U3
1
P
NC
R55
A A
PLT_RST#<33,39>
R55
1 2
0_0402_5%
0_0402_5%
5
2
4
Y
A
G
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
3
+1.05VS_VCCP
12
R50
R50 75_0402_5%
75_0402_5%
R52
R52
43_0402_1%
BUFO_CPU_RST# BUF_CPU_RST#
43_0402_1%
1 2
12
@
@
R53
R53 0_0402_5%
0_0402_5%
4
PBTN_OUT#<29,31,43>
CFG0<10>
VGATE<31,43,55>
CLK_RES_ITP<10,30> CLK_RES_ITP#<10,30> +1.05VS_VCCP
0.1U_0402_10V6K
0.1U_0402_10V6K
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
JTAG & BPM
AR33
RESET#
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
XDP_PREQ# XDP_PRDY#
XDP_BPM#0 XDP_BPM#1
XDP_BPM#2
H_PWRGOOD XDP_CPU_HOOK0 PBTN_OUT# CFG0 VGATE
C8
C8
@
@
PLT_RST#
1
2
R44 1K_0402_5%@R44 1K_0402_5%@ R45 0_0402_5%@R45 0_0402_5%@ R46 1K_0402_5%@R46 1K_0402_5%@ R47 0_0402_5%@R47 0_0402_5%@
R48 1K_0402_5%
R48 1K_0402_5%
XDP_BPM#3
1 2 1 2 1 2 1 2
@
@
1 2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JTAG & BPM
XDP_CPU_HOOK1 XDP_CPU_HOOK2 XDP_CPU_HOOK3
XDP_CPU_HOOK6 XDP_DBRESET#
XDP_TDO XDP_TRST# XDP_TDI XDP_TMS
XDP_TCK
3
TRST#
DBR#
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
JXDP1
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
ACES_87152-26051
ACES_87152-26051
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
AP27
AR26
TCK
AR27
TMS
AP30
AR28
TDI
AP26
TDO
AL35
AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32
@JXDP1
@
27 28
Compal Secret Data
Compal Secret Data
Compal Secret Data
XDP_PREQ#_R
XDP_TCK_R XDP_TMS_R XDP_TRST#_R
XDP_TDI_R XDP_TDO_R
XDP_DBRESET#_R
XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R
EN_DFAN1<43>
XDP_PRDY#_R
AP29
+FAN_VCC
Deciphered Date
Deciphered Date
Deciphered Date
R11 0_0402_5%@R11 0_0402_5%@
1 2
R12 0_0402_5%@R12 0_0402_5%@
1 2
R13 0_0402_5%@R13 0_0402_5%@
1 2
R14 0_0402_5%@R14 0_0402_5%@
1 2
R15 0_0402_5%@R15 0_0402_5%@
1 2
R16 0_0402_5%@R16 0_0402_5%@
1 2
R18 0_0402_5%@R18 0_0402_5%@
1 2
R21 0_0402_5%@R21 0_0402_5%@
1 2
R24 0_0402_5%@R24 0_0402_5%@
1 2
R25 0_0402_5%@R25 0_0402_5%@
1 2
R26 0_0402_5%@R26 0_0402_5%@
1 2
R27 0_0402_5%@R27 0_0402_5%@
1 2
R28 0_0402_5%@R28 0_0402_5%@
1 2
R30 0_0402_5%@R30 0_0402_5%@
1 2
R32 0_0402_5%@R32 0_0402_5%@
1 2
R34 0_0402_5%@R34 0_0402_5%@
1 2
Close to CPU side
+5VS
1A
1 2
R49
R49 330_0402_5%
330_0402_5%
12
2
XDP_PRDY# XDP_PREQ#
XDP_TCK XDP_TMS XDP_TRST#
XDP_TDI XDP_TDO
XDP_DBRESET#
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3
U2
U2
1
EN
GND
2
VIN
GND
3
VOUT
GND
4
VSET
GND
G996P11U SOP 8P
G996P11U SOP 8P
C7
C7
0.047U_0402_16V7K
0.047U_0402_16V7K
Routed as a single daisy chain
R20
R20
1 2
1K_0402_5%
1K_0402_5%
CFG12 <10> CFG13 <10> CFG14 <10> CFG15 <10>
+3VS
XDP_DBRESET# <29,31>
PU/PD for JTAG signals
XDP_TMS_R
XDP_TDI_R
XDP_TDO_R
XDP_TCK_R
XDP_TRST#_R
R39 51_0402_5%R39 51_0402_5%
R40 51_0402_5%R40 51_0402_5%
R41 51_0402_5%R41 51_0402_5%
R42 51_0402_5%R42 51_0402_5%
R43 51_0402_5%R43 51_0402_5%
FAN Control Circuit
2
C4
C4
10U_0805_10V4Z
10U_0805_10V4Z
1
2
C5
8 7 6 5
C5
@
@
1
Title
Title
Title
Sandy Bridge(1/6)-CLK/MISC/JTAG/XDP/FAN
Sandy Bridge(1/6)-CLK/MISC/JTAG/XDP/FAN
Sandy Bridge(1/6)-CLK/MISC/JTAG/XDP/FAN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
20mil
+FAN_VCC
1000P_0402_50V7K
1000P_0402_50V7K
1
C9
0.01U_0402_25V7K
0.01U_0402_25V7K
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
+1.05VS_VCCP
12
12
12
12
12
JFAN
JFAN
1
1
2
2
3
3
4
GND
5
GND
CVILU_CI4403M1HRT-NH
CVILU_CI4403M1HRT-NH
@
@
R51 10K_0402_5%R51 10K_0402_5%
12
FAN_SPEED1 <43>
@C9
@
5 58Friday, January 21, 2011
5 58Friday, January 21, 2011
5 58Friday, January 21, 2011
+3VS
0.1
0.1
0.1
5
4
3
2
1
+1.05VS_VCCP
D D
24.9_0402_1%
JCPUA
JCPUA
DMI_PTX_CRX_N0<31> DMI_PTX_CRX_N1<31> DMI_PTX_CRX_N2<31> DMI_PTX_CRX_N3<31>
DMI_PTX_CRX_P0<31> DMI_PTX_CRX_P1<31> DMI_PTX_CRX_P2<31> DMI_PTX_CRX_P3<31>
DMI_CTX_PRX_N0<31> DMI_CTX_PRX_N1<31> DMI_CTX_PRX_N2<31> DMI_CTX_PRX_N3<31>
DMI_CTX_PRX_P0<31> DMI_CTX_PRX_P1<31> DMI_CTX_PRX_P2<31> DMI_CTX_PRX_P3<31>
FDI_CTX_PRX_N0<31>
C C
+1.05VS_VCCP
12
R56
R56
24.9_0402_1%
24.9_0402_1%
B B
FDI_CTX_PRX_N1<31> FDI_CTX_PRX_N2<31> FDI_CTX_PRX_N3<31> FDI_CTX_PRX_N4<31> FDI_CTX_PRX_N5<31> FDI_CTX_PRX_N6<31> FDI_CTX_PRX_N7<31>
FDI_CTX_PRX_P0<31> FDI_CTX_PRX_P1<31> FDI_CTX_PRX_P2<31> FDI_CTX_PRX_P3<31> FDI_CTX_PRX_P4<31> FDI_CTX_PRX_P5<31> FDI_CTX_PRX_P6<31> FDI_CTX_PRX_P7<31>
FDI_FSYNC0<31> FDI_FSYNC1<31>
FDI_INT<31>
FDI_LSYNC0<31> FDI_LSYNC1<31>
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
FDI_FSYNC0 FDI_FSYNC1
FDI_INT
FDI_LSYNC0 FDI_LSYNC1
EDP_COMP
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]
PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]
PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]
PEG_TX#[10] PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
J22 J21 H22
PCIE_GTX_C_CRX_N15
K33
PCIE_GTX_C_CRX_N14
M35
PCIE_GTX_C_CRX_N13
L34
PCIE_GTX_C_CRX_N12
J35
PCIE_GTX_C_CRX_N11
J32
PCIE_GTX_C_CRX_N10
H34
PCIE_GTX_C_CRX_N9
H31
PCIE_GTX_C_CRX_N8
G33
PCIE_GTX_C_CRX_N7
G30
PCIE_GTX_C_CRX_N6
F35
PCIE_GTX_C_CRX_N5
E34
PCIE_GTX_C_CRX_N4
E32
PCIE_GTX_C_CRX_N3
D33
PCIE_GTX_C_CRX_N2
D31
PCIE_GTX_C_CRX_N1
B33
PCIE_GTX_C_CRX_N0
C32
PCIE_GTX_C_CRX_P15
J33
PCIE_GTX_C_CRX_P14
L35
PCIE_GTX_C_CRX_P13
K34
PCIE_GTX_C_CRX_P12
H35
PCIE_GTX_C_CRX_P11
H32
PCIE_GTX_C_CRX_P10
G34
PCIE_GTX_C_CRX_P9
G31
PCIE_GTX_C_CRX_P8
F33
PCIE_GTX_C_CRX_P7
F30
PCIE_GTX_C_CRX_P6
E35
PCIE_GTX_C_CRX_P5
E33
PCIE_GTX_C_CRX_P4
F32
PCIE_GTX_C_CRX_P3
D34
PCIE_GTX_C_CRX_P2
E31
PCIE_GTX_C_CRX_P1
C33
PCIE_GTX_C_CRX_P0
B32
PCIE_CTX_GRX_N15
M29
PCIE_CTX_GRX_N14
M32
PCIE_CTX_GRX_N13
M31
PCIE_CTX_GRX_N12
L32
PCIE_CTX_GRX_N11
L29
PCIE_CTX_GRX_N10
K31
PCIE_CTX_GRX_N9
K28
PCIE_CTX_GRX_N8
J30
PCIE_CTX_GRX_N7
J28
PCIE_CTX_GRX_N6
H29
PCIE_CTX_GRX_N5
G27
PCIE_CTX_GRX_N4
E29
PCIE_CTX_GRX_N3
F27
PCIE_CTX_GRX_N2
D28
PCIE_CTX_GRX_N1
F26
PCIE_CTX_GRX_N0
E25
PCIE_CTX_GRX_P15
M28
PCIE_CTX_GRX_P14
M33
PCIE_CTX_GRX_P13
M30
PCIE_CTX_GRX_P12
L31
PCIE_CTX_GRX_P11
L28
PCIE_CTX_GRX_P10
K30
PCIE_CTX_GRX_P9
K27
PCIE_CTX_GRX_P8
J29
PCIE_CTX_GRX_P7
J27
PCIE_CTX_GRX_P6
H28
PCIE_CTX_GRX_P5
G28
PCIE_CTX_GRX_P4
E28
PCIE_CTX_GRX_P3
F28
PCIE_CTX_GRX_P2
D27
PCIE_CTX_GRX_P1
E26
PCIE_CTX_GRX_P0
D25
PEG_COMP
24.9_0402_1%
Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)
12
R54
R54
C10 0.22U_0402_10V6KC10 0.22U_0402_10V6K C11 0.22U_0402_10V6KC11 0.22U_0402_10V6K C12 0.22U_0402_10V6KC12 0.22U_0402_10V6K C13 0.22U_0402_10V6KC13 0.22U_0402_10V6K C14 0.22U_0402_10V6KC14 0.22U_0402_10V6K C15 0.22U_0402_10V6KC15 0.22U_0402_10V6K C16 0.22U_0402_10V6KC16 0.22U_0402_10V6K C17 0.22U_0402_10V6KC17 0.22U_0402_10V6K C18 0.22U_0402_10V6KC18 0.22U_0402_10V6K C19 0.22U_0402_10V6KC19 0.22U_0402_10V6K C20 0.22U_0402_10V6KC20 0.22U_0402_10V6K C21 0.22U_0402_10V6KC21 0.22U_0402_10V6K C22 0.22U_0402_10V6KC22 0.22U_0402_10V6K C23 0.22U_0402_10V6KC23 0.22U_0402_10V6K C24 0.22U_0402_10V6KC24 0.22U_0402_10V6K C25 0.22U_0402_10V6KC25 0.22U_0402_10V6K
C26 0.22U_0402_10V6KC26 0.22U_0402_10V6K C27 0.22U_0402_10V6KC27 0.22U_0402_10V6K C28 0.22U_0402_10V6KC28 0.22U_0402_10V6K C29 0.22U_0402_10V6KC29 0.22U_0402_10V6K C30 0.22U_0402_10V6KC30 0.22U_0402_10V6K C31 0.22U_0402_10V6KC31 0.22U_0402_10V6K C32 0.22U_0402_10V6KC32 0.22U_0402_10V6K C33 0.22U_0402_10V6KC33 0.22U_0402_10V6K C34 0.22U_0402_10V6KC34 0.22U_0402_10V6K C35 0.22U_0402_10V6KC35 0.22U_0402_10V6K C36 0.22U_0402_10V6KC36 0.22U_0402_10V6K C37 0.22U_0402_10V6KC37 0.22U_0402_10V6K C38 0.22U_0402_10V6KC38 0.22U_0402_10V6K C39 0.22U_0402_10V6KC39 0.22U_0402_10V6K C40 0.22U_0402_10V6KC40 0.22U_0402_10V6K C41 0.22U_0402_10V6KC41 0.22U_0402_10V6K
PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with ­max length = 500 mils
- typical impedance = 14.5 mohms
PCIE_GTX_C_CRX_N[0..15] <14>
PCIE_GTX_C_CRX_P[0..15] <14>
PAY ATTENTION ON PCIE SWAP WHEN REVIEW
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PCIE_CTX_C_GRX_N15 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N[0..15] <14>
PCIE_CTX_C_GRX_P[0..15] <14>
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge(2/6)-DMI/FDI/PEG/eDP
Sandy Bridge(2/6)-DMI/FDI/PEG/eDP
Sandy Bridge(2/6)-DMI/FDI/PEG/eDP
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
6 58Friday, January 21, 2011
6 58Friday, January 21, 2011
6 58Friday, January 21, 2011
0.1
0.1
0.1
5
JCPUC
AP11 AN11
AL12 AM12 AM11
AL11 AP12 AN12
AJ14 AH14
AL15 AK15
AL14 AK14
AJ15 AH15
AE10
AF10
G10
N10
M10
AG6 AG5 AK6 AK5 AH5 AH6
AK8
AK9 AH8 AH9 AL9 AL8
AE8 AD9 AF9
F10
AJ5 AJ6 AJ8
AJ9
C5 D5 D3 D2 D6 C6 C2 C3
F8
G9 F9 F7 G8 G7 K4 K5 K1
J1 J5 J4 J2
K2
M8
N8 N7
M9 N9 M7
V6
JCPUC
SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
SA_BS[0] SA_BS[1] SA_BS[2]
SA_CAS# SA_RAS# SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
DDR_A_D[0..63]<12>
DDR_A_D0 DDR_A_D1 DDR_A_D2
D D
C C
B B
DDR_A_BS0<12> DDR_A_BS1<12> DDR_A_BS2<12>
DDR_A_CAS#<12> DDR_A_RAS#<12>
DDR_A_WE#<12>
DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]
SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]
SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]
SA_ODT[0]
SA_ODT[1] SA_ODT[2] SA_ODT[3]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]
SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
4
DDR_B_D[0..63]<13>
AB6 AA6 V9
AA5 AB5 V10
AB4 AA4 W9
AB3 AA3 W10
AK3 AL3 AG1 AH1
AH3 AG3 AG2 AH2
C4 G6 J3 M6 AL6 AM8 AR12 AM15
D4 F6 K3 N6 AL5 AM9 AR11 AM14
AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8
DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDRA_CLK0 <12> DDRB_CLK0 <13> DDRA_CLK0# <12> DDRA_CKE0 <12> DDRB_CKE0 <13>
DDRA_CLK1 <12> DDRA_CLK1# <12> DDRB_CLK1# <13> DDRA_CKE1 <12>
DDRA_CLK2 <12> DDRA_CLK2# <12> DDRA_CKE2 <12>
DDRA_CLK3 <12> DDRA_CLK3# <12> DDRA_CKE3 <12>
DDRA_SCS0# <12> DDRA_SCS1# <12> DDRB_SCS1# <13> DDRA_SCS2# <12> DDRA_SCS3# <12>
DDRA_ODT0 <12> DDRB_ODT0 <13> DDRA_ODT1 <12> DDRB_ODT1 <13> DDRA_ODT2 <12> DDRA_ODT3 <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
DDR_A_MA[0..15] <12>
DDR_B_CAS#<13> DDR_B_RAS#<13>
DDR_B_WE#<13>
3
JCPUD
JCPUD
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_BS0<13> DDR_B_BS1<13> DDR_B_BS2<13>
AM5 AM6 AR3
AN3 AN2 AN1
AN9
AN8 AR6 AR5 AR9
AJ11
AH11
AR8
AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15
AA10
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34]
AP3
SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40] SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
2
AE2
SB_CLK[0]
AD2
SB_CLK#[0]
R9
SB_CKE[0]
AE1
SB_CLK[1]
AD1
SB_CLK#[1]
R10
SB_CKE[1]
AB2
SB_CLK[2]
AA2
SB_CLK#[2]
T9
SB_CKE[2]
AA1
SB_CLK[3]
AB1
SB_CLK#[3]
T10
SB_CKE[3]
AD3
SB_CS#[0]
AE3
SB_CS#[1]
AD6
SB_CS#[2]
AE6
SB_CS#[3]
AE4
SB_ODT[0]
AD4
SB_ODT[1]
AD5
SB_ODT[2]
AE5
SB_ODT[3]
DDR_B_DQS#0
D7
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_DQS[7]
SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]
SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
F3 K6 N3 AN5 AP9 AK12 AP15
C7 G3 J6 M3 AN6 AP8 AK11 AP14
AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4
DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8
DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDRB_CLK0# <13>
DDRB_CLK1 <13>
DDRB_CKE1 <13>
DDRB_CLK2 <13> DDRB_CLK2# <13> DDRB_CKE2 <13>
DDRB_CLK3 <13> DDRB_CLK3# <13> DDRB_CKE3 <13>
DDRB_SCS0# <13>
DDRB_SCS2# <13> DDRB_SCS3# <13>
DDRB_ODT2 <13> DDRB_ODT3 <13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
DDR_B_MA[0..15] <13>
1
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
R59
@R59
@
0_0402_5%
0_0402_5%
1 2
S
H_DRAMRST#<5>
A A
DRAMRST_CNTRL_PCH<30>
5
4.99K_0402_1%
4.99K_0402_1%
R63
R63
0_0402_5%
0_0402_5%
1 2
DRAMRST_CNTRL
S
G
G
R62
R62
2
1 2
1
2
CONN@
CONN@
D
D
DDR3_DRAMRST#_RH_DRAMRST#
13
Q2
Q2 BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
C42
C42
0.047U_0402_16V4Z
0.047U_0402_16V4Z
+1.5V
R60
R60
1K_0402_5%
1K_0402_5%
12
R61
R61 1K_0402_5%
1K_0402_5%
1 2
WHY ADD THE IK SERISE RESISTOR?
4
SM_DRAMRST# <12,13>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
Compal Secret Data
Compal Secret Data
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge(3/6)-DDR III
Sandy Bridge(3/6)-DDR III
Sandy Bridge(3/6)-DDR III
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
7 58Friday, January 21, 2011
7 58Friday, January 21, 2011
7 58Friday, January 21, 2011
0.1
0.1
0.1
5
4
3
2
1
+CPU_CORE
JCPUF
JCPUF
POWER
POWER
94A 18A
D D
C C
B B
A A
5
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
CORE SUPPLY
CORE SUPPLY
SENSE LINES SVID
SENSE LINES SVID
4
AH13
VCCIO1
AH10
VCCIO2
AG10
VCCIO3
AC10
VCCIO4
Y10
VCCIO5
U10
VCCIO6
P10
VCCIO7
L10
VCCIO8
J14
VCCIO9
J13
VCCIO10
J12
VCCIO11
J11
VCCIO12
H14
VCCIO13
H12
VCCIO14
H11
VCCIO15
G14
VCCIO16
G13
VCCIO17
G12
VCCIO18
F14
VCCIO19
F13
VCCIO20
F12
VCCIO21
F11
VCCIO22
E14
VCCIO23
E12
VCCIO24
E11
VCCIO25
D14
VCCIO26
D13
VCCIO27
D12
VCCIO28
D11
VCCIO29
C14
VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39
VCCIO40
VIDALERT#
VIDSCLK VIDSOUT
C13 C12 C11 B14 B12 A14 A13 A12 A11
J23
AJ29 AJ30 AJ28
AJ35 AJ34
B10 A10
VCCSENSE_R VSSSENSE_R
H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT
PEG AND DDR
PEG AND DDR
VCC_SENSE VSS_SENSE
VCCIO_SENSE VSSIO_SENSE
Material Note (+1.05VS_VCCP)
2 x 330 µF (3x 330 µF for 2012 capable designs) Top Socket Cavity 22U 0805 *7 Bottom Socket Cavity 22U 0805 *5
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
1
2
C44
C44
C43
C43
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C53
C53
C54
C54
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
C46
C46
C45
C45
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
C48
C48
C47
C47
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
C50
C50
C49
C49
2
330U_D2_2V_Y
330U_D2_2V_Y
1
1
C62
C62
+
+
2
2
Cap quantity follow 439028_HR_PDDG_R1_51
+1.05VS_VCCP+1.05VS_VCCP
12
R65
R65 130_0402_5%
130_0402_5%
R67
R67
43_0402_1%
43_0402_1%
1 2
R68 0_0402_5%R68 0_0402_5%
1 2
R69 0_0402_5%R69 0_0402_5%
1 2
Close to CPU
VCCSENSE
VSSSENSE
1 2
R70 100_0402_1%R70 100_0402_1%
1 2
R71 100_0402_1%R71 100_0402_1%
0_0402_5%
0_0402_5%
R72
R72
1 2 1 2
R73 0_0402_5%R73 0_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VCCSENSE VSSSENSE
VCCIO_SENSE <52>
3
12
R66
R66 75_0402_5%
75_0402_5%
VR_SVID_ALRT# <55> VR_SVID_CLK <55> VR_SVID_DAT <55>
Resistors close to CPU
+CPU_CORE
VCCSENSE <55> VSSSENSE <55>
R74
R74
1 2
10_0402_5%
10_0402_5%
Compal Secret Data
Compal Secret Data
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+1.05VS_VCCP
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
C51
C51
C52
C52
2
2
330U_D2_2V_Y
330U_D2_2V_Y
1
C63
C63
+
+
+
C64
@+C64
@
330U_D2_2V_Y
330U_D2_2V_Y
2
2
+1.05VS_VCCP
1
C83
C83
+
+
330U_2.5V_M_R17@
330U_2.5V_M_R17@
2
reserve for test please co-layout with C62,C63
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
C73
C73
+
+
330U_2.5V_M_R17@
330U_2.5V_M_R17@
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Sandy Bridge(4/6)-PWR
Sandy Bridge(4/6)-PWR
Sandy Bridge(4/6)-PWR
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
8 58Friday, January 21, 2011
8 58Friday, January 21, 2011
8 58Friday, January 21, 2011
0.1
0.1
0.1
Group1
5
4
3
2
1
Material Note (GFXCORE)
2 x 330 µF on Bottom socket edge
+GFX_CORE
D D
C C
B B
Material Note (+1.8VS_VCCPLL)
1 x 330 µF Bottom Socket Edge 1U 0402 *1 10U 0805 *1
Bottom Socket Cavity 22U 0805 *2 Bottom Socket Edge 22U 0805 *4 Top Socket Cavity 22U 0805 *2 Top Socket Edge 22U 0805 *4
C217
330U_D2_2V_Y+C217
330U_D2_2V_Y
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
C79
330U_D2_2V_Y
C79
330U_D2_2V_Y
@
@
C414
C414
C412
C412
1
2
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C285
C285
C284
C284
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C364
C364
C365
C365
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.8VS
R124
R124
0_0805_5%
0_0805_5%
1 2
1
+
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C286
C286
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C410
C410
2
1
+
+
2
C225
330U_D2_2V_Y+C225
330U_D2_2V_Y
+
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C415
C415
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C411
C411
2
C80
C80
1
2
1
C416
C416
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C413
C413
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.8VS_VCCPLL
C81
1U_0402_6.3V6K
C81
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
POWER
JCPUG
JCPUG
26A
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
VAXG13
AP23
VAXG14
AP21
1
2
1
2
C82
C82
VAXG15
AP20
VAXG16
AP18
VAXG17
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
AN18
VAXG23
AN17
VAXG24
AM24
VAXG25
AM23
VAXG26
AM21
VAXG27
AM20
VAXG28
AM18
VAXG29
AM17
VAXG30
AL24
VAXG31
AL23
VAXG32
AL21
VAXG33
AL20
VAXG34
AL18
VAXG35
AL17
VAXG36
AK24
VAXG37
AK23
VAXG38
AK21
VAXG39
AK20
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48
AH24
VAXG49
AH23
VAXG50
AH21
VAXG51
AH20
VAXG52
AH18
VAXG53
AH17
VAXG54
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
POWER
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
Group2
SM_VREF
5A
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15
6A
VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8
FC_C22
AK35 AK34
AL1
AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1
M27 M26 L26 J26 J25 J24 H26 H25
H23
C22 C24
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID1
1 2
100_0402_1%
100_0402_1%
R129
R129
1 2
100_0402_1%
100_0402_1%
+V_SM_VREF_CNT +V_SM_VREF
1
C65
C65
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VCCSA
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C74
C74
2
H_FC_C22
1 2
R131
R131
0_0402_5%
0_0402_5%
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C66
C66
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C75
C75
2
R79
R79 10K_0402_5%
10K_0402_5%
+GFX_CORE
VCC_AXG_SENSE <55> VSS_AXG_SENSE <55>
R76
R76
12
3
@
@
Q3
Q3
1
AP2302GN-HF_SOT23-3
AP2302GN-HF_SOT23-3
RUN_ON_CPU1.5VS3
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
C68
C68
C67
C67
2
2
+VCCSA
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C76
C76
2
12
R80
@R80
@
0_0402_5%
0_0402_5%
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
1 2
330U_D2_2V_Y+C78
330U_D2_2V_Y
1
+
2
R78
R78 0_0402_5%
0_0402_5%
+1.5V_CPU
12
R75
R75 1K_0402_1%
1K_0402_1%
12
R77
R77 1K_0402_1%
1K_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C69
C69
C70
C70
2
C78
VCCSA_SENSE <54>
VCCSA_SEL <54>
+1.5V_CPU
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
C71
C71
2
2
VCCSA_SENSE
Follow DG V1.5 P.109
+V_SM_VREF should have 20 mil trace width
JP1
@ JP1
@
2
+1.5V
Material Note (VDDQ)
Bottom Socket Edge 1 x 330 µF 10U 0805 *6
+
+
330U_D2_2V_Y
330U_D2_2V_Y
C72
C72
112
JUMP_43X118
JUMP_43X118
Material Note (VCCSA)
1 x 330 µF Bottom Socket Cavity 10U 0805 *2 Bottom Socket Edge 10U 0805 *1
+1.5V_CPU Source
+1.5V +1.5V_CPU
+VSB
+3VALW
12
R83
R83 100K_0402_5%
A A
CPU1.5V_S3_GATE<43>
SUSP#<43,46,50,52,54,57,58>
R84
R84
0_0402_5%
0_0402_5%
1 2
R86
@R86
@
0_0402_5%
0_0402_5%
1 2
5
100K_0402_5%
RUN_ON_CPU1.5VS3#
61
Q35A
Q35A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
12
R81
R81 100K_0402_5%
100K_0402_5%
RUN_ON_CPU1.5VS3
3
Q35B
Q35B 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
5
4
R85
R85
330K_0402_5%
330K_0402_5%
4
Q4
Q4 SI4634DY-T1-GE3_SO8
SI4634DY-T1-GE3_SO8
8 7 6 5
4
12
1
2
1 2 3
C86
C86
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R82
R82 470_0603_5%
470_0603_5%
1 2
13
D
D
S
S
G
G
RUN_ON_CPU1.5VS3#
2
Q6
Q6 2N7002H 1N SOT23-3
2N7002H 1N SOT23-3
Security Classification
Security Classification
Security Classification
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
Compal Secret Data
Compal Secret Data
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Sandy Bridge(4/6)-PWR
Sandy Bridge(4/6)-PWR
Sandy Bridge(4/6)-PWR
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
9 58Friday, January 21, 2011
9 58Friday, January 21, 2011
9 58Friday, January 21, 2011
0.1
0.1
0.1
5
4
3
2
1
CFG Straps for Processor
CFG2
D D
JCPUE
JCPUE
L7
RSVD28
AG7
RSVD29 RSVD30 RSVD31 RSVD32
RSVD33 RSVD34 RSVD35
RSVD37 RSVD38 RSVD39 RSVD40
RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
RSVD46 RSVD47 RSVD48 RSVD49 RSVD50
RSVD51 RSVD52
RSVD53
RSVD54 RSVD55
RSVD56 RSVD57 RSVD58
KEY
AE7 AK2 W8
AT26 AM33 AJ27
T8 J16 H16 G16
AR35 AT34 AT33 AP35 AR34
B34 A33 A34 B35 C35
AJ32 AK32
AH27
AN35 AM35
AT2 AT1 AR1
B1
T20PAD@ T20PAD@
CLK_RES_ITP <5,30> CLK_RES_ITP# <5,30>
T16 PAD @T16 PAD @ T17 PAD @T17 PAD @ T18 PAD @T18 PAD @ T19 PAD @T19 PAD @
CPU_RSVD6 CPU_RSVD7
12
12
R90
R90
1K_0402_1%
1K_0402_1%
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17
CFG0<5>
CFG12<5> CFG13<5> CFG14<5> CFG15<5>
C C
B B
T4 PAD @T4 PAD @ T5 PAD @T5 PAD @ T6 PAD @T6 PAD @ T7 PAD @T7 PAD @ T3 PAD @T3 PAD @ T8 PAD @T8 PAD @ T9 PAD @T9 PAD @ T10 PAD @T10 PAD @ T11 PAD @T11 PAD @ T12 PAD @T12 PAD @ T13 PAD @T13 PAD @
T14 PAD @T14 PAD @ T15 PAD @T15 PAD @
R89
R89
1K_0402_1%
1K_0402_1%
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
RSVD1
AH31
RSVD2
AJ33
RSVD3
AH33
RSVD4
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
RSVD26
J15
RSVD27
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
RESERVED
RESERVED
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
*
Display Port Presence Strap
CFG4
*
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
12
R87
R87 1K_0402_1%
1K_0402_1%
1: Normal Operation; Lane # definition matches socket pin map definition
0:Lane Reversed
CFG4
1K_0402_1%
1K_0402_1%
12
@
@
R88
R88 1K_0402_1%
1K_0402_1%
1 : Disabled; No Physical Display Port attached to Embedded Display Port
0 : Enabled; An external Display Port device is connected to the Embedded Display Port
CFG6
CFG5
CFG7
@R91
@
12
12
R92
@R92
12
@R93
@
@
1K_0402_1%
1K_0402_1%
R93 1K_0402_1%
1K_0402_1%
R91
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7
de assertion
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0: PEG Wait for BIOS for training
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge(5/6) Reserve
Sandy Bridge(5/6) Reserve
Sandy Bridge(5/6) Reserve
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
0.1
0.1
10 58Friday, January 21, 2011
10 58Friday, January 21, 2011
10 58Friday, January 21, 2011
0.1
5
4
3
2
1
Material Note (+CPU_CORE)
4 x 330 µF Top Socket Cavity 22U 0805 *8
JCPUI
JCPUH
JCPUH
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
D D
C C
B B
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
VSS
VSS
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2
JCPUI
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
VSS
VSS
VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285
F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3
Top Socket Edge 22U 0805 *8 Bottom Socket Cavity 10U 0805 *10
+CPU_CORE
C87
10U_0805_10V7M
C87
+CPU_CORE
+CPU_CORE
10U_0805_10V7M
1
2
1
2
1
2
1
2
1
2
1
+
+
@
@
2
1
2
C92
10U_0805_10V7M
C92
10U_0805_10V7M
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
C98
22U_0805_6.3V6M
C98
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
C103
22U_0805_6.3V6M
C103
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
C108
22U_0805_6.3V6M
C108
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
330U_D2_2V_Y+C117
330U_D2_2V_Y
C219
330U_D2_2V_Y
C219
330U_D2_2V_Y
1
+
2
10U_0805_10V7M
10U_0805_10V7M
C88
10U_0805_10V7M
C88
10U_0805_10V7M
1
2
10U_0805_10V7M
10U_0805_10V7M
C93
10U_0805_10V7M
C93
10U_0805_10V7M
1
2
C99
C99
C100
22U_0805_6.3V6M
C100
22U_0805_6.3V6M
1
2
C104
C104
C105
22U_0805_6.3V6M
C105
22U_0805_6.3V6M
1
2
C110
22U_0805_6.3V6M
C110
22U_0805_6.3V6M
C109
C109
1
2
C113
C113
C117
C118
330U_D2_2V_Y+C118
330U_D2_2V_Y
1
+
2
C90
10U_0805_10V7M
C90
10U_0805_10V7M
C89
C89
1
2
10U_0805_10V7M
10U_0805_10V7M
C94
C94
1
2
C101
22U_0805_6.3V6M
C101
22U_0805_6.3V6M
1
2
C106
22U_0805_6.3V6M
C106
22U_0805_6.3V6M
1
2
C111
22U_0805_6.3V6M
C111
22U_0805_6.3V6M
1
2
C119
330U_D2_2V_Y+C119
330U_D2_2V_Y
1
+
2
C91
10U_0805_10V7M
C91
10U_0805_10V7M
1
2
C95
C95
C96
10U_0805_10V7M
C96
10U_0805_10V7M
1
2
C102
22U_0805_6.3V6M
C102
22U_0805_6.3V6M
1
2
C107
22U_0805_6.3V6M
C107
22U_0805_6.3V6M
1
2
C112
22U_0805_6.3V6M
C112
22U_0805_6.3V6M
1
2
C120
330U_D2_2V_Y+C120
330U_D2_2V_Y
1
+
2
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet
Compal Electronics, Inc.
Sandy Bridge(6/6)-GND
Sandy Bridge(6/6)-GND
Sandy Bridge(6/6)-GND
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
11 58Friday, January 21, 2011
11 58Friday, January 21, 2011
11 58Friday, January 21, 2011
0.1
0.1
0.1
of
5
+1.5V
1K_0402_1%
1K_0402_1%
12
R94
R94
+VREFA_DQ
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K C121
C121
C127
1K_0402_1%
1K_0402_1%
D D
C C
B B
Layout Note: Place near JDIMMA1.203,204
+0.75VS
A A
C127
1
1
12
R95
R95
1
2
2
2
DDRA_CKE0<7>
DDR_A_BS2<7>
DDRA_CLK0<7> DDRA_CLK0#<7>
DDR_A_BS0<7>
DDR_A_WE#<7> DDR_A_CAS#<7>
DDRA_SCS1#<7>
C135
1U_0402_6.3V6K
C135
1U_0402_6.3V6K
C136
1U_0402_6.3V6K
C136
1U_0402_6.3V6K
1
2
+3VS
1
2
5
+VREFA_DQ
DDR_A_D0 DDR_A_D1
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_D26 DDR_A_D27
DDRA_CKE0
DDR_A_BS2
DDR_A_MA12 DDR_A_MA9
DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1
DDRA_CLK0 DDRA_CLK0#
DDR_A_MA10 DDR_A_BS0
DDR_A_WE# DDR_A_CAS# DDRA_ODT0
DDR_A_MA13 DDRA_SCS1#
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_D42 DDR_A_D43
DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_D58 DDR_A_D59
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
C143
C143
C144
C144
1
2
+1.5V +1.5V
R99
10K_0402_5%
R99
10K_0402_5%
R100
10K_0402_5%
R100
10K_0402_5%
12
12
3A@1.5V
3A@1.5V
3A@1.5V3A@1.5V
JDDR1
JDDR1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1
TYCO_2-2013289-1
@
@
Standard:5.2mm <Address: SA1:SA0=00> BOT
DQ4 DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7 VSS8 DQ12 DQ13
VSS10
DM1
DQ14 DQ15
DQ20 DQ21
DM2
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
DQ30 DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1 CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35 DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47 DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA
SCL VTT2
4
Support SO DIMM X 4
2
DDR_A_D4
4
DDR_A_D5
6 8
DDR_A_DQS#0
10
DDR_A_DQS0
12 14
DDR_A_D6
16
DDR_A_D7
18 20
DDR_A_D12
22
DDR_A_D13
24 26 28
SM_DRAMRST#
30 32
DDR_A_D14
34
DDR_A_D15
36 38
DDR_A_D20
40
DDR_A_D21
42 44 46 48
DDR_A_D22
50
DDR_A_D23
52 54
DDR_A_D28
56
DDR_A_D29
58 60
DDR_A_DQS#3
62
DDR_A_DQS3
64 66
DDR_A_D30
68
DDR_A_D31
70 72
DDRA_CKE1
74 76
DDR_A_MA15
78
A15 A14
A11
A7
A6 A4
A2 A0
BA1
S0#
G2
DDR_A_MA14
80 82
DDR_A_MA11
84
DDR_A_MA7
86 88
DDR_A_MA6
90
DDR_A_MA4
92 94
DDR_A_MA2
96
DDR_A_MA0
98 100
DDRA_CLK1
102
DDRA_CLK1#
104 106
DDR_A_BS1
108
DDR_A_RAS#
110 112
DDRA_SCS0#
114 116 118
DDRA_ODT1
120 122 124
+VREF_CA
126 128
DDR_A_D36
130
DDR_A_D37
132 134 136 138
DDR_A_D38
140
DDR_A_D39
142 144
DDR_A_D44
146
DDR_A_D45
148 150
DDR_A_DQS#5
152
DDR_A_DQS5
154 156
DDR_A_D46
158
DDR_A_D47
160 162
DDR_A_D52
164
DDR_A_D53
166 168 170 172
DDR_A_D54
174
DDR_A_D55
176 178
DDR_A_D60
180
DDR_A_D61
182 184
DDR_A_DQS#7
186
DDR_A_DQS7
188 190
DDR_A_D62
192
DDR_A_D63
194 196 198
PM_SMBDATA
200
PM_SMBCLK
202 204
206
4
+0.75VS
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
Support 1066/1333MHz
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_DQS#[0..7]<7>
DDR_A_MA[0..15]<7>
SM_DRAMRST# <7,13>
Layout Note: Place near JDIMMA
+1.5V
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
10U_0603_6.3V6M
10U_0603_6.3V6M
C128
C128
C122
C122
1
1
+
+
2
2
DDRA_CKE1 <7>
DDRA_CLK1 <7> DDRA_CLK1# <7>
DDR_A_BS1 <7> DDR_A_RAS# <7>
DDRA_SCS0# <7> DDRA_ODT0 <7>
DDRA_ODT1 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C131
C131
C132
1
2
PM_SMBDATA <13,30,39> PM_SMBCLK <13,30,39>
C132
1
2
Layout Note: Place these 4 Caps near Command and Control signals of JDIMMA
+1.5V
3
+VREFA_DQ
DDR_A_D0 DDR_A_D1
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D17
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C129
C129
1
2
+1.5V
12
R96
R96 1K_0402_1%
1K_0402_1%
12
R97
R97 1K_0402_1%
1K_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K C137
C137
1
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10U_0603_6.3V6M
C123
C123
C124
C124
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K C138
C138
1
1
2
2
3
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C125
C125
1
2
C139
C139
C130
47P_0402_50V8J
C130
47P_0402_50V8J
C126
C126
1
12
2
DDRA_CKE2<7>
DDRA_CLK2<7> DDRA_CLK2#<7>
DDRA_SCS3#<7>
0.1U_0402_10V6K
0.1U_0402_10V6K C140
C140
1
2
+3VS
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
C145
C145
2
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_D26 DDR_A_D27
DDRA_CKE2
DDR_A_BS2
DDR_A_MA12 DDR_A_MA9
DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1
DDRA_CLK2 DDRA_CLK2#
DDR_A_MA10 DDR_A_BS0
DDR_A_WE# DDR_A_CAS# DDRA_ODT2
DDR_A_MA13 DDRA_SCS3#
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_D42 DDR_A_D43
DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_D58 DDR_A_D59
1 2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C146
C146
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+1.5V +1.5V
R9810K_0402_5% R9810K_0402_5%
R101
10K_0402_5%
R101
10K_0402_5%
12
3 5 7
9 11 13 15 17 19 21 23 25 27
33 35
39 41
45 47 49 51 53 55 57 59
63
67 69
73 75 77 79 81 83 85 87 89 91 93 95 97 99
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
205
2
3A@1.5V
3A@1.5V
3A@1.5V3A@1.5V
JDDR2
JDDR2
VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
G1
TYCO_2-2013287-1
TYCO_2-2013287-1
@
@
VSS3
DQS#0
DQS0 VSS6
VSS8 DQ12 DQ13
VSS10
DQ14 DQ15
DQ20 DQ21
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
DQ30 DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
VSS31
DQ38 DQ39
VSS33
DQ44
DQ45 VSS35 DQS#5
DQS5 VSS38
DQ46
DQ47 VSS40
DQ52
DQ53 VSS42
VSS43
DQ54
DQ55 VSS45
DQ60
DQ61 VSS47 DQS#7
DQS7 VSS50
DQ62
DQ63 VSS52
EVENT#
VTT2
1
2
DDR_A_D4
4
DQ4 DQ5
DQ6 DQ7
DM1
DM2
CK1
BA1
NC2
DM4
DM6
SDA SCL
A15 A14
A11
A7
A6 A4
A2 A0
S0#
G2
DDR_A_D5
6 8
DDR_A_DQS#0
10
DDR_A_DQS0
12 14
DDR_A_D6
16
DDR_A_D7
18 20
DDR_A_D12
22
DDR_A_D13
24 26 28
SM_DRAMRST#
30 32
DDR_A_D14
34
DDR_A_D15
36 38
DDR_A_D20
40
DDR_A_D21
42 44 46 48
DDR_A_D22
50
DDR_A_D23
52 54
DDR_A_D28
56
DDR_A_D29
58 60
DDR_A_DQS#3
62
DDR_A_DQS3
64 66
DDR_A_D30
68
DDR_A_D31
70 72
DDRA_CKE3
74 76
DDR_A_MA15
78
DDR_A_MA14
80 82
DDR_A_MA11
84
DDR_A_MA7
86 88
DDR_A_MA6
90
DDR_A_MA4
92 94
DDR_A_MA2
96
DDR_A_MA0
98 100
DDRA_CLK3
102
DDRA_CLK3#
104 106
DDR_A_BS1
108
DDR_A_RAS#
110 112
DDRA_SCS2#
114 116 118
DDRA_ODT3
120 122 124 126 128
DDR_A_D36
130
DDR_A_D37
132 134 136 138
DDR_A_D38
140
DDR_A_D39
142 144
DDR_A_D44
146
DDR_A_D45
148 150
DDR_A_DQS#5
152
DDR_A_DQS5
154 156
DDR_A_D46
158
DDR_A_D47
160 162
DDR_A_D52
164
DDR_A_D53
166 168 170 172
DDR_A_D54
174
DDR_A_D55
176 178
DDR_A_D60
180
DDR_A_D61
182 184
DDR_A_DQS#7
186
DDR_A_DQS7
188 190
DDR_A_D62
192
DDR_A_D63
194 196 198
PM_SMBDATA
200
PM_SMBCLK
202 204
206
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
+0.75VS
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
DDRA_CKE3 <7>
DDRA_CLK3 <7> DDRA_CLK3# <7>
DDRA_SCS2# <7> DDRA_ODT2 <7>
DDRA_ODT3 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K C133
C133
1
2
Layout Note: Place near JDIMMA2.203,204
+0.75VS
Reverse:4mm <Address: SA1:SA0=01> TOP
DDRIII-DIMMA
DDRIII-DIMMA
DDRIII-DIMMA
1
+VREF_CA
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z C134
C134
1
2
C141
1U_0402_6.3V6K
C141
1U_0402_6.3V6K
1
2
12 58Friday, January 21, 2011
12 58Friday, January 21, 2011
12 58Friday, January 21, 2011
C142
1U_0402_6.3V6K
C142
1U_0402_6.3V6K
1
2
0.1
0.1
0.1
of
5
+1.5V
1K_0402_1%
1K_0402_1%
12
R102
R102
+VREFB_DQ
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K C148
C148
C147
1K_0402_1%
1K_0402_1%
D D
C C
B B
Layout Note: Place near JDIMMB1.203,204
+0.75VS
A A
C147
1
1
12
R103
R103
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+3VS
2
DDRB_CKE0<7>
DDR_B_BS2<7>
DDRB_CLK0<7> DDRB_CLK0#<7>
DDR_B_BS0<7>
DDR_B_WE#<7> DDR_B_CAS#<7>
DDRB_SCS1#<7>
C161
C161
C162
1U_0402_6.3V6K
C162
1U_0402_6.3V6K
1
2
C171
2.2U_0603_6.3V4Z
C171
2.2U_0603_6.3V4Z
1
2
+VREFB_DQ
DDR_B_D0 DDR_B_D1
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D9
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_D26 DDR_B_D27
DDRB_CKE0
DDR_B_BS2
DDR_B_MA12 DDR_B_MA9
DDR_B_MA8 DDR_B_MA5
DDR_B_MA3 DDR_B_MA1
DDRB_CLK0 DDRB_CLK0#
DDR_B_MA10 DDR_B_BS0
DDR_B_WE# DDR_B_CAS# DDRB_ODT0
DDR_B_MA13 DDRB_SCS1#
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_D42 DDR_B_D43
DDR_B_D48 DDR_B_D49
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51
DDR_B_D56 DDR_B_D57
DDR_B_D58 DDR_B_D59
R107
R107
1 2
10K_0402_5%
10K_0402_5%
C172
0.1U_0402_10V6K
C172
0.1U_0402_10V6K
1
R109 10K_0402_5%R109 10K_0402_5%
2
5
+1.5V +1.5V
3A@1.5V
3A@1.5V
3A@1.5V3A@1.5V
JDDR3
JDDR3
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
1 2
SA1
203
VTT1
205
G1
TYCO_2-2013310-1
TYCO_2-2013310-1
@
@
Standard:9.2mm <Address: SA1:SA0=10> BOT
VSS3
DQS#0
DQS0
VSS6
VSS8 DQ12 DQ13
VSS10
DQ14 DQ15
DQ20 DQ21
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
DQ30 DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35 DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47 DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
VTT2
DQ4 DQ5
DQ6 DQ7
DM1
DM2
CK1
BA1
NC2
DM4
DM6
SDA SCL
A15 A14
A11
A7
A6 A4
A2 A0
S0#
G2
4
DDR_B_DQS#[0..7]<7>
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..15]<7>
SM_DRAMRST# <7,12>
+1.5V
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
C149
C149
1
+
+
2
DDRB_CKE1 <7>
DDRB_CLK1 <7> DDRB_CLK1# <7>
DDR_B_BS1 <7> DDR_B_RAS# <7>
DDRB_SCS0# <7> DDRB_ODT0 <7>
DDRB_ODT1 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K C157
C157
1
2
PM_SMBDATA <12,30,39> PM_SMBCLK <12,30,39>
+0.75VS
Layout Note: Place near JDIMMB
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C150
C150
C151
C151
1
1
2
2
+1.5V
12
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z C158
C158
12
1
2
Layout Note: Place these 4 Caps near Command and Control signals of JDIMMB
+1.5V
0.1U_0402_10V6K
0.1U_0402_10V6K C163
C163
1
2
2
DDR_B_D4
4
DDR_B_D5
6 8
DDR_B_DQS#0
10
DDR_B_DQS0
12 14
DDR_B_D6
16
DDR_B_D7
18 20
DDR_B_D12
22
DDR_B_D13
24 26 28
SM_DRAMRST#
30 32
DDR_B_D14
34
DDR_B_D15
36 38
DDR_B_D20
40
DDR_B_D21
42 44 46 48
DDR_B_D22
50
DDR_B_D23
52 54
DDR_B_D28
56
DDR_B_D29
58 60
DDR_B_DQS#3
62
DDR_B_DQS3
64 66
DDR_B_D30
68
DDR_B_D31
70 72
DDRB_CKE1
74 76
DDR_B_MA15
78
DDR_B_MA14
80 82
DDR_B_MA11
84
DDR_B_MA7
86 88
DDR_B_MA6
90
DDR_B_MA4
92 94
DDR_B_MA2
96
DDR_B_MA0
98 100
DDRB_CLK1
102
DDRB_CLK1#
104 106
DDR_B_BS1
108
DDR_B_RAS#
110 112
DDRB_SCS0#
114 116 118
DDRB_ODT1
120 122 124
+VREF_CB
126 128
DDR_B_D36
130
DDR_B_D37
132 134 136 138
DDR_B_D38
140
DDR_B_D39
142 144
DDR_B_D44
146
DDR_B_D45
148 150
DDR_B_DQS#5
152
DDR_B_DQS5
154 156
DDR_B_D46
158
DDR_B_D47
160 162
DDR_B_D52
164
DDR_B_D53
166 168 170 172
DDR_B_D54
174
DDR_B_D55
176 178
DDR_B_D60
180
DDR_B_D61
182 184
DDR_B_DQS#7
186
DDR_B_DQS7
188 190
DDR_B_D62
192
DDR_B_D63
194 196 198
PM_SMBDATA
200
PM_SMBCLK
202 204
206
4
3
+1.5V +1.5V
+VREFB_DQ
DDR_B_D0 DDR_B_D1
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D9
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C152
C152
1
2
R104
R104 1K_0402_1%
1K_0402_1%
R105
R105 1K_0402_1%
1K_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K C164
C164
1
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C153
C153
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
3
10U_0603_6.3V6M
10U_0603_6.3V6M
C156
47P_0402_50V8J
C156
C154
C154
1
2
C165
C165
1
2
47P_0402_50V8J
C155
C155
1
12
2
DDRB_CKE2<7>
DDRB_CLK2<7> DDRB_CLK2#<7>
DDRB_SCS3#<7>
0.1U_0402_10V6K
0.1U_0402_10V6K C166
C166
+3VS
C169
2.2U_0603_6.3V4Z
C169
2.2U_0603_6.3V4Z
1
2
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
DDR_B_D18 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_D26 DDR_B_D27
DDRB_CKE2
DDR_B_BS2
DDR_B_MA12 DDR_B_MA9
DDR_B_MA8 DDR_B_MA5
DDR_B_MA3 DDR_B_MA1
DDRB_CLK2 DDRB_CLK2#
DDR_B_MA10 DDR_B_BS0
DDR_B_WE# DDR_B_CAS# DDRB_ODT2
DDR_B_MA13 DDRB_SCS3#
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_D42 DDR_B_D43
DDR_B_D48 DDR_B_D49
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51
DDR_B_D56 DDR_B_D57
DDR_B_D58 DDR_B_D59
R10610K_0402_5% R10610K_0402_5%
1 2
1 2
C170
0.1U_0402_10V6K
C170
0.1U_0402_10V6K R108 10K_0402_5%R108 10K_0402_5%
1
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
3A@1.5V
3A@1.5V
3A@1.5V3A@1.5V
JDDR4
JDDR4
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO 2-1932323-1
TYCO 2-1932323-1
@
@
2
VSS3
DQS#0
DQS0
VSS6
VSS8 DQ12 DQ13
VSS10
DQ14 DQ15
DQ20 DQ21
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
DQ30 DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35 DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47 DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
VTT2
DQ4 DQ5
DQ6 DQ7
DM1
DM2
CK1
BA1
NC2
DM4
DM6
SDA SCL
A15 A14
A11
A7
A6 A4
A2 A0
S0#
G2
1
2
DDR_B_D4
4
DDR_B_D5
6 8
DDR_B_DQS#0
10
DDR_B_DQS0
12 14
DDR_B_D6
16
DDR_B_D7
18 20
DDR_B_D12
22
DDR_B_D13
24 26 28
SM_DRAMRST#
30 32
DDR_B_D14
34
DDR_B_D15
36 38
DDR_B_D20
40
DDR_B_D21
42 44 46 48
DDR_B_D22
50
DDR_B_D23
52 54
DDR_B_D28
56
DDR_B_D29
58 60
DDR_B_DQS#3
62
DDR_B_DQS3
64 66
DDR_B_D30
68
DDR_B_D31
70 72
DDRB_CKE3
74 76
DDR_B_MA15
78
DDR_B_MA14
80 82
DDR_B_MA11
84
DDR_B_MA7
86 88
DDR_B_MA6
90
DDR_B_MA4
92 94
DDR_B_MA2
96
DDR_B_MA0
98 100
DDRB_CLK3
102
DDRB_CLK3#
104 106
DDR_B_BS1
108
DDR_B_RAS#
110 112
DDRB_SCS2#
114 116 118
DDRB_ODT3
120 122 124
+VREF_CB
126 128
DDR_B_D36
130
DDR_B_D37
132 134 136 138
DDR_B_D38
140
DDR_B_D39
142 144
DDR_B_D44
146
DDR_B_D45
148 150
DDR_B_DQS#5
152
DDR_B_DQS5
154 156
DDR_B_D46
158
DDR_B_D47
160 162
DDR_B_D52
164
DDR_B_D53
166 168 170 172
DDR_B_D54
174
DDR_B_D55
176 178
DDR_B_D60
180
DDR_B_D61
182 184
DDR_B_DQS#7
186
DDR_B_DQS7
188 190
DDR_B_D62
192
DDR_B_D63
194 196 198
PM_SMBDATA
200
PM_SMBCLK
202 204
206
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRB_CKE3 <7>
DDRB_CLK3 <7> DDRB_CLK3# <7>
DDRB_SCS2# <7> DDRB_ODT2 <7>
DDRB_ODT3 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K C159
C159
1
2
Layout Note: Place near JDIMMB2.203,204
+0.75VS
+0.75VS
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
Reverse:8mm <Address: SA1:SA0=11> TOP
DDRIII-DIMMB
DDRIII-DIMMB
DDRIII-DIMMB
1
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
+VREF_CB
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z C160
C160
C167
C167
13 58Friday, January 21, 2011
13 58Friday, January 21, 2011
13 58Friday, January 21, 2011
C168
1U_0402_6.3V6K
C168
1U_0402_6.3V6K
1
2
0.1
0.1
0.1
5
N12PGS@
N12PGS@
UV1
UV1 N12P-GS-A1_BGA_973P
N12P-GS-A1_BGA_973P
D D
Under GPU(below 150mils) Near GPU
BLM18PG330SN1D_0603
BLM18PG330SN1D_0603
+1.05VS_DGPU
C C
B B
A A
1 2
LV1
LV1
1 2
RV24 10M_0402_5%RV24 10M_0402_5%
XTALIN XTAL_OUT
27MHZ_16PF_X5H027000FG1H
27MHZ_16PF_X5H027000FG1H
1
CV46
CV46 18P_0402_50V8J
18P_0402_50V8J
2
CLK_REQ_VGA#<30>
2N7002_SOT23-3
2N7002_SOT23-3
YV1
YV1
1 2
QV4
QV4
DGPU_PWR_EN<17,33>
@
@
D
D
S
S
5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV1
CV1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV47
CV47 18P_0402_50V8J
18P_0402_50V8J
2
13
RV115 0_0402_5%
RV115 0_0402_5%
2
G
G
1 2
10U_0603_6.3V6M
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS_DGPU
10U_0603_6.3V6M
1
CV4
CV4
2
PLTRST_VGA#<33>
RV118
RV118 10K_0402_5%
10K_0402_5%
1 2
CLK_REQ_GPU#
RV123
RV123 10K_0402_5%
10K_0402_5%
@
@
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV2
CV2
CV3
CV3
2
PCIE_GTX_C_CRX_P0 PCIE_GTX_C_CRX_N0 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_N4 PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_N5 PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_N6 PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_N7 PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_N15
RV19 stuff per NV request. 12/17
RV124
RV124 10K_0402_5%
10K_0402_5%
1 2 2
G
G
QV2
QV2
1 3
D
S
D
S
2N7002_SOT23-3
2N7002_SOT23-3
@
@
1 2
+3VS_DGPU
RV128
RV128 10K_0402_5%
10K_0402_5%
@
@
2
CV5
CV5
1
CV6 0.22U_0402_10V6KCV6 0.22U_0402_10V6K CV7 0.22U_0402_10V6KCV7 0.22U_0402_10V6K CV8 0.22U_0402_10V6KCV8 0.22U_0402_10V6K CV9 0.22U_0402_10V6KCV9 0.22U_0402_10V6K CV10 0.22U_0402_10V6KCV10 0.22U_0402_10V6K CV11 0.22U_0402_10V6KCV11 0.22U_0402_10V6K CV12 0.22U_0402_10V6KCV12 0.22U_0402_10V6K CV13 0.22U_0402_10V6KCV13 0.22U_0402_10V6K CV14 0.22U_0402_10V6KCV14 0.22U_0402_10V6K CV15 0.22U_0402_10V6KCV15 0.22U_0402_10V6K CV16 0.22U_0402_10V6KCV16 0.22U_0402_10V6K CV17 0.22U_0402_10V6KCV17 0.22U_0402_10V6K CV18 0.22U_0402_10V6KCV18 0.22U_0402_10V6K CV19 0.22U_0402_10V6KCV19 0.22U_0402_10V6K CV20 0.22U_0402_10V6KCV20 0.22U_0402_10V6K CV21 0.22U_0402_10V6KCV21 0.22U_0402_10V6K CV22 0.22U_0402_10V6KCV22 0.22U_0402_10V6K CV23 0.22U_0402_10V6KCV23 0.22U_0402_10V6K CV24 0.22U_0402_10V6KCV24 0.22U_0402_10V6K CV25 0.22U_0402_10V6KCV25 0.22U_0402_10V6K CV26 0.22U_0402_10V6KCV26 0.22U_0402_10V6K CV27 0.22U_0402_10V6KCV27 0.22U_0402_10V6K CV28 0.22U_0402_10V6KCV28 0.22U_0402_10V6K CV29 0.22U_0402_10V6KCV29 0.22U_0402_10V6K CV30 0.22U_0402_10V6KCV30 0.22U_0402_10V6K CV31 0.22U_0402_10V6KCV31 0.22U_0402_10V6K CV32 0.22U_0402_10V6KCV32 0.22U_0402_10V6K CV33 0.22U_0402_10V6KCV33 0.22U_0402_10V6K CV34 0.22U_0402_10V6KCV34 0.22U_0402_10V6K CV35 0.22U_0402_10V6KCV35 0.22U_0402_10V6K CV36 0.22U_0402_10V6KCV36 0.22U_0402_10V6K CV37 0.22U_0402_10V6KCV37 0.22U_0402_10V6K
RV27 10K_0402_5%RV27 10K_0402_5%
1 2
150mA
+PLLVDD
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
CLK_PCIE_VGA<30>
CLK_PCIE_VGA#<30>
4
PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15
PCIE_GTX_CRX_P0 PCIE_GTX_CRX_N0 PCIE_GTX_CRX_P1 PCIE_GTX_CRX_N1 PCIE_GTX_CRX_P2 PCIE_GTX_CRX_N2 PCIE_GTX_CRX_P3 PCIE_GTX_CRX_N3 PCIE_GTX_CRX_P4 PCIE_GTX_CRX_N4 PCIE_GTX_CRX_P5 PCIE_GTX_CRX_N5 PCIE_GTX_CRX_P6 PCIE_GTX_CRX_N6 PCIE_GTX_CRX_P7 PCIE_GTX_CRX_N7 PCIE_GTX_CRX_P8 PCIE_GTX_CRX_N8 PCIE_GTX_CRX_P9 PCIE_GTX_CRX_N9 PCIE_GTX_CRX_P10 PCIE_GTX_CRX_N10 PCIE_GTX_CRX_P11 PCIE_GTX_CRX_N11 PCIE_GTX_CRX_P12 PCIE_GTX_CRX_N12 PCIE_GTX_CRX_P13 PCIE_GTX_CRX_N13 PCIE_GTX_CRX_P14 PCIE_GTX_CRX_N14 PCIE_GTX_CRX_P15 PCIE_GTX_CRX_N15
CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ_GPU#
1 2
RV19 200_0402_1%RV19 200_0402_1%
1 2
RV22 0_0402_5%RV22 0_0402_5%
1 2
RV23 2.49K_0402_1%RV23 2.49K_0402_1%
+PLLVDD
Internal Thermal Sensor
SMB_CLK_GPU<15> SMB_DATA_GPU<15>
4
PEX_TSTCLK_OUT PEX_TSTCLK_OUT#
XTALIN XTAL_OUT
RV26 10K_0402_5%RV26 10K_0402_5%
PLTRST_VGA_R#
60mA
45mA
45mA
XTALOUT XTALSSIN
12
SMB_CLK_GPU SMB_DATA_GPU
VGA_EDID_CLK VGA_EDID_DATA
I2CB_SCL I2CB_SDA
I2CA_SCL I2CA_SDA
HDCP_SCL HDCP_SDA
UV1A
UV1A
AP17
PEX_RX0
AN17
PEX_RX0_N
AN19
PEX_RX1
AP19
PEX_RX1_N
AR19
PEX_RX2
AR20
PEX_RX2_N
AP20
PEX_RX3
AN20
PEX_RX3_N
AN22
PEX_RX4
AP22
PEX_RX4_N
AR22
PEX_RX5
AR23
PEX_RX5_N
AP23
PEX_RX6
AN23
PEX_RX6_N
AN25
PEX_RX7
AP25
PEX_RX7_N
AR25
PEX_RX8
AR26
PEX_RX8_N
AP26
PEX_RX9
AN26
PEX_RX9_N
AN28
PEX_RX10
AP28
PEX_RX10_N
AR28
PEX_RX11
AR29
PEX_RX11_N
AP29
PEX_RX12
AN29
PEX_RX12_N
AN31
PEX_RX13
AP31
PEX_RX13_N
AR31
PEX_RX14
AR32
PEX_RX14_N
AR34
PEX_RX15
AP34
PEX_RX15_N
AL17
PEX_TX0
AM17
PEX_TX0_N
AM18
PEX_TX1
AM19
PEX_TX1_N
AL19
PEX_TX2
AK19
PEX_TX2_N
AL20
PEX_TX3
AM20
PEX_TX3_N
AM21
PEX_TX4
AM22
PEX_TX4_N
AL22
PEX_TX5
AK22
PEX_TX5_N
AL23
PEX_TX6
AM23
PEX_TX6_N
AM24
PEX_TX7
AM25
PEX_TX7_N
AL25
PEX_TX8
AK25
PEX_TX8_N
AL26
PEX_TX9
AM26
PEX_TX9_N
AM27
PEX_TX10
AM28
PEX_TX10_N
AL28
PEX_TX11
AK28
PEX_TX11_N
AK29
PEX_TX12
AL29
PEX_TX12_N
AM29
PEX_TX13
AM30
PEX_TX13_N
AM31
PEX_TX14
AM32
PEX_TX14_N
AN32
PEX_TX15
AP32
PEX_TX15_N
AR16
PEX_REFCLK
AR17
PEX_REFCLK_N
AR13
PEX_CLKREQ_N
AJ17
PEX_TSTCLK_OUT
AJ18
PEX_TSTCLK_OUT_N
AM16
PEX_RST_N
AG21
PEX_TERMP
AE9
PLLVDD
AF9
SP_PLLVDD
AD9
VID_PLLVDD
B1
XTAL_IN
B2
XTAL_OUT
D1
XTAL_OUTBUFF
D2
XTAL_SSIN
E2
I2CS_SCL
E1
I2CS_SDA
E3
I2CC_SCL
E4
I2CC_SDA
G3
I2CB_SCL
G2
I2CB_SDA
G1
I2CA_SCL
G4
I2CA_SDA
F6
I2CH_SCL
G6
I2CH_SDA
N12P-GV-A1_BGA_973P
N12P-GV-A1_BGA_973P
N12PGV@
N12PGV@
3
Part 1 of 7
Part 1 of 7
GPIO
GPIO
MIOA_D0_NC MIOA_D1_NC MIOA_D2_NC MIOA_D3_NC MIOA_D4_NC MIOA_D5_NC MIOA_D6_NC MIOA_D7_NC MIOA_D8_NC
MIOA_D9_NC MIOA_D10_NC MIOA_D11_NC MIOA_D12_NC MIOA_D13_NC MIOA_D14_NC
DVO
DVO
MIOB_D0_NC
MIOB_D1_NC
MIOB_D2_NC
PCI EXPRESS
PCI EXPRESS
MIOB_D3_NC
MIOB_D4_NC
MIOB_D5_NC
MIOB_D6_NC
MIOB_D7_NC
MIOB_D8_NC
MIOB_D9_NC MIOBD_10_NC MIOB_D11_NC MIOB_D12_NC MIOB_D13_NC MIOB_D14_NC
MIOA_HSYNC_NC MIOA_VSYNC_NC
MIOB_HSYNC_NC MIOB_VSYNC_NC
MIOA_DE_NC
MIOA_CTL3_NC
MIOA_VREF_NC
MIOB_DE_NC
MIOB_CTL3_NC
MIOB_VREF_NC
MIOA_CLKIN_NC
MIOA_CLKOUT_NC
MIOB_CLKIN_NC
MIOB_CLKOUT_NC
MIOA_CLKOUT_NC_N MIOB_CLKOUT_NC_N
MIOACAL_PD_VDDQ_NC
MIOACAL_PU_GND_NC
MIOBCAL_PD_VDDQ_NC
MIOBCAL_PU_GND_NC
CLK
CLK
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC
DACA_VREF DACA_RSET
DACB_GREEN
DACB_BLUE
DACs
DACs
DACB_HSYNC
I2C
I2C
DACB_VSYNC
DACB_VREF DACB_RSET
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
K1
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24
DACA_RED
DACA_VDD
DACB_RED
DACB_VDD
VGA_GPIO1
K2 K3 H3 H2
GPU_VID0
H1
GPU_VID1
H4 H5
GPIO8
H6
THERM#_VGA
J7 K4 K5
GPIO12
H7 J4 J6
VGA_HDMI_HPD
L1 L2 L4 M4 L7 L5 K6 L6 M6 M7
N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6
Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6
N3 L3
W1 W2
N2 P5 N5
Y5 W3 AF1
1 2
N4
RV18 10K_0402_5%RV18 10K_0402_5%
R4
1 2
AE1
RV21 10K_0402_5%RV21 10K_0402_5%
V4
T4 W4
U5 T5
AA7 AA6
AM15 AM14 AL14
AM13
+3VS_DGPU
AL13
AJ12 AK12 AK13
AK4 AL4 AJ4
AM1 AM2
+DACB_VDD
AG7 AK6 AH7
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
GPU_VID0 <57> GPU_VID1 <57>
THERM#_VGA <15>
@
TV1@TV1
1
C880
C880
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
12
RV32 10K_0402_5%RV32 10K_0402_5%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
VGA_PWROK<33,34,46,57>
2
PCIE_GTX_C_CRX_P[0..15]<6>
PCIE_GTX_C_CRX_N[0..15]<6>
PCIE_CTX_C_GRX_P[0..15]<6>
PCIE_CTX_C_GRX_N[0..15]<6>
+3VS_DGPU
R1430
R1430
0_0402_5%
0_0402_5%
12
1
HDMI_HPD<28>
2
2
SN74AHC1G08DCKR_SC70-5
SN74AHC1G08DCKR_SC70-5
1 2
5
U55
U55
P
IN1
IN2
G
3
0_0402_5%
0_0402_5%
@
@
R1431
R1431
1
PCIE_GTX_C_CRX_P[0..15]
PCIE_GTX_C_CRX_N[0..15]
PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_N[0..15]
C879
C879
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
VGA_HDMI_HPD
4
O
GPIO8
GPIO12
VGA_EDID_CLK
VGA_EDID_DATA
SMB_CLK_GPU
SMB_DATA_GPU
THERM#_VGA
HDCP_SCL
HDCP_SDA
I2CA_SDA
I2CA_SCL
I2CB_SCL
I2CB_SDA
VGA_GPIO1
VGA_HDMI_HPD
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
VGA(1/12)-PCIE/DAC/GPIO
VGA(1/12)-PCIE/DAC/GPIO
VGA(1/12)-PCIE/DAC/GPIO
1 2
RV1 10K_0402_5%RV1 10K_0402_5%
1 2
RV2 10K_0402_5%RV2 10K_0402_5%
1 2
RV3 2.2K_0402_5%RV3 2.2K_0402_5%
1 2
RV4 2.2K_0402_5%RV4 2.2K_0402_5%
1 2
RV5 2.2K_0402_5%RV5 2.2K_0402_5%
1 2
RV6 2.2K_0402_5%RV6 2.2K_0402_5%
1 2
RV7 100K_0402_5%RV7 100K_0402_5%
1 2
RV8 2.2K_0402_5%RV8 2.2K_0402_5%
1 2
RV9 2.2K_0402_5%RV9 2.2K_0402_5%
1 2
RV10 2.2K_0402_5%RV10 2.2K_0402_5%
1 2
RV11 2.2K_0402_5%RV11 2.2K_0402_5%
1 2
RV12 2.2K_0402_5%RV12 2.2K_0402_5%
1 2
RV13 2.2K_0402_5%RV13 2.2K_0402_5%
1 2
RV17 100K_0402_5%RV17 100K_0402_5%
1 2
RV20 100K_0402_5%RV20 100K_0402_5%
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
14 58Friday, January 21, 2011
14 58Friday, January 21, 2011
14 58Friday, January 21, 2011
+3VS_DGPU
0.1
0.1
0.1
5
AM11 AM12
AM8
D D
C C
VGA_HDMI_TX2+<28>
VGA_HDMI_TX2-<28>
VGA_HDMI_TX1+<28>
VGA_HDMI_TX1-<28>
VGA_HDMI_TX0+<28>
VGA_HDMI_TX0-<28> VGA_HDMI_CLK+<28> VGA_HDMI_CLK-<28>
+3VS_DGPU
1 2
RV40 4.7K_0402_5%RV40 4.7K_0402_5%
1 2
RV43 4.7K_0402_5%RV43 4.7K_0402_5%
B B
HDMI
VGA_HDMI_CLK
VGA_HDMI_DATA
VGA_HDMI_CLK<28> VGA_HDMI_DATA<28>
STRAP0<25> STRAP1<25> STRAP2<25>
VGA_HDMI_TX2+ VGA_HDMI_TX2­VGA_HDMI_TX1+ VGA_HDMI_TX1­VGA_HDMI_TX0+ VGA_HDMI_TX0­VGA_HDMI_CLK+ VGA_HDMI_CLK-
VGA_HDMI_CLK VGA_HDMI_DATA
+3VS_DGPU
RV44
RV44 10K_0402_5%
10K_0402_5%
1 2
STRAP0 STRAP1 STRAP2
AM10
AM9
AK10
AL10
AK11
AL11
AP13 AN13
AP10 AN10 AR11 AR10 AN11 AP11
AM7 AM6
AM5 AM3 AM4
AN8 AP8
AP1 AR2
AR8 AR7 AP7 AN7 AN5 AP5 AR5 AR4
AH6 AH5 AH4 AG4 AF4 AF5 AE6 AE5
AH1 AH2 AH3
AP2 AN3
AP4 AN4
AE4 AD4
AF3 AF2
AB5
UV1D
UV1D
IFPA_TXC IFPA_TXC_N IFPA_TXD0
AL8
IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N
IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N
IFPC_L0 IFPC_L0_N
AL5
IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N
IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N
IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N
AL2
IFPF_L0
AL3
IFPF_L0_N
AJ3
IFPF_L1
AJ2
IFPF_L1_N
AJ1
IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N
IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N
IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N
IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N
IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N
A4
BUFRST_N
CEC
W5
STRAP0
W7
STRAP1
V7
STRAP2
4
Part 4 of 7
Part 4 of 7
LVDS/TMDS
LVDS/TMDS
GENERAL
GENERAL
MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GND
NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8
NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26
NC
NC
NC_27 NC_28 NC_29
VDD_SENSE_0 VDD_SENSE_1 VDD_SENSE_2
GND_SENSE_0 GND_SENSE_1 GND_SENSE_2
TEST
TEST
TESTMODE
JTAG_TCK
JTAG_TDI JTAG_TDO JTAG_TMS
JTAG_TRST_N
SERIAL
SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
NC/SPDIF_NC
THERMDP THERMDN
A2 A7 B7 C5
STRAP4
C7 D5 D6
STRAP3
D7 E5
PGOOD
E7 F4 G5 H32 J25 J26
Strap_Ref2_GND
P6 U7 V6 Y4 AA4 AB4 AB7 AC5 AD6
Add C7,D7,E7,P6 for support GV
AF6 AG6 AG20 AJ5 AK15 AL7
VDD_SENSE
D35 P7 AD20
AD19 E35 R7
TESTMODE
AP35 AP14 AN14 AN16 AR14 AP16
RV42 10K_0402_5%RV42 10K_0402_5%
C3
ROM_SI
D3
ROM_SO
C4
ROM_SCLK
D4
A5
RV45 36K_0402_5%RV45 36K_0402_5%
N9
RV46 40.2K_0402_1%RV46 40.2K_0402_1%
M9
RV47 40.2K_0402_1%RV47 40.2K_0402_1%
THERM_D+
B5
THERM_D-
B4
1 2
1 2
1 2
1 2
STRAP4 <25>
STRAP3 <25>
12
RV107
RV107
40.2K_0402_1%
40.2K_0402_1%
N12PGV@
N12PGV@
VDD_SENSE <57>
TV2@TV2 TV3@TV3 TV4@TV4 TV5@TV5
@ @ @ @
ROM_SI <25> ROM_SO <25> ROM_SCLK <25>
3
N12PGV@
N12PGV@
12
10K_0402_5%
10K_0402_5% RV102
RV102
12
10K_0402_5%
10K_0402_5% RV41
RV41
THERM_D+
THERM_D-
2
External VGA Thermal Sensor
+3VS_DGPU
@
@
12
CV49 0.1U_0402_16V4Z
CV49 0.1U_0402_16V4Z
CV50
@CV50
@
1 2
2200P_0402_50V7K
2200P_0402_50V7K
RV25
RV25
2.2K_0402_5%
2.2K_0402_5%
VGA_SMB_CK2
VGA_SMB_DA2
UV4
1
VDD
2
D+
3
D-
THERM#4GND
ADM1032ARMZ-2REEL_MSOP8
ADM1032ARMZ-2REEL_MSOP8
+3VS_DGPU
RV28
RV28
2.2K_0402_5%
2.2K_0402_5%
1 2
1 2
QV3A
QV3A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
@UV4
@
2
8
SCLK
7
SDATA
6
ALERT#
5
+3VS_DGPU
5
QV3B
QV3B
4
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
61
3
Internal Thermal Sensor
12
12
RV35
0_0402_5%
0_0402_5%
VGA_SMB_CK2
VGA_SMB_DA2
THERM#_VGA
RV35
RV36
RV36
0_0402_5%
0_0402_5%
THERM#_VGA <14>
Address: 0x9A H 0x9E H
EC_SMB_CK2 <30,43>
EC_SMB_DA2 <30,43>
1
SMB_CLK_GPU <14>
SMB_DATA_GPU <14>
N12P-GV-A1_BGA_973P
N12P-GV-A1_BGA_973P
N12PGV@
A A
5
N12PGV@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
VGA(2/12)-LVDS/HDMI/DP/THM
VGA(2/12)-LVDS/HDMI/DP/THM
VGA(2/12)-LVDS/HDMI/DP/THM
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
15 58Friday, January 21, 2011
15 58Friday, January 21, 2011
15 58Friday, January 21, 2011
0.1
0.1
0.1
5
4
3
2
1
VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98
VDD_99 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110
N12P-GV
0.85V
P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24
1V0
+VGA_CORE+VGA_CORE
GS EDP Peak is 35.32A GV EDP Peak is 21.56A
CV57
CV57
47U_0805_4V6
47U_0805_4V6
CV65
CV65
0.1U_0402_16V7K
0.1U_0402_16V7K
CV73
CV73
0.01U_0402_25V7K
0.01U_0402_25V7K
+VGA_CORE
1
2
+VGA_CORE
1
2
+VGA_CORE
1
2
+VGA_CORE
1
+
+
CV51
CV51
2
470U_D2_2VM_R4M
470U_D2_2VM_R4M
1
+
+
CV52
CV52
2
470U_D2_2VM_R4M
470U_D2_2VM_R4M
+VGA_CORE
22U_0603_6.3V6M
22U_0603_6.3V6M
CV53
CV53
Near GPU Under GPU(below 150mils)
10U_0603_6.3V6M
2
CV56
CV56
1
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
2
CV58
CV58
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
CV59
CV59
1
10U_0603_6.3V6M
10U_0603_6.3V6M
CV60
CV60
1
2
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
CV61
CV61
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CV62
CV62
12
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
Under GPU(below 150mils)
0.022U_0402_25V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
CV66
CV66
2
1
CV74
CV74
2
0.01U_0402_25V7K
0.01U_0402_25V7K
0.047U_0402_25V6K
0.047U_0402_25V6K
1
CV67
CV67
2
0.047U_0402_25V6K
0.047U_0402_25V6K
0.01U_0402_25V7K
0.01U_0402_25V7K
1
CV75
CV75
2
0.01U_0402_25V7K
0.01U_0402_25V7K
CV68
CV68
CV76
CV76
1
CV69
CV69
2
0.047U_0402_25V6K
0.047U_0402_25V6K
0.01U_0402_25V7K
0.01U_0402_25V7K
1
CV77
CV77
2
0.022U_0402_25V7K
1
CV70
CV70
2
1
CV78
CV78
2
0.01U_0402_25V7K
0.01U_0402_25V7K
1
2
1
2
0.022U_0402_25V7K
0.022U_0402_25V7K
1
CV71
CV71
2
0.022U_0402_25V7K
0.022U_0402_25V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
1
CV79
CV79
2
22U_0603_6.3V6M
22U_0603_6.3V6M
2
CV54
CV54
@
@
@
@
1
22U_0603_6.3V6M
22U_0603_6.3V6M
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
12
CV63
CV63
CV64
CV64
1
CV72
CV72
2
1
CV80
CV80
2
0.01U_0402_25V7K
0.01U_0402_25V7K
2
2
CV55
CV55
@
@
1
1
12
0
1
1
Part 7 of 7
Part 7 of 7
N12P-GS
0.825V
0.975V
1V
POWER
POWER
Pstate
P8-P12
P0(Hot)
D D
P0(cold) 1.025V
C C
B B
GPU_VID0 GPU_VID1
0
1
0
1
UV1G
UV1G
AB11
VDD_0
AB13
VDD_1
AB15
VDD_2
AB17
VDD_3
AB19
VDD_4
AB21
VDD_5
AB23
VDD_6
AB25
VDD_7
AC11
VDD_8
AC12
VDD_9
AC13
VDD_10
AC14
VDD_11
AC15
VDD_12
AC16
VDD_13
AC17
VDD_14
AC18
VDD_15
AC19
VDD_16
AC20
VDD_17
AC21
VDD_18
AC22
VDD_19
AC23
VDD_20
AC24
VDD_21
AC25
VDD_22
AD12
VDD_23
AD14
VDD_24
AD16
VDD_25
AD18
VDD_26
AD22
VDD_27
AD24
VDD_28
L11
VDD_29
L12
VDD_30
L13
VDD_31
L14
VDD_32
L15
VDD_33
L16
VDD_34
L17
VDD_35
L18
VDD_36
L19
VDD_37
L20
VDD_38
L21
VDD_39
L22
VDD_40
L23
VDD_41
L24
VDD_42
L25
VDD_43
M12
VDD_44
M14
VDD_45
M16
VDD_46
M18
VDD_47
M20
VDD_48
M22
VDD_49
M24
VDD_50
P11
VDD_51
P13
VDD_52
P15
VDD_53
P17
VDD_54
P19
VDD_55
N12P-GV-A1_BGA_973P
N12P-GV-A1_BGA_973P
N12PGV@
N12PGV@
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
VGA(3/12)-VGA CORE
VGA(3/12)-VGA CORE
VGA(3/12)-VGA CORE
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
16 58Friday, January 21, 2011
16 58Friday, January 21, 2011
16 58Friday, January 21, 2011
0.1
0.1
0.1
5
Near GPU
4.7U_0603_6.3V6K
+VRAM_1.5VS
CV82
CV82
4.7U_0603_6.3V6K
D D
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2
Under GPU(below 150mils)
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VRAM_1.5VS
C C
B B
A A
1
2
CV101
CV101
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV102
CV102
2
1
CV103
CV103
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV104
CV104
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV105
CV105
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
GS is 5.49A GV is 2.99A
1
1
CV83
CV83
CV84
CV84
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
RV116 10K_0402_5%RV116 10K_0402_5%
RV50 1K_0402_1%
RV50 1K_0402_1%
RV53 1K_0402_1%
RV53 1K_0402_1%
CV107
CV107
CV106
CV106
2
+IFPAB_PLLVDD
12
RV117 10K_0402_5%RV117 10K_0402_5%
RV49 10K_0402_5%RV49 10K_0402_5%
@
@
1 2
RV51 10K_0402_5%RV51 10K_0402_5%
@
@
RV52 10K_0402_5%RV52 10K_0402_5%
1 2
RV55 10K_0402_5%RV55 10K_0402_5%
1 2
RV56 1K_0402_1%RV56 1K_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV81
CV81
2
1
CV108
CV108
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
1 2
RV48 1K_0402_1%
RV48 1K_0402_1%
+IFPAB_IOVDD
12
+IFPC_PLLVDD
12
+IFPC_IOVDD
12
+IFPD_PLLVDD
12
+IFPD_IOVDD
12
+IFPEF_PLLVDD
+IFPE_IOVDD
+3VS_DGPU
LV4
LV4
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
1
CV120
CV120
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
+1.05VS_DGPU
LV6
LV6
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
1
CV130
CV130
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
J23 J24
J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27
AJ28
B18 E21 G17 G18 G22
G8 G9
H29
J14
J15
J16
J17
J20
J21
J22
N27 P27 R27
T27
U27 U29 V27 V29 V34
W27
Y27
AK9
AJ11
AG9
AG10
AJ9
AK7
AJ8
AC6 AB6
AK8
AJ6
AL1
AE7 AD7
N12PGV@
N12PGV@
Near GPU
12
1
CV121
CV121
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
12
1
CV131
CV131
2
UV1E
UV1E
FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37
IFPAB_PLLVDD IFPAB_RSET
IFPA_IOVDD IFPB_IOVDD
IFPC_PLLVDD IFPC_RSET
IFPC_IOVDD
IFPD_PLLVDD IFPD_RSET
IFPD_IOVDD
IFPEF_PLLVDD IFPEF_RSET
IFPE_IOVDD IFPF_IOVDD
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
3
Part 5 of 7
Part 5 of 7
PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8
PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24
PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4
POWER
POWER
PEX_PLLVDD
PEX_SVDD_3V3
PEX_SVDD_3V3_NC
VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4
MIOA_VDDQ_NC_0 MIOA_VDDQ_NC_1 MIOA_VDDQ_NC_2 MIOA_VDDQ_NC_3
MIOB_VDDQ_NC_0 MIOB_VDDQ_NC_1 MIOB_VDDQ_NC_2 MIOB_VDDQ_NC_3
N12P-GV-A1_BGA_973P
N12P-GV-A1_BGA_973P
Under GPU(below 150mils)
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CV122
CV122
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV132
CV132
2
CV123
CV123
CV133
CV133
CV124
CV124
2
1
CV134
CV134
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
GS is 2.95A GV is 3.51A
Under GPU(below 150mils) Near GPU
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16
AK16 AK17 AK21 AK24 AK27
AG14
AG19 F7
J10 J11 J12 J13 J9
P9 R9 T9 U9
AA9 AB9 W9 Y9
1
CV125
CV125
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
570mA
+IFPE_IOVDD
+PEX_PLLVDD
10K_0402_5%
10K_0402_5%
220mA
+IFPEF_PLLVDD
1
1
CV85
CV85
CV86
CV86
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CV93
CV93
CV94
CV94
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Under GPU(below 150mils)
120mA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
240mA (120mA each)
120mA(12~16mils)
RV54
RV54
1 2
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CV116
CV116
CV115
CV115
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Under GPU(below 150mils)
RV57
RV57 10K_0402_5%
10K_0402_5%
DGPU_PWR_EN#<46>
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
2
1
CV88
CV88
2
1
CV96
CV96
2
1
CV109
CV109
2
Near GPU
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
CV117
CV117
2
DGPU_PWR_EN<14,33>
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
2
Near GPU
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
2
+3VS_DGPU
1
CV118
CV118
2
DGPU_PWR_EN#
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV89
CV89
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV97
CV97
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV110
CV110
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CV119
CV119
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV90
CV90
CV98
CV98
CV111
CV111
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CV91
CV91
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV99
CV99
2
LV3
LV3
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
Near GPU
1
CV113
CV113
2
12
+3VS_DGPU
1
2
+3VS to +3VS_DGPU
+3VALW
R445
R445 100K_0402_5%
100K_0402_5%
1 2
R444
R444
1 2
47K_0402_5%
47K_0402_5%
61
Q206A
Q206A
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
CV92
CV92
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
CV100
CV100
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
CV112
CV112
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
CV114
CV114
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
C491
C491
0.1U_0402_16V7K
0.1U_0402_16V7K
1
AO3413_SOT23
AO3413_SOT23
2
C492
C492
0.01U_0402_25V7K
0.01U_0402_25V7K
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
+1.05VS_DGPU
+1.05VS_DGPU
+1.05VS_DGPU
+3VS
Vgs=-4.5V,Id=3A,Rds<97mohm
12
S
S
Q54
C683
C683
Q54
G
G
2
@
@
R128
R128 0_0805_5%
0_0805_5%
@
@
D
D
1 3
1
1
C684
C684 1U_0402_6.3V6K
1U_0402_6.3V6K
2
2
+3VS_DGPU
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
VGA(4/12)-POWER
VGA(4/12)-POWER
VGA(4/12)-POWER
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
17 58Friday, January 21, 2011
17 58Friday, January 21, 2011
17 58Friday, January 21, 2011
0.1
0.1
0.1
5
D D
C C
B B
4
UV1F
UV1F
B3
GND_0
B6
GND_1
B9
GND_2
B12
GND_3
B15
GND_4
B21
GND_5
B24
GND_6
B27
GND_7
B30
GND_8
B33
GND_9
C2
GND_10
C34
GND_11
E6
GND_12
E9
GND_13
E12
GND_14
E15
GND_15
E18
GND_16
E24
GND_17
E27
GND_18
E30
GND_19
F2
GND_20
F31
GND_21
F34
GND_22
F5
GND_23
J2
GND_24
J5
GND_25
J31
GND_26
J34
GND_27
K9
GND_28
L9
GND_29
M2
GND_30
M5
GND_31
M11
GND_32
M13
GND_33
M15
GND_34
M17
GND_35
M19
GND_36
M21
GND_37
M23
GND_38
M25
GND_39
M31
GND_40
M34
GND_41
N11
GND_42
N12
GND_43
N13
GND_44
N14
GND_45
N15
GND_46
N16
GND_47
N17
GND_48
N18
GND_49
N19
GND_50
N20
GND_51
N21
GND_52
N22
GND_53
N23
GND_54
N24
GND_55
N25
GND_56
P12
GND_57
P14
GND_58
P16
GND_59
P18
GND_60
P20
GND_61
P22
GND_62
P24
GND_63
R2
GND_64
R5
GND_65
R31
GND_66
R34
GND_67
T11
GND_68
T13
GND_69
T15
GND_70
T17
GND_71
T19
GND_72
T21
GND_73
T23
GND_74
T25
GND_75
U11
GND_76
U12
GND_77
U13
GND_78
U14
GND_79
U15
GND_80
U16
GND_81
U17
GND_82
U18
GND_83
U19
GND_84
U20
GND_85
U21
GND_86
U22
GND_87
U23
GND_88
U24
GND_89
U25
GND_90
V2
GND_91
V5
GND_92
V9
GND_93
V12
GND_94
V14
GND_95
V16
GND_96
Part 6 of 7
Part 6 of 7
GND
GND
GND_97 GND_98
GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192
V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AK14 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33
3
2
1
N12P-GV-A1_BGA_973P
N12P-GV-A1_BGA_973P
N12PGV@
N12PGV@
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/12/03 2011/12/03
2010/12/03 2011/12/03
2010/12/03 2011/12/03
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
VGA(5/12)-GND
VGA(5/12)-GND
VGA(5/12)-GND
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
PBL80 LA-7441P M/B
1
18 58Friday, January 21, 2011
18 58Friday, January 21, 2011
18 58Friday, January 21, 2011
0.1
0.1
0.1
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