Compal LA-7401P PAJ80, P430, P530, LA-7401P PAJ90 Schematic

A

1 1

B

C

D

E

Compal Confidential

Schematics Document

2 2

Intel Huron River Platform

Sandy Bridge (Dual Core BGA 1023) With

Couger Point Core Logic

3 3

4 4

A

B

LA-7401P

2011-03-24

REV:1.0

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

1 56Sunday, April 10, 20 11

E

1.0

A

B

C

D

E

Compal Confidential

Model Name : PAJ80(14" UMA/Dis)/PAJ90(15.6" UMA/Dis)

File Name : LA-7401P

1 1

VRAM
128Mx16 4pcs=1G
64Mx16 4pcs=512M
800MHz

Page 29-32

N12P-GV
OPTIMUS SETUP

Page 22-33

PCI-E 2.0x16100MHz 5GT/s PER LANE

PEG(OPT)

Intel

Sandy Bridge

Processor

Dual Channel

DD R3-SO-DIMM X 2DDR3 1066/1333MHz 1.5V

BANK 0 , 1, 2 , 3

Page 11,12

FC BGA 1023

Optimus

FDI x8

HD MI Conn.

2 2

LV D S Conn.CR T Conn.

Page 34Page 35 Page 36

100MHz

2.7GT/s

LVDS

CRT

HDMI

PCI-Express x 8 ( PCIE2.0 2.5GT/s)

SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

MINI Card x1

WLAN

USB Port 4

Page 41

LAN(GbE)

RTL8111E-VL

Page 37

SATA HDD

3 3

RJ45

Page 37

Conn.

100MHz

100MHz

SATA ODD
Conn.

Page 40Page40

31mm*24mm

Page 4-10

Intel

Cougar Point-M

PC H

98 9pin BGA

25mm*25mm

Page 13-21

DMI x4

100MHz

1GB/s x4

LPC BUS

33MHz

USB connx1

USB Port 2 USB port 3
USB charger

Page 42

USBx12

HD Audio

3.3V 48MHz

3.3V 24MHz

SPI

SPI ROM x1
4 M B

Page 13

Int. Speaker

CMOS Camera

Page 34

USB connx2

USB port 0,1

HDA Codec

ALC259

Page 38

Phone Jack x 2

Page 39 Page 39

Digital Micx1

Card Rea der
RT S5129 7 in 1

Page 42

Daughter board

USB port 10

Page 42

ENE KB930

Page 44

USB/CR daughter board

PWR BTN/Led daughter board

15.6 ODD daughter board

4 4

T/P daughter board

A

B

Touch Pad Int.KBD

Page 45

Page 45

BI OS ROM

Page 44

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

LA-7401P

E

2 56Sunday, April 10, 20 11

1.0

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

BATT+ Battery power supply (12.6V) N/A N/A N/A

B+

+CPU_CORE

+VGA_CORE Core voltage for GPU

+VGFX_CORE Core voltage for UMA graphic ON OFF OFF

+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator

+1.05VS_DGPU +1.05VS to +1.05VS_DGPU switched power rail for GPU

+1.05VS

+1.5V

+1.5VS

+VRAM_1.5VS +1.5V to +VRAM_1.5VS power rail for GPU ON OFF OFF

+1.8VS +5VALW to 1.8VS switched power rail to CPU,PCH

+3VALW +3VALW always on power rail

+3VALW_EC +3VALW always to KBC ON ON ON*

+LAN_IO

+3VALW_PCH

+3VS

+5VALW

+5VALW_PCH

+5VS +5VALW to +5VS switched power rail OFFON OFF

+VSB +VSBP to +VSB always on power rail for sequence control ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

+VCCPP to +1.05VS switched power rail for CPU,PCH

+1.5VP to +1.5V power rail for DDRIII ON ON OFF

+1.5V to +1.5VS switched power rail

+3VALW to +LAN_IO power rail for LAN

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

B

S1

S3 S5

N/A N/A N/A

ON

ON

ON OFF OFF

ON OFF OFF

ON OFF OFF

ON OFF OFF

ON

ON

ON ON

ON ON

ON

ON

ON ON

ON

ON

N/AN/AN/A

OFF

OFF

OFF

OFF

OFF

OFF

ON ON*

ON*

ON*

OFF

OFF

ON ON*

ON*

ONON

C

STATE

Full ON

S1(P ower On Suspend)

S3 ( Suspend to RAM)

S4 ( Suspend to Disk)

S5 ( Soft OFF)

USB Port Table

USB 2.00USB 1.1

UHCI0

EHCI1

EHCI2

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

SIGNAL

Port

1
2
3
4
5
6
7
8

9
10
11
12
13

D

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

ON

OFF

OFF

ON ON

ON

OFF

OFF

OFF

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

LOW LOW LOW LOW

ON

ON

ON

ON

BTO Option Table

2 External
USB Port

CONN
CONN
CONN
Camera
Mini Card(WLAN/BT)
NA

NA
NA
Card Reader

BTO Item BOM Structure

Connector CONN@
Unpop
14" PCB 14@

15.6" PCB 15@
UMA PCB UMA@
Dis PCB (Optimus) OPT@
X76 512M
X76 1G

E

LOW

OFF

OFF

OFF

OPT@Optimus

@

512M@
1G@

2540M m ean 2.6G CPU2410M m ean 2.3G CPU 2520M m ean 2.5G CPU 2310M m ean 2.2G CPU 2620M mean 2.7G CPU PCH R3 GPU R32330M m ean 2.2G CPU

U2

U2

2410MR3@

2410M CPU

U2

2410MR1@

2410M CPU

3 3

2540M CPU

U2
2540M CPU

2540MR3@

2540MR1@

U2
2520M CPU

U2
2520M CPU

2520MR3@

2520MR1@

U2
2310M CPU

U2
2310M CPU

2310MR3@

2310MR1@

U2
2620M CPU

U2
2620M CPU

2620MR3@

2620MR1@

U2
2330M CPU

2330M@

U14
PCH B3

U14
PCH B3

PCHR3@

PCHR1@

UV1

GPUR3@

GPU

UV1

GPUR1@

GPU

PCB DAZ X7613432L03

ZZZ 1

PCB_LA-7401P

ZZZ 3

X76-VRAM

1G@

PCH SM Bus Address

HEX

0001 0110 bSmart B attery

Address

1010 0000 bA0 H

EC SM Bus2 Address

PowerPower

+3VS

+3VS NVIDIA GPU

Devi ce

B

96 H

9E H

1001 0110 bPCH

1001 1110 b

SMBUS Control Table

SOURCE

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

PCH_LCD_CLK

PCH_LCD_DATA

SDVO_SCLK

SDVO_SDATA

PCH_SMBCLK
PCH_SMBDATA

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

KB930

KB930

PCH

PCH

PCH

2010/08/23 2011/08/25

BATT

V

Compal Secret Data

Deciphered Date

CPU
THERMAL
SENSOR

SODIMM 0

SODIMM 1

V

D

WLAN

WWAN

LCD
DDC
ROM

HDMI
DDC
ROM

PCH

GPU

V

V

V

V

V

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Notes List

E

3 56Monday, A pril 11, 2011

1.0

Power

+3VS

+3VS 1010 0100 bA4 H

Devi ce

DDR SO-DIMM 0

DDR SO-DIMM 1

EC SM Bus1 Address

Devi ce Address Address

+3VL

4 4

A

HEX HEX

16 H

5

D D

<P CH >

C C

<P CH >

+1.05VS

eDP_ COMP IO and ICO MPO signa ls
shou ld b e shorted near ball s
and routed with typ ical
impe dance < 25 mohms

B B

12

R19

24.9_0402_1%

4

U2A

DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>
FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>

FDI _FSYNC 0<15>
FDI _FSYNC 1<15>

FDI_I NT<15>

FDI _LSYNC0<15>
FDI _LSYNC1<15>

EDP_COMP

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

SAND Y-BRIDGE_BGA1023~D

PEG_RCOMPO

DMI Intel(R) FDI DP

PCI EXPRESS -- GRAPHICS

PEG_ICOMPI

PEG_ICOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

3

PEG_ICO MPI and RCOMPO signals should be

+1.05VS

12

R18

24.9_0402_1%

PEG_COMP

G3
G1
G4

PEG_GTX_C_HRX_N15

H22

PEG_GTX_C_HRX_N14

J21

PEG_GTX_C_HRX_N13

B22

PEG_GTX_C_HRX_N12

D21

PEG_GTX_C_HRX_N11

A19

PEG_GTX_C_HRX_N10

D17

PEG_GTX_C_HRX_N9

B14

PEG_GTX_C_HRX_N8

D13

PEG_GTX_C_HRX_N7

A11

PEG_GTX_C_HRX_N6

B10

PEG_GTX_C_HRX_N5

G8

PEG_GTX_C_HRX_N4

A8

PEG_GTX_C_HRX_N3

B6

PEG_GTX_C_HRX_N2

H8

PEG_GTX_C_HRX_N1

E5

PEG_GTX_C_HRX_N0

K7

PEG_GTX_C_HRX_P15

K22

PEG_GTX_C_HRX_P14

K19

PEG_GTX_C_HRX_P13

C21

PEG_GTX_C_HRX_P12

D19

PEG_GTX_C_HRX_P11

C19

PEG_GTX_C_HRX_P10

D16

PEG_GTX_C_HRX_P9

C13

PEG_GTX_C_HRX_P8

D12

PEG_GTX_C_HRX_P7

C11

PEG_GTX_C_HRX_P6

C9

PEG_GTX_C_HRX_P5

F8

PEG_GTX_C_HRX_P4

C8

PEG_GTX_C_HRX_P3

C5

PEG_GTX_C_HRX_P2

H6

PEG_GTX_C_HRX_P1

F6

PEG_GTX_C_HRX_P0

K6

PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15

G22

PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14

C23

PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13

D23

PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12

F21

PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11

H19

PEG_HTX_GRX_N10 PEG_HTX_C_GRX_N10

C17

PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9

K15

PEG_HTX_GRX_N8 PEG_HTX_C_GRX_N8

F17

PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7

F14

PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6

A15

PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5

J14

PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4

H13

PEG_HTX_GRX_N3 PEG_HTX_C_GRX_N3

M10

PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2

F10

PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1

D9

PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

J4

PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15

F22

PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14

A23

PEG_HTX_GRX_P13 PEG_HTX_C_GRX_P13

D24

PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12

E21

PEG_HTX_GRX_P11 PEG_HTX_C_GRX_P11

G19

PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

B18

PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9

K17

PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8

G17

PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7

E14

PEG_HTX_GRX_P6 PEG_HTX_C_GRX_P6

C15

PEG_HTX_GRX_P5 PEG_HTX_C_GRX_P5

K13

PEG_HTX_GRX_P4 PEG_HTX_C_GRX_P4

G13

PEG_HTX_GRX_P3 PEG_HTX_C_GRX_P3

K10

PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2

G10

PEG_HTX_GRX_P1 PEG_HTX_C_GRX_P1

D8

PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0

K4

Typ- suggest 220nF. The change in AC capacitor
value from 10 0nF to 220nF is to enable
compati bilit y with futu re platforms having PCIE
Gen3 (8GT/s)

C16 0.1U_0402_16V7KOPT@

1 2

C17 0.1U_0402_16V7KOPT@

1 2

C18 0.1U_0402_16V7KOPT@

1 2

C19 0.1U_0402_16V7KOPT@

1 2

C20 0.1U_0402_16V7KOPT@

1 2

C21 0.1U_0402_16V7KOPT@

1 2

C22 0.1U_0402_16V7KOPT@

1 2

C23 0.1U_0402_16V7KOPT@

1 2

C24 0.1U_0402_16V7KOPT@

1 2

C25 0.1U_0402_16V7KOPT@

1 2

C26 0.1U_0402_16V7KOPT@

1 2

C27 0.1U_0402_16V7KOPT@

1 2

C28 0.1U_0402_16V7KOPT@

1 2

C29 0.1U_0402_16V7KOPT@

1 2

C30 0.1U_0402_16V7KOPT@

1 2

C31 0.1U_0402_16V7KOPT@

1 2

C32 0.1U_0402_16V7KOPT@

1 2

C33 0.1U_0402_16V7KOPT@

1 2

C34 0.1U_0402_16V7KOPT@

1 2

C35 0.1U_0402_16V7KOPT@

1 2

C36 0.1U_0402_16V7KOPT@

1 2

C37 0.1U_0402_16V7KOPT@

1 2

C38 0.1U_0402_16V7KOPT@

1 2

C39 0.1U_0402_16V7KOPT@

1 2

C40 0.1U_0402_16V7KOPT@

1 2

C41 0.1U_0402_16V7KOPT@

1 2

C42 0.1U_0402_16V7KOPT@

1 2

C43 0.1U_0402_16V7KOPT@

1 2

C44 0.1U_0402_16V7KOPT@

1 2

C45 0.1U_0402_16V7KOPT@

1 2

C46 0.1U_0402_16V7KOPT@

1 2

C47 0.1U_0402_16V7KOPT@

1 2

shorted and routed
with - max length = 50 0 mils - typical
impedan ce = 43 mohms
PEG_ICO MPO signals should be routed w ith ­max len gth = 500 mils

- typical impedance = 14.5 mohms

<P EG >

2

PEG_GTX_C_H RX_N[0..15]

PEG_GTX_C_HRX_P [0..15]

PEG_HTX_C _GRX_N[0..15]

PEG_HTX_C_GRX_P [0..15]

1

PEG_GTX_C_H RX_N[0..15] <22>

PEG_GTX_C_HRX_P[0..15] <2 2>

PEG_HTX_C _GRX_N[0..15] <22>

PEG_HTX_C_GRX_P [0..15] <22>

<P EG >

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

of

1

4 56Monday, A pril 11, 2011

1.0

5

D D

4

3

2

1

XDP_DBRESET#

R34 1K_0402_5%

+3VS

12

PVT:R emove X DP connector for ESD request

C C

H_SNB_IVB#<18>

PROC_DETECT (Processor Detect): pulled to
ground on the processor package. There is no
connection to the processor silicon for this
signal. System board designers may use this
signal to determine if the processor is present

H_PEC I<18,43>

H_PRO CHOT#<43,55>

H_THRMTRIP#<18>

B B

H_PM _SYNC<15>

H_CPU PWRGD<18>

Layout note: Route in High Speed layer to prevent EMC issue

+3VALW

+3VS

0.1U_0402_16V4Z

PM_DRAM_PWR GD<15>

A A

R2630 10K_0402_5%

5

1

C51

2

U4
74AHC1G09GW_TSSOP5

5

1

12

P

B

4

O

2

A

G

3

SUSP<46,50>

This pin is for compability with future
platforms. A pull up resistor to VCCIO is
required if connected to the DF_TVS strap
on the PCH.

R813 10K_0 402_5%

T5 P AD

1 2

R49 0_0402_5%

1 2

R50 56_0402_5%

1 2

R52 0_0402_5%

1 2

R53 0_0402_5%

1 2

R56 0_0402_5%

1 2

R59 130_0402_5%

+1.5V_ CPU_VDDQ

12

PM_SYS _PWRGD_BUF

12

R79

@

39_0402_5%

13

2

G

D

Q4

S

@

2N7002_SOT23-3

SUSP

@

1 2

H_CATERR #

H_PEC I_ISO

H_PRO CHOT#_R

H_THEMTRIP#_R

H_PM _SYNC_R

H_CPU PWRGD_R

PM_SYS _PWRGD_BUF_RPM_SYS _PWRGD_BUF

BUF_C PU_RST#

R76
200_0402_5%

4

U2B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWR OK

D44

RESET#

SAND Y-BRIDGE_BGA1023~D

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

MISC

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#

PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CLK_C PU_DMI#_R

H2

CLK_C PU_DPLL_R

AG3

CLK_C PU_DPLL#_R

AG1

CLK_RES_ITP

N59

CLK_RES_ITP#

N58

H_DRAMRST#

AT30

SM_RCOMP0

BF44

SM_RCOMP1

BE43

SM_RCOMP2

BG43

DDR3 Compensation Signals

N53
N55

XDP_TCK

L56

TCK

XDP_TMS

L55

TMS

XDP_TRST#

J58

XDP_TDI

M60

TDI

XDP_TDO

L59

TDO

XDP_DBRESET#

K58

G58
E55
E59
G55
G59
H60
J59
J61

2010/08/23 2011/08/25

CLK_C PU_DMI_R

J3

1 2

R44 0_0402_5%

1 2

R45 0_0402_5%

1 2

R47 0_0402_5%

1 2

R46 0_0402_5%

H_DRAMRST# <6>

R74 140_0402_1%
R75 25.5_0402_1%
R77 200_0402_1%

12
12
12

XDP_DBRESET# <15>

Compal Secret Data

Deciphered Date

CLK_CP U_DMI <14>
CLK_CP U_DMI# <14>

CLK_CP U_DPLL <14>
CLK_CP U_DPLL# <14>

PLT_RST#<17,2 2,37,41,43>

2

CLK_RES_ITP <14>
CLK_RES_ITP# <14>

SN74L VC1G07DCKR_SC70-5

PLT_RST#

Buffered reset to CPU

+3VS

+1.05VS

12

R58
75_0402_5%@

1 2

R64

1.5K_0402_5%

Processor Pullups

12

12

12

BUF_C PU_RST#

12

R69
750_0402_1%

H_PROCH OT#

H_CPU PWRGD_R

H_CPU PWRGD_R

@

1

NC

2

A

R956

0_0402_5%

1 2

1

C50

0.1U_0402_16V4Z

2

@

5

U3

P

BUFO_ CPU_RST#

4

Y

G

3

+1.05VS

R48 62_0402_5%

R51 10K_0402_5%

@

C2580 220P_0402_50V7K

PU/PD for JTAG signals

XDP_TMS

R80 51_0402_5%@

XDP_TDI

R81 51_0402_5%@

XDP_TDO

R82 51_0402_5%@

Layout note: Close to XDP

XDP_TCK

R83 51_0402_5%@

XDP_TRST#

R84 51_0402_5%@

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Doc ument Number Re v

Cus tom

Date: Sheet of

1

+1.05VS

12

12

12

12

12

5 56Monday, A pril 11, 2011

1.0

5

4

3

2

1

DDR_ A_D[0..63 ]<11>

D D

C C

DDR_A_BS 0<11>

B B

DDR_A_BS 1<11>
DDR_A_BS 2<11>

DDR_A _CAS#<11>
DDR_A _RAS#<11>
DDR_A_W E#<11>

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A _D10
DDR_A _D11
DDR_A _D12
DDR_A _D13
DDR_A _D14
DDR_A _D15
DDR_A _D16
DDR_A _D17
DDR_A _D18
DDR_A _D19
DDR_A _D20
DDR_A _D21
DDR_A _D22
DDR_A _D23
DDR_A _D24
DDR_A _D25
DDR_A _D26
DDR_A _D27
DDR_A _D28
DDR_A _D29
DDR_A _D30
DDR_A _D31
DDR_A _D32
DDR_A _D33
DDR_A _D34
DDR_A _D35
DDR_A _D36
DDR_A _D37
DDR_A _D38
DDR_A _D39
DDR_A _D40
DDR_A _D41
DDR_A _D42
DDR_A _D43
DDR_A _D44
DDR_A _D45
DDR_A _D46
DDR_A _D47
DDR_A _D48
DDR_A _D49
DDR_A _D50
DDR_A _D51
DDR_A _D52
DDR_A _D53
DDR_A _D54
DDR_A _D55
DDR_A _D56
DDR_A _D57
DDR_A _D58
DDR_A _D59
DDR_A _D60
DDR_A _D61
DDR_A _D62
DDR_A _D63

U2C

AG6

SA_DQ[0]

AJ6

SA_DQ[1]

AP11

SA_DQ[2]

AL6

SA_DQ[3]

AJ10

SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]

AR11

SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]

AT13

SA_DQ[14]

AU13

SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]

BA13

SA_DQ[18]

BB11

SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]

AY13

SA_DQ[23]

AV14

SA_DQ[24]

AR14

SA_DQ[25]

AY17

SA_DQ[26]

AR19

SA_DQ[27]

BA14

SA_DQ[28]

AU14

SA_DQ[29]

BB14

SA_DQ[30]

BB17

SA_DQ[31]

BA45

SA_DQ[32]

AR43

SA_DQ[33]

AW48

SA_DQ[34]

BC48

SA_DQ[35]

BC45

SA_DQ[36]

AR45

SA_DQ[37]

AT48

SA_DQ[38]

AY48

SA_DQ[39]

BA49

SA_DQ[40]

AV49

SA_DQ[41]

BB51

SA_DQ[42]

AY53

SA_DQ[43]

BB49

SA_DQ[44]

AU49

SA_DQ[45]

BA53

SA_DQ[46]

BB55

SA_DQ[47]

BA55

SA_DQ[48]

AV56

SA_DQ[49]

AP50

SA_DQ[50]

AP53

SA_DQ[51]

AV54

SA_DQ[52]

AT54

SA_DQ[53]

AP56

SA_DQ[54]

AP52

SA_DQ[55]

AN57

SA_DQ[56]

AN53

SA_DQ[57]

AG56

SA_DQ[58]

AG53

SA_DQ[59]

AN55

SA_DQ[60]

AN52

SA_DQ[61]

AG55

SA_DQ[62]

AK56

SA_DQ[63]

BD37

SA_BS[0]

BF36

SA_BS[1]

BA28

SA_BS[2]

BE39

SA_CAS#

BD39

SA_RAS#

AT41

SA_WE#

SAND Y-BRIDGE_BGA1023~D

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AU36
AV36
AY26

AT40
AU40
BB26

BB40
BC41

AY40
BA41

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

M_CLK_DD R0
M_CLK_DDR#0
DDR_CKE 0_DIMMA

DDR_A _DQS#0
DDR_A _DQS#1
DDR_A _DQS#2
DDR_A _DQS#3
DDR_A _DQS#4
DDR_A _DQS#5
DDR_A _DQS#6
DDR_A _DQS#7

DDR_A _DQS0
DDR_A _DQS1
DDR_A _DQS2
DDR_A _DQS3
DDR_A _DQS4
DDR_A _DQS5
DDR_A _DQS6
DDR_A _DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DD R0 <11>
M_CLK_DD R#0 <11>
DDR_C KE0_DIMMA <11>

M_CLK_DD R1 <11>
M_CLK_DD R#1 <11>
DDR_C KE1_DIMMA <11>

DDR_C S0_DIMMA# <11>
DDR_C S1_DIMMA# <11>

M_ODT0 <11>
M_ODT1 <11>

DDR_A _DQS#[0.. 7] <11>

DDR_ A_DQS[0.. 7] <11>

DDR_A _MA[0..15] <11>

DDR_ B_D[0..63 ]<12>

DDR_B_BS 0<12>
DDR_B_BS 1<12>
DDR_B_BS 2<12>

DDR_B _CAS#<12>
DDR_B _RAS#<12>
DDR_B _WE#<12>

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B _D10
DDR_B _D11
DDR_B _D12
DDR_B _D13
DDR_B _D14
DDR_B _D15
DDR_B _D16
DDR_B _D17
DDR_B _D18
DDR_B _D19
DDR_B _D20
DDR_B _D21
DDR_B _D22
DDR_B _D23
DDR_B _D24
DDR_B _D25
DDR_B _D26
DDR_B _D27
DDR_B _D28
DDR_B _D29
DDR_B _D30
DDR_B _D31
DDR_B _D32
DDR_B _D33
DDR_B _D34
DDR_B _D35
DDR_B _D36
DDR_B _D37
DDR_B _D38
DDR_B _D39
DDR_B _D40
DDR_B _D41
DDR_B _D42
DDR_B _D43
DDR_B _D44
DDR_B _D45
DDR_B _D46
DDR_B _D47
DDR_B _D48
DDR_B _D49
DDR_B _D50
DDR_B _D51
DDR_B _D52
DDR_B _D53
DDR_B _D54
DDR_B _D55
DDR_B _D56
DDR_B _D57
DDR_B _D58
DDR_B _D59
DDR_B _D60
DDR_B _D61
DDR_B _D62
DDR_B _D63

U2D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

SAND Y-BRIDGE_BGA1023~D

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

DDR_B _DQS#0
DDR_B _DQS#1
DDR_B _DQS#2
DDR_B _DQS#3
DDR_B _DQS#4
DDR_B _DQS#5
DDR_B _DQS#6
DDR_B _DQS#7

DDR_B _DQS0
DDR_B _DQS1
DDR_B _DQS2
DDR_B _DQS3
DDR_B _DQS4
DDR_B _DQS5
DDR_B _DQS6
DDR_B _DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DD R2 <12>
M_CLK_DD R#2 <12>
DDR_C KE2_DIMMB <12>

M_CLK_DD R3 <12>
M_CLK_DD R#3 <12>
DDR_C KE3_DIMMB <12>

DDR_C S2_DIMMB# <12>
DDR_C S3_DIMMB# <12>

M_ODT2 <12>
M_ODT3 <12>

DDR_B _DQS#[0.. 7] <12>

DDR_ B_DQS[0.. 7] <12>

DDR_B _MA[0..15] <12>

R88

@

0_0402_5%

1 2

D

S

DDR3_ DRAMRST#_RH_DRAMRST#

1 2

13

Q5

G

BSS138_NL_SOT23-3

2

0.047U_0402_16V 4Z

C52

1

2

H_DRAMRST#<5>

R91

4.99K_0402_1%

A A

DRAMRST_CNTRL

DRAMRS T_CNTRL_PCH<14>

1 2

R92 0_0402_5%

5

+1.5V

R89

1K_0402_5%

12

1 2

R90 1K_0402_5%

4

DDR3_DRA MRST# <11,12>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

6 56Monday, A pril 11, 2011

1

1.0

5

4

3

2

1

CFG Straps for Processor

CFG2

12

R94

D D

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

U2E

B50

CFG[0]

C51

CFG2

CFG4
CFG5
CFG6
CFG7

C C

@

+CPU_C ORE

+VGFX_CORE

12

12

R96

1K_0402_1%

B B

1 2

R858 49.9_0402_1%

@

R859 49.9_0402_1%

@

1 2

R860 49.9_0402_1%

@

R861 49.9_0402_1%

CPU_R SVD6
CPU_R SVD7

R97
1K_0402_1%

12

12

VCC_VAL_SENSE
VSS_VAL_SENSE

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

SAND Y-BRIDGE_BGA1023~D

RESERVED

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

RSVD28
RSVD29

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RSVD45

BE7
BG7

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

Display Port Presence Strap

PCIE Port Bifurcation Straps

CFG[6:5 ]

*

CFG4

CFG4

*

1K_0402_1%

11: (Def aul t) x 16 - Devic e 1 functi ons 1 and 2 disabled

*

10: x8, x8 - Devi ce 1 funct ion 1 enab led ; func tion 2
d isabled

01: Rese rve d - (Device 1 function 1 disabled ; function
2 enabled )

00: x8,x 4,x 4 - Devi ce 1 funct ions 1 and 2 enable d

1K_0402_1%

1: N orma l O peration ; Lane # definition matches
sock et p in map def inition

0:La ne Revers ed

12

R95

@

1K_0402_1%

1 : Disa bled; No Physi cal Displa y Port
atta ched to Embe dded Displ ay Port

0 : Enab led ; An ext ernal Disp lay Port d evice is
conn ecte d to the Embed ded Displa y Port

CFG6

CFG5

12

12

R98

@

CFG7

12

@

R99

@

1K_0402_1%

R100
1K_0402_1%

PEG DEFER TRAINING

1: ( Defa ult ) PEG Train imme diately fo llowing xx RESETB

CFG7

de as sertion

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

0: P EG W ait for BIOS for t raining

Title

PROCESSOR(4/7) RSVD,CFG

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

1

7 56Sunday, April 10, 20 11

1.0

5

1.9m[ Loadline Design

+CPU_C ORE

Mid-Frequency D eco upling

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C761

1

1

C104

2

D D

C C

2

22U_0805_6.3V6M

C762

1

2

22U_0805_6.3V6M

C100

1

2

Low-Frequency D eco upling

330U_ D2_2V_Y

1

C105

+

2

DVT:Reserved C918 (Co-layout C106)

High-Frequency Dec oup ling

2.2U_0402_6.3V6M

C769

1

2

2.2U_0402_6.3V6M

C777

1

B B

A A

5

2

2.2U_0402_6.3V6M

C785

1

2

2.2U_0402_6.3V6M

C793

1

2

2.2U_0402_6.3V6M

C801

1

2

22U_0805_6.3V6M

C86

1

2

1

2

1

2

1

+

2

C87

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C94

C95

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C98

C99

1

2

330U_ D2_2V_Y

330U_ D2_2V_Y

1

C106

C107

+

2

DVT:Update C105 C106 C107 C108 footprint

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C770

1

2

1

2

1

2

1

2

1

2

C771

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C778

C779

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C786

C787

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C794

C795

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C802

C803

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C88

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C93

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C97

1

1

2

2

330U_ D2_2V_Y

1

C108

+

Note:
2Pin 470uF PN SGA00004200
Need confirm Type with Power Team before SMT

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C772

1

1

2

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C780

1

1

2

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C788

1

1

2

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C796

1

1

2

2

22U_0805_6.3V6M

C89

1

2

22U_0805_6.3V6M

C92

1

2

22U_0805_6.3V6M

C96

1

2

2.2U_0402_6.3V6M

C773

1

2

2.2U_0402_6.3V6M

C781

1

2

2.2U_0402_6.3V6M

C789

1

2

2.2U_0402_6.3V6M

C797

1

2

4

SV type CPU

22U_0805_6.3V6M

C672

C90

C91

C101

C774

C782

C790

C798

4

1

1

2

2

22U_0805_6.3V6M

C763

1

1

2

2

22U_0805_6.3V6M

1

1

C102

2

2

2.2U_0402_6.3V6M

C775

1

1

2

2

2.2U_0402_6.3V6M

C783

1

1

2

2

2.2U_0402_6.3V6M

C791

1

1

2

2

2.2U_0402_6.3V6M

C799

1

1

2

2

3

U2F

18A

AF46

VCCIO[1]

AG48

53A

22U_0805_6.3V6M

C670

22U_0805_6.3V6M

C764

22U_0805_6.3V6M

C103

2.2U_0402_6.3V6M

C776

2.2U_0402_6.3V6M

C784

2.2U_0402_6.3V6M

C792

2.2U_0402_6.3V6M

C800

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

SAND Y-BRIDGE_BGA1023~D

CORE SUPPLY

POWER

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]

VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]

PEG AND DDRSENSE LINES SVID QUIET RAILS

VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

VCCIO50

VCCIO51

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

W16
W17

BC22

AM25
AN22

H_CPU _SVIDALRT#

A44

H_CPU _SVIDCLK

B43

H_CPU _SVIDDAT

C44

VCCS ENSE_R

F43

VSSSENSE_R

G43

VCCIO_S ENSE

AN16

VSS_SE NSE_VCCIO

AN17

2010/08/23 2011/08/25

Mid-Frequency D eco upling

10U_0603_6.3V6M

1

C53

2

High-Frequency Dec oup ling

1U_0402_6.3V6K

1

C68

2

1U_0402_6.3V6K

1

C503

2

1U_0402_6.3V6K

1

C721

2

Mid-Frequency D eco upling

330U_ D2_2V_Y

1

C83

+

2

1 2

R862 0_0805_5%

PAD@

T85

+1.05VS

2

C722
1U_0402_6.3V6K

1

R108 0_0402_5%

1 2

R109 0_0402_5%

1 2

Compal Secret Data

Deciphered Date

2

10U_0603_6.3V6M

1

C54

2

1U_0402_6.3V6K

1

C69

2

1U_0402_6.3V6K

1

C527

2

1U_0402_6.3V6K

1

C648

2

330U_ D2_2V_Y

1

C84

+

2

+1.05VS

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

2

1

2

1

2

1

2

C56

C55

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C71

C70

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C505

C507

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C646

C655

2

12

R102
130_0402_5%

Pla ce th e PU re si stor s cl ose to CP U

1 2

R107 100_0402_1%

1 2

R111 100_0402_1%

Pla ce th e PU re sis tors clo se t o VR

R954 10_0402_5%

1 2

@

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

2

1

2

1

2

1

2

R104 43_0402_1%
R105 0_0402_5%
R106 0_0402_5%

C57

1U_0402_6.3V6K

C72

1U_0402_6.3V6K

C509

1U_0402_6.3V6K

C647

1 2
1 2
1 2

C58

2

1U_0402_6.3V6K

1

C73

2

1U_0402_6.3V6K

1

C506

2

1U_0402_6.3V6K

1

C528

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C59

2

1U_0402_6.3V6K

1

C74

2

1U_0402_6.3V6K

1

C136

2

+1.05VS+1.05VS

+CPU_ CORE

12

1

C60

2

1U_0402_6.3V6K

1

C75

2

1U_0402_6.3V6K

1

C504

2

R103
75_0402_5%

1

2

1

2

1

2

+1.05VS

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

1

+1.05VS

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C61

C62

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C508

C76

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C529

C649

2

VR_SVID_ALR T# <54>
VR_SV ID_CLK <54>
VR_SVID_DAT <54>

VCCSENS E <54>
VSSSENSE <54>

VCCIO_S ENSE <51>
VSS_SE NSE_VCCIO <51>

1

8 56Sunday, April 10, 20 11

1.0

5

4

3

2

1

GT2 3.9mΩ Loadline Design

+VGFX_CORE

D D

C C

Mid-Frequency D eco upling

22U_0805_6.3V6M

C111

1

2

10U_0603_6.3V6M

1

C114

2

Low-Frequency D eco upling

330U_ D2_2V_Y

1

C131

+

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C112

1

2

10U_0603_6.3V6M

1

C122

2

470U_ D2_2V_Y

1

C132

+

Note:
2Pin 470uF PN SGA00004200
Need confirm Type with Power Team before SMT

2

22U_0805_6.3V6M

C113

1

2

1

2

C118

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C116

1

C115

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C120

C119

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C117

C123

2

DVT:Update C131 C132 footprint

High-Frequency Dec oup ling

1

2

1

2

B B

+VCCSA

330U_ D2_2V_Y

1

C142

+

2

Low -F req ue nc y Dec oupl ing

A A

VCC_AXG_SENSE<54>
VSS_AXG_SENSE<54>

PVT:< Memo>

5

1U_0402_6.3V6K

1U_0402_6.3V6K

C836

C835

1U_0402_6.3V6K

C841

1

1

2

2

1U_0402_6.3V6K

C842

1

1

2

2

+1.8VS

10U_0603_6.3V6M

1

2

Low -F req ue nc y Dec oupl ing

10U_0603_6.3V6M

10U_0603_6.3V6M

C143

C144

1

2

Hig h- Fre qu en cy De coup ling

1U_0402_6.3V6K

1U_0402_6.3V6K

C846

C847

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C838

C837

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C843

C844

1

1

2

2

R934 0_0402_5%

1 2

R935 0_0402_5%

1 2

10U_0603_6.3V6M

@

C916

C915

1

1

2

2

10U_0603_6.3V6M

C145

C146

1

1

2

2

1U_0402_6.3V6K

C848

C849

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C839

C840

1

2

1U_0402_6.3V6K

C845

C138

330U_ D2_2V_Y

C140

1U_0402_6.3V6K

1

+

@

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C765

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C850

1

1

2

2

26A

C141

1U_0402_6.3V6K

1

2

4

6A

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46

W50
W51
W52
W53
W55
W56
W61

BC1
BC4

W20

N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59

Y48
Y61

F45
G45

BB3

L17

L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21

U2G

VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]

VAXG_SENSE
VSSAXG_SENSE

GRAPHI CS

LINES

1.8V R AIL

VCCPLL[1]
VCCPLL[2]
VCCPLL[3]

VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]

SAND Y-BRIDGE_BGA1023~D

SA RAIL

POWER

SENSE

+V_SM_VREF,+V_SM_VREF_CNT should
have 20 mil trace width

+V_SM_VREF_CNT +V_SM_VREF

AY43

DDR3 - 1.5V RAILS

SM_VREF

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]

VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

5A

C121

0.1U_0402_16V4Z

High-Frequency Dec oup ling

1U_0402_6.3V6K

1U_0402_6.3V6K

C824

C825

1

2

Mid-Frequency D eco upling

10U_0603_6.3V6M

C133

1

2

1

1

2

2

10U_0603_6.3V6M

C134

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C827

C826

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C124

C125

1

2

R112 0_0402_ 5%

1

2

1U_0402_6.3V6K

C828

1

1

2

2

10U_0603_6.3V6M

C126

1

1

2

2

Low-Frequency D eco upling

1

+

C130
330U_2.5V_M

2

+1.5V_ CPU_VDDQ

AM28

VCCDQ[1]

AN26

VCCDQ[2]

QUIET RAILS

Issued Date

BC43
BA43

U10

D48
D49

3

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

Secur ity Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C723
1U_0402_6.3V6K

2

T86PAD
T87PAD

VCCSA_SENSE

VCCS A_VID0
VCCS A_VID1

VCCS A_VID1 <52>

2010/08/23 2011/08/25

Compal Secret Data

DVT:Update C130 footprint

12

Deciphered Date

R863
10K_0402_5%

2

12

1U_0402_6.3V6K

1U_0402_6.3V6K

C829

1

2

10U_0603_6.3V6M

C127

1

2

1U_0402_6.3V6K

C830

C831

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C129

C128

1

2

Vaxg

Can connec t to G ND if motherbo

‧‧‧‧

supports external graphics and if GFX VR is not
stuffed in a common motherboard design,

V AX

‧‧‧‧

G can be left floating in a common
motherboard d esign (Gfx VR keeps VAXG from
floating) if the VR is stuffed

VCCSA_SENSE <52>

R124
0_0402_5%@

1 2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

+1.5V_ CPU_VDDQ

12

R113
1K_0402_1%

12

R115
1K_0402_1%

+1.5V_ CPU_VDDQ +1.5VS

1U_0402_6.3V6K

1U_0402_6.3V6K

C833

C832

1

2

ard only

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

1

@

JP100

1 2

PAD-OP EN 4x4m

Need to open

9 56Sunday, April 10, 20 11

1.0

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_ CPU_VDDQ

Q7

B+_BIAS

D D

C C

B B

A A

U2H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]

AA13

VSS[14]

AA50

VSS[15]

AA51

VSS[16]

AA52

VSS[17]

AA53

VSS[18]

AA55

VSS[19]

AA56

VSS[20]

AA8

VSS[21]

AB16

VSS[22]

AB18

VSS[23]

AB21

VSS[24]

AB48

VSS[25]

AB61

VSS[26]

AC10

VSS[27]

AC14

VSS[28]

AC46

VSS[29]

AC6

VSS[30]

AD17

VSS[31]

AD20

VSS[32]

AD4

VSS[33]

AD61

VSS[34]

AE13

VSS[35]

AE8

VSS[36]

AF1

VSS[37]

AF17

VSS[38]

AF21

VSS[39]

AF47

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AF51

VSS[43]

AF52

VSS[44]

AF53

VSS[45]

AF55

VSS[46]

AF56

VSS[47]

AF58

VSS[48]

AF59

VSS[49]

AG10

VSS[50]

AG14

VSS[51]

AG18

VSS[52]

AG47

VSS[53]

AG52

VSS[54]

AG61

VSS[55]

AG7

VSS[56]

AH4

VSS[57]

AH58

VSS[58]

AJ13

VSS[59]

AJ16

VSS[60]

AJ20

VSS[61]

AJ22

VSS[62]

AJ26

VSS[63]

AJ30

VSS[64]

AJ34

VSS[65]

AJ38

VSS[66]

AJ42

VSS[67]

AJ45

VSS[68]

AJ48

VSS[69]

AJ7

VSS[70]

AK1

VSS[71]

AK52

VSS[72]

AL10

VSS[73]

AL13

VSS[74]

AL17

VSS[75]

AL21

VSS[76]

AL25

VSS[77]

AL28

VSS[78]

AL33

VSS[79]

AL36

VSS[80]

AL40

VSS[81]

AL43

VSS[82]

AL47

VSS[83]

AL61

VSS[84]

AM13

VSS[85]

AM20

VSS[86]

AM22

VSS[87]

AM26

VSS[88]

AM30

VSS[89]

AM34

VSS[90]

SAND Y-BRIDGE_BGA1023~D

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

R120

0_0402_5%

CPU1.5V_S3_GATE<43>

SUSP#<43,46,51>

1 2

R121

@

0_0402_5%

1 2

+3VALW

12

R118
100K_0402_5%

61

Q8A
2N7002DW-T/R7_SOT363-6

2

U2I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G48

VSS[221]

G51

VSS[222]

G6

VSS[223]

G61

VSS[224]

H10

VSS[225]

H14

VSS[226]

H17

VSS[227]

H21

VSS[228]

H4

VSS[229]

H53

VSS[230]

H58

VSS[231]

J1

VSS[232]

J49

VSS[233]

J55

VSS[234]

K11

VSS[235]

K21

VSS[236]

K51

VSS[237]

K8

VSS[238]

L16

VSS[239]

L20

VSS[240]

L22

VSS[241]

L26

VSS[242]

L30

VSS[243]

L34

VSS[244]

L38

VSS[245]

L43

VSS[246]

L48

VSS[247]

L61

VSS[248]

M11

VSS[249]

M15

VSS[250]

SAND Y-BRIDGE_BGA1023~D

VSS

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

R116
100K_0402_5%

RUN_O N_CPU1.5VS3

3

Q8B
2N7002DW-T/R7_SOT363-6

5

4

330K_0402_5%

M4

VSS[251]

M58

VSS[252]

M6

VSS[253]

N1

VSS[254]

N17

VSS[255]

N21

VSS[256]

N25

VSS[257]

N28

VSS[258]

N33

VSS[259]

N36

VSS[260]

N40

VSS[261]

N43

VSS[262]

N47

VSS[263]

N48

VSS[264]

N51

VSS[265]

N52

VSS[266]

N56

VSS[267]

N61

VSS[268]

P14

VSS[269]

P16

VSS[270]

P18

VSS[271]

P21

VSS[272]

P58

VSS[273]

P59

VSS[274]

P9

VSS[275]

R17

VSS[276]

R20

VSS[277]

R4

VSS[278]

R46

VSS[279]

T1

VSS[280]

T47

VSS[281]

T50

VSS[282]

T51

VSS[283]

T52

VSS[284]

T53

VSS[285]

T55

VSS[286]

T56

VSS[287]

U13

VSS[288]

U8

VSS[289]

V20

VSS[290]

V61

VSS[291]

W13

VSS[292]

W15

VSS[293]

W18

VSS[294]

W21

VSS[295]

W46

VSS[296]

W8

VSS[297]

Y4

VSS[298]

Y47

VSS[299]

Y58

VSS[300]

Y59

VSS[301]

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9

VSS_NCTF_10

NCTF

VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

2010/08/23 2011/08/25

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

Compal Secret Data

AO4728L_SO8

8
7
6
5

12

R119

Deciphered Date

1
2
3

4

1

C137

0.1U_0402_16V4Z

2

2

R117
220_0402_5%

1 2
61

RUN_O N_CPU1.5VS3#RUN_O N_CPU1.5VS3#

2

Q9A
2N7002DW-T/R7_SOT363-6

Q9A on P46

+1.5V +1.5V_ CPU_VDDQ

Title

PROCESSOR(7/7) VSS

Size Doc ument Number Re v

Cus tom

Date: Sheet

1 2

C2596 0.1U _0402_16V4Z

1 2

C2597 0.1U _0402_16V4Z

1 2

C2598 0.1U _0402_16V4Z

1 2

C2599 0.1U _0402_16V4Z

Compal Electronics, Inc.

1

10 56Monday , April 11, 2011

of

1.0

5

All VREF traces should
have 10 mil trace width

D D

+1.5 V

12

R2 017
1K_ 0402_1%

12

R2 018
1K_ 0402_1%

C C

12

R2 609
1K_ 0402_1%

12

R2 612
1K_ 0402_1%

B B

+VR EF_D Q_DIMMA

+VR EF_C A_DIMMA+1.5 V

4

+VR EF_D Q_DIMMA +1.5V

2.2U _0603 _6.3V6K

+3VS

+0.75 VS

0.1U _0402 _16V4Z

C2 023

C2 000

1

1

2

2

DDR_ CKE0 _DIM MA<6>

DD R_A_B S2<6>

M_ CLK_D DR0<6>
M_C LK_DD R#0<6>

DD R_A_B S0<6>

DD R_A_ WE#<6>
DD R_A_ CAS#<6>

DDR_ CS1_ DIMM A#<6>

C2 042

0.1U _0402 _16V4Z

1

2

DDR_ CKE0 _DIM MA

DD R_A_ BS2

C2 043

2.2U _0603 _6.3V6K

1

2

DD R_A _D0
DD R_A _D1

DD R_A_ DM0

DD R_A _D2
DD R_A _D3

DD R_A _D8
DD R_A _D9

DD R_A_ DQS# 1
DD R_A _DQS 1

DD R_A _D10
DD R_A _D11

DD R_A _D16
DD R_A _D17

DD R_A_ DQS# 2
DD R_A _DQS 2

DD R_A _D18
DD R_A _D19

DD R_A _D24
DD R_A _D25

DD R_A_ DM3

DD R_A _D26
DD R_A _D27

DDR_ A_MA 12
DDR_ A_M A9

DDR_ A_M A8
DDR_ A_M A5

DDR_ A_M A3
DDR_ A_M A1

M _CLK_ DDR0
M _CLK_ DDR#0

DDR_ A_MA 10
DD R_A_ BS0

DD R_A _WE#
DD R_A_ CAS#

DDR_ A_MA 13

DDR_ CS1_ DIMM A#

DD R_A _D32
DD R_A _D33

DD R_A_ DQS# 4
DD R_A _DQS 4

DD R_A _D34
DD R_A _D35

DD R_A _D40
DD R_A _D41

DD R_A_ DM5

DD R_A _D42
DD R_A _D43

DD R_A _D48
DD R_A _D49

DD R_A_ DQS# 6
DD R_A _DQS 6

DD R_A _D50
DD R_A _D51

DD R_A _D56
DD R_A _D57

DD R_A_ DM7

DD R_A _D58
DD R_A _D59

12

3

VSS3

DQS#0

DQS0
VSS6

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5
VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

DM6

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7
VSS50

DQ62

DQ63
VSS52

EVENT#

SDA

VTT2

+1.5 V

2

DD R_A _D4

4

DQ4
DQ5

DQ6
DQ7

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

SCL

G2

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DD R_A _D5

DD R_A_ DQS# 0
DD R_A _DQS 0

DD R_A _D6
DD R_A _D7

DD R_A _D12
DD R_A _D13

DD R_A_ DM1
DD R3_DR AMRS T#

DD R_A _D14
DD R_A _D15

DD R_A _D20
DD R_A _D21

DD R_A_ DM2

DD R_A _D22
DD R_A _D23

DD R_A _D28
DD R_A _D29

DD R_A_ DQS# 3
DD R_A _DQS 3

DD R_A _D30
DD R_A _D31

DDR_ CKE1 _DIM MA

DDR_ A_MA 15
DDR_ A_MA 14

DDR_ A_MA 11
DDR_ A_M A7

DDR_ A_M A6
DDR_ A_M A4

DDR_ A_M A2
DDR_ A_M A0

M _CLK_ DDR1
M _CLK_ DDR#1

DD R_A_ BS1
DD R_A_ RAS#

DDR_ CS0_ DIMM A#
M_OD T0

M_OD T1

DD R_A _D36
DD R_A _D37

DD R_A_ DM4

DD R_A _D38
DD R_A _D39

DD R_A _D44
DD R_A _D45

DD R_A_ DQS# 5
DD R_A _DQS 5

DD R_A _D46
DD R_A _D47

DD R_A _D52
DD R_A _D53

DD R_A_ DM6

DD R_A _D54
DD R_A _D55

DD R_A _D60
DD R_A _D61

DD R_A_ DQS# 7
DD R_A _DQS 7

DD R_A _D62
DD R_A _D63

D_CK _SD ATA
D_ CK_S CLK

+0.7 5VS

DD R3_DR AMRS T# <6,12 >

DDR_ CKE1 _DIM MA <6>

M_ CLK_D DR1 <6>
M_C LK_DD R#1 <6>

DD R_A_B S1 <6>
DD R_A_ RAS# <6>

DDR_ CS0_ DIMM A# <6>
M_ODT 0 <6>

M_ODT 1 <6>

+VR EF_C A_DIMMA

2.2U _0603 _6.3V6K
C2 036

1

2

D_CK _SDA TA <12 ,14,41>
D_ CK_SC LK <12 ,14,41>

C2 037

0.1U _0402 _16V4Z

1

2

JDI MM0

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

R2 028

10K _0402_5%

203

R2 029

10K _0402_5%

205

1 2

VREF_CA
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

G1

FOX _AS0 A626-U4S N-7F

CO NN@

2

Layout Note:

+1.5 V

1

2

+1.5 V

1

2

+0.7 5VS

1

2

Place near J DIMM0

C2 025

1U_0 402_6 .3V6K

C2 024

1U_0 402_6 .3V6K

1

2

C2 030

10U_ 0603_6. 3V6M

C2 029

10U_ 0603_6. 3V6M

1

1

2

2

Layout Note:
Place near J DIMM0. 203,204

C2 039

1U_0 402_6 .3V6K

C2 038

1U_0 402_6 .3V6K

1

2

DD R_A_ DM0
DD R_A_ DM1
DD R_A_ DM2
DD R_A_ DM3
DD R_A_ DM4
DD R_A_ DM5
DD R_A_ DM6
DD R_A_ DM7

C2 026

1U_0 402_6 .3V6K

1

2

C2 031

10U_ 0603_6. 3V6M

1

2

C2 040

1U_0 402_6 .3V6K

1

2

DD R_A_ DQS# [0..7 ] <6>

DD R_A _DQS [0..7 ] <6>

DD R_A _D[0 ..63] <6>

DDR_ A_MA [0.. 15] <6>

C2 027

1U_0 402_6 .3V6K

1

2

C2 032

10U_ 0603_6. 3V6M

C2 033

10U_ 0603_6. 3V6M

1

1

2

2

C2 041

1U_0 402_6 .3V6K

1

2

C2 035

10U_ 0603_6. 3V6M

C2 034

10U_ 0603_6. 3V6M

1

1

+

C2 028
330U _2.5V_M

2

2

DVT:Update C2028 footprint

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber R ev

Cu stom

Da te: She et of

Compal Electronics, Inc.

DDRIII DIMMA

LA -71 41P

1

11 5 6Mond ay, A pril 11, 2011

1. 0

5

All VREF traces should

+1.5V

D D

+1.5V +VREF_CA_DIMMB

C C

B B

A A

R167

1K_0402_1%

R168

1K_0402_1%

12

R165
1K_0402_1%

12

R166
1K_0402_1%

12

12

+VREF_DQ_DIMMB

have 10 mil trace width

+3VS

+0.75VS

4

+1.5V

DDR_B _D0
DDR_B _D1

DDR_B_DM 0

DDR_B _D2
DDR_B _D3

DDR_B _D8
DDR_B _D9

DDR_B _DQS#1
DDR_B _DQS1

DDR_B _D10
DDR_B _D11

DDR_B _D16
DDR_B _D17

DDR_B _DQS#2
DDR_B _DQS2

DDR_B _D18
DDR_B _D19

DDR_B _D24
DDR_B _D25

DDR_B_DM 3

DDR_B _D26
DDR_B _D27

DDR_CKE 2_DIMMB

DDR_B_BS 2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DD R2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS 0

DDR_B_W E#
DDR_B _CAS#

DDR_B_MA13
DDR_C S3_DIMMB#

DDR_B _D32
DDR_B _D33

DDR_B _DQS#4
DDR_B _DQS4

DDR_B _D34
DDR_B _D35

DDR_B _D40
DDR_B _D41

DDR_B_DM 5

DDR_B _D42
DDR_B _D43

DDR_B _D48
DDR_B _D49

DDR_B _DQS#6
DDR_B _DQS6

DDR_B _D50
DDR_B _D51

DDR_B _D56
DDR_B _D57

DDR_B_DM 7

DDR_B _D58
DDR_B _D59

10K_0402_5%

12

DDR_CKE 2_DIMMB<6>

DDR_CS3_D IMMB#<6>

1

2

+VREF_DQ_DIMMB

C165

2.2U_0603_6.3V6K

1

2

DDR_B_BS 2<6>

M_CLK_DD R2<6>
M_CLK_DD R#2<6>

DDR_B_BS 0<6>

DDR_B _WE#<6>
DDR_B _CAS#<6>

R177 10K_0 402_5%

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

C185

C186

1

2

C166

0.1U_0402_16V4Z

1

2

1 2

11
13
15
17
19
21
23
25
27

33
35

39
41

45
47
49
51
53
55
57
59

63

67
69

73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205

R178

3

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS129RESET#
VSS1131VSS12
DQ10
DQ11
VSS1337VSS14
DQ16
DQ17
VSS1543VSS16
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS2261DQS#3
DM3
VSS2365VSS24
DQ26
DQ27
VSS2571VSS26

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

G1

FOX_AS0A626-U8SN-7F

CONN@

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2

2

+1.5V

2

DDR_B _D4

4

DDR_B _D5

6
8

DDR_B _DQS#0

10

DDR_B _DQS0

12
14

DDR_B _D6

16

DDR_B _D7

18
20

DDR_B _D12

22

DDR_B _D13

24
26

DDR_B_DM 1

28

DDR3_DRA MRST#

30
32

DDR_B _D14

34

DDR_B _D15

36
38

DDR_B _D20

40

DDR_B _D21

42
44

DDR_B_DM 2

46
48

DDR_B _D22

50

DDR_B _D23

52
54

DDR_B _D28

56

DDR_B _D29

58
60

DDR_B _DQS#3

62

DDR_B _DQS3

64
66

DDR_B _D30

68

DDR_B _D31

70
72

DDR_CKE 3_DIMMB

74
76

DDR_B_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DD R3
M_CLK_DDR#3

DDR_B_BS 1
DDR_B _RAS#

DDR_C S2_DIMMB#
M_ODT2

M_ODT3

DDR_B _D36
DDR_B _D37

DDR_B_DM 4

DDR_B _D38
DDR_B _D39

DDR_B _D44
DDR_B _D45

DDR_B _DQS#5
DDR_B _DQS5

DDR_B _D46
DDR_B _D47

DDR_B _D52
DDR_B _D53

DDR_B_DM 6

DDR_B _D54
DDR_B _D55

DDR_B _D60
DDR_B _D61

DDR_B _DQS#7
DDR_B _DQS7

DDR_B _D62
DDR_B _D63

D_CK_SDATA
D_CK_SCLK

+0.75VS

DDR3_ DRAMRST# <6,11>

DDR_CKE 3_DIMMB <6>

M_CLK_DD R3 <6>
M_CLK_DD R#3 <6>

DDR_B_BS 1 <6>
DDR_B _RAS# <6>

DDR_C S2_DIMMB# <6>
M_ODT2 <6>

M_ODT3 <6>

+VREF_CA_DIMMB

C183

2.2U_0603_6.3V6K

1

2

D_CK_SDATA <11,14,41>
D_CK_SCLK <11,14,41>

+1.5V

C168

1U_0402_6.3V6K

C167

1U_0402_6.3V6K

1

1

2

2

Layou t Note:

C171

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

2

2

Plac e near JDIMM1

C172

10U_0603_6.3V6M

1

2

+1.5V

DVT:Up date C178 foo tprint and SMT memo

Layou t Note:

+0.75VS

C184

0.1U_0402_16V4Z

1

2

1

2

Plac e ne ar JDIMM1. 203,204

C179

1U_0402_6.3V6K

C180

1U_0402_6.3V6K

1

2

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

C169

1U_0402_6.3V6K

1

2

C173

1

2

C181

1U_0402_6.3V6K

1

2

1

DDR_B _DQS#[0.. 7] <6>

DDR_ B_DQS[0.. 7] <6>

DDR _B_D[0..6 3] <6>

DDR_B _MA[0..15] <6>

C170

1U_0402_6.3V6K

1

2

C174

10U_0603_6.3V6M

C175

10U_0603_6.3V6M

1

2

C182

1U_0402_6.3V6K

1

2

C176

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_2.5V_M

C177

1

1

2

C178

1

+

2

2

@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMB

1

1.0

of

12 56Monday , April 11, 2011

5

PCH_RTCX1

1 2

R179 10M_0402_5%

Y2

1

C188
15P_0402_50V8J

D D

2

32.768 KHZ_12.5PF_Q13MC14610002

+RTCVCC

1 2

R198 1M_0402_5%

1 2

R199 330K_0402_5%

INTVRMEN

H Inte grate

：：：：

*

L Inte grate d VR

：：：：

d VRM en able

(INTVR MEN should alw ays be pull high.)

+3VS

+3VALW_PCH

C C

HDA_S DO<43>

HDA_SDO

ME d ebug m ode ,this signal has a weak internal PD
Low = Disab led (D efault)

*

High = Enabled [Fla sh Des criptor Sec urity Overide]

+3VALW_PCH

Thi s sign al has a we ak int ernal pull-do wn

On Die PLL VR Select is supplied by

1.5 V when smaple d high

*

1.8 V when sampl ed low
Nee ds to be pulled High f or Hur on River pla tfrom

B B

@

1 2

R204 1K_0402_5%

HIGH= Enable ( No Reboot )
LOW= D isable (Default)

*

R206 1K_04 02_5%

R208 0_0402_ 5%

R213 1K_0402_5%

12

Preven t back driv e issu e; +3V LAW leaka ge to +3VS f rom HDA_SYNC

HDA_B ITCLK_AUDIO<38>

HDA _SYNC_AU DIO<38>

HDA_R ST_AUDIO#<38>

HDA_S DOUT_AUDIO<38>

PCH_RTCX2

1

OSC4OSC

NC3NC

2

SM_INTR UDER#

PCH_INT VRMEN

M disabl e

HDA_SPKR

HDA_SDOUT

@

12

12

HDA _SYNC

1 2

R217 33_0402 _5%

1 2

R218 33_0402 _5%

R220 1M_0402_5%

R219 33_0402 _5%

R223 33_0402 _5%

12

1 2

1 2

1

C189
15P_0402_50V8J

2

HDA_BIT_CLK

HDA_RST#

HDA_SDOUT

W=20mi ls

+RTCBATT

R235 1K_04 02_5%

DVT :C188 C18 9 18 p-->1 5p

Need to open

+RTCVCC

1U_0603_10V4Z

1 2

R205 20K _0402_5%

1 2

R207 20K _0402_5%

1U_0603_10V4Z

C190

C191

1

2

1

2

ME

Need to open

HDA_SPKR<38>

HDA_S DIN0<38>

R222 51_0402_5%

+3VS

G

2

Q10
BSS138_NL_SOT23-3

HDA _SYNCHDA _SYNC_R

13

D

S

@

CMOS

SHORT PAD S

12

SHORT PAD S

12

12

JCMOS1

JME1

@

4

+RTCBATT_R

12

D1

1

BAS40-04_SOT23-3

Pla ce C1 94 c lose to P CH.

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTR UDER#

PCH_INT VRMEN

HDA_BIT_CLK

HDA _SYNC

HDA_SPKR

HDA_RST#

HDA_S DIN0

HDA_SDOUT

T90 PAD

T91 PAD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JT AG_TDI

PCH_JTAG_TDO

PCH_S PI_CLK

PCH_S PI_CS#

PCH_S PI_SI

PCH_S PI_SO

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

W=10mi ls

+3VLP

W=20mi ls

+RTCVCC

2

3

1

C194

1U_0603_10V4Z

U14A

RTCX1

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

BD82C PMS-QMVY-A1_FCBGA989~D

2

RTCIHDA

JTAG

SPI

PCH_G PIO49<18>

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

3

C38
A38
B37
C37

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

2

DVT:Add U67 R987 R988 for SATA issue

+3VS

PCH_G PIO49

PCH_G PIO19 ODD_DETECT #_R

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SERIR Q

LPC_AD0 <41,43>
LPC_AD1 <41,43>
LPC_AD2 <41,43>
LPC_AD3 <41,43>

LPC_FRAME# <41,43>

SERIR Q <43>

SATA_PRX_DTX_N0 <40>
SATA_PRX_DTX_P0 <40>
SATA_PTX_DRX_N0 <40>
SATA_PTX_DRX_P0 <40>

SATA_PRX_DTX_N1 <40>
SATA_PRX_DTX_P1 <40>
SATA_PTX_DRX_N1 <40>
SATA_PTX_DRX_P1 <40>

SATA_PRX_DTX_N2 <40>
SATA_PRX_DTX_P2 <40>
SATA_PTX_DRX_N2 <40>
SATA_PTX_DRX_P2 <40>

5

1

4

OE#

A2Y

@

3

PVT:Reserved D28

SATA_COMP

R224 37.4_0402_1%

SATA3_COMP

R225 49.9_0402_1%

RBIAS_SATA3

R230 750_040 2_1%

PCH_SATALED#

PCH_G PIO21

PCH_G PIO19

1 2

1 2

1 2

+1.05VS_VCC_SATA

+1.05VS_SATA3

PCH_SATALED# <44>

12

R988

@

200K_0402_5%

P

G

U67
74AHCT1G125GW_SOT353-5

HDD

ODD r eserved

ODD

+3VS

R987

1 2

0_0402_5%

@

If u se SPI programmer ,
R211 should b e open
(Norm al is pop)

1 2

R211 0_0402_5%

2 1

D28 CH 751H-40PT_SOD323-2

@

PCH_S PI_CS#

PCH_S PI_CLK

PCH_S PI_SI

SERIR Q

PCH_SATALED#

PCH_G PIO19

ODD_DETECT #_R <40>

R202 10K_0402_5%

R203 10K_0402_5%

R892 10K_0402_5%

@

32M MX25L3206EM2I-12G SOP 8P 3V

SPI ROM FOR ME ( 4MByte )

PCH_S PI_WP#
PCH_S PI_HOLD#
PCH_S PI_CS#_R

+3V_DSW_SPI

PCH_S PI_WP#

PCH_S PI_HOLD#

1 2

R214 0_0402_5%

1 2

R215 0_0402_5%

1 2

R216 0_0402_5%

PCH_S PI_CLK_R

PCH_S PI_CS#_R

PCH_S PI_CLK_R

PCH_S PI_SI_R PCH_SP I_SO_R

@

R221 33_0402 _5%

Res er ve fo r EMI p leas e cl ose to U1 4

PCH_G PIO21

R226 10K_0402_5%

U15

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

64M M X25L6405DZNI-12G WSON 8P

12

12

1

12

12

1 2

&U1

R209 3.3K_0402_5%

1 2

R210 3.3K_0402_5%

1 2

R340 3.3K_0402_5%@

1 2

1 2

R212 0_0402_5%

4

VSS

2

Q

@

1 2

C193 22P_0402_50V8J

+3V_DSW_SPI

+3VS

PCH_S PI_SOPC H_SPI_SO_R

1

C192

0.1U_0402_16V4Z

2

+3VS

+3VS

+3VALW_PCH +3VALW_PCH+3VALW_PCH

12

A A

R227
200_0402_5%

PCH_JTAG_TDO PCH_JT AG_TDIPCH_JTAG_TMS

12

R232
100_0402_1%

12

R228
200_0402_5%

12

R233
100_0402_1%

12

R229
200_0402_5%

12

R234
100_0402_1%

5

4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (1/8) SATA,HDA,SPI, LPC, XDP

Size Doc ument Number Re v

Cus tom

Date: Sheet

1

of

13 56Monday , April 11, 2011

1.0

5

12
12

12

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

CLK_BCLK_ITP#
CLK_BCLK_ITP

PCH_G PIO56

PCIE_PRX_DTX_N1<37>

PCIE LAN

Mini Card 1

D D

C C

Mini Card 1

PCIE LAN

B B

+3VS

R241 10K_0402_5%
R248 10K_0402_5%

+3VALW_PCH

A A

R249 10K_0402_5%

R251 10K_0402_5%

R253 10K_0402_5%

R254 10K_0402_5%

R255 10K_0402_5%

R256 10K_0402_5%

PCIE_PRX_DTX_P1<37>
PCIE_PTX_C_DRX_N1<37>
PCIE_PTX_C_DRX_P1<37>

PCIE_PRX_DTX_N2<41>

PCIE_PRX_DTX_P2<41>
PCIE_PTX_C_DRX_N2<41>
PCIE_PTX_C_DRX_P2<41>

CLK_P CIE_MINI1#<41>
CLK_P CIE_MINI1<41>

MINI1_ CLKREQ#<41>

CLK_P CIE_LAN#<37>
CLK_P CIE_LAN<37>

LAN_CL KREQ#<37>

CLK_RES_ITP#<5>
CLK_RES_ITP<5>

12

12

12

12

12

12

12

12

PCH_G PIO18
PCH_G PIO20

PCH_G PIO73

PCH_G PIO25

PCH_G PIO26

PCH_G PIO44

PCH_G PIO45

PCH_G PIO46

5

1 2

C199 0.1U_0402_10V7K

1 2

C200 0.1U_0402_10V7K

1 2

C197 0.1U_0402_10V7K

1 2

C198 0.1U_0402_10V7K

1 2

R262 0_0402_5%

1 2

R264 0_0402_5%

1 2

R266 0_0402_5%

R257 0_0402_5%
R258 0_0402_5%

R259 0_0402_5%

@

R279 0_0402_5%
R280 0_0402_5%

12

@

12

PCH_G PIO73

CLK_M INI1#
CLK_M INI1

PCH_G PIO18

PCH_G PIO20

CLK_LAN#
CLK_LAN

PCH_G PIO25

PCH_G PIO26

PCH_G PIO44

PCH_G PIO56

PCH_G PIO45

PCH_G PIO46

4

U14B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82C PMS-QMVY-A1_FCBGA989~D

R284 10K_0402_5%

4

12

PCI-E*

+3VALW_PCH

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLOCKS

CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

REFCLK14IN

XTAL25_IN

3

EC_LID_OUT#

E12

PCH_SMBCLK

H14

PCH_SMBDATA

C9

DRAM RST_CNTRL_PCH

A12

PCH_SMB0CLK

C8

PCH_SMB0DATA

G12

PCH_G PIO74

C13

PCH_SML1CLK

E14

PCH_SML1DATA

M16

M7

T11

P10

PEG_CLKR EQ#_R

M10

CLK_VGA#

AB37

CLK_VGA

AB38

CLK_C PU_DMI#

AV22

CLK_C PU_DMI

AU22

CLK_CP U_DPLL#

AM12

CLK_CP U_DPLL

AM13

CLK_B UF_CPU_DMI#

BF18

CLK_B UF_CPU_DMI

BE18

CLKIN _DMI2#

BJ30

CLKIN _DMI2

BG30

CLK_B UF_DREF_96M#

G24

CLK_B UF_DREF_96M

E24

CLK_BU F_PCIE_SATA#

AK7

CLK_BU F_PCIE_SATA

AK5

CLK_B UF_ICH_14M

K45

CLK_PC I_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

CLK_FKEX0

K43

CLK_27M_PCH_R

F47

CLK_FKEX2

H47

K49

Project ID G PIO 67
UMA

ptimus(Dis)

O

2010/08/23 2011/08/25

3

EC_LI D_OUT# <43>

DRAM RST_CNTRL_PCH <6>

PEG_CLKR EQ#_R

R427 10K_0402_5%
R428 10K_0402_5%

R263 10K_0402_5%
R265 10K_0402_5%

R267 10K_0402_5%
R268 10K_0402_5%

R270 10K_0402_5%
R272 10K_0402_5%

R274 10K_0402_5%

1 2

R278 90.9_0402_1%

T21 PAD

@

1 2

R804 22_0402 _5%

PCH_G PIO67

1 2

R240 10K_0402_5%

12

R2860_0402_5%

R2750_0402_5%

12

R2760_0402_5%

12

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

CLK_PC I_LPBACK <17>

+3VS

0
1

Compal Secret Data

Deciphered Date

VGA_CLKREQ# <22>

CLK_PCIE_VGA# <22>
CLK_PC IE_VGA <22>

CLK_CP U_DMI# <5>
CLK_C PU_DMI <5>

CLK_CP U_DPLL# <5>
CLK_CP U_DPLL <5>

+1.05V S_VCCDI FFCLKN

CLK_27M_PCH <22 >

CLK_FKEX2 <37>

12

R938
10K_0402_5%

OPT@

12

R939
10K_0402_5%

UMA@

2

SMB SMBus to DD R3 DIM M/P anel/Mini Card

+3VALW_PCH

DVT :C201 C20 2 18 p-->2 7p

2

PCH_SMBCLK

2N7002DW-T/R7_SOT363-6

PCH_SMBDATA

2N7002DW-T/R7_SOT363-6

+3VS

GP U

CP U

CP U

PCH_SML1CLK

2N7002DW-T/R7_SOT363-6

PCH_SML1DATA

2N7002DW-T/R7_SOT363-6

+3VS

1

EC_LID_OUT#

DRAM RST_CNTRL_PCH

PCH_SMBCLK

PCH_SMBDATA

PCH_G PIO74

PCH_SML1CLK

PCH_SML1DATA

PCH_SMB0CLK

PCH_SMB0DATA

6 1

Q1A

3

Q1B

SML1 SMBus to G PU/EC

3

Q11B

XTAL25_IN

XTAL25_OUT

27P_0402_50V8J

2

4

5

6 1

Q11A

2

4

5

C201

1 2

R236 10K_0402_5%

1 2

R242 10K_0402_5%

1 2

R237 2.2K_0402_5%

1 2

R243 2.2K_0402_5%

1 2

R244 10K_0402_5%

1 2

R245 2.2K_0402_5%

1 2

R246 2.2K_0402_5%

1 2

R238 2.2K_0402_5%

1 2

R239 2.2K_0402_5%

D_CK_SCLK <11,12,41>

D_CK_SCLK

D_CK_SDATA

1 2

R277 1M_0402_5%

25MHZ_20PF_7A25000012

1

2

D_CK_SDATA <11,12,41>

1 2

R2 4.7K_0402_5%

1 2

R1 4.7K_0402_5%

EC_SMB_CK2 <22,43>

EC_SMB_DA2 <22,43>

Y3

12

Res er ve fo r EMI , N eed clos e to U14

CLK_PC I_LPBACK

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

@

R285 33_0402_5%

12

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

@

1 2

C204 22P_0402_50V8J

1

+3VALW_PCH

1

C202

27P_0402_50V8J

2

14 56Monday , April 11, 2011

+3VS

+3VS

1.0

5

D D

4

3

2

1

U14C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82C PMS-QMVY-A1_FCBGA989~D

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_ INT

FDI _FSYNC 0

FDI _FSYNC 1

FDI _LSYNC0

FDI _LSYNC1

DSW ODVREN

PCH_D PWROK

WAKE#

1 2

R297 0_0402_5%

PCH_G PIO32

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

T88 PAD

T29 PAD

H_PM _SYNC

PCH_G PIO29

FDI_CTX_PRX_N0 <4>
FDI_CTX_PRX_N1 <4>
FDI_CTX_PRX_N2 <4>
FDI_CTX_PRX_N3 <4>
FDI_CTX_PRX_N4 <4>
FDI_CTX_PRX_N5 <4>
FDI_CTX_PRX_N6 <4>
FDI_CTX_PRX_N7 <4>

FDI_CTX_PRX_P0 <4>
FDI_CTX_PRX_P1 <4>
FDI_CTX_PRX_P2 <4>
FDI_CTX_PRX_P3 <4>
FDI_CTX_PRX_P4 <4>
FDI_CTX_PRX_P5 <4>
FDI_CTX_PRX_P6 <4>
FDI_CTX_PRX_P7 <4>

FDI_I NT <4>

FDI _FSYNC 0 <4>

FDI _FSYNC 1 <4>

FDI _LSYNC0 <4>

FDI _LSYNC1 <4>

PVT:< Memo>

1 2

R293 0_0402_ 5%

PCH_RSMRST#_R

PCH_D PWROK <43>

PCH_P CIE_WAKE# <37,41>

T25 PAD

DVT:De l R303 and update net name

T26 PAD

T27 PAD

T28 PAD

T30 PAD

SUSCLK <43>

PM_SLP_S5# <43>

PM_SLP_S4# <43>

PM_SLP_S3# <43>

H_PM _SYNC <5>

DSW ODVREN

*

WAKE#

PCH_G PIO29

PCH_G PIO32

PCH_G PIO32

R288 330K_0402_5%

R289 330K_0402_5%@

DSW OD VRE N - On Die DSW VR E nabl e
H En：able
L Di：sable

R295 10K_0402_5%

R298 10K_0402_5%

R300 8.2K_0402_5%

R936 8.2K_0402_5%

@

1 2

@

1 2

1 2

@

1 2

EC re ques t

12

12

+RTCVCC

+3VALW_PCH

+3VS

1 2

PCH_P WROK_R

1 2

1 2

1 2

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOM P

RBIA S_CPY

SUSACK#_R

XDP_DBRESET#_P

SYS_PW ROK

APWROK

PM_DRAM_PWR GD

SUSW ARN#_R

PBTN_OUT#_R

PCH_A CIN

21

PCH_G PIO72

RI#

DMI_CTX_PRX_N0<4>

+3VS

5

PCH_P WROK<43>

VGATE<54>

C C

1

IN1

VCC

OUT

2

IN2

GND

3

R292 10K_0402_5%

12

SUSW ARN#_RSUSACK#_R

@

R299 0_0402_5%

12

SYS_PW ROK

4

U16
MC74V HC1G08DFT2G_SC70-5

SYS_PW ROK

XDP_DBRESET#<5>

PVT:Reserved R991

PCH_A PWROK<43>

PM_DRAM_PWR GD<5>

+3VS

R305 200_0402_5%

B B

+3VALW_PCH

R308 10K_0402_5%

R309 200K_0402_5%

R310 10K_0402_5%

R311 10K_0402_5%

12

12

12

12

12

PM_DRAM_PWR GD

SUSW ARN#

PCH_A CIN

PCH_G PIO72

RI#

PCH_RSMRST#<43>

DMI_CTX_PRX_N1<4>
DMI_CTX_PRX_N2<4>
DMI_CTX_PRX_N3<4>

DMI_CTX_PRX_P0<4>
DMI_CTX_PRX_P1<4>
DMI_CTX_PRX_P2<4>
DMI_CTX_PRX_P3<4>

DMI_CRX_PTX_N0<4>
DMI_CRX_PTX_N1<4>
DMI_CRX_PTX_N2<4>
DMI_CRX_PTX_N3<4>

DMI_CRX_PTX_P0<4>
DMI_CRX_PTX_P1<4>
DMI_CRX_PTX_P2<4>
DMI_CRX_PTX_P3<4>

+1.05VS

1 2

R290 49.9_0402_1%

1 2

R291 750_0402_1%

4mil width and place
with in 500 mil of th e PCH

R296 0_0402_5%

R301

PCH_P WROK

SUSW ARN#<43>

PBTN_OUT#<43>

0_0402_5%

1 2
1 2

R991 0_0402_5%@

1 2

R302 0_0402_5%

PCH_RSMRST# PCH_RSMRST# _R

ACIN<2 2,43,44,46,48>

R304 0_0402_5%

R306 0_0402_5%

R307 0_0402_5%

D2 CH7 51H-40PT_SOD323-2

R312 10K_0402_5%

A A

12

5

PCH_RSMRST#

SPOK<49,55>

PVT:Reserved D29 D30

@

2 1

D30 CH751H-40PT_SOD323-2

D29 CH751H-40PT_SOD323-2

21

@

4

PCH_RSMRST#PCH_P WROK

Defualt DSW Enable

Note: 1.SLP_ SUS an d S USA CK# are NC if DSW is no t supported

2.DPWR OK sho uld co nnect to RSMRS T# if DSW not supp orted

3.The DSW ra ils mu st be stable f or at lea st 10ms before DP WRO K i s asserted to PCH
***4.P CH_ DPW ROK pu ll up to +V3S ena ble s D SW wupport. No in sta ll R52 61 to disab le DSW

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,

1

15 56Monday , April 11, 2011

1.0

5

4

3

2

1

R2613 100K_0402_5%

1 2

D D

+3VS

R524 2.2K_0402_5%

1 2

R525 2.2K_0402_5%

1 2

+3VS

R316 2.2K_0402_5%

1 2

R318 2.2K_0402_5%

1 2

C C

R322 150_0402_1%

1 2

R323 150_0402_1%

1 2

R324 150_0402_1%

1 2

+3VS

R320 2.2K_0402_5%

1 2

R321 2.2K_0402_5%

1 2

B B

ENBKL

PCH_L CD_CLK

PCH_LC D_DATA

CTRL_CLK

CTRL_DATA

PCH_CRT_ B

PCH_C RT_G

PCH_C RT_R

PCH_C RT_CLK

PCH_CRT_DATA

ENBKL<43>

PCH_E NVDD<34>

DPST_PWM<34>

PCH_L CD_CLK<34>
PCH_LC D_DATA<34>

R315 2.37K_0402_1%

R317 0_0402_5%

PCH_TXCLK-< 34>
PCH_TXCLK+<34>

PCH_TXOUT0-<34>
PCH_TXOUT1-<34>
PCH_TXOUT2-<34>

PCH_TXOUT0+<34>
PCH_TXOUT1+<34>
PCH_TXOUT2+<34>

PCH_CRT_ B<36>
PCH_C RT_G<36>
PCH_C RT_R<36>

PCH_C RT_CLK<36>

PCH_CRT_DATA<36>

PCH_ CRT_HSYN C<36>
PCH_C RT_VSYNC<36>

12

12

PCH_TXCLK­PCH_TXCLK+

PCH_TXOUT0­PCH_TXOUT1­PCH_TXOUT2-

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

PCH_CRT_ B
PCH_C RT_G
PCH_C RT_R

PCH_C RT_CLK
PCH_CRT_DATA

PCH _CRT_HS YNC
PCH_C RT_VSYNC

R327

1K_0402_0.5%

CTRL_CLK
CTRL_DATA

LVDS_IBG

LVD_VREF

CRT_I REF

12

U14D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82C PMS-QMVY-A1_FCBGA989~D

SDVO_SDATA

SDVO_SCLK

PCH_D PB_HPD

SDVO_SCLK <35>
SDVO_SDATA <35>

PCH_D PB_HPD <35>

SDVO_INTN
SDVO_INTP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

SDVO_SCLK
SDVO_SDATA

PCH_D PB_HPD

PCH_D PB_N2 <35>
PCH_DPB_ P2 <35>
PCH_D PB_N1 <35>
PCH_DPB_ P1 <35>
PCH_D PB_N0 <35>
PCH_DPB_ P0 <35>
PCH_D PB_N3 <35>
PCH_DPB_ P3 <35>

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DDPD_AUXP

R865 2.2K_0402_5%

R864 2.2K_0402_5%

R866 100K_0402_5%@

HDMI D2

HDMI D1

HDMI D0

HDMI CLK

1 2

12

12

+3VS

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet

Compal Electronics, Inc.

PCH (4/9) LVDS,CRT,DP,HDMI

of

1

16 56Monday , April 11, 2011

1.0

5

4

3

2

1

+3VS

D D

C C

RP23

PCI_P IRQA#

18

PCI_P IRQD#

27

PCI_P IRQC#

36

PCI_P IRQB#

45

8.2K_0804_8P4R_5%

RP24

PCH_W L_OFF#

18

WW AN_OFF#

27

PCH_G PIO5

36

PCH_G PIO52

45

8.2K_0804_8P4R_5%

RP25

PCH_G PIO2

18

PCH_G PIO4

27

ODD_DA#

36
45

8.2K_0804_8P4R_5%

1 2

R331 8.2K_0402_5%

@

1 2

R337 8.2K_0402_5%

1 2

R332 8.2K_0402_5%

1 2

R330 1K_0402_5%

PCH_G PIO53

DGPU_ HOLD_RST#

DGPU_ PWR_EN

Boot BIO S Strap bi t1 BBS1

Boot BIOS

Bit10

1

1

0

Desti nation

Reserve d

PCI

SPI

LPC

CLK_PC I_LPBACK
CLK_P CI_LPC

CLK_P CI_DEBUG

PCI_P IRQA#
PCI_P IRQB#
PCI_P IRQC#
PCI_P IRQD#

T31PAD @

T32PAD @
T33PAD @
T34PAD @

DGPU_ HOLD_RST#
PCH_G PIO52
DGPU_ PWR_EN

WW AN_OFF#
PCH_G PIO53
PCH_W L_OFF#

PCH_G PIO2
ODD_DA#
PCH_G PIO4
PCH_G PIO5

PLT_RST#

CLK_PC I0
CLK_PC I1
CLK_PC I2
CLK_PC I3
CLK_PC I4

*

For Op tim us USB /CR

R334 22_0402_5%
R335 22_0402_5%

1 2

R953 22_0402_5%

1 2

DGPU_ HOLD_RST#<22>

DGPU_ PWR_EN<45,53>

PCH_W L_OFF#<41>

ODD_DA#<40>

PLT_RST#<5,22,37,41,43>

12

Bit11

GNT1#/
GPIO51

0

110

0

B B

CLK_PC I_LPBACK<14>

CLK_P CI_LPC<43>

CLK_P CI_DEBUG<41>

U14E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82C PMS-QMVY-A1_FCBGA989~D

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

USB

RSVD22

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

AV5
AV10

AT8

AY5
BA2

AT12
BF3

USB20_N0

C24

USB20_P0

A24

USB20_N1

C25

USB20_P1

B25

USB20_N2

C26

USB20_P2

A26

USB20_N3

K28

USB20_P3

H28

USB20_N4

E28

USB20_P4

D28
C28
A28
C29
B29
N28

PCH HM65 config not support USB port 6 & 7.

M28
L30
K30
G30
E30

USB20_N10

C30

USB20_P10

A30
L32
K32
G32
E32
C32
A32

USBR BIAS

C33

B33

USB_OC0#

A14

USB_OC1#

K20

USB_OC2#

B17

USB_OC3#

C16

USB_OC4#

L16

USB_OC5#

A16

USB_OC6#

D14

USB_OC7#

C14

USB20_N0 <42>
USB20_P0 <42>
USB20_N1 <42>
USB20_P1 <42>
USB20_N2 <42>
USB20_P2 <42>
USB20_N3 <34>
USB20_P3 <34>
USB20_N4 <41>
USB20_P4 <41>

USB20_N10 <42>
USB20_P10 <42>

Within 500 mils

1 2

R333 22.6_0402_1%

Rig ht USB-1

Rig ht USB-2

Lef t U SB

Ca mer a

MPC IE- WLA N/BT

USB_OC0# < 42,43>
USB_OC1# < 42,43>

USB_OC3#
USB_OC0#
USB_OC7#
USB_OC5#

USB_OC1#
USB_OC4#
USB_OC6#
USB_OC2#

RP26

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP27

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

+3VALW_PCH

RSVD

PCI

@

R336 0_0402_5%

PLT_RST#

A A

SN74A HC1G08DCKR_SC70-5

U19

12

+3VS

5

1

P

IN1

2

IN2

G

3

12

R339

100K_0402_5%

4

O

PLT_RST_BUF# <41>

DV T: <S MT mem o>upd ate U 19 P/ N

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (5/9) PCI, USB, NVRAM

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

1

17 56Monday , April 11, 2011

1.0

5

4

3

2

1

GPI O28

On-D ie PLL V oltage Regulato r
This si gna l has a weak interna l pull up

H O n-D ie vo lta ge reg u：lator enable

*

：

L O n-D ie PL L V olt age Re g

D D

GPI O27

PCH_ GPI O27 (Hav e intern al Pull -High)

Hig h: VCC VRM VR Enabl e

*

Low : V CCV RM VR Disab le

SAT A2G P/G PIO 36 & S ATA 3GP/G PIO37

Samp led at Rising edge of PWROK.
Weak in ter nal pu ll-d own . (w eak int ernal p ull-down is dis abled a fter PLT RST# de -assert s)

NOTE : T his si gna l sh ould NO T be pu lled hig h when strap i s sample d

+3VS

R357 2 00K_0402_1%

+3VS

R801 1 K_0402_5%

C C

R776 1 00K_0402_5%

+3VS

B B

+3VAL W_PCH

A A

1 2

R421 1 0K_0402_5%

1 2

R420 1 0K_0402_5%

1 2

R352 1 0K_0402_5%

1 2

R353 1 0K_0402_5%

1 2

R354 1 0K_0402_5%

1 2

R347 1 0K_0402_5%

1 2

R356 1 0K_0402_5%

1 2

R358 1 0K_0402_5%

1 2

R359 1 0K_0402_5%

1 2

R360 1 0K_0402_5%

1 2

R361 1 0K_0402_5%

1 2

R362 1 K_0402_5%

1 2

R363 1 0K_0402_5%

1 2

R364 1 0K_0402_5%

1 2

R429 1 0K_0402_5%

1 2

R365 1 0K_0402_5%

@

1 2

R343 1 K_0402_5%

@

1 2

R344 1 0K_0402_5%

1 2

@

12

12

@

@

ODD _DETECT#

PCH _GPIO37

PCH _GPIO6

PCH _GPIO1

PCH _GPIO16

DGP U_PW ROK_R

PCH _GPIO22

PCH _GPIO38

PCH _GPIO39

BT_ON#

PCH _GPIO48

PCH _GPIO49

PCH _GPIO12

USB30 _SMI#

PCH _GPIO28

PCH _GPIO57

PCH _GPIO24

PCH _GPIO35

5

ulator disab le

PCH _GPIO28

PCH _GPIO27

CRT_ DET#<36>

For Op ti mus

DGP U_PWR OK<45,53>

DV T: Add PCH_ GPI O49 ne t o ff pa ge

+3VS

Note : H igh - CRT Plug ged

R342
10K_0 402_5%

1 2

CRT _DET

13

D

2

G

Q12

S

@

2N700 2_SOT23-3

EC_ SCI#<43>

EC_SM I#<4 3>

1 2

R350 0_0402_5%

BT_ON#<41>

ODD _DETECT#<40>

PCH_ GPIO49<13>

4

CRT _DET

PCH _GPIO1

PCH _GPIO6

EC_ SCI#

EC_SM I#

PCH _GPIO12

USB30 _SMI#

PCH _GPIO16

DGP U_PW ROK_R

PCH _GPIO22

PCH _GPIO24

PCH _GPIO27

PCH _GPIO28

BT_ON#

PCH _GPIO35

ODD _DETECT#

PCH _GPIO37

PCH _GPIO38

PCH _GPIO39

PCH _GPIO48

PCH _GPIO49

PCH _GPIO57

U14 F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82C PMS-QMVY -A1_FCB GA989~D

ODD _EN#

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

PROCPWRGD

GPIO

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

NCTF

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C40

PCH _GPIO69

B41

PCH _GPIO70

C41

PCH _GPIO71

A40

P4

A20GATE

RCIN#

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

PCH _PEC I_R

AU16

PECI

P5

AY11

PCH _THRMT RIP#_R

AY10

T14

Note: This signal has weak internal PU, can't pull low

NV_ CLE

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

2010/08/23 2011/08/25

Compal Secret Data

ODD _EN# <40>

@

1 2

R348 0_ 0402_5%

1 2

R351 390_0402_5%

Int el Ant i-T hef t T echonl ogy

NV_ALE

Deciphered Date

2

Pro jec t ID GP IO69
14"

15. 6"

GATEA20 <43>

H_P ECI <5,43>

EC_KB RST# <43>

H_C PUPW RGD <5>

H_THR MTRIP# <5>

R329 1 K_0402_5%

High=Endabled

Low=Disable(floating)

ODD _EN#

PCH _GPIO70

PCH _GPIO71

GATEA20

EC_K BRST#

+1.8VS

12

12

@

1 2

R2614 1 0K_0402_5%

1 2

R2616 1 0K_0402_5%

1 2

R2617 1 0K_0402_5%

1 2

R346 1 0K_0402_5%

1 2

R345 1 0K_0402_5%

+3VS

0
1

PCH _GPIO69

R328

2.2K_ 0402_5%

Layout note: CLOSE TO THE BRANCHING POINT

12

R2615
10K_0 402_5%

15@

12

R940
10K_0 402_5%

14@

H_S NB_IVB# < 5>

*

Compal Electronics, Inc.

Title

PCH (6/9) GPIO, CPU, MISC

Size Doc umen t Num ber Re v

Cu stom

Dat e: Sh eet of

1

+3VS

1.0

18 56Mond ay, April 11, 201 1

5

4

3

2

1

PCH Power Rail Table

Vol ta ge Rail

V_P RO C_IO

V5R EF

V5R EF _Sus

Vcc 3_3

Vcc ADA C

Vcc AD PLLA

Vcc AD PLLB

Vcc Cor e

Vcc DMI

Vcc VRM 1.8 / 1 .5 0 .16

Vcc SSC 1. 05 0.0 95

Vcc DI FFC LKN 1 .05 0. 055

Vcc ALV DS 3.3

292 5mA

POWER

VCC CORE

VCCIO

FDI

CRTLVDS

60m A

DMI

20m A

190 mA

DFT / SPI HVCMOS

1mA

VCCADAC

VSSADAC

1mA

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

20m A

VCCSPI

+VCCA DAC

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

Layout note: Close to AB36

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

V1

1

2

+3VS

Layout note: Close to AM37

+VCCTX_LVDS

0.01U_0402_16V7K

+3VS_VCC3_3_6

1

2

+VCCA FDI_VRM

+VCCP _VCCDMI

+VCCP _VCC_DMI_CCI

1

2

1

2

Layout note: Close to V1

C210

0.01U_0402_16V7K

C211

0.1U_0402_10V7K

1

1

2

1

C213

2

1 2

R370 0_0805_5%

Layout note: Close to V33

C216

0.1U_0402_10V7K

10UH_LB2012T100MR_20%

1

2

Layout note: Close to AG16

R375 0_0805_5%

C225

0.1U_0402_10V7K

1 2

R378 0_0805_5%

C227
1U_0402_6.3V6K

2

0.01U_0402_16V7K

1

C214

2

L2401

1 2

C223
1U_0402_6.3V6K

1 2

C212
22U_0603_6.3V6M

+3VALW_PCH

+3VS

1

C926
22U_0603_6.3V6M

2

0.1UH_MLF1608D R10KT_10%_1608

0.1uH inductor, 200mA

22U_0805_6.3V6M

1

C215

2

Layout note: Close to AT20

R372 0_0805_5%

1

+1.05VS

C222
1U_0402_6.3V6K

2

L5

MBK16 08221YZF_2P

L6

1 2

+3VS

12

+1.8VS

12

+1.05VS+VCCP _VCCDMI

+1.05VS

Layout note: Close to AA23

C206

10U_0603_6.3V6M

1

1

2

D D

+1.05VS

+1.05VS

C C

B B

1 2

R371 0_0805_5%

+3VS +1.8VS+VCCP NAND

+1.05VS

2

R368 0_0603_5%

This pin ca n be left as no connect in
On-Die VR en abled mode (defau lt).

Layout note: Close to AN21,AN16,AN23

+1.05VS_VCC_EXP

C217

10U_0603_6.3V6M

C218

1U_0402_6.3V6K

1

1

2

2

Layout note: Close to BH29

1 2

R374 0_0805_5%

@

R376 0_0603_ 5%

12

+1.05VS

R377 0_0805_5%

C208

1U_0402_6.3V6K

C207

1U_0402_6.3V6K

1

2

+1.05VS_VCCDPLLEXP

C219

1

2

1 2

+VCCP _VCCDMI

+1.05VS_VCCDPLLEXP

+VCCAPLLEXP

C220

1U_0402_6.3V6K

+1.05V S_VCCAPLL_FDI

+1.05V S_VCCDPLL_FDI

12

T71PAD @

1U_0402_6.3V6K

1

2

1

C224

0.1U_0402_10V7K

2

C209

1U_0402_6.3V6K

1

2

C221

1U_0402_6.3V6K

1

2

+3VS_VCCA3GBG

+VCCA FDI_VRM

U14G

130 0mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

BD82C PMS-QMVY-A1_FCBGA989~D

Vol tag e

1.0 5

3.3

3.3

1.0 5

1.0 5

1.0 5

1.0 5

1.0 5Vcc IO 2.925

1.0 5Vcc ASW 1. 01

3.3Vc cSPI 0. 02

3.3Vc cDSW 0. 003

1.8 0.1 9Vcc pNAN D

3.3Vc cRTC 6 uA

3.3Vc cSu s3_3

3.3 / 1.5Vcc Su sHDA

1.0 5Vcc CL KDMI

1.8Vc cTX _LVD S 0.06

S0 Iccmax
Current (A)

0.0 01

5

5

0.0 01

0.0 01

0.2 66

0.0 01

0.0 8

0.0 8

1.3

0.0 42

0.1 19

0.0 1

0.0 2

0.0 01

+1.5VS

R379 0_0603_5%

+1.8VS

R380 0_0603_5%

VCCV RM==>1 .5V FOR M OBILE
VCCV RM== >1.8V FOR DESKTOP
VCCV RM = 160m A detal w aiting for newest sp ec

A A

5

12

@

12

4

+VCCA FDI_VRM

+VCCA FDI_VRM

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

PCH (7/9) PWR

1

19 56Sun day, April 10, 2 011

1.0

5

+3VS

1 2

L9

L10

12

@

5

Layout note: Close to T38

+3VS_VCC_C LKF33

C228

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

+1.05VS_VCCA_A _DPL

+1.05VS_VCCA_B _DPL

10U_0603_6.3V6M

C248

220U_B2_2.5VM_R35

1

C913

1

+

2

2

@

Layout note: Close to AF17

12

1

C254
1U_0402_6.3V6K

2

Layout note: Close to AF33

+1.05V S_VCCDI FFCLKN

12

1

C257
1U_0402_6.3V6K

2

Layout note: Close to AG33

12

1

C259
1U_0402_6.3V6K

2

+1.05VS

+1.05VM_VCCSUS

1

C262
1U_0402_6.3V6K

2

C229

1U_0402_6.3V6K

1

2

1

C234

@

2

+1.05VS

10U_0603_6.3V6M

C249

1U_0402_6.3V6K

C914

1

1

2

2

+VCCD IFFCLK

+1.05VS_SSC VCC

1 2

R410 0_0603_5%

L7

10UH_LB2012T100MR_20%

1 2

D D

+1.05VS

L8 10UH_LB2012T100MR_20%@

DVT:Reserved C913 C914

+1.05VS

10UH_LB2012T100MR_20%

1 2

C C

B B

A A

+1.05VS

R407 0_0603_ 5%

1 2

10UH_LB2012T100MR_20%

+1.05VS

R401 0_0603_5%

+1.05VS

R403 0_0603_5%

+1.05VS

R405 0_0603_5%

@

+1.05VS

+3VALW_PCH

1 2

R384 0_0603_5%

+1.05VS

R385 0_0603_5%

1 2

R394 0_0805_5%

C250

220U_B2_2.5VM_R35

C251

1U_0402_6.3V6K

1

1

+

2

2

@

PVT:< Memo>

0.1U_0402_10V7K

0.1U_0402_10V7K

Layout note: Close to BJ8

C263

4.7U_0603_6.3V6K

1

1

2

2

4

Ha ve int ernal VRM

@

R382 0_0603_5%

C230 0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

12

Layout note: Close to T16

@

12

@

Layout note: Close to AA19

+1.05VM_VCCASW

1

2

C242

1U_0402_6.3V6K

1

1

2

2

1

C256

2

1

C261

2

C264

C265

0.1U_0402_10V7K

1

+RTCVCC

2

4

1

C231

0.1U_0402_10V7K

2

1

C237
1U_0402_6.3V6K

2

C239

22U_0805_6.3V6M

C243

1U_0402_6.3V6K

+VCCRTCEXT

+VCCA FDI_VRM

+1.05VS_VCCA_A _DPL

+1.05VS_VCCA_B _DPL

+VCCD IFFCLK

+1.05V S_VCCDIFFC LKN

+1.05VS_SSC VCC

+VCCSST

+1.05VM_VCCSUS

+V_CPU _IO

Layout note: Close to A22

1

2

+VCCACLK

+VCCPDSW

+PCH_ VCCDSW

+3VS_VCC_C LKF33

+VCCA PLL_CPY_PCH

+VCCD PLL_CPY

+VCCSUS1

C240

22U_0805_6.3V6M

1

2

C244

1U_0402_6.3V6K

1

2

C267

0.1U_0402_10V7K

C266

1U_0402_6.3V6K

1

1

2

2

3

2

1

VCC3 _3 = 266m A detal w aiting for newest sp ec

VCCD MI = 42mA detal wa iting for newest spe c

Layout note: Close to N26

+1.05V S_VCCUSBCORE

N26

P26

P28

T27

T29

Layout note: Close to T23

T23

T24

V23

V24

P24

+1.05VS_VCCAU PLL

T26

+PCH_ V5REF_SUS

M26

+VCCA_US BSUS

AN23

+3V_VCCPSUS

AN24

+PCH_ V5REF_RUN

P34

+3V_VCCPSUS

N20

N22

P20

P22

+3VS_VCCP CORE

AA16

W16

+3VS_VC CPPCI

T34

Layout note: Close to AJ2 Layout note: Close to T34

+VCC3_3_2

AJ2

AF13

AH13

AH14

AF14

AK1

+VCCA FDI_VRM

AF11

+1.05VS_VCC_SATA

AC16

AC17

AD17

+VCCME_22

T21

+VCCME_23

V21

+VCCME_21

T19

Layout note: Close to P32

+VCCS USHDA

P32

2010/08/23 2011/08/25

R386 0_0603_5%

1

C232
1U_0402_6.3V6K

2

+3V_VCCPUSB

0.1U_0402_10V7K
C235

1

+3V_VCCAUBG

2

Layout note: Close to AA16 Layout note: Close to N20

+VCCA FDI_VRM

1

C269

0.1U_0402_16V4Z

2

1

C236

0.1U_0402_10V7K

Layout note: Close to P24

2

R393 0_0603_5%

C241 1 U_0402_6.3V6K

1

C247

0.1U_0402_10V7K

2

R400 0_0603_5%

1

C253

0.1U_0402_10V7K

2

+1.05VS_SATA3

+VCCSATAPLL

R408 0_0603_5%

R409 0_0603_5%

R411 0_0603_5%

Compal Secret Data

Deciphered Date

101 0mA

80m A

80m A

55m A

95m A

1mA

POWER

3mA

Clock and Mi sce lla neous

CPURTC

119 mA

PCI/GPIO/LPCMISC

SATA USB

10m A

HDA

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

1mA

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

1mA

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

V5REF

U14J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

C268

0.1U_0402_10V7K

BD82C PMS-QMVY-A1_FCBGA989~D

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.05VS

12

+3VALW_PCH

R390 0_0603_5%

R391 0_0603_ 5%

R398 0_0805_5%

R412 0_0603_5%

12

+3VALW_PCH

12

12

@

1 2

+3VS

12

1

C252

+3VS

12

R406 0_0805_5%

1

C260
1U_0402_6.3V6K

2

Layout note: Close to AC16

12

12

12

0.1U_0402_10V7K

2

R402 0_0805_5%

1

C255
1U_0402_6.3V6K

2

Layout note: Close to AH13

12

+1.05VS

+3VALW_PCH

12

2

+1.05VS

1

2

R399 0_0603_5%

+1.05VS+1.05VS_VCC_SATA

+5VALW

R383 0_0603_5%

PCH_P WR_EN#<46>

+3VALW_PCH

R395 0_0603_5%

C245
1U_04 02_6.3V4Z

12

12

+3VS

12

+1.05VS+1.05VS_SATA3

L11

@

10UH_LB2012T100MR_20%

1 2

@

1

C258

10U_0603_6.3V6M

2

Layout note: Close to AK1

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

12

Q13

@

AO3413_SOT23-3

D

S

13

G

2

12/29 change SC1H751H010 to SCS00003500

R392

10_0402_5%

Layout note: Close to M26

R396

10_0402_5%

Layout note: Close to P34

+1.05VS

1

@

2

+3VALW_PCH+5VALW_PCH

12

21

1

2

+3VS+5VS

12

21

1

2

+5VALW_PCH

R388

20K_0402_5%

C233

0.1U_0402_10V7K

12

@

D3
CH751H-40PT_S OD323-2

+PCH_ V5REF_SUS

C238

0.1U_0603_25V7K

D4
CH751H-40PT_S OD323-2

+PCH_ V5REF_RUN

C246
1U_0603_10V6K

Compal Electronics, Inc.

PCH (8/9) PWR

1

20 56Monday , April 11, 2011

1.0

5

D D

C C

B B

A A

U14H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

BD82C PMS-QMVY-A1_FCBGA989~D

4

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

3

U14I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

BD82C PMS-QMVY-A1_FCBGA989~D

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

2

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

PCH (9/9) VSS

1

21 56Sun day, April 10, 2 011

1.0

5

LV2

OPT@

BLM18 PG330SN1D_ 0603

+1.0 5VS_DGPU

D D

C C

B B

1 2

PEG_G TX_C_HRX_ N[0..15]<4>

PEG_G TX_C_HRX_ P[0..15]<4>

PEG_HT X_C_GRX_ N[0..15]<4>

PEG_HT X_C_GRX_ P[0..15]<4>

@

XTALIN

Layout note: Reserve for EMI please close to UV1

22_04 02_5%

1 2

RV28 10M_0402_5%

27MHZ _16PF_7M27 070004

1

CV45
18P_0 402_50V8J

OPT@

2

+3VS _DGPU

R2647

@

OPT@

YV 1

18P_0 402_50V8J

Layout note: Under GPU

OPT@

0.1U_ 0402_1 6V4Z

OPT@

1

1

CV11

CV8

2

2

C2581

@

10P_0 402_50V8J

12

1 2

XTAL_OUTXTALIN

13
24

CV46

OPT@

0.1U_ 0402_1 6V4Z

0.1U_ 0402_1 6V4Z

OPT@

1

CV12

2

PEG_G TX_C_HRX_ N[0..15]

PEG_G TX_C_HRX_ P[0..15]

PEG_HT X_C_GRX_ N[0..15]

PEG_HT X_C_GRX_ P[0..15]

PEG_G TX_C_HRX_P0
PEG_G TX_C_HRX_N0
PEG_G TX_C_HRX_P1
PEG_G TX_C_HRX_N1
PEG_G TX_C_HRX_P2
PEG_G TX_C_HRX_N2
PEG_G TX_C_HRX_P3
PEG_G TX_C_HRX_N3
PEG_G TX_C_HRX_P4
PEG_G TX_C_HRX_N4
PEG_G TX_C_HRX_P5
PEG_G TX_C_HRX_N5
PEG_G TX_C_HRX_P6
PEG_G TX_C_HRX_N6
PEG_G TX_C_HRX_P7
PEG_G TX_C_HRX_N7
PEG_G TX_C_HRX_P8
PEG_G TX_C_HRX_N8
PEG_G TX_C_HRX_P9
PEG_G TX_C_HRX_N9
PEG_G TX_C_HRX_P10
PEG_G TX_C_HRX_N10
PEG_G TX_C_HRX_P11
PEG_G TX_C_HRX_N11
PEG_G TX_C_HRX_P12
PEG_G TX_C_HRX_N12
PEG_G TX_C_HRX_P13
PEG_G TX_C_HRX_N13
PEG_G TX_C_HRX_P14
PEG_G TX_C_HRX_N14
PEG_G TX_C_HRX_P15
PEG_G TX_C_HRX_N15

1

2

150mA

+PLL VDD

0.1U_ 0402_1 6V4Z

OPT@

10U_0 603_6.3V6M

OPT@

2

1

CV9

CV7

1

2

C270 0 .1U_040 2_16V7KOPT@
C271 0 .1U_040 2_16V7KOPT@
C272 0 .1U_040 2_16V7KOPT@
C273 0 .1U_040 2_16V7KOPT@
C274 0 .1U_040 2_16V7KOPT@
C275 0 .1U_040 2_16V7KOPT@
C276 0 .1U_040 2_16V7KOPT@
C277 0 .1U_040 2_16V7KOPT@
C278 0 .1U_040 2_16V7KOPT@
C279 0 .1U_040 2_16V7KOPT@
C280 0 .1U_040 2_16V7KOPT@
C281 0 .1U_040 2_16V7KOPT@
C282 0 .1U_040 2_16V7KOPT@
C283 0 .1U_040 2_16V7KOPT@
C284 0 .1U_040 2_16V7KOPT@
C285 0 .1U_040 2_16V7KOPT@
C286 0 .1U_040 2_16V7KOPT@
C287 0 .1U_040 2_16V7KOPT@
C290 0 .1U_040 2_16V7KOPT@
C288 0 .1U_040 2_16V7KOPT@
C291 0 .1U_040 2_16V7KOPT@
C292 0 .1U_040 2_16V7KOPT@
C294 0 .1U_040 2_16V7KOPT@
C295 0 .1U_040 2_16V7KOPT@
C296 0 .1U_040 2_16V7KOPT@
C297 0 .1U_040 2_16V7KOPT@
C298 0 .1U_040 2_16V7KOPT@
C299 0 .1U_040 2_16V7KOPT@
C300 0 .1U_040 2_16V7KOPT@
C301 0 .1U_040 2_16V7KOPT@
C302 0 .1U_040 2_16V7KOPT@
C303 0 .1U_040 2_16V7KOPT@

Layout note: Differential signal

CLK_2 7M_PCH<14>

2

SMB_C LK_GPU

SMB_D ATA_GPU

A A

VGA_C LKREQ#<1 4>

2N700 2DW-T/ R7_SOT363-6

61

Q14A

OPT@

4

Q14B

2N700 2DW-T/ R7_SOT363-6

+3VS _DGPU + 3VS_DGPU

2

G

1 3

D

S

Q15

OPT@

2N700 2_SOT23-3

5

3

EC_SM B_CK2 <14,43>

EC_SM B_DA2 <14,43>

12

OPT@

R442
10K_0 402_5%

CLK _REQ_GP U#

5

OPT@

4

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CLK _PCIE_VG A<14>

CLK_ PCIE_VGA #<14>

@

1 2

RV16 200_0402_1%

OPT@

1 2

RV18 0_0402_ 5%

OPT@

1 2

RV19 2.49K_ 0402_1%

+PLL VDD

@

R894 22 _0402_5%

RV26 10K_0 402_5%
RV25 10K_0 402_5%

12

OPT@

12

OPT@

12

Note: Internal Thermal Sensor

4

PEG_HT X_C_GRX_P0
PEG_HT X_C_GRX_N0
PEG_HT X_C_GRX_P1
PEG_HT X_C_GRX_N1
PEG_HT X_C_GRX_P2
PEG_HT X_C_GRX_N2
PEG_HT X_C_GRX_P3
PEG_HT X_C_GRX_N3
PEG_HT X_C_GRX_P4
PEG_HT X_C_GRX_N4
PEG_HT X_C_GRX_P5
PEG_HT X_C_GRX_N5
PEG_HT X_C_GRX_P6
PEG_HT X_C_GRX_N6
PEG_HT X_C_GRX_P7
PEG_HT X_C_GRX_N7
PEG_HT X_C_GRX_P8
PEG_HT X_C_GRX_N8
PEG_HT X_C_GRX_P9
PEG_HT X_C_GRX_N9
PEG_HT X_C_GRX_P10
PEG_HT X_C_GRX_N10
PEG_HT X_C_GRX_P11
PEG_HT X_C_GRX_N11
PEG_HT X_C_GRX_P12
PEG_HT X_C_GRX_N12
PEG_HT X_C_GRX_P13
PEG_HT X_C_GRX_N13
PEG_HT X_C_GRX_P14
PEG_HT X_C_GRX_N14
PEG_HT X_C_GRX_P15
PEG_HT X_C_GRX_N15

PEG_GTX_HRX_P0
PEG_G TX_HRX_N0
PEG_GTX_HRX_P1
PEG_G TX_HRX_N1
PEG_GTX_HRX_P2
PEG_G TX_HRX_N2
PEG_GTX_HRX_P3
PEG_G TX_HRX_N3
PEG_GTX_HRX_P4
PEG_G TX_HRX_N4
PEG_GTX_HRX_P5
PEG_G TX_HRX_N5
PEG_GTX_HRX_P6
PEG_G TX_HRX_N6
PEG_GTX_HRX_P7
PEG_G TX_HRX_N7
PEG_GTX_HRX_P8
PEG_G TX_HRX_N8
PEG_GTX_HRX_P9
PEG_G TX_HRX_N9
PEG_G TX_HRX_P10
PEG_G TX_HRX_N10
PEG_G TX_HRX_P11
PEG_G TX_HRX_N11
PEG_G TX_HRX_P12
PEG_G TX_HRX_N12
PEG_G TX_HRX_P13
PEG_G TX_HRX_N13
PEG_G TX_HRX_P14
PEG_G TX_HRX_N14
PEG_G TX_HRX_P15
PEG_G TX_HRX_N15

CLK _PCIE_V GA
CLK _PCIE_VG A#
CLK _REQ_GP U#

PEX_TSTCLK_ OUT
PEX_TSTCLK_ OUT#

PLTRST_ VGA_R#PLTRST_ VGA#

XTALIN
XTAL_OUT

XTALOUT
XTALSSIN

SMB_C LK_GPU
SMB_D ATA_GPU

VGA _EDID_ CLK
VGA _EDID_D ATA

I2C B_SCL
I2C B_SDA

VGA _CRT_CLK
VGA_ CRT_DATA

HDC P_SCL
HDC P_SDA

UV1A

AP17
AN17
AN19

AP19
AR19
AR20

AP20
AN20
AN22

AP22
AR22
AR23

AP23
AN23
AN25

AP25
AR25
AR26

AP26
AN26
AN28

AP28
AR28
AR29

AP29
AN29
AN31

AP31
AR31
AR32
AR34

AP34

AL17
AM17
AM18
AM19

AL19

AK19

AL20
AM20
AM21
AM22

AL22

AK22

AL23
AM23
AM24
AM25

AL25

AK25

AL26
AM26
AM27
AM28

AL28

AK28

AK29

AL29
AM29
AM30
AM31
AM32
AN32

AP32

AR16
AR17
AR13

AJ17

AJ18

AM16
AG21

AE9

60mA

AF9

45mA

AD9

45mA

B1
B2

D1
D2

E2
E1

E3
E4

G3
G2

G1
G4

F6

G6

N12P- GS1-A1_ BGA_973P

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

PEX_RST_N
PEX_TERMP

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN
XTAL_OUT

XTAL_OUTBUFF
XTAL_SSIN

I2CS_SCL
I2CS_SDA

I2CC_SCL
I2CC_SDA

I2CB_SCL
I2CB_SDA

I2CA_SCL
I2CA_SDA

I2CH_SCL
I2CH_SDA

3

Par t 1 of 7

GPIO

MIOA_D0_NC
MIOA_D1_NC
MIOA_D2_NC
MIOA_D3_NC
MIOA_D4_NC
MIOA_D5_NC
MIOA_D6_NC
MIOA_D7_NC
MIOA_D8_NC

MIOA_D9_NC
MIOA_D10_NC
MIOA_D11_NC
MIOA_D12_NC
MIOA_D13_NC
MIOA_D14_NC

DVO

MIOB_D0_NC

MIOB_D1_NC

MIOB_D2_NC

PCI EXPRESS

MIOB_D3_NC

MIOB_D4_NC

MIOB_D5_NC

MIOB_D6_NC

MIOB_D7_NC

MIOB_D8_NC

MIOB_D9_NC
MIOBD_10_NC
MIOB_D11_NC
MIOB_D12_NC
MIOB_D13_NC
MIOB_D14_NC

MIOA_HSYNC_NC

MIOA_VSYNC_NC

MIOB_HSYNC_NC

MIOB_VSYNC_NC

MIOA_DE_NC

MIOA_CTL3_NC
MIOA_VREF_NC

MIOB_DE_NC

MIOB_CTL3_NC
MIOB_VREF_NC

MIOA_CLKIN_NC

MIOA_CLKOUT_NC

MIOB_CLKIN_NC

MIOB_CLKOUT_NC

MIOA_CLKOUT_NC_N
MIOB_CLKOUT_NC_N

MIOACAL_PD_VDDQ_NC

MIOACAL_PU_GND_NC

MIOBCAL_PD_VDDQ_NC

MIOBCAL_PU_GND_NC

CLK

DACA_GREEN

DACA_HSYNC
DACA_VSYNC

DACB_GREEN

DACs

DACB_HSYNC

I2C

DACB_VSYNC

2010/08/23 2011/08/25

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24

DACA_RED

DACA_BLUE

DACA_VDD
DACA_VREF
DACA_RSET

DACB_RED

DACB_BLUE

DACB_VDD
DACB_VREF
DACB_RSET

OPT@

Compal Secret Data

K1

HP D_C H PD_C

K2
K3
H3
H2

GPU _VID0

H1

GPU _VID1

H4
H5

OVERT# _VGA

H6

THERM# _VGA

J7
K4
K5

ACI N_VGA

H7
J4
J6

HDM I_HPD _VGA

L1
L2
L4
M4

EDP _HPD_ R

L7
L5

HPD _F

K6
L6
M6
M7

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

N3
L3

W1
W2

N2
P5
N5

Y5
W3
AF1

N4

1 2

RV15 10K_0402_5%

R4

AE1

1 2

RV17 10K_0402_5%

V4

T4
W4

U5

RV131 10K_ 0402_5%

T5

AA7

RV132 10K_ 0402_5%

AA6

AM15
AM14
AL14

AM13
AL13

AJ12
AK12
AK13

AK4
AL4
AJ4

AM1
AM2

AG7
AK6
AH7

GPU _VID0 <53>
GPU _VID1 <53>

D2425

2 1

CH751 H-40PT_ SOD323-2

TV6

OPT@

OPT@

OPT@

1 2

OPT@

1 2

OPT@

1 2

RV130 10K _0402_5%

Deciphered Date

@

DGP U_HOLD _RST#<17>

2

AC IN <15,4 3,44,46,48 >

DGP U_HOL D_RST#

PLT_RST#<5,17 ,37,41,43>

PLT_RST#

SN7 4AHC1G 08DCKR_ SC70-5

DV T: <SMT mem o> upd ate U21 P /N

2

Dat e: Sh eet of

1

OPT@

1 2

EDP _HPD_ R

HPD _F

HDM I_HPD _VGA

VGA _EDID_ CLK

VGA _EDID_D ATA

SMB_C LK_GPU

SMB_D ATA_GPU

ACI N_VGA

THERM# _VGA

OVERT# _VGA

HDC P_SCL

HDC P_SDA

VGA_ CRT_DATA

VGA _CRT_CLK

I2C B_SCL

I2C B_SDA

+3VS

1

IN1

2

IN2

U21

OPT@

Title

Size Doc umen t Num ber Re v

Compal Electronics, Inc.

RV4 100K_ 0402_5%

OPT@

1 2

RV5 100K_ 0402_5%

OPT@

1 2

RV29 100K_ 0402_5%

OPT@

R1436 100K_ 0402_5%

OPT@

1 2

RV6 2.2K_ 0402_5%

OPT@

1 2

RV7 2.2K_ 0402_5%

OPT@

1 2

RV8 2.2K_ 0402_5%

OPT@

1 2

RV9 2.2K_ 0402_5%

OPT@

1 2

RV32 10K_0 402_5%

OPT@

1 2

RV10 100K_ 0402_5%

OPT@

1 2

RV37 10K_0 402_5%

OPT@

1 2

RV11 2.2K_ 0402_5%

OPT@

1 2

RV12 2.2K_ 0402_5%

OPT@

1 2

RV13 2.2K_ 0402_5%

OPT@

1 2

RV14 2.2K_ 0402_5%

OPT@

1 2

RV121 2.2K_04 02_5%

OPT@

1 2

RV122 2.2K_04 02_5%

5

P

PLTRST_ VGA#

4

O

G

3

12

OPT@

R426

100K_ 0402_5%

VGA_PCIE/DAC/GPIO

LA-7401P

1

12

+3VS_ DGPU

22 56Mond ay, April 11, 201 1

1.0

5

D D

C C

B B

+3VS_ DGPU

STRAP0<33>
STRAP1<33>
STRAP2<33>

A A

4

OPT@

1 2

RV49 10K_0402 _5%

STRAP0
STRAP1
STRAP2

UV1D

AM11

IFPA_TXC

AM12

IFPA_TXC_N

AM8

IFPA_TXD0

AL8

IFPA_TXD0_N

AM10

IFPA_TXD1

AM9

IFPA_TXD1_N

AK10

IFPA_TXD2

AL10

IFPA_TXD2_N

AK11

IFPA_TXD3

AL11

IFPA_TXD3_N

AP13

IFPB_TXC

AN13

IFPB_TXC_N

AN8

IFPB_TXD4

AP8

IFPB_TXD4_N

AP10

IFPB_TXD5

AN10

IFPB_TXD5_N

AR11

IFPB_TXD6

AR10

IFPB_TXD6_N

AN11

IFPB_TXD7

AP11

IFPB_TXD7_N

AM7

IFPC_L0

AM6

IFPC_L0_N

AL5

IFPC_L1

AM5

IFPC_L1_N

AM3

IFPC_L2

AM4

IFPC_L2_N

AP1

IFPC_L3

AR2

IFPC_L3_N

AR8

IFPD_L0

AR7

IFPD_L0_N

AP7

IFPD_L1

AN7

IFPD_L1_N

AN5

IFPD_L2

AP5

IFPD_L2_N

AR5

IFPD_L3

AR4

IFPD_L3_N

AH6

IFPE_L0

AH5

IFPE_L0_N

AH4

IFPE_L1

AG4

IFPE_L1_N

AF4

IFPE_L2

AF5

IFPE_L2_N

AE6

IFPE_L3

AE5

IFPE_L3_N

AL2

IFPF_L0

AL3

IFPF_L0_N

AJ3

IFPF_L1

AJ2

IFPF_L1_N

AJ1

IFPF_L2

AH1

IFPF_L2_N

AH2

IFPF_L3

AH3

IFPF_L3_N

AP2

IFPC_AUX_I2CW _SCL

AN3

IFPC_AUX_I2CW _SDA_N

AP4

IFPD_AUX_I2CX_SCL

AN4

IFPD_AUX_I2CX_SDA_N

AE4

IFPE_AUX_I2CY_SCL

AD4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

A4

BUFRST_N

AB5

CEC

W5

STRAP0

W7

STRAP1

V7

STRAP2

N12P- GS1-A1_BGA_973P

Part 4 of 7

LVDS/TMDS

GENERAL

MULTI_STRAP_REF0_GND

MULTI_STRAP_REF1_GND

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

NC

NC_27
NC_28
NC_29

VDD_SENSE_0
VDD_SENSE_1
VDD_SENSE_2

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

TEST

TESTMODE

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SI

ROM_SO

ROM_SCLK

NC/SPDIF_NC

THERMDP
THERMDN

OPT@

3

A2
A7
B7
C5
C7
D5
D6
D7
E5
E7
F4
G5
H32
J25
J26
P6
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AF6
AG6
AG20
AJ5
AK15
AL7

D35
P7
AD20

AD19
E35
R7

AP35
AP14
AN14
AN16
AR14
AP16

C3
D3
C4
D4

A5

N9

M9

B5
B4

OPT@

RV134 20K _0402_1%

1 2

OPT@

RV133 4.99 K_0402_1%

1 2

RV135 10K _0402_5%OPT@

1 2

RV136 40.2K_ 0402_1%OPT@

1 2

TESTMODE

RV47 10K_0402_5%

RV41 10K_0402_5%

ROM_CS#
ROM_SI

RV44 10K _0402_5%

ROM_SO
ROM_SCLK

OPT@

1 2

RV48 40.2K_0402_1%

OPT@

1 2

RV50 40.2K_0402_1%

+VGASENSE <53>

OPT@

1 2

TV2
TV3
TV4
TV5

OPT@

1 2

@

12

+3VS_DGPU

ROM_SI <33>
ROM_SO <33>
ROM_SCLK <33>

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Do cument Number R ev

2

Da te: Sh eet of

Compal Electronics, Inc.

VGA_STRAPS

LA-7401P

1

23 56Sun day, April 10 , 2011

1.0

5

D D

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

+VGA_ CORE+VGA_ CORE

UV1G

AB11

VDD_0

AB13

VDD_1

AB15

VDD_2

AB17

VDD_3

AB19

VDD_4

AB21

VDD_5

AB23

VDD_6

AB25

VDD_7

C C

B B

AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24

M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28

L11

VDD_29

L12

VDD_30

L13

VDD_31

L14

VDD_32

L15

VDD_33

L16

VDD_34

L17

VDD_35

L18

VDD_36

L19

VDD_37

L20

VDD_38

L21

VDD_39

L22

VDD_40

L23

VDD_41

L24

VDD_42

L25

VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

Par t 7 of 7

POWER

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98

VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

4

Layout note: Close to Power

+VGA_ CORE

330U_D 2_2V_Y

330U_D 2_2V_Y

1

+

2

OPT@

@

1

+

CV58

CV57

2

DVT:<SMT memo>CV57 SMT-->@

+VGA_ CORE

10U_0603_ 6.3V6M

10U_0603_ 6.3V6M

OPT@

OPT@

2

2

1

Layout note: Under GPU

+VGA_ CORE

1

2

+VGA_ CORE

1

2

CV60

CV61

1

0.047U_0 402_25V6K

0.047U_0 402_25V6K

OPT@

OPT@

1

CV65

CV64

2

0.01U_04 02_25V7K

0.01U_04 02_25V7K

OPT@

OPT@

1

CV75

CV74

2

3

+VGA_ CORE

22U_0603_ 6.3V6M

22U_0603_ 6.3V6M

@

2

CV225

1

22U_0805_ 6.3V6M

4.7U_060 3_6.3V6K

OPT@

1

CV212

2

0.047U_0 402_25V6K

OPT@

1

CV66

2

0.01U_04 02_25V7K

OPT@

1

CV76

2

47U_0805_4V6

OPT@

1

2

1

2

1

2

OPT@

1

CV43

CV10

2

0.022U_0 402_25V7K

OPT@

CV123

0.01U_04 02_25V7K

OPT@

CV77

0.022U_0 402_25V7K

0.022U_0 402_25V7K

OPT@

OPT@

1

1

2

1

2

CV71

CV70

2

0.01U_04 02_25V7K

0.01U_04 02_25V7K

OPT@

OPT@

1

CV79

CV78

2

0.1U_040 2_16V7K

0.1U_040 2_16V7K

OPT@

1

1

CV59

2

2

0.01U_04 02_25V7K

0.01U_04 02_25V7K

OPT@

1

1

CV124

2

2

22U_0603_ 6.3V6M

@

2

1

OPT@

CV63

OPT@

CV125

@

2

CV226

CV227

1

1U_0402_6 .3V4Z

OPT@

1

CV62

2

0.22U_04 02_6.3V6K

0.22U_04 02_6.3V6K

0.22U_04 02_6.3V6K

OPT@

OPT@

12

12

CV44

OPT@

12

CV52

CV55

2

1

N12P-G S1-A1_BGA_973P OPT@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size Docum ent Nu mber R ev

2

Dat e: Sheet of

Compal Electronics, Inc.

VGA_VGA CORE

LA-7401P

24 56Sund ay, April 10, 2011

1

1.0

5

4.7 U_0603_6 .3V6K

+VRAM _1.5VS

D D

+VRAM _1.5VS

C C

Layout note: Under GPU

0.1 U_0402_ 16V4Z

0.1 U_0402_ 16V4Z

OPT@

1

1

CV9 9

2

2

0.1 U_0402_ 16V4Z

OPT@

1

CV1 00

2

4.7 U_0603_6 .3V6K

OPT@

1

2

OPT@

CV1 01

OPT@

1

CV8 2

CV8 3

2

0.1 U_0402_ 16V4Z

0.1 U_0402_ 16V4Z

OPT@

1

2

RV1 23 10K_0402 _5%
RV9 6 1K_04 02_1%

RV1 24 10K_0402 _5%

RV1 25 10K_0402 _5%
RV5 1 1K_04 02_1%

RV1 26 10K_0402 _5%

RV1 27 10K_0402 _5%

RV5 3 1K_04 02_1%

RV1 28 10K_0402 _5%

OPT@

1

CV1 02

CV1 03

2

OPT@

1 2

@

1 2

OPT@

1 2

OPT@

1 2

@

1 2

OPT@

1 2

@

1 2

RV5 2 1K_04 02_1%

OPT@

1 2

@

1 2

OPT@

1 2

4

UV1 E

3.5A

1U_ 0402_6. 3V4Z

1U_ 0402_6. 3V4Z

OPT@

OPT@

1

1

2

CV6 8

CV6 7

2

0.1 U_0402_ 16V4Z

OPT@

1

CV1 04

2

0.1 U_0402_ 16V4Z

OPT@

1

CV1 26

2

0.1 U_0402_ 16V4Z

OPT@

1

CV8 6

2

+IFP AB_PLLVDD

+IFP AB_IOVDD

+IFP D_PLLVDD

+IFP D_IOVD D

+IFP D_PLLVDD

+IFP D_IOVD D

+IF PEF_ PLLVDD

+IF PE_IO VDD

J23
J24

J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27

AJ28

B18

E21
G17
G18
G22

G8
G9

H29

J14
J15
J16
J17
J20
J21

J22
N27
P27
R27
T27
U27
U29
V27
V29
V34

W27

Y27

AK9

AJ11

AG9

AG10

AJ9

AK7

AJ8

AC6
AB6

AK8

AJ6
AL1

AE7
AD7

N12P- GS1-A1_ BGA_973P

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37

IFPAB_PLLVDD
IFPAB_RSET

IFPA_IOVDD
IFPB_IOVDD

IFPC_PLLVDD
IFPC_RSET

IFPC_IOVDD

IFPD_PLLVDD
IFPD_RSET

IFPD_IOVDD

IFPEF_PLLVDD
IFPEF_RSET

IFPE_IOVDD
IFPF_IOVDD

Par t 5 of 7

1600mA

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

POWER

PEX_SVDD_3V3

PEX_SVDD_3V3_NC

MIOA_VDDQ_NC_0
MIOA_VDDQ_NC_1
MIOA_VDDQ_NC_2
MIOA_VDDQ_NC_3

MIOB_VDDQ_NC_0
MIOB_VDDQ_NC_1
MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3

600mA

120mA

PEX_PLLVDD

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

OPT@

3

Layout note: Under GPU

2200m A

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

AK16
AK17
AK21
AK24
AK27

0.1 U_0402_ 16V4Z

0.1 U_0402_ 16V4Z

OPT@

OPT@

1

1

2

1

2

CV8 8

CV8 7

2

0.1 U_0402_ 16V4Z

0.1 U_0402_ 16V4Z

OPT@

OPT@

1

CV9 3

CV9 4

2

1U_ 0402_6. 3V4Z

1U_ 0402_6. 3V4Z

OPT@

OPT@

1

1

2

1

2

1

2

CV9 0

CV8 9

2

1U_ 0402_6. 3V4Z

1U_ 0402_6. 3V4Z

OPT@

OPT@

1

CV9 6

CV9 5

2

0.1 U_0402_ 16V4Z

1U_ 0402_6. 3V4Z

OPT@

OPT@

1

CV10 5

CV10 7

2

120mA

+PEX_ PLLVDD

AG14

120mA

AG19
F7

J10
J11
J12
J13

120mA

J9

P9
R9
T9
U9

AA9
AB9
W9
Y9

0.1 U_0402_ 16V4Z

OPT@

1

CV2 17

2

0.1 U_0402_ 16V4Z

0.1 U_0402_ 16V4Z

OPT@

1

CV2 16

2

1U_ 0402_6. 3V4Z

OPT@

1

1

CV1 12

2

2

2

10U_0 603_6.3V6 M

4.7 U_0603_6 .3V6K

OPT@

1

1

CV9 1

2

2

4.7 U_0603_ 6.3V6K

10U_ 0603_6.3V 6M

OPT@

1

1

CV9 7

2

2

LV4

BLM18 PG121SN 1D_0603

4.7 U_0603_ 6.3V6K

OPT@

1

CV10 8

2

4.7 U_0603_ 6.3V6K

OPT@

OPT@

1

CV1 13

CV1 14

2

22U_0 805_6.3V6 M

OPT@

1

CV9 2

2

22U_ 0805_6.3V 6M

OPT@

1

CV9 8

2

OPT@

0.1 U_0402_ 16V4Z

+3V S_DGPU

OPT@

CV3

OPT@

CV4

12

+1. 05VS_DGP U

+1. 05VS_DGP U

4.7 U_0603_ 6.3V6K

OPT@

1

CV1 09

2

OPT@

CV1 10

+1. 05VS_DGP U

+3V S_DGPU

1

1

2

2

OPT@

CV1 11

4.7 U_0603_6 .3V6K

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size Docum ent Number R ev

2

Da te: She et o f

Compal Electronics, Inc.

VGA_POWER

LA-7401P

25 56Sun day, April 10, 2011

1

1.0

5

D D

C C

B B

A A

4

UV1F

B3

GND_0

B6

GND_1

B9

GND_2

B12

GND_3

B15

GND_4

B21

GND_5

B24

GND_6

B27

GND_7

B30

GND_8

B33

GND_9

C2

GND_10

C34

GND_11

E6

GND_12

E9

GND_13

E12

GND_14

E15

GND_15

E18

GND_16

E24

GND_17

E27

GND_18

E30

GND_19

F2

GND_20

F31

GND_21

F34

GND_22

F5

GND_23

J2

GND_24

J5

GND_25

J31

GND_26

J34

GND_27

K9

GND_28

L9

GND_29

M2

GND_30

M5

GND_31

M11

GND_32

M13

GND_33

M15

GND_34

M17

GND_35

M19

GND_36

M21

GND_37

M23

GND_38

M25

GND_39

M31

GND_40

M34

GND_41

N11

GND_42

N12

GND_43

N13

GND_44

N14

GND_45

N15

GND_46

N16

GND_47

N17

GND_48

N18

GND_49

N19

GND_50

N20

GND_51

N21

GND_52

N22

GND_53

N23

GND_54

N24

GND_55

N25

GND_56

P12

GND_57

P14

GND_58

P16

GND_59

P18

GND_60

P20

GND_61

P22

GND_62

P24

GND_63

R2

GND_64

R5

GND_65

R31

GND_66

R34

GND_67

T11

GND_68

T13

GND_69

T15

GND_70

T17

GND_71

T19

GND_72

T21

GND_73

T23

GND_74

T25

GND_75

U11

GND_76

U12

GND_77

U13

GND_78

U14

GND_79

U15

GND_80

U16

GND_81

U17

GND_82

U18

GND_83

U19

GND_84

U20

GND_85

U21

GND_86

U22

GND_87

U23

GND_88

U24

GND_89

U25

GND_90

V2

GND_91

V5

GND_92

V9

GND_93

V12

GND_94

V14

GND_95

V16

GND_96

N12P-GS 1-A1_BGA_973P

Par t 6 o f 7

GND

3

GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192

OPT@

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size D ocumen t Number Re v

2

Dat e: Sheet of

Compal Electronics, Inc.

VGA_GND

LA-7401P

26 56Su nday, A pril 10, 2011

1

1.0

5

4

3

2

1

UV1B

0.1U_04 02_16V4Z

OPT@

CV229

0.1U_04 02_16V4Z

OPT@

CV230

MDA[0 ..63]

+VRAM_1.5VS

OPT@

RV101 60.4_0 402_1%

OPT@

RV57 10K_0402_5%

D D

C C

+1.05VS _DGPU

+1.05VS _DGPU

B B

LV6

OPT@

BLM18PG3 30SN1D_0603

1 2

10U_060 3_6.3V6M

OPT@

2

CV106

1

LV9

OPT@

BLM18PG3 30SN1D_0603

1 2

10U_060 3_6.3V6M

OPT@

2

CV137

1

10U_060 3_6.3V6M

2

1

10U_060 3_6.3V6M

2

1

MDA[0 ..63]<29,30>

100mA

+FB_ AVDD0

0.1U_04 02_16V4Z

1U_0402 _6.3V4Z

OPT@

1

CV69

2

OPT@

1

CV121

2

1U_0402 _6.3V4Z

OPT@

CV149

OPT@

CV150

OPT@

1

CV84

2

100mA

+FB_ AVDD1

0.1U_04 02_16V4Z

OPT@

1

CV136

2

1

2

1

2

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8

MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

+FB_ AVDD0

+FB_ AVDD1

12
12

L32

FBA_D0

N33

FBA_D1

L33

FBA_D2

N34

FBA_D3

N35

FBA_D4

P35

FBA_D5

P33

FBA_D6

P34

FBA_D7

K35

FBA_D8

K33

FBA_D9

K34

FBA_D10

H33

FBA_D11

G34

FBA_D12

G33

FBA_D13

E34

FBA_D14

E33

FBA_D15

G31

FBA_D16

F30

FBA_D17

G30

FBA_D18

G32

FBA_D19

K30

FBA_D20

K32

FBA_D21

H30

FBA_D22

K31

FBA_D23

L31

FBA_D24

L30

FBA_D25

M32

FBA_D26

N30

FBA_D27

M30

FBA_D28

P31

FBA_D29

R32

FBA_D30

R30

FBA_D31

AG30

FBA_D32

AG32

FBA_D33

AH31

FBA_D34

AF31

FBA_D35

AF30

FBA_D36

AE30

FBA_D37

AC32

FBA_D38

AD30

FBA_D39

AN33

FBA_D40

AL31

FBA_D41

AM33

FBA_D42

AL33

FBA_D43

AK30

FBA_D44

AK32

FBA_D45

AJ30

FBA_D46

AH30

FBA_D47

AH33

FBA_D48

AH35

FBA_D49

AH34

FBA_D50

AH32

FBA_D51

AJ33

FBA_D52

AL35

FBA_D53

AM34

FBA_D54

AM35

FBA_D55

AF33

FBA_D56

AE32

FBA_D57

AF34

FBA_D58

AE35

FBA_D59

AE34

FBA_D60

AE33

FBA_D61

AB32

FBA_D62

AC35

FBA_D63

AG27

FB_DLLA VDD_0

AF27

FB_PLLA VDD_0

J19

FB_DLLA VDD_1

J18

FB_PLLA VDD_1

J27

FB_VREF _NC

T30

FBA_DEB UG0

T29

FBA_DEB UG1

N12P-GS 1-A1_BGA_973P

Par t 2 of 7

MEMORY INTERFACE

FBA_CMD 0
FBA_CMD 1
FBA_CMD 2
FBA_CMD 3
FBA_CMD 4
FBA_CMD 5
FBA_CMD 6
FBA_CMD 7
FBA_CMD 8

FBA_CMD 9
FBA_CMD 10
FBA_CMD 11
FBA_CMD 12
FBA_CMD 13
FBA_CMD 14
FBA_CMD 15
FBA_CMD 16
FBA_CMD 17
FBA_CMD 18
FBA_CMD 19
FBA_CMD 20
FBA_CMD 21
FBA_CMD 22
FBA_CMD 23
FBA_CMD 24
FBA_CMD 25
FBA_CMD 26
FBA_CMD 27
FBA_CMD 28
FBA_CMD 29
FBA_CMD 30
FBA_CMD 31

FBA_DQM 0

FBA_DQM 1

FBA_DQM 2

FBA_DQM 3

FBA_DQM 4

FBA_DQM 5

FBA_DQM 6

FBA_DQM 7

FBA_DQS _RN0

A

FBA_DQS _RN1
FBA_DQS _RN2
FBA_DQS _RN3
FBA_DQS _RN4
FBA_DQS _RN5
FBA_DQS _RN6
FBA_DQS _RN7

FBA_DQS _WP0
FBA_DQS _WP1
FBA_DQS _WP2
FBA_DQS _WP3
FBA_DQS _WP4
FBA_DQS _WP5
FBA_DQS _WP6
FBA_DQS _WP7

FBA_W CK0

FBA_W CK0_N

FBA_W CK1

FBA_W CK1_N

FBA_W CK2

FBA_W CK2_N

FBA_W CK3

FBA_W CK3_N

FBA_CLK 0

FBA_CLK 0_N

FBA_CLK 1

FBA_CLK 1_N

OPT@

U30
V30
U31
V32
T35
U33
W32
W33
W31
W34
U34
U35
U32
T34
T33
W30
AB30
AA30
AB31
AA32
AB33
Y32
Y33
AB34
AB35
Y35
W35
Y34
Y31
Y30
W29
Y29

P32
H34
J30
P30
AF32
AL32
AL34
AF35

L35
G35
H31
N32
AD32
AJ31
AJ35
AC34

L34
H35
J32
N31
AE31
AJ32
AJ34
AC33

P29
R29
L29
M29
AG29
AH29
AD29
AE29

T32
T31

AC31
AC30

CMDA0

CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16

CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

CLKA0
CLKA0#

CLKA1
CLKA1#

CMDA0 <29>

CMDA2 <29>
CMDA3 <29>
CMDA4 <29,30>
CMDA5 <29,30>
CMDA6 <29,30>
CMDA7 <29,30>
CMDA8 <29,30>
CMDA9 <29,30>
CMDA10 <29,30>
CMDA11 <29,30>
CMDA12 <29,30>
CMDA13 <29,30>
CMDA14 <29,30>
CMDA15 <29,30>
CMDA16 <30>

CMDA18 <30>
CMDA19 <30>
CMDA20 <29,30>
CMDA21 <29,30>
CMDA22 <29,30>
CMDA23 <29,30>
CMDA24 <29,30>
CMDA25 <29,30>
CMDA26 <29,30>
CMDA27 <29,30>
CMDA28 <29,30>
CMDA29 <29,30>
CMDA30 <29,30>

CLKA0 <29>
CLKA0# <29>

CLKA1 <30>
CLKA1# <30>

DQMA[ 7..0] <29 ,30>
DQSA #[7..0] <29,30>

DQSA [7..0] < 29,30>

Mode E - Mirror Mode Mapping

GB2-128

Address

CMD3

CMD8

CMD2

CMD21

CMD24

CMD23

CMD26

CMD7

CMD13

CMD4

CMD18

CMD29

CMD27

CMD6

CMD17

CMD19

CMD22

CMD12

CMD28

CMD10

CMD25

CMD9

CMD1

CMD11

CMD0

CMD5

CMD16

CMD20

CMD14

CMD30

DATA Bus

0..31

CKE_L

A8

CS0#_L

A7

A2

A11

A5

A0

CAS#CMD15

BA1

A9

BA0

BA2

A3

A4

A13

WE#

A1

A10

A12

CS1#_L

RAS#

ODT_L

A6

RST

A14

A15

32..63

A8

A6

A1

A9

A4

A12

CAS#

A3

A11

CS0#_H

BA0

A15

BA1

CS1#_H

ODT_H

A5

A14

A10

A2

WE#

A0

RAS#

A7

CKE_H

RST

A13

BA2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size D ocumen t Number Re v

2

Dat e: Sheet of

Compal Electronics, Inc.

VGA_MEM Interface A

LA-7401P

27 56Mo nday, April 11, 2011

1

1.0

5

D D

C C

B B

OPT@

+VRAM_1. 5VS

1 2

RV58 40.2_0402_1%

OPT@

1 2

RV59 40.2_0402_1%

OPT@

1 2

RV60 60.4_0402_1%

+VRAM_1. 5VS

RV105 60.4_0 402_1%
RV61 10 K_0402_5%

OPT@
OPT@

4

UV 1C

B13

FBC_D0

D13

FBC_D1

A13

FBC_D2

A14

FBC_D3

C16

FBC_D4

B16

FBC_D5

A17

FBC_D6

D16

FBC_D7

C13

FBC_D8

B11

FBC_D9

C11

FBC_D10

A11

FBC_D11

C10

FBC_D12

C8

FBC_D13

B8

FBC_D14

A8

FBC_D15

E8

FBC_D16

F8

FBC_D17

F10

FBC_D18

F9

FBC_D19

F12

FBC_D20

D8

FBC_D21

D11

FBC_D22

E11

FBC_D23

D12

FBC_D24

E13

FBC_D25

F13

FBC_D26

F14

FBC_D27

F15

FBC_D28

E16

FBC_D29

F16

FBC_D30

F17

FBC_D31

D29

FBC_D32

F27

FBC_D33

F28

FBC_D34

E28

FBC_D35

D26

FBC_D36

F25

FBC_D37

D24

FBC_D38

E25

FBC_D39

E32

FBC_D40

F32

FBC_D41

D33

FBC_D42

E31

FBC_D43

C33

FBC_D44

F29

FBC_D45

D30

FBC_D46

E29

FBC_D47

B29

FBC_D48

C31

FBC_D49

C29

FBC_D50

B31

FBC_D51

C32

FBC_D52

B32

FBC_D53

B35

FBC_D54

B34

FBC_D55

A29

FBC_D56

B28

FBC_D57

A28

FBC_D58

C28

FBC_D59

C26

FBC_D60

D25

FBC_D61

B25

FBC_D62

A25

FBC_D63

K27

FBCAL_PD_VDDQ

L27

FBCAL_PU_GND

M27

12
12

FBCAL_TERM_GND

G19

FBC_DEBUG0

G16

FBB_DEBUG1

N12P-G S1-A1_BGA_973P

Par t 3 of 7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2

MEMORY INTERFACE C

FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FBC_WCK0_N

FBC_WCK1_N

FBC_WCK2_N

FBC_WCK3_N

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_WCK0

FBC_WCK1

FBC_WCK2

FBC_WCK3

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

OPT@

F18
E19
D18
C17
F19
C19
B17
E20
B19
D20
A19
D19
C20
F20
B20
G21
F22
F24
F23
C25
C23
F21
E22
D21
A23
D22
B23
C22
B22
A22
A20
G20

A16
D10
F11
D15
D27
D34
A34
D28

B14
B10
D9
E14
F26
D31
A31
A26

C14
A10
E10
D14
E26
D32
A32
B26

G14
G15
G11
G12
G27
G28
G24
G25

E17
D17

D23
E23

3

2

1

GB2 -128

Mode E - Mirror Mode Mapping

Address

CMD3

CMD8

CMD2

CMD21

CMD24

CMD23

CMD26

CMD7

CMD13

CMD4

CMD18

CMD29

CMD27

CMD6

CMD17

CMD19

CMD22

CMD12

CMD28

CMD10

CMD25

CMD9

CMD1

CMD11

CMD0

CMD5

CMD16

CMD20

CMD14

CMD30

DATA Bus

0..31

CKE_L

A8

CS0#_L

A7

A2

A11

A5

A0

CAS#CMD15

BA1

A9

BA0

BA2

A3

A4

A13

WE#

A1

A10

A12

CS1#_L

RAS#

ODT_L

A6

RST

A14

A15

32..63

A8

A6

A1

A9

A4

A12

CAS#

A3

A11

CS0#_H

BA0

A15

BA1

CS1#_H

ODT_H

A5

A14

A10

A2

WE#

A0

RAS#

A7

CKE_H

RST

A13

BA2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size Docum ent Nu mber R ev

2

Dat e: Sheet o f

Compal Electronics, Inc.

VGA_MEM Interface C

LA-7401P

28 56Sund ay, April 10, 2011

1

1.0

5

4

3

2

1

DATA Bus

A8

A7

A2

A11

A5

A0

CAS#CMD15

BA1

A9

BA0

BA2

A3

A4

A13

WE#

A1

A10

A12

RAS#

A6

RST

A14

A15

MDA[ 0..63] <27,30>

CMDA [30..0] <2 7,30>

DQMA [7..0] <27,30>

DQS A[7..0] <27 ,30>

DQS A#[7..0] <27 ,30>

32..63

A8

A6

A1

A9

A4

A12

CAS#

A3

A11

CS0#_H

BA0

A15

BA1

CS1#_H

ODT_H

A5

A14

A10

A2

WE#

A0

RAS#

A7

CKE_H

RST

A13

BA2

Memory Partition A - Lower 32 bits

+VRAM_1. 5VS

D D

1.1K_04 02_1%

1.1K_04 02_1%

C C

B B

A A

RV62

OPT@

RV63

OPT@

OPT@

160_040 2_1%

RV64

1 2

CLKA 0#

12

12

CLKA 0

+FBA _VREF0

1

CV151

0.01U_0 402_25V7K

OPT@

2

10K_040 2_5%

1U_0402_6 .3V4Z

1

2

RV65

OPT@

OPT@

1

CV231

2

+FBA _VREF0 +FBA _VREF0

CMDA 7
CMDA 10
CMDA 24
CMDA 6
CMDA 22
CMDA 26
CMDA 5
CMDA 21
CMDA 8
CMDA 4
CMDA 25
CMDA 23
CMDA 9
CMDA 12
CMDA 14
CMDA 30

CMDA 29
CMDA 13
CMDA 27

RV66

243_0402_1%

OPT@

1U_0402_6 .3V4Z

OPT@

1

CV152

2

CLKA 0
CLKA 0#
CMDA 3

CMDA 0
CMDA 2
CMDA 11
CMDA 15
CMDA 28

DQS A0
DQS A3

DQMA0
DQMA3

DQS A#0
DQS A#3

CMDA 20

12

1

2

CLKA 0<27>
CLKA0#<27>

12

+VRAM_1. 5VS

1U_0402_6 .3V4Z

OPT@

CV232

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

0.1U_040 2_16V4Z

1U_0402_6 .3V4Z

OPT@

1

CV153

2

UV5

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL

SDR AM DDR 3

128MX16 H5TQ2G63BFR-11C

@

OPT@

CV154

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

1

2

OPT@

OPT@

1

CV156

CV155

2

MDA3

E3

MDA6

F7

MDA1

F2

MDA4

F8

MDA2

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

2

Group0

MDA7
MDA0
MDA5

MDA29
MDA26
MDA30
MDA24
MDA27

Group3

MDA25
MDA31
MDA28

+VRAM_1. 5VS +V RAM_1.5VS

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

OPT@

OPT@

1

CV157

CV158

2

RV67

243_0402_1%

OPT@

1U_0402_6 .3V4Z

OPT@

1

CV233

2

CMDA 7
CMDA 10
CMDA 24
CMDA 6
CMDA 22
CMDA 26
CMDA 5
CMDA 21
CMDA 8
CMDA 4
CMDA 25
CMDA 23
CMDA 9
CMDA 12
CMDA 14
CMDA 30

CMDA 29
CMDA 13
CMDA 27

CLKA 0
CLKA 0#
CMDA 3

CMDA 0
CMDA 2
CMDA 11
CMDA 15
CMDA 28

DQS A2
DQS A1

DQMA2
DQMA1

DQS A#2
DQS A#1

CMDA 20

12

1

2

M8

H1

N3
P7

P3
N2
P8
P2
R8
R2
T8
R3
L7
R7

N7

T3
T7

M7

M2

N8

M3

J7
K7
K9

K1

L2
J3
K3
L3

F3
C7

E7
D3

G3

B7

T2

L8

J1
L1
J9
L9

+VRAM_1. 5VS

1U_0402_6 .3V4Z

OPT@

1

CV234

2

1U_0402_6 .3V4Z

UV6

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL

SDR AM DDR 3

128MX16 H5TQ2G63BFR-11C

@

OPT@

CV159

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_040 2_16V4Z

1U_0402_6 .3V4Z

1

2

OPT@

OPT@

1

CV161

CV160

2

MDA19

E3

MDA17

F7

MDA18

F2

MDA16

F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

MDA20
MDA22
MDA21
MDA23

MDA14
MDA9
MDA12
MDA11
MDA13
MDA8
MDA15
MDA10

Group2

Group1

CMDA 0

CMDA 3

RV98

10K_040 2_5%

OPT@

GB2 -128

ode E - Mirror Mode Mapping

M

Address

CMD3

CMD8

CMD2

CMD21

CMD24

CMD23

CMD26

CMD7

CMD13

CMD4

CMD18

RV102
10K_040 2_5%

1 2

OPT@

1 2

CMD29

CMD27

CMD6

CMD17

CMD19

CMD22

CMD12

CMD28

CMD10

CMD25

CMD9

CMD1

CMD11

CMD0

0..31

CKE_L

CS0#_L

CS1#_L

ODT_L

CMD5

CMD16

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

OPT@

OPT@

1

1

CV162

2

1

CV163

2

2

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

OPT@

OPT@

1

CV165

CV164

2

CMD20

CMD14

CMD30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size Docum ent Nu mber R ev

2

Dat e: Sheet of

Compal Electronics, Inc.

VGA_VRAM_A Lower

LA-7401P

29 56Sund ay, April 10, 2011

1

1.0

5

4

3

2

1

Memory Partition A - Upper 32 bits

MDA[ 0..63] <27,29>

CMDA [30..0] <2 7,29>

DQMA [7..0] <27,29>

DQS A[7..0] <27 ,29>

DQS A#[7..0] <2 7,29>

GB2 -128

DATA Bus

0..31

CKE_L

A8

CS0#_L

A7

A2

A11

A5

A0

CAS#CMD15

BA1

A9

BA0

BA2

A3

A4

A13

WE#

A1

A10

A12

CS1#_L

RAS#

ODT_L

A6

RST

A14

A15

32..63

A8

A6

A1

A9

A4

A12

CAS#

A3

A11

CS0#_H

BA0

A15

BA1

CS1#_H

ODT_H

A5

A14

A10

A2

WE#

A0

RAS#

A7

CKE_H

RST

A13

BA2

+VRAM_1. 5VS

12

D D

C C

B B

RV68

1.1K_04 02_1%

OPT@

RV69

1.1K_04 02_1%

OPT@

RV70
160_040 2_1%

1 2

OPT@

12

CLKA 1

CLKA 1#

+FBA _VREF1

1

CV166

0.01U_0 402_25V7K

OPT@

2

1U_0402_6 .3V4Z

OPT@

1

CV235

2

CLKA 1<27>
CLKA1#<27>

1

2

+FBA _VREF1 +FBA _VREF1

CMDA 9
CMDA 24
CMDA 10
CMDA 13
CMDA 26
CMDA 22
CMDA 21
CMDA 5
CMDA 8
CMDA 23
CMDA 28
CMDA 4
CMDA 7
CMDA 14
CMDA 12
CMDA 27

CMDA 29
CMDA 6
CMDA 30

CLKA 1
CLKA 1#
CMDA 16

CMDA 19
CMDA 18
CMDA 11
CMDA 15
CMDA 25

DQS A4
DQS A5

DQMA4
DQMA5

DQS A#4
DQS A#5

CMDA 20 CMDA 20

12

RV71

243_0402_1%

OPT@

+VRAM_1. 5VS +VRAM_1. 5VS

1U_0402_6 .3V4Z

1U_0402_6 .3V4Z

OPT@

OPT@

1

1

CV236

CV167

2

2

M8

H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3

L7
R7
N7
T3
T7

M7

M2

N8

M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

J1

L1

J9

L9

1U_0402_6 .3V4Z

0.1U_040 2_16V4Z

OPT@

1

CV168

2

UV8

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL

SDR AM DDR 3

128MX16 H5TQ2G63BFR-11C

@

OPT@

CV169

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

1

2

OPT@

OPT@

1

CV171

CV170

2

MDA38

E3

MDA33

F7

MDA39

F2

MDA35

F8

MDA36

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

+VRAM_1. 5VS +VRAM_1. 5VS

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

0.1U_040 2_16V4Z

1

2

MDA34
MDA37
MDA32

MDA42
MDA45
MDA40
MDA46
MDA41
MDA47
MDA43
MDA44

OPT@

CV172

1

2

Group4

Group5

0.1U_040 2_16V4Z

OPT@

CV173

1U_0402_6 .3V4Z

1U_0402_6 .3V4Z

OPT@

1

1

CV237

2

2

RV72

243_0402_1%

OPT@

OPT@

1

CV238

2

CMDA 9
CMDA 24
CMDA 10
CMDA 13
CMDA 26
CMDA 22
CMDA 21
CMDA 5
CMDA 8
CMDA 23
CMDA 28
CMDA 4
CMDA 7
CMDA 14
CMDA 12
CMDA 27

CMDA 29
CMDA 6
CMDA 30

CLKA 1
CLKA 1#
CMDA 16

CMDA 19
CMDA 18
CMDA 11
CMDA 15
CMDA 25

DQS A7
DQS A6

DQMA7
DQMA6

DQS A#7
DQS A#6

1U_0402_6 .3V4Z

OPT@

CV174

12

UV7

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

128MX16 H5TQ2G63BFR-11C

@

1U_0402_6 .3V4Z

OPT@

1

1

CV175

2

2

96-BALL
SDR AM DDR 3

0.1U_040 2_16V4Z

OPT@

1

CV176

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

MDA59

F7

MDA57

F2

MDA61

F8

MDA60

H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

MDA62
MDA56
MDA63

MDA51
MDA52
MDA48
MDA53
MDA49
MDA54
MDA50
MDA55

Group7

Group6

CMDA 19

CMDA 16

RV100
10K_040 2_5%

OPT@

1 2

Mode E - Mirror Mode Mapping

Address

CMD3

CMD8

CMD2

CMD21

CMD24

CMD23

CMD26

CMD7

CMD13

CMD4

CMD18

CMD29

CMD27

CMD6

RV104
10K_040 2_5%

OPT@

1 2

CMD17

CMD19

CMD22

CMD12

CMD28

CMD10

CMD25

CMD9

CMD1

CMD11

MDA58

E3

CMD0

CMD5

CMD16

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

OPT@

OPT@

1

1

CV178

CV177

2

2

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

OPT@

OPT@

1

CV180

CV179

2

CMD20

CMD14

CMD30

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size Docum ent Nu mber R ev

2

Dat e: Sheet of

Compal Electronics, Inc.

VGA_VRAM_A Upper

LA-7401P

30 56Sund ay, April 10, 2011

1

1.0

5

4

3

2

1

Memory Partition C - Lower 32 bits

D D

GB2 -128

Mode E - Mirror Mode Mapping

Address

CMD3

CMD8

CMD2

CMD21

CMD24

EVT:Del B ch VRAM

C C

B B

CMD23

CMD26

CMD7

CMD13

CMD4

CMD18

CMD29

CMD27

CMD6

CMD17

CMD19

CMD22

CMD12

CMD28

CMD10

CMD25

CMD9

CMD1

CMD11

CMD0

CMD5

CMD16

CMD20

CMD14

CMD30

DATA Bus

0..31

CKE_L

A8

CS0#_L

A7

A2

A11

A5

A0

CAS#CMD15

BA1

A9

BA0

BA2

A3

A4

A13

WE#

A1

A10

A12

CS1#_L

RAS#

ODT_L

A6

RST

A14

A15

32..63

A8

A6

A1

A9

A4

A12

CAS#

A3

A11

CS0#_H

BA0

A15

BA1

CS1#_H

ODT_H

A5

A14

A10

A2

WE#

A0

RAS#

A7

CKE_H

RST

A13

BA2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size Docum ent Nu mber R ev

Cust om

2

Dat e: Sheet of

Compal Electronics, Inc.

VGA_VRAM_C Lower

LA-7401P

31 56Sund ay, April 10, 2011

1

1.0

5

4

3

2

1

Memory Partition C - Upper 32 bits

D D

GB2 -128

ode E - Mirror Mode Mapping

M

Address

CMD3

CMD8

CMD2

CMD21

EVT:Del B ch VRAM

C C

B B

CMD24

CMD23

CMD26

CMD7

CMD13

CMD4

CMD18

CMD29

CMD27

CMD6

CMD17

CMD19

CMD22

CMD12

CMD28

CMD10

CMD25

CMD9

CMD1

CMD11

CMD0

CMD5

CMD16

CMD20

CMD14

CMD30

DATA Bus

0..31

CKE_L

A8

CS0#_L

A7

A2

A11

A5

A0

CAS#CMD15

BA1

A9

BA0

BA2

A3

A4

A13

WE#

A1

A10

A12

CS1#_L

RAS#

ODT_L

A6

RST

A14

A15

32..63

A8

A6

A1

A9

A4

A12

CAS#

A3

A11

CS0#_H

BA0

A15

BA1

CS1#_H

ODT_H

A5

A14

A10

A2

WE#

A0

RAS#

A7

CKE_H

RST

A13

BA2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

Title

Size Docum ent Nu mber R ev

Cust om

2

Dat e: Sheet of

Compal Electronics, Inc.

VGA_VRAM_C Upper

LA-7401P

32 56Sund ay, April 10, 2011

1

1.0

5

+3VS _DGPU

RV87

45.3K_0402_ 1%

D D

STRAP0<23>
STRAP1<23>
STRAP2<23>

STRAP0
STRAP1
STRAP2

OPT@

1 2

RV85

34.8K_0402_ 1%

@

1 2

RV86
15K_0402_1 %

@

1 2

4

Note: RV89 = 5K for set N12P-GV ,ID=1050)

3

Physical
Strapping p in

ROM_SO FB_0_BAR_SI ZE

ROM_SCLK

ROM_SI

STRAP2

STRAP1

STRAP0

Power Rail

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU

Logical
Strapping B it3

XCLK_417

PCI_DEVID[4]

PCI_DEVID[3]

3GIO_PADCFG[3]

USER[3]

2

Logical
Strapping B it2

SUB_VENDOR

Logical
Strapping B it1

SLOT_CLK_CFG

RAMCFG[1]RAMCFG[3] RAMCFG[2]

1

Logical
Strapping B it0

VGA_DEVICESMB_ALT_ADD R

PEX_PLLEN_TERM

RAMCFG[0]

PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]

USER[0]USER[1]USER[2]

RV84

45.3K_0402_ 1%

@

1 2

C C

ROM_SI<23>

ROM_SO<23>

ROM_ SCLK<23>

ROM_SI
ROM_SO
ROM_ SCLK

RV90

4.99K_0402_ 1%

@

1 2

RV93
15K_0402_1 %

@

1 2

X76 strap pin for VRAM vender and size

B B

GPU V RAM size Compa l VRAM P/N

N12P-GV (29x29) 64bit
(Layou t 4pcs only)

Proje ct ROM_S I net s etup

PAJ80(14")

PAJ90(15.6")

512M(x4) DDR3 Samsung 64Mx16 1.5V

1G(x4)

1G(x4)

RV88

34.8K_0402_ 1%

OPT@

1 2

RV91
10K_0402_1 %

OPT@

1 2

RV94

4.99K_0402_ 1%

@

1 2

CH VRAM de scrip tion

Desc ription

DDR3 Hynix 64Mx16 1.5V

CHA

CHA

DDR3 Hynix 128Mx16 1.5V

CHA

DDR3 Samsung 128Mx16 1.5V

CHA

1 2

+3VS _DGPU

1 2

1 2

RV89

4.99K_0402_ 1%

OPT@

RV92

4.99K_0402_ 1%

OPT@

RV95
15K_0402_1 %

@

SA0000324C0 H5TQ1G63DFR-12C 800MHz512M(X4)

SA00004HS00

SA00003VS00

SA00003MQ40

K4W1G1646G-BC12 800MHz

H5TQ2G63BFR-12C 800MHz

K4W2G1646C-HC12 800MHz

ROM_SI net for VRAM strap

Resistor Va lues

5K

10K

15K

20K

25K

30K

35K

45K

0010

0011

0110

0111

PD or PU
(RV93)

PD 15K

PD 20K

PD 35K

PD 45K

R P/N

SD034150280(15K)

SD034200280(20K)

SD034348280(34.8K)

SD034453280(45.3K)

Pull-up to +3VS

1000

1001

1010

1011

1100

1101

1110

1111

Pull-down to Gnd

0000

0001

0010

0011

0100

0101

0110

0111

SUB_VENDOR

0

No VBIOS ROM (Default)

1

BIOS ROM is present

FB_0_BAR_SIZE

0

256MB (Default)

1

Reserved

3GIO_PADCFG

3GIO_PADCFG [3:0]

0110

Notebook Default

XCLK_417

0

277MHz (Default)

1

Reserved

USER Straps

User[3:0]

1000-1100

PEX_PLL_EN_TERM

0

Disable (Def ault)

1

Enab le

Cust ome r d efined

SLOT_CLOCK_CFG

0

GPU and MCH don't share a common ref erence clock

1

GPU and MCH share a common re ference clock (Default)

SMBUS_ALT_ADDR

0

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

3

Compal Secret Data

Deciphered Date

0x9E (Default)

1

0x9C (Multi-GPU usage)

2

Title

Size Docu ment Nu mber R ev

Cus tom

Dat e: Sheet o f

VGA_DEVICE

0

3D Device

1

VGA Device (Default)

Compal Electronics, Inc.

VGA_MSIC

LA-7401P

33 56Sund ay, Apri l 10, 2011

1

1.0

5

LCD POWER CIRCUIT

+LCDV DD

12

R521

300_0603_5%

D D

2N7002DW-T/R7_SOT363-6

PCH_E NVDD<16>

C C

BKOFF#<43>

B B

61

Q16A

R319

100K_0402_5%

DPST_PWM<16>

BKOFF# DISPOF F#

+3VS

12

R522
100K_0402_5%

2

3

Q16B

5

2N7002DW-T/R7_SOT363-6

4

1 2

1 2

R532 0_0402_5%

R992 0_0402_5%

1 2

RB751V_SOD323

12

R542
10K_0402_5%

R523
1K_0402_5%

0.047U_0402_16V7K

INVTPWM

12

@

@

D6

21

12

C468

4.7U_0805_10V4Z

R536
10K_0402_5%

2

1

2

C469

INVTPWM <56>

+3VS

12

R540

4

+3VS

W=60mils

3

S

Q17
AO3413L_SOT23-3

G

D

1

1

2

4.7K_0402_5%

1

2

+LCDVD D

1

2

C462

4.7U_0805_10V4Z

W=60mils

C471

0.1U_0402_16V4Z

Driver IC

DISPOF F# <56>

USB20_N3<17>

USB20_P3<17>

D

river IC

3

1

C463

0.1U_0402_16V4Z

2

R533 0_0402_5%

WCM 2012F2SF-900T04_0805

3

2

R534 0_0402_5%

USB20_CMOS_N3

USB20_CMOS_P3

+LCDV DD+3VS

3

2

Need closed to JLVDS1

1

C464

10U_0603_6.3V6M

2

PCH_LC D_DATA<16>

+LG_VOUT

@

1 2

4

4

1

1

L51

1 2

@

@

1 2

C483 22P_0402_50V8J

@

1 2

C482 22P_0402_50V8J

1

C465

0.1U_0402_16V4Z

2

PCH_L CD_CLK<16>

PCH_TXOUT0+<16>

PCH_TXOUT0-<16>

PCH_TXOUT1+<16>

PCH_TXOUT1-<16>

PCH_TXOUT2+<16>

PCH_TXOUT2-<16>

PCH_TXCLK+<16>
PCH_TXCLK-< 16>

FB1<56>
FB2<56>
FB3<56>
FB4<56>

USB20_CMOS_N3

USB20_CMOS_P3

+3VS

2

W=60mils

C466

680P_0402_50V7K

+INVPWR_B+

1

2

1

C467
68P_0402_50V8J

2

L18

FBMA-L11-201209-221LMA30T_0805

L19

FBMA-L11-201209-221LMA30T_0805

SM010014520 3000 ma
220 ohm@100mhz
DCR 0.04

LCD/LED PANEL Connector

+LCDV DD+3VS

JLVDS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

FB1
FB2
FB3
FB4

USB20_CMOS_N3
USB20_CMOS_P3

DVT:<EMI>L51 @-->SMT

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

GND

32

GND

33

GND

34

GND

35

GND

STARC_111H 30-000000-G4-R

CONN@

PVT:Add L1 for ESD reuqest

12

12

FB1

FB2

FB3

FB4

C909 22P_0 402_50V8J@

C910 22P_0 402_50V8J@

C911 22P_0 402_50V8J@

C912 22P_0 402_50V8J@

1 2

1 2

1 2

1 2

1

L1

1 2

1.2UH _1231AS-H-1R2N-P3_2.9A_30%

FB1

FB2

FB3

FB4

D26

2

3

PJDLC05C_SOT23-3

@

D27

2

3

PJDLC05C_SOT23-3

@

B+

1

1

D5

6

I/O4

5

A A

+3VS

USB20_CMOS_N3

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

REF2

4

I/O3

PJUSB208H_SOT23-6

2010/08/23 2011/08/25

REF1

I/O1

I/O2

USB20_CMOS_P3

1

2

3

DVT:<EMI>D5 @-->SMT

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet

Compal Electronics, Inc.

LVDS Connector

1

34 56Monday , April 11, 2011

1.0

of

5

+5VS

D1 2

CH4 91DPT _SOT23- 3

2 1

W=40mils

+HD MI_5 V

2 1

+5VS

D D

C C

D8

CH4 91DPT _SOT23- 3

SDV O_SD ATA<1 6>

SDV O_SC LK<16>

SDV O_SD ATA

SDV O_SC LK

Lane R eversed on Page 16

B B

21

F1 1 .1A _6V_SM D1812P11 0TF

0.1 U_04 02_16V4 Z

+3VS

5

4

Q93 B

2N7 002D W-T/R 7_SOT36 3-6

PCH _DPB _P2<16>
PCH _DPB _N2<16>

PCH _DPB _P1<16>
PCH _DPB _N1<16>

PCH _DPB _P0<16>
PCH _DPB _N0<16>

PCH _DPB _P3<16>
PCH _DPB _N3<16>

+HD MI_5 V_OUT

1

C50 1

2

RB7 51V_ SOD323

2

Q93 A
2N7 002D W-T/R 7_SOT36 3-6

3

4

+HD MI_5 V_OUT

D1 3

R54 6

2.2 K_0402 _5%

61

C4 97
C4 96

C4 95
C4 94

C4 93
C4 92

C4 99
C4 98

21

D1 4

12

21

RB7 51V_ SOD323

12

R54 5

2.2 K_0402 _5%

10P _0402_ 50V8J

12
12

12
12

12
12

12
12

HDM I_S DATA

HDM I_S CLK

C49 0

@

0.1 U_04 02_16V7K

0.1 U_04 02_16V7K

0.1 U_04 02_16V7K

0.1 U_04 02_16V7K

0.1 U_04 02_16V7K

0.1 U_04 02_16V7K

0.1 U_04 02_16V7K

0.1 U_04 02_16V7K

3

+3VS

2

1

HDMI Connector

12

R56 9

1M_ 0402_5%

PC H_D PB_H PD<16>

2N7 002D W-T/R 7_SOT36 3-6

1

1

C49 1
10P _0402_ 50V8J

2

2

@

HDMI _TX2+

HDMI _TX2-

HDMI _TX1+

HDMI _TX1-

HDMI _TX0+

HDMI _TX0-

HDM I_C LK+

HDM I_C LK-

Note: Reresve for RF

HDMI_TX2+

R94 5 6 80_0 402_5%

HDMI_TX2-

R94 4 6 80_0 402_5%

HDMI_TX1+

R94 7 6 80_0 402_5%

HDMI_TX1-

R94 6 6 80_0 402_5%

HDMI_TX0+

R94 9 6 80_0 402_5%

HDMI_TX0-

R94 8 6 80_0 402_5%

HDMI_CLK+

R95 1 6 80_0 402_5%

HDMI_CLK-

R95 0 6 80_0 402_5%

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

2

Q23A

HDM I_D ETECT

61

12

R56 6
20K _0402_5 %

12

C903
220P_0402_25V8J

@

+HD MI_5 V_OUT

HDM I_D ETECT

HDM I_S DATA
HDM I_S CLK

HDM I_R _CK-

HDM I_R _CK+
HDM I_R _D0-

HDM I_R _D0+
HDM I_R _D1-

HDM I_R _D1+
HDM I_R _D2-

HDM I_R _D2+

JHD MI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

GND

11

CK_shield

GND

10

CK+

GND

9

D0-

GND

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUY IN_ 1000 42MR 019S153Z L

CO NN@

20
21
22
23

DVT:<EMI>L20 L23 L24 L25 @-->SMT

+3VS

3

Q23 B

5

2N7 002D W-T/R 7_SOT36 3-6

4

SM07000131 0 400ma 90ohm@10 0mhz DCR 0.3

HDM I_C LK+

WCM 2012 F2SF -900T04 _0805

L20

HDM I_C LK-

WCM 2012 F2SF -900T04 _0805

L23

HDMI _TX0- H DMI _R_ D0-

WCM 2012 F2SF- 900T04_0 805

L24

HDMI _TX1- H DMI _R_ D1-

HDMI _TX2+

WCM 2012 F2SF- 900T04_0 805

L25

HDMI _TX2- H DMI _R_ D2-

@

R54 7 0_04 02_5%

1 2

4

4

1

1

R54 8 0_04 02_5%

1 2

R54 9 0_04 02_5%

1 2

4

4

1

1

R55 0 0_04 02_5%

1 2

R55 2 0_04 02_5%

1 2

4

4

1

1

R55 7 0_04 02_5%

1 2

R56 0 0_04 02_5%

1 2

4

4

1

1

R56 3 0_04 02_5%

1 2

3

3

2

2

@

@

3

3

2

2

@
@

3

3

2

2

@
@

3

3

2

2

@

HDM I_R _CK+

HDM I_R _CK-

HDM I_R _D0+HDM I_TX0+

HDM I_R _D1+HDM I_TX1+

HDM I_R _D2+

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

2

Title

Size Doc ume nt N umber R ev

C

Dat e: Shee t

Compal Electronics, Inc.

HDMI Connector

1

35 56Sun day, Ap ril 10, 2011

o f

1.0

A

B

C

D

E

CRT Connector

+HDMI_5V_OUT

W=40mils

2

3

2

3

CRT_R_2

CRT_G_2

CRT_B_2

D9

1

2.2P_0402_50V8C

1

C518

2

10P_0402_50V8J

1

C522

2

10P_0402_50V8J

C523

1

2

1

2

1

2.2P_0402_50V8C

C517

CRT_H SYNC_2

CRT_V SYNC_2

1 1

DVT:Update L28~L33 footprint

PJDLC05 C_SOT23-3

PVT:< Memo>

L28

0_0402_5%

PCH_C RT_R<16>

PCH_C RT_G<16>

PCH_CRT_ B<16>

2 2

PCH_C RT_HSYNC<16>

PCH_C RT_VSYNC<16>

150_0402_1%

150_0402_1%

12

12

R570

R571

1 2

C521 0.1U _0402_16V4Z

150_0402_1%

12

R572

2.2P_0402_50V8C

2.2P_0402_50V8C

1

C511

2

@

1

1

C512

2

2

@

DVT:+CRT_VCC_-->+HDMI_5V_OUT

+HDMI_5V_OUT

U42

5

1

74AHCT1G125GW_SOT353-5

P

4

OE#

A2Y

G

3

1 2

C526 0.1U _0402_16V4Z

+HDMI_5V_OUT

@

1 2

0_0402_5%

1 2

0_0402_5%

1 2

2.2P_0402_50V8C

C513

R573 10K_0402_5%

U43

5

1

74AHCT1G125GW_SOT353-5

P

OE#

A2Y

G

3

L30

L32

4

CRT_R_1

CRT_G_1

CRT_B_1

12

CRT_H SYNC_1

CRT_V SYNC_1

2.2P_0402_50V8C

2.2P_0402_50V8C

1

C514

2

1

1

C515

2

2

SM01001 2010 300ma 120ohm@100mhz DCR 0.4

DVT:+CRT_VCC_-->+HDMI_5V_OUT

NBQ100505T-800Y_0402

1 2

NBQ100505T-800Y_0402

1 2

NBQ100505T-800Y_0402

1 2

2.2P_0402_50V8C

C516

MBC1 608121YZF_0603

MBC1 608121YZF_0603

L29

L31

L33

L34

1 2

L35

1 2

DVT:De l F2 and chnage D12 to P35

D10
PJDLC05 C_SOT23-3

DVT:Add T7

2.2P_0402_50V8C

1

C519

2

DVT:+CRT_VCC_-->+HDMI_5V_OUT

JCRT1

T7 P AD

PCH_CRT_ DATA_R

100P_0402_50V8J

C520

1

2

PCH_C RT_CLK_R

68P_0402_50V8J

68P_0402_50V8J

1

1

C524

C525

2

2

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_0 70546FR0 15S293ZR

CONN @

1 2

+HDMI_5V_OUT

G

G

R574
100K_0402_5%

16
17

CRT_DET# <18>

DVT:+CRT_VCC_-->+HDMI_5V_OUT

3 3

+3VS

2

PCH_CRT_DATA<16>

PCH_C RT_CLK<16>

4 4

PCH_CRT_DATA

5

3

4

Q25B
2N7002DW -T/R7_SOT363-6

Q25A
2N7002DW-T/R7_SOT363-6

4.7K_0402_5%

61

R575

+HDMI_5V_OUT

12

12

R576

4.7K_0402_5%

PCH_CRT_ DATA_R

PCH_C RT_CLK_RPCH_C RT_CLK

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DVT:+CRT_VCC_-->+HDMI_5V_OUT

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

CRT Connector

E

36 56Sun day, April 10, 2 011

1.0

5

=60mils

+3VALW

1U_0402_6.3V6K

C531

1

2

D D

B+_BIAS

@

1 2

R577 0_1206_5%

123

DGS

Q57
AO3413L_SOT23-3

1.5A

4

W=60milsW

+LAN_IO

3

Layout note: Close to U44.12

Layout note: Close to U44.27

0.1U_0402_16V7K

C532

1

2

Layout note: Close to U44.39

0.1U_0402_16V7K

C533

1

2

Layout note: Close to U44.42

0.1U_0402_16V7K

C534

1

2

Layout note: Close to U44.47

0.1U_0402_16V7K

C535

1

2

Layout note: Close to U44.48

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

C536

C537

1

2

2

+LAN_VDD

1

Layout note: Close to U44.3

Layout note: Close to U44.6

Layout note: Close to U44.9

Layout note: Close to U44.13

Layout note: Close to U44.29

Layout note: Close to U44.41

Layout note: Close to U44.45

0.1U_0402_16V7K

0.1U_0402_16V7K

C538

1

1

2

2

0.1U_0402_16V7K

C539

C540

1

1

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C541

C542

1

1

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C543

C544

1

2

R578
470K_0402_5%

1 2

EN_WOL

13

D

WOL_EN<43>

C C

2

G

PCIE_PRX_DTX_P1<14>

PCIE_PRX_DTX_N1<14>

PCIE_PTX_C_DRX_P1<14>
PCIE_PTX_C_DRX_N1<14>

CLK_P CIE_LAN<14>

CLK_P CIE_LAN#<14>

Q88

S

2N7002E-T1-GE3_SOT23-3

LAN_CLKRE Q#<14>

PLT_RST#<5,17,22,41,43>

DVT :PC _P ME# P U o n P4 3

EC_PME#<43>

PCH_P CIE_WAKE#<15,41>

1 2

+3VS

R586 1K_0402_5%

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

5

15K_0402_5%

B B

LAN_M DIN3

R995 0_0402_5%

LAN_MDIP3

R996 0_0402_5%

LAN_M DIN2

R997 0_0402_5%

LAN_MDIP2

R998 0_0402_5%

LAN_M DIN1

R999 0_0402_5%

LAN_MDIP1

A A

R1000 0_0402_5%

LAN_M DIN0

R1001 0_0402_5%

LAN_MDIP0

R1002 0_0402_5%

+LAN_IO

R587

1 2

+LAN_IO

Note: 3.3V - Enable switching regulator

2

C556

0.01U_0402_16V7K

1

Note: +LAN_IO R isi ng tim e (10%~90%) >1mS and <100mS

R579

1.5M_0402_5%

1 2

C550 0.1U_0402_16V7K

1 2

C551 0.1U_0402_16V7K

1 2

1 2

R895 0_0402_5%

@

1 2

R2680 10K_0402_5%

1 2

R584 0_0402_5%

@

1 2

R585 0_0402_5%

ISOLATEB

+LAN_IO

@

12

R2678 0_0402_5%
R591 0_0402_5%

0V - Disable switching regulator

+V_DAC
LAN_M DIN3_R
LAN_MDIP3_R

+V_DAC
LAN_M DIN2_R
LAN_MDIP2_R

+V_DAC
LAN_M DIN1_R
LAN_MDIP1_R

+V_DAC
LAN_M DIN0_R
LAN_MDIP0_R

12

1
2
3

4
5

7
8
9

10
11
12

0.1U_0603_25V7K

C545

1

2

PCIE_PRX_C_DTX_P1

PCIE_PRX_C_DTX_N1

LAN_C LKREQ#_R

1 2

R588 10K_0402_5%

1 2

R589 1K_0402_5%

+LAN_VD DREG

1 2

R592 2.49K_0402_1%

TS1

TCT1
TD1+
TD1-

TCT2
TD2+
TD2-6MX2-

TCT3
TD3+
TD3-

TCT4
TD4+
TD4-

TAIMA G _IH-160 LAN_24P

MCT1
MX1+

MX1-

MCT2
MX2+

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

24

RJ45_TX3-

23

RJ45_TX3+

22

21

RJ45_TX2-

20

RJ45_TX2+

19

18

RJ45_RX1-

17

RJ45_RX1+

16

15

RJ45_TX0-

14

RJ45_TX0+

13

4

U44

22

23

17
18

16

25

19
20

XTLI

43

XTLO

44

LANWAKEB

28

26

14
15
38

33

34
35

46

24
49

RTL8111E-VL-CGT_QFN48_6X6

1 2

R594 75_0402_5%

1 2

R595 75_0402_5%

1 2

R597 75_0402_5%

1 2

R598 75_0402_5%

HSOP

HSON

HSIP
HSIN

CLKREQB

PERSTB

REFCLK_P
REFCLK_N

CKXTAL1

CKXTAL2

LANWAKEB

ISOLATEB

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

ENSWREG

VDDREG
VDDREG

RSET

GND
PGND

LED3/EEDO
LED1/EESK

EECS/SCL

EEDI/SDA

NC/MDIP2

NC/MDIN2

NC/MDIP3

NC/MDIN3

DVDD10
DVDD10
DVDD10

DVDD33
DVDD33

AVDD33
AVDD33
AVDD33
AVDD33

EVDD10

AVDD10
AVDD10
AVDD10
AVDD10

REGOUT

W=60mi ls W=6 0mils

L36

+LAN_SROUT1.05

Layout note: All components close to U44.36 within 200mils

31
37
40

LED0

R582 10K_0402_5%

1 2

30

R583 10K_0402_5%

1 2

32

LAN_MDIP0

1

MDIP0
MDIN0
MDIP1
MDIN1

LAN_M DIN0

2

LAN_MDIP1

4

LAN_M DIN1

5

LAN_MDIP2

7

LAN_M DIN2

8

LAN_MDIP3

10

LAN_M DIN3

11

13
29
41

27
39

12
42
47
48

21

3
6
9
45

36

2

C557
1000P_1206_2KV7K

1

Secur ity Classification

+LAN_EVDD10

+LAN_SROUT1.05

+LAN_VDD

+LAN_IO

+LAN_VDD

L12

1 2

100UH _SSC0301101MCF_0.18A_20%

D15
PJDLC05C_SOT23-3

1

1 2

C2600 0.1U_0402_16V7K

1 2

C2601 0.1U_0402_16V7K

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LAN_C LKREQ#_R

2

3

2010/08/23 2011/08/25

2.2UH +-5% NLC2 52018T-2R2J-N

1 2

@

1 2

R2677 10K_0402_5%

RJ45_TX0+

RJ45_TX0-

RJ45_RX1+

RJ45_TX2+

RJ45_TX2-

RJ45_RX1-

RJ45_TX3+

RJ45_TX3-

LAN_GND

Compal Secret Data

Deciphered Date

+LAN_IO

2

+LAN_VDD

4.7U_0603_6.3V6K

0.1U_0402_16V7K

C552

1

2

C553

2

1

DVT :Add R590 R957

CLK_FKEX2<14>

1 2

C554 27P_0402_50V8J

1 2

C555 27P_0402_50V8J

JLAN1

conn@

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

SANTA_130451-F

+LAN_VDD

1 2

R581 0_0603_5%

+LAN_IO

R580 0_0603_5%

1 2

R957 22_0402_5%

R590 0_0402_5%

12

25MHZ_20PF_7A25000012
Y5

LED_YELLOW_A1

LED_YELLOW_A2

LED_GREEN_B1

LED_GREEN_B2

Cus tom

9

10

11

12

13

GND

14

GND

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

LAN Realtek RTL8111E

LA-7401P

+LAN_EVDD10

+LAN_VD DREG

1 2

@

12

DVT :Up dat e Y5 sourc e

XTLO

LAN_GND

1

0.1U_0402_16V7K

C548

1

1

2

2

4.7U_06 03_6.3V6K

C546

1

1

2

2

XTLI

37 56Monday , April 11, 2011

1U_0402_6.3V6K

C549

0.1U_0402_16V7K

C547

1.0

A

+5VS

4.7U_0805_10V4Z

CA75

@

1 1

@

1 2

RA55 10K_0402_5%

1 2

RA54 0_0603_5%

UA2

@

1

IN

2

GND

3

SHDN

APL5151-475BC-TRG_SOT23-5

OUT

5

4

BP

40mil

@

2

1

0.01U_0402_16V7K

CA77

B

+AVDD

1

CA3

@

2

10U_0805_10V6K

+5VS_PVDD

CA61

0.1U_0402_16V7K

600 mA

1

CA57

2

0.1U_0402_16V7K

1

2

C

RA2

0_0603_5%

1

CA56
10U_0805_10V6K

2

0.1U_0402_16V7K

12

CA44

1

2

+5VS

1

CA43
10U_0805_10V6K

2

D

E

Pre MP:CA19,CA20,CA25,CA26-->SMT

+3VS_DVDD

1 2

+3VS

RA1 FBMH1608HM601-T

12

MIC1_ LINE1_R_L<39>

MIC1_ LINE1_R_R<39>

CA11

0.01U_0402_25V7K

@

For EMI

Ext. Mic

2 2

HDA_R ST_AUDIO#<13>

RA40

100K_0402_5%

@

EC_MUTE#

12

RA45

3 3

4.7K_0402_5%

CA8

10U_0805_10V6K

DMIC_DATA<42>

0.1U_0402_16V7K

1

2

MIC1_ LINE1_R_L

MIC1_ LINE1_R_R

1 2

CA12 100P_0402_50V8J

1

2

CA15

2.2U_0603_6.3V6K

+MIC1_VREFO_L

SENSE_A

1 2

DGND

CA7

DMIC_DATA

DMIC_ CLK_R

EC_MUTE#

HDA_R ST_AUDIO#

MONO_IN

CA214.7U_0805_10V6K

12

12

CA224.7U_0805_10V6K

1

2

MIC_L

MIC_R

35 mA

CA1

0.1U_0402_16V7K

1

DVDD

23

LINE1_L

24

LINE1_R

14

LINE2_L

15

LINE2_R

21

MIC1_L

22

MIC1_R

16

MIC2_L

17

MIC2_R

2

GPIO0/DMIC_DATA

3

GPIO1/DMIC_CLK

4

PD#

11

RESET#

12

PCBEEP

13

SENSE A

18

SENSE B

36

CBP

35

CBN

31

MIC1_VREFO_L

43

PVSS2

42

PVSS1

49

DVSS2

7

DVSS1

9

DVDD_IO

ALC259-VB5-GR_QFN48_7X7

46

AVDD125AVDD2

PVDD139PVDD2

SPK_OUT_L+

SPK_OUT_L-

SPK_OUT_R+

SPK_OUT_R-

HP_OUT_L

HP_OUT_R

SYNC

BCLK

SDATA_OUT

SDATA_IN

EAPD

SPDIFO

MONO_OUT

MIC2_VREFO

MIC1_VREFO_R

LDO_CAP

VREF

JDREF

CPVEE

AVSS1
AVSS2

+AVDD

38

68 mA

UA1

40
41

45
44

32
33

HDA _SYNC_A UDIO

10

HDA_B ITCLK_AUDIO

6

HDA_S DOUT_AUDIO

5

HDA_S DIN0_R

8

47

RA53 0_0402_5%

48

20

29

30
28

AC_VR EF

27

AC_JD REF

19

CPVEE

34

CA14 2.2 U_0603_6.3V6K

26
37

10U_0805_10V6K

1

CA5

CA4

2

0.1U_0402_16V7K

SPKL+
SPKL-

SPKR+
SPKR-

RA6 33_0402_5%

RA9 20K _0402_1%

1 2

AGND

1

2

12

12

+MIC1_VR EFO_R

12

0.1U_0402_16V7K

1

CA6 0.1U_0402 _16V7K

2

HP_L <39>
HP_R <39>

HDA _SYNC_AUD IO <13>

HDA_B ITCLK_AUDIO <13>

HDA_S DOUT_AUDIO <13>

HDA_S DIN0 <13>EC_MUTE#<43>

EAPD <43>

CA23

10U_0805_10V6K

1 2

EVT:CA16 SMT-->@

1

12

2

@

CA16

2.2U_0603_6.3V6K

CA17

plac e close to chip

Speaker Connector

EC Beep

BEEP#<43 >

PCI Beep

HDA_SPKR<13>

RA13

0_0603_5%

RA14

0_0603_5%

RA15

0_0603_5%

RA16

0_0603_5%

12

12

12

12

SPKL+

SPKL-

SPKR+

SPKR-

1

CA19
680P_0402_50V7K

2

1

CA20
680P_0402_50V7K

2

1

CA25
680P_0402_50V7K

2

1

CA26
680P_0402_50V7K

2

RA7

1 2

47K_0402_5%

RA8

1 2

47K_0402_5%

4.7K_0402_5%

SPK_L1

2

CA24
1U_0402_6.3V4Z

@

1

SPK_L2

SPK_R1

2

CA27
1U_0402_6.3V4Z

@

1

SPK_R2

Beep sound

12

RA12

CA13

1 2

0.1U_0402_16V7K

1

CA18
100P_0402_50V8J

2

SPK_L1 <39>

SPK_L2 <39>

SPK_R1 <39>

SPK_R2 <39>

MONO_IN

EC c ontr ol EC_MUT E# behavio r: High-st ate / low- state

For EMI

RA47

DMIC_CLK<42>

FBMA-10-100505-301T

DMIC_ CLK_R

1

CA74
27P_0402_50V8J

@

2

CA48 0.1U_0603_50V7K@

1 2

CA49 0.1U_0603_50V7K@

1 2

CA50 0.1U_0603_50V7K@

1 2

1 2

RA18 FBMH1608HM601-T

HDA_B ITCLK_AUDIO

1 2

RA42 22_0402_5%

P

re MP: RA42-->SMT and CA62-->SMT

CA62

1 2

27P_0402_50V8J

Sense Pin Impedance

39.2K

SENSE A

4 4

20K

10K

5.1K

A

Codec Signals

PORT-I (PIN 32, 33)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

(PIN 48)

Function

Headpho ne out

Ext. MIC

MIC_SENSE<39>

B

place close to chip

MIC_SENSE SENSE_A

NBA_PLUG<39>

RA10 20K_0402_1%

RA21 39.2K_0402_1%

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

C

2010/04/28 2011/04/28

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Audio ALC259

LA-7401P

E

38 56Monday , April 11, 2011

1.0

5

4

3

2

1

< SPK connector >

DA7

1

D D

SPK_R 1<38>
SPK_R 2<38>
SPK_L1<38>
SPK_L2<38>

SPK_R 1
SPK_R 2
SPK_L1
SPK_L2

PJDL C05C_SO T23-3

DA6

1

PJDL C05C_SO T23-3

3

2

3

2

JSPK1
E&T_3 806-F04N-02R

6

GND2

5

GND1

4

4

3

3

2

2

1

1

CON N@

RA46

C C

MIC_S ENSE<38>

MIC 1_R

MIC1_ L

B B

NBA_ PLUG<38>

HP_ R<38>

HP_L<38>

A A

NBA_P LUG

HP_ R HP_ R_R

MIC 1_LINE1_ R_R<38>

MIC1 _LINE1_R _L<38>

LA2 FBM- 11-160808-601-T_0603

1 2

LA1 FBM- 11-160808-601-T_0603

1 2

RA52 8 2_0402_1%

1 2

RA51 8 2_0402_1%

1 2

MIC 1_LINE1 _R_R

MIC 1_LINE1_ R_L

CA68

33P_0 402_50V8J

HP _L_RH P_L

1K_04 02_5%

12

12

1K_04 02_5%

RA35

MIC 1_R_1

MIC1_ L_1

1

1

CA69
33P_0 402_50V8J

2

2

LA4 F BM-11-160808-6 01-T_0603

1 2

LA3 F BM-11-160808-6 01-T_0603

1 2

0.1U_ 0402_16V4Z

CA67

12

RA36 2 .2K_0402_5%

MIC 1_R

MIC1_ L

12

RA29 2 .2K_0402_5%

MIC_S ENSE

2

3

1

@

12

CA70

33P_0 402_50V8J

+MIC1 _VREFO_ R

+MIC1 _VREFO_L

DA8
PJDL C05C_SO T23-3

PR

PL

1

1

CA71
33P_0 402_50V8J

2

2

1

CA63

0.1U_ 0402_16V 4Z

2

@

2

3

1

DA9
PJDL C05C_SO T23-3

< JMIC1 Jack>

CON N@

SINGA _2SJ228 5-112252_6P-T

4

SHL D1

6

5
2

1

3

JMIC 1

1

CA64

0.1U_ 0402_16V4Z

2

<JHP2 Head phone >

CON N@

SINGA _2SJ228 5-112252_6P-T

4

SHL D1

6

5
2

1

3

JH P2

1

CA66

0.1U_ 0402_16V7K

2

ES D r eq ues t

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/04/07 2 012/10/21

3

Compal Secret Data

Deciphered Date

Title

Size D ocum ent Nu mber R ev

2

Dat e: Sheet o f

Compal Electronics, Inc.

SPK/Jack

LA-7401P

39 56Monday, A pril 11, 2011

1

1.0

5

4

3

2

1

D D

+5VS

SATA_PTX_DRX_P0<13>
SATA_PTX_DRX_N0<13>

SATA_PRX_DTX_N0<13>

SATA_PRX_DTX_P0<13>

C C

B+_BIAS

R678

470K_0402_5%

B B

ODD_EN#<18>

5

Q31A on P41

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

+5VS

R677 0_0805_5%

1U_0402_6.3V6K

C624

1

1 2

2

ODD_EN

3

Q31B
2N7002DW -T/R7_SOT363-6

4

C612 0.01U_0402_16V7K
C613 0.01U_0402_16V7K

C614 0.01U_0402_16V7K
C611 0.01U_0402_16V7K

@

1 2

D

6

S

45

2

Q30

1

SI3456DDV-T1-GE3_TSOP6

G

3

1.5M_0402_5%

1 2

1 2
1 2

1 2
1 2

+5VS_ODD

R681

0.1U_0402_16V4Z

C629

1

2

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

SATA_PTX_DRX_P1<13>

SATA_PTX_DRX_N1<13>

SATA_PRX_DTX_N1<13>
SATA_PRX_DTX_P1<13>

SATA_PTX_DRX_P2<13>

SATA_PTX_DRX_N2<13>

SATA_PRX_DTX_N2<13>
SATA_PRX_DTX_P2<13>

SATA HDD1 Connector

JHD D1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

G11119

10

C922 0.01U_0402_16V7KSATA@

1 2

C923 0.01U_0402_16V7KSATA@

1 2

C924 0.01U_0402_16V7KSATA@

1 2

C925 0.01U_0402_16V7KSATA@

1 2

1 2

C621 0.01U_0402_16V7K

1 2

C620 0.01U_0402_16V7K

1 2

C622 0.01U_0402_16V7K

1 2

C623 0.01U_0402_16V7K

12

G12

10

ACES_87212-10G0

CONN@

ODD_DETECT #_R<13>

ODD_DETECT#<18>

ODD_DA#<17>

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2

+5VS

100mils

1U_0402_6.3V4Z

10U_0805_10V4Z

1

2

1 2

R679 0_0402_5%

1 2

R680 0_0402_5%

C616

C617

1

2

ODD_DETECT #_R

ODD_D A#_R

1000P_0402_50V7K

0.1U_0402_16V4Z

1

2

C619

C618

1

2

<14" SATA ODD Connector>

JODD1

CONN@

1

GND

2

TX+

3

TX-

4

GND

5

RX-

6

RX+

7

GND

8

DP

+5VS_ODD

9

5V

10

5V

11

MD

12

GND

13

GND

SANTA_202801-1_13P

GND
GND

14
15

+5VS_ODD

80mils

10U_0805_10V4Z

1U_04 02_6.3V4Z

C625

1

2

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

HDD/ODD Connector

C626

1

2

1

1000P_0402_50V7K

0.1U_0402_16V4Z

C628

C627

1

1

2

2

40 56Sun day, April 10, 2 011

1.0

A

PCH_P CIE_WAKE#<15,37>

MINI1_ CLKREQ#<14>

CLK_P CIE_MINI1#<14>

CLK_P CIE_MINI1<14>

CLK_P CI_DEBUG<17>

PCIE_PRX_DTX_N2<14>
PCIE_PRX_DTX_P2<14>

1K_0402_5%

60mil

PLT_RST#<5,17,2 2,37,43>

RM13

+3VS_WLAN

1

2

E51RXD_P80CLK

12

Wireless LAN

1 1

PCIE_PTX_C_DRX_N2<14>
PCIE_PTX_C_DRX_P2<14>

BT_CTRL E51TXD_P80DATA

61

2 2

BT_ON#<18>

Q31A

2

2N7002DW-T/R7_SOT363-6

E51TXD_P80DATA<43>

E51RXD_P80CLK<43>

BT_CTRL E51RXD_P80CLK

B

4.7U_0805_10V4Z

0.1U_0402_16V4Z

CM3

CM2

1

2

1 2

RM5 0_0402_5%

PLT_RST#
CLK_P CI_DEBUG

0.1U_0402_16V4Z

1

2

@

+3VS_WLAN

CM4

12

RM6
100K_0402_5%

+1.5VS +1.5VS_WLAN

1 2

RM4 0_060 3_5%

T89 PAD

BT_CTRL

60mil

JMIN1

1

1

3

3

5

5

7

7
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

MOLEX_67910-5700

conn@

4.7U_0805_10V4Z

1

2

+1.5VS_WLAN

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

C

D

E

Mini Card P ower Rating

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CM5

CM6

CM7

1

1

2

2

+3VS_WLAN

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

RM7 0_0402_5%

1 2

RM8 0_0402_5%@

1 2

D_CK_SCLK <11,12,14>
D_CK_SDATA <11,12,14>

USB20_N4 <17>
USB20_P4 <17>

RM9 0_0402_5%@

1 2

LPC_FRAME# <13,43>
LPC_AD3 <13,43>
LPC_AD2 <13,43>
LPC_AD1 <13,43>
LPC_AD0 <13,43>

PCH_W L_OFF# <17>

WL_O FF# <43>

MINI1_LED#

12

RM10
100K_0402_5%

(9~16mA)

+3VS_WLAN

Pow er

+3VS

+3V

+1.5VS

+3VS_WLAN

RM12

10K_0402_5%

Primary Pow er (mA)

Peak Normal

1000

330

500

12

DM1

2 1

CH751H-40PT_S OD323-2

RM11 0_0402_5%@

1 2

750

250

375

Auxili ary Power (mA)

Normal

250 (wake enable )

5 (Not wake enabl e)

PLT_RST_BUF# <17>

Q31A on P41

CLK_P CI_DEBUG

3 3

4 4

1 2

R955 10_0402_5%

@

A

C908

1 2

12P_0402_50V8J

@

100K_0402_5%

WLAN _PWR_EN#<43>

B

+3VS +3VS

RM2

1 2

47K_0402_5%

RM3

1 2

WLAN _PWR_EN#_R

0.1U_0402_16V7K

CM1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

3

1

S

QM1
AO3413L_SOT23-3

2

G

D

1

C

12

RM1

@

0_0805_5%

+3VS_WLAN

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

MINI CARD WLAN & WWAN

E

41 56Monday , April 11, 2011

1.0

A

1 1

2 2

B

C

DVT :Ad d R 56 0 and up da te JP CR1 p in1 8 ne t

DVT :Up dat e USB _OC 1#--> USB_O C0#

USB_EN#<43>

PVT:Add R993

USB_EN#

USB_OC0#<17,43>

+5VALW

D

R960
100K_0402_5%

1 2

R993 0_0402_5%

+5VALW

1 2

E

JPCR1

+3VS

USB20_N10<17>
USB20_P10<17>

USB20_N0<17>
USB20_P0<17>

USB20_N1<17>
USB20_P1<17>

DMIC_C LK<38>
DMIC_DATA<38>

USB20_N10
USB20_P10

USB20_N0
USB20_P0

USB20_N1
USB20_P1

DMIC_C LK
DMIC_DATA

DMIC_C LK

CA72 33P_0402_50V8J

DMIC_DATA

CA73 10P_0402_50V8J

Layout note: Close to JMIC2

1 2

@

1 2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

GND1

24

GND2

ACES_87213-2200G

CONN@

Pre MP:Add C923 C924

+5VALW +USB_VCCB

150U_B2_6.3VM_R35M

10U_0805_10V4Z

1000P_0402_50V7K

1U_0402_6.3V6K

0.1U_0402_16V4Z

C2507

1

2

PVT:Update net USB_CHARGE_EN#-->USB_CHARGE_EN

3 3

USB_OC1#<17,43>

<P CH > <C ONN >

USB_C HARGE_EN<43>

USB_CTL1<43>
USB_CTL2<43>
USB_CTL3<43>

R994 0_0402_5%

1 2

USB20_N2<17>
USB20_P2<17>

R2600 0_0402_5%

1 2

USB20_N2 U2D_D N2
USB20_P2

U2415

1

IN

13

2
3

4
5

6
7
8

OUT

NC

FAULT#

DM_OUT

DM_IN

DP_OUT

DP_IN

ILIM_SEL

ILIM1

EN

ILIM0

CTL1
CTL2

GND

CTL3

GPAD

TPS2540RTER_QFN16_3X3

<BOM S tructure>

1

C667

C2543

1

+

2

2

12

9

11

U2D_D P2

10

15
16

R2498 19.1K_0402_1%

14
17

12

C669

1

2

1U_0402_6.3V6K

1

1

C927

C928

2

2

@

12

USB20_N2_R

4

4

1

1

L48

3

3

USB20_P2_R

2

2

12

@

U2D_D N2
U2D_D P2

R716 0_0402_5%

WCM2012F2S-900T04_0805

R717 0_0402_5%

+USB_VCCB

USB20_N2_R

USB20_P2_R

JUSB1

1

VCC

2

D-

3

D+

4

GND

GND1
GND2
GND3
GND4

Che ck fo otpri nt

5
6
7
8

ACON_ UARBG-4K1926_4P

CONN@

PVT:Remove R2664 R2499 R2500 R2501 for DFX issue

DVT:<EMI>L48 D20 @-->SMT

D20

6

CH3

+USB_VCCB

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

USB20_N2_R

5

Vp

4

CH4

PJUSB208H_SOT23-6

D

USB20_P2_R

3

CH2

2

Vn

1

CH1

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

USB Combo Connector

E

42 56Monday , April 11, 2011

1.0

5

R961 0_0402_5%

PCH_P WR_EN<46>

EC_PME#<37>

ON/ OFF<44>
EAPD<38>

ENBKL<16>

D D

BATT_LOW_LED#<44>

PWR_LED#<44>

PM_SLP_S4#<15>

LID_SW#<44>

H_PEC I<5,18>

C C

GFX_CORE_PW RGD<54>

EC_PME#

EAPD

PCH_P WROK

PWR_LED#

BATT_LOW_LED#

PM_SLP_S4#
EC_AC IN

EC_ON

ON/ OFF

EC_PME# EC_PME#_R
LID_SW#

PM_SLP_S4#

43_0402_1%

PCH_P WR_EN

1 2

R962 0_0402_5%9012@

1 2

R963 0_0402_5%

1 2

R964 0_0402_5%9012@

1 2

R965 0_0402_5%9012@

1 2

R979 0_0402_5%

1 2

R966 0_0402_5%9012@

1 2

R980 0_0402_5%

1 2

R967 0_0402_5%9012@

1 2

R981 0_0402_5%

1 2

R982 0_0402_5%9012@

1 2

R968 0_0402_5%9012@

1 2

R969 0_0402_5%

1 2

R970 0_0402_5%9012@

1 2

R971 0_0402_5%

1 2

R972 0_0402_5%9012@

1 2

R973 0_0402_5%

1 2

R974 0_0402_5%9012@

1 2

R975 0_0402_5%

1 2

R976 0_0402_5%9012@

1 2

R977 0_0402_5%

1 2

R978 0_0402_5%9012@

1 2

12

R743

R989 0_0402_5%
R990 0_0402_5%9012@

PCH_P WR_EN_RPCH_P WR_EN

ON/ OFF_RON /OFF

ENBKL_9012E NBKL

H_PRO CHOT#_EC_RH_PRO CHOT#_EC

BATT_LOW_LED#_RBATT_LOW_LED#

PWR _LED#_R

H_PRO CHOT#_EC_R_2H_PRO CHOT#_EC

PM_SLP_S4#_R

ENBKL_RENBKL

EAPD_REA PD

EC_AC IN_REC_AC IN

PVT:Update net name USB_CHARGE_EN

R983 0_0402_5%

1 2

R984 0_0402_5%9012@

1 2

1 2
1 2

GFX_C ORE_PWRGD_RGFX_CORE_PW RGD

PVT :Fi ne tu ne fo r K B9012

R719

R735

@

33_0402_5%

1 2

33_0402_5%

12

12

@

CLK_P CI_LPC

12

KSO1
KSO2
EC_SMI#

EC_SMB_DA1

EC_SMB_CK1

EC_SMB_CK2
EC_SMB_DA2
EC_SC I#

EC_RST#

DVT:Add USB_OC0# on pin16
Add USB_OC1# on pin17

Pre MP:Add PWR_BTN_LED#

SUSCLK<15>

C680

@

22P_0402_50V8J

12

+3VALW_EC

+3VALW_EC

B B

22P_0402_50V8J

+3VS

R721 47K_0402_5%

C681 0 .1U_0402_16V4Z

Note: ENE Recommand

R728 47K_0402_5%

1 2

R730 47K_0402_5%

1 2

R731 10K_0402_5%

1 2

R732 2.2K_0402_5%

1 2

R734 2.2K_0402_5%

1 2

C683

@

12

Layout note: Reserve for EMI please close to U64

R741 2.2K_0402_5%

1 2

R742 2.2K_0402_5%

1 2

R744 10K_0402_5%

1 2

KSI[ 0..7]<44>

KSO[0.. 17]<44>

PV T:< Me mo >

DV T :Updat e net name S USC LK_ R- ->S USC LK

EC_XCLK1

A A

C686

@

22P_0402_50V8J

X1

32.768 KHZ_12.5PF_Q13MC14610002

EC_XCLK0

1

2

1

OSC4OSC

NC3NC

2

@

C687

22P_0402_50V8J

1

2

@

PV T:< Me mo >

DVT :C6 86 C687 15p-->22p

5

4

+3VLP

+3VALW

USB_C HARGE_EN<42>

EC_PE CI_R

PECI_KB9012_RPECI_KB9012

R943

0_0805_5%

1 2

R718
0_0805_5%

1 2

GATEA20<18>

EC_KBRST#<18>

SERIR Q<13>

LPC_FRAME#<13,41>

LPC_AD3<13,41>
LPC_AD2<13,41>
LPC_AD1<13,41>
LPC_AD0<13,41>

CLK_P CI_LPC<17>

PLT_RST#<5,17, 22,37,41>

EC_SC I#<18>

KSI [0..7]

KSO[0.. 17]

EC_SMB_CK1<55>
EC_SMB_DA1<55>
EC_SMB_CK2<14,22>
EC_SMB_DA2<14,22>

PM_SLP_S3#<15>
PM_SLP_S5#<15>

EC_SMI#<18>
USB_OC0#<17,42>
USB_OC1#<17,42>

WL_OFF#<41>

SUSW ARN#<15>

FAN_SPEED1<45>

E51TXD_P80DATA<41>
E51RXD_P80CLK<41>

PWR_BTN_LED#<44>

1 2

R746 0_0402_5%

R958

100K_0402_5%

4

@

0.1U_0402_16V4Z

C673

1

2

GATEA20
EC_KBRST#
SERIR Q
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_P CI_LPC
PLT_RST#
EC_RST#
EC_SC I#

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
USB_OC0#
USB_OC1#
WL_O FF#
SUSW ARN#

FAN_SPEED 1
PCH_P WR_EN_R
E51TXD_P80DATA
E51RXD_P80CLK
ON/ OFF_R
PWR_BTN_LED#

12

1

2

0.1U_0402_16V4Z

C674

1

1

2

2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

T96PAD

EC_XCLK1

C917
20P_0402_50V8J

+3VALW_EC

1000P_0402_50V7K

1000P_0402_50V7K

C677

2

2

1

1

LPC & MISC

Int . K/B
Matr ix

FBMA-L11-160808-800LMT_0603

C678

9

VCC

PS 2 Inter face

SM Bu s

+3VALW_EC +EC_VCCA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C676

C675

1

2

U64

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LPC_FRAME#/LFRAME#

5

LPC_AD3/LAD3

7

LPC_AD2/LAD2

8

LPC_AD1/LAD1

10

LPC_AD0/LAD0

12

CLK_PCI_EC/PCICLK

13

PCIRST#/GPIO05

37

EC_RST#/ECRST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/SCL0/GPIO44

78

EC_SMB_DA1/SDA0/GPIO45

79

EC_SMB_CK2/SCL1/GPIO46

80

EC_SMB_DA2/SDA1/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

SUS_PWR_DN_AC K/GPIO0D

25

INVT_PWM/PWM 2/GPIO11

28

FAN_SPEED1/FANFB0/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLK1

123

XCLK0

KB930QF-A1_LQFP128_14X14

DVT :Add R958 C917

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

L49

1 2

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

PWM Output

DA Ou tput

EC_MUTE#/PSCLK1/GPIO4A

SPI De vic e I /F

SP I Fl ash ROM

GP IO

GP IO

G PO

GP I

GND

GND

GND

GND

GND

11

24

35

94

113

3

0.1U_0402_16V4Z

1 2

R985

1 2

0_0402_5%

67

AVCC

PWM0/GPIO0F

BEEP#/PWM1/GPIO10

FANPWM0/GPIO12

ACOFF/FANPWM1/GPIO13

BATT_TEMP/AD0/GPI38

BATT_OVP/AD1/GPI39

ADP_I/AD2/GPI3A

AD In pu t

USB_EN#/PSDAT1/GPIO4B

CAP_INT#/PSCLK2/GPIO4C

TP_DATA/PSDAT3/GPIO4F

WOL_EN/SDICLK/GPXIOA01

ME_EN/SDIMOSI/GPXIOA02

AD3/GPI3B

AD4/GPI42
AD5/GPI43

DAC_BRIG/DA0/GPO3C

EN_DFAN1/DA1/GPO3D

IREF/DA2/GPO3E

DA3/GPO3F

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXIOA00

LID_SW#/GPXIOD00

SPIDI/MISO

SPIDO/MOSI

SPICLK/GPIO58

SPICS#

GPIO40

H_PECI/GPIO41

FSTCHG/GPIO50

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

PWR_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04

EC_ON/GPXIOA05

EC_SWI#/GPXIOA06

ICH_PWROK/GPXIOA07

BKOFF#/GPXIOA08

RF_OFF#/GPXIOA09

GPXIOA10
GPXIOA11

PM_SLP_S4#/GPXIOD01

ENBKL/GPXIOD02

EAPD/GPXIOD03

EC_THERM#/GPXIOD04

SUSP#/GPXIOD05

PBTN_OUT#/GPXIOD06

EC_PME#/GPXIOD07

AGND

69

20mil

ECAGND

FBMA-L11-160808-800LMT_0603

V18R

L50

2010/08/23 2011/08/25

C679

1 2

0_0402_5%

ECAGND

R986

@

WLAN _PWR_EN#

21

BEEP#

23

PCH_D PWROK

26

ACOF F

27

BATT_TEMP

63
64

ADP_I

65
66
75

IMON_R

76

68

EN_DF AN1

70

IRE F

71

CHGVA DJ

72

EC_MUTE#

83

USB_EN#

84

USB_CTL1

85

H_PRO CHOT#_EC_R

86

TP_CLK

87

TP_DATA

88

GFX_C ORE_PWRGD_R

97

WOL_EN

98

HDA_S DO

99

LID_SW#

109

FRD #_R

119

FWR #_R

120

SPI_CLK_R

126
128

ENBKL_9012

73

EC_PE CI_R

74

FSTCHG

89

USB_CTL2

90

USB_CTL3

91

BATT_LOW_LED#_R

92

PWR _LED#_R

93

SYS ON

95

VR_ON

121

EC_AC IN_R

127

PCH_RSMRST#

100

EC_LID_OUT#

101

EC_ON

102

H_PRO CHOT#_EC_R_2

103

PCH_P WROK

104

BKOFF#

105

CPU1.5V_S3_GATE

106

PCH_APW ROK

107

SA_PGOOD

108

PM_SLP_S4#_R

110

ENBKL_R

112

EAPD_R

114

EC_PME#_R

115

SUSP#

116

PBTN_OUT#

117

PECI_KB9012_R

118

+V18REC_XCLK0

124

12

R718

R943

+3VLP

R985

R986

C682 100P_0402_50V8J

T93 PAD

R726 0_0402_5%

T95 PAD

R736 0_0402_5%

1 2

R737 33_0402_5%

1 2

R738 33_0402_5%

1 2

R739 33_0402_5%

1 2

1

C688

4.7U_0805_10V4Z

2

Compal Secret Data

Deciphered Date

2

KB930 KB9012

+3 VALW +3 VL P +3 VA LW +3 VLP

SM T

SM T

@

SM T

@

SM T

SM T

@

@

SM T

@

@

SM T

@

SM T

@

DVT :Ad d W LAN _P WR_ EN#

WLAN _PWR_EN# <41>
BEEP# <38>

PCH_D PWROK <15>

ACOF F <48>

12

12

EN_DF AN1 <45>
IREF <48>
CHGVA DJ <48>

EC_MUTE# <38>

USB_EN# <42>
USB_CTL1 <42>

TP_CLK < 44>
TP_DATA <44>

ECAGND

BATT_TEMP <55>

ADP_I <48,55>

IMVP_IMON <54>

DVT :Ad d USB _EN#

DVT :Ad d U SB_ CTL1

PVT :Fi ne tu ne fo r K B9012

WOL_EN <37>
HDA_S DO <13>

FR D#
FWR #
SPI_CLK
FSEL#FSEL#_R

FSTCHG <48>
USB_CTL2 <42>
USB_CTL3 <42>

SYSO N < 46,50>
VR_ON <54>

PCH_RSMRST# <15>

EC_LI D_OUT# <14>

EC_ON <44>

PCH_P WROK <15>
BKOFF# <34>
CPU1.5V_S3_GATE < 10>
PCH_APW ROK <15>

SA_PGOOD <52>

SUSP# <10,46,51>
PBTN_OUT# <15>

DVT :Ad d U SB_CT L2 an d U SB_CT L3

DVT :Add PECI_KB9 012_ R

2

EC_MUTE#

PWR_LED#

EC_PME#

PWR_BTN_LED#

TP_CLK

TP_DATA

GFX_CORE_PW RGD

PCH_P WROK

VR_ON

PCH_APW ROK

PCH_D PWROK

PLT_RST#

R733 200K_0402_5%

2 1

D22

EC_AC IN

C684 100P_0402_50V8J

LID_SW#

VR_HOT#<54>

H_PRO CHOT#_EC

1

@

R720 10K_0402_5%

1 2

R2650 10K_0402_5%

R723 10K_0402_5%

R1005 10K_0402_5%

R724 4.7K_0402_5%

R725 4.7K_0402_5%

R727 10K_0402_5%

12

CH751H-40PT_S OD323-2

12

1 2

R2653 100K_0402_5%

VR_HOT#

@

1 2

1 2

1 2

R928 10K_0402_5%

1 2

R931 10K_0402_5%

1 2

R930 10K_0402_5%

1 2

R929 10K_0402_5%@

1 2

R927 100K_0402_5%

R740

0_0402_5%

12

3

5

4

ACIN < 15,22,44,46,48>

+3VALW_EC

12

12

12

+5VS

+3VS

12

+3VALW_EC

+3VALW_EC

H_PROCH OT# <5,55>

2N7002DW-T/R7_SOT363-6
Q34B

Q34B on P46

SPI ROM 128KB

+3VALW_EC

1

C685

0.1U_0402_16V4Z

SA00002C 100 (S IC FL 1MB MX25L1005AMC-12G SOP 8P

3.3V)

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet

2

FSEL#

SPI_CLK

SPI_CLK_R

Layout note: Reserve for EMI please close to U64

Compal Electronics, Inc.

EC ENE-KB930

20mil s

@

22_0402_5%

R747

U52

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

1

Q

D

MX25L1005AMC-12G_SO8

C689

@

100P_0402_50V8J

12

1 2

43 56Monday , April 11, 2011

4

FR D#FWR#

2

of

1.0

INT_KBD Connector
New key board

Key board pin define (Down)

CIS symbol (DVT)

CIS symbol (PVT need reverese pin define)

28

GND1

27

GND2

26

26

25

25

24

24

23

23

22

22

21

21

Key boa rd Pin 1 is KSO16

P in 2 is KSO15

.. .

ACES_88514-02601-071

20
19
18
17
16
15
14
13
12
11
10

JKB1

CONN@

20
19
18
17
16
15
14
13
12
11
10
9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

Pin1

Pin1

KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSI0
KSI1
KSO2
KSI2
KSI3
KSI4
KSI5
KSO1
KSO0
KSI6
KSI7

PVT:Update JKB1 footprint

Pin1

KSI [0..7]

KSO[0.. 17]

KSO7

KSO6

KSO5

KSO4

KSO3

KSI4

KSO2

KSO1

KSO0

KSI5

KSI6

KSI7

@

1 2

@

C695 100P_0402_50V8J

1 2

C697 100P_0402_50V8J

@

1 2

@

C699 100P_0402_50V8J

1 2

C701 100P_0402_50V8J

@

1 2

@

C703 100P_0402_50V8J

1 2

C705 100P_0402_50V8J

@

1 2

C707 100P_0402_50V8J

@

1 2

C709 100P_0402_50V8J

@

1 2

C711 100P_0402_50V8J

@

1 2

@

C713 100P_0402_50V8J

1 2

C715 100P_0402_50V8J

@

1 2

C717 100P_0402_50V8J

KSI [0..7] <43>

KSO[0.. 17] <43>

KSO16

KSO17

KSO15

KSO14

KSO13

KSO12

KSI0

KSO11

KSO10

KSI1

KSI2

KSO9

KSI3

KSO8

@

1 2

@

C691 100P_ 0402_50V8J

1 2

@

C693 100P_ 0402_50V8J

1 2

@

C696 100P_ 0402_50V8J

1 2

C698 100P_ 0402_50V8J

@

1 2

C700 100P_ 0402_50V8J

@

1 2

C702 100P_ 0402_50V8J

@

1 2

@

C704 100P_ 0402_50V8J

1 2

C706 100P_ 0402_50V8J

@

1 2

C708 100P_ 0402_50V8J

@

1 2

C710 100P_ 0402_50V8J

@

1 2

@

C712 100P_ 0402_50V8J

1 2

C714 100P_ 0402_50V8J

@

1 2

C716 100P_ 0402_50V8J

@

1 2

C718 100P_ 0402_50V8J

TP_CLK<43>
TP_DATA<43>

EVT:Check pin define

<T/P conn>

+5VS

JTP1

1

1

2

2

3

3

100P_0402_50V8J

100P_0402_50V8J

@

@

1

1

C692

C694

2

2

4

4

5

G1

6

G2

ACES_85201-0405N

CONN@

PVT:Update JTP1 footprint

TP_CLK

TP_DATA

2

3

1

+5VS

@

D24
PJDLC05 C_SOT23-3

0.1U_0402_16V4Z

C690

1

2

ON/OFF BTN#

EC_ON<43>

+5VALW

Pre MP:Add R1003 R1004

Power Button

+3VALW_EC

R759
100K_0402_5%

1 2

2

EC_ON

R764

10K_0402_5%

1

D25
CHN20 2UPT_SC70-3

1 2

51ON#

3

13

D

2

G

Q36

S

2N7002E-T1-GE3_SOT23-3

R1003 0_0402_5%

1 2

R1004 0_0402_5%

1 2

@

+3VALW_EC+5VS

100P_0402_50V8J

DVT:R759 pin1 +3VALW-->+3VALW_EC

ON/ OFF <43>

51ON# <47>

DVT:Del R937

EC requirement

C921

1

100P_0402_50V8J

2

<Power Button/Lid B conn>

JPWR 1

1

7

1

PWR_BTN_LED#

C919

100P_0402_50V8J

ON/OFF BTN#

1

2

C920

PWR_BTN_LED#<43>

LID_SW#<43>

1

2

DVT:Update JPWR1 footprint and pin define

Pre MP:Update JPWR1 pin define

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

G1

2

2

3

3

4

4

5

5

6

8

6

G2

ACES_88231-06001

CONN@

2010/08/23 2011/08/25

<Power on LED>

+5VALW

<AC in LED>

DVT:Add R959 for DC in LED control

+5VALW

<HDD LED>

+5VS

Compal Secret Data

Deciphered Date

1 2

R752 330_0402_5%

1 2

R753 330_0402_5%

1 2

R952 330_0402_5%

LED3

2 1

HT-110TW_WHITE

LED4

2 1

HT-110TW_WHITE

LED5

2 1

HT-110TW_WHITE

Title

Size Doc ument Number Re v

B

Date: Sheet

PWR_LED#

1 2

R959 0_040 2_5%

2

G

1 3

D

S

@

Q39

2N7002_SOT23-3

PCH_SATALED#

Compal Electronics, Inc.

KB/TP/LED/FUNC

PWR_LED# <43>

BATT_LOW_LED# <43>

ACIN < 15,22,43,46,48>

PCH_SATALED# <13>

of

44 56Monday , April 11, 2011

1.0

Vgs =4 .5V ,I d= 3A,Rd s<22 mohm

Q85

OPT@

AO3416_SOT23-3

+1.05VS_DGPU

DGPU_ PWR_EN<17,53>

2N7002DW-T/R7_SOT363-6

1

2

OPT@

100K_0402_5%

DGPU_ PWR_EN#

Q80A

OPT@

+1.05VS to +1.05VS_DGPU

0.01U_0402_25V7K

OPT@

C2572

+5VALW

1 2

61

2

C2564

0.1U_0402_16V7K

OPT@

1

2

C2565

OPT@

0.01U_0402_25V7K

1

@

4.7U_0805_10V4Z

R2639

OPT@

47K_0402_5%

DGPU_ PWR_EN#

2

Q86A
2N7002DW -T/R7_SOT363-6

OPT@

+3VS

Vgs =- 4.5 V, Id =3A,R ds<9 7moh m

3

S

Q50
AO3413L_SOT23-3

2

G

OPT@

D

1

1

C2567

2

+1.05VS

13

D

2

G

S

4.7U_0603_6.3V6K

@

C2573

2

1U_0402_6.3V4Z

1

OPT@

1

C2574

2

+3VS TO +3VS_DGPU

+3VALW

R2633

R2634

OPT@

1 2

47K_0402_5%

1 2

61

2

1

2

1U_0402_6.3V4Z

OPT@

C2566

+1.05VS_DGPU

OPT@

470_0805_5%

1 2

3

OPT@

Q86B

5

2N7002DW-T/R7_SOT363-6

4

+3VS_DGPU

R2640

FAN Connector

+5VS

1A

2

C904

10U_0805_10V6K

U66

1

EN

GND

2

VIN

EN_DF AN1<43>

+FAN1

1

C905
10U_0805_10V6K

2

GND

3

VOUT

GND

4

VSET

GND

APL5607KI-TRG_SO8

1

8
7
6
5

+FAN1

2

C906
1000P_0402_50V7K

@

1

@

1
2
3

ACES_85204-03001

R2651

2

C907

0.01U_0402_25V7K

1

JFAN1

1
2

G1

3

G2

CONN@

12

10K_0402_5%

FAN_SPEED 1 <43>

4
5

+3VS

OPT@

+1.5V

OPT@

8

D

7

D

6

D

5

D

FDS6676AS_SO8

4.7U_0805_10V4Z

OPT@

1

2

C2570

+3VS_DGPU

R2631

470_0805_5%

1 2
3

OPT@

Q80B

4

DGPU_ PWR_EN#

5

2N7002DW-T/R7_SOT363-6

+1.5V to +VRAM_1.5VS

+VRAM_1.5VS

Q82

1

S

2

S

3

S

4

G

0.1U_0402_25V6

OPT@

1

2

C2571

Vgs =1 0V, Id =1 4.5A, Rds= 6moh m

1U_0402_6.3V4Z

OPT@

1

C2568

2

R2637

61

DGPU_PW ROK<18,53>

12

OPT@

820K_0402_5%

+VGA_CORE

R2632

OPT@

470_0805_5%

1 2
61

OPT@

Q84A
2N7002DW -T/R7_SOT363-6

2

4.7U_0805_10V4Z

OPT@

1

C2569

2

R2636 220K_0402_5%

OPT@

Q83A
2N7002DW-T/R7_SOT363-6

2

B+_BIAS

OPT@

1 2

VGA_PWROK#

R2638 100K_0402_5%

3

Q84B

5

2N7002DW-T/R7_SOT363-6

OPT@

4

5

1 2

OPT@

470_0805_5%

1 2
3

Q83B
2N7002DW-T/R7_SOT363-6

OPT@

4

OPT@

R2635

+5VALW

H7

H_4P7

H_4P2X4P7

CPU screw hole

FD1

@

1

FIDUC IAL_C40M80

FD3

@

1

FIDUC IAL_C40M80

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

FD2

@

1

FIDUC IAL_C40M80

FD4

@

1

FIDUC IAL_C40M80

H1

H_2P8

H11

H_2P8

H22

H_2P8

@

1

H_2P8

@

1

H2P8

@

1

@

1

H8

1

H2

1

H12

1

H23

H_2P8

H20

H_3P2N

@

@

1

H27

H_3P2 x4P2N

H5

H_4P2

@

1

@

1

H21

H_4P3X3P3N

1

H9

H10

H_4P2

H_4P2X4P7

@

@

@

1

1

H4

H_2P8

@

H13

H_2P8

@

@

1

@

1

H14

H15

H_2P8

H_2P8

@

@

1

H24

H_2P8

@

1

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

@

1

1

H25

H26

H_2P8

H_5P5

@

1

1

Compal Electronics, Inc.

Optimus Power/FAN/Screw Hole

H6

H_4P2

@

H28

H_6P0N

@

1

H29

H_2P0N

@

@

1

1

45 56Sun day, April 10, 2 011

1.0

A

3VALW TO +3VALW(PCH AUX Power)

+

Short J1 for PCH VCCSUS3.3

J1 need to o pen

+3VALW

1 1

10U_0603_6.3V6M

C734

1

2

20mil

B+_BIAS

R778 200K_0402_5%

12

PCH_P WR_EN#

J1

@

112

JUMP_43X79
U57
SI4800 BDY-T1-GE3_SO8

8
7

5

4

10mil

3V_GATE

3

Q95B

5

2N7002DW-T/R7_SOT363-6

4

2

+3VALW_PCH

1
2
36

10U_0603_6.3V6M

1

2

0.1U_0603_25V7K

1

C738

2

+5VALW TO +5VS

2 2

10U_0805_10V4Z

1

2

B+_BIAS

R777 100K_ 0402_5%

+5VALW

U56

SI4800 BDY-T1-GE3_SO8

8
7

10U_0805_10V4Z

5

C731

C730

1

2

12

SUSP

10mil

5VS_GATE

3

Q38B

5

2N7002DW-T/R7_SOT363-6

4

4

+5VS

1
2
36

10U_0805_10V4Z

C732

1

2

0.1U_0603_25V7K

1

C737

2

40mil

C735

1

2

1U_0603_10V4Z

Q38A

1U_0603_10V4Z

C736

1

2

Q95A

C733

B

PVT:< Memo>Fine t une + 3VALW_PCH power

R774
470_0603_5%

1 2

61

PCH_P WR_EN#

2

2N7002DW-T/R7_SOT363-6

R773
680_0603_5%

1 2

61

SUSP

2

2N7002DW-T/R7_SOT363-6

C

2N7002DW -T/R7_SOT363-6

9A on P10

Q

Q9B

PVT:R780 R772 +5VALW-->VL

VL

R772
100K_0402_5%

5

12

Q92B

1 2
3

Q90B
2N7002DW-T/R7_SOT363-6

4

+1.8VS

R798
470_0603_5%

1 2
3

2N7002DW-T/R7_SOT363-6

SUSP

5

4

SYSO N#

SYSO N<43,50> SUSP#<10,43,51>

+0.75VS

12

R793
22_0603_5%

3

4

SYS ON

R775

100K_0402_5%

SUSP SUSP

5

Q92A

D

+1.05VS

1 2
61

SUSP<5,50>

R794
470_0603_5%

2N7002DW -T/R7_SOT363-6

2

SUSP

R783

10K_0402_5%

E

VL

R780
100K_0402_5%

1 2
61

Q90A

2

12

2N7002DW -T/R7_SOT363-6

+1.5V

R799

@

470_0603_5%

1 2
13

D

SYSO N#

2

G

Q54

@

S

2N7002E-T1-GE3_SOT23-3

+1.5V to +1.5VS

+1.5V

U63

3 3

10U_0603_6.3V6M

C739

1

2

R785 200K_0402_5%

B+_BIAS

2N7002DW-T/R7_SOT363-6

4 4

+3VALW TO +3VS

+3VALW

U61
SI4800 BDY-T1-GE3_SO8

8

10U_0603_6.3V6M

7

C740

1

5

2

12

SUSP

4

10mil

3VS_GATE

3

Q79B

5

4

+3VS

1
2
36

10U_0603_6.3V6M

1

2

0.1U_0603_25V7K

C749

1

2

1U_0603_10V4Z

1

C741

C742

R781

2

330_0603_5%

1 2

61

SUSP

2

Q79A
2N7002DW-T/R7_SOT363-6

10U_0603_6.3V6M

C743

1

2

B+_BIAS

R787 750K_ 0402_1%

0.1U_0402_16V4Z

10U_0603_6.3V6M

C745

C744

1

SUSP

1

2

2

12

2

AC IN

1

2

ACIN<15 ,22,43,44,48>

SI4800 BDY-T1-GE3_SO8

8

0.1U_0402_16V4Z

7

C746

5

10mil

1.5VS_GATE

61

Q40A

2N7002DW-T/R7_SOT363-6

2

G

4

0.1U_0603_25V7K

510K_0402_5%

@

C750

1

12

R788

2

13

D

Q43

@

2N7002E-T1-GE3_SOT23-3

S

+1.5VS

1
2
36

10U_0603_6.3V6M

1U_0603_10V4Z

C747

1

2

C748

1

2

R784
470_0603_5%

1 2

3

2N7002DW-T/R7_SOT363-6

Q40B

4

+5VALW

R786
100K_0402_5%

5

PCH_P WR_EN#<20>

PCH_P WR_EN<43>

PCH_P WR_EN#SUSP

12

R789
100K_0402_5%

1 2

61

Q34A

2

2N7002DW-T/R7_SOT363-6

Q34A on P43

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/23 2011/08/25

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

DC-DC Interface

E

46 56Sun day, April 10, 2 011

1.0

5

PJP1

@

1

D D

C C

B B

1

2

2

3

3

4

4

5

6

ACE S_88290-044G

2

3

1

BATT+

PD5
PJS OT24C_SOT23-3

51ON#<4 4>

12

PD4

LL4148_ LL34-2

1 2

PR1 1

22K_040 2_1%

PC 1

100 P_0402_50V8J

12

4

SMB 3025500YA_2 P

1 2

12

PC2
1000P_0 402_50V7K

0_1206_ 5%

Pre-V

12

12

PR 10

100K_ 0402_5%

PL1

12

PR3 5

PQ4
TP0610K-T1-E3 _SOT23-3

PC 5

2

0.2 2U_0603_25 V7K

3

VINADPIN

12

PC 3

100 P_0402_50V8J

12

PC4
1000P_0 402_50V7K

VL

PR3 0

@

100K_04 02_1%

12

2

VIN

PR2 9

@

2.2M_040 2_5%

PD1

@

LL4148_ LL34-2

12

1

PR1

@

1K_1206 _5%

1 2

PR2

@

1K_1206 _5%

N3

12

1 2

PR3

@

1K_1206 _5%

1 2

12

PR4

@

511K_04 02_1%

B+

Pre-V

PU2 A

@

8

P

+

O

-

G

4

12

PR3 2

@

66.5 K_0402_1%

@

8

LM393DT _SO8

P

+

O

-

G

4

LM393DT _SO8

3

2

PU2 B

5

6

12

PC1 6

@

1000P_0 402_50V7K

12

PR7

@

150K_04 02_1%

PQ807

@

SSM 3K7002FU _SC70-3

13

D

2

G

@

S

47K_040 2_5%

13

12

PR5

@

255K_04 02_1%

12

PR6

PQ3
PDT C115EU_SOT 323-3

@

2

12

PC1 4

@

1000P_0 402_50V7K

PACIN <48>

+5VALW

13

VIN

PD3
LL4148_ LL34-2

1 2

12

PR 8

68_12 06_5%

12

PC6

0.1U _0603_25V7 K

12

PR9
68_1206 _5%

VS

PD2

@

EN0<49>

ACON<48>

2

1

3

RB7 15F_SOT323-3

6251VREF

1

12

PC1 5

@

1000P_0 402_50V7K

1 2

PR3 1

@

34K_040 2_1%

7

RTC Battery

PBJ1

- +

MAXEL_ML1220T10@

12

PR3 3

560_060 3_5%

1 2

X7999651L01

A A

5

4

PR3 4

560_060 3_5%

1 2

+RTCBATT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/23 2011/12/31

3

Compal Secret Data

Deciphered Date

2

Title

PWR-DCIN / Pre-Charge / RTC

Size Doc ument Number R ev

Cu stom

DB-806P

Da te: Sh eet o f

47 56Mo nday, Ap ril 11, 2 011

1

0.1

A

B

C

D

PQ102

1
2
36

12

PC101

0.1U_0 603_25V7K

5

13

PQ113
PDTC 115EU_SOT323-3

P2

SI4459 ADY-T1- GE3_SO8

1
2
3 6

4

12

PR104
200K_ 0402_1%

12

PR111
150K_ 0402_1%

3

PQ107B
DMN6 6D0LDW -7 2N SOT363-6

4

ADP_I<43,55>

PR124

80.6K _0402_1%

IR EF<43>

FSTCHG<43>

PQ101

VIN

1 1

12

PR101
200K_ 0402_1%

2

61

PQ107A
DMN6 6D0LDW -7 2N SOT363-6

2

2 2

PACI N

ACON<47>

ACOFF<43>

3 3

AO440 7A_SO8

8
7

5

47K

2

47K

13

PQ105
PDTC 115EU_SOT323-3

PR123

47K_0 402_5%

1 2

ACOF F

4

1 3

PQ104
PDTA1 44EU_SOT323-3

2

P3 B+

8
7

5

PC102
@560 0P_0402_25V7K

1 2

PD103

1SS35 5_SOD323-2

1 2

1 2

PR110

10K_0 402_5%

PR112

0_0402_5%

PC115

0.01U _0402_25V7K

@

12

12

PR126

100K_ 0402_1%

12

12

12

10K_0 402_1%

12

PC116
100P_ 0402_50V8J

12

PC117
.1U_0 402_16V7K

6251 VREF 6251ACLIM

PC119

0.01U_ 0402_25V7K

CHGVADJ<43>

PR102

0.015 _2512_1%

1

CSI P C SI N

2

6251VDD

12

PC106

2.2U_ 0603_6.3V 6K

ACS ETIN

12

12

PC108

.1U_04 02_16V7K

12

PR118

6800P _0402_25V7K

6251VREF

1 2

PR127

53.6K _0402_1%

12

PR129
20K_0 402_1%

15.4K _0402_1%

1 2

PL102

1.2UH _1231AS -H-1R2N =P3_2.9A_30%

VIN

PD101
RB751 V-40_SOD3 23-2

1 2

12

PR108
10_12 06_5%

D CIN

0.1U_ 0603_25V7K

ACP RN

PC112

0.047 U_0402_16V7K

1 2

PC11 4

0.1U_ 0603_25V7K

1 2

LX_CHG

DH_ CHG

BST_C HG

6251V DDP

DL_ CHG

1 2

PC109

1 2

PR136

1 2

0_0603_5%

PR125

1 2

2.2_0 603_5%

12

4

PR113

PC113

PR130

100K_ 0402_1%

3

12

PR120

100_0 402_1%

12

12

PC138

PC139

4.7U_0 805_25V6-K

4.7U_0 805_25V6-K

PU101

1

VDD

2

ACSET

6251_ EN CSON

3

EN

4

CELLS

5

ICOMP

6

VCOMP

12

7

ICM

6251 VREF

8

VREF

9

CHLIM

10

ACLIM

11

VADJ

12

GND

ISL625 1AHAZ-T_Q SOP24

12

PR131

31.6K _0402_1%

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

24

23

22

21

20

19

18

17

16

15

14

13

12

PR105
191K_ 0402_1%

ACS ETIN

12

PR109

14.3K _0402_1%

1 2

PR115

20_04 02_5%

1 2

PR116

20_04 02_5%

PR117

20_04 02_5%

1 2

PR119

2_0402_5%

BST_C HGA

12

PD105
RB751 V-40_SOD3 23-2

1 2

PR128

4.7_0 603_5%

PC125

4.7U_ 0603_6.3V6M

12

12

PC103

10U_0 805_25V6K

CSOP

CS IN

12

CSI P

PC118

1 2

0.1U_ 0603_25V7K

6251 VDD

12

PC104

PC105

10U_0 805_25V6K

12

PC107
1000P _0402_50V7K

CHG_B+

4.7U_0 805_25V6-K

6

578

4

6

578

4

PQ110

AO446 6L_SO8

123

PQ112

AO446 6L_SO8

123

B+

PQ103

AO440 7A_SO8

1
2
3 6

4

PR103

200K_ 0402_1%

12

PR106
47K_0 402_1%

13

PQ106
PDTC 115EU_SOT323-3

PR114

@

100K_ 0402_1%

BATT_ON

1 2

PL101

10UH_ SIL104R- 100PF_4. 4A_30%

1 2

12

PR122

4.7_1 206_5%

12

PC123
680P_ 0402_50V7K

8
7

5

2

C HG

CSOP

CS ON

12

VIN

1 2

PD102
1SS35 5_SOD323-2

1 2

PD104

1SS35 5_SOD323-2

TC R=5 0p pm / C

1

2

PR121

0.02_ 1206_1%

200K_ 0402_1%

12

4

3

PR107

PC111

12

13

D

S

0.1U_0 603_25V7K

ACO FF

VIN

PAC IN

2

PQ109

G

SSM3 K7002FU_SC 70-3

12

12

PC120

10U_0 805_25V6K

BATT+

PC121

10U_0 805_25V6K

6251VDD

12

12

PR132
47K_0 402_1%

ACP RN

4 4

A

PR133
10K_0 402_1%

13

PQ114
PDTC 115EU_SOT323-3

2

B

1 2

PR134

10K_0 402_1%

PAC IN

12

PR135

14.3K _0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ACIN <15,22, 43,44,46>

PACIN <47>

2009/08/23 2011/12/31

Compal Secret Data

B+

12

PC126

2200P _0402_50V7K

Deciphered Date

C

For RF team

12

PC128

PC127

0.1U_0 402_25V6

68P_0 402_50V8J

12

12

PC129

PC130

2200P _0402_50V7K

12

12

PC131

0.1U_0 402_25V6

PC132

68P_0 402_50V8J

Title

PWR-CHARGER

Size D ocum ent Nu mber R ev

Cus tom

DB-806P

Dat e: Sheet o f

12

12

PC134

PC133

0.1U_0 402_25V6

2200P _0402_50V7K

Compal Electronics, Inc.

12

12

PC135

68P_0 402_50V8J

2200P _0402_50V7K

D

12

12

PC136

PC137

0.1U_0 402_25V6

68P_0 402_50V8J

48 56M onday, Apr il 11, 2 011

0.1

5

4

3

2

1

2VREF_51125

12

PC3 01

D D

PR3 01

13K_040 2_1%

1 2

PR3 03

20K_040 2_1%

B+

12

C C

PL304

1 2

1.2U H_123 1AS-H-1 R2N=P3_2 .9A_30%

PC3 02

@

680P_04 02_50V7K

+3VALWP

1

+

PC3 13
220 U_6.3V_M

2

PJP301

2

+3VALWP +3VALW +5VALWP +5VALW

B B

3.3VALWP

112

JUMP_43 X118

PL301

1 2

HCB 2012KF-121 T50_0805

1 2

4.7U H_PCM C063T- 4R7MN_5.5A_2 0%

TPS51125_B+

12

PC3 03

4.7 U_0805_25V 6-K

SIS41 2DN-T 1-GE3_POW ERPAK8-5

PL302

Typ: 175 mA

+3VLP

12

12

PC3 05

PC3 04

0.1 U_0603_25V 7K

PQ301

12

PR3 09

4.7 _1206_5%

3V_ SNB

12

PC3 15

680P_ 0402_50V7K

5

2200P _0402_50V7K

4

123

5

PQ303

123

SI771 6ADN- T1-GE3_POW ERPAK8-5

0.1U _0603_25V7 K

4

TPS51 125_B+

PC3 11

1 2

EN0<47>

12

PC3 07

4.7 U_0805_10V 6K

499K_04 02_1%

1 2

PR3 07

0_0603_ 5%

PR3 11

1 2

TDC A
Peak Current A
OCP current A

ENT RIP1

3

PQ305B
DMN 66D0LD W-7 2 N SOT363-6

5

4

ENT RIP2

61

PQ305A
DMN 66D0LD W-7 2 N SOT363-6

2

1 2

PR3 05

110K_04 02_1%

1 2

PU3 01

25

7

8

3V_BST

9

3V _DH

10

3V_LX

11

3V_ DL

12

MAINP WON

12

12

PC3 17

PR3 13

100K_ 0402_1%

2VREF_51125

P PAD

VO2

VREG3

BOOT2

UGATE2

PHASE2

LGATE2

1U_ 0603_10V6K

1U_ 0603_10V6K

ENT RIP2

6

4

5

FB2

TONSEL

ENTRIP2

VFB=2.0V

SKIPSEL

EN

14

15

13

1

2

3

FB1

REF

ENTRIP1

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

NC18VREG5

VIN16GND

17

12

PC3 18

4.7U _0805_10V6 K

12

PC3 19

0.1U _0603_25V7 K

PR3 02

30K_040 2_1%

1 2

PR3 04

20K_040 2_1%

1 2

PR3 06

130K_04 02_1%

ENT RIP1

1 2

24

VO1

23

5V_BST

22

5V _DH

21

5V_LX

20

5V_ DL

19

RT8205E GQW_W QFN24_4X4

Typ: 175mA

VL

TPS51125_B+

5V_BST_ 13V_BST_ 1

1 2

PR3 08

0_0603_ 5%

0.1U _0603_25V7 K

SI771 6ADN- T1-GE3_POW ERPAK8-5

SPOK <1 5,55>

PC3 12

1 2

TPS51125_B+

12

PL303

12

PC3 10

PC3 09

0.1 U_0603_25V 7K
2200P _0402_50V7K

+5VALWP

1

+

PC3 14
220 U_6.3V_M

2

12

PC3 06

5

PQ302

4

SIS41 2DN-T 1-GE3_POW ERPAK8-5

123

5

PQ304

4

123

10U _0805_25V6K

1 2

4.7U H_PCM C063T- 4R7MN_5.5A_2 0%

12

PR3 10

4.7_ 1206_5%

5V_ SNB

12

PC3 16
680P_04 02_50V7K

PJP302

2

112

JUMP_43 X118

5VALWP
TDC A
Peak Current A
OCP current A

VL

VS_ON<55>

VS

A A

5

1 2

100K_04 02_1%

1 2

1 2

PR3 18

100K_04 02_1%

PR3 16

PR3 17

0_0402_ 5%

12

13

PQ306
PDT C115EU_SOT 323-3

2

12

PR3 19

40. 2K_0402_1%

PC3 20

2.2 U_0603_16V 5K

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/23 2011/12/31

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR-3VALWP/5VALWP

Size Doc ument Number R ev

Cu stom

DB-806P

Da te: Sh eet o f

49 56Mo nday, Ap ril 11, 2 011

1

0.1

A

B

C

D

1.5_5 1117_B+

1 1

PR401

0_0402_5%

SYSON<43,46>

+5VALW

2 2

3 3

1 2

1 2

PR406

316_0 402_1%

12

PC401

@

.1U_0 402_16V7K

12

PC412

1U_06 03_10V6K

PC415

@

1 2

47P_0 402_50V8J

1 2

PR408

10K_0 402_1%

12

PR409
10K_0 402_1%

+1.5V_CPU_VDDQ

2

2

1

1

SUSP<5,46>

1 2

PR411

100K_ 0402_1%

1.5V_ TON

1.5V_ VOUT

1. 5V_VDD

1.5V_ FB

PJP4 06
JUMP_43X118

12

PC420
1U_04 02_16V6K

2

3

4

5

6

PU401

TON

VOUT

VDD

FB

PGOOD

+1.5V

2

G

1

VFB=0.75V

2

2

1

1

PC416

4.7U_ 0805_6.3V 6K

1 2

13

D

S

PQ403
SSM3 K7002F_SC59-3

1 2

267K_ 0402_1%

BST_1.5V

15

14

NC

BOOT

UGATE

EN/DEM

PHASE

VDDP

LGATE

GND7PGND

RT820 9BGQW_W QFN14_3P5X3P5

8

PJP4 05
JUMP_43X118

PR402

CS

12

12

1 2

PR403

0_0603_5%

1. 5V_DH

13

1.5V_LX

12

1.5V_ CS

11

1.5 V_VDDP

10

1.5V_ DL

9

PR410

1K_04 02_1%

PR412
1K_04 02_1%

12

BST_1.5V- 1

1 2

14K_0 402_1%

PR413

1K_04 02_1%

PC407

1 2

0.1U_ 0603_25V7K

PR405

12

PC418

.1U_04 02_16V7K

+5VALW

12

0. 75V_VIN

0.7 5V_VREF

PC413

4.7U_ 0805_10V6K

PU402

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL53 36KAC-TRL_SO8

+0.75VSP

12

PC419
10U_0 603_6.3V6M

4

NC

NC

NC

TP

678

35241

786

5

123

0.75V _VCNTL

6

5

7

8

9

PQ401
SI4128 DY-T1-G E3_SO8

12

PR404

PQ402

4.7_1 206_5%

1.5V _SNB

12

FDS66 90AS-G_SO8

PC414
680P_ 0402_50V7K

12

12

12

PC402

PC403

4.7U_0 805_25V6-K

4.7U_0 805_25V6-K

PL401

1UH_P CMC063T -1R0MN_11A_20%

1 2

+3VALW

PC417
1U_06 03_10V6K

12

PC404

0.1U_0 603_25V7K

+0.75VSP

PJP4 01

2

JUMP_43X118

12

PC405
2200P _0402_50V7K

12

112

12

PC408

PC411

@

@

.1U_04 02_16V7K

10U_0 805_6.3V6M

B+

12

@

PC406

680P_ 0402_50V7K

1

+

PC409

2

220U _D2_2VY_ R15M

1.5VP
TDC 10 A
Peak Current 13 A
OCP current 16.9 A

PJP4 04

2

112

JUMP_43X118

+0.75VS

+0.75VSP
Thermal Desi gn Current:0.7A
Peak current :1A
Vout=VDDQSNS /2=1.5V/2=0.75V

+1.5VP

PJP4 02

112

JUMP_43X118

PJP4 03

112

JUMP_43X118

2

+1.5V+1.5VP

2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/23 2011/12/31

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

PWR-1.5VP/0.75VSP

Size D ocum ent Nu mber R ev

Cus tom

Dat e: Sheet o f

D

50 56Su nday, A pril 10, 2011

0.1

5

4

3

2

1

VCC P_51117_B+

1 2

PR5 02

267K_04 02_1%

D D

SUSP#< 10,43,46>

+5VALW

C C

1 2

PR5 01

20K_040 2_1%

PR5 04

316_040 2_1%

1 2

12

PC5 01

1U_ 0402_16V6K

VCC P_VOUT-1

12

PC5 08

1U_ 0603_10V6K

PR5 19

0_0402_ 5%

12

PR5 10

10K_040 2_1%

VCC P_TON

VCC P_VOUT

12

VC CP_VD D

VC CP_FB

VC CP_PGD

2

3

4

5

6

+3VS

12

PR5 12
10K_040 2_1%

PU5 01

TON

VOUT

VDD

FB

PGOOD

1

VFB=0.75V

VCC P_BST

14NC15

BOOT

EN/DEM

UGATE

PHASE

VDDP

LGATE

GND7PGND

RT8209B GQW_W QFN14_3P5X3P 5

8

VTTPW RGOOD <52>

CS

1 2

PR5 03

0_0603_ 5%

VC CP_D H

13

VCCP_LX

12

VC CP_CS

11

VC CP_VD DP

10

VC CP_DL

9

VCC P_BST_1

0.1U _0603_25V7 K

1 2

PR5 05

6.98 K_0402_1%

PC5 05

1 2

+5VALW

12

PC5 09

4.7U _0805_10V6 K

PQ501

4

4

5

5

213

12

PC5 02

TPC A8065-H_PP AK56-8-5

123

PQ502

1UH _PCMC0 63T-1R0MN_ 11A_20%

12

VC CP_SN B

12

TPC A8059- H_SOP-AD VANCE8-5

12

PC5 03

10U _0805_25V6K

4.7 U_0805_25V 6-K

PL501

1 2

PR5 06

4.7_ 1206_5%

PC5 13
680P_04 02_50V7K

PR5 08

4.02 K_0402_1%

12

12

PC5 07

PC5 06

4.7 U_0805_25V 6-K

0.1 U_0603_25V 7K

12

PC5 21

0.1 U_0402_10V 7K

VCC P_VOUT-1

12

Clos e to PU50 1.7

PJP501

2

JUMP_43 X118

12

PC5 04
2200P_0 402_50V7K

1

+

PC5 10

2

PR5 11

100_040 2_1%

PR5 13

0_0402_ 5%

112

B+

+1.05VS

+1.05VS
Peak Current 16.2 A
OCP current 21A

150 U_B2_1.5VM _R15M

12

VCC IO_SENSE <8>

12

VSS_S ENSE_VCC IO <8>

B B

A A

5

SUSP#< 10,43,46>

PJP505

112

JUMP_43 X79

2

12

PC5 14
10U _0805_10V6K

12

1 2

PR5 15

510K_04 02_1%

1. 8V_VIN

PC5 15
10U _0805_10V6K

12

PR5 16

@

1M_0402 _5%

4

PU5 02

10

9

8

1.8V _EN

5

12

PC5 19

0.47 U_0402 _6.3V6K

4

2

LX

PVIN

PG

3

LX

PVIN

SVIN

EN

6

FB

TP

NC

NC

7

1

11

SY803 3BDBC _DFN10 _3X3

1.8V_LX

1.8V _FB

1UH _PCMC0 63T-1R0MN_ 11A_20%

12

PR5 14

4.7_ 1206_5%

1.8 V_SNB

PC5 18
680P_06 03_50V7K

1 2

12

PR5 18

14.3 K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PL502

1 2

12

PC5 16
22U _0805_6.3VAM

1 2

PR5 17

28.7 K_0402_1%

PC5 20

@

12

22P_040 2_50V8J

2009/08/23 2011/12/31

3

Compal Secret Data

Deciphered Date

12

PC5 17
22U _0805_6.3VAM

2

PJP506

2

112

JUMP_43 X79

+1.8VS+1.8VSP+1.8VSP+5VALW

1.8VSP
TDC 2 A
Peak Current 3 A

Compal Electronics, Inc.

Title

PWR-VCCPP/1.8VSP

Size Doc ument Number R ev

Cu stom

DB-806P

Da te: Sh eet o f

51 56Mo nday, Ap ril 11, 2 011

1

0.1

5

D D

4

3

2

1

+3VS

12

PR7 04
10K _0402_5 %

1 2

PR7 03

0_0 402_5%

PJP 701
JUMP _43X79

+5VALW

C C

VTTPWRGOOD<51>

112

2

12

PC7 02
10U _0805 _10V6K

1 2

PR7 01

0_0 402_5%

12

PC7 03
10U _0805_ 10V6K

12

@

1M_0 402_5%

PR7 02

VC CSA _VIN

VC CSA _EN

PC7 01

@

12

0.4 7U_0 402_6. 3V6K

+3VS

12

PR7 16
10K _0402_ 5%

PR7 12

10K _0402_5 %

PR7 13

10K _0402_ 5%

VCCSA_VID1<9>

1 2

12

PR7 18
10K _0402_ 5%

1

2

PQ7 04

3

PMBT2 222A_SOT 23-3

1 2

12

PR7 17
100 K_0402 _5%

12

10

9

8

5

2

G

PC7 14

@

.1U _040 2_16V7K

4

PVIN

PVIN

SVIN

EN

TP

11

12

PR7 09

21. 5K_040 2_1%

13

D

PQ7 03

S

SSM 3K700 2F_SC59 -3

VCCSA_LX

2

LX

PG

3

LX

VC CSA _FB

6

FB

PU7 01

SS

LX

SY8 035D BC_D FN10 _3X3

7

1

PC7 04

@

12

0.4 7U_0 402_6.3 V6K

Need to check
for <1.8 ms SS t ime

SA_ PGOOD < 43>

12

PR7 11

10. 2K_040 2_1%

PL7 01

1UH _PCM C06 3T-1R0 MN_11A_ 20%

1 2

12

PR7 06

4.7 _1206_5 %

VCC SA_S NB

12

PC7 13
680 P_0603 _50V7K

PR7 08

12

3.4 8K_040 2_1%

PC7 12

@

12

22P _0402_ 50V8J

PJP 702

+VCC SAP

12

PC7 08
22U _0805_ 6.3VAM

12

PC7 15

0.1 U_04 02_10V7 K

PR7 15

1 2

100 _0402_1 %

12

PC7 09
22U _0805_ 6.3VAM

+VC CSAP

VCCSA_SENSE <9>

+VC CSAP
TDC 4. 8A
Pea k Cur rent 6A

112

JUM P_43X118

2

+VCC SA

V ID [1] VCCS A Vou t Requ ired Req uire on 2012

B B

A A

0 0 .9V Yes Yes
1 0 .8V Yes Yes

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/23 2011/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR-VCCSAP

Size Doc ume nt N umber R ev

C

DB-806P

Dat e: Shee t

1

52 56Mon day, Apr il 11, 2011

o f

0.1

5

4

3

2

1

PL801

1

1

PC810

PC809

0.1U_0 402_10V7K

PR810

2

2

10U_0 805_6.3V6M

12

+VGA_COREP

12

B+

1

+

PC811

PC813

2

10U_0 805_6.3V6M

+VGASENSE <23>

1

2

330U _2VYD2_ R7M

PJP8 02

JUMP_43X118

PJP8 03

JUMP_43X118

PJP8 04

JUMP_43X118

+

112

112

112

PC812

330U _2VYD2_ R7M

2

2

2

VGA_COR EP
TDC :TBC A
Peak Current :21.56 A
OCP current :TDB A

+VGA_COREP

+VGA_CORE

PQ801

4

4

+VGA_B+

5

TPCA8 065-H_PPAK56-8- 5

123

PQ802

123 5

TPCA8 057-H_SO P-ADVANC E8-5

12

PC802

10U_0 805_25V6K

0.36U H_FDU10 40D-R36 M-P3_26A_20%

12

PR806

4.7_1 206_5%

VGA_S NB

12

PC815
680P_ 0603_50V7K

PL802

1 2

PR807

2.37K _0402_1%

12

12

PC803

10U_0 805_25V6K

D D

+3VS

12

PR820
10K_0 402_5%

+3VS

DGPU _PWROK <18,45>

PR819

PR801

@

10K_0 402_5%

PR804

1 2

12

PC801

@

.1U_0 402_16V7K

DGPU _PWR_EN<17,45>

C C

1 2

0_0402_5%

0_0402_5%

1 2

PR803

78.7K _0402_1%

VGA_P GD

12

VGA_T RIP

VGA_E N VGA_LX

VGA_F B

VGA _RF

12

PR805
470K_ 0402_5%

PU801

1

VBST

PGOOD

2

TRIP

DRVH

3

EN

4

5

SW

V5IN

VFB

DRVL

RF

TPS51 212DSCR _SON10_3X3

TP

10

9

8

7

6

11

VFB= 0.7V

12

PR80 9

12.7K _0402_1%

12

PR811
75K_0 402_1%

VGA_BST

VGA _DH

VGA_D L

PR802

2.2_0 603_5%

1 2

VGA_BST_1

+5VALW

1

PC814
1U_06 03_6.3V6M

2

PC808

1 2

0.22U _0603_25V7K

12

PC806

0.1U_0 603_25V7K

12

PC818

HCB45 32KF-80 0T90_1812

12

PC807
2200P _0402_50V7K

12

0.1U_0 402_10V7K

100_0 402_1%

+3VS

12

PR812
10K_0 402_5%

GPU_VID 1<22>

B B

1 2

PR813

4.7K_ 0402_5%

12

PR814

100K_ 0402_5%

@

+3VS

12

PR816
10K_0 402_5%

GPU_VID 0<22>

A A

1 2

PR817

10K_0 402_5%

12

PR818

100K_ 0402_5%

@

GVI D1-2

13

D

2

G

PQ806

S

PC816

0.01UF _0402_25 V7K

2

G

PC817

0.01UF _0402_25 V7K

SSM3 K7002FU_SC 70-3

12

PR815
11K_0 402_1%

GVI D0-2

13

D

PQ805

S

SSM3 K7002FU_SC 70-3

12

12

GP IO5 GP I O6

GP U_ VID 0 GPU_ VI D1

1

1

1

0

00

N1 2P -GV

Co re Vo lt age Le vel

1.02 5V

1.00 0V

0.85 0V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/23 2011/12/31

3

Compal Secret Data

Deciphered Date

Title

PWR-VGA_CORE

Size D ocum ent Nu mber R ev

Cus tom

DB-806P

2

Dat e: Sheet o f

53 56M onday, Apr il 11, 2 011

1

0.1

5

PR2 09

D D

GFX VR_IM ON

VSS_A XG_SENS E

@

499K _0402_1 %

12

PR 216

22.6 K_040 2_1%

Parall el and tune length

VR_SVID_DAT<8>

VR_SVI D_ALRT#<8>

VSS SENSE

@

499_ 0402_1%

@

499K _0402_1 %

VR_ SVID_CLK<8>

12

PR2 27

1 2

PR 228

PR 240

1 2

12

33.2 K_040 2_1%

+3VS

PC2 27

0.03 3U_06 03_16V7K

12

PC 229
47P _0402_5 0V8J

12

PR2 35

8.06 K_040 2_1%

10P _0402_5 0V8J

PC2 44

12

150P _0402_ 50V8J

PC2 59

@

12

100P _0402_ 50V8J

Alert# PU resister need close CPU,
so the PU resister in HW schematic.
but DAT and CLK need close PWM-IC,
so the PU resister in POWER schematic.

C C

IMVP_IMON<43>

VR_HOT#<43>

+1.05VS

B B

PC2 60

@

100P _0402_ 50V8J

PC2 12

150P _0402_ 50V8J

12

12

PR2 02

8.06 K_040 2_1%

+1.05VS

12

PC 215

0.04 7U_06 03_16V7K

PC2 17

1 2

@

1 2

PR2 26

1.91 K_040 2_1%

VGATE <15>

3.83 K_040 2_1%

12

PC 234
1000 P_0402_ 50V7K

PC2 40

12

PR 244

412K _0402_1 %

PR 256

@

2K_ 0402_1%

12

@

2K_ 0402_1%

PC2 08

68P _0402_5 0V8J

12

12

475K _0402_1 %

12

PR2 18

130_ 0402_1%

.1U_ 0402_ 16V7K

GFX _CORE_PWRGD<43>

VR_ON<43>

470K +-5 % ER TJ0EV47 4J 0402

12

PR 229

PR2 42

499_ 0402_1%

12

3.01 K_04 02_1%

12

VC CSEN SE<8>

VSS SENSE<8>

PR 257

PR2 11

12

PR2 19

54.9 _0402_1 %

1 2

27.4 K_040 2_1%

12

PR2 45

12

PR2 08

422_ 0402_1%

12

12

PC2 01
1000 P_0402_ 50V7K

+3VS

12

SVI D_SD A

SVI D_AL ERT#

SVI D_SC LK

PR 225

0_04 02_5%

PH 203

12

12

PR 230

PC 242

12

470P _0402_50V 7K

12

12

PR 220

1.91 K_040 2_1%

PR2 12

2.87 K_040 2_1%

VSU M-

*Iccma x in T urbo M ode fo r SV (35W) is 53A

+CPU_CORE

A A

Icc-max=53A
Rdson=3.6~4.5m ohm
DCR=1.1m ohm
HW output cap:
(1)10U_0805_4V *10
(2)22U_0805_6.3V *15
(3)470U_D2_2V *4(ESR=4.5m ohm)

+VGFX_COREP

Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A
Rdson=3.6~4.5m ohm
DCR=1.1m ohm
HW output cap:
(1)22U_0805_6.3V *12
(2)470U_D2_2V *2(ESR=4.5m ohm)

*OCP s etting value =71.5A *OCP s etting value =37A

5

4

PR2 01

@

PC2 10

680P _0402_5 0V7K

12

1

2

3

4

5

6

7

8

9

10

11

12

22P _0402_5 0V8J

3.83 K_04 02_1%

12

46

48

47

49

FBG

GND

VWG

IMONG

PGOODG

SDA

ALERT#

SCLK

VR_ON

PGOOD

IMON

VR_HOT#

NTC

VW

PC2 36

0.22 U_040 2_6.3V6 K

0.22 U_040 2_6.3V6 K

330P _0402_5 0V7K

1000 P_0402_50 V7K

VSENG

COMPG

ISL 95831 CRZ-T_ TQFN48_6X 6

COMP13FB14ISEN3/ FB215ISEN216ISEN117VSEN18RTN19ISUMN20ISUMP21VDD22VIN23PROG1

IS EN2

IS EN1

12

PC2 37

12

PC2 43

12

PC2 47

12

PC2 51

12

4

12

12

PC2 09

ISP G

44

45

RTNG

12

PC2 48

330P _0402_50V 7K

330P _0402_5 0V7K

1000 P_0402_ 50V7K

IS NG

43

ISPG

ISNG

330P _0402_5 0V7K

PH 201

@

470K +-5 % ER TJ0EV47 4J 0402

PC 206

1 2

PC 211

NT CG

42

NTCG

1.5K _0402 _1%

1 2

PR 203

@

27.4 K_040 2_1%

12

PR2 17

16.5 K_040 2_1%

1 2

BOOTG

40

41

PROG2

BOOTG

12

PR2 48

PHA SEG

UGA TEG

39

UGG

PC 238

1U_0 603_10V 6K

12

12

12

10_0 402_1%

PR 213

10_0 402_1%

LGATE G

37

38

LGG

PHG

BOOT2

UG2

PH2

VSSP2

LG2

VDDP

PWM3

LG1

VSSP1

PH1

UG1

BOOT1

24

12

PC 239

0.22 U_060 3_25V7K

PC 245

0.33 U_060 3_10V7K

NT CGNT CG

+VGFX_CORE

12

PR 204

VCC_AXG_SENSE <9>

VSS_AXG_SENSE <9>

12

BOOT2

36

UGA TE2

35

PHA SE2

34

33

LGATE 2

32

31

30

LGATE 1

29

28

PHA SE1

27

UGA TE1

26

BOOT1

25

PU2 01

12

CPU _B+

PR2 31

0_06 03_5%

12

+5VS

PR2 37

1_06 03_5%

12

12

PC 246

@

0.02 2U_04 02_16V7K

3

PQ20 1

UGA TEG

PHA SEG

BOOTG

LGATE G

1 2

PR2 05

2.2_ 0603_5%

0_06 03_5%

BOO TG_1

PR2 58

12

PC2 07

1 2

0.22 U_060 3_10V7K

4

4

+5VALW

12

PR 221

@

0_04 02_5%

IS NG

1 2

PR2 24

0_06 03_5%

12

12

PC 226

PC 225

2.2U _0603 _10V6K

2.2U _0603 _10V6K

12

PR2 32

7.87 K_040 2_1%

VSU M+

12

PR2 43

2.61 K_040 2_1%

12

PR 247

11K _0402_1%

PH2 04

VSU M-

10K B_060 3_5%_ ERTJ1VR 103J

12

PC 249
.1U_ 0402_ 16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VG FX_CORE

12

12

12

PC2 20

PC2 19

PC2 21

12P _0402_5 0V8J

12P _0402_5 0V8J

12P _0402_5 0V8J

@

@

@

+5VS

PQ20 3

UGA TE2

PHA SE2

BOOT2

LGATE 2

UGA TE1

PHA SE1

BOOT1

LGATE 1

2.2_ 0603_5%

2.2_ 0603_5%

PR2 59

12

PC2 35

12

0.22 U_060 3_10V7K

PQ20 5

PR 260

12

PC 257

12

Compal Secret Data

4

4

4

4

0_06 03_5%

PR 236

12

0_06 03_5%

PR 250

12

0.22 U_060 3_10V7K

2009/08/23 2011/12/31

CPU _B+

5

TPC A8065-H _PPAK56- 8-5

123

PQ2 02

123 5

12

12

PC2 24

PC2 22

PC2 23

12P _0402_5 0V8J

12P _0402_5 0V8J

@

@

@

CPU _B+

5

TPC A8065-H _PPAK56- 8-5

123

5

PQ20 4
TPC A8059 -H_S OP-ADVA NCE8-5

213

5

TPC A8065-H _PPAK56- 8-5

123

5

PQ20 6
TPC A8059 -H_S OP-ADVA NCE8-5

213

Deciphered Date

2

12

12

PC2 02

TPC A8057 -H_S OP-ADV ANCE8-5

12

12P _0402_5 0V8J

CPU _B+

12

PC2 50

10U_ 0805_ 25V6K

2

12

12

PC2 05

PC2 03

10U_ 0805_25 V6K

10U_ 0805_25 V6K

12

PC2 30

10U_ 0805_25 V6K

12

PC2 52

10U_ 0805_ 25V6K

2200 P_0402_50 V7K

PC2 04

0.1U _0603 _25V7K

0.36 UH_E TQP4 LR36W HC_24 A_20%

4

12

PR 206

4.7_ 1206_5%

GFX _SNB

12

PC 214

680P _0402_50V 7K

ISP G

IS NG

12

PC2 31

12

PC2 53

12

12

PC2 33

PC2 32

10U_ 0805_25 V6K

10U_ 0805_25 V6K

12

IS EN2

PR2 38

4.7_ 1206_5%

VSU M+

CP U_S NB1CP U_S NB2

12

10U_ 0805_ 25V6K

12

PR2 53

12

3.65 K_060 3_1%

PC2 41

VSU M-

680P _0402_5 0V7K

12

12

PC2 54

PC2 61

0.1U _0603 _25V7K

IS EN1

10K _0603_1%

4.7_ 1206_5%

VSU M+

3.65 K_060 3_1%

PC2 58

VSU M-

1_04 02_5%

680P _0402_50V 7K

Title

Size D ocum ent N umber R ev

Cu stom

Da te: She et of

3

12

PR2 10
10K _0402_1%

PR2 14

7.5K _0402 _1%

1 2

10K _0402 _5%_TSM0 A103J4302RE

1 2

11K _0402_1%

.1U_ 0402_ 16V7K

@

0.01 U_040 2_16V7K

0_04 02_5%

12

PC2 64
2200 P_0402_ 50V7K

0.1U _0603 _25V7K

0.36 UH_E TQP4 LR36W HC_24 A_20%

4

12

3

PR 233

10K _0603_1%

12

PR 239

12

PR 241

1_04 02_5%

1

2200 P_0402_ 50V7K

PR 251

PR 254

PR 255

2

PL204

0.36 UH_E TQP4 LR36W HC_24 A_20%

4

12

3

12

12

PWR-CPU_CORE/GFX_CORE

DB-806P

PL201

PH 202

1 2

PR2 15

1 2

PC2 16

1 2

PC2 18

PR2 23

PL202

+

PC2 55

100U _25V_M

1

1

+VGFX_CORE

2

12

PR 207
1_04 02_5%

12

PR 222

12

1

2

549_ 0402_1%

1

+CPU_CORE

2

PR2 34

10K _0402_1%

PL203

HCB 4532K F-800 T90_1812

1

+

PC 256
100U _25V_M

2

+CPU_CORE

IS EN2

12

PR 252

10K _0402_1%

1

12

PC2 13
.1U_ 0402_ 16V7K

IS EN1

12

12

12

54 5 6Mond ay, A pril 11, 2011

B+

12

PC2 68

PC2 67

10U_ 0805_ 25V6K

10U_ 0805_ 25V6K

0. 1

5

4

3

2

1

BATT++

D D

12

PC8
1000P_0402_50V7K

PJPB1 battery connector

PJP2

@

SUYIN_2 00275MR008G15QZR

C C

B B

SPOK<15,49>

10

GND

9

GND

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

+5VALWP

PR26
100K_0402_1%

1 2

1 2

0_0402_5%

PR27

2

3

PD6
PJSOT24C_SOT23-3

1

12

PR24

1 2

PR25

22K_0402_1%

13

D

PQ7

2

G

SSM3K7002FU_SC70-3

S

12

PC13

@

.1U_0402_16V7K

PL2

HCB2012KF-121T50_0805

1 2

PL3

HCB2012KF-121T50_0805

1 2

PR13

@

1 2

100K_0402_1%

12

PR14
1K_0402_1%

PR17

1 2

6.49K_0402_1%

Pla ce cl so e to EC pin

BATT_TEMP

1 2

PR18

1K_0402_5%

1 2

PR19

100_0402_5%

1 2

PR22

100_0402_5%

PQ6
TP0610K-T1-E3_SOT23-3

12

PC11

@

100K_0402_1%

2

0.22U_0805_16V7K

+3VALW

+3VALW

PC10
.1U_0402_16V7K

1 2

13

BATT+

BATT+

12

PC7

0.01U_0402_25V7K

BATT_TEMP <43>

EC_SMB_CK1 <43>

EC_SMB_DA1 <43>

12

PC12

@

0.1U_0603_25V7K

VL

12

PC9

0.1U_0603_25V7K

VL

PR15

@

100K_0402_1%

+3VS

1 2

PR28

100K_0402_1%

PQ5

@

13

D

SSM3K7002FU_SC70-3

2

G

S

VS_ON<49>

H_PROCH OT#<5,43>

B+_BIASB+

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

12

PR12
21K_0402_1%

12

PH1
100K_ 0402_1%_NCP15WF104F03RC

12

PR21

@

10K_0402_1%

12

PR23

@

10K_0402_1%

12

PU1

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

8

7

6

5

1 2

PR16

9.53K_0402_1%

PR20

@

47K_0402_1%

12

ADP_I <43,48>

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/23 2011/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-BATTERY CONN

Size Doc ument Number Re v

Cus tom

DB-806P

2

Date: Sheet of

1

55 56Monday , April 11, 2011

0.1

5

D D

+INVPWR_B+

12

12

PC901

0.1U_0603_ 25V7K

C C

DISP OFF#<34 >

B B

@RB751V-40_SOD323-2

INVTPWM<34>

A A

10K_0402_1%

PR905

1 2

PD902

1 2

PC902

2.2U_0805_ 25V6K

@

12

PC911

1000P_0402_50V7K

PR906

60.4K_0402_1%

1 2

1 2

PR909
@1.1K_0402_1%

4

PAD-O PEN 2x2m~D

P5103EMG_SOT23-3

12

PR908
@0_0402_5%

1 2

PR907
@100K_0402_1%

1 2

PJP901

2 1

PQ901

@

D

S

13

G

2

PC912

2.2U_0805_ 25V6K

12

PC913
.001U_0402_50V7-M

1U_0603_25V6K

+INVPW R_B+

+3VS

5

P

2

I

G

3

3

4.7UH _PCMC063T-4R7MN_5.5A_20%
PL901

1 2

PC910

12

1

REGOUT

2

EN

3

PGATE

4

VIN

5

MONITOR

6

PGND1

7

NC

4

O

1

NC

PU902
TC7SZ17F_SOT23-5

SW

2 1

PD901

12

B160-13-F_SMA2

PR901

10_1206_1%

12

PC907

220P_0603_50V8J

24

23

29

PU901

TB62758FTG_VQON24_3P8X3P8

SW8VOUT10PGND2

SW

25

TP

GND26GND27GND28GND

AGND

NC9NC11OUT1

12

+LG_VOUT

13

+INVPWR _B+

FSET

14

+INVPWR _B+

22

COMP
ISET

PGND3

PWM

OUT6

OUT5

OUT4

OUT3

OUT2

91K_0402_1%
PR902

1 2

510_0402_1%

PR903

1 2

21

20

19

18

17

16

15

2

0.1U_0603_ 50V7K
PC908

1 2

0.001U_0402_50V7M~D
PC909

@

1 2

11K_0402_1%

PR904

1 2

12

PC914
@0.015U_0402_16V7K

1

+LG_VOUT

12

12

PC903

12

12

PC904

PC905

PC906

2.2U_1206_ 50V7K

2.2U_1206_ 50V7K

0.1U_0603_ 50V7K

0.1U_0805_ 50V7K

FB4 <34>

FB3 <34>

FB2 <34>

FB1 <34>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/23 2011/12/31

3

Compal Secret Data

Deciphered Date

Title

PWR-LED Converter

Size Docum ent Number R ev

B

DB-806P

2

Dat e: S heet o f

56 56Sunda y, April 10, 2011

1

0.1