Compal LA-7391P PBL22 Schematic

A
1 1
2 2
B
C
D
E
Compal Confidential
PBL22 MB Schematic Document
LA-7391P
3 3
Rev: 0.2
2011.04.07
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-7391P
LA-7391P
LA-7391P
E
0.2
0.2
0.2
of
of
of
164Thursday, April 07, 2011
164Thursday, April 07, 2011
164Thursday, April 07, 2011
A
B
C
D
E
Compal Confidential
Project Code : PBL22
Chief River
CPU XDP Conn.
P.5
File Name : LA-7391P
P.38
P.51
E
PCH XDP Conn.
USB board
Port 0
Audio board
Audio board
Audio board
of
of
of
264Thursday, April 07, 2011
264Thursday, April 07, 2011
264Thursday, April 07, 2011
P.15
0.2
0.2
0.2
Fan Control
1 1
PEG x16 (DIS) GEN 1/2/3
N12P-GE 64*16 1GB
P.24-35
LVDS Conn.
P.38 P.44 P.37
2 2
eDP Conn.
CRT Conn.HDMI Conn.
P.36
OPTIMUS/UMA
SW
DP Conn.
IO board
Port 5-8
Light Peak
P.52-53
3 3
P.54
CIO
7 in 1 card
Port 2
Express Card
IO board
Port 4
Mini Card-1 WLAN (Half) +Blue Tooth combo
USB2.0 port 10
Port 3
P.51
Reader
IO board
Mini Card-1 WWAN (full) Reserved for
Sub-board
IO board (LS-7391P)
IO Board to Board :LS-7394P
4 4
Audio Board : LS-7392P USB (Port,11)
Light Peak Board : LS-7393P USB (Port,10)
P.47
P.46
P.46
A
Function Board: LS-6002P
PWR Button Board:LS-6003P
USB Board : LS7395P
FPC Cable : LF7391P
P.50
P.48
P.46
P.46
m-SATA
ENE 3810
B
eDP (UMA)
CRT HDMI LVDS
DisplayPort
DisplayPort
PCI-E x4 PCI-E x1
Port 1
LAN(GbE)
RTL8111E-VB
RJ45
P.42
USB2.0 port 5 SATA Port1
P.51
P.47
Touch Pad Int.KBD
(UMA)
100MHz
2.7GT/s
ENE KB930/Co-lay KB9012
P.50 P.50 P.50
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Intel
Ivy Bridge
Processor
rPGA 989 Socket
Intel
Cougar Point Panther Point
PCH
BGA 989 Balls
LPC Bus
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
C
P.4~9
DMI x4FDI x8
100MHz 5GB/s
P15~22
EC ROM
Memory Bus
Dual Channel
1.5V DDR3 1866MHz
SATA
USB2.0
USB 3.0
HD Audio
SPI
P.49
SYS BIOS ROM
Deciphered Date
Deciphered Date
Deciphered Date
Port 0
Port 2
Port 4 Port 1
Port 8
Port 9
Port 0
Port 8
Port 4
Port 2 Port 2
204pin DDRIII SO-DIMM x2
BANK 0, 1, 2, 3
SATA HDD-1 Conn. SATA 3.0
SATA ODD Conn. SATA 2.0
ESATA+ USB 2.0
USB 2.0 Conn.
on right side
USB 2.0 Conn./light peak
on right side
USB 2.0 /USB 3.0 Conn.
Camera Mini Card-1 (WLAN& BTcombo)
( Half )
USB 2.0/USB 3.0 Conn.
On Left Side
Audio Codec
Realtek ALC269
P.15
D
Audio board
Title
Title
Title
Chief River-Block Diagram
Chief River-Block Diagram
Chief River-Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
Date: Sheet
P.45
P.36
IO board
P.46
Compal Electronics, Inc.
LA-7391P
P.48
P.11, 12
Reserved USB2.0 / USB 3.0 Port3
Audio board
light peak board
IO board
Int. Speaker Audio Jack x2
( HeadPhone, MIC)
Digital MIC
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0 1 2 3 4 5 6 7 NC
100K +/- 5%Ra
Rb V min
00 V
8.2K +/- 5% 0.168V 0.250 V 0.362 V 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
AD_BID
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
V typ
AD_BID
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
V
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
max
BOARD ID Table
Board ID
0 1 2 3 4 5 6 7
PCB Revision
0.1
A
USB PORT#
0 1 2 3 4
USB2/3 (Ext Right Side Up) ESATA ( Ext Right Side Up) USB2/3 (Ext Left Side Down) USB2/3 (Ext FPC board) JMINI1 (WLAN)
DESTINATION
Bluetooth
5
SMBUS Control Table
SOURCE
EC_SMB_CK1 EC_SMB_DA1
EC_SMB_CK2 EC_SMB_DA2
PCH_SMBCLK PCH_SMBDATA PCH
PCH_SMLCLK PCH_SMLDATA
KB930
KB930
PCH
MIINI1 BATT SODIMM
X X
VV
MINI2
V
XX
X
XX
EXPRESS CARD
X
XX X
V
XX
X
V
X
DGPU Internal Thermal sensor
JXDP1 JXDP2
XX
V
X
V
X
V
X
CLKOUT PCI0 PCI1 PCI2 PCI3
DESTINATION
PCH_LOOPBACK
EC
Debug Port
LPC Debug Port
PCH
6 7 8 9 10 11 12
PCI4
1 1
UMA: UMA@/XDP@/UO@
None
13
JMINI2 (WWAN) None None CAMERA JUSB3 ( Ext Right Side Down) EXPRESS CARD JUSB4 ( Ext Right Side Down) None None
OPTIMUS: XDP@/D@/UO@ DISCRETE:XDP@D@/DIS@
CLK
CLKOUT_PCIE0 CLKOUT_PCIE1 CLKOUT_PCIE2 CLKOUT_PCIE3 CLKOUT_PCIE4
DESTINATIONDIFFERENTIAL 10/100/1G LAN
EXPRESS CARD CARD READER Light Peak
FLEX CLOCKS DESTINATION CLKOUTFLEX0 CLKOUTFLEX1 CLKOUTFLEX2 CLKOUTFLEX3
None CLK_14MMINI CARD-1 WLAN 27M_CLK 27M_SSC
SATA SATA0 SATA1 SATA2 SATA3 SATA4
DESTINATION
HDD m-SATA ODD None
ESATA
PCI EXPRESS
Lane 1 Lane 2 Lane 3 Lane 4 Lane 5
DESTINATION 10/100/1G LAN MINI CARD-1 WLAN EXPRESS CARD CARD READER Light Peak
CLKOUT_PCIE5
CLKOUT_PCIE7 CLKOUT_PEG_B
None NoneCLKOUT_PCIE6 None None
6\PERO1RWH
PHDQV'LJLWDO*URXQG
PHDQV$QDORJ*URXQG
SATA5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I NG DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECT R ONICS, INC. AND C ONTAINS CONFIDENT IAL
THIS SHEET OF ENGINEER I NG DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECT R ONICS, INC. AND C ONTAINS CONFIDENT IAL
THIS SHEET OF ENGINEER I NG DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECT R ONICS, INC. AND C ONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
A
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
None
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Lane 6 Lane 7 Lane 8
Light Peak Light Peak Light Peak
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-7391P
LA-7391P
LA-7391P
of
of
of
364Thursday, April 07, 2011
364Thursday, April 07, 2011
364Thursday, April 07, 2011
0.2
0.2
0.2
5
JCPU1A
D D
DMI_CRX_PTX_N017 DMI_CRX_PTX_N117 DMI_CRX_PTX_N217 DMI_CRX_PTX_N317
DMI_CRX_PTX_P017 DMI_CRX_PTX_P117 DMI_CRX_PTX_P217 DMI_CRX_PTX_P317
DMI_CTX_PRX_N017 DMI_CTX_PRX_N117 DMI_CTX_PRX_N217 DMI_CTX_PRX_N317
DMI_CTX_PRX_P017 DMI_CTX_PRX_P117 DMI_CTX_PRX_P217 DMI_CTX_PRX_P317
FDI_CTX_PRX_N017 FDI_CTX_PRX_N117 FDI_CTX_PRX_N217 FDI_CTX_PRX_N317 FDI_CTX_PRX_N417 FDI_CTX_PRX_N517
RC2
RC2
FDI_CTX_PRX_N617 FDI_CTX_PRX_N717
FDI_CTX_PRX_P017 FDI_CTX_PRX_P117 FDI_CTX_PRX_P217 FDI_CTX_PRX_P317 FDI_CTX_PRX_P417 FDI_CTX_PRX_P517 FDI_CTX_PRX_P617 FDI_CTX_PRX_P717
FDI_FSYNC017 FDI_FSYNC117
FDI_INT17 FDI_LSYNC017
FDI_LSYNC117
EDP_AUXP41 EDP_AUXN41
EDP_TXP041 EDP_TXP141 EDP_TXP241 EDP_TXP341
EDP_TXN041 EDP_TXN141 EDP_TXN241 EDP_TXN341
C C
+V1.05S_VCCP
12
24.9_0402_1%
24.9_0402_1%
eDP_COMPIO and ICOMPO signals should be shorted
B B
near balls and routed with typical impedance <25 mohms
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
FDI_FSYNC0 FDI_FSYNC1
FDI_INT FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
EDP_HPD#
JCPU1A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD#
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
+V1.05S_VCCP
12
RC3
RC3 1K_0402_5%
1K_0402_5%
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
4
+V1.05S_VCCP
12
RC1
RC1
24.9_0402_1%
24.9_0402_1%
PEG_COMP
PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]
PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
J22 J21 H22
PCIE_GTX_C_CRX_N15
K33
PCIE_GTX_C_CRX_N14
M35
PCIE_GTX_C_CRX_N13
L34
PCIE_GTX_C_CRX_N12
J35
PCIE_GTX_C_CRX_N11
J32
PCIE_GTX_C_CRX_N10
H34
PCIE_GTX_C_CRX_N9
H31
PCIE_GTX_C_CRX_N8
G33
PCIE_GTX_C_CRX_N7
G30
PCIE_GTX_C_CRX_N6
F35
PCIE_GTX_C_CRX_N5
E34
PCIE_GTX_C_CRX_N4
E32
PCIE_GTX_C_CRX_N3
D33
PCIE_GTX_C_CRX_N2
D31
PCIE_GTX_C_CRX_N1
B33
PCIE_GTX_C_CRX_N0
C32
PCIE_GTX_C_CRX_P15
J33
PCIE_GTX_C_CRX_P14
L35
PCIE_GTX_C_CRX_P13
K34
PCIE_GTX_C_CRX_P12
H35
PCIE_GTX_C_CRX_P11
H32
PCIE_GTX_C_CRX_P10
G34
PCIE_GTX_C_CRX_P9
G31
PCIE_GTX_C_CRX_P8
F33
PCIE_GTX_C_CRX_P7
F30
PCIE_GTX_C_CRX_P6
E35
PCIE_GTX_C_CRX_P5
E33
PCIE_GTX_C_CRX_P4
F32
PCIE_GTX_C_CRX_P3
D34
PCIE_GTX_C_CRX_P2
E31
PCIE_GTX_C_CRX_P1
C33
PCIE_GTX_C_CRX_P0
B32
PCIE_CTX_GRX_N15
M29
PCIE_CTX_GRX_N14
M32
PCIE_CTX_GRX_N13
M31
PCIE_CTX_GRX_N12
L32
PCIE_CTX_GRX_N11
L29
PCIE_CTX_GRX_N10
K31
PCIE_CTX_GRX_N9
K28
PCIE_CTX_GRX_N8
J30
PCIE_CTX_GRX_N7
J28
PCIE_CTX_GRX_N6
H29
PCIE_CTX_GRX_N5
G27
PCIE_CTX_GRX_N4
E29
PCIE_CTX_GRX_N3
F27
PCIE_CTX_GRX_N2
D28
PCIE_CTX_GRX_N1
F26
PCIE_CTX_GRX_N0
E25
PCIE_CTX_GRX_P15
M28
PCIE_CTX_GRX_P14
M33
PCIE_CTX_GRX_P13
M30
PCIE_CTX_GRX_P12
L31
PCIE_CTX_GRX_P11
L28
PCIE_CTX_GRX_P10
K30
PCIE_CTX_GRX_P9
K27
PCIE_CTX_GRX_P8
J29
PCIE_CTX_GRX_P7
J27
PCIE_CTX_GRX_P6
H28
PCIE_CTX_GRX_P5
G28
PCIE_CTX_GRX_P4
E28
PCIE_CTX_GRX_P3
F28
PCIE_CTX_GRX_P2
D27
PCIE_CTX_GRX_P1
E26
PCIE_CTX_GRX_P0
D25
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
CC1 0.22U_0402_10V6KD@CC1 0.22U_0402_10V6KD@
1 2
CC2 0.22U_0402_10V6KD@CC2 0.22U_0402_10V6KD@
1 2
CC3 0.22U_0402_10V6KD@CC3 0.22U_0402_10V6KD@
1 2
CC4 0.22U_0402_10V6KD@CC4 0.22U_0402_10V6KD@
1 2
CC5 0.22U_0402_10V6KD@CC5 0.22U_0402_10V6KD@
1 2
CC6 0.22U_0402_10V6KD@CC6 0.22U_0402_10V6KD@
1 2
CC7 0.22U_0402_10V6KD@CC7 0.22U_0402_10V6KD@
1 2
CC8 0.22U_0402_10V6KD@CC8 0.22U_0402_10V6KD@
1 2
CC9 0.22U_0402_10V6KD@CC9 0.22U_0402_10V6KD@
1 2
CC10 0.22U_0402_10V6KD@CC10 0.22U_0402_10V6KD@
1 2
CC11 0.22U_0402_10V6KD@CC11 0.22U_0402_10V6KD@
1 2
CC12 0.22U_0402_10V6KD@CC12 0.22U_0402_10V6KD@
1 2
CC13 0.22U_0402_10V6KD@CC13 0.22U_0402_10V6KD@
1 2
CC14 0.22U_0402_10V6KD@CC14 0.22U_0402_10V6KD@
1 2
CC15 0.22U_0402_10V6KD@CC15 0.22U_0402_10V6KD@
1 2
CC16 0.22U_0402_10V6KD@CC16 0.22U_0402_10V6KD@
1 2
CC17 0.22U_0402_10V6KD@CC17 0.22U_0402_10V6KD@
1 2
CC18 0.22U_0402_10V6KD@CC18 0.22U_0402_10V6KD@
1 2
CC19 0.22U_0402_10V6KD@CC19 0.22U_0402_10V6KD@
1 2
CC20 0.22U_0402_10V6KD@CC20 0.22U_0402_10V6KD@
1 2
CC21 0.22U_0402_10V6KD@CC21 0.22U_0402_10V6KD@
1 2
CC22 0.22U_0402_10V6KD@CC22 0.22U_0402_10V6KD@
1 2
CC23 0.22U_0402_10V6KD@CC23 0.22U_0402_10V6KD@
1 2
CC24 0.22U_0402_10V6KD@CC24 0.22U_0402_10V6KD@
1 2
CC25 0.22U_0402_10V6KD@CC25 0.22U_0402_10V6KD@
1 2
CC26 0.22U_0402_10V6KD@CC26 0.22U_0402_10V6KD@
1 2
CC27 0.22U_0402_10V6KD@CC27 0.22U_0402_10V6KD@
1 2
CC28 0.22U_0402_10V6KD@CC28 0.22U_0402_10V6KD@
1 2
CC29 0.22U_0402_10V6KD@CC29 0.22U_0402_10V6KD@
1 2
CC30 0.22U_0402_10V6KD@CC30 0.22U_0402_10V6KD@
1 2
CC31 0.22U_0402_10V6KD@CC31 0.22U_0402_10V6KD@
1 2
CC32 0.22U_0402_10V6KD@CC32 0.22U_0402_10V6KD@
1 2
3
PCIE_GTX_C_CRX_N[0..15] 24
PCIE_GTX_C_CRX_P[0..15] 24
PAY ATTENTION ON PCIE SWAP WHEN REVIEW
PCIE_CTX_C_GRX_N15 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P0
2
PCIE_CTX_C_GRX_N[0..15] 24
PCIE_CTX_C_GRX_P[0..15] 24
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
VSS
VSS
1
F22
VSS234
F19
VSS235
E30
VSS236
E27
VSS237
E24
VSS238
E21
VSS239
E18
VSS240
E15
VSS241
E13
VSS242
E10
VSS243
E9
VSS244
E8
VSS245
E7
VSS246
E6
VSS247
E5
VSS248
E4
VSS249
E3
VSS250
E2
VSS251
E1
VSS252
D35
VSS253
D32
VSS254
D29
VSS255
D26
VSS256
D20
VSS257
D17
VSS258
C34
VSS259
C31
VSS260
C28
VSS261
C27
VSS262
C25
VSS263
C23
VSS264
C10
VSS265
C1
VSS266
B22
VSS267
B19
VSS268
B17
VSS269
B15
VSS270
B13
VSS271
B11
VSS272
B9
VSS273
B8
VSS274
B7
VSS275
B5
VSS276
B3
VSS277
B2
VSS278
A35
VSS279
A32
VSS280
A29
VSS281
A26
VSS282
A23
VSS283
A20
VSS284
A3
VSS285
EDP_HPD#
13
D
D
QC1
QC1
A A
CPU_EDP_HPD41
5
2
G
G
12
RC4
RC4 100K_0402_5%
100K_0402_5%
2N7002_SOT23-3
2N7002_SOT23-3
S
S
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(1/6) DMI,FDI,PEG
PROCESSOR(1/6) DMI,FDI,PEG
PROCESSOR(1/6) DMI,FDI,PEG
LA-7391P
LA-7391P
LA-7391P
1
of
of
of
464Thursday, April 07, 2011
464Thursday, April 07, 2011
464Thursday, April 07, 2011
0.2
0.2
0.2
5
XDP_PREQ# XDP_PRDY#
XDP_BPM#0 XDP_BPM#1
XDP_BPM#2 XDP_BPM#3
CFG10_R
RC150_0402_5% @ RC150_0402_5% @
D D
C C
B B
A A
CFG107 CFG117
CFG07 VGATE17,49,64
The resistor for HOOK2 should be placed such that the stub is very small on CFG0 net
H_PECI19,49
H_PROCHOT#49,56
H_THERMTRIP#19
H_PM_SYNC17
H_CPUPWRGD19
VDDPWRGOOD
CFG0
H_SNB_IVB#19
T0501PAD~D @T0501PAD~D @
5
H_CPUPWRGD
1K_0402_5%~D
1K_0402_5%~D
RC42
RC42
1 2
56_0402_5%
56_0402_5%
RC50
RC50
1 2
0_0402_5%
0_0402_5%
RC54
RC54
1 2
0_0402_5%
0_0402_5%
RC58
RC58
1 2
130_0402_1%
130_0402_1%
12
CFG11_R
RC170_0402_5% @ RC170_0402_5% @
12
XDP_BPM#4 XDP_BPM#5
XDP_BPM#6 XDP_BPM#7
RC24
RC24
1K_0402_5%~D
1K_0402_5%~D
1 2 1 2
RC26 0_0402_5%~D
RC26 0_0402_5%~D RC27
1 2 1 2
RC29 0_0402_5%~D
RC29 0_0402_5%~D
PCH_SMBDATA11,12,16,47,51 PCH_SMBCLK11,12,16,47,51
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#
H_PM_SYNC_R
H_CPUPWRGD_R
VDDPWRGOOD_R
BUF_CPU_RST#
XDP@
XDP@ XDP@
XDP@ XDP@RC27
XDP@ XDP@
XDP@
H_CPUPWRGD_XDP CFD_PWRBTN#_XDP
XDP_HOOK2 SYS_PWROK_XDP
XDP_TCK
12
@
@
RC34
RC34 1K_0402_5%~D
1K_0402_5%~D
SYS_PWROK_XDP
C26
AN34
AL33
AN33
AL32
AN32
AM34
AP33
AR33
+V1.05S_VCCP +V1.05S_VCCP
T0502PAD~D @T0502PAD~D @
+V1.05S_VCCP+3VALW
XDP@
XDP@
JCPU1B
JCPU1B
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
V8
SM_DRAMPWROK
RESET#
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
4
JXDP1
CONN@JXDP1
CONN@
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A
SAMTE_BSH-030-01-L-D-A
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
XDP@
XDP@
CC34
CC34
2
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSDATA_D0 OBSDATA_D1
OBSDATA_D2 OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CC35
CC35
2
Place near JXDP1
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
CLOCKS
CLOCKS
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
4
GND1 OBSFN_C0 OBSFN_C1
GND3
GND5
GND7 OBSFN_D0 OBSFN_D1
GND9
GND11
GND13
GND15
TD0
TRST#
TDI
TMS
GND17
BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
PRDY# PREQ#
TCK TMS
TRST#
TDO
DBR#
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
TDI
CLK_CPU_ITP CLK_CPU_ITP#
XDP_RST#_R XDP_DBRESET#
XDP_TDO XDP_TRST# XDP_TDI XDP_TMS
CLK_CPU_DMI_R
A28
CLK_CPU_DMI#_R
A27
CLK_CPU_DPLL_R
A16
CLK_CPU_DPLL#_R
A15
H_DRAMRST#
R8
SM_RCOMP0
AK1
SM_RCOMP1
A5
SM_RCOMP2
A4
XDP_PRDY#
AP29
XDP_PREQ#
AP27
XDP_TCK
AR26
XDP_TMS
AR27
XDP_TRST#
AP30
XDP_TDI_R
AR28
XDP_TDO_R
AP26
XDP_DBRESET#_R
AL35
XDP_BPM#0_R
AT28
XDP_BPM#1_R
AR29
XDP_BPM#2_R
AR30
XDP_BPM#3_R
AT30
XDP_BPM#4_R
AP32
XDP_BPM#5_R
AR31
XDP_BPM#6_R
AT31
XDP_BPM#7_R
AR32
XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7
3
SYSTEM_PWROK17
RC11
RC11
200_0402_1%
200_0402_1%
PM_DRAM_PWRGD17
CLK_CPU_ITP 16 CLK_CPU_ITP# 16PBTN_OUT#15,17,49
PLT_RST#
XDP@
XDP@
12
RC28 1K_0402_5%
RC28 1K_0402_5%
RC39 0_0402_5%RC39 0_0402_5%
1 2
RC36 0_0402_5%RC36 0_0402_5%
1 2
RC37 0_0402_5%RC37 0_0402_5%
1 2
RC41 0_0402_5%RC41 0_0402_5%
1 2
H_DRAMRST# 6
Processor Pullups
H_PROCHOT#
RC51 0_0402_5%XDP@RC51 0_0402_5%XDP@
1 2
RC52 0_0402_5%XDP@RC52 0_0402_5%XDP@
1 2
RC57 0_0402_5%XDP@RC57 0_0402_5%XDP@
1 2
RC60 0_0402_5%XDP@RC60 0_0402_5%XDP@
1 2
RC62 0_0402_5%XDP@RC62 0_0402_5%XDP@
1 2
RC63 0_0402_5%XDP@RC63 0_0402_5%XDP@
1 2
RC64 0_0402_5%XDP@RC64 0_0402_5%XDP@
1 2
RC65 0_0402_5%XDP@RC65 0_0402_5%XDP@
1 2
RC66 0_0402_5%XDP@RC66 0_0402_5%XDP@
1 2
RC67 0_0402_5%XDP@RC67 0_0402_5%XDP@
1 2
RC68 0_0402_5%XDP@RC68 0_0402_5%XDP@
1 2
RC69 0_0402_5%@RC69 0_0402_5%@
1 2
RC70 0_0402_5%@RC70 0_0402_5%@
1 2
RC71 0_0402_5%@RC71 0_0402_5%@
1 2
RC72 0_0402_5%@RC72 0_0402_5%@
1 2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
XDP_DBRESET#
3
CLK_CPU_DMI 16 CLK_CPU_DMI# 16
CLK_CPU_DPLL 16 CLK_CPU_DPLL# 16
+V1.05S_VCCP
1 2
XDP_TDI XDP_TDO
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
RC4462_0402_5% RC4462_0402_5%
XDP_DBRESET#_R 15,17
CFG12 7 CFG13 7 CFG14 7 CFG15 7
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+3V_PCH +3VS
12
12
12
RC12
RC12
@
@
0_0402_5%
0_0402_5%
1 2
RC21 0_0402_5%RC21 0_0402_5%
D_PWG
STUFF R0570 UNSTUFF R0569
RUN_ON_CPU1.5VS3#9,11,55
PLT_RST#18,42,47,49,51,52
XDP_DBRESET#_R
H_CPUPWRGD_R
DDR3 Compensation Signals
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
2
RC13
RC13
10K_0402_5%
10K_0402_5%
1 2
1 2
1 2 1 2 1 2
1
+3VALW
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CC33
CC33
1
2
5
UC1
UC1
1
P
A
4
O
2
B
G
74AHC1G09GW TSSOP 5P
74AHC1G09GW TSSOP 5P
3
RUN_ON_CPU1.5VS3#
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CC36
CC36
2
1
5
UC2
UC2
P
BUFO_CPU_RST# BUF_CPU_RST#
4
NC
A2Y
G
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
3
+3VS
RC431K_0402_5% RC431K_0402_5%
RC4510K_0402_5% RC4510K_0402_5%
RC56140_0402_1% RC56140_0402_1% RC5925.5_0402_1% RC5925.5_0402_1% RC61200_0402_1% RC61200_0402_1%
Title
Title
Title
PROCESSOR(2/6) PM,XDP,CLK
PROCESSOR(2/6) PM,XDP,CLK
PROCESSOR(2/6) PM,XDP,CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-7391P
LA-7391P
LA-7391P
Date: Sheet
Date: Sheet
Date: Sheet
+1.5V_CPU_VDDQ
12
RC14
RC14 200_0402_1%
200_0402_1%
VDDPWRGOOD
@
@
RC25
RC25 39_0402_1%
39_0402_1%
1 2
13
D
D
@
@
QC2
QC2
2
G
G
2N7002_SOT23-3
2N7002_SOT23-3
S
S
+V1.05S_VCCP
12
RC38
RC38 75_0402_5%
75_0402_5%
RC35
RC35
1 2
43_0402_1%
43_0402_1%
12
PU/PD for JTAG signals
XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TDO_R
XDP_TCK XDP_TRST#
1 2 1 2 1 2 1 2
1 2 1 2
Compal Electronics, Inc.
1
@
@
RC40
RC40 0_0402_5%
0_0402_5%
564Thursday, April 07, 2011
564Thursday, April 07, 2011
564Thursday, April 07, 2011
RC4651_0402_5% RC4651_0402_5% RC4751_0402_5% RC4751_0402_5% RC4851_0402_5% @ RC4851_0402_5% @ RC4951_0402_5% RC4951_0402_5%
RC5351_0402_5% RC5351_0402_5% RC5551_0402_5% RC5551_0402_5%
+V1.05S_VCCP
of
of
of
0.2
0.2
0.2
5
JCPU1C
JCPU1C
DDR_A_D[0..63]11
D D
C C
B B
DDR_A_BS011 DDR_A_BS111 DDR_A_BS211
DDR_A_CAS#11 DDR_A_RAS#11 DDR_A_WE#11
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
G10
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
N10
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
M10
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
AG6
SA_DQ[32]
AG5
SA_DQ[33]
AK6
SA_DQ[34]
AK5
SA_DQ[35]
AH5
SA_DQ[36]
AH6
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
AK8
SA_DQ[41]
AJ9
SA_DQ[42]
AK9
SA_DQ[43]
AH8
SA_DQ[44]
AH9
SA_DQ[45]
AL9
SA_DQ[46]
AL8
SA_DQ[47]
AP11
SA_DQ[48]
AN11
SA_DQ[49]
AL12
SA_DQ[50]
AM12
SA_DQ[51]
AM11
SA_DQ[52]
AL11
SA_DQ[53]
AP12
SA_DQ[54]
AN12
SA_DQ[55]
AJ14
SA_DQ[56]
AH14
SA_DQ[57]
AL15
SA_DQ[58]
AK15
SA_DQ[59]
AL14
SA_DQ[60]
AK14
SA_DQ[61]
AJ15
SA_DQ[62]
AH15
SA_DQ[63]
AE10
SA_BS[0]
AF10
SA_BS[1]
V6
SA_BS[2]
AE8
SA_CAS#
AD9
SA_RAS#
AF9
SA_WE#
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]
RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]
SA_CS#[0]
SA_CS#[1] RSVD_TP[7] RSVD_TP[8]
SA_ODT[0]
SA_ODT[1] RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]
SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
4
AB6 AA6 V9
AA5 AB5 V10
AB4 AA4 W9
AB3 AA3 W10
AK3 AL3 AG1 AH1
AH3 AG3 AG2 AH2
C4 G6 J3 M6 AL6 AM8 AR12 AM15
D4 F6 K3 N6 AL5 AM9 AR11 AM14
AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDRA_CLK0 11 DDRA_CLK0# 11 DDRA_CKE0 11
DDRA_CLK1 11 DDRA_CLK1# 11 DDRA_CKE1 11
DDRA_SCS0# 11 DDRA_SCS1# 11
DDRA_ODT0 11 DDRA_ODT1 11
DDR_A_DQS#[0..7] 11
DDR_A_DQS[0..7] 11
DDR_A_MA[0..15] 11
3
DDR_B_D[0..63]12
DDR_B_BS012 DDR_B_BS112 DDR_B_BS212
DDR_B_CAS#12 DDR_B_RAS#12 DDR_B_WE#12
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
2
JCPU1D
JCPU1D
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
AM5
SB_DQ[32]
AM6
SB_DQ[33]
AR3
SB_DQ[34]
AP3
SB_DQ[35]
AN3
SB_DQ[36]
AN2
SB_DQ[37]
AN1
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
AN9
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
AN8
SB_DQ[45]
AR6
SB_DQ[46]
AR5
SB_DQ[47]
AR9
SB_DQ[48]
AJ11
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
AH11
SB_DQ[52]
AR8
SB_DQ[53]
AJ12
SB_DQ[54]
AH12
SB_DQ[55]
AT11
SB_DQ[56]
AN14
SB_DQ[57]
AR14
SB_DQ[58]
AT14
SB_DQ[59]
AT12
SB_DQ[60]
AN15
SB_DQ[61]
AR15
SB_DQ[62]
AT15
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
AA10
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
1
AE2
SB_CLK[0]
AD2
SB_CLK#[0]
R9
SB_CKE[0]
AE1
SB_CLK[1]
AD1
SB_CLK#[1]
R10
SB_CKE[1]
AB2
RSVD_TP[11]
AA2
RSVD_TP[12]
T9
RSVD_TP[13]
AA1
RSVD_TP[14]
AB1
RSVD_TP[15]
T10
RSVD_TP[16]
AD3
SB_CS#[0]
AE3
SB_CS#[1]
AD6
RSVD_TP[17]
AE6
RSVD_TP[18]
AE4
SB_ODT[0]
AD4
SB_ODT[1]
AD5
RSVD_TP[19]
AE5
RSVD_TP[20]
DDR_B_DQS#0
D7
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]
SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
F3 K6 N3 AN5 AP9 AK12 AP15
C7 G3 J6 M3 AN6 AP8 AK11 AP14
AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4
DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDRB_CLK0 12 DDRB_CLK0# 12 DDRB_CKE0 12
DDRB_CLK1 12 DDRB_CLK1# 12 DDRB_CKE1 12
DDRB_SCS0# 12 DDRB_SCS1# 12
DDRB_ODT0 12 DDRB_ODT1 12
DDR_B_DQS#[0..7] 12
DDR_B_DQS[0..7] 12
DDR_B_MA[0..15] 12
+1.5V
@
@
1 2
RC75 0_0402_5%~D
RC75 0_0402_5%~D
QC3
QC3
BSS138_SOT23
BSS138_SOT23
D
S
D
S
H_DRAMRST#5
A A
H_DRAMRST#
RC78
RC78
4.99K_0402_1%~D
4.99K_0402_1%~D
5
12
13
G
G
2
DRAMRST_CNTRL
1
CC37
CC37
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2
DDR3_DRAMRST#_R
12
RC76
RC76 1K_0402_5%~D
1K_0402_5%~D
1 2
RC77 1K_0402_5%RC77 1K_0402_5%
DG 0.5
4
DRAMRST_CNTRL_PCH16
SM_DRAMRST# 11,12
1 2
RC73 0_0402_5%~DRC73 0_0402_5%~D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
DRAMRST_CNTRL
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
DRAMRST_CNTRL 9
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Num b er Rev
Size Document Num b er Rev
Size Document Num b er Rev Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(3/6) DDRIII
PROCESSOR(3/6) DDRIII
PROCESSOR(3/6) DDRIII
LA-7391P
LA-7391P
LA-7391P
1
664Thursday, April 07, 2011
664Thursday, April 07, 2011
664Thursday, April 07, 2011
of
of
of
0.2
0.2
0.2
5
4
3
2
1
CFG Straps for Processor
D D
JCPU1E
JCPU1E
T0749 PAD~D@T0749 PAD~D@ T0750 PAD~D@T0750 PAD~D@
T0704 PAD~D@T0704 PAD~D@ T0705 PAD~D@T0705 PAD~D@ T0701 PAD~D@T0701 PAD~D@ T0702 PAD~D@T0702 PAD~D@
T0706 PAD~D@T0706 PAD~D@
T0707 PAD~D@T0707 PAD~D@ T0708 PAD~D@T0708 PAD~D@ T0709 PAD~D@T0709 PAD~D@
T0710 PAD~D@T0710 PAD~D@ T0711 PAD~D@T0711 PAD~D@ T0703 PAD~D@T0703 PAD~D@ T0712 PAD~D@T0712 PAD~D@
T0713 PAD~D@T0713 PAD~D@ T0714 PAD~D@T0714 PAD~D@ T0715 PAD~D@T0715 PAD~D@ T0716 PAD~D@T0716 PAD~D@ T0717 PAD~D@T0717 PAD~D@
T0719 PAD~D@T0719 PAD~D@ T0720 PAD~D@T0720 PAD~D@ T0721 PAD~D@T0721 PAD~D@ T0722 PAD~D@T0722 PAD~D@ T0723 PAD~D@T0723 PAD~D@
T0728 PAD~D@T0728 PAD~D@ T0730 PAD~D@T0730 PAD~D@
CLK_RES_ITP 16 CLK_RES_ITP# 16
T0744 PAD~D@T0744 PAD~D@ T0745 PAD~D@T0745 PAD~D@ T0746 PAD~D@T0746 PAD~D@
T0748 PAD~D@T0748 PAD~D@
PEG Static Lane Reversal - CFG2 is for the 16x
Display Port Presence Strap
PCIE Port Bifurcation Straps
CFG[6:5]
RSVD28 RSVD29 RSVD30 RSVD31
RSVD32
RSVD33 RSVD34 RSVD35
RSVD37 RSVD38 RSVD39 RSVD40
RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5
RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9
RSVD51 RSVD52
BCLK_ITP
BCLK_ITP#
AH27 AH26
L7 AG7 AE7 AK2
W8
AT26 AM33 AJ27
T8 J16 H16 G16
AR35 AT34 AT33 AP35 AR34
B34 A33 A34 B35 C35
AJ32 AK32
AN35 AM35
AT2 AT1 AR1
B1
KEY
CFG
CFG
RESERVED
RESERVED
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD_NCTF10
RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13
CFG05
T0751PAD~D @T0751PAD~D @ T0752PAD~D @T0752PAD~D @
T0753PAD~D @T0753PAD~D @ T0754PAD~D @T0754PAD~D @
+VCC_GFXCORE_ AXG
+VCC_CORE
12
RC80
RC80
49.9_0402_1%
49.9_0402_1%
12
RC81
RC81
49.9_0402_1%
49.9_0402_1%
C C
B B
VCC_AXG_VAL_SENSE
CFG105 CFG115 CFG125 CFG135 CFG145 CFG155
T0755PAD~D @T0755PAD~D @ T0756PAD~D @T0756PAD~D @
VCC_VAL_SENSE
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE
T0718PAD~D @T0718PAD~D @
T0724PAD~D @T0724PAD~D @ T0725PAD~D @T0725PAD~D @ T0726PAD~D @T0726PAD~D @ T0727PAD~D @T0727PAD~D @ T0729PAD~D @T0729PAD~D @ T0731PAD~D @T0731PAD~D @ T0732PAD~D @T0732PAD~D @ T0733PAD~D @T0733PAD~D @ T0734PAD~D @T0734PAD~D @ T0735PAD~D @T0735PAD~D @ T0736PAD~D @T0736PAD~D @ T0737PAD~D @T0737PAD~D @ T0738PAD~D @T0738PAD~D @ T0739PAD~D @T0739PAD~D @ T0740PAD~D @T0740PAD~D @ T0741PAD~D @T0741PAD~D @
T0742PAD~D @T0742PAD~D @ T0743PAD~D @T0743PAD~D @
T0747PAD~D @T0747PAD~D @
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
CFG2
12
RC79
RC79 1K_0402_1%~D
1K_0402_1%~D
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition 0:Lane Reversed
CFG4
12
RC82
RC82 1K_0402_1%~D
1K_0402_1%~D
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is connected to the Embedded Display Port
CFG6 CFG5
1K_0402_1%~D
1K_0402_1%~D
RC83
@RC83
@
12
12
RC84
@RC84
@
1K_0402_1%~D
1K_0402_1%~D
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
12
RC85
@RC85
@
1K_0402_1%~D
1K_0402_1%~D
No discribe in CPU EDS 1.5
Need PWR add new circuit on 1.05V(refer CRB)
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE
12
RC86
RC86
49.9_0402_1%
A A
49.9_0402_1%
12
RC87
RC87
49.9_0402_1%
49.9_0402_1%
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following RESETB de assertion 0: PEG Wait for BIOS for training
INTEL 12/28 recommand to add RC120, RC121, RC122, RC123 Please place as close as JCPU1
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Num b er Rev
Size Document Num b er Rev
Size Document Num b er Rev Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(4/6) RSVD,CFG
PROCESSOR(4/6) RSVD,CFG
PROCESSOR(4/6) RSVD,CFG
LA-7391P
LA-7391P
LA-7391P
764Thursday, April 07, 2011
764Thursday, April 07, 2011
764Thursday, April 07, 2011
1
0.2
0.2
0.2
of
of
of
5
D D
C C
B B
A A
4
JCPU1F
JCPU1F
+VCC_CORE
97A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
3
POWER
POWER
PEG AND DDR
PEG AND DDR
CORE SUPPLY
CORE SUPPLY
VSS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8
VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24
VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39
VCCIO40
VIDALERT#
VIDSCLK VIDSOUT
VCC_SENSE VSS_SENSE
VCCIO_SENSE
+V1.05S_VCCP
8.5A
AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12
E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11
J23
H_CPU_SVIDALRT#
AJ29
H_CPU_SVIDCLK
AJ30
H_CPU_SVIDDAT
AJ28
Place the PU resistors close to CPU
VCCSENSE_R
AJ35
VSSSENSE_R
AJ34
B10 A10
2
+V1.05S_VCCP
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CC49
CC49
1 2
43_0402_1%
43_0402_1%
RC96
RC96
10_0402_1%
10_0402_1%
RC98
RC98 10_0402_1%
10_0402_1%
+V1.05S_VCCP
RC91
RC91
+V1.05S_VCCP
12
12
RC89
RC89 75_0402_5%
75_0402_5%
12
VCCIO_SENSE 60
2
RC90
RC90
130_0402_1%~D
130_0402_1%~D
H_CPU_SVIDDAT
1 2
RC94 0_0402_5% ~DRC94 0_0402_5% ~D
1 2
RC95 0_0402_5% ~DRC95 0_0402_5% ~D
12
H_CPU_SVIDCLK
Place the PU resistors close to CPU
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
RC92 0_0402_5%~DRC92 0_0402_5%~D
CC50
CC50
1 2
RC121
RC121
1 2
100_0402_1%~D
100_0402_1%~D
@
@
1 2
RC88 0_0402_5%~DRC88 0_0402_5%~D
+VCC_CORE
12
12
RC93
RC93 100_0402_1%~D
100_0402_1%~D
RC97
RC97 100_0402_1%~D
100_0402_1%~D
VR_SVID_ALRT# 64
VCCSENSE 64 VSSSENSE 64
1
VR_SVID_CLK 64
VR_SVID_DAT 64
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PRO PR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CO N FIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PRO PR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CO N FIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PRO PR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CO N FIDENTIAL AND TRADE SECRET INFORMAT ION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMAT ION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMAT ION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH I R D PARTY WITHOUT PRIOR W R I TTEN CONSENT OF COMPAL ELECT R ON I C S, INC.
MAY BE USED BY OR DISCLOSED TO ANY TH I R D PARTY WITHOUT PRIOR W R I TTEN CONSENT OF COMPAL ELECT R ON I C S, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY TH I R D PARTY WITHOUT PRIOR W R I TTEN CONSENT OF COMPAL ELECT R ON I C S, INC.
3
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(5/6) PWR,BYPASS
PROCESSOR(5/6) PWR,BYPASS
PROCESSOR(5/6) PWR,BYPASS
LA-7391P
LA-7391P
LA-7391P
864Thursday, April 07, 2011
864Thursday, April 07, 2011
864Thursday, April 07, 2011
of
of
1
of
0.2
0.2
0.2
5
4
3
2
1
+1.5V_CPU_VDDQ
+1.5V +1.5V_CPU_VDDQ
+VSBP+3VALW
12
RC101
D D
RC103
@RC103
@
SUSP#47,49,55,59,60,61,65
CPU1.5V_S3_GATE49
C C
B B
1 2
0_0402_5%~D
0_0402_5%~D
RC104
RC104
1 2
0_0402_5%~D
0_0402_5%~D
+VCC_GFXCORE_AXG
33A
AR24 AR23 AR21 AR20 AR18 AR17
AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17
AK24 AK23 AK21 AK20 AK18 AK17
AH24 AH23 AH21 AH20 AH18 AH17
AT24 AT23 AT21 AT20 AT18 AT17
AP24 AP23 AP21 AP20 AP18 AP17
AL24 AL23 AL21 AL20 AL18 AL17
AJ24 AJ23 AJ21 AJ20 AJ18 AJ17
+1.8VS +1.8VS_VCCPLL
RC119
RC119
0_0805_5%
0_0805_5%
1 2
A A
+V_DDR_REFA
+V_DDR_REFB
DRAMRST_CNTRL
10U_0805_6.3VAM
10U_0805_6.3VAM
1
2
RC115 0_0402_5%~D@RC115 0_0402_5%~D@ RC116 0_0402_5%~D@RC116 0_0402_5%~D@
2
G
G
CC58
CC58
13
D
D
S
S
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC59
CC59
2
1 2 1 2
QC8
QC8 BSS138_SOT23
BSS138_SOT23
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CC60
CC60
13
D
D
G
G
S
S
RC117
RC117
1K_0402_1%
1K_0402_1%
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1
CC61
CC61
+
+
2 3
QC7
QC7
BSS138_SOT23
BSS138_SOT23
2
12
@
@
1.5A
B6 A6 A2
DRAMRST_CNTRL 6
12
RC118
RC118 1K_0402_1%
1K_0402_1%
@
@
RC101 100K_0402_5%~D
100K_0402_5%~D
RUN_ON_CPU1.5VS3#
61
QC5A
QC5A 2N7002DW-7-F_SOT363-6~D
2N7002DW-7-F_SOT363-6~D
2
POWER
JCPU1G
JCPU1G
VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54
VCCPLL1 VCCPLL2 VCCPLL3
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
+V_DDR_REFA_R +V_DDR_REFB_R
POWER
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
SM_VREF
SA_DIMM_VREFDQ SB_DIMM_VREFDQ
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID[0] VCCSA_VID[1]
VCCIO_SEL
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
5
4
12
RC99
RC99 100K_0402_5%~D
100K_0402_5%~D
RUN_ON_CPU1.5VS3
3
QC5B
QC5B
5
2N7002DW-7-F_SOT363-6~D
2N7002DW-7-F_SOT363-6~D
4
RUN_ON_CPU1.5VS3# 5, 11,55
AK35 AK34
+V_SM_VREF_CNT
AL1
+V_DDR_REFA_R
B4
+V_DDR_REFB_R
D1
+1.5V_CPU_VDDQ
5A
AF7
VDDQ1
AF4
VDDQ2
AF1
VDDQ3
AC7
VDDQ4
AC4
VDDQ5
AC1
VDDQ6
Y7
VDDQ7
Y4
VDDQ8
Y1
VDDQ9
U7
VDDQ10
U4
VDDQ11
U1
VDDQ12
P7
VDDQ13
P4
VDDQ14
P1
VDDQ15
6A
M27
VCCSA1
M26
VCCSA2
L26
VCCSA3
J26
VCCSA4
J25
VCCSA5
J24
VCCSA6
H26
VCCSA7
H25
VCCSA8
H23
C22 C24
A19
H_VCCSA_VID0 63 H_VCCSA_VID1 63
H_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SEL
IVY Bridge drives VCCIO_SEL low VCCP_PWRCTRL:0
Sandy Bridge is NC for A19 VCCP_PWRCTRL:1
Security Classifica t i on
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AO4728L_SO8~D
AO4728L_SO8~D
8 7 6 5
12
+VCC_GFXCORE_AXG
12
RC105
RC105 10_0402_1%
10_0402_1%
RC106
RC106
10_0402_1%
10_0402_1%
+1.5V_CPU_VDDQ
12
12
10U_0805_6.3VAM
10U_0805_6.3VAM
10U_0805_6.3VAM
10U_0805_6.3VAM
1
1
CC51
CC51
2
2
10U_0805_6.3VAM
10U_0805_6.3VAM
1
CC40
CC40
2
10K_0402_5%
10K_0402_5%
Issued Date
Issued Date
Issued Date
3
QC4
QC4
1 2
12
3
1
4
CC38
CC38
2
RC100
RC100
20K_0402_5%~D
20K_0402_5%~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
2
RC102
RC102
330K_0402_1%
330K_0402_1%
0.1U_0603_50V_X7R
0.1U_0603_50V_X7R
CC39
CC39
Place near CPU
VCC_AXG_SENSE 64
12
RC120
RC120 1K_0402_1%~D
1K_0402_1%~D
RC109
RC109 1K_0402_1%~D
1K_0402_1%~D
10U_0805_6.3VAM
10U_0805_6.3VAM
1
CC52
CC52
2
10U_0805_6.3VAM
10U_0805_6.3VAM
1
CC41
CC41
2
12
@ RC111
@
RC112
RC112
12
RC1140_0402_5%~D RC1140_0402_5%~D
RUN_ON_CPU1.5VS3
1
CC53
CC53
2
10U_0805_6.3VAM
10U_0805_6.3VAM
1
2
RC111
0_0402_5%~D
0_0402_5%~D
1 2
VSS_AXG_SENSE 64
12
RC1070_0402_5% @RC1070_0402_5% @
QC6
QC6
@
@
D
S
D
S
13
G
G
PMV45EN_ SOT23-3
PMV45EN_ SOT23-3
2
10U_0805_6.3VAM
10U_0805_6.3VAM
10U_0805_6.3VAM
10U_0805_6.3VAM
10U_0805_6.3VAM
10U_0805_6.3VAM
1
1
CC54
CC54
CC55
CC55
2
2
330U_D2_2VM_R6M
330U_D2_2VM_R6M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
@
@
1
+
+
CC42
CC42
CC43
CC43
2 3
2
+VCCSA_SENSE 63
+3VALW+3VS
RC113
RC113
10K_0402_5%
10K_0402_5%
1 2
@
@
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
1 2
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1
CC57
CC57
CC56
CC56
+
+
2 3
CC44
CC44
VCCP_PWRCTRL 60
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+V_SM_VREF should have 10 mil trace width
+V_SM_VREF
+1.5V
JP0901
@JP0901
@
PAD-OPEN 4x4m
PAD-OPEN 4x4m
+VCCSA
+1.5V
2
@
@
12
RC108
RC108 1K_0402_1%~D
1K_0402_1%~D
12
RC110
RC110 1K_0402_1%~D@
1K_0402_1%~D@
JCPU1H
JCPU1H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
Title
Title
Title
PROCESSOR(6/6) PWR,VSS
PROCESSOR(6/6) PWR,VSS
PROCESSOR(6/6) PWR,VSS
Size Document Number Rev
Size Docu me n t Number Rev
Size Docu me n t Number Rev
Custom
Custom
Custom
LA-7391P
LA-7391P
LA-7391P
Date: Sheet
Date: Sheet
Date: Sheet
VSS
VSS
+1.5V_CPU_VDDQ +1.5V
CC45 0.1U_0402_10V7K~DCC45 0.1U_0402_10V7K~D
12
CC46 0.1U_0402_10V7K~DCC46 0.1U_0402_10V7K~D
12
CC47 0.1U_0402_10V7K~DCC47 0.1U_0402_10V7K~D
12
CC48 0.1U_0402_10V7K~DCC48 0.1U_0402_10V7K~D
12
Compal Electronics, Inc.
1
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
964Thursday, April 07, 2011
964Thursday, April 07, 2011
964Thursday, April 07, 2011
AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2
of
of
of
0.2
0.2
0.2
5
+1.5VS_S3.5
12
RD1
RD1
1K_0402_1%
1K_0402_1%
+V_DDR_REFA
RD2
D D
C C
B B
A A
RD2
1K_0402_1%
1K_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
CD50
CD50
1
12
2
DDRA_CKE06
DDR_A_BS26
DDRA_CLK06 DDRA_CLK0#6
DDR_A_BS06 DDR_A_WE#6
DDR_A_CAS#6
DDRA_SCS1#6
+3VS
5
2.2U_0603_6.3V4Z
CD1
CD1
CD2
1
2
CD2
1
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
CD25
CD25
1
1
2
2
+1.5VS_S3.5 +1.5VS_S3.5
DDR3 SO-DIMM A
DDR_A_D0 DDR_A_D1
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_D26 DDR_A_D27
DDRA_CKE0
DDR_A_BS2 DDR_A_MA12
DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3
DDR_A_MA1 DDRA_CLK0
DDRA_CLK0# DDR_A_MA10
DDR_A_BS0 DDR_A_WE#
DDR_A_CAS# DDRA_ODT0 DDR_A_MA13
DDRA_SCS1#
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_D42 DDR_A_D43
DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_D58 DDR_A_D59
CD26
CD26
RD8
10K_0402_5%
RD8
10K_0402_5%
RD9
10K_0402_5%
RD9
10K_0402_5%
12
12
4
4BA2/6W
4BA2/6W
4BA2/6W4BA2/6W
JDDRL
JDDRL
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4526-0100
LCN_DAN06-K4526-0100 CONN@
CONN@
4
DQ4 DQ5
VSS3
DQS#0
DQS0 VSS6
DQ6
DQ7 VSS8 DQ12 DQ13
VSS10
DM1
VSS12
DQ14 DQ15
VSS14
DQ20 DQ21
VSS16
DM2
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
VSS24
DQ30 DQ31
VSS26
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA VTT2
A15 A14
A11
CK1
BA1
S0#
NC2
SCL
3
DDR_A_D[0..63]6 DDR_A_DQS[0..7]6 DDR_A_DQS#[0..7]6
DDRA_CKE1 6
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
DDR_A_MA[0..15]6
+1.5VS_S3.5
12
RD6
RD6 1K_0402_1%
1K_0402_1%
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
CD15
CD15
CD16
CD16
12
1
RD7
RD7 1K_0402_1%
1K_0402_1%
2
2010/05/27 2011/05/11
2010/05/27 2011/05/11
2010/05/27 2011/05/11
3
+VREF_CA
2
DDR_A_D4
4
DDR_A_D5
6 8
DDR_A_DQS#0
10
DDR_A_DQS0
12 14
DDR_A_D6
16
DDR_A_D7
18 20
DDR_A_D12
22
DDR_A_D13
24 26 28
SM_DRAMRST#
30 32
DDR_A_D14
34
DDR_A_D15
36 38
DDR_A_D20
40
DDR_A_D21
42 44 46 48
DDR_A_D22
50
DDR_A_D23
52 54
DDR_A_D28
56
DDR_A_D29
58 60
DDR_A_DQS#3
62
DDR_A_DQS3
64 66
DDR_A_D30
68
DDR_A_D31
70 72
DDRA_CKE1
74 76
DDR_A_MA15
78
DDR_A_MA14
80 82
DDR_A_MA11
84
DDR_A_MA7
86
A7
88
DDR_A_MA6
90
A6 A4
A2 A0
G2
DDR_A_MA4
92 94
DDR_A_MA2
96
DDR_A_MA0
98 100
DDRA_CLK1
102
DDRA_CLK1#
104 106
DDR_A_BS1
108
DDR_A_RAS#
110 112
DDRA_SCS0#
114 116 118
DDRA_ODT1
120 122 124 126 128
DDR_A_D36
130
DDR_A_D37
132 134 136 138
DDR_A_D38
140
DDR_A_D39
142 144
DDR_A_D44
146
DDR_A_D45
148 150
DDR_A_DQS#5
152
DDR_A_DQS5
154 156
DDR_A_D46
158
DDR_A_D47
160 162
DDR_A_D52
164
DDR_A_D53
166 168 170 172
DDR_A_D54
174
DDR_A_D55
176 178
DDR_A_D60
180
DDR_A_D61
182 184
DDR_A_DQS#7
186
DDR_A_DQS7
188 190
DDR_A_D62
192
DDR_A_D63
194 196 198
PM_SMBDATA
200
PM_SMBCLK
202 204
206
+0.75VS
1/76BA1/86W
1/76BA1/86W
1/76BA1/86W1/76BA1/86W
SM_DRAMRST# 6,12
DDRA_CLK1 6 DDRA_CLK1# 6
DDR_A_BS1 6 DDR_A_RAS# 6
DDRA_SCS0# 6 DDRA_ODT0 6
DDRA_ODT1 6
PCH_SMBDATA 5,12,16,47,51 PCH_SMBCLK 5,12,16,47,51
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.5V
Deciphered Date
Deciphered Date
Deciphered Date
JP1102
JP1102
PAD-OPEN 4x4m@
PAD-OPEN 4x4m@
JP1101
JP1101
@
@
PAD-OPEN 4x4m
PAD-OPEN 4x4m
QD1
QD1
8 7 6 5
FDS6676AS_SO8
FDS6676AS_SO8
1
CD5
CD5
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
+1.5VS_S3.5
12
12
+1.5V to +1.5VS_S3.5
1
Vgs=10V,Id=14.5A,Rds=6mohm
1
CD3
CD3
1
S
D
2
S
D
S
D
G
D
2
3 4
CD6
CD6
1
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_25V6
0.1U_0402_25V6
RUN_ON_CPU1.5VS3#5,9,55
+1.5VS_S3.5
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
CD7
CD7
1
+
+
2
12
RD5
RD5 820K_0402_5%
820K_0402_5%
10U_0603_6.3V6M
10U_0603_6.3V6M
CD8
CD8
1
2
1
CD4
CD4
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
RD4
RD4
1 2
220K_0402_5%
220K_0402_5%
61
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Layout Note: Place near JDDRL
10U_0603_6.3V6M
10U_0603_6.3V6M
CD9
CD9
1
2
Layout Note: Place these 4 Caps near Command and Control sig n als of JDDRL
+1.5VS_S3.5
Layout Note: Place near JDDRL.203,204
+0.75VS
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
+VSBP
QD2A
QD2A
RUN_ON_CPU1.5VS3#
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
RUN_ON_CPU1.5VS3#
10U_0603_6.3V6M
10U_0603_6.3V6M
CD11
CD11
CD10
CD10
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
CD17
CD17
1
1
2
2
CD21
1U_0402_6.3V6K
CD21
1U_0402_6.3V6K
1
1
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRIII-DDRL
DDRIII-DDRL
DDRIII-DDRL
LA-7391P
LA-7391P
LA-7391P
RD3
RD3
470_0805_5%
470_0805_5%
1 2 3
QD2B
QD2B
5
4
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD12
CD12
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K CD19
CD19
CD18
CD18
1
1
2
2
CD22
1U_0402_6.3V6K
CD22
1U_0402_6.3V6K
CD23
1U_0402_6.3V6K
CD23
1U_0402_6.3V6K
1
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD14
CD14
CD13
CD13
1
1
@
@
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K CD20
CD20
CD24
1U_0402_6.3V6K
CD24
1U_0402_6.3V6K
1
2
of
of
of
11 64Thursday, April 07, 2011
11 64Thursday, April 07, 2011
11 64Thursday, April 07, 2011
0.2
0.2
0.2
5
+1.5VS_S3.5
12
RD10
RD10
1K_0402_1%
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
CD28
CD28
2
1K_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K
1
2
DDRB_CKE06
DDR_B_BS26
DDRB_CLK06 DDRB_CLK0#6
DDR_B_BS06 DDR_B_WE#6
DDR_B_CAS#6
DDRB_SCS1#6
+3VS
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_B_D0 DDR_B_D1
1
12
RD11
RD11
CD27
CD27
CD51
CD51
2
DDR_B_D2 DDR_B_D3
DDR_B_D8
1K_0402_1%
1K_0402_1%
DDR_B_D9 DDR_B_DQS#1
DDR_B_DQS1 DDR_B_D10
DDR_B_D11 DDR_B_D16
DDR_B_D17 DDR_B_DQS#2
DDR_B_DQS2 DDR_B_D18
DDR_B_D19 DDR_B_D24
DDR_B_D25
DDR_B_D26 DDR_B_D27
DDRB_CKE0
DDR_B_BS2 DDR_B_MA12
DDR_B_MA9 DDR_B_MA8
DDR_B_MA5 DDR_B_MA3
DDR_B_MA1 DDRB_CLK0
DDRB_CLK0# DDR_B_MA10
DDR_B_BS0 DDR_B_WE#
DDR_B_CAS# DDRB_ODT0 DDR_B_MA13
DDRB_SCS1#
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_D42 DDR_B_D43
DDR_B_D48 DDR_B_D49
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51
DDR_B_D56 DDR_B_D57
DDR_B_D58 DDR_B_D59
RD14
RD14
1 2
10K_0402_5%
10K_0402_5%
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z CD49
CD49
CD48
CD48
1
1
2
5
RD15 10K_0402_5%RD15 10K_0402_5%
2
+V_DDR_REFB
D D
C C
B B
A A
+1.5VS_S3.5 +1.5VS_S3.5
4BA2/6W
4BA2/6W
4BA2/6W4BA2/6W
JDDRH
JDDRH
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
VREF_CA VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
G1
LCN_DAN06-K4926-0100
LCN_DAN06-K4926-0100 CONN@
CONN@
1 2
127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
205
VSS3
DQS#0
DQS0 VSS6
VSS8 DQ12 DQ13
VSS10
VSS12
DQ14 DQ15
VSS14
DQ20 DQ21
VSS16 VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
VSS24
DQ30 DQ31
VSS26
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36 DQ37
VSS30 VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42 VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
DQ4 DQ5
DQ6 DQ7
DM1
DM2
CK1
CK1#
BA1
NC2
DM4
DM6
SDA SCL
VTT2
4
2
DDR_B_D4
4
DDR_B_D5
6 8
DDR_B_DQS#0
10
DDR_B_DQS0
12 14
DDR_B_D6
16
DDR_B_D7
18 20
DDR_B_D12
22
DDR_B_D13
24 26 28
SM_DRAMRST#
30 32
DDR_B_D14
34
DDR_B_D15
36 38
DDR_B_D20
40
DDR_B_D21
42 44 46 48
DDR_B_D22
50
DDR_B_D23
52 54
DDR_B_D28
56
DDR_B_D29
58 60
DDR_B_DQS#3
62
DDR_B_DQS3
64 66
DDR_B_D30
68
DDR_B_D31
70 72
DDRB_CKE1
74 76
DDR_B_MA15
78
A15 A14
A11
A7 A6
A4 A2
A0
S0#
G2
DDR_B_MA14
80 82
DDR_B_MA11
84
DDR_B_MA7
86 88
DDR_B_MA6
90
DDR_B_MA4
92 94
DDR_B_MA2
96
DDR_B_MA0
98 100
DDRB_CLK1
102
DDRB_CLK1#
104 106
DDR_B_BS1
108
DDR_B_RAS#
110 112
DDRB_SCS0#
114 116 118
DDRB_ODT1
120 122 124
+VREF_CB
126 128
DDR_B_D36
130
DDR_B_D37
132 134 136 138
DDR_B_D38
140
DDR_B_D39
142 144
DDR_B_D44
146
DDR_B_D45
148 150
DDR_B_DQS#5
152
DDR_B_DQS5
154 156
DDR_B_D46
158
DDR_B_D47
160 162
DDR_B_D52
164
DDR_B_D53
166 168 170 172
DDR_B_D54
174
DDR_B_D55
176 178
DDR_B_D60
180
DDR_B_D61
182 184
DDR_B_DQS#7
186
DDR_B_DQS7
188 190
DDR_B_D62
192
DDR_B_D63
194 196 198
PM_SMBDATA
200
PM_SMBCLK
202 204
206
4
1/76BA1/86W
1/76BA1/86W
1/76BA1/86W1/76BA1/86W
SM_DRAMRST# 6,11
DDRB_CKE1 6
DDRB_CLK1 6 DDRB_CLK1# 6
DDR_B_BS1 6 DDR_B_RAS# 6
DDRB_SCS0# 6 DDRB_ODT0 6
DDRB_ODT1 6
0.1U_0402_10V6K
0.1U_0402_10V6K CD46
CD46
1
2
PCH_SMBDATA 5,11,16,47,51 PCH_SMBCLK 5,11,16,47,51
+0.75VS
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
3
DDR_B_DQS#[0..7]6 DDR_B_D[0..63]6 DDR_B_DQS[0..7]6 DDR_B_MA[0..15]6
Layout Note: Place these 4 Caps near Command and Control si g n a l s o f JDDRH
+1.5VS_S3.5
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K CD32
CD32
CD29
CD29
1
1
2
2
+1.5VS_S3.5
12
RD12
RD12
1K_0402_1%
1K_0402_1%
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z CD47
CD47
1
2
1K_0402_1%
1K_0402_1%
RD13
RD13
3
12
2010/05/27 2011/05/11
2010/05/27 2011/05/11
2010/05/27 2011/05/11
0.1U_0402_10V6K
0.1U_0402_10V6K CD30
CD30
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K CD33
CD33
1
2
Deciphered Date
Deciphered Date
Deciphered Date
+1.5VS_S3.5
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
@
@
CD31
CD31
1
+
+
2
2
Layout Note: Place near JDDRH
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD34
CD34
CD35
CD35
1
@
@
@
@
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD36
CD36
CD37
CD37
1
1
2
1
2
2
Layout Note: Place near JDDRH.203 and 204
+0.75VS
1U_0603_10V4Z
1U_0603_10V4Z
CD42
CD42
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD38
CD38
1U_0603_10V4Z
1U_0603_10V4Z
CD43
CD43
1
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD39
CD39
1
1
2
2
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
CD45
CD45
CD44
CD44
1
1
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-7391P
LA-7391P
LA-7391P
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD41
CD41
CD40
CD40
1
1
2
2
DDRIII-DDRH
DDRIII-DDRH
DDRIII-DDRH
1
0.2
0.2
0.2
of
12 64Thursday, April 07, 2011
of
12 64Thursday, April 07, 2011
of
12 64Thursday, April 07, 2011
5
PCH_RTCX1
1 2
RH2 10M_0402_5%RH2 10M_0402_5%
15P_0402_50V8J
15P_0402_50V8J
1
1
CH2
CH2
OSC4OSC
2
YH1
D D
C C
B B
A A
YH1
NC3NC
2
far away hot spot
ME_EN from EC. Please place close to RH29 aviod the branch.
HDA_SDO49
HDA for AUDIO
HDA_BITCLK_AUDIO46
HDA_RST_AUDIO#46
+3V_PCH +3V_PCH+3V_PCH
12
RH38
RH38
200_0402_5%
200_0402_5%
PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS
12
RH44
RH44
100_0402_1%
100_0402_1%
RH50
RH50
Intel DPDG Rev1.2 requirement.
HDA_SYNC_AUDIO46 EC_ON 48,49,58
+3V_PCH
RH59
RH59
RH61
RH61
10P_0402_50V8J
10P_0402_50V8J
Reserve for EMI please close to U1502
PCH_RTCX2
32.768KHZ_12.5PF_Q13MC14610002
32.768KHZ_12.5PF_Q13MC14610002
1
CH3
CH3 15P_0402_50V8J
15P_0402_50V8J
2
RH25 0_0402_5%~DRH25 0_0402_5%~D
1 2
RH27 33_0402_5%RH27 33_0402_5%
1 2
RH30 33_0402_5%RH30 33_0402_5%
1 2
RH32 33_0402_5%RH32 33_0402_5%
12
RH39
RH39
200_0402_5%
200_0402_5%
12
RH45
RH45
100_0402_1%
100_0402_1%
12
51_0402_5%
51_0402_5%
1 2
RH54 33_0402_5%RH54 33_0402_5%
PCH_SPI_WP#
1 2
3.3K_0402_5%
3.3K_0402_5%
PCH_SPI_HOLD#
1 2
3.3K_0402_5%
3.3K_0402_5%
CH7
CH7
RH65
RH65
12
1 2
0_0402_5%
0_0402_5%
+RTCVCC
1 2
RH12 1M_0402_5%RH12 1M_0402_5%
+RTCVCC
1 2
PCH_JTAG_TCK
12
12
1M_0402_5%
1M_0402_5%
CH4
CH4
1U_0603_10V4Z
1U_0603_10V4Z
1 2
RH23 20K_0402_5%RH23 20K_0402_5%
1 2
RH24 20K_0402_5%RH24 20K_0402_5%
CH5
CH5
1U_0603_10V4Z
1U_0603_10V4Z
HDA_SDOUT
HDA_BIT_CLK
HDA_RST# HDA_SDOUT PCH_INTVRMEN
RH40
RH40
200_0402_5%
200_0402_5%
RH46
RH46
100_0402_1%
100_0402_1%
+5VS
12
RH56
RH56
1
12
SHORT PADS
SHORT PADS
2
1
12
SHORT PADS
SHORT PADS
2
CLP1 & CLP2 place near DIMM
PCH_SPI_CLK PCH_SPI_CS#
PCH_SPI_SI PCH_SPI_SO
G
G
2
13
D
S
D
S
BSS138_SOT23
BSS138_SOT23 QH1
QH1
SM_INTRUDER#
CMOS
CLRP1
CLRP1
CLRP2
CLRP2
ME CMOS
HDA_SPKR46
HDA_SDIN046
@
@
1 2
RH47 0_0402_5%
RH47 0_0402_5%
@
@
1 2
RH49 0_0402_5%
RH49 0_0402_5%
@
@
1 2
RH51 0_0402_5%
RH51 0_0402_5%
@
@
1 2
RH53 0_0402_5%
RH53 0_0402_5%
Please place RH68, RH69, RH72, RH156 to close to UH6
HDA_SYNC EC_ON
Intel recommend
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_CLK
1 2 1 2 1 2
4
UH1A
PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN
HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#
HDA_SDIN0
HDA_SDOUT
PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO
PCH_SPI_CLK_RR PCH_SPI_CS#_RR
PCH_SPI_SI_RR PCH_SPI_SO_RR
UH1A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVR MEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
JTAG
JTAG
63,520)250(0%\WH
+3V_SPI
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
@
@
CH6
CH6
PCH_SPI_WP#
PCH_SPI_HOLD# PCH_SPI_CS#_RPCH_SPI_CS# PCH_SPI_CLK_R
PCH_SPI_SI_R
1
CH99
CH99 10P_0402_50V8J
10P_0402_50V8J
2
1
2
UH3
UH3
8 3 7 1 6 5
W25Q32BVSSIG_SO8
W25Q32BVSSIG_SO8
@
@
RH60
RH60
3.3K_0402_5%
3.3K_0402_5%
RH64 0_0402_5%RH64 0_0402_5% RH66 0_0402_5%RH66 0_0402_5% RH67 0_0402_5%RH67 0_0402_5%
+3V_SPI
RTCIHDA
RTCIHDA
SPI
SPI
VCC W HOLD S C D
FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
SATA1RXN SATA1RXP
SATA 6G
SATA 6G
SATA1TXN SATA1TXP
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
SATA3RXN SATA3RXP SATA3TXN SATA3TXP
SATA4RXN SATA4RXP SATA4TXN
SATA
SATA
SATA4TXP SATA5RXN
SATA5RXP SATA5TXN SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19
4
VSS
PCH_SPI_SO_R
2
Q
V14 P1
C38 A38 B37 C37
D36 E36
K36 V5
AM3 AM1 AP7 AP5
AM10 AM8 AP11 AP10
AD7 AD5 AH5 AH4
AB8 AB10 AF3 AF1
Y7 Y5 AD3 AD1
Y3 Y1 AB3 AB1
Y11 Y10
AB12 AB13
AH1
P3
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_FRAME# LPC_LDRQ0#
LPC_LDRQ1# SERIRQ
PCH_SATALED# PCH_GPIO21 BBS_BIT0_R
+3VS
RH57
RH57
@
@
0_0402_5%
0_0402_5%
1 2
RH68
RH68
1 2
0_0402_5%
0_0402_5%
3
SATA_COMP
SATA3_COMP
RBIAS_SATA3
+3V_PCH
NEC flash issue.
LPC_AD0 49 LPC_AD1 49 LPC_AD2 49 LPC_AD3 49
LPC_FRAME# 49
T1511 PAD~D@ T 1511 PAD~D@ T1509 PAD~D@ T 1509 PAD~D@
SERIRQ 49
SATA_PRX_DTX_N0 45 SATA_PRX_DTX_P0 45 SATA_PTX_DRX_N0 45 SATA_PTX_DRX_P0 45
SATA_PRX_DTX_N1 51 SATA_PRX_DTX_P1 51 SATA_PTX_DRX_N1 51 SATA_PTX_DRX_P1 51
SATA_PRX_DTX_N2 36HDA_SDOUT_AUDIO46 SATA_PRX_DTX_P2 36 SATA_PTX_DRX_N2 36 SATA_PTX_DRX_P2 36
T1501 PAD~D@ T1501 PAD~D@ T1502 PAD~D@ T1502 PAD~D@ T1503 PAD~D@ T1503 PAD~D@ T1504 PAD~D@ T1504 PAD~D@
SATA_PRX_DTX_N4 47 SATA_PRX_DTX_P4 47 SATA_PTX_DRX_N4 47 SATA_PTX_DRX_P4 47
T1505 PAD~D@ T1505 PAD~D@ T1506 PAD~D@ T1506 PAD~D@ T1507 PAD~D@ T1507 PAD~D@ T1508 PAD~D@ T1508 PAD~D@
1 2
RH41 37.4_0402_1%RH41 37.4_0402_1%
1 2
RH43 49.9_0402_1%RH43 49.9_0402_1%
1 2
RH48 750_0402_1%RH48 750_0402_1%
PCH_SATALED# 50
RH52 0_0402_5%@ RH52 0_0402_5%@ T1510 PAD~D@ T 1510 PAD~D@
RH58
RH58 0_0402_5%
0_0402_5%
1 2
+3V_PCH
RH63
RH63
3.3K_0402_5%
3.3K_0402_5%
@
@
1 2
PCH_SPI_SO
Please close to JXDP2
PCH_RSMRST#17,49
+1.05VS_VCC_SATA
+1.05VS_SATA3
12
+3VALW
KSI449,50 KSI549,50 KSI649,50 KSI749,50
PCH_SPI_CS#_RR PCH_SPI_CLK_RR PCH_SPI_SI_RR PCH_SPI_SO_RR
PBTN_OUT#5,17,49
HDD1
m-SATA
ODD
E-SATA
CIO_LSOE_1 52,54
+3V_PCH
KSI4 KSI5
KSI7
2
+3V_PCH
1
CH97
CH97
XDP@
XDP@
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1K_0402_5%~D
1K_0402_5%~D
RH257
1 2
RH258
1 2
RH259
+V1.05S
RH260
+3V_PCH
1 2
0_0402_5%~D
0_0402_5%~D
XDP_DBRESET#_R5,17
PCH_INTVRMEN
+'$B6'2
ME debug mode , this signal has a weak internal PD
L=>security measures defined in the Flash Descriptor will be in effect (default)
H=>Flash Descriptor Security will be overridden
UH2
UH2
1
VDD
4
VDD
9
VDD
19
VDD
24
A0
22
B0
18
C0
17
D0
14
E0
23
A1
21
B1
16
C1
15
D1
13
E1
PI3V512QE_QSOP24
PI3V512QE_QSOP24
RSMRST#_XDP
XDP@RH257
XDP@
PCH_PWRBTN#_XDP
XDP@RH258
XDP@
0_0402_5%~D
0_0402_5%~D
XDP@RH259
XDP@
1 2
0_0402_5%~D
0_0402_5%~D
+3V_PCH_XDP
XDP@RH260
XDP@
XDP_DBRESET#_R
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMS
PCH_JTAG_TCK
RH33 330K_0402_5%RH33 330K_0402_5% RH35 330K_0402_5%@RH35 330K_0402_5%@
INTVRMEN
H烉Integrated VRM enable
*
L
Integrated VRM disable
12
SEL
2
YA
PCH_SPI_CS#
5
YB
PCH_SPI_CLK
6
YC
PCH_SPI_SI
8
YD
PCH_SPI_SOKSI6
11
YE
3
GND
7
GND
10
GND
20
GND
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
12 12
Check
+3V_SPI+3V_PCH
RH69
RH69
@
@
1 2
0_0402_5%
0_0402_5%

CONN@

CONN@
JXDP2
JXDP2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
27
25
G1
28
26
G2
ACES_87152-26051
ACES_87152-26051
SERIRQ
+RTCVCC
HDA_SYNC
This signal has a weak internal pull-down On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low Needs to be pulled High for Chief River platfrom
+3V_SPI
1
CH98
CH98 10P_0402_50V8J
10P_0402_50V8J
2
+RTCVCC
RH28 10K_0402_5%RH28 10K_0402_5%
PCH_GPIO21
RH29 10K_0402_5%RH29 10K_0402_5%
PCH_SATALED#
RH31 10K_0402_5%RH31 10K_0402_5%
BBS_BIT0_R
RH34 4.7K_0402_5%RH34 4.7K_0402_5%
HDA_SPKR
RH36 1K_0402_5%@RH36 1K_0402_5%@
HDA_SDOUT
RH42 1K_0402_5%@RH42 1K_0402_5%@
*
HDA_SYNC
RH55 1K_0402_5%RH55 1K_0402_5%
RTC Battery
W=20mils
1
CH8
CH8 1U_0603_10V4Z
1U_0603_10V4Z
2
LOW=Default HIGH=No Reboot
*
Low = Disabled High = Enabled
+RTCBATT
DH1
DH1
3
BAS40-04_SOT23-3
BAS40-04_SOT23-3
1
12 12 12 12
12
12
12
MAX. 8000mil
RH62
RH62 1K_0402_5%
1K_0402_5%
1 2 1
W=20mils
+CHGRTC
2
W=20mils
+3VS
+3VS
+3V_PCH
+3V_PCH
Remove JDBG1
5
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PRO PR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PRO PR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PRO PR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMAT ION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMAT ION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMAT ION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH I R D PAR T Y WITHOUT PRIOR WRI T T EN CONSENT OF COMPAL ELECTRONI C S, I N C .
MAY BE USED BY OR DISCLOSED TO ANY TH I R D PAR T Y WITHOUT PRIOR WRI T T EN CONSENT OF COMPAL ELECTRONI C S, I N C .
MAY BE USED BY OR DISCLOSED TO ANY TH I R D PAR T Y WITHOUT PRIOR WRI T T EN CONSENT OF COMPAL ELECTRONI C S, I N C .
3
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciph ered Date
Deciph ered Date
Deciph ered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (1/8) SATA,HDA,SPI, LPC
PCH (1/8) SATA,HDA,SPI, LPC
PCH (1/8) SATA,HDA,SPI, LPC
LA-7391P
LA-7391P
LA-7391P
1
15 64Thursday, April 07, 2011
15 64Thursday, April 07, 2011
15 64Thursday, April 07, 2011
of
of
of
0.2
0.2
0.2
5
4
3
2
1
EC_LID_OUT#
1 2
UH1B
D D
10/100/1G LAN --->
MiniWLAN (Mini Card 1)--->
EXPRESS_CARD --->
CARD_READER --->
Light Peak
C C
10/100/1G LAN --->
MiniWLAN (Mini Card 1)--->
EXPRESS_CARD --->
Card Reader --->
B B
Light Peak --->
@
@
RH113
33_0402_5%
33_0402_5%
YH2
YH2
1 2
RH113
12
RH1171M_0402_5% RH1171M_0402_5%
CH27
CH27
CLK_PCI_LPBACK
Reserve for EMI please close to UH4
25MHZ 12PF 5XFA2500012CIF50Q3
25MHZ 12PF 5XFA2500012CIF50Q3
A A
CH26
CH26
15P_0402_50V8J
15P_0402_50V8J
1
2
12
1 2
22P_0402_50V8J
22P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
1
2
5
PCIE_PRX_GLANTX_N142 PCIE_PRX_GLANTX_P142 PCIE_PTX_GLANRX_N142 PCIE_PTX_GLANRX_P142
PCIE_PRX_WLANTX_N251 PCIE_PRX_WLANTX_P251 PCIE_PTX_WLANRX_N251 PCIE_PTX_WLANRX_P251
PCIE_PRX_EXPTX_N347 PCIE_PRX_EXPTX_P347 PCIE_PTX_EXPRX_N347 PCIE_PTX_EXPRX_P347
PCIE_PRX_CARDTX_N447 PCIE_PRX_CARDTX_P447 PCIE_PTX_CARDRX_N447 PCIE_PTX_CARDRX_P447
@
@
CH25
CH25
XTAL25_IN
XTAL25_OUT
PCIE_PTX_C_LPX_N552 PCIE_PTX_C_LPX_P552
PCIE_LPX_C_PRX_N552 PCIE_LPX_C_PRX_P552
PCIE_PTX_C_LPX_N652 PCIE_PTX_C_LPX_P652
CLK_CPU_ITP#5 CLK_CPU_ITP5
CLK_RES_ITP#7 CLK_RES_ITP7
PCIE_LPX_C_PRX_N652 PCIE_LPX_C_PRX_P652
PCIE_PTX_C_LPX_N752
PCIE_PTX_C_LPX_P752 PCIE_LPX_C_PRX_N752 PCIE_LPX_C_PRX_P752
PCIE_PTX_C_LPX_N852
PCIE_PTX_C_LPX_P852 PCIE_LPX_C_PRX_N852 PCIE_LPX_C_PRX_P852
CLK_PCH_14M
CLK_PCIE_LAN#42 CLK_PCIE_LAN42
CLK_PCIE_WLAN#51 CLK_PCIE_WLAN51
WLANCLK_REQ#51
CLK_PCIE_EXP#47 CLK_PCIE_EXP47
EXPCLK_REQ#47
CLK_PCIE_CD#47 CLK_PCIE_CD47
CDCLK_REQ#47
CLK_PCIE_LP#52 CLK_PCIE_LP52
LANCLK_REQ#42
+3V_PCH
33_0402_5%
33_0402_5%
+3V_PCH
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
CLK_CPU_ITP# CLK_CPU_ITP
@
@
RH124
RH124
CH9 0.1U_0402_10V7KCH9 0.1U_0402_10V7K
1 2
CH12 0.1U_0402_10V7KCH12 0.1U_0402_10V7K
1 2
CH13 0.1U_0402_10V7KCH13 0.1U_0402_10V7K
1 2
CH14 0.1U_0402_10V7KCH14 0.1U_0402_10V7K
1 2
CH10 0.1U_0402_10V7KCH10 0.1U_0402_10V7K
1 2
CH15 0.1U_0402_10V7KCH15 0.1U_0402_10V7K
1 2
CH11 0.1U_0402_10V7KCH11 0.1U_0402_10V7K
1 2
CH16 0.1U_0402_10V7KCH16 0.1U_0402_10V7K
1 2
CH17 0.1U_0402_10V7KCH17 0.1U_0402_10V7K
1 2
CH18 0.1U_0402_10V7KCH18 0.1U_0402_10V7K
1 2
CH19 0.1U_0402_10V7KCH19 0.1U_0402_10V7K
1 2
CH20 0.1U_0402_10V7KCH20 0.1U_0402_10V7K
1 2
CH21 0.1U_0402_10V7KCH21 0.1U_0402_10V7K
1 2
CH22 0.1U_0402_10V7KCH22 0.1U_0402_10V7K
1 2
CH23 0.1U_0402_10V7KCH23 0.1U_0402_10V7K
1 2
CH24 0.1U_0402_10V7KCH24 0.1U_0402_10V7K
1 2
RH92 0_0402_5%RH92 0_0402_5%
1 2
RH93 0_0402_5%RH93 0_0402_5%
1 2
RH95 10K_0402_5%RH95 10K_0402_5%
1 2
RH97 0_0402_5%RH97 0_0402_5% RH98 0_0402_5%RH98 0_0402_5% RH99 10K_0402_5%RH99 10K_0402_5%
+3VS
RH100 0_0402_5%RH100 0_0402_5% RH101 0_0402_5%RH101 0_0402_5% RH104 10K_0402_5%RH104 10K_0402_5%
1 2
RH105 0_0402_5%RH105 0_0402_5% RH106 0_0402_5%RH106 0_0402_5% RH107 10K_0402_5%RH107 10K_0402_5%
RH109 10K_0402_5%@RH109 10K_0402_5%@
RH110 10K_0402_5%RH110 10K_0402_5%
RH112 10K_0402_5%RH112 10K_0402_5%
RH114 10K_0402_5%RH114 10K_0402_5%
1 2
RH116 10K_0402_5%RH116 10K_0402_5%
1 2
RH119 10K_0402_5%RH119 10K_0402_5%
1 2
RH120 0_0402_5%RH120 0_0402_5% RH121 0_0402_5%RH121 0_0402_5%
RH122 0_0402_5%@RH122 0_0402_5%@ RH123 0_0402_5%@RH123 0_0402_5%@
@
@
CH28
CH28
12
1 2
22P_0402_50V8J
22P_0402_50V8J
12 12 12
12 12
12 12 12
12 12
12
12 12
12 12
PCIE_PRX_GLANTX_N1 PCIE_PRX_GLANTX_P1 PCIE_PTX_GLANRX_N1_C PCIE_PTX_GLANRX_P1_C
PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2_C PCIE_PTX_WLANRX_P2_C
PCIE_PRX_EXPTX_N3 PCIE_PRX_EXPTX_P3 PCIE_PTX_EXPRX_N3_C PCIE_PTX_EXPRX_P3_C
PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4 PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C
PCIE_PTX_C_LPX_N5 PCIE_PTX_C_LPX_P5 PCIE_LPX_PRX_N5 PCIE_LPX_PRX_P5
PCIE_PTX_C_LPX_N6 PCIE_PTX_C_LPX_P6 PCIE_LPX_PRX_N6 PCIE_LPX_PRX_P6
PCIE_PTX_C_LPX_N7 PCIE_PTX_C_LPX_P7 PCIE_LPX_PRX_N7 PCIE_LPX_PRX_P7
PCIE_PTX_C_LPX_N8 PCIE_PTX_C_LPX_P8 PCIE_LPX_PRX_N8 PCIE_LPX_PRX_P8
PCIE_LAN# PCIE_LAN
LANCLK_REQ#
PCIE_WLAN# PCIE_WLAN
WLANCLK_REQ#
PCIE_EXP# PCIE_EXP
EXPCLK_REQ#
PCIE_CD# PCIE_CD
CDCLK_REQ#
LPCLK_REQ#
T1623PAD~D @T1623PAD~D @ T1622PAD~D @T1622PAD~D @
T1616PAD~D @T1616PAD~D @ T1617PAD~D @T1617PAD~D @
PEG_B_CLKREQ#
T1618PAD~D @T1618PAD~D @ T1619PAD~D @T1619PAD~D @
PCIE_CLKREQ6#
T1620PAD~D @T1620PAD~D @ T1621PAD~D @T1621PAD~D @
GPIO46
CLK_BCLK_ITP# CLK_BCLK_ITP
CLK_BCLK_ITP
4
UH1B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
PCH_LID_SW_IN#
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_GND1_N CLKIN_GND1_P
CLKIN_DOT_96N CLKIN_DOT_96P
CLKIN_SATA_N CLKIN_SATA_P
CLKIN_PCILOOPBACK
CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
3
E12
SMBCLK
H14
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
CLKIN_DMI_N CLKIN_DMI_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SMBDATA
C9
DRAMRST_CNTRL_PCH
A12
SML0CLK
C8
SML0DATA
G12
PCH_HOT#
C13
SML1CLK
E14
SML1DATA
M16
M7
T11
P10
PEG_CLKREQ#_R
M10
CLK_PCIE_VGA#
AB37
CLK_PCIE_VGA
AB38
CLK_CPU_DMI#
AV22
CLK_CPU_DMI
AU22
CLK_CPU_DPLL#
AM12
CLK_CPU_DPLL
AM13
CLKIN_DMI#
BF18
CLKIN_DMI
BE18
CLKIN_DMI2#
BJ30
CLKIN_DMI2
BG30
CLKIN_DOT96#
G24
CLKIN_DOT96
E24
CLKIN_SATA#
AK7
CLKIN_SATA
AK5
CLK_PCH_14M
K45
CLK_PCI_LPBACK
H45
XTAL25_IN
V47
XTAL25_OUT
V49
Y47
K43 F47 H47 K49
T1624 PAD~D@ T1624 PAD~D@
T1625 PAD~D@ T1625 PAD~D@
T1626 PAD~D@ T1626 PAD~D@
XCLK_RCOMP
CLK_FLEX0 CLK_14M_R
RH118
RH118
1 2
22_0402_5%
22_0402_5%
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
RH710_0402_5% RH710_0402_5%
MEMORY
DRAMRST_CNTRL_PCH 6
PCH_HOT# 49
CLK_PCIE_VGA# 24 CLK_PCIE_VGA 24
CLK_CPU_DMI# 5 CLK_CPU_DMI 5
CLK_CPU_DPLL# 5 CLK_CPU_DPLL 5
CLK_PCI_LPBACK 18
1 2
RH115 90.9_0402_1%RH115 90.9_0402_1%
27M_CLK 24 27M_SSC 24
Compal Secret Data
Compal Secret Data
Compal Secret Data
+1.05VS_VCCDIFFCLKN
T1615 PAD~D@ T1615 PAD~D@ T1627 PAD~D@ T1627 PAD~D@
Deciphered Date
Deciphered Date
Deciphered Date
+3V_PCH
12
VGA
2
EC_LID_OUT# 49
RH89
RH89
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
@
@
RH96
RH96 10K_0402_5%
10K_0402_5%
+3VS_DGPU
12
RH90
RH90
2
6 1
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6 QH2A
QH2A
RH94 0_0402_5%
0_0402_5%
SMBCLK
SMBDATA
6 1
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1 2
+3VS_DGPU
RH88
RH88
1K_0402_5%
1K_0402_5%
3
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
QH2B
QH2B
@RH94
@
1 2
2
QH3A
QH3A
RH108
RH108
@
@
0_0402_5%
0_0402_5%
3
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
SML1CLK
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
SML1DATA
SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA
PCH_HOT#
DRAMRST_CNTRL_PCH
CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M
12
If use extenal CLK gen, please place close to CLK gen
else, please place close to PCH
5
QH3B
QH3B
RH111
RH111
@
@
1 2
0_0402_5%
0_0402_5%
12
4
RH102
RH102
2.2K_0402_5%
2.2K_0402_5%
5
4
+3V_PCH
2
6 1
QH4A
QH4A
3
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
QH4B
QH4B
Title
Title
Title
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-7391P
LA-7391P
LA-7391P
Date: Sheet
Date: Sheet
Date: Sheet
1 2
RH70 2.2K_0402_5%RH70 2.2K_0402_5%
1 2
RH72 2.2K_0402_5%RH72 2.2K_0402_5%
1 2
RH77 2.2K_0402_5%RH77 2.2K_0402_5%
1 2
RH73 2.2K_0402_5%RH73 2.2K_0402_5%
1 2
RH74 2.2K_0402_5%RH74 2.2K_0402_5%
1 2
RH78 2.2K_0402_5%RH78 2.2K_0402_5%
1 2
RH75 10K_0402_5%RH75 10K_0402_5%
1 2
RH76 1K_0402_1%RH76 1K_0402_1%
RH79
RH79 RH80
RH80 RH81 10K_0402_5%RH81 10K_0402_5% RH82 10K_0402_5%RH82 10K_0402_5% RH83 10K_0402_5%RH83 10K_0402_5% RH84 10K_0402_5%RH84 10K_0402_5% RH85 10K_0402_5%RH85 10K_0402_5% RH86 10K_0402_5%RH86 10K_0402_5% RH87 10K_0402_5%RH87 10K_0402_5%
PEG_CLKREQ# 24
RH91
RH91
@
@
10K_0402_5%
10K_0402_5%
+3VS+3VS
1 2
1 2
5
4
10K_0402_5%
10K_0402_5% 10K_0402_5%
10K_0402_5%
1 2 1 2 1 2 1 2 1 2 1 2 1 2
RH103
RH103
2.2K_0402_5%
2.2K_0402_5%
PCH_SMBCLK 5,11,12,47,51
PCH_SMBDATA 5,11,12,47,51
PCH_SMLCLK 25,49
PCH_SMLDATA 25,49
Compal Electronics, Inc.
16 64Thursday, April 07, 2011
16 64Thursday, April 07, 2011
1
16 64Thursday, April 07, 2011
of
of
of
+3V_PCH
0.2
0.2
0.2
5
4
3
2
1
UH1C
DMI_CTX_PRX_N04 DMI_CTX_PRX_N14 DMI_CTX_PRX_N24 DMI_CTX_PRX_N34
DMI_CTX_PRX_P04 DMI_CTX_PRX_P14
XDP_DBRESET#_R5,15
SYSTEM_PWROK
PBTN_OUT#5,15,49
ACIN49,57
1 2
RH147 0_0402_5%RH147 0_0402_5%
5
DMI_CTX_PRX_P24 DMI_CTX_PRX_P34
DMI_CRX_PTX_N04 DMI_CRX_PTX_N14 DMI_CRX_PTX_N24 DMI_CRX_PTX_N34
DMI_CRX_PTX_P04 DMI_CRX_PTX_P14 DMI_CRX_PTX_P24 DMI_CRX_PTX_P34
+1.05VS_VCC_EXP
RH126 49.9_0402_1%RH126 49.9_0402_1% RH127 750_0402_1%~DRH127 750_0402_1%~D
4mil width and place within 500mil of the PCH
T1710PAD~D T1710PAD~D
1 2
RH130 0_0402_5%RH130 0_0402_5%
1 2
RH131 0_0402_5%RH131 0_0402_5%
PM_DRAM_PWRGD
RH134
RH134
1 2
1 2
RB751V-40_SOD323-2
RB751V-40_SOD323-2
+3VS
5
2
P
B
1
A
G
3
PCH_GPIO72 RI# WAKE# AC_PRESENT_R SUSWARN# PCH_GPIO29
PCH_RSMRST#
D D
C C
B B
PCH_PWROK49
PM_DRAM_PWRGD5
PCH_RSMRST#15,49
VGATE5,49,64
RH161=200K
A A
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
1 2
1 2
1 2
RH137 0_0402_5%~DRH137 0_0402_5%~D
DH2
DH2
UH5
UH5
Y
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
DMI_IRCOMP RBIAS_CPY
XDP_DBRESET#_R
SYSTEM_PWROK_I
PM_PWROK_R
1 2
RH132 0_0402_5%RH132 0_0402_5%
PCH_RSMRST#_R
0_0402_5%~D
0_0402_5%~D
SUSWARN#
PBTN_OUT#_R
AC_PRESENT_R
SYSTEM_PWROK
4
RH155 10K_0402_5%RH155 10K_0402_5%
1 2
RH157 10K_0402_5%RH157 10K_0402_5%
1 2
RH159 10K_0402_5%RH159 10K_0402_5%
1 2
RH161 200K_0402_5%RH161 200K_0402_5%
1 2
RH234 10K_0402_5%RH234 10K_0402_5%
1 2
RH162 10K_0402_5%RH162 10K_0402_5%
1 2
RH163 10K_0402_5%RH163 10K_0402_5%
1 2
PCH_GPIO72
RI#
UH1C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
SYSTEM_PWROK 5
+3V_PCH
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6
DMI
FDI
DMI
FDI
FDI_RXP7
FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
System Power Management
System Power Management
4
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
Check EC for S3 S4 LED
DSWODVREN DSWODVREN
RH150 330K_0402_5%RH150 330K_0402_5% RH151 330K_0402_5%@RH151 330K_0402_5%@
DSWODVREN - On Die DSW VR Enable
H烉Enable
*
Disable
L
PM_CLKRUN#
AY14 BE14 BH13 BC12 BJ12 BG10 BG9
BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9
AW16 AV12 BC10 AV14 BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
DSWODVREN
WAKE#
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
H_PM_SYNC
12 12
+3VS
12
1 2
FDI_CTX_PRX_N0
BJ14
FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1
RH129
RH129
1 2
PM_CLKRUN#
RH133
RH133
PCH_GPIO29
RH256
RH256
8.2K_0402_5%
8.2K_0402_5%
RH160
RH160 10K_0402_5%
10K_0402_5%
@
@
RH128 0_0402_5%~DRH128 0_0402_5%~D
1 2
0_0402_5%~D
0_0402_5%~D
T1701 PAD~DT1701 PAD~D
12
0_0402_5%
0_0402_5%
T1702 PAD~DT1702 PAD~D
T1703 PAD~DT1703 PAD~D
T1704 PAD~DT1704 PAD~D
T1724 PAD~DT1724 PAD~D
T1705 PAD~DT1705 PAD~D T1706 PAD~DT1706 PAD~D
+RTCVCC
FDI_CTX_PRX_N0 4 FDI_CTX_PRX_N1 4 FDI_CTX_PRX_N2 4 FDI_CTX_PRX_N3 4 FDI_CTX_PRX_N4 4 FDI_CTX_PRX_N5 4 FDI_CTX_PRX_N6 4 FDI_CTX_PRX_N7 4
FDI_CTX_PRX_P0 4 FDI_CTX_PRX_P1 4 FDI_CTX_PRX_P2 4 FDI_CTX_PRX_P3 4 FDI_CTX_PRX_P4 4 FDI_CTX_PRX_P5 4 FDI_CTX_PRX_P6 4 FDI_CTX_PRX_P7 4
FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4
PCH_RSMRST#_RPCH_DPWROK
PCIE_WAKE# 42,47,51
SUSCLK_R 49
PM_SLP_S5# 49
PM_SLP_S4# 49
PM_SLP_S3# 49
H_PM_SYNC 5
PCH_CRT_HSYNC37 PCH_CRT_VSYNC37
Can be left NC when IAMT is not support on the platfrom
+3VS
1 2
RH142 2.2K_0402_5%~DRH142 2.2K_0402_5%~D
1 2
RH144 2.2K_0402_5%~DRH144 2.2K_0402_5%~D
1 2
RH145 2.2K_0402_5%~DRH145 2.2K_0402_5%~D
1 2
RH146 2.2K_0402_5%~DRH146 2.2K_0402_5%~D
RH152 150_0402_1%~DRH152 150_0402_1%~D RH154 150_0402_1%~DRH154 150_0402_1%~D RH156 150_0402_1%~DRH156 150_0402_1%~D RH158 100K_0402_5%~D@RH158 100K_0402_5%~D@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PCH_ENBKL49
PCH_ENVDD38
PCH_INV_PWM38
PCH_LCD_CLK38 PCH_LCD_DATA38
PCH_TXCLK-38 PCH_TXCLK+38
PCH_TXOUT0-38 PCH_TXOUT1-38 PCH_TXOUT2-38
PCH_TXOUT0+38 PCH_TXOUT1+38 PCH_TXOUT2+38
PCH_TZCLK-38 PCH_TZCLK+38
PCH_TZOUT0-38 PCH_TZOUT1-38 PCH_TZOUT2-38
PCH_TZOUT0+38 PCH_TZOUT1+38 PCH_TZOUT2+38
PCH_CRT_BLU37 PCH_CRT_GRN37 PCH_CRT_RED37
PCH_CRT_DDC_CLK37 PCH_CRT_DDC_DAT37
PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT
PCH_CRT_BLU
1 2
PCH_CRT_GRN
1 2
PCH_CRT_RED
1 2
PCH_ENVDD
1 2
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
PCH_ENBKL
1 2
T1708PAD~D T1708PAD~D
PCH_TXCLK­PCH_TXCLK+
PCH_TXOUT0­PCH_TXOUT1­PCH_TXOUT2-
PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+
PCH_TZCLK­PCH_TZCLK+
PCH_TZOUT0­PCH_TZOUT1­PCH_TZOUT2-
PCH_TZOUT0+ PCH_TZOUT1+ PCH_TZOUT2+
PCH_CRT_BLU PCH_CRT_GRN PCH_CRT_RED
PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT
RH135 33_0402_5%RH135 33_0402_5%
1 2 1 2
RH136 33_0402_5%RH136 33_0402_5%
RH138
RH138
1K_0402_0.5%~D
1K_0402_0.5%~D
CTRL_CLK CTRL_DATA
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
RH125
RH125
CTRL_CLK CTRL_DATA
LVDS_IBG
HSYNC_PCH VSYNC_PCH
12
100K_0402_5%
100K_0402_5%
CRT_IREF
2
UH1D
UH1D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
@RH255
@
1 2 1 2
DPC_HPD
100K_0402_5%
100K_0402_5%
DPD_HPD
100K_0402_5%
100K_0402_5%
TMDS_B_HPD LVDS_IBG
12
RH255 RH254
RH254
1 2
RH141 20K_0402_5%RH141 20K_0402_5% RH143 2.37K_0402_1%~DRH143 2.37K_0402_1%~D
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
CRT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
AP43 AP45
AM42 AM40
AP39
SDVO_INTN
AP40
SDVO_INTP
HDMICLK_NB
P38
HDMIDAT_NB
M39
AT49
DDPB_AUXN
AT47
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
DDPD_AUXN DDPD_AUXP
DDPD_HPD
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
+3VS
+3VS
TMDS_B_HPD
AT40
TMDS_B_DATA2#
AV42
TMDS_B_DATA2
AV40
TMDS_B_DATA1#
AV45
TMDS_B_DATA1
AV46
TMDS_B_DATA0#
AU48
TMDS_B_DATA0
AU47
TMDS_B_CLK#
AV47
TMDS_B_CLK
AV49
PCH_DPC_CLK
P46
PCH_DPC_DAT
P42
PCH_DPC_AUXN
AP47
PCH_DPC_AUXP
AP49
DPC_HPD
AT38
PCH_DPC_N0
AY47
PCH_DPC_P0
AY49
PCH_DPC_N1
AY43
PCH_DPC_P1
AY45
PCH_DPC_N2
BA47
PCH_DPC_P2
BA48
PCH_DPC_N3
BB47
PCH_DPC_P3
BB49
PCH_DPD_CLK
M43
PCH_DPD_DAT
M36
PCH_DPD_AUXN
AT45
PCH_DPD_AUXP
AT43
DPD_HPD
BH41
PCH_DPD_N0
BB43
PCH_DPD_P0
BB45
PCH_DPD_N1
BF44
PCH_DPD_P1
BE44
PCH_DPD_N2
BF42
PCH_DPD_P2
BE42
PCH_DPD_N3
BJ42
PCH_DPD_P3
BG42
RH139 2.2K_0402_5%RH139 2.2K_0402_5%
1 2
RH140 2.2K_0402_5%RH140 2.2K_0402_5%
1 2
RH148 2.2K_0402_5%RH148 2.2K_0402_5%
1 2
RH149 2.2K_0402_5%RH149 2.2K_0402_5%
1 2
Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM,GFX,DP
PCH (3/8) DMI,FDI,PM,GFX,DP
PCH (3/8) DMI,FDI,PM,GFX,DP
LA-7391P
LA-7391P
LA-7391P
1
HDMICLK_NB 44 HDMIDAT_NB 44
TMDS_B_HPD 44 TMDS_B_DATA2# 44
TMDS_B_DATA2 44 TMDS_B_DATA1# 44 TMDS_B_DATA1 44 TMDS_B_DATA0# 44 TMDS_B_DATA0 44 TMDS_B_CLK# 44 TMDS_B_CLK 44
PCH_DPC_CLK 47 PCH_DPC_DAT 47
PCH_DPC_AUXN 47 PCH_DPC_AUXP 47
DPC_HPD 47 PCH_DPC_N0 47
PCH_DPC_P0 47 PCH_DPC_N1 47 PCH_DPC_P1 47 PCH_DPC_N2 47 PCH_DPC_P2 47 PCH_DPC_N3 47 PCH_DPC_P3 47
PCH_DPD_AUXN 52 PCH_DPD_AUXP 52
DPD_HPD 52 PCH_DPD_N0 52
PCH_DPD_P0 52 PCH_DPD_N1 52 PCH_DPD_P1 52 PCH_DPD_N2 52 PCH_DPD_P2 52 PCH_DPD_N3 52 PCH_DPD_P3 52
PCH_DPD_CLK PCH_DPD_DAT
PCH_LCD_CLK PCH_LCD_DATAPCH_PWROK
of
of
of
17 64Thursday, April 07, 2011
17 64Thursday, April 07, 2011
17 64Thursday, April 07, 2011
0.2
0.2
0.2
5
T1801PAD~D @T1801PAD~D @ T1802PAD~D @T1802PAD~D @ T1813PAD~D @T1813PAD~D @ T1803PAD~D @T1803PAD~D @ T1814PAD~D @T1814PAD~D @ T1815PAD~D @T1815PAD~D @ T1804PAD~D @T1804PAD~D @ T1805PAD~D @T1805PAD~D @ T1819PAD~D @T1819PAD~D @ T1806PAD~D @T1806PAD~D @ T1807PAD~D @T1807PAD~D @
T1834PAD~D @T1834PAD~D @
12
T1836PAD~D @T1836PAD~D @ T1835PAD~D @T1835PAD~D @ T1833PAD~D @T1833PAD~D @
T1816PAD~D @T1816PAD~D @ T1820PAD~D @T1820PAD~D @ T1808PAD~D @T1808PAD~D @ T1809PAD~D @T1809PAD~D @ T1817PAD~D @T1817PAD~D @ T1818PAD~D @T1818PAD~D @ T1810PAD~D @T1810PAD~D @ T1811PAD~D @T1811PAD~D @ T1812PAD~D @T1812PAD~D @
T1821PAD~D @T1821PAD~D @ T1822PAD~D @T1822PAD~D @ T1823PAD~D @T1823PAD~D @ T1824PAD~D @T1824PAD~D @
T1825PAD~D @T1825PAD~D @
T1826PAD~D @T1826PAD~D @
T1827PAD~D @T1827PAD~D @
T1828PAD~D @T1828PAD~D @
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
DGPU_HOLD_RST# PCH_GPIO52
DGPU_PWR_EN
PCH_GPIO51 PCH_GPIO53
PCH_WL_OFF#
ODD_DA# DP_CBL_DET PCH_GPIO5
+3VS
PCH_PLTRST#
CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4
D D
USB3_RX1_N47 USB3_RX3_N46
USB3_RX4_N46 USB3_RX1_P47
USB3_RX3_P46 USB3_RX4_P46
USB3_TX1_N47 USB3_TX3_N46
USB3_TX4_N46
CLK_PCI_LPBACK CLK_PCI_LPC
USB3_TX1_P47 USB3_TX3_P46
USB3_TX4_P46
DGPU_PWR_EN27,55,65
PCH_WL_OFF#51
ODD_DA#36 DP_CBL_DET47
RH166 22_0402_5%RH166 22_0402_5% RH167 22_0402_5%RH167 22_0402_5%
1 2
RPH3
RPH3
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
RPH4
RPH4
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
RPH5
RPH5
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
RH175 10K_0402_5%@RH175 10K_0402_5%@
1 2
RH176 10K_0402_5%RH176 10K_0402_5%
1 2
C C
B B
A A
CLK_PCI_LPBACK16
CLK_PCI_LPC49
PCH_WL_OFF# PCI_PIRQB# PCI_PIRQD# PCI_PIRQC#
PCH_GPIO51 PCH_GPIO5
PCH_GPIO52
PCH_GPIO53 PCI_PIRQA#
ODD_DA#
DGPU_HOLD_RST# DGPU_PWR_EN
5
4
UH1E
UH1E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3Tp1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
4
RSVD
RSVD
PCI
PCI
3
AY7
RSVD1
AV7
RSVD2
AU3
RSVD3
BG4
RSVD4
AT10
RSVD5
BC8
RSVD6
AU2
RSVD7
AT4
RSVD8
AT3
RSVD9
AT1
RSVD10
AY3
RSVD11
AT5
RSVD12
AV3
RSVD13
AV1
RSVD14
BB1
RSVD15
BA3
RSVD16
BB5
RSVD17
BB3
RSVD18
BB7
RSVD19
BE8
RSVD20
BD4
RSVD21
BF6
RSVD22 RSVD23
RSVD24 RSVD25 RSVD26
RSVD27 RSVD28
RSVD29
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N
USBP9P USBP10N USBP10P
USB
USB
USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43
OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14
@
@
RH171
RH171
10K_0402_5%
10K_0402_5%
PLT_RST#5,42,47,49,51,52
+3VS
NV_ALE
AV5 AV10
AT8 AY5
BA2 AT12
BF3
USB20_N0
C24
USB20_P0
A24
USB20_N1
C25
USB20_P1
B25
USB20_N2
C26
USB20_P2
A26
USB20_N3
K28
USB20_P3
H28
USB20_N4
E28
USB20_P4
D28
USB20_N5
C28
USB20_P5
A28
C29
B29
N28
M28
USB20_N8
L30
USB20_P8
K30
USB20_N9
G30
USB20_P9
E30
USB20_N10
C30
USB20_P10
A30
USB20_N11
L32
USB20_P11
K32
G32
E32
C32
A32
USBRBIAS
C33
B33
USB_OC0#
A14
USB_OC1#
K20
USB_OC2#
B17
USB_OC3#
C16
USB_OC4#
L16
USB_OC5#
A16
USB_OC6#
D14 C14
UH6
1 2
UH6
12
RH173
RH173 100K_0402_5%
100K_0402_5%
USB20_N0 47 USB20_P0 47 USB20_N1 47 USB20_P1 47 USB20_N2 46 USB20_P2 46 USB20_N3 46 USB20_P3 46 USB20_N4 51 USB20_P4 51 USB20_N5 51 USB20_P5 51
USB20_N8 36,38 USB20_P8 36,38 USB20_N9 46 USB20_P9 46 USB20_N10 47 USB20_P10 47 USB20_N11 46 USB20_P11 46
Within 500 mils
1 2
RH165 22.6_0402_1%RH165 22.6_0402_1%
RH168
RH168
1 2
0_0402_5%
0_0402_5%
@
@
1 2
RH170 0_0402_5%
RH170 0_0402_5%
+3VS
CH30
CH30
1 2
5
VCC
IN1
4
OUT
IN2
GND
3
USB2/3 IO (ESATA+USB COMBO)
USB2/3 left Conn. USB2/3 FPC
BluetoothMini Card(WLAN)
Mini Card(WWAN)
Camera USB Conn. R(light peak) EXPRESS CARD USB Conn. R
USB_OC0# 47 USB_OC1# 46
Issued Date
Issued Date
Issued Date
USB_OC5# 46 ESATA_DETECT# 47
ESATA_DETECT#
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
PCH_PLTRST#
1 2
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
(For USB Port0, 1)
(For USB Port 6,7)
PLTRST_VGA#24
Compal Secret Data
Compal Secret Data
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Compal Secret Data
2
USB_OC0# USB_OC2# ESATA_DETECT# USB_OC5#
USB_OC1# USB_OC4# USB_OC3# USB_OC6#
12
100_0402_5%
100_0402_5%
100K_0402_5%
100K_0402_5%
Deciphered Date
Deciphered Date
Deciphered Date
2
GPIO19 => BBS_BIT0 GPIO51 => BBS_BIT1
Boot BIOS Strap
BBS_BIT1BBS_BIT0
0
0
1
Intel Anti-Theft Techonlogy
NV_ALE
NV_ALE
RH172
RH172
RH174
RH174
0
1
0
11
High=Endabled
Low=Disable(floating)
RH164 1K_0402_5%@ RH164 1K_0402_5%@
1 2
RPH1
RPH1
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
RPH2
RPH2
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
@
@
1 2
RH169 0_0402_5%
RH169 0_0402_5%
+3VS
CH29
CH29
1 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
5
UH7
UH7
PCH_PLTRST#
2
P
B
4
Y
DGPU_HOLD_RST#
1
A
G
12
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
1
Boot BIOS Location
LPC
Reserved(NAND)
Reserved
SPI
*
*
+1.8VS
+3V_PCH
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (4/8) PCI, USB, NVRAM
PCH (4/8) PCI, USB, NVRAM
PCH (4/8) PCI, USB, NVRAM
LA-7391P
LA-7391P
LA-7391P
1
0.2
0.2
0.2
of
of
of
18 64Thursday, April 07, 2011
18 64Thursday, April 07, 2011
18 64Thursday, April 07, 2011
5
+3VS
CRT_DET# ODD_DETECT# PCH_GPIO16 PCH_BT_ON#
D D
C C
KB_RST# PCH_GPIO48 PCH_GPIO22 ODD_EN# DGPU_PWROK
+3VS
@
1 2
UMA@
UMA@
1 2
PCH_GPIO6
RH198
RH198
1 2
RH199 10K_0402_5%@RH199 10K_0402_5%@
1 2
RH200 10K_0402_5%@RH200 10K_0402_5%@
D@
D@
1 2
RH201 10K_0402_5%
RH201 10K_0402_5%
12
RH19010K_0402_5% RH19010K_0402_5% RH19210K_0402_5%@RH19210K_0402_5%
12
RH19310K_0402_5%
RH19310K_0402_5%
12
RH19410K_0402_5% RH19410K_0402_5% RH19510K_0402_5% RH19510K_0402_5%
RH197 10K_0402_5%RH197 10K_0402_5%
1 2
12
100K_0402_5%
100K_0402_5%
PCH_GPIO27
10K_0402_5%@
10K_0402_5%@
1 2
RH177
RH177
200K_0402_5%
200K_0402_5%
1 2
RH178
RH178
10K_0402_5%
10K_0402_5%
1 2
RH179
RH179
10K_0402_5%
10K_0402_5%
1 2
RH180
RH180
10K_0402_5%
10K_0402_5%
1 2
RH184
RH184
10K_0402_5%
10K_0402_5%
1 2
RH181
RH181
10K_0402_5%
10K_0402_5%
1 2
RH185
RH185
10K_0402_5%
10K_0402_5%
1 2
RH183
RH183
10K_0402_5%
10K_0402_5%
1 2
RH186
RH186
PCH_GPIO1 PCH_GPIO37 OPTIMUS_EN# PCH_GPIO39 PCH_GPIO49
+3VS
PCH_GPIO37
PCH_WAN_RADIO_OFF#
OPTIMUS_EN#
PCH_WAN_RADIO_OFF#51
CABC_SAVING38
OPTIMUS_EN# H: Diable optimus
OPTIMUS_EN# L: Enable optimus
+3V_PCH
10K_0402_5%
PCH_GPIO28
B B
HDD2_DETECT#
PCH_GPIO15 EC_SMI#
1 2
RH202
RH202
1 2
RH203
RH203
1 2
RH204
RH204
1 2
RH205
RH205
10K_0402_5%
10K_0402_5%
10K_0402_5%
1K_0402_5%
1K_0402_5% 10K_0402_5%
10K_0402_5%
GPIO28
On-Die PLL Voltage Regulator This signal has a weak internal pull up
On-Die voltage regulator enable
H
*
L烉On-Die PLL Voltage Regulator disable
RH206 1K_0402_5%~D@RH206 1K_0402_5%~D@
1 2
PCH_GPIO28
4
EC_SCI#49 EC_SMI#49
PCH_GPIO1552
DGPU_PWROK55,65
PCH_BT_ON#51
ODD_DETECT#36
RH253 0_0402_5%
RH253 0_0402_5%
12
@
@
HDD2_DETECT#51
CRT_DET PCH_GPIO1 PCH_GPIO6
EC_SMI#
PCH_GPIO15
PCH_GPIO16
DGPU_PWROK PCH_GPIO22
PCH_GPIO27 PCH_GPIO28 PCH_BT_ON#
PCH_WAN_RADIO_OFF#
ODD_DETECT# PCH_GPIO37 OPTIMUS_EN# PCH_GPIO39 PCH_GPIO48 PCH_GPIO49 HDD2_DETECT#
T1907PAD~D @T1907PAD~D @ T1909PAD~D @T1909PAD~D @ T1911PAD~D @T1911PAD~D @ T1913PAD~D @T1913PAD~D @ T1915PAD~D @T1915PAD~D @ T1917PAD~D @T1917PAD~D @ T1919PAD~D @T1919PAD~D @ T1921PAD~D @T1921PAD~D @ T1923PAD~D @T1923PAD~D @ T1925PAD~D @T1925PAD~D @ T1927PAD~D @T1927PAD~D @ T1929PAD~D @T1929PAD~D @ T1931PAD~D @T1931PAD~D @ T1933PAD~D @T1933PAD~D @
UH1F
UH1F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PW R_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
3
ODD_EN#
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4
NC_1
VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32
C40 B41 C41 A40
P4 AU16 P5 AY11 AY10 T14 AY1
AH8 AK11 AH10 AK10
P37
BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49
GPIO69 GPIO70 GPIO71
PCH_PECI_R
H_THERMTRIP#_C
INIT3_3V#
NV_CLE
T1902 PAD~D@ T1902 PAD~D@
T1903 PAD~D@ T1903 PAD~D@ T1904 PAD~D@ T1904 PAD~D@ T1905 PAD~D@ T1905 PAD~D@ T1906 PAD~D@ T1906 PAD~D@ T1908 PAD~D@ T1908 PAD~D@ T1910 PAD~D@ T1910 PAD~D@ T1912 PAD~D@ T1912 PAD~D@ T1914 PAD~D@ T1914 PAD~D@ T1916 PAD~D@ T1916 PAD~D@ T1918 PAD~D@ T1918 PAD~D@ T1920 PAD~D@ T1920 PAD~D@ T1922 PAD~D@ T1922 PAD~D@ T1924 PAD~D@ T1924 PAD~D@ T1926 PAD~D@ T1926 PAD~D@ T1928 PAD~D@ T1928 PAD~D@ T1930 PAD~D@ T1930 PAD~D@ T1932 PAD~D@ T1932 PAD~D@ T1934 PAD~D@ T1934 PAD~D@
T1935 PAD~D@ T1935 PAD~D@ T1936 PAD~D@ T1936 PAD~D@ T1901 PAD~D@ T1901 PAD~D@
A20M#
1 2
KB_RST# 49 H_CPUPWRGD 5
1 2
@
RH1880_0402_5%@RH1880_0402_5%
TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71
GPIO
GPIO
CPU/MISC
CPU/MISC
NCTF
NCTF
PCH_GPIO28 needs to be connected to XDP_FN8 PCH_GPIO35 needs to be connected to XDP_FN9 PCH_GPIO15 needs to be connected to XDP_FN16
Please refer to Huron River Debug Board DG 1.2
ODD_EN# 36
RH191390_0402_5% RH191390_0402_5%
12
@
@
RH196
RH196 10K_0402_5%
10K_0402_5%
2
+3VS
@
@
RH182
RH182 10K_0402_5%
10K_0402_5%
1 2
H_PECI 5,49
H_THERMTRIP#
INIT3_3V
This signal has weak internal PU, can't pull low
H_THERMTRIP# 5
1
DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
Weak internal PU,Do not pull low
NV_CLE
RH187
RH187
2.2K_0402_5%
2.2K_0402_5%
12
RH1891K_0402_5% RH1891K_0402_5%
+1.8VS
CLOSE TO THE BRANCHING POINT
RH149 and RH150 Follow CRB FAB2 setting
12
H_SNB_IVB# 5
+3VS
RH207
High: CRT Plug g e d
A A
CRT_DET
CRT_DET#37
RH207 10K_0402_5%
10K_0402_5%
1 2 13
D
D
QH5
QH5
2
G
2N7002_SOT23-3
G
2N7002_SOT23-3
S
S
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (5/8) GPIO, CPU, MISC
PCH (5/8) GPIO, CPU, MISC
PCH (5/8) GPIO, CPU, MISC
LA-7391P
LA-7391P
LA-7391P
1
19 64Thursday, April 07, 2011
19 64Thursday, April 07, 2011
19 64Thursday, April 07, 2011
of
of
of
0.2
0.2
0.2
5
4
3
2
1
+V1.05S
PJPH1
PJPH1
12
PAD-OPEN 4x4m
PAD-OPEN 4x4m
@
D D
+V1.05S
@
+V1.05S
+VCCAPLLEXP_R
@
@
12
RH210 0_0603_5%~D
RH210 0_0603_5%~D
1
10U_0805_6.3V6M
10U_0805_6.3V6M
2
RH209 0_0603_5%~DRH209 0_0603_5%~D
1 2
1UH_LB2012T1R0M_20%~D
1UH_LB2012T1R0M_20%~D
Place C2011 Near BJ22 pin
+V1.05S
12
RH212
RH212
0_0805_5%
C C
+V1.05S
B B
0_0805_5%
+3VS
12
1
2
RH217 0_0603_5%~D
RH217 0_0603_5%~D
CH43
CH43
10U_0805_6.3V6M
10U_0805_6.3V6M
RH215
RH215 0_0805_5%
0_0805_5%
+3VS_VCCA3GBG
CH50
CH50
0.1U_0402_10V7K
0.1U_0402_10V7K
Place CH53 Near BG6 pin
@
@
12
1
1
2
2
1
CH52
CH52
2
@
@
1
CH32
CH32
CH31
CH31
2
12
LH3
@LH3
@
+1.05VS_VCC_EXP
1
CH45
CH45
CH44
CH44
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+V1.05S
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+1.05VS_VCCCORE
1
CH33
CH33
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+1.05VS_VCCDPLLEXP
1
@
@
2
+1.05VS_VCC_EXP
1
1
CH46
CH46
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+1.05VS_VCCAPLL_FDI
RH218
RH218
+1.05VS_VCCDPLL_FDI
1 2
0_0805_5%
0_0805_5%
+VCCP_VCCDMI
1
CH34
CH34
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+VCCAPLLEXP
CH41
CH41 10U_0805_6.3V6M
10U_0805_6.3V6M
CH47
CH47
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+VCCAFDI_VRM
UH1G
UH1G
1300mA
AA23
VCCCORE[1]
AC23
VCCCORE[2]
AD21
VCCCORE[3]
AD23
VCCCORE[4]
AF21
VCCCORE[5]
AF23
VCCCORE[6]
AG21
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9]
AG26
VCCCORE[10]
AG27
VCCCORE[11]
AG29
VCCCORE[12]
AJ23
VCCCORE[13]
AJ26
VCCCORE[14]
AJ27
VCCCORE[15]
AJ29
VCCCORE[16]
AJ31
VCCCORE[17]
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VccAFDIPLL
AP17
VCCIO[27]
AU20
VCCDMI[2]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
POWER
POWER
3709mA
CRTLVDS
CRTLVDS
VCC CORE
VCC CORE
40mA
75mA
DMI
DMI
VCCIO
VCCIO
2mA
DFT / SPI HVCMOS
DFT / SPI HVCMOS
FDI
FDI
1mA
VCCADAC
VSSADAC
1mA
VCCALVDS
VSSALVDS
VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
10mA
VCCSPI
+VCCADAC
U48
U47
+VCCA_LVDS
AK36 AK37
AM37 AM38 AP36 AP37
+3VS_VCC3_3_6
V33
V34
+VCCAFDI_VRM
AT16
+VCCP_VCCDMI
AT20
+1.05VS_VCC_DMI_CCI
AB36
AG16
AG17
AJ16
AJ17
+3V_VCCPSPI
V1
1
CH35
CH35
2
+VCCTX_LVDS
CH38
CH38
0.01U_0402_16V7K
0.01U_0402_16V7K
1
CH42
CH42
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
CH51
CH51
2
1
CH53
CH53 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
2
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
RH211
RH211
1 2
0_0805_5%
0_0805_5%
1
CH49
CH49 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+VCCPNAND
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
BLM18PG181SN1_0603~D
BLM18PG181SN1_0603~D
1
CH37
CH37 10U_0805_6.3V6M
10U_0805_6.3V6M
CH36
CH36
2
0.1U_0402_10V7K
0.1U_0402_10V7K RH208 0_0805_5%RH208 0_0805_5%
Near AP43
1
CH39
CH39
0.01U_0402_16V7K
0.01U_0402_16V7K
2
+3VS
+VCCP_VCCDMI
RH214
RH214
1 2
0_0805_5%
0_0805_5%
1 2
RH216 0_0805_5%~DRH216 0_0805_5%~D
@
@
1 2
RH219 0_0805_5%
RH219 0_0805_5%
RH220 0_0603_5%RH220 0_0603_5%
LH1
LH1
12
1 2
CH40
CH40
1
22U_0805_6.3V6M
22U_0805_6.3V6M
2
+V1.05S
+1.8VS
+3V_PCH
12
+3VS
+3VS
LH2
LH2
0.1UH_MLF1608DR10KT_10%_1608
0.1UH_MLF1608DR10KT_10%_1608
0.1uH inductor, 200mA
RH213
RH213
1 2
1
0_0805_5%
0_0805_5%
CH48
CH48
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+3VS
+1.8VS
12
+V1.05S_VCCP
PCH Power Rail Table Refer to CPU EDS R1.5
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1.05
1.05
1.05
1.05
S0 Iccmax Current (A)
0.001
5
5
0.001
0.001
0.228
0.001
0.075
0.075
1.3
0.042
1.05VccIO 3.709
1.05VccASW 0.903
3.3VccSPI 0.01
3.3VccDSW 0.001
1.8 0.002VccDFTERM
3.3VccRTC 6 uA
3.3VccSus3_3
3.3 / 1.5VccSusHDA
0.065
0.01
VccVRM 1.8 / 1.5 0.167
1.05VccCLKDMI
0.075
VccSSC 1.05 0.095
VccDIFFCLKN 1.05 0.055
VccALVDS 3.3
0.001
1.8VccTX_LVDS 0.04
+1.5VS
RH221
RH221
+VCCAFDI_VRM
+1.8VS
@RH222
@
0_0603_5%~D
0_0603_5%~D
A A
5
4
Intel recommand stuff R2012 and unstuff R2013
12
0_0603_5%~D
0_0603_5%~D
12
RH222
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+VCCAFDI_VRM
VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP
Compal Secret Data
Compal Secret Data
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PCH (6/8) PWR
PCH (6/8) PWR
PCH (6/8) PWR
LA-7391P
LA-7391P
LA-7391P
1
of
of
of
20 64Thursday, April 07, 2011
20 64Thursday, April 07, 2011
20 64Thursday, April 07, 2011
0.2
0.2
0.2
5
4
3
2
1
+V1.05S
+3V_PCH
1 2
RH224 0_0603_5%~DRH224 0_0603_5%~D
D D
+V1.05S
C C
+3VS
B B
A A
+V1.05S
@ RH226
@
1 2
0_0805_5%~D
0_0805_5%~D
+V1.05S
RH243 0_0603_5%
RH243 0_0603_5%
+V1.05S
+V1.05S
+V1.05S
1 2
RH252
RH252
0_0805_5%~D
0_0805_5%~D
RH226
+VCCAPLL_CPY +3VS_VCC_CLKF33
RH239 0_0805_5%~DRH239 0_0805_5%~D
1 2
@
@
12
+V1.05S_VCCP
+VCCA_DPLL_L
5
12
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
RH244 0_0603_5%RH244 0_0603_5%
LH4
@LH4
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
@
@
+V1.05S
LH5
LH5
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
@
@
+1.05VM_VCCSUS
1
CH79
CH79 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
12
RH247 0_0603_5%RH247 0_0603_5%
12
RH248 0_0603_5%RH248 0_0603_5%
1 2
RH249 0_0603_5%~DRH249 0_0603_5%~D
LH7
LH7
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
1 2
LH8
LH8
1
CH59
CH59
2
DcpSus and DcpSusByp do not require Decoupling. Stuffing Decoupling Caps may cause voltage oscillations, when Internal 1.05 Voltage Regulator is used. By CPET
1 2
RH235 0_0805_5%~DRH235 0_0805_5%~D
+VCCDIFFCLK
1
2
1
CH84
CH84 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
1
+
+
2
1
CH55
CH55
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+V1.05S
1 2
RH231 0_0603_5%~DRH231 0_0603_5%~D
22U_0805_6.3V6M
22U_0805_6.3V6M
+3VS_VCC_CLKF33
1
1
CH73
CH73
CH74
CH74
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
+1.05VS_VCCDIFFCLKN
CH81
CH81 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH86
CH86
+V_CPU_IO
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
1
CH93
CH93
CH94
CH94
2
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
+1.05VS_VCCDIFFCLKN
1
2
1
2
1
+
+
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CH64
CH64
+1.05VS_SSCVCC
CH85
CH85
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CH95
CH95
@
@
RH223 0_0603_5%
RH223 0_0603_5%
CH58
@CH58
@
1
2
1
CH67
CH67
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH78
CH78
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
CH87
CH87
CH88
CH88
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH96
CH96
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
12
1
2
1
CH65
CH65 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
CH68
CH68
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+VCCRTCEXT
1
@
@
CH83
CH83 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+RTCVCC
4
+VCCACLK
+VCCPDSW
+PCH_VCCDSW
+VCCAPLL_CPY_PCH
+VCCDPLL_CPY
+VCCSUS1
1
@
@
CH54
CH54 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+1.05VM_VCCASW
1
CH69
CH69
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+VCCAFDI_VRM
+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL
+VCCSST
+1.05VM_VCCSUS
1
1
CH90
CH90
CH89
CH89
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
UH1J
UH1J
AD49
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3[5]
BH23
VCCAPLLDMI2
AL29
VCCIO[14]
AL24
DCPSUS[3]
AA19
VCCASW[1]
AA21
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD29
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
N16
DCPRTC
Y49
VCCVRM[4]
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO[7]
AF33
VCCDIFFCLKN[1]
AF34
VCCDIFFCLKN[2]
AG34
VCCDIFFCLKN[3]
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS[1]
V19
DCPSUS[2]
BJ8
V_PROC_IO
A22
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
VCCRTC
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
CH91
CH91
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
POWER
POWER
N26
VCCIO[29]
P26
1mA
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
10mA
HDA
HDA
3
VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]
VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCIO[34]
V5REF_SUS
DCPSUS[4]
VCCSUS3_3[1]
V5REF
1mA
VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5]
VCC3_3[1] VCC3_3[8] VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12] VCCIO[13]
VCCIO[6]
VCCAPLLSATA
VCCVRM[1]
VCCIO[2] VCCIO[3] VCCIO[4]
VCCASW[22]
VCCASW[23]
VCCASW[21]
VCCSUSHDA
P28 T27 T29
T23 T24 V23 V24 P24
T26
M26
AN23 AN24
P34
N20 N22 P20 P22
AA16 W16 T34
AJ2
AF13
AH13 AH14
AF14 AK1
AF11
AC16 AC17 AD17
T21
V21
T19
P32
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
3mA
119mA
903mA
Clock and Miscellaneous
Clock and Miscellaneous
75mA
75mA
55mA
95mA
1mA
CPURTC
CPURTC
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.05VS_VCCUSBCORE
1
CH56
CH56 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+3V_VCCPUSB
1
CH60
CH60
2
+1.05VS_VCCAUPLL
+PCH_V5REF_SUS
+VCCA_USBSUS
+3V_VCCPSUS
+PCH_V5REF_RUN
1
CH70
CH70 1U_0402_6.3V
1U_0402_6.3V
2
+3VS_VCCPPCI
+VCC3_3_2
+VCCAFDI_VRM
+VCCAFDI_VRM
+1.05VS_VCC_SATA
+VCCME_22
+VCCME_23
+VCCME_21
+VCCSUSHDA
1
CH92
CH92
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
Compal Secret Data
Compal Secret Data
Compal Secret Data
+3V_VCCAUBG
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
RH233 0_0603_5%~DRH233 0_0603_5%~D
+3V_VCCPSUS
+3VS_VCCPCORE
RH241
RH241
1
0_0603_5%~D
0_0603_5%~D
CH76
CH76
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+1.05VS_SATA3
+VCCSATAPLL
+1.05VS_VCC_SATA
@
@
RH251
RH251
Deciphered Date
Deciphered Date
Deciphered Date
RH225 0_0603_5%~DRH225 0_0603_5%~D
1
CH61
CH61
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
12
12
150_0402_1%
150_0402_1%
12
RH229 0_0603_5%~DRH229 0_0603_5%~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
1
2
+3VS
1
2
RH250 0_0402_5%RH250 0_0402_5%
12
RH230 0_0603_5%~DRH230 0_0603_5%~D
12
CH66
CH66
RH236
RH236 0_0603_5%~D
0_0603_5%~D
RH238 0_0805_5%~DRH238 0_0805_5%~D
CH72
CH72
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
+1.05VS_SATA3
RH246
RH246
0_0805_5%~D
0_0805_5%~D
CH82
CH82
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2
2
CH75
CH75
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
+V1.05S
+3V_PCH
12
+VCCA_USBSUS
+V1.05S
12
+3V_PCH
+3VS
12
RH240 0_0603_5%RH240 0_0603_5%
12
+V1.05S
12
RH242
RH242
0_0805_5%~D
0_0805_5%~D
CH77
CH77 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+V1.05S
+3V_PCH
12
JPH1
@JPH1
@
2 1
PAD-OPEN 2x2m
PAD-OPEN 2x2m
+3V_PCH
RH232
RH232
10_0402_5%
1
2
+3VS
+V1.05S
LH6
@LH6
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
1
CH80
@CH80
@
10U_0805_10V4Z~D
10U_0805_10V4Z~D
Place C2127 Near AK1 pin
2
If it support 3.3V audio signals POP:R2130 (0ohm)
If it support 1.5V audio signals POP:R2130 (180 ohm)/R2131 (150 ohm)
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
10_0402_5%
CH62
@ CH62
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
RH237
RH237
10_0402_5%
10_0402_5%
+VCCSATAPLL_R
Compal Electronics, Inc.
PCH (7/8) PWR
PCH (7/8) PWR
PCH (7/8) PWR
LA-7391P
LA-7391P
LA-7391P
1
2
+3V_PCH+5V_PCH
1 2
+3VS+5VS
1 2
@
@
RH245
RH245
12
0_0805_5%~D
0_0805_5%~D
1
CH57
CH57
21
1
2
21
1
2
+5V_PCH+5VALW
12
RH228
RH228
20K_0402_5%~D
20K_0402_5%~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DH3
DH3 RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+PCH_V5REF_SUS
CH63
CH63
0.1U_0603_25V7K
0.1U_0603_25V7K
DH4
DH4 RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+PCH_V5REF_RUN
CH71
CH71 1U_0603_10V6K~D
1U_0603_10V6K~D
+V1.05S
of
of
of
21 64Thursday, April 07, 2011
21 64Thursday, April 07, 2011
21 64Thursday, April 07, 2011
0.2
0.2
0.2
5
UH1H
D D
C C
B B
A A
UH1H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
4
VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]
VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]
AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28
3
UH1I
UH1I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]
H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28
2
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL
THIS SHEET OF ENGINEER I N G D R AW ING IS THE PROPRIETARY PR OPER T Y OF C OMPAL ELECTRONICS, INC . AN D C ON T AINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2011/12/31
2009/12/01 2011/12/31
2009/12/01 2011/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
PCH (8/8) VSS
PCH (8/8) VSS
PCH (8/8) VSS
LA-7391P
LA-7391P
LA-7391P
1
0.2
0.2
0.2
of
of
of
22 64Thursday, April 07, 2011
22 64Thursday, April 07, 2011
22 64Thursday, April 07, 2011
5
D D
Under GPU(below 150mils)
BLM18PG330SN1D_0603
BLM18PG330SN1D_0603
+1.05VS_DGPU
C C
B B
A A
1 2
LV1
LV1
27M_SSC16
1 2
RV105 10M _0402_5%RV105 10M_0402_5%
XTALIN XTAL_OUT
27MHZ_16PF_X5H027000FG1H
27MHZ_16PF_X5H027000FG1H
1
CV38
CV38 18P_0402_50V8J
18P_0402_50V8J
2
1 2
RV101 0_0402_5%
RV101 0_0402_5%
YV1
YV1
1 2
5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV1
CV1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
1
CV39
CV39 18P_0402_50V8J
18P_0402_50V8J
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV2
CV2
1
CV3
CV3
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCIE_GTX_C_CRX_P0 PCIE_GTX_C_CRX_N0 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_N4 PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_N5 PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_N6 PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_N7 PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_N15
Differential signal
XTALSSIN
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV4
CV4
2
PLTRST_VGA#18
27M_CLK16
RV108
RV108
10K_0402_5%
10K_0402_5%
4
150mA
+PLLVDD
2
CV5
CV5
1
CV6 0.22U_0402_10V6KCV6 0.22U_0402_10V6K
1 2
CV7 0.22U_0402_10V6KCV7 0.22U_0402_10V6K
1 2
CV8 0.22U_0402_10V6KCV8 0.22U_0402_10V6K
1 2
CV9 0.22U_0402_10V6KCV9 0.22U_0402_10V6K
1 2
CV10 0.22U_0402_10V6KCV10 0.22U_0402_10V6K
1 2
CV11 0.22U_0402_10V6KCV11 0.22U_0402_10V6K
1 2
CV12 0.22U_0402_10V6KCV12 0.22U_0402_10V6K
1 2
CV13 0.22U_0402_10V6KCV13 0.22U_0402_10V6K
1 2
CV14 0.22U_0402_10V6KCV14 0.22U_0402_10V6K
1 2
CV15 0.22U_0402_10V6KCV15 0.22U_0402_10V6K
1 2
CV16 0.22U_0402_10V6KCV16 0.22U_0402_10V6K
1 2
CV17 0.22U_0402_10V6KCV17 0.22U_0402_10V6K
1 2
CV18 0.22U_0402_10V6KCV18 0.22U_0402_10V6K
1 2
CV19 0.22U_0402_10V6KCV19 0.22U_0402_10V6K
1 2
CV20 0.22U_0402_10V6KCV20 0.22U_0402_10V6K
1 2
CV21 0.22U_0402_10V6KCV21 0.22U_0402_10V6K
1 2
CV22 0.22U_0402_10V6KCV22 0.22U_0402_10V6K
1 2
CV23 0.22U_0402_10V6KCV23 0.22U_0402_10V6K
1 2
CV24 0.22U_0402_10V6KCV24 0.22U_0402_10V6K
1 2
CV25 0.22U_0402_10V6KCV25 0.22U_0402_10V6K
1 2
CV26 0.22U_0402_10V6KCV26 0.22U_0402_10V6K
1 2
CV27 0.22U_0402_10V6KCV27 0.22U_0402_10V6K
1 2
CV28 0.22U_0402_10V6KCV28 0.22U_0402_10V6K
1 2
CV29 0.22U_0402_10V6KCV29 0.22U_0402_10V6K
1 2
CV30 0.22U_0402_10V6KCV30 0.22U_0402_10V6K
1 2
CV31 0.22U_0402_10V6KCV31 0.22U_0402_10V6K
1 2
CV32 0.22U_0402_10V6KCV32 0.22U_0402_10V6K
1 2
CV33 0.22U_0402_10V6KCV33 0.22U_0402_10V6K
1 2
CV34 0.22U_0402_10V6KCV34 0.22U_0402_10V6K
1 2
CV35 0.22U_0402_10V6KCV35 0.22U_0402_10V6K
1 2
CV36 0.22U_0402_10V6KCV36 0.22U_0402_10V6K
1 2
CV37 0.22U_0402_10V6KCV37 0.22U_0402_10V6K
1 2
CLK_PCIE_VGA16
CLK_PCIE_VGA#16
PEG_CLKREQ#16
1 2
RV100 200_0402_1%RV100 200_0402_1%
1 2
RV103 0_0402_5%RV103 0_0402_5%
1 2
RV104 2.49K_0402_1%RV104 2.49K_0402_1%
+PLLVDD
@
@
RV106 0_0402_5%
RV106 0_0402_5%
1 2
12
Internal Thermal Sensor
SMB_CLK_GPU25 SMB_DATA_GPU25
LVDS
VGA_LCD_CLK38 VGA_LCD_DATA38
CRT
4
3
UV1A
PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15
PCIE_GTX_CRX_P0 PCIE_GTX_CRX_N0 PCIE_GTX_CRX_P1 PCIE_GTX_CRX_N1 PCIE_GTX_CRX_P2 PCIE_GTX_CRX_N2 PCIE_GTX_CRX_P3 PCIE_GTX_CRX_N3 PCIE_GTX_CRX_P4 PCIE_GTX_CRX_N4 PCIE_GTX_CRX_P5 PCIE_GTX_CRX_N5 PCIE_GTX_CRX_P6 PCIE_GTX_CRX_N6 PCIE_GTX_CRX_P7 PCIE_GTX_CRX_N7 PCIE_GTX_CRX_P8 PCIE_GTX_CRX_N8 PCIE_GTX_CRX_P9 PCIE_GTX_CRX_N9 PCIE_GTX_CRX_P10 PCIE_GTX_CRX_N10 PCIE_GTX_CRX_P11 PCIE_GTX_CRX_N11 PCIE_GTX_CRX_P12 PCIE_GTX_CRX_N12 PCIE_GTX_CRX_P13 PCIE_GTX_CRX_N13 PCIE_GTX_CRX_P14 PCIE_GTX_CRX_N14 PCIE_GTX_CRX_P15 PCIE_GTX_CRX_N15
CLK_PCIE_VGA CLK_PCIE_VGA# PEG_CLKREQ#
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
PLTRST_VGA_R#
60mA 45mA 45mA
XTALIN XTAL_OUT
XTALOUT
XTALSSIN
12
RV107 10K_0402_5%RV107 10K_0402_5%
SMB_CLK_GPU SMB_DATA_GPU
VGA_LCD_CLK VGA_LCD_DATA
I2CB_SCL I2CB_SDA
VGA_DDC_CLK VGA_DDC_DATA
HDCP_SCL HDCP_SDA
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER I NG DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECT R ONICS, INC. AND C ONTAINS CONFIDENT I AL
THIS SHEET OF ENGINEER I NG DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECT R ONICS, INC. AND C ONTAINS CONFIDENT I AL
THIS SHEET OF ENGINEER I NG DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECT R ONICS, INC. AND C ONTAINS CONFIDENT I AL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
UV1A
AP17
PEX_RX0
AN17
PEX_RX0_N
AN19
PEX_RX1
AP19
PEX_RX1_N
AR19
PEX_RX2
AR20
PEX_RX2_N
AP20
PEX_RX3
AN20
PEX_RX3_N
AN22
PEX_RX4
AP22
PEX_RX4_N
AR22
PEX_RX5
AR23
PEX_RX5_N
AP23
PEX_RX6
AN23
PEX_RX6_N
AN25
PEX_RX7
AP25
PEX_RX7_N
AR25
PEX_RX8
AR26
PEX_RX8_N
AP26
PEX_RX9
AN26
PEX_RX9_N
AN28
PEX_RX10
AP28
PEX_RX10_N
AR28
PEX_RX11
AR29
PEX_RX11_N
AP29
PEX_RX12
AN29
PEX_RX12_N
AN31
PEX_RX13
AP31
PEX_RX13_N
AR31
PEX_RX14
AR32
PEX_RX14_N
AR34
PEX_RX15
AP34
PEX_RX15_N
AL17
PEX_TX0
AM17
PEX_TX0_N
AM18
PEX_TX1
AM19
PEX_TX1_N
AL19
PEX_TX2
AK19
PEX_TX2_N
AL20
PEX_TX3
AM20
PEX_TX3_N
AM21
PEX_TX4
AM22
PEX_TX4_N
AL22
PEX_TX5
AK22
PEX_TX5_N
AL23
PEX_TX6
AM23
PEX_TX6_N
AM24
PEX_TX7
AM25
PEX_TX7_N
AL25
PEX_TX8
AK25
PEX_TX8_N
AL26
PEX_TX9
AM26
PEX_TX9_N
AM27
PEX_TX10
AM28
PEX_TX10_N
AL28
PEX_TX11
AK28
PEX_TX11_N
AK29
PEX_TX12
AL29
PEX_TX12_N
AM29
PEX_TX13
AM30
PEX_TX13_N
AM31
PEX_TX14
AM32
PEX_TX14_N
AN32
PEX_TX15
AP32
PEX_TX15_N
AR16
PEX_REFCLK
AR17
PEX_REFCLK_N
AR13
PEX_CLKREQ_N
AJ17
PEX_TSTCLK_OUT
AJ18
PEX_TSTCLK_OUT_N
AM16
PEX_RST_N
AG21
PEX_TERMP
AE9
PLLVDD
AF9
SP_PLLVDD
AD9
VID_PLLVDD
B1
XTAL_IN
B2
XTAL_OUT
D1
XTAL_OUTBUFF
D2
XTAL_SSIN
E2
I2CS_SCL
E1
I2CS_SDA
E3
I2CC_SCL
E4
I2CC_SDA
G3
I2CB_SCL
G2
I2CB_SDA
G1
I2CA_SCL
G4
I2CA_SDA
F6
I2CH_SCL
G6
I2CH_SDA
N12P-GE-A1_BGA973
N12P-GE-A1_BGA973
Part 1 of 7
Part 1 of 7
GPIO
GPIO
MIOA_D0_NC MIOA_D1_NC MIOA_D2_NC MIOA_D3_NC MIOA_D4_NC MIOA_D5_NC MIOA_D6_NC MIOA_D7_NC MIOA_D8_NC
MIOA_D9_NC MIOA_D10_NC MIOA_D11_NC MIOA_D12_NC MIOA_D13_NC MIOA_D14_NC
DVO
DVO
MIOB_D0_NC
MIOB_D1_NC
MIOB_D2_NC
MIOB_D3_NC
PCI EXPRESS
PCI EXPRESS
MIOB_D4_NC
MIOB_D5_NC
MIOB_D6_NC
MIOB_D7_NC
MIOB_D8_NC
MIOB_D9_NC MIOBD_10_NC MIOB_D11_NC MIOB_D12_NC MIOB_D13_NC MIOB_D14_NC
MIOA_HSYNC_NC
MIOA_VSYNC_NC
MIOB_HSYNC_NC
MIOB_VSYNC_NC
MIOA_DE_NC MIOA_CTL3_NC MIOA_VREF_NC
MIOB_DE_NC MIOB_CTL3_NC MIOB_VREF_NC
MIOA_CLKIN_NC
MIOA_CLKOUT_NC
MIOB_CLKIN_NC
MIOB_CLKOUT_NC
MIOA_CLKOUT_NC_N MIOB_CLKOUT_NC_N
MIOA_CAL_PD_VDDQ_NC
MIOA_CAL_PU_GND_NC
MIOB_CAL_PD_VDDQ_NC
MIOB_CAL_PU_GND_NC
CLK
CLK
DACA_GREEN
DACA_BLUE
DACA_HSYNC DACA_VSYNC
DACA_VREF DACA_RSET
DACB_GREEN
DACB_BLUE
DACB_HSYNC
DACs
DACs
I2C
I2C
DACB_VSYNC
DACB_VREF DACB_RSET
Compal Secret Data
Compal Secret Data
2010/05/27 2011/05/11
2010/05/27 2011/05/11
2010/05/27 2011/05/11
3
Compal Secret Data
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24
DACA_RED
DACA_VDD
DACB_RED
DACB_VDD
Deciphered Date
Deciphered Date
Deciphered Date
K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 M7
N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6
Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6
N3 L3
W1 W2
N2 P5 N5
Y5 W3 AF1
N4 R4
AE1 V4
T4 W4
U5 T5
AA7 AA6
AM15 AM14 AL14
AM13 AL13
AJ12 AK12 AK13
AK4 AL4 AJ4
AM1 AM2
AG7 AK6 AH7
+DACB_VDD
VGA_GPIO1 VGA_PNL_PWM DGPU_ENVDD DGPU_BKL_EN GPU_VID0 GPU_VID1
GPU_OVERT# THERM#_VGA
GPIO12
10K_0402_5%
10K_0402_5%
GPU_OVERT#
RV99 10K_0402_5%RV99 10K_0402_5%
RV102 10K_0402_5%RV102 10K_0402_5%
+DACA_VDD
124_0402_1%@
124_0402_1%@
2
T2401@T2401@
RV85
RV85
1 2
1 2
1 2
T2402@T2402 T2403@T2403 T2404@T2404
T2405@T2405 T2406@T2406
RV109 10K_0402_5%RV109 10K_0402_5%
12
RV272
RV272
RV110 10K_0402_5%RV110 10K_0402_5%
2
VGA_PNL_PWM 38 DGPU_ENVDD 38 DGPU_BKL_EN 49 GPU_VID0 65 GPU_VID1 65
THERM#_VGA 25
+3VS_DGPU
G
G
2
13
D
S
D
S
QV1
QV1 2N7002_SOT23-3
2N7002_SOT23-3
120mA
@ @ @
@ @
12
1
CV277
CV277
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
2
12
1
PCIE_GTX_C_CRX_P[0..15]4
PCIE_GTX_C_CRX_N[0..15]4
PCIE_CTX_C_GRX_P[0..15]4
PCIE_CTX_C_GRX_N[0..15]4
TH_OVERT# 49
GPIO12 VGA_LCD_CLK VGA_LCD_DATA
SMB_CLK_GPU SMB_DATA_GPU THERM#_VGA HDCP_SCL HDCP_SDA VGA_DDC_DATA VGA_DDC_CLK I2CB_SCL I2CB_SDA
DGPU_ENVDD DGPU_BKL_EN VGA_PNL_PWM
VGA_GPIO1
PCIE_GTX_C_CRX_P[0..15]
PCIE_GTX_C_CRX_N[0..15]
PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_N[0..15]
1 2
RV82 10K_0402_5%RV82 10K_0402_5%
1 2
RV83 2.2K_0402_5%RV83 2.2K_0402_5%
1 2
RV84 2.2K_0402_5%RV84 2.2K_0402_5%
1 2
RV86 2.2K_0402_5%RV86 2.2K_0402_5%
1 2
RV87 2.2K_0402_5%RV87 2.2K_0402_5%
1 2
RV88 100K_0402_5%RV88 100K_0402_5%
1 2
RV89 2.2K_0402_5%RV89 2.2K_0402_5%
1 2
RV90 2.2K_0402_5%RV90 2.2K_0402_5%
1 2
RV91 2.2K_0402_5%RV91 2.2K_0402_5%
1 2
RV92 2.2K_0402_5%RV92 2.2K_0402_5%
1 2
RV93 2.2K_0402_5%RV93 2.2K_0402_5%
1 2
RV94 2.2K_0402_5%RV94 2.2K_0402_5%
1 2
RV95 10K_0402_5%DIS@RV95 10K_0402_5%DIS@ RV96 10K_0402_5%DIS@RV96 10K_0402_5%DIS@ RV97 10K_0402_5%DIS@RV97 10K_0402_5%DIS@
1 2
RV98 100K_0402_5%RV98 100K_0402_5%
20MIL
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
VGA(1/12)-PCIE/DAC/GPIO
VGA(1/12)-PCIE/DAC/GPIO
VGA(1/12)-PCIE/DAC/GPIO
LA-7391P
LA-7391P
LA-7391P
1
+3VS_DGPU
12 12
0.2
0.2
0.2
of
24 64Thursday, April 07, 2011
of
24 64Thursday, April 07, 2011
of
24 64Thursday, April 07, 2011
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