Compal LA-7241P P4LS0, ID47H, EasyNote NX69 Schematic
5
4
3
2
1
D D
+1.05VS_VCCP
12
R419
R419
24.9_0402_1%
JCPU1A
JCPU1A
EDP_COMP
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
CONN@
CONN@
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
C C
+1.05VS_VCCP
eDP_COMPIO and ICOMPO signals
B B
should be shorted near balls
and routed with typical
impedance <25 mohms
12
R106
R106
24.9_0402_1%
24.9_0402_1%
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
J21
H22
PEG_GTX_C_HRX_N15
K33
PEG_GTX_C_HRX_N14
M35
PEG_GTX_C_HRX_N13
L34
PEG_GTX_C_HRX_N12
J35
PEG_GTX_C_HRX_N11
J32
PEG_GTX_C_HRX_N10
H34
PEG_GTX_C_HRX_N9
H31
PEG_GTX_C_HRX_N8
G33
PEG_GTX_C_HRX_N7
G30
PEG_GTX_C_HRX_N6
F35
PEG_GTX_C_HRX_N5
E34
PEG_GTX_C_HRX_N4
E32
PEG_GTX_C_HRX_N3
D33
PEG_GTX_C_HRX_N2
D31
PEG_GTX_C_HRX_N1
B33
PEG_GTX_C_HRX_N0
C32
PEG_GTX_C_HRX_P15
J33
PEG_GTX_C_HRX_P14
L35
PEG_GTX_C_HRX_P13
K34
PEG_GTX_C_HRX_P12
H35
PEG_GTX_C_HRX_P11
H32
PEG_GTX_C_HRX_P10
G34
PEG_GTX_C_HRX_P9
G31
PEG_GTX_C_HRX_P8
F33
PEG_GTX_C_HRX_P7
F30
PEG_GTX_C_HRX_P6
E35
PEG_GTX_C_HRX_P5
E33
PEG_GTX_C_HRX_P4
F32
PEG_GTX_C_HRX_P3
D34
PEG_GTX_C_HRX_P2
E31
PEG_GTX_C_HRX_P1
C33
PEG_GTX_C_HRX_P0
B32
PEG_HTX_GRX_N15
M29
PEG_HTX_GRX_N14
M32
PEG_HTX_GRX_N13
M31
PEG_HTX_GRX_N12
L32
PEG_HTX_GRX_N11
L29
PEG_HTX_GRX_N10
K31
PEG_HTX_GRX_N9
K28
PEG_HTX_GRX_N8
J30
PEG_HTX_GRX_N7
J28
PEG_HTX_GRX_N6
H29
PEG_HTX_GRX_N5
G27
PEG_HTX_GRX_N4
E29
PEG_HTX_GRX_N3
F27
PEG_HTX_GRX_N2
D28
PEG_HTX_GRX_N1
F26
PEG_HTX_GRX_N0
E25
PEG_HTX_GRX_P15
M28
PEG_HTX_GRX_P14
M33
PEG_HTX_GRX_P13
M30
PEG_HTX_GRX_P12
L31
PEG_HTX_GRX_P11
L28
PEG_HTX_GRX_P10
K30
PEG_HTX_GRX_P9
K27
PEG_HTX_GRX_P8
J29
PEG_HTX_GRX_P7
J27
PEG_HTX_GRX_P6
H28
PEG_HTX_GRX_P5
G28
PEG_HTX_GRX_P4
E28
PEG_HTX_GRX_P3
F28
PEG_HTX_GRX_P2
D27
PEG_HTX_GRX_P1
E26
PEG_HTX_GRX_P0
D25
PEG_COMP
24.9_0402_1%
C547 0.1U_0402_10V7KOPT@C547 0.1U_0402_10V7KOPT@
1 2
C545 0.1U_0402_10V7KOPT@C545 0.1U_0402_10V7KOPT@
1 2
C543 0.1U_0402_10V7KOPT@C543 0.1U_0402_10V7KOPT@
1 2
C541 0.1U_0402_10V7KOPT@C541 0.1U_0402_10V7KOPT@
1 2
C555 0.1U_0402_10V7KOPT@C555 0.1U_0402_10V7KOPT@
1 2
C553 0.1U_0402_10V7KOPT@C553 0.1U_0402_10V7KOPT@
1 2
C556 0.1U_0402_10V7KOPT@C556 0.1U_0402_10V7KOPT@
1 2
C561 0.1U_0402_10V7KOPT@C561 0.1U_0402_10V7KOPT@
1 2
C563 0.1U_0402_10V7KOPT@C563 0.1U_0402_10V7KOPT@
1 2
C569 0.1U_0402_10V7KOPT@C569 0.1U_0402_10V7KOPT@
1 2
C571 0.1U_0402_10V7KOPT@C571 0.1U_0402_10V7KOPT@
1 2
C574 0.1U_0402_10V7KOPT@C574 0.1U_0402_10V7KOPT@
1 2
C576 0.1U_0402_10V7KOPT@C576 0.1U_0402_10V7KOPT@
1 2
C579 0.1U_0402_10V7KOPT@C579 0.1U_0402_10V7KOPT@
1 2
C582 0.1U_0402_10V7KOPT@C582 0.1U_0402_10V7KOPT@
1 2
C587 0.1U_0402_10V7KOPT@C587 0.1U_0402_10V7KOPT@
1 2
C546 0.1U_0402_10V7KOPT@C546 0.1U_0402_10V7KOPT@
1 2
C544 0.1U_0402_10V7KOPT@C544 0.1U_0402_10V7KOPT@
1 2
C542 0.1U_0402_10V7KOPT@C542 0.1U_0402_10V7KOPT@
1 2
C540 0.1U_0402_10V7KOPT@C540 0.1U_0402_10V7KOPT@
1 2
C554 0.1U_0402_10V7KOPT@C554 0.1U_0402_10V7KOPT@
1 2
C552 0.1U_0402_10V7KOPT@C552 0.1U_0402_10V7KOPT@
1 2
C557 0.1U_0402_10V7KOPT@C557 0.1U_0402_10V7KOPT@
1 2
C562 0.1U_0402_10V7KOPT@C562 0.1U_0402_10V7KOPT@
1 2
C565 0.1U_0402_10V7KOPT@C565 0.1U_0402_10V7KOPT@
1 2
C570 0.1U_0402_10V7KOPT@C570 0.1U_0402_10V7KOPT@
1 2
C572 0.1U_0402_10V7KOPT@C572 0.1U_0402_10V7KOPT@
1 2
C575 0.1U_0402_10V7KOPT@C575 0.1U_0402_10V7KOPT@
1 2
C577 0.1U_0402_10V7KOPT@C577 0.1U_0402_10V7KOPT@
1 2
C581 0.1U_0402_10V7KOPT@C581 0.1U_0402_10V7KOPT@
1 2
C585 0.1U_0402_10V7KOPT@C585 0.1U_0402_10V7KOPT@
1 2
C588 0.1U_0402_10V7KOPT@C588 0.1U_0402_10V7KOPT@
1 2
PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with Âmax length = 500 mils
- typical impedance = 14.5 mohms
PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0
PEG_GTX_C_HRX_N[0..15] <23>
PEG_GTX_C_HRX_P[0..15] <23>
PEG_HTX_C_GRX_N[0..15] <23>
PEG_HTX_C_GRX_P[0..15] <23>
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2011/09/28
2011/09/28
2011/09/28
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
4
4
4
1
55
55
55
0.1
0.1
0.1
5
D D
4
3
2
1
XDP_DBRESET#
R407 1K_0402_5%R407 1K_0402_5%
+3VS
12
For eDP
CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R
JCPU1B
JCPU1B
C C
H_SNB_IVB#<18>
+1.05VS_VCCP
B B
PLT_RST# PM_DRAM_PWR GD_RPM_SYS_PWRGD_BUF
Follow DG 0.71
A A
PM_DRAM_PWR GD<16>
Processor Pullups
R67 62_0402_5%R67 62_0402_5%
R70 10K_0402_5%R70 10K_0402_5%
12
12
Buffered reset to CPU
+3VS
12
C74
C74
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
U8
U8
1
P
NC
2
A
PLT_RST# <18,35,38,39,44>
BUFO_CPU_RST#
4
Y
G
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
3
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10K_0402_5%
10K_0402_5%
1 2
5
R440
R440
H_PROCHOT#
H_CPUPWRGD
+1.05VS_VCCP
12
12
C280
C280
R84
R84
75_0402_5%
75_0402_5%
R85
R85
43_0402_1%
43_0402_1%
1 2
+3VALW
U11
U11
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
5
1
P
B
2
A
G
3
SUSP<46,53>
BUF_CPU_RST#
12
@
@
R86
R86
0_0402_5%
0_0402_5%
PM_SYS_PWRGD_BUF
4
O
SUSP
2
G
G
+1.5V_CPU_VDDQ
12
@
@
R153
R153
39_0402_5%
39_0402_5%
13
D
D
@
@
Q19
Q19
2N7002E_SOT23-3
2N7002E_SOT23-3
S
S
12
R149
R149
200_0402_5%
200_0402_5%
R72
R72
H_CATERR#
H_PROCHOT#_R
H_CPUPWRGD
BUF_CPU_RST#
T9 PADT9 PAD
H_PECI<19,39>
56_0402_5%
56_0402_5%
H_PROCHOT#<39,50>
H_THRMTRIP#<19>
H_CPUPWRGD<19>
4
1 2
H_PM_SYNC<16>
R150
R150
130_0402_5%
130_0402_5%
1 2
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWR OK
AR33
RESET#
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
CONN@
CONN@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
CLOCKS
CLOCKS
DDR3
DDR3
JTAG & BPM
JTAG & BPM
2010/09/28
2010/09/28
2010/09/28
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
MISC
MISC
PREQ#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
Compal Secret Data
Compal Secret Data
Compal Secret Data
BCLK
BCLK#
PRDY#
TRST#
DBR#
A28
A27
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
TCK
AR27
TMS
AP30
AR28
TDI
AP26
TDO
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
Deciphered Date
Deciphered Date
Deciphered Date
CLK_CPU_DMI
CLK_CPU_DMI#
CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R
H_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DBRESET#_R
2
R409 1K_0402_5%R409 1K_0402_5%
1 2
R414 1K_0402_5%R414 1K_0402_5%
1 2
H_DRAMRST# <6>
T7PAD T7PAD
T27PAD T27PAD
T25PAD T25PAD
T26PAD T26PAD
T6PAD T6PAD
R402 0_0402_5%R402 0_0402_5%
1 2
2011/09/28
2011/09/28
2011/09/28
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
XDP_DBRESET#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
R410 0_0402_5%@R410 0_0402_5%@
1 2
R413 0_0402_5%@R413 0_0402_5%@
1 2
+1.05VS_VCCP
CLK_CPU_DPLL <15>
CLK_CPU_DPLL# <15>
DDR3 compensation Signals
SM_RCOMP0
R151 140_0402_1%R151 140_0402_1%
SM_RCOMP1
R436 25.5_0402_1%R436 25.5_0402_1%
SM_RCOMP2
R437 200_0402_1%R437 200_0402_1%
12
12
12
PU/PD for JTAG signals
Del resister and add test point
XDP_DBRESET# <16>
Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
1
5
5
5
0.1
0.1
0.1
55
55
55
5
JCPU1C
JCPU1C
4
3
JCPU1D
JCPU1D
2
1
DDR_A_D[0..63]<11,12>
D D
C C
B B
DDR_A_BS0<11,12>
DDR_A_BS1<11,12>
DDR_A_BS2<11,12>
DDR_A_CAS#<11,12>
DDR_A_RAS#<11,12>
DDR_A_WE#<11,12>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AE8
AD9
AF9
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
SA_DQ[41]
AJ9
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
V6
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
RSVD_TP[10]
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_CLK_DDR1
M_CLK_DDR#1
R159 36_0402_1%R159 36_0402_1%
R161 36_0402_1%R161 36_0402_1%
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 <11,12>
M_CLK_DDR#0 <11,12>
DDR_CKE0_CHA <11,12>
12
R160 36_0402_1%R160 36_0402_1%
DDR_CS0_CHA# < 11,12>
12
M_ODT0 <11,12>
12
DDR_A_DQS#[0..7] <11,12>
DDR_A_DQS[0..7] <11,12>
DDR_A_MA[0..15] <11,12> DDR_B_MA[0..15] <13>
+0.75VS
DDR_B_D[0..63]<13>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
J10
C9
A7
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K9
J9
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
R6
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
RSVD_TP[17]
RSVD_TP[18]
RSVD_TP[19]
RSVD_TP[20]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
M_ODT2 <13>
M_ODT3 <13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
R156@
R156@
0_0402_5%
0_0402_5%
1 2
D
S
D
S
123
Q17
Q17
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
G
G
12
C260
C260
0.047U_0402_16V4Z
0.047U_0402_16V4Z
DDR3_DRAMRST#_R
5
H_DRAMRST#
4.99K_0402_1%
4.99K_0402_1%
R155
R155
1 2
H_DRAMRST#<5>
A A
DRAMRST_CNTRL_PCH<11,13,15>
+1.5V
R192
R192
1K_0402_5%
1K_0402_5%
12
R193
R193
1K_0402_5%
1K_0402_5%
1 2
4
CONN@
CONN@
DDR3_DRAMRST# <11,12,13>
M_CLK_DDR1
M_CLK_DDR#1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1 2
1
C251
C251
1.8P_0402_50V8
1.8P_0402_50V8
2
1 2
R163
R163
30.1_0402_1%
30.1_0402_1%
R162
R162
30.1_0402_1%
30.1_0402_1%
2010/09/28
2010/09/28
2010/09/28
1
C261
C261
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
CONN@
CONN@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
1
0.1
0.1
0.1
55
6
55
6
55
6
5
4
3
2
1
CFG Straps for Processor
CFG2
D D
JCPU1E
JCPU1E
L7
RSVD28
AG7
AK28
CFG[0]
AK29
CFG2
CFG4
CFG5
CFG6
CFG7
C C
B B
AJ31 change to VAXG_VAL_SENSE
AH31 change to VSSAXG_VAL_SENSE
AJ33 change to VCC_VAL_SENSE
AH33 change to VSS_VAL_SENSE
RSVD6 and RSVD7 had changed to
SA_DIMM_VREFDQ and SB_DIMMVREFDQ
SA_DIMM_VREFDQ<11>
+3VS
SB_DIMM_VREFDQ<13>
12
R406
R406
10K_0402_5%@
10K_0402_5%@
VCCIO_SEL
12
R408
R408
10K_0402_5%@
10K_0402_5%@
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC
R157
R157
1K_0402_1%
1K_0402_1%
T8 PADT8 PAD
T4 PADT4 PAD
T3 PADT3 PAD
T2 PADT2 PAD
12
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
12
R158
R158
1K_0402_1%
1K_0402_1%
VCCIO_SEL
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
RESERVED
RESERVED
VCCIO_SEL
1/NC : (Default) +1.05VS_VTT
A19
*
0: +1.0VS_VTT
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
CONN@
CONN@
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
VCC_DIE_SENSE
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
KEY
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
B1
T5PAD T5PAD
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
*
Display Port Presence Strap
CFG4
*
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
12
R90
R90
1K_0402_1%
1K_0402_1%
1: Normal Operation; Lane # definition matches
socket pin map definition
0:Lane Reversed
CFG4
1K_0402_1%
1K_0402_1%
12
@
@
R91
R91
1K_0402_1%
1K_0402_1%
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
CFG5
CFG7
12
12
R87@
12
R87@
1K_0402_1%
1K_0402_1%
R71@
R71@
1K_0402_1%
1K_0402_1%
R88@
R88@
VCCIO_SEL For 2012 CPU support
RSVD26 had changed the name to VCCIO_SEL
Need PH +3VS 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select
A A
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7
de assertion
0: PEG Wait for BIOS for training
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
1
7
7
7
55
55
55
0.1
0.1
0.1
5
+CPU_CORE
C97
10U_0805_6.3V6M
C97
10U_0805_6.3V6M
C98
10U_0805_6.3V6M
C98
10U_0805_6.3V6M
12
D D
12
+CPU_CORE
C59
22U_0805_6.3V6M
C59
22U_0805_6.3V6M
12
C100
22U_0805_6.3V6M
C100
22U_0805_6.3V6M
+CPU_CORE
12
@
@
C C
B B
A A
12
C608
10U_0805_6.3V6M
C608
10U_0805_6.3V6M
12
12
330U_D2_2V_Y
330U_D2_2V_Y
12
+
+
C80
10U_0805_6.3V6M
C80
10U_0805_6.3V6M
12
C60
22U_0805_6.3V6M
C60
22U_0805_6.3V6M
C58
22U_0805_6.3V6M
C58
22U_0805_6.3V6M
12
C81
22U_0805_6.3V6M
C81
22U_0805_6.3V6M
C92
22U_0805_6.3V6M
C92
22U_0805_6.3V6M
12
C551
330U_D2_2V_Y+C551
330U_D2_2V_Y
C33
C33
12
+
4
SV type CPU
QC 94A
DC 53A
C77
10U_0805_6.3V6M
C77
10U_0805_6.3V6M
C82
10U_0805_6.3V6M
C82
10U_0805_6.3V6M
C78
10U_0805_6.3V6M
C78
10U_0805_6.3V6M
12
C595
10U_0805_6.3V6M
C595
10U_0805_6.3V6M
12
C55
22U_0805_6.3V6M
C55
22U_0805_6.3V6M
12
C99
22U_0805_6.3V6M
C99
22U_0805_6.3V6M
12
C516
330U_D2_2V_Y+C516
330U_D2_2V_Y
12
12
+
+
12
12
C592
10U_0805_6.3V6M
C592
10U_0805_6.3V6M
12
12
12
C128
330U_D2_2V_Y+C128
330U_D2_2V_Y
C594
10U_0805_6.3V6M
C594
10U_0805_6.3V6M
12
C34
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C79
22U_0805_6.3V6M
C79
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
330U_D2_2V_Y
330U_D2_2V_Y
12
C603
C603
+
+
C591
22U_0805_6.3V6M
C591
22U_0805_6.3V6M
C593
22U_0805_6.3V6M
C593
C600
C600
C96
C96
22U_0805_6.3V6M
12
12
C105
22U_0805_6.3V6M
C105
22U_0805_6.3V6M
12
C605
22U_0805_6.3V6M
C605
22U_0805_6.3V6M
12
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
3
POWER
JCPU1F
JCPU1F
POWER
8.5A
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
CORE SUPPLY
CORE SUPPLY
SENSE LINES SVID
SENSE LINES SVID
PEG AND DDR
PEG AND DDR
VCCIO_SENSE
VSSIO_SENSE
VCC_SENSE
VSS_SENSE
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
2
+1.05VS_VCCP
12
12
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C163
C163
C168
C168
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C164
C164
C166
C166
12
R59
R59
130_0402_5%
130_0402_5%
R56 0_0402_5%R56 0_0402_5%
R58 0_0402_5%R58 0_0402_5%
VCCIO_SENSE <53>
VSSIO_SENSE <53>
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C167
C167
22U_0805_6.3V6M
22U_0805_6.3V6M
12
@
@
C111
C111
+1.05VS_VCCP+1.05VS_VCCP
R57
R57
43_0402_1%
43_0402_1%
1 2
1 2
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C161
C161
22U_0805_6.3V6M
22U_0805_6.3V6M
12
@
@
C126
C126
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C165
C165
330U_D2_2V_Y
330U_D2_2V_Y
12
C598
C598
+
+
22U_0805_6.3V6M
12
12
C612
C612
12
+
+
C155@
C155@
330U_D2_2V_Y
330U_D2_2V_Y
12
C613
C613
330U_D2_2V_Y
330U_D2_2V_Y
12
C606
C606
+
+
Cap quantity follow 43890_HR_CHKLST_Rev07
12
R54
R54
75_0402_5%
75_0402_5%
Place the PU
resistors
close to VR
R76
R76
100_0402_1%
100_0402_1%
R77
R77
100_0402_1%
100_0402_1%
Place the PU
resistors
close to CPU
VCCSENSE <54 >
VSSSENSE <54>
+CPU_CORE
12
12
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C611
C611
VR_SVID_ALRT# <54>
VR_SVID_CLK <54>
VR_SVID_DAT <54>
C610
C610
+1.05VS_VCCP
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C156
C156
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
CONN@
CONN@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
1
8
8
8
55
55
55
0.1
0.1
0.1
5
D D
+VGFX_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C109
C109
12
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C88
C88
12
12
C124
C124
C95
C95
12
2x 470 µF Bottom Socket Edge
2x 22 µF Top Socket Cavity
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
4x 22 µF Top Socket Edge
C C
2x 470 µF Bottom Socket Cavity
22U_0805_6.3V6M
C119
C119
C87
C87
12
12
22U_0805_6.3V6M
22U_0805_6.3V6M
C135
C135
C94
12
C94
12
4x 22 µF Bottom Socket Edge
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
12
12
+
+
@
@
C583
C583
C614
C614
+
+
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@
@
@
@
C141
C141
C596
C596
12
12
Vaxg
Can connect to GND if motherboard only
‧
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
B B
‧
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
+1.8VS
R432
R432
0_0805_5%
0_0805_5%
1 2
C618
330U_D2_2V_Y+C618
330U_D2_2V_Y
12
+
4
POWER
QC 33A
DC 26A
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C125
C125
C110
C110
12
12
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C142
C142
C604
12
C604
12
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
JCPU1G
JCPU1G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
POWER
GRAPHICS
GRAPHICS
1.5A
+1.8VS_VCCPLL
C624
1U_0402_6.3V6K
C624
1U_0402_6.3V6K
C623
1U_0402_6.3V6K
C623
C622
10U_0805_6.3V6M
C622
10U_0805_6.3V6M
12
1U_0402_6.3V6K
12
12
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
1.8V RAIL
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
CONN@
CONN@
1.8V RAIL
SENSE
SENSE
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
3
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
FC_C22
VCCSA_VID1
AK35
AK34
+V_SM_VREF should
have 20 mil trace width
AL1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
H_FC_C22
C22
C24
VCC_AXG_SENSE <54>
VSS_AXG_SENSE <54>
+V_SM_VREF
12
C642
C642
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
12
12
C259
C259
C276
C276
+VCCSA
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
12
12
C29
C29
C590
C590
12
R95
R95
10K_0402_5%
10K_0402_5%
1 2
2
Follow DG 0.71 page 6
+1.5V_CPU_VDDQ
12
R438
R438
1K_0402_1%
1K_0402_1%
12
R439
R439
1K_0402_1%
1K_0402_1%
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
12
C248
C248
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
12
10U_0805_6.3V6M
12
C255
C255
+VCCSA
C85
C85
12
+
+
VCCSA_SENSE <52>
VCCSA_VID1 <52>
10U_0805_6.3V6M
10U_0805_6.3V6M
12
C250
C250
10U_0805_6.3V6M
10U_0805_6.3V6M
12
C93
C93
R93@
R93@
0_0402_5%
0_0402_5%
+1.5V_CPU_VDDQ
10U_0805_6.3V6M
10U_0805_6.3V6M
12
12
+
+
C262
C262
C263
C263
330U_D2_2V_Y
330U_D2_2V_Y
R390 0_0402_5%R390 0_0402_5%
1 2
C32
C32
330U_D2_2V_Y
330U_D2_2V_Y
R389 0_0402_5%R389 0_0402_5%
1 2
JP1@
JP1@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
VCCSA_SENSE
VSSSA_SENSE <52>
1
+1.5VS
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
1
9
55
9
55
9
55
0.1
0.1
0.1
5
D D
C C
B B
4
JCPU1H
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AR25
AR22
AR19
AR16
AR13
AR10
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AJ25
AT7
AT4
AT3
AR7
AR4
AR2
AP7
AP4
AP1
AN7
AN4
AL7
AL4
AL2
AK7
AK4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
3
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS
2
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
1
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
SUYIN_100361HK988_SANDY BRIDGE
CONN@
CONN@
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
SUYIN_100361HK988_SANDY BRIDGE
CONN@
CONN@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Friday, November 19, 2010
Friday, November 19, 2010
Friday, November 19, 2010
1
10
55
10
55
10
55
0.1
0.1
0.1
5
4
3
2
1
U41
R552
R552
F10
H10
A11
N11
C4
D4
B4
C8
C3
C9
E4
E9
D3
E8
A8
B8
H9
E2
J9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
J8
H2
F2
A1
N8
A4
N1
R335
R335
U41
DQS
DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A15/BA3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MT41J256M8HX-187E:D C38
MT41J256M8HX-187E:D C38
X76@
X76@
C4
D4
B4
C8
C3
C9
E4
E9
D3
E8
A8
B8
H9
E2
J9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
J8
F10
H2
F2
H10
A1
N8
A11
A4
N1
N11
RESET#
U20
U20
DQS
DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A15/BA3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MT41J256M8HX-187E:D C38
MT41J256M8HX-187E:D C38
X76@
X76@
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CKE
RAS#
CAS#
WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK#
BA0
BA1
BA2
CS#
CK
RESET#
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
C736
2.2U_0603_6.3V6K
C736
2.2U_0603_6.3V6K
1 2
240_0402_1%
240_0402_1%
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA[0..15]
DDR_A_DQS#[0..3]
DDR_A_DQS[0..3]
DDR_A_D[0..31]
DDR_A_DQS3
DDR_A_DQS#3
5
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
1 2
240_0402_1%
240_0402_1%
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
D D
+VREF0 +VREF0 +VREF0
C750
0.1U_0402_16V4Z
C750
0.1U_0402_16V4Z
1
12
2
+VREF1
C740
0.1U_0402_16V4Z
C740
0.1U_0402_16V4Z
1
2
C C
DDR_A_MA[0..15]<6,12>
DDR_A_DQS#[0..3]<6>
DDR_A_DQS[0..3]<6>
DDR_A_D[0..31]<6>
B B
+VREF0
C412 0.1U_0402_16V4ZC412 0 .1U_0402_16V4Z
C411 0.1U_0402_16V4ZC411 0 .1U_0402_16V4Z
1
1
2
2
+VREF1
C450
0.1U_0402_16V4Z
C450
0.1U_0402_16V4Z
1
2
A A
+1.5V +1.5V
B10
C2
E3
E10
A3
A10
D8
G3
G9
K2
K10
M2
M10
G2
F8
G8
DDR_CKE0_CHA
G10
J3
K9
J4
DDR_CS0_CHA#
H3
F4
G4
H4
DDR3_DRAMRST#
N3
B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CK
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
B10
C2
E3
E10
A3
A10
D8
G3
G9
K2
K10
M2
M10
G2
F8
G8
DDR_CKE0_CHA
G10
J3
K9
J4
DDR_CS0_CHA#
H3
F4
G4
H4
DDR3_DRAMRST#
N3
B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10
M_ODT0 <6,12>
M_CLK_DDR0 <6,12>
M_CLK_DDR#0 <6,12>
DDR_CKE0_CHA <6,12>
DDR_A_BS0 <6,12>
DDR_A_BS1 <6,12>
DDR_A_BS2 <6,12>
DDR_CS0_CHA# <6,12>
DDR_A_RAS# <6,12>
DDR_A_CAS# <6,12>
DDR_A_WE# <6,12>
DDR3_DRAMRST# <6,12,13>
+1.5V
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
4
C452 0.1U_0402_16V4ZC452 0.1U_0402_16 V4Z
+VREF1
C455
0.1U_0402_16V4Z
C455
0.1U_0402_16V4Z
1
2
M3 support
SA_DIMM_VREFDQ<7>
DRAMRST_CNTRL_PC H<6,13,15>
DDR_A_DQS1
DDR_A_DQS#1
1 2
240_0402_1%
C451 0.1U_0402_16V4ZC451 0.1U_0402_16 V4Z
1
2
240_0402_1%
1
2
BSS138_NL_SOT23-3 @
BSS138_NL_SOT23-3 @
R343
R343
1K_0402_1%
1K_0402_1%
R338
R338
1K_0402_1%
1K_0402_1%
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
@R345
@
0_0402_5%
0_0402_5%
1 2
S
S
+1.5V
12
12
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
R336
R336
R345
D
D
13
Q39
Q39
G
G
2
C449
0.1U_0402_16V4Z
C449
0.1U_0402_16V4Z
12
Issued Date
Issued Date
Issued Date
C4
D4
B4
C8
C3
C9
E4
E9
D3
E8
A8
B8
H9
E2
J9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
J8
F10
H2
F2
H10
A1
N8
A11
A4
N1
N11
U21
U21
DQS
DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A15/BA3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MT41J256M8HX-187E:D C38
MT41J256M8HX-187E:D C38
X76@
X76@
+1.5V
12
R346
R346
1K_0402_1%
1K_0402_1%
12
12
R347
R347
1K_0402_1%
1K_0402_1%
+VREF1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C448
C448
12
3
B10
VDDQ
C2
VDDQ
E3
VDDQ
E10
VDDQ
A3
VDD
A10
VDD
D8
VDD
G3
VDD
G9
VDD
K2
VDD
K10
VDD
M2
VDD
M10
VDD
G2
ODT
F8
CK
G8
CK#
G10
CKE
J3
BA0
K9
BA1
J4
BA2
H3
CS#
F4
RAS#
G4
CAS#
H4
WE#
N3
RESET#
B3
VSSQ
B9
VSSQ
C10
VSSQ
D2
VSSQ
D10
VSSQ
A2
VSS
A9
VSS
B2
VSS
F3
VSS
F9
VSS
D9
VSS
J2
VSS
J10
VSS
L2
VSS
L10
VSS
N2
VSS
N10
VSS
+VREF0
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C442
C442
C462
C462
12
2010/04/26 2011/04/26
2010/04/26 2011/04/26
2010/04/26 2011/04/26
+1.5V
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_CHA
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS0_CHA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
Layout Note:
Place near JDIMM1.203,204
DDR_A_RAS#
DDR_A_CAS#
M_ODT0
DDR_CKE0_CHA
DDR_A_WE#
DDR_A_MA10
DDR_CS0_CHA#
DDR_A_BS2
DDR_A_BS0
DDR_A_MA12
DDR_A_MA0
DDR_A_BS1
DDR_A_MA3
DDR_A_MA1
DDR_A_MA2
DDR_A_MA4
DDR_A_MA5
DDR_A_MA11
DDR_A_MA9
DDR_A_MA14
DDR_A_MA13
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA15
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C741 0.1U_0402_16V4ZC741 0 .1U_0402_16V4Z
C739
C739
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
R272 36_0402_1%R272 36_0402_1%
SPD define A0 address
1
12
2
+VREF1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
RP1
RP1
36_0804_8P4R_5%
36_0804_8P4R_5%
36_0804_8P4R_5%
36_0804_8P4R_5%
RP2
RP2
RP3
RP3
36_0804_8P4R_5%
36_0804_8P4R_5%
RP4
RP4
36_0804_8P4R_5%
36_0804_8P4R_5%
RP5
RP5
36_0804_8P4R_5%
36_0804_8P4R_5%
36_0804_8P4R_5%
36_0804_8P4R_5%
RP7
RP7
12
2
C747
2.2U_0603_6.3V6K
C747
2.2U_0603_6.3V6K
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
1 2
240_0402_1%
240_0402_1%
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
+0.75VS
U42
U42
C4
DQS
D4
DQS#
B4
DQ0
C8
DQ1
C3
DQ2
C9
DQ3
E4
DQ4
E9
DQ5
D3
DQ6
E8
DQ7
A8
NU/TDQS#
B8
DM/TDQS
R550
R550
H9
ZQ
E2
VREFDQ
J9
VREFCA
K4
A0
L8
A1
L4
A2
K3
A3
L9
A4
L3
A5
M9
A6
M3
A7
N9
A8
M4
A9
H8
A10/AP
M8
A11
K8
A12/BC#
N4
A13
J8
A15/BA3
F10
NC
H2
NC
F2
NC
H10
NC
A1
NC
N8
NC
A11
NC
A4
NC
N1
NC
N11
NC
MT41J256M8HX-187E:D C38
MT41J256M8HX-187E:D C38
X76@
X76@
+0.75VS
C407
1U_0402_6.3V6K
C407
1U_0402_6.3V6K
12
12
+1.5V
C454
1U_0402_6.3V6K
C454
1U_0402_6.3V6K
12
+1.5V
C429
10U_0603_6.3V6M
C429
10U_0603_6.3V6M
12
12
Title
Title
Title
DDRIII DIMMA
DDRIII DIMMA
DDRIII DIMMA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1U_0402_6.3V6K
1U_0402_6.3V6K
C388
C388
12
10U_0603_6.3V6M
10U_0603_6.3V6M
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C453
1U_0402_6.3V6K
C453
1U_0402_6.3V6K
C751
C751
CK
12
12
B10
C2
E3
E10
A3
A10
D8
G3
G9
K2
K10
M2
M10
G2
F8
G8
G10
J3
K9
J4
H3
F4
G4
H4
N3
B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10
C394
1U_0402_6.3V6K
C394
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C738
10U_0603_6.3V6M
C738
10U_0603_6.3V6M
1
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_CHA
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS0_CHA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
C400
1U_0402_6.3V6K
C400
1U_0402_6.3V6K
12
Layout Note:
Place near each
memory part
C445
1U_0402_6.3V6K
C445
1U_0402_6.3V6K
C428
C428
12
C456
10U_0603_6.3V6M
C456
10U_0603_6.3V6M
330U_D2_2V_Y
330U_D2_2V_Y
C408
C408
12
12
+
+
11 54Wednesday, December 29, 2010
11 54Wednesday, December 29, 2010
11 54Wednesday, December 29, 2010
0.1
0.1
0.1
5
U19
DDR_A_DQS4
C463
C463
DDR_A_DQS#4
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
1 2
240_0402_1%
240_0402_1%
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
1 2
240_0402_1%
240_0402_1%
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
5
D D
+VREF0
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
12
C464
C464
2
+VREF1
C447
0.1U_0402_16V4Z
C447
0.1U_0402_16V4Z
1
2
C C
B B
+VREF0
C444
0.1U_0402_16V4Z
C444
0.1U_0402_16V4Z
1
2
+VREF1
C446
0.1U_0402_16V4Z
C446
0.1U_0402_16V4Z
A A
C443
0.1U_0402_16V4Z
C443
0.1U_0402_16V4Z
1
2
1
2
U19
C4
D4
B4
C8
C3
C9
E4
E9
D3
E8
A8
B8
R302
R302
H9
E2
J9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
J8
F10
H2
F2
H10
A1
N8
A11
A4
N1
N11
MT41J256M8HX-187E:D C38
MT41J256M8HX-187E:D C38
X76@
X76@
U18
U18
C4
D4
B4
C8
C3
C9
E4
E9
D3
E8
A8
B8
R337
R337
H9
E2
J9
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
J8
F10
H2
F2
H10
A1
N8
A11
A4
N1
N11
MT41J256M8HX-187E:D C38
MT41J256M8HX-187E:D C38
X76@
X76@
DQS
DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A15/BA3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQS
DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A15/BA3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CK#
CKE
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CK#
CKE
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B10
C2
E3
E10
A3
A10
D8
G3
G9
K2
K10
M2
M10
M_ODT0
G2
M_CLK_DDR0
F8
CK
BA0
BA1
BA2
CK
BA0
BA1
BA2
G8
G10
J3
K9
J4
H3
F4
G4
H4
N3
B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10
B10
C2
E3
E10
A3
A10
D8
G3
G9
K2
K10
M2
M10
G2
F8
G8
G10
J3
K9
J4
H3
F4
G4
H4
N3
B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10
M_CLK_DDR#0
DDR_CKE0_CHA
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS0_CHA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_CHA
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS0_CHA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
+1.5V
+1.5V
4
C744
C744
M_ODT0 <6,11>
M_CLK_DDR0 <6,11>
M_CLK_DDR#0 <6,11>
DDR_CKE0_CHA <6,11>
DDR_CS0_CHA# <6,11>
DDR_A_RAS# <6,11>
DDR_A_CAS# <6,11>
DDR_A_WE# <6,11>
DDR3_DRAMRST# <6,11,13>
4
3
+1.5V
U43
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
+VREF0 +VREF0
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C742
C742
1
2
2
+VREF1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
1 2
240_0402_1%
240_0402_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_MA0
C743
C743
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
U43
C4
DQS
D4
DQS#
B4
DQ0
C8
DQ1
C3
DQ2
C9
DQ3
E4
DQ4
E9
DQ5
D3
DQ6
E8
DQ7
A8
NU/TDQS#
B8
DM/TDQS
R553
R553
H9
ZQ
E2
VREFDQ
J9
VREFCA
K4
A0
L8
A1
L4
A2
K3
A3
L9
A4
L3
A5
M9
A6
M3
A7
N9
A8
M4
A9
H8
A10/AP
M8
A11
K8
A12/BC#
N4
A13
J8
A15/BA3
F10
NC
H2
NC
F2
NC
H10
NC
A1
NC
N8
NC
A11
NC
A4
NC
N1
NC
N11
NC
MT41J256M8HX-187E:D C38
MT41J256M8HX-187E:D C38
X76@
X76@
DDR_A_MA[0..15]<6,11>
DDR_A_DQS#[4..7]<6>
DDR_A_DQS[4..7]<6>
DDR_A_D[32..63]<6>
+1.5V +1.5V
C718
10U_0603_6.3V6M
C718
10U_0603_6.3V6M
C460
10U_0603_6.3V6M
C460
10U_0603_6.3V6M
C728
10U_0603_6.3V6M
C728
10U_0603_6.3V6M
12
12
12
Layout Note:
Place near each
memory part
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
12
VDDQ
VDDQ
VDDQ
VDDQ
RAS#
CAS#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
10U_0603_6.3V6M
10U_0603_6.3V6M
B10
C2
E3
E10
A3
VDD
A10
VDD
D8
VDD
G3
VDD
G9
VDD
K2
VDD
K10
VDD
M2
VDD
M10
VDD
G2
ODT
F8
CK
G8
CK#
G10
CKE
J3
BA0
K9
BA1
J4
BA2
H3
CS#
F4
G4
H4
WE#
N3
B3
B9
C10
D2
D10
A2
VSS
A9
VSS
B2
VSS
F3
VSS
F9
VSS
D9
VSS
J2
VSS
J10
VSS
L2
VSS
L10
VSS
N2
VSS
N10
VSS
DDR_A_MA[0..15]
DDR_A_DQS#[4..7]
DDR_A_DQS[4..7]
DDR_A_D[32..63]
C457
C457
2009/12/01
2009/12/01
2009/12/01
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_CHA
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS0_CHA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
C748
1U_0402_6.3V6K
C748
1U_0402_6.3V6K
12
C733
1U_0402_6.3V6K
C733
1U_0402_6.3V6K
C732
1U_0402_6.3V6K
C732
1U_0402_6.3V6K
12
12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
DDR_A_BS0 <6,11>
DDR_A_BS1 <6,11>
DDR_A_BS2 <6,11>
12
2
1
2
+VREF1
C746
0.1U_0402_16V4Z
C746
0.1U_0402_16V4Z
C724
1U_0402_6.3V6K
C724
1U_0402_6.3V6K
2010/12/31
2010/12/31
2010/12/31
2
1
+1.5V
U44
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
1 2
240_0402_1%
240_0402_1%
C749
2.2U_0603_6.3V6K
C749
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
C745
C745
1
2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA15DDR_A_MA15
DDR_A_MA14
M_CLK_DDR0<6,11>
M_CLK_DDR#0<6,11>
D_CK_SCLK<13,15>
D_CK_SDATA<13,15>
U44
C4
DQS
D4
DQS#
B4
DQ0
C8
DQ1
C3
DQ2
C9
DQ3
E4
DQ4
E9
DQ5
D3
DQ6
E8
DQ7
A8
NU/TDQS#
B8
DM/TDQS
R554
R554
H9
ZQ
E2
VREFDQ
J9
VREFCA
K4
A0
L8
A1
L4
A2
K3
A3
L9
A4
L3
A5
M9
A6
M3
A7
N9
A8
M4
A9
H8
A10/AP
M8
A11
K8
A12/BC#
N4
A13
J8
A15/BA3
F10
NC
H2
NC
F2
NC
H10
NC
A1
NC
N8
NC
A11
NC
A4
NC
N1
NC
N11
NC
MT41J256M8HX-187E:D C38
MT41J256M8HX-187E:D C38
X76@
X76@
C367
C367
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R246
R246
30.1_0402_1%
30.1_0402_1%
1
C397
C397
1.8P_0402_50V8
1.8P_0402_50V8
2
+3VS
R368
R368
@
@
1 2
10K_0402_5%
10K_0402_5%
Title
Title
Title
DDRIII DIMMB
DDRIII DIMMB
DDRIII DIMMB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-7221P
LA-7221P
LA-7221P
Date: Sheet of
Date: Sheet of
Date: Sheet of
@
@
U24
U24
8
VCC
7
WP
6
SCL
5
SDA
AT24C02N-10SU-2.7_SO8
AT24C02N-10SU-2.7_SO8
Compal Electronics, Inc.
Wednesday, December 29, 2010
Wednesday, December 29, 2010
Wednesday, December 29, 2010
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT
CK
CK#
CKE
BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
12
END topology
A0
A1
A2
GND
1
B10
C2
E3
E10
A3
A10
D8
G3
G9
K2
K10
M2
M10
G2
F8
G8
G10
J3
K9
J4
H3
F4
G4
H4
N3
B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10
1
2
3
4
12
M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_CHA
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS0_CHA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR3_DRAMRST#
Tacoma
R250
R250
30.1_0402_1%
30.1_0402_1%
12
12
12
55
55
55
0.1
0.1
0.1
5
R483
@R483
M3 support
SB_DIMM_VREFDQ<7>
BSS138_NL_SOT23-3 @
BSS138_NL_SOT23-3 @
DRAMRST_CNTRL_PC H<6,11,15>
D D
C C
B B
A A
@
0_0402_5%
0_0402_5%
1 2
S
S
G
G
2
D
D
13
Q48
Q48
<Address: 01>
DIMM_B Reverse type H:4mm
5
+1.5V
12
R498
R498
1K_0402_1%
1K_0402_1%
12
R496
R496
1K_0402_1%
1K_0402_1%
10K_0402_5%
10K_0402_5%
+0.75VS
4
12
All VREF traces should
have 10 mil trace width
DDR_CKE2_DIMMB<6>
DDR_B_BS2<6>
M_CLK_DDR2<6>
M_CLK_DDR#2<6>
DDR_B_BS0<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDR_CS3_DIMMB#<6>
+3VS
C354
0.1U_0402_16V4Z
C354
0.1U_0402_16V4Z
12
R228
R228
4
12
3
+1.5V
+DIMM1_VREF
C702
0.1U_0402_16V4Z
C702
0.1U_0402_16V4Z
C705
2.2U_0603_6.3V6K
C705
2.2U_0603_6.3V6K
C355
2.2U_0603_6.3V6K
C355
2.2U_0603_6.3V6K
12
DDR_B_D0
12
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB DDR_CKE3_DIMM B
DDR_B_BS2
DDR_B_MA9
DDR_B_MA8
M_CLK_DDR2 M_CLK_DDR3
M_CLK_DDR#2 M_CLK_DDR#3
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
+3VS
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
12
R229
R229
10K_0402_5%
10K_0402_5%
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013290-1
TYCO_2-2013290-1
CONN@
CONN@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
+1.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
2010/09/28
2010/09/28
2010/09/28
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11DDR_B_MA12
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4DDR_B_MA5
DDR_B_MA2DDR_B_MA3
DDR_B_MA0DDR_B_MA1
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
+VREF_CB
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK
+0.75VS
Compal Secret Data
Compal Secret Data
Compal Secret Data
DDR3_DRAMRST# <6,11,12>
DDR_CKE3_DIMMB <6>
M_CLK_DDR3 <6>
M_CLK_DDR#3 <6>
DDR_B_BS1 <6>
DDR_B_RAS# <6>
DDR_CS2_DIMMB# <6>
M_ODT2 <6>
M_ODT3 <6>
12
D_CK_SDATA <12,15>
D_CK_SCLK <12,15>
Deciphered Date
Deciphered Date
Deciphered Date
2
+1.5V
C346
1U_0402_6.3V6K
C346
1U_0402_6.3V6K
C351
1U_0402_6.3V6K
C351
1U_0402_6.3V6K
12
12
Layout Note:
+1.5V
+1.5V
12
R202
R202
1K_0402_1%
1K_0402_1%
C311
2.2U_0603_6.3V6K
C311
2.2U_0603_6.3V6K
C312
0.1U_0402_16V4Z
C312
0.1U_0402_16V4Z
12
R201
R201
12
1K_0402_1%
1K_0402_1%
2011/09/28
2011/09/28
2011/09/28
2
+0.75VS
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Place near JDIMMB
C673
10U_0603_6.3V6M
C673
10U_0603_6.3V6M
10U_0603_6.3V6M
C671
10U_0603_6.3V6M
C671
10U_0603_6.3V6M
12
C322
1U_0402_6.3V6K
C322
1U_0402_6.3V6K
12
10U_0603_6.3V6M
12
12
Layout Note:
Place near JDIMMB.203,204
C352
1U_0402_6.3V6K
C352
1U_0402_6.3V6K
12
Compal Electronics, Inc.
DDRIII DIMMB
DDRIII DIMMB
DDRIII DIMMB
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
C347
1U_0402_6.3V6K
C347
1U_0402_6.3V6K
12
C344
C344
12
C353
1U_0402_6.3V6K
C353
1U_0402_6.3V6K
12
1
DDR_B_DQS#[0..7] <6>
DDR_B_DQS[0..7] <6>
DDR_B_D[0..63] <6>
DDR_B_MA[0..15] <6>
C349
1U_0402_6.3V6K
C349
1U_0402_6.3V6K
12
C348
10U_0603_6.3V6M
C348
10U_0603_6.3V6M
C309
10U_0603_6.3V6M
C309
10U_0603_6.3V6M
12
C321
1U_0402_6.3V6K
C321
1U_0402_6.3V6K
12
1
330U_D2_2V_Y
C350
10U_0603_6.3V6M
C350
10U_0603_6.3V6M
12
330U_D2_2V_Y
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
@
@
C307
C307
C345
C345
12
12
+
+
0.1
0.1
0.1
55
13
55
13
55
13
5
PCH_RTCX1
1 2
R557 10M_0402_5%R557 10M_0402_5%
1
Y4
Y4
18P_0402_50V8J
18P_0402_50V8J
12
D D
32.768KHZ_12.5PF_9H03200413
32.768KHZ_12.5PF_9H03200413
+RTCVCC
R354 1M_0402_5%R354 1M_0402_5%
R582 330K_0402_5%R582 330K_0402_5%
*
OSC4OSC
NC3NC
C753
C753
2
1 2
1 2
INTVRMEN
H：Integrated VRM enable
L：Integrated VRM disable
PCH_RTCX2
12
C752
C752
18P_0402_50V8J
18P_0402_50V8J
SM_INTRUDER#
PCH_INTVRMEN
(INTVRMEN should always be pull high.)
+3VS
R261 @ 1K_0402_5%R261 @ 1K_0402_5%
1 2
HIGH= Enable ( No Reboot )
LOW= Disable (Default)
*
+3VALW_PCH
C C
HDA_SDO<39>
HDA_SDO
ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
*
High = Enabled [Flash Descriptor Security Overide]
+3VALW_PCH
R501 1K_0402_5%R501 1K_0402_5%
R538@
R538@
1K_0402_5%
1K_0402_5%
R535
R535
0_0402_5%
0_0402_5%
12
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when sampled high
*
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
33_0402_5%
33_0402_5%
HDA_BITCLK_AUDIO<42>
HDA_SYNC_AUDIO<42>
B B
HDA_RST_AUDIO#<42>
HDA_SDOUT_AUDIO<42>
No PCH XDP
Delete JTAG_TMS,PCH_JTAG_TDI,JTAG_TD0
W=20mils
+RTCBATT +RTCVCC +3VS
A A
R341
R341
1K_0402_5%
1K_0402_5%
1 2
33_0402_5%
33_0402_5%
1 2
33_0402_5%
33_0402_5%
1 2
33_0402_5%
33_0402_5%
1 2
trace width 10mil
D19
D19
1
12
BAS40-04_SOT23-3
BAS40-04_SOT23-3
R524
R524
R312
R312
R534
R534
Place C174 clos e to PCH.
5
12
12
HDA_SYNC
R517
R517
HDA_BIT_CLK
HDA_SYNC_R
HDA_RST#
HDA_SDOUT_R
+CHGRTC
2
3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
HDA_SPKR
HDA_SDOUT
W=20mils
1
C466
C466
2
+RTCVCC
R351 20K_0402_5%R351 20K _0402_5%
R353 20K_0402_5%R353 20K _0402_5%
12
C465
C465
1U_0603_10V4Z
1U_0603_10V4Z
1 2
1 2
1U_0603_10V4Z
1U_0603_10V4Z
C471
C471
12
ME
HDA_SPKR<42>
HDA_SDIN0<42>
Prevent back drive issue.
+3VS
G
G
S
S
1 2
R504@
R504@
0_0402_5%
0_0402_5%
12
R521
R521
1M_0402_5%
1M_0402_5%
9/29 DG1.5
CMOS
JCMOS1
SHORT PADS
JCMOS1
SHORT PADS
12
JME1
SHORT PADS
JME1
SHORT PADS
12
R520
R520
51_0402_5%
51_0402_5%
12
T22
T22
@PAD
@PAD
@PAD
@PAD
T21
T21
@PAD
@PAD
T51
T51
Q49
Q49
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
123
D
D
4
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDIN0
HDA_SDOUT
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS#
PCH_SPI_SI
PCH_SPI_SO
HDA_SYNCHDA_SYNC_R
4
U38A
U38A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
Prevent back drive issue.
G
G
2
Q51
Q51
BSS138_NL_SOT23-3
HDA_SDOUT_R HDA_SDOUT
3
S
S
1 2
R530@
R530@
0_0402_5%
0_0402_5%
BSS138_NL_SOT23-3
1
D
D
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA LPC
SATA LPC
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
3
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PCH_GPIO23
SERIRQ
SATA_COMP
SATA3_COMP
RBIAS_SATA3
PCH_SATALED#
PCH_GPIO21
PCH_GPIO19
LPC_AD0 <39>
LPC_AD1 <39>
LPC_AD2 <39>
LPC_AD3 <39>
LPC_FRAME# <39>
PCH_GPIO23 <19>
SERIRQ <39>
SATA_PRX_DTX_N0 <35>
SATA_PRX_DTX_P0 <35>
SATA_PTX_DRX_N0 <35>
SATA_PTX_DRX_P0 <35>
SATA_PRX_DTX_N2 <35>
SATA_PRX_DTX_P2 <35>
SATA_PTX_DRX_N2 <35>
SATA_PTX_DRX_P2 <35>
R258
R258
37.4_0402_1%
37.4_0402_1%
1 2
R259
R259
49.9_0402_1%
49.9_0402_1%
1 2
1 2
R492 750_0402_1%R492 750_0402_1%
@ PAD
@ PAD
+1.05VS_PCH
+1.05VS_PCH
PCH_SATALED# <41>
T50
T50
HDD
ODD
2
SERIRQ
PCH_SATALED#
PCH_GPIO21
SPI ROM FOR ME ( 4MByte )
If use SPI programmer,
R144 should be open
(Normal is pop)
+3VS
PCH_SPI_CS# P CH_SPI_CS#_R
PCH_SPI_CLK P CH_SPI_CLK_R
PCH_SPI_SI PCH_SPI_SI_R
PCH_GPIO19
Debug Port DG 1.2 PH 4.7K +3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
R249 10K_0402_5%R249 10K_0402_5%
R500 10K_0402_5%R500 10K_0402_5%
R252 10K_0402_5%R252 10K_0402_5%
R580
R580
0_0402_5%
0_0402_5%
1 2
Please short PJP35
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
R576 0_0402_5%R576 0_0402_5%
1 2
R499 0_0402_5%R499 0_0402_5%
1 2
R593 0_0402_5%R593 0_0402_5%
+3V_DSW_SPI
C755
C755
1 2
C762@
C762@
22P_0402_50V8J
22P_0402_50V8J
12
12
12
PCH_SPI_WP#
PCH_SPI_HOLD#
12
Reserve for EMI please close t o UH1
+3VS
12
R502
R502
4.7K_0402_5% @
4.7K_0402_5% @
Compal Electronics, Inc.
Title
Title
Title
PCH (1/8) SATA,HDA,SPI, LPC, XDP
PCH (1/8) SATA,HDA,SPI, LPC, XDP
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Date: Sheet of
Thursday, December 23, 2010
Date: Sheet of
Thursday, December 23, 2010
Date: Sheet of
Thursday, December 23, 2010
PCH_SPI_WP#
PCH_SPI_HOLD#
PCH_SPI_SO_R
U48
U48
8
VCC
3
W
7
HOLD
1
S
6
C
5
D
W25Q32BVSSIG
W25Q32BVSSIG
P/N:SA00003K800
R590@
R590@
33_0402_5%
33_0402_5%
PCH_SPI_CLK_R
1 2
1
+3VS
R565 3.3K_0402_5%R565 3.3K_0402_5%
1 2
R587 3.3K_0402_5%R587 3.3K_0402_5%
1 2
R577
R577
0_0402_5%
0_0402_5%
PCH_SPI_SO
1 2
4
VSS
PCH_SPI_SO_R
2
Q
14
55
14
55
14
1
55
+3VS
0.1
0.1
0.1
5
PCIE_PRX_DTX_N1<35>
PCIE LAN
Mini Card
D D
Card Reader
USB3.0
+3VS
R511 10K_0402_5%R511 10K_0402_5%
R264 10K_0402_5%R264 10K_0402_5%
+3VALW_PCH
R522 10K_0402_5%R522 10K_0402_5%
R548 10K_0402_5%R548 10K_0402_5%
R348 10K_0402_5%R348 10K_0402_5%
R350 10K_0402_5%R350 10K_0402_5%
R276 10K_0402_5%R276 10K_0402_5%
C C
R310 10K_0402_5%R310 10K_0402_5%
PCIE_PRX_DTX_P1<35>
PCIE_PTX_C_DRX_N1<35>
PCIE_PTX_C_DRX_P1<35>
PCIE_PRX_DTX_N2<36>
PCIE_PRX_DTX_P2<36>
PCIE_PTX_C_DRX_N2<36>
PCIE_PTX_C_DRX_P2<36>
PCIE_PRX_DTX_N3<38>
PCIE_PRX_DTX_P3<38>
PCIE_PTX_C_DRX_N3<38>
PCIE_PTX_C_DRX_P3<38>
PCIE_PRX_DTX_N4<44>
PCIE_PRX_DTX_P4<44>
PCIE_PTX_C_DRX_N4<44>
PCIE_PTX_C_DRX_P4<44>
12
12
12
12
12
12
12
12
MINI1_CLKREQ#
USB30_CLKREQ#
PCH_GPIO73
LAN_CLKREQ#
CARD_CLKREQ#
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46
Mini Card
USB3.0
PCIE LAN
Card Reader
B B
+3VALW_PCH
12
R313
R313
10K_0402_5%
A A
PEG_CLKREQ#_R
10K_0402_5%
for safe
5
C681 0.1U_0402_10V7KC681 0.1U_0402_10V7K
1 2
C678 0.1U_0402_10V7KC678 0.1U_0402_10V7K
1 2
C682 0.1U_0402_10V7KC682 0.1U_0402_10V7K
1 2
C683 0.1U_0402_10V7KC683 0.1U_0402_10V7K
1 2
C688 0.1U_0402_10V7KC688 0.1U_0402_10V7K
1 2
C694 0.1U_0402_10V7KC694 0.1U_0402_10V7K
1 2
C685 0.1U_0402_10V7KC685 0.1U_0402_10V7K
1 2
C684 0.1U_0402_10V7KC684 0.1U_0402_10V7K
1 2
CLK_PCIE_MINI1#<36>
CLK_PCIE_MINI1<36>
MINI1_CLKREQ#<36>
CLK_PCIE_USB30#<44>
CLK_PCIE_USB30<44>
USB30_CLKREQ#<44>
CLK_PCIE_LAN#<35>
CLK_PCIE_LAN<35>
LAN_CLKREQ#<35>
CLK_PCIE_CARD#<38>
CLK_PCIE_CARD<38>
CARD_CLKREQ#<38>
CLK_PEG_VGA#<23>
CLK_PEG_VGA<23>
2
G
G
1 3
D
S
D
R308
R308
@
@
2.2K_0402_5%
2.2K_0402_5%
S
12
VGA_ON <18,26,46,55>
Q37
OPT@
Q37
OPT@
2N7002E_SOT23-3
2N7002E_SOT23-3
12
R332
R332
@
@
2.2K_0402_5%
2.2K_0402_5%
4
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCH_GPIO73
PCH_GPIO44
PEG_CLKREQ#_R
PCH_GPIO45
PCH_GPIO46
Pull high @ VGA side
4
U38B
U38B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
PEG_CLKREQ# <23>
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
3
LID_SW_OUT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
OPTIMUS
UMA
E12
PCH_SMBCLK
H14
PCH_SMBDATA
C9
DRAMRST_CNTRL_PCH
A12
C8
G12
PCH_GPIO74
C13
PCH_SML1CLK
E14
PCH_SML1DATA
M16
M7
T11
P10
PCH_GPIO47
M10
AB37
AB38
CLK_CPU_DMI#
AV22
CLK_CPU_DMI
AU22
CLK_CPU_DPLL#
AM12
CLK_CPU_DPLL
AM13
CLK_BUF_CPU_DMI#
BF18
CLK_BUF_CPU_DMI
BE18
CLKIN_DMI2#
BJ30
CLKIN_DMI2
BG30
CLK_BUF_DREF_96M#
G24
CLK_BUF_DREF_96M
E24
CLK_BUF_PCIE_SATA#
AK7
CLK_BUF_PCIE_SATA
AK5
CLK_BUF_ICH_14M
K45
CLK_PCI_LPBACK
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
CLK_FLEX0
K43
CLK_27M_TCLK_R
F47
H47
DGPU_PRSNT#
K49
GPIO67
DGPU_PRSNT#
2010/09/28
2010/09/28
2010/09/28
0
1
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_DMI2_N
CLKIN_DMI2_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
LID_SW_OUT# <39>
PCH_SMBCLK <36>
PCH_SMBDATA <36>
DRAMRST_CNTRL_PCH <6,11,13>
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
CLK_CPU_DPLL# <5>
CLK_CPU_DPLL <5>
CLK_PCI_LPBACK <18>
R271
R271
90.9_0402_1%
90.9_0402_1%
1 2
@ PAD
@ PAD
T17
T17
R319 22_0402_5%@R319 22_0402_5%@
1 2
DGPU_PRSNT#
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+3VS
12
1 2
2
120MHz for eDP.
+1.05VS_PCH
R533
R533
10K_0402_5%
10K_0402_5%
UMA ONLY@
UMA ONLY@
R531
R531
10K_0402_5%
10K_0402_5%
OPT@
OPT@
2
CLK_27M_TCLK <23>
2011/09/28
2011/09/28
2011/09/28
1
LID_SW_OUT#
DRAMRST_CNTRL_PCH
PCH_SMBCLK
PCH_SMBDATA
PCH_GPIO74
PCH_SML1CLK
PCH_SML1DATA
PCH_GPIO47
For DDR
PCH_SMBDATA
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
PCH_SMBCLK
PCH_SML1DATA
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
PCH_SML1CLK
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLKIN_DMI2#
CLKIN_DMI2
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
CLK_BUF_ICH_14M
XTAL25_IN
XTAL25_OUT
CLK_PCI_LPBACK
6
R328 10K_0402_5%R328 10K_0402_5%
1 2
R562 1K_0402_5%R562 1 K_0402_5%
1 2
R382 2.2K_0402_5%R382 2.2K_0402_5%
1 2
R360 2.2K_0402_5%R360 2.2K_0402_5%
1 2
R561 10K_0402_5%R561 10K_0402_5%
1 2
R589 2.2K_0402_5%R589 2.2K_0402_5%
1 2
R591 2.2K_0402_5%R591 2.2K_0402_5%
1 2
R305 10K_0402_5%R305 10K_0402_5%
1 2
+3VS
Q43A
Q43A
3
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
6
Q57A
Q57A
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
1
C725
C725
2
R363
R363
4.7K_0402_5%
4.7K_0402_5%
2
1 2
1
5
1 2
4
Q43B
Q43B
+3VS
2
1
5
4
3
Q57B
Q57B
R225 10K_0402_5%R225 10K_0402_5%
1 2
R220 10K_0402_5%R220 10K_0402_5%
1 2
R480 10K_0402_5%R480 10K_0402_5%
1 2
R481 10K_0402_5%R481 10K_0402_5%
1 2
R334 10K_0402_5%R334 10K_0402_5%
1 2
R333 10K_0402_5%R333 10K_0402_5%
1 2
R242 10K_0402_5%R242 10K_0402_5%
1 2
R245 10K_0402_5%R245 10K_0402_5%
1 2
R304 10K_0402_5%R304 10K_0402_5%
1 2
1 2
R512 1M_0402_5%R512 1M_0402_5%
Y3
Y3
25MHZ_20PF_7A25000012
25MHZ_20PF_7A25000012
33P_0402_50V8J
33P_0402_50V8J
R317@
R317@
33_0402_5%
33_0402_5%
12
+3VS
D_CK_SDATA
R364
R364
4.7K_0402_5%
4.7K_0402_5%
+3VS
D_CK_SCLK
Pull up at EC side.
EC_SMB_DA2
EC_SMB_CK2
12
C723
C723
C436@
C436@
22P_0402_50V8J
22P_0402_50V8J
1 2
1
2
Reserve for EMI please close t o UH4
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
1
+3VALW_PCH
D_CK_SDATA <12,13>
D_CK_SCLK <12,13>
EC_SMB_DA2 <23,39>
EC_SMB_CK2 <23,39>
33P_0402_50V8J
33P_0402_50V8J
55
15
55
15
55
15
0.1
0.1
0.1
5
D D
@
@
R586 0_0402_5%
R586 0_0402_5%
1 2
+3VS
5
SUSACK#_R
1
IN1
VCC
OUT
2
IN2
GND
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
3
12
R563
R563
0_0402_5%
0_0402_5%
12
@
@
12
12
12
12
12
SYS_PWROKSYS_PW ROK
4
U47
U47
SYS_PWROK
XDP_DBRESET#<5>
SUSWARN#_R
PM_DRAM_PWR GD<5>
PCH_RSMRST#<39>
PM_DRAM_PWR GD
SUSWARN#_R
PCH_ACIN PCH_GPIO29
PCH_GPIO72
RI#
PBTN_OUT#<39>
PCH_PWROK<39>
VGATE<54>
C C
R585 10K_0402_5%R585 10K_0402_5%
+3VS
B B
R575 200_0402_5%R575 200_0402_5%
+3VALW_PCH
R564 10K_0402_5%R564 10K_0402_5%
R352 200K_0402_5%R352 200K_0402_5%
R323 10K_0402_5%R323 10K_0402_5%
R578 10K_0402_5%R578 10K_0402_5%
+1.05VS_PCH
PCH_PWROK
ACIN<39,46,48>
4
DMI_CTX_PRX_N0<4>
DMI_CTX_PRX_N1<4>
DMI_CTX_PRX_N2<4>
DMI_CTX_PRX_N3<4>
DMI_CTX_PRX_P0<4>
DMI_CTX_PRX_P1<4>
DMI_CTX_PRX_P2<4>
DMI_CTX_PRX_P3<4>
DMI_CRX_PTX_N0<4>
DMI_CRX_PTX_N1<4>
DMI_CRX_PTX_N2<4>
DMI_CRX_PTX_N3<4>
DMI_CRX_PTX_P0<4>
DMI_CRX_PTX_P1<4>
DMI_CRX_PTX_P2<4>
DMI_CRX_PTX_P3<4>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
1 2
DMI_IRCOMP
RBIAS_CPY
SYS_PWROK
PCH_PWROK_R PCH_GPIO29
PM_DRAM_PWR GD
PCH_RSMRST#_R
SUSWARN#_R
PBTN_OUT#_R
PCH_ACIN
1 2
R482 49.9_0402_1%R482 49.9_0402_1%
1 2
R479 750_0402_1%R479 750_0402_1%
4mil width and place
within 500mil of the
PCH
R566 0_0402_5%R566 0_0402_5%
1 2
R574 0_0402_5%R574 0_0402_5%
1 2
R365 0_0402_5%R365 0_0402_5%
1 2
D21 CH751H-40PT_SOD323-2D 21 CH751H-40PT_SOD323-2
SUSACK#_R
PCH_GPIO72
RI#
U38C
U38C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN# / SUS_PW R_DN_ACK / GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
3
DMI
DMI
System Power Management
System Power Management
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_RSMRST#_R
WAKE#
1 2
CLKRUN#
SUS_STAT#
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
SLP_A#
PM_SLP_SUS#
H_PM_SYNC
R558
R558
0_0402_5%
0_0402_5%
R303 100K_0402_5%
R303 100K_0402_5%
2
FDI_CTX_PRX_N0 <4>
FDI_CTX_PRX_N1 <4>
FDI_CTX_PRX_N2 <4>
FDI_CTX_PRX_N3 <4>
FDI_CTX_PRX_N4 <4>
FDI_CTX_PRX_N5 <4>
FDI_CTX_PRX_N6 <4>
FDI_CTX_PRX_N7 <4>
FDI_CTX_PRX_P0 <4>
FDI_CTX_PRX_P1 <4>
FDI_CTX_PRX_P2 <4>
FDI_CTX_PRX_P3 <4>
FDI_CTX_PRX_P4 <4>
FDI_CTX_PRX_P5 <4>
FDI_CTX_PRX_P6 <4>
FDI_CTX_PRX_P7 <4>
FDI_INT <4>
FDI_FSYNC0 <4>
FDI_FSYNC1 <4>
FDI_LSYNC0 <4>
FDI_LSYNC1 <4>
not support Dee p S4,S5 DPWROK mux with PWROK
check list1.0 P .42
PCH_PCIE_WAKE# <35,36,44>
T23 PADT23 PAD
SUSCLK <39>
1 2
@
@
PM_SLP_S5# <39>
PM_SLP_S4# <39>
PM_SLP_S3# <39>
T19 PADT19 PAD
T24 PADT24 PAD
H_PM_SYNC <5>
Can be left NC when IAMT is no t
support on the platfrom
not support Dee p S4,S5 can NC
PCH EDS1.2 P.74
DSWODVREN
DSWODVREN - On Die DSW VR Enab le
H：Enable
*
L：Disable
WAKE#
CLKRUN#
EC team suggest ion
South Bridge si de must have
pull-low 10K on this pin(GPIO3 2)
1
R567 330K_0402_5%R567 330K_0402_5%
R584 @ 330K_0402_5%R584 @ 330K_0402_5%
R549 10K_0402_5%R549 10K_0402_5%
R349 10K_0402_5%R349 10K_0402_5%
R510 8.2K_0402_5%R510 8.2K_0402_5%
R505 10K_0402_5%@R505 10K_0402_5%@
12
12
1 2
1 2
1 2
1 2
+RTCVCC
+3VALW_PCH
+3VS
R583 10K_0402_5%R583 10K_0402_5%
A A
12
5
PCH_RSMRST#_R
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM,
PCH (3/8) DMI,FDI,PM,
PCH (3/8) DMI,FDI,PM,
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
1
16
55
16
55
16
55
0.1
0.1
0.1
5
4
3
2
1
ENBKL
ENBKL<39>
D D
C C
B B
R539 0_0402_5%R539 0_0402_5%
+3VS
R295 2.2K_0402_5%R295 2.2K_0402_5%
1 2
R298 2.2K_0402_5%R298 2.2K_0402_5%
1 2
+3VS
R536 2.2K_0402_5%R536 2.2K_0402_5%
1 2
R532 2.2K_0402_5%R532 2.2K_0402_5%
1 2
R285 150_0402_1%R285 150_0402_1%
1 2
R284 150_0402_1%R284 150_0402_1%
1 2
R288 150_0402_1%R288 150_0402_1%
1 2
12
IGPU_BKLT_EN
R537
R537
100K_0402_5%
100K_0402_5%
1 2
CTRL_CLK
CTRL_DATA
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
Pull high at LVDS conn side.
PCH_ENVDD<32>
DPST_PWM<32>
PCH_LCD_CLK<32>
PCH_LCD_DATA<32>
2.37K_0402_1%
2.37K_0402_1%
R263
R263
0_0402_5%
0_0402_5%
R262
R262
PCH_TXCLK-<32>
PCH_TXCLK+<32>
PCH_TXOUT0-<32>
PCH_TXOUT1-<32>
PCH_TXOUT2-<32>
PCH_TXOUT0+<32>
PCH_TXOUT1+<32>
PCH_TXOUT2+<32>
PCH_CRT_B<33>
PCH_CRT_G<33>
PCH_CRT_R<33>
PCH_CRT_CLK<33>
PCH_CRT_DATA<33>
PCH_CRT_HSYNC<33>
PCH_CRT_VSYNC<33>
IGPU_BKLT_EN
12
12
PCH_TXCLKÂPCH_TXCLK+
PCH_TXOUT0ÂPCH_TXOUT1ÂPCH_TXOUT2-
PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_HSYNC
PCH_CRT_VSYNC
R287
R287
1K_0402_0.5%
1K_0402_0.5%
CTRL_CLK
CTRL_DATA
LVDS_IBG
LVD_VREF
CRT_IREF
12
U38D
U38D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
SDVO_INTN
SDVO_INTP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
SDVO_CTRLDATA strap pull high
at level shift page
SDVO_SCLK
SDVO_SDATA
PCH_DPB_HPD
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3
SDVO_SCLK <34>
SDVO_SDATA <34>
PCH_DPB_HPD <34>
PCH_DPB_N0 <34>
PCH_DPB_P0 <34>
PCH_DPB_N1 <34>
PCH_DPB_P1 <34>
PCH_DPB_N2 <34>
PCH_DPB_P2 <34>
PCH_DPB_N3 <34>
PCH_DPB_P3 <34>
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
CRT
CRT
DDPD_AUXP
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Thursday, December 23, 2010
Thursday, December 23, 2010
Thursday, December 23, 2010
1
17
17
17
55
55
55
0.1
0.1
0.1
5
+3VS
D D
C C
RP8
RP8
PCI_PIRQA#
1
8
7
6
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
8
7
6
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
8
7
6
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
R542 8.2K_0402_5%R542 8.2K_0402_5%
1 2
R540 100K_0402_5%R540 100K_0402_5%
1 2
RP6
RP6
RP9
RP9
2
3
45
1
2
3
45
1
2
3
45
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
PCH_GPIO55
PCH_GPIO51
PCH_GPIO5
PCH_GPIO52
PCH_GPIO2
PCH_GPIO53
PCH_GPIO4
ODD_DA#
DGPU_HOLD_RST#
PLT_RST#
Boot BIOS Strap bit1 BBS1
Boot BIOS
Bit10
1
1
0
Destination
Reserved
PCI
SPI
LPC
CLK_PCI_LPBACK<15>
CLK_PCI_LPC<39>
PLT_RST#
DGPU_HOLD_RST#
CLK_PCI_LPBACK
CLK_PCI_LPC
Bit11
GNT1#/
GPIO51
B B
A A
0
110
0
4
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
DGPU_HOLD_RST#
PCH_GPIO52
VGA_ON<15,26,46,55>
ODD_DA#<35>
T18 @PAD T18 @PAD
PLT_RST#<5,35,38,39,44>
R316 22_0402_5%R316 22_0402_5%
R309 22_0402_5%R309 22_0402_5%
1 2
1
2
U45
U45
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
OPT@
OPT@
VGA_ON
PCH_GPIO51
PCH_GPIO53
PCH_GPIO55
PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5
PLT_RST#
12
T52 @PAD T52 @PAD
T16 @PAD T16 @PAD
T20 @PAD T20 @PAD
+3VS
5
IN1
VCC
OUT
IN2
GND
3
4
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4
12
100K_0402_5%
100K_0402_5%
U38E
U38E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ32
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG32
TP32
AV26
TP33
BB26
TP34
AU28
TP35
AY30
TP36
AU26
TP37
AY26
TP38
AV28
TP39
AW30
TP40
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
R291OPT@
R291OPT@
100_0402_5%
100_0402_5%
1 2
R523OPT@
R523OPT@
NVRAM
NVRAM
RSVD
RSVD
PCI
PCI
USB
USB
PLTRST_VGA# <23>
3
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQS0
NV_DQS1
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
NV_ALE
NV_CLE
NV_RCOMP
NV_RB#
NV_RE#_WRB0
NV_RE#_WRB1
NV_WE#_CK0
NV_WE#_CK1
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
PLT_RST#
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
DF_TVS
AY1
AV10
AT8
AY5
BA2
AT12
BF3
USB20_N0
C24
USB20_P0
A24
USB20_N1
C25
USB20_P1
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
Some PCH config not support USB port 6 & 7.
M28
USB20_N8
L30
USB20_P8
K30
G30
E30
USB20_N10
C30
USB20_P10
A30
L32
K32
G32
E32
USB20_N13
C32
USB20_P13
A32
USBRBIAS
C33
B33
USB_OC0#
A14
USB_OC1#
K20
USB_OC2#
B17
USB_OC3#
C16
USB_OC4#
L16
USB_OC5#
A16
USB_OC6#
D14
USB_OC7#
C14
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
Within 500 mils
R559 22.6_0402_ 1%R559 22.6_0402_ 1%
0_0402_5%
0_0402_5%
+3VS
5
1
IN1
2
IN2
3
U46
U46
USB20_N0 <37>
USB20_P0 <37>
USB20_N1 <37>
USB20_P1 <37>
USB20_N8 <36>
USB20_P8 <36>
USB20_N10 <32>
USB20_P10 <32>
USB20_N13 <37>
USB20_P13 <37>
1 2
R545@
R545@
VCC
OUT
GND
12
4
12
R555
R555
100K_0402_5%
100K_0402_5%
USB/B (Right side)
USB/B (Right side)
Mini Card (WLAN)
CMOS Camera (LVDS)
Bluetooth
2
USB_OC0# <37>
PLT_RST_BUF# <36>
1
DMI Termination Voltage
DF_TVS
Set to Vcc when HIGH
Set to Vss when LOW
DG1.2 CRB1.0 PH 2.2K series 1K
+1.8VS
12
R490
R490
2.2K_0402_5%
2.2K_0402_5%
DF_TVS
R489 1K_0402_5%R489 1K_0402_5%
12
CLOSE TO THE BRANCHING POINT
RP11
USB_OC7#
USB_OC1#
USB_OC4#
USB_OC6#
USB_OC2#
USB_OC5#
USB_OC3#
USB_OC0#
RP11
4 5
3
2
1
10K_1206_8P4R_5%
10K_1206_8P4R_5%
RP10
RP10
4 5
3
2
1
10K_1206_8P4R_5%
10K_1206_8P4R_5%
H_SNB_IVB# <5 >
+3VALW_PCH
6
7
8
6
7
8
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Compal Electronics, Inc.
Title
Title
Title
PCH (5/9) PCI, USB, NVRAM
PCH (5/9) PCI, USB, NVRAM
PCH (5/9) PCI, USB, NVRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Date: Sheet of
Thursday, December 23, 2010
Date: Sheet of
Thursday, December 23, 2010
Date: Sheet of
Thursday, December 23, 2010
1
55
18
55
18
55
18
0.1
0.1
0.1
+3VS
UMA ONLY@
UMA ONLY@
R503 10K_0402_5%
R503 10K_0402_5%
R506 10K_0402_5%OPT@R 506 10K_0402_5%OPT@
1 2
* OPTIMUS
D D
Non-OPTIMUS
5
12
OPTIMUS_EN#
GPIO38
OPTIMUS_EN#
0
1
4
3
2
ODD_EN#
EC_KBRST#
1
R573 10K_0402_5%R573 10K_0402_5%
1 2
R279 10K_0402_5%R279 10K_0402_5%
1 2
+3VS
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
H
：：：：
On-Die PLL voltage regulator enable
*
L
：：：：
On-Die PLL Voltage Regulator disable
+3VALW_PCH
R296 4.7K_0402_5%@R 296 4.7K_0402_5%@
1 2
@
@
R290
R290
1K_0402_5%
1K_0402_5%
Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
No use PD to GND Check list1.0 P.70
C C
B B
A A
R322 10K_0402_5%R322 10K_0402_5%
1 2
+3VS
R266 10K_0402_5%R266 10K_0402_5%
R570 10K_0402_5%R570 10K_0402_5%
1 2
R314 10K_0402_5%R314 10K_0402_5%
1 2
R495 10K_0402_5%R495 10K_0402_5%
1 2
R569 10K_0402_5%R569 10K_0402_5%
1 2
R300 100K_0402_5%R300 100K_0402_5%
1 2
R268 200K_0402_5%R268 200K_0402_5%
1 2
R518 10K_0402_5%R518 10K_0402_5%
1 2
R256 10K_0402_5%R256 10K_0402_5%
1 2
R497 10K_0402_5%R497 10K_0402_5%
1 2
+3VALW_PCH
R543 10K_0402_5%R543 10K_0402_5%
1 2
R541 1K_0402_5%R541 1K_0402_5%
1 2
R315 10K_0402_5%R315 10K_0402_5%
1 2
R320 10K_0402_5%R320 10K_0402_5%
1 2
+3VS
R270 10K_0402_5%X7 6@R270 10K_0402_5%X76@
1 2
R289 10K_0402_5%X7 6@R289 10K_0402_5%X76@
1 2
R340 10K_0402_5%X7 6@R340 10K_0402_5%X76@
1 2
R339 10K_0402_5%X7 6@R339 10K_0402_5%X76@
1 2
12
12
PCH_GPIO28
PCH_GPIO0
PCH_GPIO1
DGPU_HPD_INT#
PCH_GPIO16
DGPU_PWROK
GPIO37
ODD_DETECT#
BT_ON#
PCH_GPIO48
WL_OFF#
PCH_GPIO12
SMIB
PCH_GPIO57
PCH_GPIO24
PCH_GPIO22
PCH_GPIO23
PCH_GPIO27
CRB1.0 PH200K to +3VS
CRB1.0 PH10K to +3VALW
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.
PCH_GPIO23 <14>
+1.5VSDGPU
Modify R02
+3VS
12
R594
R594
10K_0402_5%
10K_0402_5%
1
C
C
Q60
Q60
PDTC143TT_SOT23-3
PDTC143TT_SOT23-3
2
B
B
E
E
3
2
G
G
+3VS
12
13
D
D
S
S
R568
R568
10K_0402_5%
10K_0402_5%
Q61
Q61
2N7002E_SOT23-3
2N7002E_SOT23-3
DGPU_HPD_INT#<34>
EC_SCI#<39>
EC_SMI#<39>
SMIB<44>
BT_ON#<36,37>
ODD_DETECT#<35>
WL_OFF#<36>
PCH_GPIO0
PCH_GPIO1
DGPU_HPD_INT#
EC_SCI#
EC_SMI#
PCH_GPIO12
SMIB
PCH_GPIO16
DGPU_PWROK
PCH_GPIO22
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
BT_ON#
ODD_DETECT#
GPIO37
OPTIMUS_EN#
PCH_GPIO39
PCH_GPIO48
WL_OFF#
PCH_GPIO57
T58 @PAD T58 @PAD
T68 @PAD T68 @PAD
T67 @PAD T67 @PAD
T66 @PAD T66 @PAD
T60 @PAD T60 @PAD
T62 @PAD T62 @PAD
T57 @PAD T57 @PAD
T65 @PAD T65 @PAD
T47 @PAD T47 @PAD
T48 @PAD T48 @PAD
T46 @PAD T46 @PAD
T40 @PAD T40 @PAD
T45 @PAD T45 @PAD
T41 @PAD T41 @PAD
U38F
U38F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
ODD_EN#
A20GATE
PECI
RCIN#
THRMTRIP#
INIT3_3V#
NC_1
NC_2
NC_3
NC_4
NC_5
C40
PCH_GPIO69
B41
PCH_GPIO70
C41
PCH_GPIO71
A40
P4
PCH_PECI_R
AU16
EC_KBRST#
P5
AY11
PCH_THRMTRIP#_R
AY10
T14
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
PROCPWRGD
GPIO
GPIO
CPU/MISC
CPU/MISC
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
NCTF
NCTF
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
0_0402_5% R487
0_0402_5%
T39@ PADT39@ PAD
T42@ PADT42@ PAD
T38@ PADT38@ PAD
T30@ PADT30@ PAD
T36@ PADT36@ PAD
T44@ PADT44@ PAD
T31@ PADT31@ PAD
T43@ PADT43@ PAD
T35@ PADT35@ PAD
T34@ PADT34@ PAD
T55@ PADT55@ PAD
T64@ PADT64@ PAD
T56@ PADT56@ PAD
T63@ PADT63@ PAD
T53@ PADT53@ PAD
T61@ PADT61@ PAD
T54@ PADT54@ PAD
T59@ PADT59@ PAD
ODD_EN# <35>
T69@ PADT69@ PAD
T70@ PADT70@ PAD
@
@
1 2
R487
1 2
R488 390_0402_5%R488 390_0402_5%
H_PECI < 5,39>
EC_KBRST# <39>
H_CPUPWRGD <5>
H_THRMTRIP#
+3VS
INIT3_3V
This signal has weak internal
PU, can't pull low
Intel schematic reviwe recommand.
Follow P5WE0 R02
10K_0402_5% X76@
10K_0402_5% X76@
PCH_GPIO71
10K_0402_5% X76@
10K_0402_5% X76@
VRAM 800 MHz
VRAM 900 MHz
R294
R294
10K_0402_5%
10K_0402_5%
1 2
R571
R571
R572
R572
+3VS
12
1 2
GATEA20 <39>
H_THRMTRIP# <5>
GPIO71
PCH_GPIO71
0
1
R515 10K_0402_5%@R515 10K_0402_5%@
1 2
R513 10K_0402_5%R513 10K_0402_5%
1 2
5
PCH_GPIO39
on board ram flag
GPIO22
GPIO23
GPIO39
Samsung 2G
0
0
0
Hynix 2G Nanya 2G Micron 2G
0
1
0
4
1
0
0
Security Classification
Security Classification
1
1
0
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Wednesday, December 29, 2010
Wednesday, December 29, 2010
Wednesday, December 29, 2010
1
19
19
19
55
55
55
0.1
0.1
0.1
5
4
3
2
1
POWER
2925mA
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
60mA
DMI
DMI
190mA
NAND / SPI HVCMOS
NAND / SPI HVCMOS
20mA
1mA
VCCADAC
VSSADAC
1mA
VCCALVDS
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCIO[1]
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
20mA
VCCSPI
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
+VCCADAC
12
+VCCTX_LVDS
12
C366
C366
0.01U_0402_16V7K
0.01U_0402_16V7K
+3VS
12
+VCCAFDI_VRM
+1.8VS
12
12
0.1U_0402_10V7K
0.1U_0402_10V7K
C730
0.01U_0402_16V7K
C730
0.01U_0402_16V7K
12
C405
C405
0.1U_0402_10V7K
0.1U_0402_10V7K
C378
C378
0.1U_0402_10V7K
0.1U_0402_10V7K
C396
C396
1U_0402_6.3V6K
1U_0402_6.3V6K
C729
C729
12
12
C368
C368
0.01U_0402_16V7K
0.01U_0402_16V7K
+1.05VS_PCH
12
C363
C363
1U_0402_6.3V6K
1U_0402_6.3V6K
+3VS
L42
L42
MBK1608221YZF_2P
MBK1608221YZF_2P
C731
C731
10U_0805_6.3V6M
10U_0805_6.3V6M
+3VS
12
+3VS
12
L39
0.1UH_MLF1608DR10KT_10%_1608
0.1UH_MLF1608DR10KT_10%_1608
22U_0805_6.3V6M
22U_0805_6.3V6M
C701
C701
L39
0.1uH inductor, 200mA
+1.8VS
12
+1.05VS_VCCP
D D
C C
B B
JP2@
JP2@
12
C679
10U_0805_6.3V6M
C679
10U_0805_6.3V6M
C379
1U_0402_6.3V6K
C379
1U_0402_6.3V6K
12
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
T33 @PAD T33 @PAD
C374
C374
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
C328
C328
0.1U_0402_10V7K
0.1U_0402_10V7K
T37 @PAD T37 @PAD
+1.05VS_PCH
C369
C369
PAD-OPEN 4x4m
PAD-OPEN 4x4m
This pin can be left as no connect in
On-Die VR enabled mode (default).
+1.05VS_PCH
C680
10U_0805_6.3V6M
C680
10U_0805_6.3V6M
12
+3VS
+1.05VS_PCH
C375
1U_0402_6.3V6K
C375
1U_0402_6.3V6K
12
+1.05VS_PCH
+VCCAPLLEXP
C373
1U_0402_6.3V6K
C373
1U_0402_6.3V6K
12
+1.05VS_VCCAPLL_FDI
12
C380
1U_0402_6.3V6K
C380
1U_0402_6.3V6K
12
C372
1U_0402_6.3V6K
C372
1U_0402_6.3V6K
12
+VCCAFDI_VRM
C362
C362
1U_0402_6.3V6K
1U_0402_6.3V6K
U38G
U38G
1300mA
AA23
VCCCORE[1]
AC23
VCCCORE[2]
AD21
VCCCORE[3]
AD23
VCCCORE[4]
AF21
VCCCORE[5]
AF23
VCCCORE[6]
AG21
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9]
AG26
VCCCORE[10]
AG27
VCCCORE[11]
AG29
VCCCORE[12]
AJ23
VCCCORE[13]
AJ26
VCCCORE[14]
AJ27
VCCCORE[15]
AJ29
VCCCORE[16]
AJ31
VCCCORE[17]
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VCCFDIPLL
AP17
VCCIO[27]
AU20
VCCDMI[2]
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
PCH Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1.05
1.05
1.05
1.05
S0 Iccmax
Current
(A)
0.001
5
5
0.001
0.001
0.266
0.001
0.08
0.08
1.3
0.042
1.05Vcc IO 2.925
1.05Vcc ASW 1.01
3.3VccSPI 0.02
3.3VccDSW 0.003
1.8 0.19VccpNAND
3.3VccRTC 6 uA
3.3VccSus3_3
3.3 / 1.5VccSusHDA
0.119
0.01
VccVRM 1.8 / 1.5 0.16
1.05Vcc CLKDMI
0.02
VccSSC 1.05 0.095
VccDIFFCLKN 1.05 0.055
VccALVDS 3.3
0.001
1.8VccTX_LVDS 0.06
+1.5VS
R237 0_0603_5%R237 0_0603_5%
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec
A A
5
12
4
+VCCAFDI_VRM
+VCCAFDI_VRM
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/09/28
2010/09/28
2010/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2011/09/28
2011/09/28
2011/09/28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (7/9) PWR
PCH (7/9) PWR
PCH (7/9) PWR
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
P4LS0 M/B LA-7241P Schematic
Friday, November 19, 2010
Friday, November 19, 2010
Friday, November 19, 2010
1
55
20
55
20
55
20
0.1
0.1
0.1
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