COMPAL LA-7204P Schematics

A

1 1

B

C

D

E

PWWHA

2 2

Delhi 10RG

LA-7204P SchematicREV 0.1

3 3

4 4

Intel Processor(Sandy Bridge) / PCH(Cougar Point)

2010-12-19 Rev 0.1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

153Thursday, January 13, 2011

E

A

of

A

B

C

D

E

Fan Control Circuit

page 5

PCI-Express 8X 2.5GHz

Intel CPU Sandy Bridge

1 1

rPGA-989

37.5mm*37.5mm

page 5,6,7,8,9,10

FDI X8

2.7GT/s

DMI X4

5GT/s

VGA Board(GDDR3)

CRT

2 2

790MHz

page 13,14,15,16,17,18

NVIDIA N12M-GE-S-B1 BGA 533P

page 20

LVDS Conn.

page 19

Intel PCH Cougar Point - M

FCBGA-989

25mm*25mm

page 21,22,23,24,25,26,27,28,29

RJ45

page 33

RTL8105E 10/100M

PCIe port 1

page 33

PCIe 1x

1.5V 5GT/s

HDMI Conn.

3 3

page 30

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

USB Right/Left

USB port 0,1

USB

5V 480MHz

page 31,35

PCIeMini Card

USB

5V 480MHz

PCIe 1x

1.5V 5GT/s

SATA port 0

5V 6GHz(600MB/s)

SATA port 2

5V 3GHz(300MB/s)

WiMax PCIeMini Card

WLAN

SATA HDD

SATA ODD

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

USB port 9

page 32

PCIe port 9

page 32

SATA port 1

page 31

SATA port 4

page 31

Card Reader 2IN1 RTS5137

USB port 10

page 34

Int. Camera

page 11,12

USB port 11

page 19

LPC BUS

RTC CKT.

page 21

DC/DC Interface CKT.

page 41

Power Circuit DC/DC

4 4

page 42,43,44,45, 46,47,48,49,50

Power/B

page 40

A

SPI ROM (4MB)

page 21

B

Debug Port

page 39

Touch Pad

page 40

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3.3V 33 MHz

ENE KB930

2010/09/03 2012/12/31

C

page 38

Int.KBD

page 39

Compal Secret Data

HD Audio

EC ROM (128KB)

page 39

Deciphered Date

3.3V 24MHz

MIC Conn

D

Int.

HDA Codec

ALC259-VB5-GR QFN 48P

page 36

SPK Conn

page 37page 37

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

HP Conn

page 37

SCHEMATICS,MB A7204

4019CU

E

of

253Thursday, January 13, 2011

of

253Thursday, January 13, 2011

of

253Thursday, January 13, 2011

A

B+

B

Ipeak=5A, Imax=3.5A, Iocp min=7.9A

C

DESIGN CURRENT 0.1A

DESIGN CURRENT 10A

+3VL +5VALW

D

E

SUSP#

SY8033BDBC

1 1

SUSP

N-CHANNEL

DESIGN CURRENT 1.8A

DESIGN CURRENT 5.5A

+1.8VS

+5VS

SI4800

Ipeak=5A, Imax=3.5A, Iocp min=7.7A

DESIGN CURRENT 6A

+3VALW

WOL_EN#

P-CHANNEL

AO-3413

VGA_ENVDD

P-CHANNEL

AO-3413

TPS51125ARGER

SUSP

N-CHANNEL

SI4800

SUSP or 0.75VR_EN#

G2992F1U

2 2

DESIGN CURRENT 330mA

DESIGN CURRENT 4.5A

DESIGN CURRENT 2A

DESIGN CURRENT 0.5A

+3V_LAN

+3VS

+LCD_VDD

+0.75VS

VR_ON

Ipeak=53A, Imax=36A, Iocp min=70A

DESIGN CURRENT 53A

+CPU_CORE

ISL95831CRZ-T

SUSP#

TPS51218DSCR

Ipeak=20A, Imax=14A, Iocp min=26A

DESIGN CURRENT 21A

+VGA_CORE

SUSP#

Ipeak=12.5A, Imax=8.75A, Iocp min=21.4A

TPS5117

DESIGN CURRENT 17A

+1.05VS_VCCP

VCCPPWRGD

3 3

TPS51117

SYSON

TPS51117RGYR

Ipeak=6A, Imax=4.2A, Iocp min=7.76A

Ipeak=16.5A, Imax=11.55A, Iocp min=21.03A

SUSP

N-CHANNEL

DESIGN CURRENT 6A

DESIGN CURRENT 20A

DESIGN CURRENT 2A

+VCCSA

+1.5V

+1.5V_CPU

FDS6676AS

SUSP

N-CHANNEL

DESIGN CURRENT 0.7A

+1.5VS

FDS6676AS

VGA_PWROK#

4 4

A

N-CHANNEL FDS6676AS

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DESIGN CURRENT 3A

2010/09/03 2012/12/31

C

+1.5V_MEM_GFX

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

353Thursday, January 13, 2011

E

A

of

A

B

C

D

E

Voltage Rails

1 1

State

power plane

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+3VL

+5VALW +3VALW +VSB

+1.5V

+5VS +3VS +1.8VS +1.5VS +1.05VS +0.75VS +CPU_CORE +GFX_CORE

BTO Option Table

Function

DIS only

description

S0

2 2

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O O O O O O

O O O O O

X

O O O O O

X

O O O O

X X

O

XX X XX

OO OO

X

explain

BTO

Function

description

explain

BTO

DIS@

PCH

Q65R3@

MINI PCI-E SLOT

SLOT1

WIMAX

WIMAX@

HDMI

HDMI@

10/100M Giga

8105ELDO@ 8111E@

LAN

Camera & Mic

CAM@8105ESWR@

PCH SM Bus Address

3 3

Power

+3VS +3VS +3VS

Device

DDR SO-DIMM 0 DDR SO-DIMM 1 WLAN/WIMAX

EC SM Bus1 Address

Device Address Address

+3VL

4 4

A

HEX HEX

16 H

HEX

0001 0110 bSmart Battery

Address

1010 0000 bA0 H 1010 0100 bA4 H

PowerPower

+3VS

EC SM Bus2 Address

Device

96 H

B

1001 0110 bPCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

2010/09/03 2012/12/31

C

SIGNAL

Compal Secret Data

SLP_S3#

HIGH HIGHHIGH

LOW

LOW LOW

Deciphered Date

SLP_S4# SLP_S5#

HIGH HIGHHIGH

HIGH

LOW LOWLOW

D

HIGH

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

453Thursday, January 13, 2011

of

E

of

A

@

1 1

C4871000P_0402_50V7K

12

C4881000P_0402_50V7K

12

PM_DRAM_PWRGD_R

H_PWRGOOD

H_SNB_IVB#<25>

B

T1 PADT1 PAD

T2 PADT2 PAD

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

JCPUB

PROC_SELECT#

C26

AN34

AL33

SNB_IVB#

SKTOCC#

CATERR#

C

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

100 MHz

A28 A27

120 MHz

A16 A15

CLK_CPU_DMI CLK_CPU_DMI#

CLK_CPU_DPLL CLK_CPU_DPLL#

D

CLK_CPU_DMI <22> CLK_CPU_DMI# <22>

E

Stuff R41 and R42 if do not support eDP

+1.05VS_VCCP

CLK_CPU_DPLL# CLK_CPU_DPLL

R42 1K_0402_5%R42 1K_0402_5%

1 2

R41 1K_0402_5%R41 1K_0402_5%

1 2

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

EN_DFAN1<38>

H_DRAMRST#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_PRDY#_R XDP_PREQ#_R

XDP_TCK_R XDP_TMS_R XDP_TRST#_R

XDP_TDI_R XDP_TDO_R

XDP_DBRESET#_R

XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R

+FAN2

10mil

H_DRAMRST# <7>

R1437 140_0402_1%R1437 140_0402_1% R1438 25.5_0402_1%R1438 25.5_0402_1% R1439 200_0402_1%R1439 200_0402_1%

12 12 12

R1 0_0402_5%@R1 0_0402_5%@

1 2

R2 0_0402_5%@R2 0_0402_5%@

1 2

R4 0_0402_5%@R4 0_0402_5%@

1 2

R6 0_0402_5%@R6 0_0402_5%@

1 2

R7 0_0402_5%@R7 0_0402_5%@

1 2

R8 0_0402_5%@R8 0_0402_5%@

1 2

R10 0_0402_5%@R10 0_0402_5%@

1 2

R11 0_0402_5%@R11 0_0402_5%@

1 2

R12 0_0402_5%@R12 0_0402_5%@

1 2

R13 0_0402_5%@R13 0_0402_5%@

1 2

R15 0_0402_5%@R15 0_0402_5%@

1 2

R18 0_0402_5%@R18 0_0402_5%@

1 2

FAN Control Circuit (RPM and PWM)

+5VS

1A

U1

1

EN

2

VIN

3

VOUT

4

VSET

1

APL5607KI-TRG_SO8

C17

C17 10U_0805_10V6K

10U_0805_10V6K

2

FAN Control Circuit

+5VS

R1445

1A

1 2

0_0603_5%

2

C902

C902 10U_0805_10V6K

10U_0805_10V6K

1

D

FAN_SPEED1<38>

+FAN1

40 mil

DDR3 Compensation Signals Layout Note:Place these resistors near Processor

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

10U_0805_10V6K

8

GND

7

GND

6

GND

5

GND

+5VS

C13

Routed as a single daisy chain

R36

1 2

1K_0402_5%

+FAN2

2

C15

C15 1000P_0402_50V7K

1000P_0402_50V7K @

@

1

+3VS

12

R1444

R1444 10K_0402_5%

10K_0402_5%

FANPWM<38>

+FAN1

1

C899

0.01U_0402_25V7K

0.01U_0402_25V7K @

@

2

D85

1 2

1SS355_SOD323-2

BAS16_SOT23-3

D86

12

C900

C900 10U_0805_10V6K

10U_0805_10V6K

+3VS

XDP_DBRESET# <23>

1 2 3

4 5

ACES_85204-0300N

R24 10K_0402_5%@R24 10K_0402_5%@

12

FAN_SPEED1

1

C14

0.01U_0402_25V7K

0.01U_0402_25V7K @

@

2

FANPWM

ACES_85204-0400N

2

1

1000P_0402_50V7K

2

Close to Connector

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

553Thursday, January 13, 2011

E

of

JFAN2

1 2 3

GND GND

1 2 3 4

C901

JFAN

1 2 3 4

+3VS

@JFAN2

@

@JFAN

@

A

R450

H_PECI

H_PROCHOT#_R

56_0402_5%

H_THERMTRIP#

H_PECI<38>

H_PROCHOT#<38,43>

H_THERMTRIP#<26>

1 2

Remove R14(o ohm) for HW Review demand

+1.05VS_VCCP

R47 62_0402_5%R47 62_0402_5%

2 2

R51 10K_0402_5%R51 10K_0402_5%

PM_PWROK<23,38>

DRAMPWROK<23>

3 3

12

C93

0.1U_0402_16V4Z

R312

1 2

0_0402_5%

1 2

Buffered Reset to CPU

PLT_RST# <13,25,32,33,35,38,39>

U3

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

4 4

VCC

OUT

5

4

A

H_PROCHOT#

H_PWRGOOD

12

U10

PS3@

74AHC1G09GW_TSSOP5

5

PS3@

1

P

B

2

A

R384

WPS3@

SUSP<9,32,41>

+3VS

0.1U_0402_16V4Z

1

C84

2

BUFO_CPU_RST# BUF_CPU_RST#

O

PS3@

G

3

0_0402_5%

+1.05VS_VCCP

PM_SYS_PWRGD_BUF

4

SUSP

12

R69

R69 75_0402_5%

75_0402_5%

R155

43_0402_1%

1 2

H_PM_SYNC<23>

H_PWRGOOD<26>

1 2

R454 130_0402_5%R454 130_0402_5%

+1.5V_CPU+3VALW

12

R339

R339 200_0402_5%

200_0402_5%

12

R340

R340 39_0402_5%

39_0402_5% @

@

13

D

Q5

Q5 2N7002_SOT23

2N7002_SOT23

2

G

@

G

@

S

PU/PD for JTAG signals

XDP_TMS_R XDP_TDI_R XDP_TDO XDP_TCK_R XDP_TRST#_R

XDP Connector

12

R209

R209 0_0402_5%

0_0402_5% @

@

B

H_PM_SYNC

H_PWRGOOD

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

R28 51_0402_5%R28 51_0402_5% R29 51_0402_5%R29 51_0402_5% R30 51_0402_5%R30 51_0402_5% R31 51_0402_5%R31 51_0402_5% R32 51_0402_5%R32 51_0402_5%

PBTN_OUT#<23,38>

CFG0<10>

VGATE<23,38,49>

CLK_CPU_ITP<22> CLK_CPU_ITP#<22> +1.05VS_VCCP

0.1U_0402_10V6K

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

Sandy Bridge_rPGA_Rev0p61 @

12 12 12 12 12

H_PWRGOOD XDP_CPU_HOOK0 PBTN_OUT# CFG0 VGATE

PLT_RST#

1

C8

C8 @

@

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.05VS_VCCP

R35 1K_0402_5%@R35 1K_0402_5%@

1 2

R152 0_0402_5%@R152 0_0402_5%@

1 2

R37 1K_0402_5%@R37 1K_0402_5%@

1 2

R451 0_0402_5%@R451 0_0402_5%@

1 2

@

1 2

R40 1K_0402_5%

Issued Date

XDP_PREQ# XDP_PRDY#

XDP_BPM#0 XDP_BPM#1

XDP_BPM#2 XDP_BPM#3

XDP_CPU_HOOK1 XDP_CPU_HOOK2 XDP_CPU_HOOK3 CLK_CPU_ITP CLK_CPU_ITP#

XDP_CPU_HOOK6 XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

XDP_TCK

2010/09/03 2012/12/31

C

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY# PREQ#

TCK TMS

TRST#

TDI

TDO

DBR#

BPM#[0]

JTAG & BPM

MOLEX 52435-2671

BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

JXDP

@

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

27 28

Compal Secret Data

Deciphered Date

A

B

C

D

E

+1.05VS_VCCP

R34

24.9_0402_1%

JCPUA

1 1

DMI_PTX_CRX_N0<23> DMI_PTX_CRX_N1<23> DMI_PTX_CRX_N2<23> DMI_PTX_CRX_N3<23>

DMI_PTX_CRX_P0<23> DMI_PTX_CRX_P1<23> DMI_PTX_CRX_P2<23> DMI_PTX_CRX_P3<23>

DMI_CTX_PRX_N0<23> DMI_CTX_PRX_N1<23> DMI_CTX_PRX_N2<23> DMI_CTX_PRX_N3<23>

DMI_CTX_PRX_P0<23> DMI_CTX_PRX_P1<23> DMI_CTX_PRX_P2<23> DMI_CTX_PRX_P3<23>

FDI_CTX_PRX_N0<23> FDI_CTX_PRX_N1<23> FDI_CTX_PRX_N2<23>

2 2

+1.05VS_VCCP

3 3

+1.05VS_VCCP

FDI_CTX_PRX_N3<23> FDI_CTX_PRX_N4<23> FDI_CTX_PRX_N5<23> FDI_CTX_PRX_N6<23> FDI_CTX_PRX_N7<23>

FDI_CTX_PRX_P0<23> FDI_CTX_PRX_P1<23> FDI_CTX_PRX_P2<23> FDI_CTX_PRX_P3<23> FDI_CTX_PRX_P4<23> FDI_CTX_PRX_P5<23> FDI_CTX_PRX_P6<23> FDI_CTX_PRX_P7<23>

FDI_FSYNC0<23> FDI_FSYNC1<23>

FDI_INT<23> FDI_LSYNC0<23>

FDI_LSYNC1<23>

R9 24.9_0402_1%R9 24.9_0402_1%

1 2

R33 10K_0402_5%

@

12

DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3

DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

EDP_COMP

Reserve R33 for HW Review demand eDP_COMP signals should be

shorted near balls and routed with typical impedance <25m ohm

JCPUA

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61 @

DMI

Intel(R) FDI

eDP

PEG_ICOMPO

PEG_RCOMPO

PCI EXPRESS* - GRAPHICS

PEG_ICOMPI

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_COMP

PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_N15

PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_P15

PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P15

C29 .1U_0402_16V7KC29 .1U_0402_16V7K

1 2

C30 .1U_0402_16V7KC30 .1U_0402_16V7K

1 2

C31 .1U_0402_16V7KC31 .1U_0402_16V7K

1 2

C32 .1U_0402_16V7KC32 .1U_0402_16V7K

1 2

C33 .1U_0402_16V7KC33 .1U_0402_16V7K

1 2

C34 .1U_0402_16V7KC34 .1U_0402_16V7K

1 2

C35 .1U_0402_16V7KC35 .1U_0402_16V7K

1 2

C36 .1U_0402_16V7KC36 .1U_0402_16V7K

1 2

C45 .1U_0402_16V7KC45 .1U_0402_16V7K

1 2

C46 .1U_0402_16V7KC46 .1U_0402_16V7K

1 2

C47 .1U_0402_16V7KC47 .1U_0402_16V7K

1 2

C48 .1U_0402_16V7KC48 .1U_0402_16V7K

1 2

C49 .1U_0402_16V7KC49 .1U_0402_16V7K

1 2

C50 .1U_0402_16V7KC50 .1U_0402_16V7K

1 2

C51 .1U_0402_16V7KC51 .1U_0402_16V7K

1 2

C52 .1U_0402_16V7KC52 .1U_0402_16V7K

1 2

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

PCIE_GTX_C_CRX_N[8..15] <13>

PCIE_GTX_C_CRX_P[8..15] <13>

PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N15

PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P15

PCIE_CTX_C_GRX_N[8..15] <13>

PCIE_CTX_C_GRX_P[8..15] <13>

4 4

Security Classification

2010/09/03 2012/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

653Thursday, January 13, 2011

E

A

of

A

JCPUC

DDR_A_D[0..63]<11>

JCPUC

B

C

JCPUD

DDR_B_D[0..63]<12>

JCPUD

D

E

DDRA_CLK0

AB6

SA_CLK[0]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5

1 1

2 2

3 3

DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

F10

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AJ5 AJ6 AJ8

AK8

AJ9 AK9 AH8 AH9 AL9 AL8

AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9

F9

F7 G8 G7

K4

K5

K1

J1 J5 J4 J2

K2 M8

N8

N7 M9

N9 M7

V6

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CLK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CLK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]

SA_ODT[0]

SA_ODT[1] SA_ODT[2] SA_ODT[3]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

DDRA_CLK0#

AA6

DDRA_CKE0

V9

DDRA_CLK1 DDRB_CLK1

AA5

DDRA_CLK1# DDRB_CLK1#

AB5

DDRA_CKE1 DDRB_CKE1

V10

AB4 AA4 W9

AB3 AA3 W10

DDRA_SCS0# DDRB_SCS0#

AK3

DDRA_SCS1#

AL3 AG1 AH1

DDRA_ODT0 DDRB_ODT0

AH3

DDRA_ODT1

AG3 AG2 AH2

DDR_A_DQS#0

C4

DDR_A_DQS#1

G6

DDR_A_DQS#2

J3

DDR_A_DQS#3

M6

DDR_A_DQS#4

AL6

DDR_A_DQS#5

AM8

DDR_A_DQS#6

AR12

DDR_A_DQS#7

AM15

DDR_A_DQS0

D4

DDR_A_DQS1

F6

DDR_A_DQS2

K3

DDR_A_DQS3

N6

DDR_A_DQS4

AL5

DDR_A_DQS5

AM9

DDR_A_DQS6

AR11

DDR_A_DQS7

AM14

DDR_A_MA0

AD10

DDR_A_MA1

W1

DDR_A_MA2

W2

DDR_A_MA3

W7

DDR_A_MA4

V3

DDR_A_MA5

V2

DDR_A_MA6

W3

DDR_A_MA7

W6

DDR_A_MA8

V1

DDR_A_MA9

W5

DDR_A_MA10

AD8

DDR_A_MA11

V4

DDR_A_MA12

W4

DDR_A_MA13

AF8

DDR_A_MA14

V5

DDR_A_MA15

V7

DDRA_CLK0 <11> DDRB_CLK0 <12> DDRA_CLK0# <11> DDRA_CKE0 <11> DDRB_CKE0 <12>

DDRA_CLK1 <11> DDRA_CLK1# <11> DDRB_CLK1# <12> DDRA_CKE1 <11>

DDRA_SCS0# <11> DDRA_SCS1# <11> DDRB_SCS1# <12>

DDRA_ODT0 <11> DDRB_ODT0 <12> DDRA_ODT1 <11> DDRB_ODT1 <12>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7

AA10

AB8 AB9

J10

M5 N4 N2 N1 M4 N5 M2 M1

C9 A7

C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2

J7 J8

K9

J9

K8 K7

R6

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CLK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CLK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3]

SB_ODT[0]

SB_ODT[1] SB_ODT[2] SB_ODT[3]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDRB_CLK0 DDRB_CLK0# DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDRB_CLK0# <12>

DDRB_CLK1 <12> DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

Sandy Bridge_rPGA_Rev0p61 @

+1.5V

R466

R466 0_0402_5%WPS3@

0_0402_5%WPS3@

1 2

Q14

D

S

D

S

1 2

13

BSS138_NL_SOT23-3

G

PS3@

2

C140

1 2

0.047U_0402_25V6K

0.047U_0402_25V6K PS3@

PS3@

4 4

H_DRAMRST#<5>

R464

4.99K_0402_1%

PS3@

DRAMRST_CNTRL_PCH<22>

A

1 2

R463 0_0402_5%

DRAMRST_CNTRL

1K_0402_5%

DDR3_DRAMRST#_RH_DRAMRST#

12

R465

R467

PS3@

B

R467 1K_0402_5%

1K_0402_5%

1 2

SM_DRAMRST# <11,12>

Security Classification

2010/09/03 2012/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Sandy Bridge_rPGA_Rev0p61 @

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

753Thursday, January 13, 2011

E

A

of

A

B

C

D

E

+CPU_CORE

JCPUF

53A (SV 35W)

AG35

VCC1

AG34

VCC2

1 1

2 2

3 3

4 4

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev0p61 @

POWER

PEG AND DDR

CORE SUPPLY

VSS_SENSE_VCCIO

SENSE LINES SVID

A

8.5A

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

22U_0805_6.3V6M

AH13 AH10

C146

AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11

C147

H14 H12 H11 G14 G13

22U_0805_6.3V6M

G12 F14 F13 F12 F11 E14 E12

Bottom Socket Cavity x 5

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

VCCIO_SENSE

B10 A10

R102

R102 0_0402_5%

0_0402_5%

1 2

22U_0805_6.3V6M

1

C144

C143

2

22U_0805_6.3V6M

1

C145

C163

@

2

22U_0805_6.3V6M

12

R70

R70 130_0402_5%

130_0402_5%

R65 0_0402_5%R65 0_0402_5%

1 2

R52 0_0402_5%R52 0_0402_5%

1 2

R105

R105 100_0402_1%

100_0402_1% @

@

1 2

+1.05VS_VCCP

Close to CPU

B

TOP Socket Cavity x 7

22U_0805_6.3V6M

1

2

1

2

R67 43_0402_1%R67 43_0402_1% R63 0_0402_5%R63 0_0402_5% R66 0_0402_5%R66 0_0402_5%

C137

C141

2

22U_0805_6.3V6M

1

C153

C160

@

2

22U_0805_6.3V6M

+1.05VS_VCCP+1.05VS_VCCP

1 2 1 2 1 2

VCCIO_SENSE <47>

1

C136

2

22U_0805_6.3V6M

1

C152

@

2

12

close to CPU

R68

R68 75_0402_5%

75_0402_5%

Pull high resistor on VR side

+CPU_CORE

R64

R64 100_0402_1%

100_0402_1%

1 2

12

R62

R62 100_0402_1%

100_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

22U_0805_6.3V6M

1

C135

C134

2

22U_0805_6.3V6M

1

C138

C139

@

2

22U_0805_6.3V6M

ESR 9mohm

330U_D2_2V_Y

VR_SVID_ALRT# <49> VR_SVID_CLK <49> VR_SVID_DAT <49>

Close to CPU

+1.05VS_VCCP

+1.05VS_VCCP Decoupling:

22U_0805_6.3V6M

1

C133

C142

2

22U_0805_6.3V6M

1

C132

@

2

22U_0805_6.3V6M

330U_D2_2V_Y

1

+

C12

@+C12

C10

2

@

C11

2

VCCSENSE <49> VSSSENSE <49>

2010/09/03 2012/12/31

C

2X 330U (6m ohm), 12X 22U

1

2

+CPU_CORE

10U_0805_10V6K

1

C101

C102

1

+

330U_D2_2V_Y

2

9/02 Add C898 3Pin Bulk Cap by Power Demand 9/02 Change C890, C891, C894 from SGA00005R00 to SGA00004X80 for Power demand

Compal Secret Data

Deciphered Date

2

10U_0805_10V6K

+CPU_CORE

C159

22U_0805_6.3V6M

+CPU_CORE

C158

22U_0805_6.3V6M

1

2

1

2

+CPU_CORE Decoupling: 4X 470U (4m ohm), 16X 22U, 10X 10U

Bottom Socket Cavity

10U_0805_10V6K

1

C103

2

10U_0805_10V6K

1

C104

2

1

C105

2

10U_0805_10V6K

1

C106

2

1

C107

2

10U_0805_10V6K

1

C108

2

Top Socket Edge

22U_0805_6.3V6M

1

C130

2

22U_0805_6.3V6M

1

C129

2

22U_0805_6.3V6M

1

C124

C123

2

22U_0805_6.3V6M

1

C122

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

C151

9/02 Remove C126, C131 by Power Demand

Top Socket Cavity

22U_0805_6.3V6M

1

C128

2

22U_0805_6.3V6M

1

C127

2

22U_0805_6.3V6M

1

C120

C118

2

22U_0805_6.3V6M

1

C119

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

C150

Bottom Socket Edge

+CPU_CORE

1

+

C2

330U_D2_2V_Y

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

2

Compal Electronics, Inc.

SCHEMATICS,MB A7204

1

C109

2

10U_0805_10V6K

22U_0805_6.3V6M

1

C125

C121

2

22U_0805_6.3V6M

1

C117

2

330U_D2_2V_Y

1

+

C5

2

330U_D2_2V_Y

4019CU

10U_0805_10V6K

1

C110

2

1

@

2

1

+

C7

2

E

1

C111

@

2

10U_0805_10V6K

1

+

C9

2

330U_D2_2V_Y

853Thursday, January 13, 2011

1

2

330U_D2_2V_Y

1

+

C3

2

of

A

JCPUG

AT24

VAXG1

AT23

VAXG2

AT21

R14

R14 0_0402_5%

0_0402_5%

1 1

2 2

1 2

AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18

AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17

AK24

AK23

AK21

AK20

AK18

AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

33A

VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

R76

10U_0805_10V6K

3 3

4 4

12

0_0805_5%

330U_B2_2.5VM_R15M

C185

C185 @

@

1

+

2

C186

+1.8VS_VCCPLL

1

C206

2

1U_0402_6.3V6K

1

C230

C230 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1.2A

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev0p61 @

B

POWER

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

VCCSA_VID0

1.8V RAIL

08/18 Reserve R119 to follow CRB 1.0

VAXG_SENSE

SM_VREF

5A

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

6A

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

FC_C22

VCCSA_VID1

C

AK35 AK34

+V_SM_VREF should have 20 mil trace width

+V_SM_VREF_CNT +V_SM_VREF

AL1

12

R486

C148

@

100K_0402_5%

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

10U_0805_10V6K

1

0.1U_0402_16V4Z

2

10U_0805_10V6K

C114

R111

0_0402_5%

12

2

@

@ AP2302GN-HF_SOT23-3

AP2302GN-HF_SOT23-3

1

RUN_ON_CPU1.5VS3

1

C115

2

10U_0805_10V6K

Q2

C116

3

Bottom Socket Cavity

10U_0805_10V6K

M27 M26 L26 J26 J25 J24 H26 H25

10U_0805_10V6K

C100

10U_0805_10V6K

1

2

C447

10U_0805_10V6K

1

C476

2

10U_0805_10V6K

C477

@

Bottom Socket Edge

VCCSA_SENSE

H23

C22 C24

VCCSA_VID0

R114

10K_0402_5%

1 2

0_0402_5% @

R119

1 2

R95

@

1 2

+1.5V_CPU Decoupling: 1X 330U (6m ohm), 6X 10U

+1.5V_CPU

1

+

C875

C875 330U_2.5V_M_R17

330U_2.5V_M_R17

ESR 17mohm

2

10U_0805_10V6K

1

C154

C149

2

10U_0805_10V6K

12

R252

R252 1K_0402_5%

1K_0402_5%

1

2

10U_0805_10V6K

1

C155

2

+VCCSA Decoupling: 1X 330U (6m ohm), 3X 10U

+VCCSA

VCCSA_SENSE

1 2

R253 0_0402_5%R253 0_0402_5%

1

+

C877

C877 330U_2.5V_M_R17

330U_2.5V_M_R17 @

@

2

VCCSA_SENSE <46>

VCCSAP_VID1 <46>

+1.5V_CPU +1.5V

PS3@

C213 0.1U_0402_16V4Z

1 2

PS3@

C212 0.1U_0402_16V4Z

1 2

PS3@

C211 0.1U_0402_16V4Z

1 2

PS3@

C210 0.1U_0402_16V4Z

1 2

SUSP

R122

1K_0402_5%

470_0805_5%

D

PJ32

2

112

@

JUMP_43X118

@

8/20 Add PJ32 for Cost down +1.5V to +1.5V_CPU

0

1

0

1

0

11

1

C179

@ C179

R449

5

@

1 2 34

@

Q46B

2N7002KDWH_SOT363-6

10U_0805_10V4K

2

0.1U_0402_25V6

C472

+1.5VS

+1.5V_CPU

1

@

2

+VCCSAVCCSA_VID0 VCCSA_VID1

0.90 V

0.80 V

0.75 V

0.65 V

PJ30

@PJ30

@

2

112

JUMP_43X118

JUMP_43X118 Q33

@Q33

@

1

S

D

2

S

D

3

S

D

4

G

D

FDS6676AS_SO8

RUN_ON_CPU1.5VS3

12

R420

R420 820K_0402_5%@

820K_0402_5%@

For Sandy Bridge

+1.5V+1.5V_CPU

8 7 6 5

1 2

220K_0402_5%

61

Q46A

@

2N7002KDWH_SOT363-6

2

E

R455

@R455

@

+VSB

SUSP

SUSP <5,32,41>

Security Classification

2010/09/03 2012/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

953Thursday, January 13, 2011

E

A

of

A

JCPUH

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

1 1

2 2

3 3

4 4

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

Sandy Bridge_rPGA_Rev0p61 @

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

B

JCPUI

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

Sandy Bridge_rPGA_Rev0p61 @

VSS

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267

B19

VSS268

B17

VSS269

B15

VSS270

B13

VSS271

B11

VSS272

B9

VSS273

B8

VSS274

B7

VSS275

B5

VSS276

B3

VSS277

B2

VSS278

A35

VSS279

A32

VSS280

A29

VSS281

A26

VSS282

A23

VSS283

A20

VSS284

A3

VSS285

PEG DEFER TRAINING

CFG7

C

JCPUE

CFG0<5>

T5 PADT5 PAD T6 PADT6 PAD T7 PADT7 PAD T11 PADT11 PAD T12 PADT12 PAD T15 PADT15 PAD T18 PADT18 PAD T16 PADT16 PAD T19 PADT19 PAD T21 PADT21 PAD T20 PADT20 PAD T44 PADT44 PAD T45 PADT45 PAD T46 PADT46 PAD T47 PADT47 PAD T26 PADT26 PAD T27 PADT27 PAD

T22 PADT22 PAD T24 PADT24 PAD T25 PADT25 PAD T23 PADT23 PAD

R115

1K_0402_1%

1: (Default) PEG Train immediately following xxRESETB de assertion

12

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

CPU_RSVD6 CPU_RSVD7

12

R116

R116 1K_0402_1%

1K_0402_1%

CFG7

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

RSVD1

AH31

RSVD2

AJ33

RSVD3

AH33

RSVD4

AJ26

RSVD5

SA_DIMM_VREFDQ

B4

RSVD6

D1

RSVD7

SB_DIMM_VREFDQ

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

RSVD26

VCCIO_SEL

J15

RSVD27

Sandy Bridge_rPGA_Rev0p61 @

12

R258

R258 1K_0402_1%

1K_0402_1% @

@

D

RSVD28 RSVD29 RSVD30 RSVD31 RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

RESERVED

RSVD51 RSVD52

RSVD53

RSVD54 RSVD55

RSVD56 RSVD57 RSVD58

0: PEG Wait for BIOS for training

KEY

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

B1

E

CFG Straps for Processor

(CFG[17:0] internal pull high to VCCIO)

CFG2

PEG Static Lane Reversal

- CFG2 is for the 16x

*

1: Normal Operation;

CFG2

Lane # definition matches socket pin map definition

12

R254

R254 1K_0402_1%

1K_0402_1%

0:Lane Reversed

T28 PADT28 PAD

CLK_RES_ITP <22> CLK_RES_ITP# <22>

CFG4

Embedded Display Port Presence Strap

CFG4

CFG6 CFG5

1K_0402_1%

12

R255

R255 1K_0402_1%

1K_0402_1% @

@

1 : Disabled; No

*

Physical Display Port attached to mbedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

12

R256

R257

R256 1K_0402_1%

1K_0402_1% @

@

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1

*

function 1 enabled ; function 2 disabled

CFG[6:5]

01: Reserved (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Security Classification

2010/09/03 2012/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

10 53Thursday, January 13, 2011

E

A

of

A

+VREF_DQA

1

C156

C157

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

1 1

Close to JDDRL.1

DDR_A_BS2<7>

2 2

DDRA_CLK0<7> DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

3 3

+3VS

C181

4 4

C181

2.2U_0603_6.3V6K

1 C182

C182

2

1

2

R90

R90 10K_0402_5%

10K_0402_5%

1

2

0.1U_0402_16V4Z

A

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDRA_CLK0

DDRA_CLK0# DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDRA_SCS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

1 2

+0.75VS

12

R91

R91 10K_0402_5%

10K_0402_5%

+1.5V

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205 207

JDDRL

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

GND1 GND2

FOX_AS0A626-U2SN-7F_204P

FOX_AS0A626-U2SN-7F_204P @

@

DQS0#

DQS0

DQ12 DQ13

RESET#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

CKE1

CK1#

RAS#

ODT0 ODT1

VREF_CA

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

EVENT#

BOSS1 BOSS2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS DM1

VSS

VSS DM2 VSS

VSS

VDD

VDD CK1

VDD BA1

VDD

VDD VSS

VSS DM4 VSS

VSS

VSS DM6 VSS

VSS

VSS SDA

SCL VTT

A15 A14

A11

A7 A6

A4 A2

A0

S0#

NC

B

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26 28

SM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44 46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDRA_CKE1

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100

DDRA_CLK1

102

DDRA_CLK1#

104 106

DDR_A_BS1

108

DDR_A_RAS#

110 112

DDRA_SCS0#

114

DDRA_ODT0

116 118

DDRA_ODT1

120 122 124

+VREF_CAA

126 128

DDR_A_D36

130

DDR_A_D37

132 134 136 138

DDR_A_D38

140

DDR_A_D39

142 144

DDR_A_D44

146

DDR_A_D45

148 150

DDR_A_DQS#5

152

DDR_A_DQS5

154 156

DDR_A_D46

158

DDR_A_D47

160 162

DDR_A_D52

164

DDR_A_D53

166 168 170 172

DDR_A_D54

174

DDR_A_D55

176 178

DDR_A_D60

180

DDR_A_D61

182 184

DDR_A_DQS#7

186

DDR_A_DQS7

188 190

DDR_A_D62

192

DDR_A_D63

194 196 198

PM_SMBDATA

200

PM_SMBCLK

202 204

+0.75VS

206 208

B

DDR3 SO-DIMM A Reverse Type

SM_DRAMRST# <7,12>

DDRA_CKE1 <7>DDRA_CKE0<7>

DDRA_CLK1 <7> DDRA_CLK1# <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDRA_SCS0# <7> DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

C161

2.2U_0603_6.3V6K

close to JDDRL.126

PM_SMBDATA <12,22,32> PM_SMBCLK <12,22,32>

1

C162

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_A_DQS[0..7] <7> DDR_A_DQS#[0..7] <7> DDR_A_D[0..63] <7> DDR_A_MA[0..15] <7>

+VREF_DQA

+1.5V

12

R80

1K_0402_1%

12

R82

1K_0402_1%

Layout Note: Place near JDDRL

Change C218 to OSCON at DVT

+1.5V

@

+

C218 390U_2.5V_M_R10

1 2

C166 10U_0603_6.3V6MC166 10U_0603_6.3V6M

1 2

C168 10U_0603_6.3V6MC168 10U_0603_6.3V6M

1 2

C171 10U_0603_6.3V6MC171 10U_0603_6.3V6M

1 2

C174 10U_0603_6.3V6MC174 10U_0603_6.3V6M

1 2

C176 10U_0603_6.3V6MC176 10U_0603_6.3V6M

1 2

C178 10U_0603_6.3V6MC178 10U_0603_6.3V6M

1 2

Compal Secret Data

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

D

+1.5V

12

R79

1K_0402_1%

12

R81

1K_0402_1%

Layout Note: Place near JDDRL1.203 and 204

+1.5V +0.75VS

C164 0.1U_0402_16V4ZC164 0.1U_0402_16V4Z

1 2

C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z

1 2

C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z

1 2

C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

E

C165 10U_0603_6.3V6MC165 10U_0603_6.3V6M

1 2

C169 1U_0402_6.3V6KC169 1U_0402_6.3V6K

12

C172 1U_0402_6.3V6KC172 1U_0402_6.3V6K

12

C175 1U_0402_6.3V6KC175 1U_0402_6.3V6K

12

C177 1U_0402_6.3V6KC177 1U_0402_6.3V6K

12

of

11 53Thursday, January 13, 2011

E

A

+VREF_DQB

1

C183

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

1 1

Close to JDDRH.1

DDRB_CKE0<7>

DDR_B_BS2<7>

2 2

DDRB_CLK0<7> DDRB_CLK0#<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDRB_SCS1#<7>

3 3

+3VS

2.2U_0603_6.3V6K

4 4

C207

1

@

2

1

2

0.1U_0402_16V4Z

1

C184

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

R98

R98 10K_0402_5%

10K_0402_5%

R99

1 2

10K_0402_5%

C208

C208 @

@

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDRB_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDRB_CLK0

DDRB_CLK0# DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDRB_SCS1#

DDR_B_D37 DDR_B_D36

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D54 DDR_B_D55

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

1 2

A

+0.75VS

+1.5V

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205 207

JDDRH

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

GND1 GND2

FOX_AS0A626-UASN-7F_204P

FOX_AS0A626-UASN-7F_204P @

@

DQS0#

DQS0

DQ12 DQ13

RESET#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

CKE1

CK1#

RAS#

ODT0 ODT1

VREF_CA

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

EVENT#

BOSS1 BOSS2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS DM1

VSS

VSS DM2 VSS

VSS

VDD

VDD CK1

VDD BA1

VDD

VDD VSS

VSS DM4 VSS

VSS

VSS DM6 VSS

VSS

VSS SDA

SCL VTT

A15 A14

A11

A7 A6

A4 A2

A0

S0#

NC

B

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26 28

SM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44 46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDRB_CKE1

74 76

DDR_B_MA15

78

DDR_B_MA14

80 82

DDR_B_MA11

84

DDR_B_MA7

86 88

DDR_B_MA6

90

DDR_B_MA4

92 94

DDR_B_MA2

96

DDR_B_MA0

98 100

DDRB_CLK1

102

DDRB_CLK1#

104 106

DDR_B_BS1

108

DDR_B_RAS#

110 112

DDRB_SCS0#

114

DDRB_ODT0

116 118

DDRB_ODT1

120 122 124

+VREF_CAB

126 128

DDR_B_D32

130

DDR_B_D33

132 134 136 138

DDR_B_D38

140

DDR_B_D39

142 144

DDR_B_D44

146

DDR_B_D45

148 150

DDR_B_DQS#5

152

DDR_B_DQS5

154 156

DDR_B_D46

158

DDR_B_D47

160 162

DDR_B_D52

164

DDR_B_D53

166 168 170 172

DDR_B_D50

174

DDR_B_D51

176 178

DDR_B_D60

180

DDR_B_D61

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196 198

PM_SMBDATA

200

PM_SMBCLK

202 204

+0.75VS

206 208

B

SM_DRAMRST# <7,11>

DDRB_CKE1 <7>

DDRB_CLK1 <7> DDRB_CLK1# <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>DDR_B_BS0<7>

DDRB_SCS0# <7> DDRB_ODT0 <7>

DDRB_ODT1 <7>

C187

Close to JDDRH.126

PM_SMBDATA <11,22,32> PM_SMBCLK <11,22,32>

Reverse Type DDR3 SO-DIMM B

+VREF_DQB

1

C188

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_B_DQS#[0..7] <7> DDR_B_DQS[0..7] <7> DDR_B_D[0..63] <7> DDR_B_MA[0..15] <7>

+1.5V

12

R83

1K_0402_1%

12

R84

1K_0402_1%

+1.5V

12

R86

1K_0402_1%

12

R94

1K_0402_1%

Layout Note: Place near JDDRH

+1.5V

C192 10U_0603_6.3V6MC192 10U_0603_6.3V6M

1 2

C194 10U_0603_6.3V6MC194 10U_0603_6.3V6M

1 2

C197 10U_0603_6.3V6MC197 10U_0603_6.3V6M

1 2

C200 10U_0603_6.3V6MC200 10U_0603_6.3V6M

1 2

C202 10U_0603_6.3V6MC202 10U_0603_6.3V6M

1 2

C204 10U_0603_6.3V6MC204 10U_0603_6.3V6M

1 2

Compal Secret Data

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

D

C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z

1 2

C196 0.1U_0402_16V4ZC196 0.1U_0402_16V4Z

1 2

C199 0.1U_0402_16V4ZC199 0.1U_0402_16V4Z

1 2

D

E

Layout Note: Place near JDDRH.203 and 204

+0.75VS+1.5V

C191 10U_0603_6.3V6MC191 10U_0603_6.3V6M

1 2

C195 1U_0402_6.3V6KC195 1U_0402_6.3V6K

12

C198 1U_0402_6.3V6KC198 1U_0402_6.3V6K

12

C201 1U_0402_6.3V6KC201 1U_0402_6.3V6K

12

C203 1U_0402_6.3V6KC203 1U_0402_6.3V6K

12

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

12 53Thursday, January 13, 2011

E

of

A

PCIE_CTX_C_GRX_P[8..15]<6> PCIE_CTX_C_GRX_N[8..15]<6> PCIE_GTX_C_CRX_P[8..15]<6> PCIE_GTX_C_CRX_N[8..15]<6>

1 1

2 2

PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_N11 PCIE_GTX_CRX_N11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_P15

3 3

PCIE_GTX_C_CRX_N15

Differential signal

PLT_RST#<5,25,32,33,35,38,39>

4 4

PCIE_CTX_C_GRX_P[8..15] PCIE_CTX_C_GRX_N[8..15] PCIE_GTX_C_CRX_P[8..15] PCIE_GTX_C_CRX_N[8..15]

CV18 .1U_0402_16V7KCV18 .1U_0402_16V7K CV19 .1U_0402_16V7KCV19 .1U_0402_16V7K CV20 .1U_0402_16V7KCV20 .1U_0402_16V7K CV21 .1U_0402_16V7KCV21 .1U_0402_16V7K CV22 .1U_0402_16V7KCV22 .1U_0402_16V7K CV23 .1U_0402_16V7KCV23 .1U_0402_16V7K CV24 .1U_0402_16V7KCV24 .1U_0402_16V7K CV25 .1U_0402_16V7KCV25 .1U_0402_16V7K CV26 .1U_0402_16V7KCV26 .1U_0402_16V7K CV27 .1U_0402_16V7KCV27 .1U_0402_16V7K CV28 .1U_0402_16V7KCV28 .1U_0402_16V7K CV29 .1U_0402_16V7KCV29 .1U_0402_16V7K CV30 .1U_0402_16V7KCV30 .1U_0402_16V7K CV31 .1U_0402_16V7KCV31 .1U_0402_16V7K CV32 .1U_0402_16V7KCV32 .1U_0402_16V7K CV33 .1U_0402_16V7KCV33 .1U_0402_16V7K

+3VS

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

CLK_PCIE_VGA<22>

CLK_PCIE_VGA#<22>

1 2

RV13 200_0402_1%@RV13 200_0402_1%@

RV15 2.49K_0402_1%RV15 2.49K_0402_1%

1 2

RV18 0_0402_5%RV18 0_0402_5%

1 2

RV21 10K_0402_5%RV21 10K_0402_5%

PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15

PCIE_GTX_CRX_P8 PCIE_GTX_CRX_N8 PCIE_GTX_CRX_P9 PCIE_GTX_CRX_N9 PCIE_GTX_CRX_P10 PCIE_GTX_CRX_N10 PCIE_GTX_CRX_P11

PCIE_GTX_CRX_P12 PCIE_GTX_CRX_N12 PCIE_GTX_CRX_P13 PCIE_GTX_CRX_N13 PCIE_GTX_CRX_P14 PCIE_GTX_CRX_N14 PCIE_GTX_CRX_P15 PCIE_GTX_CRX_N15

PEX_TSTCLK_OUT PEX_TSTCLK_OUT# XTALSSIN

12

CLK_REQ#

R39 0_0402_5%

@

1 2

R405

10_0402_5%

@

10P_0402_50V8J

C88

B

UV1A

AE12

PEX_RX0

AF12

PEX_RX0_N

AG12

PEX_RX1

AG13

PEX_RX1_N

AF13

PEX_RX2

AE13

PEX_RX2_N

AE15

PEX_RX3

AF15

PEX_RX3_N

AG15

PEX_RX4

AG16

PEX_RX4_N

AF16

PEX_RX5

AE16

PEX_RX5_N

AE18

PEX_RX6

AF18

PEX_RX6_N

AG18

PEX_RX7

AG19

PEX_RX7_N

AF19

PEX_RX8

AE19

PEX_RX8_N

AE21

PEX_RX9

AF21

PEX_RX9_N

AG21

PEX_RX10

AG22

PEX_RX10_N

AF22

PEX_RX11

AE22

PEX_RX11_N

AE24

PEX_RX12

AF24

PEX_RX12_N

AG24

PEX_RX13

AF25

PEX_RX13_N

AG25

PEX_RX14

AG26

PEX_RX14_N

AF27

PEX_RX15

AE27

PEX_RX15_N

AD10

PEX_TX0

AD11

PEX_TX0_N

AD12

PEX_TX1

AC12

PEX_TX1_N

AB11

PEX_TX2

AB12

PEX_TX2_N

AD13

PEX_TX3

AD14

PEX_TX3_N

AD15

PEX_TX4

AC15

PEX_TX4_N

AB14

PEX_TX5

AB15

PEX_TX5_N

AC16

PEX_TX6

AD16

PEX_TX6_N

AD17

PEX_TX7

AD18

PEX_TX7_N

AC18

PEX_TX8

AB18

PEX_TX8_N

AB19

PEX_TX9

AB20

PEX_TX9_N

AD19

PEX_TX10

AD20

PEX_TX10_N

AD21

PEX_TX11

AC21

PEX_TX11_N

AB21

PEX_TX12

AB22

PEX_TX12_N

AC22

PEX_TX13

AD22

PEX_TX13_N

AD23

PEX_TX14

AD24

PEX_TX14_N

AE25

PEX_TX15

AE26

PEX_TX15_N

AB10

PEX_REFCLK

AC10

PEX_REFCLK_N

AF10

PEX_TSTCLK_OUT

AE10

PEX_TSTCLK_OUT_N

AG10

PEX_TERMP

AD9

PEX_RST_N

AE9

PEX_CLKREQ_N

N12M-GE-S-B1 BGA 533P

CLK_27MCLK_27M_IN

12

1

@

2

Part 1 of 5

CLK_27M <22>

Near GPU

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11

GPIO

GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19

DACA_HSYNC

DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_VREF DACA_RSET

DACB_HSYNC

DACB_VSYNC

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_VREF DACB_RSET

PCI EXPRESS

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

TEST

TESTMODE

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2C DACADACB

GPIO20 GPIO21

I2CS_SCL

I2CS_SDA

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

CLK

N1 G1 C1 M2 M3 K3 K2 J2 C2 M1 D2 D1 J3 J1 K1 F3 G3 G2 F1 F2

AD2 AD1

AE2 AD3 AE3

AF1 AE1

U6 U4

T5 R4 T4

R6 V6

AF3 AG4 AE4 AF4 AG3

AD25

R1 T3

R2 R3

A2 B1

A3 A4

T1 T2

D11 E9 E10 D10

I2CB_SCL I2CB_SDA

C

VGA_PWM VGA_ENVDD VGA_ENBKL GPU_VID0 GPU_VID1

GPU_GPIO8 GPU_GPIO9

GPU_GPIO12

TV8@TV8@

DACA_VREF DACA_RSET

GPU_JTAG_TCK GPU_JTAG_TDI GPU_JTAG_TDO GPU_JTAG_TMS GPU_JTAG_TRST#

GPU_TESTMODE

I2CH_SCL I2CH_SDA

GPU_SMBCLK GPU_SMBDAT

XTALOUTBUFF NV_CLK_27M_OUT CLK_27M_IN

CLK_27M_IN

27MHZ_16PF_X5H027000FG1H

1

CV34

2

18P_0402_50V8J

VGA_PWM <19> VGA_ENVDD <19> VGA_ENBKL <38> GPU_VID0 <50> GPU_VID1 <50>

HDMI_HPD <26,30>

VGA_CRT_HSYNC <20> VGA_CRT_VSYNC <20>

VGA_CRT_R <20>

VGA_CRT_B <20>

VGA_CRT_G <20>

CV13 0.1U_0402_16V4ZCV13 0.1U_0402_16V4Z

1 2

RV6 124_0402_1%RV6 124_0402_1%

TV1@TV1@ TV2@TV2@ TV3@TV3@ TV4@TV4@

1 2

RV9 1K_0402_1%RV9 1K_0402_1%

VGA_CRT_CLK <20>

VGA_CRT_DATA <20>

LCD_EDID_CLK <19>

LCD_EDID_DATA <19>

1 2

RV12 10K_0402_5%RV12 10K_0402_5%

1 2

RV16 10K_0402_5%RV16 10K_0402_5%

YV1

1 2

1

CV35

2

FERMI Changed

NV_CLK_27M_OUT

18P_0402_50V8J

2.2K_0402_5%

GPU_SMBCLK

GPU_SMBDAT

D

VGA_CRT_CLK VGA_CRT_DATA I2CH_SCL I2CH_SDA I2CB_SCL I2CB_SDA GPU_GPIO8 GPU_GPIO9 GPU_GPIO12 LCD_EDID_CLK LCD_EDID_DATA

VGA_PWM VGA_ENBKL

HDMI_HPD

VGA_CRT_R VGA_CRT_G VGA_CRT_B

GPU_TESTMODE

+3VS

RV22

1 2

R25 100K_0402_5%

Close to GPU

RV3 150_0402_1%RV3 150_0402_1%

1 2

RV4 150_0402_1%RV4 150_0402_1%

1 2

RV5 150_0402_1%RV5 150_0402_1%

+3VS

RV25

2.2K_0402_5%

QV1A

1 2

12

RV7

@ RV7

@ 10K_0402_5%

10K_0402_5%

12

RV8

RV8 10K_0402_5%

10K_0402_5%

+3VS

2

2N7002KDWH_SOT363-6

61

2N7002KDWH_SOT363-6

5

1 2 1 2

1 2 1 2 1 2 1 2

1 2 1 2

@

QV1B

34

+3VS

RV234.7K_0402_5% RV234.7K_0402_5%

12

RV244.7K_0402_5% RV244.7K_0402_5%

12

RV10010K_0402_5% @RV10010K_0402_5% @

12

RV10110K_0402_5% @ RV10110K_0402_5% @

12

RV272.2K_0402_5% RV272.2K_0402_5% RV282.2K_0402_5% RV282.2K_0402_5% RV10210K_0402_5% RV10210K_0402_5%

12

RV2610K_0402_5% RV2610K_0402_5% RV2910K_0402_5% RV2910K_0402_5% RV142.2K_0402_5% RV142.2K_0402_5% RV172.2K_0402_5% RV172.2K_0402_5%

RV1010K_0402_5% RV1010K_0402_5% RV1110K_0402_5% RV1110K_0402_5%

EC_SMB_CK2 <22,38>

EC_SMB_DA2 <22,38>

E

Security Classification

2010/09/03 2012/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

13 53Thursday, January 13, 2011

E

A

of

A

UV1C

LCD_TXCLK+<19> LCD_TXCLK-<19>

LCD_TXOUT0+<19>

LCD_TXOUT0-<19>

LCD_TXOUT1+<19>

LCD_TXOUT1-<19>

LCD_TXOUT2+<19>

@

RV50

1 2

34.8K_0402_1%

RV56

34.8K_0402_1%

1 2

VGA_HDMI_CLK<30> VGA_HDMI_DATA<30>

VGA_HDMI_TX2+<30>

VGA_HDMI_TX2-<30>

VGA_HDMI_TX1+<30>

VGA_HDMI_TX1-<30>

VGA_HDMI_TX0+<30>

VGA_HDMI_TX0-<30>

VGA_HDMI_CLK+<30>

VGA_HDMI_CLK-<30>

HDMI@

1 2

HDMI@

1 2

LCD_TXOUT2-<19>

RV51

15K_0402_1%

1 2

RV57

@

4.99K_0402_1%

1 2

RV97

@

10K_0402_1%

1 2

RV41

4.99K_0402_1%

1 2

VGA_HDMI_CLK

VGA_HDMI_DATA

RV98

@

10K_0402_1%

RV99

20K_0402_1%

1 2

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

1 2

VGA_HDMI_CLK VGA_HDMI_DATA VGA_HDMI_TX2+ VGA_HDMI_TX2VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_CLK+ VGA_HDMI_CLK-

+3VS

1 1

RV49

1 2

45.3K_0402_1%

RV55

@

4.99K_0402_1%

1 2

2 2

+3VS

RV119 4.7K_0402_5%

3 3

RV120 4.7K_0402_5%

AC4

IFPA_TXC

AD4

IFPA_TXC_N

V5

IFPA_TXD0

V4

IFPA_TXD0_N

AA5

IFPA_TXD1

AA4

IFPA_TXD1_N

W4

IFPA_TXD2

Y4

IFPA_TXD2_N

AB4

IFPA_TXD3

AB5

IFPA_TXD3_N

AB3

IFPB_TXC

AB2

IFPB_TXC_N

W1

IFPB_TXD4

V1

IFPB_TXD4_N

W3

IFPB_TXD5

W2

IFPB_TXD5_N

AA2

IFPB_TXD6

AA3

IFPB_TXD6_N

AB1

IFPB_TXD7

AA1

IFPB_TXD7_N

G4

IFPC_AUX_I2CW_SCL

G5

IFPC_AUX_I2CW_SDA_N

P4

IFPC_L0

N4

IFPC_L0_N

M5

IFPC_L1

M4

IFPC_L1_N

L4

IFPC_L2

K4

IFPC_L2_N

H4

IFPC_L3

J4

IFPC_L3_N

D3

IFPD_AUX_I2CX_SCL

D4

IFPD_AUX_I2CX_SDA_N

F5

IFPD_L0

F4

IFPD_L0_N

E4

IFPD_L1

D5

IFPD_L1_N

C3

IFPD_L2

C4

IFPD_L2_N

B3

IFPD_L3

B4

IFPD_L3_N

F7

IFPE_AUX_I2CY_SCL

G6

IFPE_AUX_I2CY_SDA_N

D6

IFPE_L0

C6

IFPE_L0_N

A6

IFPE_L1

A7

IFPE_L1_N

B6

IFPE_L2

B7

IFPE_L2_N

E6

IFPE_L3

E7

IFPE_L3_N

N12M-GE-S-B1 BGA 533P

Physical Strapping pin

ROM_SO FB_0_BAR_SIZE ROM_SCLK ROM_SI STRAP2

+3VS

STRAP1 STRAP0

B

Part 3 of 5

MULTI_STRAP_REF2_GND

LVDS / TMDS

Power Rail

+3VS +3VS +3VS +3VS +3VS +3VS

PGOOD

NCDBG

DBG_DATA1 DBG_DATA2 DBG_DATA3 DBG_DATA4

STRAP0 STRAP1 STRAP2

BUFRST_N

THERMDN

THERMDP

STRAP4

GENERAL STRAPSERIAL

STRAP3

ROM_CS_N

ROM_SCLK

ROM_SI

ROM_SO

IFPAB_RSET

IFPC_RSET IFPD_RSET

IFPE_RSET

Logical Strapping Bit3

XCLK_417 PCI_DEVID[4]

PCI_DEVID[3] 3GIO_PADCFG[3] USER[3]

C15

NC

D15

NC

J5

T6 W6 Y6 AA6 N3

C7 B9 A9

N5

D8 D9

N2 F9

B10 C9 A10 C10

AB6 R5 M6 F8

1 2

RV1 10K_0402_1%@RV1 10K_0402_1%@

GB1B-64 : PGOOD

1 2

RV2 40.2_0402_1%RV2 40.2_0402_1%

GB1B-64 : MULTI_STRAP_REF2_GND

STRAP0 STRAP1 STRAP2

STRAP4 STRAP3

ROM_SCLK_GPU ROM_SI_GPU ROM_SO_GPU

1 2

RV32 1K_0402_1%@RV32 1K_0402_1%@

1 2

RV45 1K_0402_1%@RV45 1K_0402_1%@

1 2

RV47 1K_0402_1%@RV47 1K_0402_1%@

1 2

RV48 1K_0402_1%@RV48 1K_0402_1%@

C

Fermi changed

Logical Strapping Bit2

SUB_VENDOR

Logical Strapping Bit1

SLOT_CLK_CFG RAMCFG[1]RAMCFG[3] RAMCFG[2]

UV1E

B2

GND

B5

GND

B8

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B26

GND

E2

GND

E5

GND

E8

GND

E11

GND

E17

GND

E20

GND

E23

GND

E26

GND

H2

GND

H5

GND

J11

GND

J14

GND

J17

GND

K9

GND

K19

GND

L2

GND

L5

GND

L11

GND

L12

GND

L13

GND

L14

GND

L15

GND

L16

GND

L17

GND

M12

GND

M13

GND

M14

GND

M15

GND

M16

GND

P2

GND

P5

GND

P9

GND

P19

GND

P23

GND

P26

GND

T12

GND

T13

GND

W16

GND_SENSE

E14

GND_SENSE

N12M-GE-S-B1 BGA 533P

Logical Strapping Bit0

VGA_DEVICESMB_ALT_ADDR

PEX_PLLEN_TERM RAMCFG[0] PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2] 3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2] USER[0]USER[1]USER[2]

D

Part 5 of 5

GND

FB_CAL_PU_GND

FB_CAL_TERM_GND MULTI_STRAP_REF0_GND MULTI_STRAP_REF1_GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

U2 U5 U11 U12 U13 U14 U15 U16 U17 U23 U26 V9 V19 W11 W14 W17 Y2 Y5 Y23 Y26 AC2 AC5 AC6 AC8 AC11 AC14 AC17 AC20 AC23 AC26 AF2 AF5 AF8 AF11 AF14 AF17 AF20 AF23 AF26 T16 T15 T14 F6

1 2

A15

RV42 40.2_0402_1%RV42 40.2_0402_1%

1 2

B16

RV43 60.4_0402_1%RV43 60.4_0402_1%

1 2

F11

RV44 40.2K_0402_1%RV44 40.2K_0402_1%

1 2

F10

RV46 40.2K_0402_1%RV46 40.2K_0402_1%

E

Resistor Values

RV52

@

15K_0402_1%

1 2

RV53

RV54

@

1 2

4.99K_0402_1%

1 2

4.99K_0402_1%

4.99K_0402_1% ROM_SCLK_GPU

ROM_SI_GPU ROM_SO_GPU

5K 10K 15K 20K 25K 30K

@

15K_0402_1%

4 4

1 2

X76

1 2

10K_0402_1%

1 2

A

RV60

RV59

RV58

15K_0402_1%

@

35K 45K

B

Pull-up to +3VS

1000 1001 1010 1011 1100 1101 1110 1111

Pull-down to Gnd

0000 0001 0010 0011 0100 0101 0110

Hynix (800MHZ) 64M16 H5TQ1G63DFR-12C SA0000324C0

Samsung (800MHZ) 64MX16 K4W1G1646G-BC12 SA00004HS00

512MB(64Mx16)

1GB (128Mx16)

512MB(64Mx16)

1GB (128Mx16)

0111

Security Classification

2010/09/03 2012/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

D

0010

0110

0011

0111

RV59 PD 15K

RV59 PD 34.8K (SD034348280)

RV59 PD 20K (SD034200280)

RV59 PD 45.3K (SD034453280)

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

(SD034150280)

4019CU

14 53Thursday, January 13, 2011

of

E

of

A

.1U_0402_16V7K

CV40

CV161

+VGA_CORE

1

+

C876

2

.1U_0402_16V7K

CV50

1

2

0.022U_0402_25V7K

1

CV44

2

@

CV164

.1U_0402_16V7K

CV41

1

2

1U_0402_6.3V6K

1

CV58

2

NV DG for VDD Cap:

0.01uF 10% X7R x6

0.047uF 10% X7R x3

0.1uF 10% X7R x1

4.7uF 10% X5R x1 For GB1b-64 add:

4.7u X5R x1

1 1

1

2

.1U_0402_16V7K

CV49

CV162

330U_2.5V_M_R17

1

2

0.022U_0402_25V7K

1

2

under GPU

+3VS

2 2

+1.8VS

3 3

220R 100MHZ

LV11 PBY160808T-221Y-N_2PLV11 PBY160808T-221Y-N_2P

12

4.7U_0603_6.3V6K

1

2

CV175

220R 100MHZ

LV1

PBY160808T-221Y-N_2P

1 2

285mA

+IFPAB_IOVDD

1U_0402_6.3V6K

.1U_0402_16V7K

1

CV172

2

+3.3V_RUN_VDD33

+3VS

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K CV80

CV80

1

2

.1U_0402_16V7K

CV166

1

2

4.7U_0603_6.3V6K

1

2

CV174

1U_0402_6.3V6K

1

CV74

2

.1U_0402_16V7K

CV81

1

2

CV75

22U_0603_6.3V6M

1

2

.1U_0402_16V7K

CV51

1

2

1

2

0.022U_0402_25V7K

.1U_0402_16V7K

1

CV68

2

CV59

B

CV163

1

2

+VGA_CORE

22U_0603_6.3V6M

1

2

1U_0402_6.3V6K

CV42

1

2

1

CV60

2

0.022U_0402_25V7K

.1U_0402_16V7K

CV76

1U_0402_6.3V6K

1

2

1

2

0.022U_0402_25V7K

.1U_0402_16V7K

1

CV69

120mA

2

120mA

+IFPAB_IOVDD

+IFPAB_PLLVDD

CV43

12

RV20

RV20 10K_0402_5%

10K_0402_5%

UV1D

J9

VDD

J10

VDD

J12

VDD

J13

VDD

L9

VDD

M9

VDD

M11

VDD

M17

VDD

N9

VDD

N11

VDD

N12

VDD

N13

VDD

N14

VDD

N15

VDD

N16

VDD

N17

VDD

N19

VDD

P11

VDD

P12

VDD

P13

VDD

P14

VDD

P15

VDD

P16

VDD

P17

VDD

R9

VDD

R11

VDD

R12

VDD

R13

VDD

R14

VDD

R15

VDD

R16

VDD

R17

VDD

T9

VDD

T11

VDD

T17

VDD

U9

VDD

U19

VDD

W9

VDD

W10

VDD

W12

VDD

W13

VDD

W18

VDD

W19

VDD

A12

VDD33

B12

VDD33

C12

VDD33

D12

VDD33

E12

VDD33

F12

VDD33

AG9

PEX_SVDD_3V3

V3

IFPA_IOVDD

V2

IFPB_IOVDD

J6

IFPCD_IOVDD

H6

IFPE_IOVDD

AD5

IFPAB_PLLVDD

P6

IFPC_PLLVDD

N6

IFPD_PLLVDD

D7

IFPE_PLLVDD

N12M-GE-S-B1 BGA 533P

Part 4 of 5

POWER

2A

FB_CAL_PD_VDDQ

C

FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_PLLVDD

VID_PLLVDD

SP_PLLVDD

PLLVDD FB_PLLAVDD FB_PLLAVDD FB_DLLAVDD

DACA_VDD DACB_VDD

VDD_SENSE VDD_SENSE

A13

2.97A

B13 C13 D13 D14 E13 F13 F14 F15 F16 F17 F19 F22 H23 H26 J15 J16 J18 J19 L19 L23 L26 M19 N22 U22 Y22

AG6 AF6 AE6 AD6 AC13 AC7 AB17 AB16 AB13 AB9 AB8 AB7

AG7 AF7 AE7 AD8 AD7 AC9

+PEX_PLLVDD

AF9

+PLLVDD

K6 L6 K5 R19

100mA

AC19 T19

100mA

+DACA_VDD

AG2

1 2

W5

RV63 10K_0402_1%RV63 10K_0402_1%

+1.5V_MEM_VDDQ

B15 W15 E15

route as 50ohm

D

ClosetoPin C1747tobeclosetotheGPU

0.01U_0402_25V7K

CV53

0.01U_0402_25V7K

1

2

1

2

0.047U_0402_25V6K

.1U_0402_16V7K

1

2

.1U_0402_16V7K

1

2

0.01U_0402_25V7K

0.01U_0402_25V7K CV38

CV38

1

2

1

CV52

2

0.047U_0402_25V6K

.1U_0402_16V7K

CV61

1

2

PLACECLOSETOBALL PLACENEARGPU

.1U_0402_16V7K

CV70

1

2

0.01U_0402_25V7K

CV45

CV62

CV71

CV54

CV46

1

2

1

2

0.047U_0402_25V6K

1U_0402_6.3V6K

CV63

1

2

1U_0402_6.3V6K

CV72

1

2

1

@

2

1

2

1

2

1U_0402_6.3V6K

CV47

1U_0402_6.3V6K

CV64

1U_0402_6.3V6K

CV73

1

2

1

2

1

2

120mA

PLACENEARGPU

12

20 mil

CV82

+1.5V_MEM_GFX

1U_0402_6.3V6K

1

2

add for GB1b-64

120mA

+PEX_PLLVDD

.1U_0402_16V7K

1

2

+FB_AVDD

VDD_SENSE <50>

RV65 40.2_0402_1%RV65 40.2_0402_1%

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K CV48

CV48

1

@

2

4.7U_0603_6.3V6K

CV65

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K CV77

CV77

1

2

10U_0603_6.3V6M

1

CV83

2

add for GB1b-64

CV90

1

2

E

10U_0603_6.3V6M

+1.5V_MEM_GFX

CV39

N10M SPEC FBVDDQ TYP. 1.8V.

+1.5V_MEM_GFX

+1.05VS_VCCP

22U_0805_6.3V6M

10U_0603_6.3V6M

CV67

1

2

10U_0603_6.3V6M

1

2

.1U_0402_16V7K

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K CV93

CV93

1

2

CV67

CV79

CV165

SBK160808T-300Y-N_2P

SBK160808T-121Y-N_2P

CV66

+1.05VS_VCCP

22U_0805_6.3V6M

CV78

1U_0402_6.3V6K

CV92

LV2

+1.05VS_VCCP

LV4

12

+1.05VS_VCCP

12

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K CV91

CV91

1

2

+1.05VS_VCCP

4 4

LV10

SBK160808T-121Y-N_2P

12

285mA

+IFPAB_PLLVDD

4.7U_0603_6.3V6K

1U_0402_6.3V6K

1

CV171

CV168

2

add for GB1b-64

CV168

2

.1U_0402_16V7K

1

2

CV167

1

2

LV3

SBK160808T-300Y-N_2P

22U_0603_6.3V6M

CV84

12

150mA,10mil

.1U_0402_16V7K

CV87

1

2

.1U_0402_16V7K

CV88

1

2

+PLLVDD

CV179

.1U_0402_16V7K

CV180

1

2

10U_0603_6.3V6M

CV181

1

2

120mA

+DACA_VDD

1U_0402_6.3V6K

1

2

add for GB1b-64

.1U_0402_16V7K

CV107

1

2

CV109

.1U_0402_16V7K

CV110

1

2

1

2

300ohm 100MHz ESR0.25ohm

.1U_0402_16V7K

CV108

CV112

1

2

MMZ1608D301BT_2P

4.7U_0603_6.3V6K

1

2

LV7

1 2

CV113

+3VS+1.05VS_VCCP

4.7U_0603_6.3V6K

CV114

1

2

add for GB1b-64

Security Classification

2010/09/03 2012/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

15 53Thursday, January 13, 2011

E

A

of

A

B

C

D

E

FBAD[0..63] FBA_CMD[0..30] DQMA#[0..7] DQSA_RN[0..7]

1 1

2 2

3 3

DQSA_WP[0..7]

12

+1.5V_MEM_GFX

1.1K_0402_1%

12

10K_0402_5%

RV66

10K_0402_5%

RV68

10K_0402_5%

RV71

10K_0402_5%

RV72

10K_0402_5%

RV75

RV77

FBAD[0..63] <17,18> FBA_CMD[0..30] <17,18> DQMA#[0..7] <17,18> DQSA_RN[0..7] <17,18> DQSA_WP[0..7] <17,18>

FBA_CMD3

CKE_1

FBA_CMD19

ODT_2

FBA_CMD0

ODT_1

FBA_CMD16

CKE_2

FBA_CMD20

RST

FBAD0 FBAD1 FBAD2 FBAD3 FBAD4 FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD24 FBAD25 FBAD26 FBAD27 FBAD28 FBAD29 FBAD30 FBAD31 FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63

UV1B

D22

FBA_D0

E24

FBA_D1

E22

FBA_D2

D24

FBA_D3

D26

FBA_D4

D27

FBA_D5

C27

FBA_D6

B27

FBA_D7

A21

FBA_D8

B21

FBA_D9

C21

FBA_D10

C19

FBA_D11

C18

FBA_D12

D18

FBA_D13

B18

FBA_D14

C16

FBA_D15

E21

FBA_D16

F21

FBA_D17

D20

FBA_D18

F20

FBA_D19

D17

FBA_D20

F18

FBA_D21

D16

FBA_D22

E16

FBA_D23

A22

FBA_D24

C24

FBA_D25

D21

FBA_D26

B22

FBA_D27

C22

FBA_D28

A25

FBA_D29

B25

FBA_D30

A26

FBA_D31

U24

FBA_D32

V24

FBA_D33

V23

FBA_D34

R24

FBA_D35

T23

FBA_D36

R23

FBA_D37

P24

FBA_D38

P22

FBA_D39

AC24

FBA_D40

AB23

FBA_D41

AB24

FBA_D42

W24

FBA_D43

AA22

FBA_D44

W23

FBA_D45

W22

FBA_D46

V22

FBA_D47

AA25

FBA_D48

W27

FBA_D49

W26

FBA_D50

W25

FBA_D51

AB25

FBA_D52

AB26

FBA_D53

AD26

FBA_D54

AD27

FBA_D55

V25

FBA_D56

R25

FBA_D57

V26

FBA_D58

V27

FBA_D59

R26

FBA_D60

T25

FBA_D61

N25

FBA_D62

N26

FBA_D63

N12M-GE-S-B1 BGA 533P

Part 2 of 5

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0

MEMORY INTERFACE

FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_CLK0_N

FBA_CLK1_N

FBA_DEBUG

FB_VREF

FBA_CLK0

FBA_CLK1

G24 F27 F25 F26 G26 G27 G25 J25 J24 H24 H22 J26 G22 G23 J22 J27 M24 L24 J23 K23 K22 M23 K24 M27 N27 M26 K26 K27 K25 M25 L22

C26 B19 D19 D23 T24 AA23 AB27 T26

D25 A18 E18 B24 R22 Y24 AA27 R27

C25 A19 E19 A24 T22 AA24 AA26 T27

A16 F24

F23 N24

N23 M22

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7

DQSA_RN0 DQSA_RN1 DQSA_RN2 DQSA_RN3 DQSA_RN4 DQSA_RN5 DQSA_RN6 DQSA_RN7

DQSA_WP0 DQSA_WP1 DQSA_WP2 DQSA_WP3 DQSA_WP4 DQSA_WP5 DQSA_WP6 DQSA_WP7

+FB_VREF

1 2

RV76 10K_0402_5%RV76 10K_0402_5%

Mode E - Mirror Mode Mapping

TV6PAD~D @TV6PAD~D @

TV5PAD~D @TV5PAD~D @

CLKA0 <17> CLKA0# <17>

CLKA1 <18> CLKA1# <18>

+1.5V_MEM_GFX

Address

CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14

CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30

DATA Bus

0..31 ODT_L CS1#_L CS0#_L CKE_L

A9 A6 A3 A0 A8 A12 A1 RAS# A13 BA1 A14 CAS#CMD15

RST A7 A4 A11 A2 A10 A5 BA2 WE# BA0 A15

32..63

A11 A7 BA1 A12 A8 A0 A2 RAS# A14 A3 A13 CAS#

CKE_H CS1#_H CS0#_H ODT_H

RST

A6

A5

A9

A1

WE#

A4

A15

A10

BA0

BA2

16mil

+FB_VREF

1.1K_0402_1%

4 4

1.1K_0402_1% @

@

0.01U_0402_25V7K

12

RV78

1

CV128

2

A

B

Security Classification

2010/09/03 2012/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A7204

4019CU

16 53Thursday, January 13, 2011

E

of

A