Compal LA-6855P PBU00 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

Cougar

LA-6855P Schematics Document

Intel Pine View Processor/ Tiger point

3 3

4 4

A

B

2010-10-10

REV: 1.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

4019AD

4019AD

4019AD

136Wednesday, March 16, 2011

136Wednesday, March 16, 2011

136Wednesday, March 16, 2011

E

of

of

of

D

D

D

A

B

C

D

E

Compal Confidential

Model Name : PBU00
File Name : LA-6855P

1 1

CRT Conn.

page 15

Fan Control

page 24

Intel Pineview-M

LED Conn.

page 16

LVDS

ONE CHANNEL

(22x22mm)

page 6,7,8

Thermal Sensor

EMC1402

page 7

Memory BUS(DDRII)

1.8V DDRII 667

Low Power Clock Generator

ICS9LVRS387AKLFT MLF

page 9

200pin DDRII-SO-DIMM

page 10

2 2

DMI x 2

PCIeMini Card
WWAN

USB port 6

page 16

PCIeMini Card
WLAN +BT COMBO

PCIe port 2

page 16

RJ45

page 22

3 3

RTC CKT.

page 13

DC/DC Interface CKT.

page 26

(FULL)

(HALF)

RTL8105E
10/100 LAN

PCIe port 3

page 22

USB

5V 480MHz

PCIe 1x [2]

1.5V 2.5GHz(250MB/s)

PCIe 1x

1.5V 2.5GHz(250MB/s)

Tiger Pointer

(17x17mm)

page 11,12,13,14

3.3V 33 MHz

LPC BUS

USB

5V 480MHz

USB

SATA port 0

5V 1.5GHz(150MB/s)

HD Audio

USB Conn X3

USB port 0,1,4

page 18,21

Card Reader
RTL5137

USB port 3

SATA HDD

3.3V 24.576MHz/48Mhz

page 23

Int. Camera

USB port 7

page 16

Card Reader Conn.

page 19

HDA Codec

ALC269

page 23

page 20

ENE KB926 E0

page 25

page 24

SPI ROM

page 25

Int.

page 20 page 21 page 21 page 21

HP CONN SPK CONNMIC CONNMIC CONN

(10A 1X) (10B 2X)

Power Circuit DC/DC

page 27~35

Touch Pad

page 26

4 4

Power/B

page 26

Int.KBD

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

4019AD

4019AD

4019AD

236Wednesday, March 16, 2011

236Wednesday, March 16, 2011

236Wednesday, March 16, 2011

E

D

D

D

of

of

of

A

B

C

D

E

Voltage Rails

1 1

OFF

G3

OFF

Power Plane Description

VIN
B+
+CPU_CORE

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

S1 S3 S5

ON ON ON OFF
ON ON ON ON

ON OFF
+0.89VS 0.89VS GFX support voltage OFFON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator
+1.05VS
+1.5VS
+1.8V

VCCP switched power rail

1.5V switched power rail

1.5V power rail for DDR
+1.8VS 1.8VS switched power rail
+3VALW

3.3V always on power rail

ON OFF
ON OFF OFF
ON OFF OFF
ON OFF

ON

ON

OFF
ONON ON

+3V_LAN 3.3V power rail for LAN ON

2 2

+3VS
+5VALW 5V always on power rail
+5VS 5V switched power rail
+VSB VSB always on power rail ON
+RTCVCC RTC power

+3V_WLAN

3.3V power rail for LAN ON ON

3.3V switched power rail

ON OFF

ON

ON OFF

OFF OFFONOFF

ON

ON

ON

ON

OFF

OFF

OFF
OFF

ON

OFF
OFF
OFF
OFF
OFF
OFF
OFFON
OFF
OFF
OFFON

OFF
ON

BTO Option Table

Function

description

explain

BTO

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Mini PCI-E SLOT

WLAN@ 3GGPS@

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Function

description

explain

BTO

3 3

EC SM Bus1 address

Device

Smart Battery

Address

EC SM Bus2 address

Device

EMC1402

Address

1001 010X b0001 011X b

WIMAX@

SIGNAL

3GGPSWi-Fi WiMax

SLP_S3#

SLP_S4#

SLP_S5#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

CAMERA & MIC

3G

CAMERA MIC

3G@

CAM@ MIC@

HIGHHIGHHIGH

HIGH

HIGH

LOW

+VALW

ON

ON

ON

ON

ON

BLUE TOOTH

BLUE TOOTH

BT@

+V +VS Clock

ON

ON

ON

OFF

OFF

ON

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

low@ normal@

Clock gen

Tpye

ICH7M SM Bus address

Device

Clock Generator
(SLG8SP556VTR)

DDR DIMMA
WWAN/WLAN

4 4

A

Address

1101 001Xb

1010 000Xb

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855
4019AD

4019AD

4019AD

336Wednesday, March 16, 2011

336Wednesday, March 16, 2011

336Wednesday, March 16, 2011

of

of

E

of

D

D

D

5

D D

C C

B B

4

3

2

1

A A

5

4

Security Classification

Security Classification

Security Classification

2010/06/27 2011/6/27

2010/06/27 2011/6/27

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/27 2011/6/27

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855
4019AD

4019AD

4019AD

436Wednesday, March 16, 2011

436Wednesday, March 16, 2011

436Wednesday, March 16, 2011

1

of

of

of

D

D

D

5

4

3

2

1

DESIGN CURRENT 250mA

B+

Cougar Power Map

Ipeak=6.97A, Imax=4.88A

DESIGN CURRENT 522mA

+3VALWP +-5%

** The SW just is reserved.

UP6182CQAG

D D

C C

SUSP#

The power passes by jump or
0-ohm resistor.

Ipeak=3.98A, Imax=2.8A

SUSP

N-CHANNEL
SI4800BDY

SUSP

N-CHANNEL

SI4800BDY

SUSP#

SY8033BDBC

** P-CHANNEL

AO3413

P-CHANNEL

AO3413

WOL_EN#

ENVDD

DESIGN CURRENT 300mA

DESIGN CURRENT 3010mA

DESIGN CURRENT 2286mA

DESIGN CURRENT 5586mA

DESIGN CURRENT 2000mA

DESIGN CURRENT 2640mA

+3V_LAN

+5VALWP +-5%

+5VS

+3VS

+LCD_VDD

+0.89VSP

SY8033BDBC +1.05VSP +-5%

Ipeak=1.308A, Imax=4A

DESIGN CURRENT 3489mA

VR_ON

B B

ADP3211AMNR2G

Imax=3.5A

DESIGN CURRENT 6000mA

+CPU_CORE

SYSON

Ipeak=19.6A, Imax=13.72A

DESIGN CURRENT 2000mA

+1.8VP +-5%

G5603RU1U

SUSP#

APL5930KAI

DESIGN CURRENT 2112mA

SUSP

G2992F1U

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

4

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

DESIGN CURRENT 500mA

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

4019AD

4019AD

4019AD

+1.5VSP

+0.9VSP

536Wednesday, March 16, 2011

536Wednesday, March 16, 2011

536Wednesday, March 16, 2011

1

D

D

D

of

of

of

5

N455@

N455@
U1

U1
U80610006237AA SLBX9 A0 1.66G

U80610006237AA SLBX9 A0 1.66G

DMI_RXP0_C
DMI_RXN0_C
DMI_RXP1_C

D D

CLK_CPU_EXP#<9>
CLK_CPU_EXP<9>

C C

DMI_RXN1_C

C948

DMI_RXP0<12>

DMI_RXN0<12>

DMI_RXP1<12>

DMI_RXN1<12>

C948

C949

C949

C950

C950

C951

C951

N475@

N475@
U1

U1
AU80610006240AA SLBX5

AU80610006240AA SLBX5

U1A

U1A

F3

DMI_RXP_0

F2

DMI_RXN_0

H4

DMI_RXP_1

G3

DMI_RXN_1

N7

EXP_CLKINN

N6

EXP_CLKINP

R10

EXP_TCLKINN

R9

EXP_TCLKINP

N10

RSVD

N9

RSVD

K2

RSVD

J1

RSVD

M4

RSVD

L3

RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
DMI_RXN1_C

0.1U_0402_10V6K

0.1U_0402_10V6K

DMI_RXP0_C

DMI_RXN0_C

DMI_RXP1_C

1 2

1 2

1 2

1 2

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

DMI

DMI

EXP_RCOMPO

Close to CPU

XDP Reserve

XDP_TDI

R495

@R495

@

XDP_TDI<7>
XDP_TMS<7>
XDP_TDO<7>

B B

XDP_PREQ#<7>

XDP_TRST#<7>
XDP_TCK<7>

XDP_TMS

XDP_TDO

XDP_PREQ#

XDP_TRST#
XDP_TCK

R496

@R496

@

R499

@R499

@

R501

@R501

@

R502

@R502

@

R505

@R505

@

1 2

51_0402_5%

51_0402_5%

1 2

51_0402_5%

51_0402_5%

1 2

51_0402_5%

51_0402_5%

1 2

51_0402_5%

51_0402_5%

1 2

51_0402_5%

51_0402_5%

1 2

51_0402_5%

51_0402_5%

+1.05VS

# MP Remove XDP resistor for ESD

+5VALW +1.8V

1

1

1

C1050

2

2

C1050

0.1U_0402_16V4Z

0.1U_0402_16V4Z

68P_0402_50V8J

68P_0402_50V8J

C203

A A

C203

68P_0402_50V8J

68P_0402_50V8J

C204

C204

1

2

2

C1065

C1065

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1

EXP_ICOMPI

EXP_RBIAS

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD
RSVD

1 OF 6

1 OF 6

G2
G1
H3
J2

L10

DMI_IRCOMPDMI_IRCOMP

L9
L8

N11

T1T1

P11

T2T2

K3
L2
M2
N2

SYSON#<27>

PM_SLP_S4#<13,24>

SYSON<24,27,32>

DMI_TXP0 <12>
DMI_TXN0 <12>
DMI_TXP1 <12>
DMI_TXN1 <12>

R492

R492
R493

R493

49.9_0402_1%

49.9_0402_1%
750_0402_1%

750_0402_1%

Pull-down must be placed
within 500 mils from Pineview-M

@

@

SYSON#

2

G

G

R884

@ R884

@

1K_0402_5%

1K_0402_5%

Q40A

@Q40A

@

R882

@R882

@

1 2

@R886

@

1 2

0_0402_5%

0_0402_5%
R886

0_0402_5%

0_0402_5%

2

Reserve PM_SLP_S4# to turn on DRAM_PWROK

Change Power rail to 1.8V
Derek 8/20

13

D

D

Q37

Q37

2N7002_SOT23

2N7002_SOT23

S

S

1 2

+5VALW

12

61

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

0.01U_0402_16V7K

0.01U_0402_16V7K

1

2

R880 10K_0402_5%@R880 10K_0402_5%

@

@

R885

R885

10K_0402_5%

10K_0402_5%

Q40B

@Q40B

@

C952

C952

SMPWROK

C1063 0.1U_0402_16V4Z@C1063 0.1U_0402_16V4Z

5

+1.8V

3

DDR_A_DQS#[0..7]<10>
DDR_A_D[0..63]<10>
DDR_A_DM[0..7]<10>
DDR_A_DQS[0..7]<10>
DDR_A_MA[0..14]<10>

+1.8V

12

3

4

R497

R497

1

80.6_0402_1%

80.6_0402_1%

2

Add 1.8V for PWROK
Derek 8/20

SM_PWROK

DRAMRST#

+1.8V

12

R500

R500

1K_0402_1%

1K_0402_1%

12

R504

R504

1K_0402_1%

1K_0402_1%

DDR_RPU

+1.8V

DDR_VREF

DDR_A_WE#<10>
DDR_A_CAS#<10>
DDR_A_RAS#<10>

DDR_A_BS0<10>
DDR_A_BS1<10>
DDR_A_BS2<10>

DDR_CS0#<10>
DDR_CS1#<10>

DDR_CKE0<10>
DDR_CKE1<10>

M_ODT0<10>
M_ODT1<10>

M_CLK_DDR0<10>
M_CLK_DDR#0<10>
M_CLK_DDR1<10>
M_CLK_DDR#1<10>

R881 0_0402_5%@R881 0_0402_5%@

@R878

@

1 2

10K_0402_5%

10K_0402_5%

R503

R503

80.6_0402_1%

80.6_0402_1%

1 2

R878

DDR_RPD

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS0#
DDR_CS1#

DDR_CKE0
DDR_CKE1

M_ODT0
M_ODT1

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

1

C953

C953

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

SMPWROK

T3T3
T4T4

DDR_RPD
DDR_RPU

2

PINEVIEW_M

DDR_A

DDR_A

PINEVIEW_M

REV = 1.1

REV = 1.1

2 OF 6

2 OF 6

DDR_A_DQS_0

DDR_A_DQS#_0

DDR_A_DM_0
DDR_A_DQ_0

DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_1

DDR_A_DQS#_1

DDR_A_DM_1
DDR_A_DQ_8

DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_2

DDR_A_DQS#_2

DDR_A_DM_2
DDR_A_DQ_16

DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_3

DDR_A_DQS#_3

DDR_A_DM_3
DDR_A_DQ_24

DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_4

DDR_A_DQS#_4

DDR_A_DM_4
DDR_A_DQ_32

DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_5

DDR_A_DQS#_5

DDR_A_DM_5
DDR_A_DQ_40

DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_6

DDR_A_DQS#_6

DDR_A_DM_6
DDR_A_DQ_48

DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_7

DDR_A_DQS#_7

DDR_A_DM_7
DDR_A_DQ_56

DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

U1B

U1B

AH19

DDR_A_MA_0

AJ18

DDR_A_MA_1

AK18

DDR_A_MA_2

AK16

DDR_A_MA_3

AJ14

DDR_A_MA_4

AH14

DDR_A_MA_5

AK14

DDR_A_MA_6

AJ12

DDR_A_MA_7

AH13

DDR_A_MA_8

AK12

DDR_A_MA_9

AK20

DDR_A_MA_10

AH12

DDR_A_MA_11

AJ11

DDR_A_MA_12

AJ24

DDR_A_MA_13

AJ10

DDR_A_MA_14

AK22

DDR_A_WE#

AJ22

DDR_A_CAS#

AK21

DDR_A_RAS#

AJ20

DDR_A_BS_0

AH20

DDR_A_BS_1

AK11

DDR_A_BS_2

AH22

DDR_A_CS#_0

AK25

DDR_A_CS#_1

AJ21

DDR_A_CS#_2

AJ25

DDR_A_CS#_3

AH10

DDR_A_CKE_0

AH9

DDR_A_CKE_1

AK10

DDR_A_CKE_2

AJ8

DDR_A_CKE_3

AK24

DDR_A_ODT_0

AH26

DDR_A_ODT_1

AH24

DDR_A_ODT_2

AK27

DDR_A_ODT_3

AG15

DDR_A_CK_0

AF15

DDR_A_CK_0#

AD13

DDR_A_CK_1

AC13

DDR_A_CK_1#

AC15

DDR_A_CK_3

AD15

DDR_A_CK_3#

AF13

DDR_A_CK_4

AG13

DDR_A_CK_4#

AD17

RSVD

AC17

RSVD

AB15

RSVD

AB17

RSVD

AB4

DRAM_PWROK

AK8

DRAM_RST#

AB11

RSVD_TP

AB13

RSVD_TP

AL28

DDR_VREF

AK28

DDR_RPD

AJ26

DDR_RPU

AK29

RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

1

AD3
AD2
AD4

AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3

AB8
AD7
AA9

AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6

AD8
AD10
AE8

AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10

AK5
AK3
AJ3

AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6

AG22
AG21
AD19

AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21

AE26
AG27
AJ27

AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27

AE30
AF29
AF30

AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28

AB27
AA27
AB26

AA24
AB25
W24
W22
AB24
AB23
AA23
W27

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DM4

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DM5

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DM6

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM7

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

2010.07.12 RF request

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

4019AD

4019AD

4019AD

636Wednesday, March 16, 2011

636Wednesday, March 16, 2011

636Wednesday, March 16, 2011

1

D

D

D

of

of

of

5

PINEVIEW_M

U1C

U1C

D12

T8T8
T18T18
T9T9
T10T10
T19T19

D D

T11T11
T20T20
T12T12
T13T13

XDP_RSVD_9

T14T14
T15T15
T44T44
T17T17
T21T21
T22T22
T23T23
T24T24

T25T25

C C

T26T26
T27T27
T28T28
T29T29

T31T31
T33T33
T35T35
T37T37

C10
D10
B11
B10
B12
C11

AA7
AA6

AA21

W21

V21

A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8

L11

R5
R6

T21

XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17

RSVD

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

PINEVIEW_M

REV = 1.1

REV = 1.1

VGA

VGA

PM_EXTTS#_1/DPRSLPVR

MISC

MISC

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_IRTN

CRT_DDC_DATA

CRT_DDC_CLK

DAC_IREF

REFCLKINP

REFCLKINN
REFSSCLKINP
REFSSCLKINN

PM_EXTTS#_0

PWROK

RSTIN#

HPL_CLKINN

HPL_CLKINP

M30
M29

GMCH_CRT_R

N31

GMCH_CRT_G

P30

GMCH_CRT_B

P29
N30

L31
L30

P28
Y30

Y29
AA30
AA31

K29
J30
L5
AA3

W8
W9

R510 be placed <500 mils to U1.P28

DAC_IREF
CPU_DREFCLK

CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#

PM_EXTTS#1
PM_EXTTS#0
PCH_POK
PLTRST#

CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK

To be placed <250 mils to U1 ball

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
ENBKL

To be placed <500 mils to U1 ball

B B

XDP_RSVD_9

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

R518

R518
1K_0402_5%

1K_0402_5%

1 2

+3VS

1

C961

C961

2

0.1U_0402_16V4Z

A A

+3VS

0.1U_0402_16V4Z

C968

C968

1 2

2200P_0402_50V7K

2200P_0402_50V7K

1 2

R524 10K_0402_5%R524 10K_0402_5%

5

H_THERMDA

H_THERMDC
CPU_THERM#

3 OF 6

3 OF 6

CPU THERMAL SENSOR

U2

U2

GND

8
7
6
5

EC_SMB_CK2
EC_SMB_DA2

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

EMC1402-1-ACZL-TR_MSOP8

Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2

SMCLK

SMDATA

ALERT#

4

GMCH_CRT_HSYNC <15>
GMCH_CRT_VSYNC <15>

GMCH_CRT_R <15>
GMCH_CRT_G <15>
GMCH_CRT_B <15>

GMCH_CRT_DATA <15>
GMCH_CRT_CLK <15>

R510 665_0402_1%R510 665_0402_1%

CPU_DREFCLK <9>
CPU_DREFCLK# <9>
CPU_SSCDREFCLK <9>
CPU_SSCDREFCLK# <9>

0_0402_5%

0_0402_5%

R512

R512

PM_EXTTS#0 <10>
PCH_POK <13>
PLTRST# <13,17,22>

1 2
1 2
1 2

LCD_EDID_CLK

LCD_EDID_DATA

PM_DPRSLPVR <13>

CLK_CPU_HPLCLK# <9>
CLK_CPU_HPLCLK <9>

R514

R514
150_0402_1%

150_0402_1%
R515

R515
150_0402_1%

150_0402_1%
R516

R516
150_0402_1%

150_0402_1%
R517

R517

100K_0402_5%

100K_0402_5%

RF@C205

RF@

1 2

RF@C206

RF@

1 2

C205

12P_0402_50V8J

12P_0402_50V8J
C206

12P_0402_50V8J

12P_0402_50V8J

2010.07.12 RF request

# PVT C205, C206 change to
12p and stuff for RF

EC_SMB_CK2 <24>
EC_SMB_DA2 <24>

12

R523 10K_0402_5%@R523 10K_0402_5%@

4

+3VS

LCD_TXCLK-<16>

LCD_TXCLK+<16>
LCD_TXOUT0-<16>
LCD_TXOUT0+<16>
LCD_TXOUT1-<16>
LCD_TXOUT1+<16>
LCD_TXOUT2-<16>
LCD_TXOUT2+<16>

R509 be placed U1.R22

ENBKL<24>

GMCH_INVT_PWM<16>

LCD_EDID_CLK<16>
LCD_EDID_DATA<16>

GMCH_ENVDD<16>

+3VS

12

PM_EXTTS#0

Close to Processor pin

Close to CPU

R513

R513
10K_0402_5%

10K_0402_5%

3

R509

R509

2.37K_0402_1%

2.37K_0402_1%

ENBKL

PINEVIEW_M

U1D

U1D

U25

LA_CLKN

U26

LA_CLKP

R23

LA_DATAN_0

R24

LA_DATAP_0

N26

LA_DATAN_1

N27

LA_DATAP_1

R26

LA_DATAN_2

R27

LA_DATAP_2

L_IBG

R22

LIBG

J28

LVBG

N22

LVREFH

N23

LVREFL

L27

LBKLT_EN

L26

LBKLT_CTL

L23

LCTLA_CLK

K25

LCTLB_DATA

K23

LDDC_CLK

K24

LDDC_DATA

H26

LVDD_EN

G11

T43T43
T47T47
T46T46
T45T45

T30T30
T32T32
T34T34
T36T36

E15
G13
F13

B18
B20
C20
B21

BPM_1_0#
BPM_1_1#
BPM_1_2#
BPM_1_3#

BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD

PINEVIEW_M

LVDS

LVDS

REV = 1.1

REV = 1.1

ICH

ICH

CPU

CPU

2

Close to CPU

G5

T38T38

H_THERMDA
H_THERMDC

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

XDP_TDI
XDP_TDO
XDP_TCK
XDP_TMS

XDP_TRST#

XDP_TDI<6>
XDP_TDO<6>
XDP_TCK<6>
XDP_TMS<6>
XDP_TRST#<6>

H_DPRSTP#

H_DPSLP#

H_PWRGD

H_A20M#

H_IGNNE#

H_INIT#

H_INTR

H_FERR#

H_NMI

H_SMI#

H_STPCLK#

C954 220P_0402_50V7K@C954 220P_0402_50V7K@
C955 220P_0402_50V7K@C955 220P_0402_50V7K@
C956 220P_0402_50V7K@C956 220P_0402_50V7K@
C957 220P_0402_50V7K@C957 220P_0402_50V7K@
C958 220P_0402_50V7K@C958 220P_0402_50V7K@
C959 220P_0402_50V7KC959 220P_0402_50V7K
C960 220P_0402_50V7KC960 220P_0402_50V7K
C962 220P_0402_50V7K@C962 220P_0402_50V7K@
C965 220P_0402_50V7K@C965 220P_0402_50V7K@
C966 220P_0402_50V7K@C966 220P_0402_50V7K@
C967 220P_0402_50V7K@C967 220P_0402_50V7K@

# PVT C959, C960 stuff for ESD

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

3

RSVD

D14

TDI

D13

TDO

B14

TCK

C14

TMS

C16

TRST#

D30

THRMDA_1

E30

THRMDC_1

C30

THRMDA_2/RSVD

D31

THRMDC_2/RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

ESD request

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4 OF 6

4 OF 6

220P_0402_50V7K

220P_0402_50V7K

2

E7

SMI#

H7

A20M#

H6

FERR#

F10

LINT0

F11

LINT1

E5

IGNNE#

F8

STPCLK#

G6

DPRSTP#

G10

DPSLP#

G8

INIT#

E11

PRDY#

F15

PREQ#

GTLREF

RSVD
RSVD

BCLKN
BCLKP

BSEL_0
BSEL_1
BSEL_2

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

RSVD
RSVD
RSVD
RSVD

RSVD_TP
RSVD_TP

2

@

@

1

E13

C18
W1

A13
H27

VSS

L6
E17

H10
J10

K5
H5
K6

H30
H29
H28
G30
G29
F29
E29

L7
D20
H13
D18

K9
D19
K7

R519

R519
1K_0402_1%

1K_0402_1%

R521

R521
2K_0402_1%

2K_0402_1%

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

THERMTRIP#

PROCHOT#

CPUPWRGOOD

EXTBGREF

placed within 0.5"
of processor pin.

C963

C963

H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#

H_DPRSTP#
H_DPSLP#
H_INIT#

T48T48

XDP_PREQ#

H_THERMTRIP#

H_PROCHOT#

H_PWRGD

H_GTLREF

CLK_CPU_BCLK#
CLK_CPU_BCLK

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

T39T39
T40T40

H_EXTBGREF

Title

Title

Title

B

B

B

1

H_SMI# <11>
H_A20M# <11>
H_FERR# <11>
H_INTR <11>
H_NMI <11>
H_IGNNE# <11>
H_STPCLK# <11>

H_DPRSTP# <13>
H_DPSLP# <13>
H_INIT# <11>

XDP_PREQ# <6>

H_THERMTRIP# <11>

Close to CPU

H_PWRGD <13>

CPU_BSEL0 <9>
CPU_BSEL1 <9>
CPU_BSEL2 <9>

CPU_VID0 <35>
CPU_VID1 <35>
CPU_VID2 <35>
CPU_VID3 <35>
CPU_VID4 <35>
CPU_VID5 <35>
CPU_VID6 <35>

placed within 0.5" of processor
pin and 5 mils spacing

1U_0402_6.3V6K

1U_0402_6.3V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

Close to CPU

CLK_CPU_BCLK# <9>
CLK_CPU_BCLK <9>

H_EXTBGREFH_GTLREF

1

C964

C964

2

4019AD

4019AD

4019AD

1

+1.05VS

R51168_0402_5% R51168_0402_5%

+1.05VS+1.05VS

R520

R520
976_0402_1%

976_0402_1%

R522

R522

3.3K_0402_1%

3.3K_0402_1%

736Wednesday, March 16, 2011

736Wednesday, March 16, 2011

736Wednesday, March 16, 2011

of

of

of

D

D

D

5

U1E

U1E

+0.89VS

D D

modify C979,C980,C981,C982,C983
from 1U to 2.2U base on Intel check list
Derek 08/24

+1.8V

R527

R527

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1 2

0_1206_5%

0_1206_5%

C979

C979

Change to +1.8V power rail
Derek 08/24

+1.8V

C C

1 2

R530

R530

0_0603_5%

0_0603_5%

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2

2

2

C981

C981

C980

C980

1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

C982

C982

1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

Please closed U1 ball

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C992

C992

2

2

Please closed U1 ball

B B

1380mA

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2

2

C983

C983

@

@

1

1

+VCC_SM

+VCCCK_DDR

+VCCCK_DDR

C993

C993
1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCA_VCCD

1880mA

+VCCSFR_AB_DPL

+VCC_SM

2270mA

W14
W16
W18
W19

AK13
AK19

AL11
AL16
AL21
AL25

W10
W11

AA10
AA11

AA19

AC31

T13
T14
T16
T18

T19
V13
V19

AK9

AK7
AL7

U10

U5
U6
U7
U8
U9
V2
V3
V4

V11

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VCCCK_DDR
VCCCK_DDR

VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

VCCACK_DDR
VCCACK_DDR

VCCD_AB_DPL

VCCD_HMPLL

VCCSFR_AB_DPL

GFX/MCH

GFX/MCH

DDR

DDR

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

154mA

+3VS

+RING_EAST
+RING_WEST

+LGI_VID +DMI_HMPLL

+0.89VS

A A

2

C1006

C1006

C1005

C1005

1

2.2U_0603_10V6K

2.2U_0603_10V6K

+VCC_CRT_DAC

5mA

305mA

1

1

1

C1007

C1007

C1008

2

C1008

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C1009

C1009

T30

VCCACRTDAC

T31

VCC_GIO

J31

VCCRING_EAST

C3

VCCRING_WEST

B2

VCCRING_WEST

C2

VCCRING_WEST

A21

VCC_LGI

5 OF 6

5 OF 6

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

1

1

2

1

C1012

C1010

C1010

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C1012

C1011

C1011

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

EXP\CRT\PLL

EXP\CRT\PLL

1

2

1

C1013

C1013

C1014

2

C1014

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

Close Chipset pin

5

POWER

POWER

DMI

DMI

VCCSFR_DMIHMPLL

1

+

+

C1004

C1004

2

10U_0805_10V4Z

10U_0805_10V4Z

LVDS

LVDS

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

CPU

CPU

4

VCCSENSE

4

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSSSENSE

VCCA

VCCP
VCCP

VCCP

VCCALVDS
VCCDLVDS

VCCA_DMI
VCCA_DMI
VCCA_DMI

RSVD

VCCP

3500mA

1U_0402_6.3V6K

VCCSENSE
VSSSENSE

420mA

1U_0402_6.3V6K

@

@

A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21

C29
B29
Y2

80mA

D4
B4

B3

Please closed U1.D4

+VCC_ALVD

V30

+VCC_DLVD

W31

60mA

+VCC_DMI

T1

480mA

T2
T3

P2
AA1

104mA

E2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C974

C974

C975

C975

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

Please closed U1 ball

+CPU_CORE

2 x 330uF(9mohm/2)

1

+

+

C984

C984

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

+CPU_CORE

1

1

C989

C989

C990

C990

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.05VS

1

C999

C999

0.1U_0402_10V6K

0.1U_0402_10V6K

2

+1.05VS

Please closed U1.Y2

+0.89VS

T41T41

+CPU_CORE

2010.07.12 RF request

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1
C976

C976

2

1

C991

C991

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C996

C996

0.01U_0402_16V7K

0.01U_0402_16V7K

2

+VCCA_VCCD

+VCCCK_DDR

Issued Date

Issued Date

Issued Date

3

+CPU_CORE

1
C977

C977

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

+

+

C985

C985

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.5VS

3

+1.05VS

R525

R525

1 2

0_0805_5%

0_0805_5%

1

2

C970

C970

C971

C971

1

@

@

0.1U_0402_10V6K

0.1U_0402_10V6K

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C986

C986

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C994

C994

2

1U_0402_6.3V6K

1U_0402_6.3V6K

R534

R534

1 2

0_0603_5%

0_0603_5%

C997

C997

1U_0402_6.3V6K

1U_0402_6.3V6K

R535

R535

1 2

0_0603_5%

0_0603_5%

C1000

C1000

1U_0402_6.3V6K

1U_0402_6.3V6K

R536

R536

1 2

0_0603_5%

0_0603_5%

C1001

C1001

1U_0402_6.3V6K

1U_0402_6.3V6K

R537

R537

1 2

0_0603_5%

0_0603_5%

C1002

C1002

22U_0805_6.3V6M

22U_0805_6.3V6M

R538

R538

1 2

0_0603_5%

0_0603_5%

C1003

C1003

1U_0402_6.3V6K

1U_0402_6.3V6K

Deciphered Date

Deciphered Date

Deciphered Date

1

2

C978

C978

+RING_WEST

C987

C987

@

@

C988

C988

C995

C995

C969

C969

2

@

@

0.1U_0402_10V6K

0.1U_0402_10V6K

+1.05VS

R526

R526

1 2

0_0603_5%

0_0603_5%

R528

R528

1 2

0_0603_5%

0_0603_5%

R529

R529

1 2

0_0603_5%

0_0603_5%

R531

R531

1 2

0_0603_5%

0_0603_5%

+CPU_CORE

12

R532

R532

100_0402_5%

100_0402_5%

VCCSENSE <35>
VSSSENSE <35>

12

R533

R533

100_0402_5%

100_0402_5%

1 2

C159 22P_0402_50V8J

C159 22P_0402_50V8J

RF@

RF@

1 2

C150 22P_0402_50V8J

C150 22P_0402_50V8J

RF@

RF@

1 2

C153 22P_0402_50V8J

C153 22P_0402_50V8J

RF@

RF@

1 2

C156 22P_0402_50V8J

C156 22P_0402_50V8J

RF@

RF@

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

+1.8VS

Compal Secret Data

Compal Secret Data

Compal Secret Data

+VCCA_VCCD

1

C973

C973

C972

C972

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

+RING_EAST

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+LGI_VID

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCC_DMI

+VCC_DMI

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCSFR_AB_DPL

1

C998

C998

1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCC_CRT_DAC+VCC_CRT_DAC+VCC_CRT_DAC

1

2

+DMI_HMPLL

1

2

+VCC_ALVD

1

2

+VCC_DLVD

1

2

2

PINEVIEW_M

PINEVIEW_M

U1F

U1F

REV = 1.1

REV = 1.1

A11

VSS

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

2

A16

VSS

A19

VSS

A29

RSVD_NCTF

A3

RSVD_NCTF

A30

RSVD_NCTF

A4

RSVD_NCTF

AA13

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA2

VSS

AA22

VSS

AA25

VSS

AA26

VSS

AA29

VSS

AA8

VSS

AB19

VSS

AB21

VSS

AB28

VSS

AB29

VSS

AB30

VSS

AC10

VSS

AC11

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC28

VSS

AC30

VSS

AD26

VSS

AD5

VSS

AE1

VSS

AE11

VSS

AE13

VSS

AE15

VSS

AE17

VSS

AE22

VSS

AE31

VSS

AF11

VSS

AF17

VSS

AF21

VSS

AF24

VSS

AF28

VSS

AG10

VSS

AG3

VSS

AH18

VSS

AH23

VSS

AH28

VSS

AH4

VSS

AH6

VSS

AH8

VSS

AJ1

RSVD_NCTF

AJ16

VSS

AJ31

RSVD_NCTF

AK1

RSVD_NCTF

AK2

RSVD_NCTF

AK23

VSS

AK30

RSVD_NCTF

AK31

RSVD_NCTF

AL13

VSS

AL19

VSS

AL2

RSVD_NCTF

AL23

VSS

AL29

RSVD_NCTF

AL3

RSVD_NCTF

AL30

RSVD_NCTF

AL9

VSS

B13

VSS

B16

VSS

B19

VSS

B22

VSS

B30

RSVD_NCTF

B31

RSVD_NCTF

B5

VSS

B9

VSS

C1

RSVD_NCTF

C12

VSS

C21

VSS

C22

VSS

C25

VSS

C31

RSVD_NCTF

D22

VSS

E1

RSVD_NCTF

E10

VSS

E19

VSS

E21

VSS

E25

VSS

E8

VSS

F17

VSS

F19

VSS

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

6 OF 6

6 OF 6

GND

GND

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

4019AD

4019AD

4019AD

1

F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4

T29

D

D

D

of

of

of

836Wednesday, March 16, 2011

836Wednesday, March 16, 2011

836Wednesday, March 16, 2011

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKSEL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

0 1001 166 33.31 14.318 96.0 48.0

D D

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

111

Reserved

Normal Power Low Power

R477 @ Stuff
R478
R479
R480
R483

C C

CPU_BSEL0<7>

CPU_BSEL1<7>

B B

CPU_BSEL2<7>

Stuff
Stuff

@
@

+1.05VS

R482

R482

2.2K_0402_5%

2.2K_0402_5%

FSA

FSB

FSC

1 2

R86

R86
0_0402_5%

0_0402_5%

R486

R486
1K_0402_5%

1K_0402_5%

1 2

R487

R487
0_0402_5%

0_0402_5%

R490

R490

10K_0402_5%

10K_0402_5%

1 2

R104

R104
0_0402_5%

0_0402_5%

12

+1.05VS

12

+1.05VS

12

7/22 Add R242 to R253 for Intel request

A A

2010.03.09 Change Y1 to 5 x3.2 size

5

@

@
Stuff
Stuff

12

R481

R481
470_0402_5%

470_0402_5%

8/24 Change net name to FSB for U3.2

12

12

12

12

12

14.31818MHZ 20PF 7A14300003

14.31818MHZ 20PF 7A14300003

7/13 Add 33pF to GND for RF request

R484

@R484

@

7/21 Reserve 33pF to GND for RF request

1K_0402_5%

1K_0402_5%

8/27 C303, C324, C325, C326, C327 to GND for RF request

+3VS

7/22 Add R241 pull up to +3VS for RF Intel request

R485

R485
470_0402_5%

470_0402_5%

R488

@R488

@
0_0402_5%

0_0402_5%

+3VS

8/14 Add R250 pull up for Intel request

R489

R489
470_0402_5%

470_0402_5%

R491

@R491

@
0_0402_5%

0_0402_5%

C147 22P_0402_50V8JC147 22P_0402_50V8J

C148 22P_0402_50V8JC148 22P_0402_50V8J

12

Y1

Y1

Routing the trace at least 10mil

R65

R65

1 2

R608

R608

1 2

CLK_XTAL_IN

CLK_XTAL_OUT

+1.5VM_CK505

+1.05VM_CK505

+1.5VM_CK505

H_STP_CPU#

10K_0402_5%

10K_0402_5%

H_STP_PCI#_R

10K_0402_5%

10K_0402_5%

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#

For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only) 1=Overclocking of CPU and SRC NOT allowed

4

+3VM_CK505

R81

R81

1 2

+3VS

0_0603_5%

0_0603_5%

+1.05VM_CK505

+1.05VS

R82

R82

1 2

FBMH1608HM601-T_0603

FBMH1608HM601-T_0603

7/13 For RF request

+3VM_1.5VM_R

C943

C943

+1.05VM_1.5VM_R

C946

C946

+1.5VM_CK505

1

C942

C942

2

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R427 0_0402_5%@R427 0_0402_5%@

1 2

R477

R477

1 2

+1.5VS

0_0603_5%

0_0603_5%

LOW@

LOW@

7/13 For RF request

+3VM_CK505

R478

NORMAL@ R478

NORMAL@

1 2

0_0603_5%

0_0603_5%

R483

LOW@R483

LOW@

1 2

0_0603_5%

0_0603_5%

R479

NORMAL@ R479

NORMAL@

1 2

0_0603_5%

0_0603_5%
R480

LOW@R480

LOW@

1 2

0_0603_5%

0_0603_5%

7/13 For RF request

CLK_48M_CR<23>
CLK_PCH_48M<12>

CLK_PCH_14M<13>

VGATE<13,24,35>

H_STP_CPU#<13>

H_STP_PCI#<13>

CLK_PCI_DDR<17>

CLK_PCI_LPC<24>
CLK_PCI_PCH<11>

7/13 Add 33pF to GND for RF request

1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS

ITP_EN PCI2_TME

R113

R113
10K_0402_5%

10K_0402_5%

1 2

PCI4_SEL

R114

R114
10K_0402_5%

10K_0402_5%

1 2

4

2010.03.23 Change R81 from bead to 0 ohm

3

250 mA

1

C126

C126
10U_0805_10V4Z

10U_0805_10V4Z

2

1

C127

C127

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C128

C128

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C129

C129

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

80 mA

1

C134

C134
10U_0805_10V4Z

10U_0805_10V4Z

2

1

C135

C135

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C136

C136

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C137

C137

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2010.03.23 Change R477 from bead to 0 ohm
8/27 Delete C93, C94, C95, C102 for low power CLK GEN

SA00003H610 (ICS :CS9LVRS387AKLFT MLF)

Low power CLK Gen.

10U_0805_10V4Z

10U_0805_10V4Z

1

1

C944

C944

C945

C945

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.05VM_CK505

@

@

C947

C947

47P_0402_50V8J

47P_0402_50V8J

R9210_0402_5% R9210_0402_5%

1 2

R9110_0402_5% R9110_0402_5%

1 2

1 2

C143 22P_0402_50V8JC143 22P_0402_50V8J

R9333_0402_5% R9333_0402_5%

1 2

1 2

C868 22P_0402_50V8JC868 22P_0402_50V8J

1 2

C144 22P_0402_50V8JC144 22P_0402_50V8J

R10333_0402_5% R10333_0402_5%

1 2

1 2

C145 22P_0402_50V8JC145 22P_0402_50V8J

R10733_0402_5% R10733_0402_5%

1 2

R10833_0402_5% R10833_0402_5%

1 2

1 2

C146 22P_0402_50V8JC146 22P_0402_50V8J

+3VS

R112

R112
10K_0402_5%

10K_0402_5%

1 2

@

@
R115

R115
10K_0402_5%

10K_0402_5%

1 2

+3VM_CK505

LOW@U4

LOW@

FSA
FSB
FSC

VGATE

H_STP_CPU#
H_STP_PCI#_R

CLK_XTAL_IN
CLK_XTAL_OUT

CLK_PCI_DDR_R

CLK_PCI_DDR_R
PCI2_TME

PCI4_SEL

PCI4_SEL
ITP_EN

ITP_EN

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NORMAL@

NORMAL@
U4

U4
RTM875N-397-GR

RTM875N-397-GR

U4

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

ICS9LVRS387AKLFT MLF

ICS9LVRS387AKLFT MLF

3

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2

C133

C133
47P_0402_50V8J

47P_0402_50V8J

1

C138

C138

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C139

C139

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C141

C141
47P_0402_50V8J

47P_0402_50V8J

7/21 Delete C296, C297 for RF request
7/13 Add 22pF to gnd and close to U3 for RF request
7/21 Reserve 22pF to gnd and close to U3 for RF request

SRC_0/DOT_96

SRC_0#/DOT_96#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SRC_10#

SRC_11#

CLKREQ_3#
CLKREQ_4#
CLKREQ_6#
CLKREQ_7#

CLKREQ_9#
SLKREQ_10#
CLKREQ_11#

USB_1/CLKREQ_A#

Compal Secret Data

Compal Secret Data

Compal Secret Data

SDA

SCL

CPU_0

CPU_0#

CPU_1

CPU_1#

SRC_2

SRC_2#

SRC_3

SRC_3#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_7

SRC_7#

SRC_9

SRC_9#

SRC_10

SRC_11

CLK_SMBDATA

9

CLK_SMBCLK

10

CLK_CPU_BCLK

71

CLK_CPU_BCLK#

70

CLK_CPU_HPLCLK

68

CLK_CPU_HPLCLK#

67

24
25

CPU_SSCDREFCLK

28

CPU_SSCDREFCLK#

29

CLK_CPU_EXP

32

CLK_CPU_EXP#

33

35
36

CLK_PCIE_SATA

39

CLK_PCIE_SATA#

40

CLK_PCIE_WLAN

57

CLK_PCIE_WLAN#

56

61
60

64
63

CLK_PCIE_LAN

44

CLK_PCIE_LAN#

45

CLK_PCIE_PCH

50

CLK_PCIE_PCH#

51

CLK_PCIE_WWAN

48

CLK_PCIE_WWAN#

47

37
41

WLAN_CLKREQ#

58
65

LAN_CLKREQ#

43
49

WWAN_CLKREQ#

46
21

Deciphered Date

Deciphered Date

Deciphered Date

CPU_DREFCLK
CPU_DREFCLK#

CLK_PCIE_PCH
CLK_PCIE_PCH#

2010.07.12 RF request

7/21 Change WWAN_CLKREQ# from REQ4 to REQ11

2

CPU_SSCDREFCLK CPU_SSCDREFCLK#

1

C940

@C940

@
33P_0402_50V8K

33P_0402_50V8K

2

7/13 For RF request

7/13 Add 33pFfor RF request
7/21 Reserve 33pFfor RF request

Q1A

Q1A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

6 1

+3VS

3

SRC PORT LIST

PORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

WLAN_CLKREQ#
WWAN_CLKREQ#
LAN_CLKREQ#

REQ PORT LIST

REQ_3#

REQ_4#
REQ_6#
REQ_7#

CLK_SMBDATA <10,17>
CLK_SMBCLK <10,17>

CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_HPLCLK <7>
CLK_CPU_HPLCLK# <7>

CPU_DREFCLK <7>
CPU_DREFCLK# <7>

CPU_SSCDREFCLK <7>
CPU_SSCDREFCLK# <7>

CLK_CPU_EXP <6>
CLK_CPU_EXP# <6>

CLK_PCIE_SATA <11>
CLK_PCIE_SATA# <11>

CLK_PCIE_WLAN <17>
CLK_PCIE_WLAN# <17>

1 2

C1067 56P_0402_50V8@C1067 56P_0402_50V8@

1 2

C1066 56P_0402_50V8@C1066 56P_0402_50V8@

CLK_PCIE_LAN <22>
CLK_PCIE_LAN# <22>

CLK_PCIE_PCH <12>
CLK_PCIE_PCH# <12>

CLK_PCIE_WWAN <17>
CLK_PCIE_WWAN# <17>

PCH_SMBDATA<13>

PCH_SMBCLK<13>

REQ_9#
REQ_10#

WLAN_CLKREQ# <17>

LAN_CLKREQ# <22>

WWAN_CLKREQ# <17>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

REQ_11#
REQ_A#

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855
4019AD

4019AD

4019AD

1

1

C941

@C941

@
33P_0402_50V8K

33P_0402_50V8K

2

+3VS

R83

R83

2.2K_0402_5%

2.2K_0402_5%

2
5

4

Q1B 2N7002DW-T/R7_SOT363-6Q1B 2N7002DW-T/R7_SOT363-6

R84

R84

2.2K_0402_5%

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

DEVICE

CPU_DREFCLK
CPU_EXP

PCIE_SATA
PCIE_WLAN

PCIE_LAN
PCIE_PCH
PCIE_WWAN

R99 10K_0402_5%R99 10K_0402_5%
R100 10K_0402_5%R100 10K_0402_5%
R101 10K_0402_5%R101 10K_0402_5%

12
12
12

DEVICEPORT

PEIC_WLAN

PCIE_LAN

PEIC_WWAN

of

936Wednesday, March 16, 2011

of

936Wednesday, March 16, 2011

of

936Wednesday, March 16, 2011

1

+3VS

D

D

D

5

DDR_A_DQS#[0..7]<6>

DDR_A_D[0..63]<6>

DDR_A_DM[0..7]<6>

DDR_A_DQS[0..7]<6>

DDR_A_MA[0..14]<6>

D D

+1.8V

2

2

1

C1078

C1078

C1077

C1077

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

1

+

+

@

@

C1080

C1080

C C

+0.9VS

1

1

2

2

C1091

C1091

C1092

B B

A A

C1092

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

M_ODT1
DDR_CS1#
DDR_A_CAS#
DDR_A_WE#

DDR_A_MA8
DDR_A_MA9

DDR_A_MA12

DDR_A_MA5

DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA6

DDR_CKE1
DDR_A_BS2
DDR_CKE0

5

2

2

C1081

C1081

0.1U_0402_16V4Z

0.1U_0402_16V4Z

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

1

1

2

2

C1093

C1093

C1094

C1094

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

R893

R893

1 2

47_0402_5%

47_0402_5%
R894

R894

1 2

47_0402_5%

47_0402_5%
R895

R895

1 2

47_0402_5%

47_0402_5%

2

2

1

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C1083

C1083

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C1096

C1096

0.1U_0402_16V4Z

0.1U_0402_16V4Z

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

C1073

C1073

1

2

C1097

C1097

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C1084

C1084

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RP2

RP2

RP4

RP4

RP6

RP6

C1079

C1079

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

2

C1082

C1082

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C1095

C1095

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+0.9VS

RP1

RP1

RP3

RP3

RP5

RP5

C1074

C1074

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1098

C1098

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_BS0

18

DDR_A_MA10

27

DDR_A_MA1

36

DDR_A_MA3

45

M_ODT0

18

DDR_A_MA13

27

DDR_CS0#

36

DDR_A_RAS#

45

DDR_A_MA4

18

DDR_A_MA11

27

DDR_A_MA7

36

DDR_A_MA14

45

2

1

1

2

Layout Note:
Place near JDDR1

1

2

C1099

C1099

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1100

C1100

1

2

C1101

C1101

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4

C1085

C1085

1

2

Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1000 mil

4

1

1

2

2

C1104

C1104

C1103

C1103

C1102

C1102

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closely DIMMA,all
trace length<1000 mil

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

1

2

+1.8V

12

R888

R888

1K_0402_1%

1K_0402_1%

+DIMM_VREF

12

R889

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C1086

C1086

@

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C1105

C1105

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R889

1K_0402_1%

1K_0402_1%

+DIMM_VREF

C1075

C1075

1

2

C1087

C1087

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C1106

C1106

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Share +DIMM_VREF for

1.DDRII VREF

2.GMCH SM_VREF_0
SM_VREF_1

20mils

1

2

1

1

2

2

C1088

C1088

C1089

C1089

C1090

C1090

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C1109

C1109

C1108

C1108

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1107

C1107

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Modify DDR3 to DDR2
Derek 8/19

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C1076

C1076

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C1110

C1110

0.1U_0402_16V4Z

0.1U_0402_16V4Z

3

2

+1.8V

JDDR1

JDDR1

+DIMM_VREF

DDR_CKE0<6>

DDR_A_BS2<6>

DDR_A_BS0<6>

DDR_A_CAS#<6>

DDR_CS1#<6>

M_ODT1<6>

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CLK_SMBDATA<9,17>

CLK_SMBCLK<9,17>

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2009/04/07 2012/10/21

2009/04/07 2012/10/21

2009/04/07 2012/10/21

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D9
DDR_A_D8

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_D16
DDR_A_D17

DDR_A_DM2

DDR_A_D18
DDR_A_D19

DDR_CKE0

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1#

M_ODT1
DDR_A_D33

DDR_A_D32
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D34
DDR_A_D41

DDR_A_D40
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D62

DDR_A_D59
CLK_SMBDATA

CLK_SMBCLK

1

C1111

C1111

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

1

C1112

C1112

2

Deciphered Date

Deciphered Date

Deciphered Date

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

G1

FOX_AS0A426-N4SN-7F_200P

FOX_AS0A426-N4SN-7F_200P
CONN@

CONN@

DIMMA

2

DQS3#

NC/CKE1

NC/A15
NC/A14

NC/A13

DQS5#

DQS7#

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS
DQS3

VSS
DQ30
DQ31

VSS

VDD

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS
DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS
DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

+1.8V

2

DDR_A_D5

4

DDR_A_D4

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D12

20

DDR_A_D13

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34

DDR_A_D14

36

DDR_A_D15

38
40

42

DDR_A_D24

44

DDR_A_D25

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

G2

DDR_A_DM3

52
54

DDR_A_D26

56

DDR_A_D27

58
60

DDR_A_D20

62

DDR_A_D21

64
66

DDR_A_DQS#2

68

DDR_A_DQS2

70
72

DDR_A_D22

74

DDR_A_D23

76
78

DDR_CKE1

80
82
84

DDR_A_MA14

86
88

DDR_A_MA11

90

DDR_A_MA7

92

DDR_A_MA6

94
96

DDR_A_MA4

98

DDR_A_MA2

100

DDR_A_MA0

102
104

DDR_A_BS1

106

DDR_A_RAS#

108

DDR_CS0#

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D36

124

DDR_A_D37

126
128

DDR_A_DM4

130
132

DDR_A_D38

134

DDR_A_D35

136
138

DDR_A_D44

140

DDR_A_D45

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D46

152

DDR_A_D47

154
156

DDR_A_D52

158

DDR_A_D53

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D58

192

DDR_A_D63

194
196

R891 10K_0402_5%R891 10K_0402_5%

198
200

202

1 2

R892 10K_0402_5%R892 10K_0402_5%

1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

4019AD

4019AD

4019AD

1

M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>

PM_EXTTS#0 <7>

DDR_CKE1 <6>

DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDR_CS0# <6>DDR_A_WE#<6>

M_ODT0 <6>

M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

10 36Wednesday, March 16, 2011

10 36Wednesday, March 16, 2011

10 36Wednesday, March 16, 2011

1

D

D

D

of

of

of

+3VS

R539 8.2K_0402_5%R539 8.2K_0402_5%

1 2

R540 8.2K_0402_5%R540 8.2K_0402_5%

1 2

+3VS

D D

+3VS

+3VS

+3VS

C C

+3VS

B B

RP7

RP7

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP8

RP8

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP16

RP16

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%
RP10

RP10

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP11

RP11

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

5

PCI_PIRQB#
PCI_PIRQF#
PCI_PIRQC#
PCI_PIRQA#

PCI_PIRQE#
PCI_PLOCK#
PCI_PIRQG#
PCI_IRDY#

PCI_SERR#
PCI_PERR#
PCI_TRDY#
GPIO1

GPIO22
PCI_DEVSEL#
PCI_PIRQD#
PCI_PIRQH#

REQ2#
REQ1#
PCI_STOP#
PCI_FRAME#

RSVD01
RSVD02

CLK_PCI_PCH<9>
PCI_RST#<24>

4

100K_0402_5%

100K_0402_5%

For EC request.

R543

R543

10K_0402_5%

10K_0402_5%

@

@

@

@

1 2

CLK_PCI_PCH
PCI_RST#

12

R541

R541

R544

R544
10K_0402_5%

10K_0402_5%
@

@

R545

R545
1K_0402_5%

1K_0402_5%

+3VS

PCI_DEVSEL#

PCI_IRDY#
PCI_SERR#

PCI_STOP#
PCI_PLOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#

REQ1#
REQ2#

GPIO22
GPIO1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

RSVD01
RSVD02

R551

R551

1 2

8.2K_0402_5%

8.2K_0402_5%

R12
AE20
AD17
AC15
AD18

Y12
AA10
AA12

Y10
AD15

W10

V12
AE21
AE18
AD19

U12
AC17

AB13
AC13
AB15

Y14
AB16

AE24
AE23

AA14

V14

AD16
AB11
AB10

AD23

B15
A23
C22

B11

A10
D10
A16

A18
E16

G16
A20

G14
C15

H10

D11

M13

A5

J12

B7

F14

A8

A2
C9

B2
D7
B3

E8
D6
H8
F8

K9

U15A

U15A

PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#

GNT1#
GNT2#

REQ1#
REQ2#

GPIO48/STRAP1#
GPIO17/STRAP2#
GPIO22
GPIO1

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

STRAP0#
RSVD01
RSVD02

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

U15C

U15C

RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18

RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

RSVD24
RSVD25
RSVD26

RSVD27
RSVD28

RSVD29
RSVD30
RSVD31

GPIO36

TGP

TGP

PCI

PCI

TGP

TGP

3

SATA

SATA

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

1

1

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

SATALED#

A20GATE

A20M#

CPUSLP#

IGNNE#

INIT3_3V#

FERR#

RCIN#

HOST

HOST

SERIRQ

STPCLK#

THRMTRIP#

INIT#
INTR

NMI

SMI#

B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1

H16
M15
C13
L16

AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9

AD4
AC4

AD11
AC11
AD25

U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20

SATARBIAS

GATEA20
H_A20M#

H_IGNNE#
H_INIT#

H_INTR
H_FERR#
H_NMI
EC_KBRST#
SERIRQ
H_SMI#
H_STPCLK#

T63 PADT63 PAD
T64 PADT64 PAD
T65 PADT65 PAD
T66 PADT66 PAD

CLK_PCIE_SATA# <9>
CLK_PCIE_SATA <9>

R547 24.9_0402_1%R547 24.9_0402_1%

SATALED# <26>

GATEA20 <24>
H_A20M# <7>

H_IGNNE# <7>
H_INIT# <7>

H_INTR <7>
H_FERR# <7>
H_NMI <7>
EC_KBRST# <24>
SERIRQ <24>
H_SMI# <7>
H_STPCLK# <7>

2

PCI_RST#

CLK_PCI_PCH

@

@

10_0402_5%

10_0402_5%

8.2P_0402_50V8D

8.2P_0402_50V8D

For EMI, close to TigerPoint

SATA_IRX_C_DTX_N0 <19>
SATA_IRX_C_DTX_P0 <19>
SATA_ITX_DRX_N0 <19>
SATA_ITX_DRX_P0 <19>

Please closed Tiger point
PIN within 500 mils

+1.05VS

12

R552

R552
56_0402_5%

56_0402_5%

R110 to be within 1" from the Tiger
Point chipset.

H_THERMTRIP# <7>

1

12

1

@

2

C1015

C1015

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H_FERR#

@

+1.05VS

R546

R546
56_0402_5%

56_0402_5%

R542

R542

@

@

C1016

C1016

1

2

R111 closed TigerPoint within 1"

+3VS

R548

SATALED#

GATEA20

SERIRQ

R548

10K_0402_5%

10K_0402_5%

R549

R549
10K_0402_5%

10K_0402_5%
R550

R550

1 2

8.2K_0402_5%

8.2K_0402_5%

3

A A

5

4

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

4019AD

4019AD

4019AD

11 36Wednesday, March 16, 2011

11 36Wednesday, March 16, 2011

11 36Wednesday, March 16, 2011

1

D

D

D

of

of

of

5

4

3

2

1

D D

TGP

U15B

U15B

DMI_TXN0<6>
DMI_TXP0<6>
DMI_RXN0<6>
DMI_RXP0<6>
DMI_TXN1<6>
DMI_TXP1<6>
DMI_RXN1<6>
DMI_RXP1<6>

C C

WLAN+BT Combo

LAN

WWLAN

PCIE_ITX_PRX_N2

PCIE_ITX_PRX_P2

B B

# PVT C225, C226 add
12p to GND for RF

C225

RF@C225

RF@

1 2

12P_0402_50V8J

12P_0402_50V8J
C226

RF@C226

RF@

1 2

12P_0402_50V8J

12P_0402_50V8J

PCIE_PTX_C_IRX_N2<17>
PCIE_PTX_C_IRX_P2<17>

PCIE_ITX_C_PRX_N2<17>

PCIE_ITX_C_PRX_P2<17>

PCIE_PTX_C_IRX_N3<22>

PCIE_PTX_C_IRX_P3<22>
PCIE_ITX_C_PRX_N3<22>
PCIE_ITX_C_PRX_P3<22>
PCIE_PTX_C_IRX_N4<17>

PCIE_PTX_C_IRX_P4<17>
PCIE_ITX_C_PRX_N4<17>
PCIE_ITX_C_PRX_P4<17>

C1017 0.1U_0402_10V6KC1017 0.1U_0402_10V6K
C1018 0.1U_0402_10V6KC1018 0.1U_0402_10V6K

C1019 0.1U_0402_10V6KC1019 0.1U_0402_10V6K
C1020 0.1U_0402_10V6KC1020 0.1U_0402_10V6K

C1021 0.1U_0402_10V6K@C1021 0.1U_0402_10V6K@
C1022 0.1U_0402_10V6K@C1022 0.1U_0402_10V6K@

Please closed Tiger point
PIN within 500 mils

CLK_PCIE_PCH#<9>
CLK_PCIE_PCH<9>

12
12

12
12

12
12

+1.5VS

T51PAD T51PAD
T52PAD T52PAD
T53PAD T53PAD
T54PAD T54PAD
T55PAD T55PAD
T56PAD T56PAD
T57PAD T57PAD
T58PAD T58PAD

T59PAD T59PAD
T60PAD T60PAD
T61PAD T61PAD
T62PAD T62PAD

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2

PCIE_ITX_PRX_N2

PCIE_ITX_PRX_P2
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3

PCIE_ITX_PRX_N3

PCIE_ITX_PRX_P3
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4

PCIE_ITX_PRX_N4

PCIE_ITX_PRX_P4

R555 24.9_0402_1%R555 24.9_0402_1%

1 2

R23

DMI0RXN

R24

DMI0RXP

P21

DMI0TXN

P20

DMI0TXP

T21

DMI1RXN

T20

DMI1RXP

T24

DMI1TXN

T25

DMI1TXP

T19

DMI2RXN

T18

DMI2RXP

U23

DMI2TXN

U24

DMI2TXP

V21

DMI3RXN

V20

DMI3RXP

V24

DMI3TXN

V23

DMI3TXP

K21

PERN1

K22

PERP1

J23

PETN1

J24

PETP1

M18

PERN2

M19

PERP2

K24

PETN2

K25

PETP2

L23

PERN3

L24

PERP3

L22

PETN3

M21

PETP3

P17

PERN4

P18

PERP4

N25

PETN4

N24

PETP4

H24

DMI_ZCOMP

J22

DMI_IRCOMP

W23

DMI_CLKN

W24

DMI_CLKP

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

TGP

USB20_N0

H7

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P

DMI PCI-E

DMI PCI-E

USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

OC0#
OC1#
OC2#
OC3#

USB

USB

OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

USBRBIAS

USBRBIAS#

CLK48

2

2

USB20_P0

H6

USB20_N1

H3

USB20_P1

H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2

D4
C5
D3
D2
E5
E6
C2
C3

G2
G3

F4

T49 PADT49 PAD
T50 PADT50 PAD

USB20_N4
USB20_P4
USB20_N5_L
USB20_P5_L
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USB_OC#0_1_PCH
USB_OC#0_1_PCH
USB_OC#2
USB_OC#3
USB_OC#4_PCH
SLP_CHG_M3_PCH
SLP_CHG_M4_PCH
USB_OC#7

22.6_0402_1%

22.6_0402_1%

CLK_PCH_48M

12

R554

R554
33_0402_5%

33_0402_5%

1

@

@

C1023

C1023
22P_0402_50V8J

22P_0402_50V8J

2

For EMI, Close to TigerPoint

R553

R553

@

@

USB20_N0 <18>
USB20_P0 <18>
USB20_N1 <18>
USB20_P1 <18>

USB20_N3 <23>
USB20_P3 <23>
USB20_N4 <18>
USB20_P4 <18>

USB20_N6 <17>
USB20_P6 <17>
USB20_N7 <16>
USB20_P7 <16>

USB_OC#0_1_PCH <18>

USB_OC#4_PCH <18>
SLP_CHG_M3_PCH <18>

SLP_CHG_M4_PCH <18>

#EVT 6/27 support sleep charge function

CLK_PCH_48M <9>

USB1(Right)
USB2(Right)

Card-reader

USB3(Left)
WWAN
WLAN + BT (Combo)
CMOS

#DVT USB_OC# control by EC PCH reserve

Please closed Tiger point
PIN within 200 mils

1 2

R3 0_0402_5%R3 0_0402_5%

L2

RF@ L2

USB20_N5_L

USB20_P5_L

2010.07.12 RF request

RF@

1

1

4

4

WCM-2012-900T_0805

WCM-2012-900T_0805

1 2

R4 0_0402_5%R4 0_0402_5%

2

2

3

3

USB20_N5

USB20_P5

USB PORT LIST

PORT

#EVT DEVICE
USB0
USB1
USB2
USB3
USB4
USB5
USB6
USB7

#6/27 EVT

USB1(Left)
USB2(Left)
NC
Card-reader
USB3(Right)
WWAN
WLAN + BT
CMOS

USB_OC#0_1_PCH
SLP_CHG_M4_PCH
USB_OC#7

10K_0804_8P4R_5%

10K_0804_8P4R_5%

USB_OC#3
USB_OC#2
USB_OC#4_PCH
SLP_CHG_M3_PCH

10K_0804_8P4R_5%

10K_0804_8P4R_5%

USB20_N5 <17>

USB20_P5 <17>

RP12

RP12
4 5
3 6
2 7
1 8

RP13

RP13
4 5
3 6
2 7
1 8

+3VALW

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/27 2011/6/27

2010/06/27 2011/6/27

2010/06/27 2011/6/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A6855

SCHEMATIC A6855

SCHEMATIC A6855

4019AD

4019AD

4019AD

1

D

D

D

of

of

of

12 36Wednesday, March 16, 2011

12 36Wednesday, March 16, 2011

12 36Wednesday, March 16, 2011