Compal LA-6161P Fossil 2.0 UMA Schematic

A

1 1

B

C

D

E

Compal Confidential

Schematics Document

2 2

INTEL Auburndale BGA with IBEX core logic

Fo

3 3

ssil 2.0 UMA

LA-6161P

2010-05-18

REV:0.5

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-6161P

E

1 41Tuesday, May 18, 2010

0.5

A

Compal Confidential

File Name : LA-6161P

B

C

Fossil 2.0 UMA

D

XDP Conn.

Page 4

E

Accelerometer

LI S30 2DLTR

DD R3-SO-DIMM X 1DDR3 1066/1333MHz 1.5V

Mobile

1 1

Single Channel

BANK 2 , 3

Arrandale CPU

Page 9

Fan C ontrol

Page 22

Page 4

BG A 1288pins

LVDS

Display port

Page 18

Page 17

DDI_D

FDI

Page 4,5,6,7,8

DM I X4

BT(SoftBreeze) Conn USB x 1

page 26

CRT

Page 19

2 2

WWAN
+SIM Card

USB*1

Page 22

USB2.0

PCI-E BUS

10/100/1 000 LAN
RT L8151DH-GR

Page 21

3 3

RJ45 CONN

Page 21

WLAN Card

PCIE*1

Page 22

DDI

USB2.0

Intel Ibex Peak M

Azalia

10 71pi ns

25mm*27mm

SATA0

Page 11,12,13,14,15,16

ONFI Interface

USB conn x 3(For I/O)

page 24

CardReader Controller

RealTe k RTS5159

USB x1(Camara)

FPR conn x1

Audio CKT

IDT 92HD80

Page 18

Page 19

Page 23

daughter board

SD/MM C Slot

sub/B Page 3

daughter board

Audio Jack

sub/B Page 2

SPI BUS

RTC CKT.

Page 11

Power OK CKT.

4 4

Power On/Off CKT.

DC/DC Interface CKT.

Page 29

Page 25

Page 30

LED

LED Board

Page 20

A

Touch Pad CONN.

Page 25

SP I ROM 4 M B

MX25L6445EM2I-10G

B

Page 27

SMSC KBC 1098

page 28

Int.KBD

Page 25

SPI BUS

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

D

Page 19

CK505

Clock Generator
SL G8SP5 85V T R

Page 11

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-6161P

E

2 41Tues day, May 18, 2010

0.5

SATA HDD Connector

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

( O MEANS ON X MEANS OFF )

+RTCVCC

power
plane

O

O

O

O

O

O

+B

+3VL +0.75V

O

O

O

O

O

X

+5VALW

+3VALW

O

O

O

O

X

X X X

+1.5V

O

X X

X

+5VS

+3VS

+1.5VS

+VCCP

+CPU_CORE

1.05VS

+

+1.8VS

OO

OO

X

X

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

ULV@ : means just install for ULV CPU
CONN@ : means ME part.

Lay out Note s

L

07/ 24 upda te

: Q ues ti on Are a Mar k.( Wait che ck)

Install below 45 level BOM structure for ver. 0.1

4

5@ : means just put it in the BOM of 45 level.

Install below 43 level BOM structure for ver. 0.1

DEBUG@ : means just build when PCIE port 80 CARD function enable.

Remove before MP

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMBCLK
SMBDATA

SML0CLK
SML0DATA

SML1CLK
SML1DATA

SMSC1098

Calpella

Calpella

Calpella

BATT

V

X
X
X

THERMAL

SODIMM CLK CHIP

XDP G-SENSOR

X

X X

V V

X

X

X X

MINI CARD

X

V V

X

X

X X

DOCK

X

V

X
X

SENSOR

NIC

X X
X

V

X

X
X

V

X

V

X

V

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/03

A

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-6161P

3 41Tues day, May 18, 2010

0.5

Layout rule 1 0mil w idth ：trace
length < 0.5 ", spa cing 20mil

A A

H_ PECI<14>

to power; PU to VCCP at power side also

H_ PROCH OT#<37>

H_T HERM TRIP#<14>

H_ CPUR ST#

H_ PM_S YNC<13>

H_ CPU PW RGD

H_ CPU PW RGD< 14>

B B

PM_ DRAM _PWR GD<13>

from power

VTT PWRG OOD<29>

BUF _PLT_R ST#< 14>

C C

PM_ PWRB TN#_R

1

R22 0_040 2_1%

1 2

R52 0_040 2_1%

1 2

R74 9.9_0 402_1%

1 2

R94 9.9_0 402_1%

1 2

T48PA D

R1 4

1 2

0_04 02_5%

R1 5

1 2

0_04 02_5%

R1 7

1 2

0_04 02_5%

R1 8

@

1 2

0_04 02_5%

R1 9

1 2

0_04 02_5%

R2 1

1 2

0_04 02_5%

R2 2

1 2

0_04 02_5%

R2 6

1 2

0_04 02_5%

R3 2

1 2

0_04 02_5%@

1 2

1.5K _0402 _1%

750_ 0402_1%

@

1 2

R2 0 1K_ 0402_5%

H_CO MP3

H_CO MP2

H_CO MP1

H_CO MP0

TP_ SKTOCC#

H_ CATE RR#

H_P ECI_I SO

H_ PRO CHOT# _D

H_T HERM TRIP# _R

H_ CPUR ST#_ R

H_ PM_ SYNC _R

SYS _AGE NT_P WROK

VC CPW RGOO D_0

VD DPW RGO OD_R

H_ PWRG D_XD P_RH_P WRGD _XDP

PLT _RST#_R

R3 3

12

R3 5

+VC CP

U1 B

AD71

COMP3

AC70

COMP2

AD69

COMP1

AE66

COMP0

M71

PROC_DETECT

N61

CATERR#

N19

PECI

N67

PROCHOT#

N17

THERMTRIP#

N70

RESET_OBS#

M17

PM_SYNC

AM7

VCCPWRGOOD_1

Y67

VCCPWRGOOD_0

AM5

SM_DRAMPWROK

H15

VTTPWRGOOD

Y70

TAPPWRGOOD

G3

RSTIN#

INT EL_A UBURN DALE _1288

2nd So urce :
SV - i 5-540M CPU : 2.53 G (K0 )

SV - i 5-450M CPU : 2.4G (K0)
SV - i 3-350M CPU : 2.26G (K0)
SV- i3 -370M CPU : 2.4G (K0)
ULV -U 3400 C PU : 1 .06G (K0)

Misc

Thermal Power Management

Intel S3 power reduction circuit for Calpella. 11/09

VD DPW RGO OD_R

1 2

R1 2 1.5K_ 0402_1%

1 2

R1 3 750_04 02_1%

Clocks

DDR3

Misc

JTAG & MBP

2

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#

PREQ#

TCK
TMS

TRST#

TDI

TDO

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

VC CP_1. 5VSP WRG D < 29>

AK7
AK8

K71
J70

L21
J21

Y2
W4

BJ12

BV33
BP39
BV40

AV66
AV64

U71
U69

T67
N65
P69

T69
T71
P71
T70

W71

J69
J67
J62
K65
K62
J64
K69
M69

CL K_CP U_BC LK
CLK _CPU_ BCLK #

CLK _CPU_ XDP
CLK _CPU_ XDP#

CLK_EX P
CLK_ EXP#

SM_ DRAMR ST#

SM_ RCOMP0
SM_ RCOMP1
SM_ RCOMP2

PM_EXTTS#0
PM_EXTTS#1

XDP _PRD Y#
XDP _PREQ#

XDP _TCK
XDP_TMS
XDP_TR ST#

XDP _TDI
XDP _TDO
XDP _TDI_M

XDP _DBRES ET#

XDP_B PM#0
XDP_B PM#1
XDP_B PM#2
XDP_B PM#3
XDP_B PM#4
XDP_B PM#5
XDP_B PM#6
XDP_B PM#7

R1 6

1 2

R1 493 0_ 0402_5%@
R1 494 0_ 0402_5%@

0.1U _0402 _16V4Z

CLK _CPU_ BCLK < 14>
CLK _CPU_ BCLK # < 14>

CLK_EX P <12>
CLK_EX P# <12>

CL K_DP <12 >
CLK _DP# <1 2>

T49 PA D

0_04 02_5%

PM_EX TTS#1_R <9>

1 2
1 2

reserv e for ESD, Compal SI 1/19

ESD re que st to add

+VC CP

1

C1

2

@

CF G12<5>

CF G13<5>

CF G14<5>

CF G15<5>

3

from DDR

XDP _PRE Q#_R
X DP_PR DY#_ R

XDP_B PM#0

XDP_B PM#1

XDP_B PM#2

XDP_B PM#3

XDP_B PM#4
XDP_B PM#5

XDP_B PM#6
XDP_B PM#7

H_ CPU PW RGD

PM_ PWRB TN#_R<13>

H_P WRGD _XDP

Add te st p oints

Intel S3 power reduction circuit for Calpella. 11/09

XDP _PRE Q#_R

CF G17<5>
CF G16<5>

1 2
1 2

1 2
1 2

R3 6

1 2

1K_ 0402_5%

R3 7

1 2

0_04 02_5%

X DP_PR DY#_ R

XDP _BPM#4_R

R4 30_04 02_5%

XDP _BPM#5_R

R4 80_04 02_5%

XDP _BPM#6_R

R4 00_04 02_5%

XDP _BPM#7_R

R4 10_04 02_5%

H_ CPU PW RGD_ R
PM_ PWRB TN#_R

T112PA D
T113PA D

XDP _TCK

R2 3 0_04 02_5%

1 2

R2 4 0_04 02_5%@

1 2

R2 5 0_04 02_5%

1 2

R2 7 0_04 02_5%@

1 2

R2 8 0_04 02_5%

1 2

R2 9 0_04 02_5%@

1 2

R3 0 0_04 02_5%

1 2

R3 1 0_04 02_5%@

1 2

PWM Fan Control circuit

SM_ DRAMR ST#

R1 092

100K _0402_5 %

@

4

R4 6 0_040 2_5%

1 2

12

2

CPU XDP Connector

JP4

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAM TE_BSH- 030-01-L-D -A CO NN@

R1 093

@

61

Q52A

2N70 02DW -7-F_S OT363-6

C6 470P _0402_5 0V7K

1 2

1K_ 0402_5%

12

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

+1.5 V

DRA MRST# <9>

PC H_D DR_RS T <14>

2

GND1

4
6
8

GND3

10
12
14

GND5

16
18
20

GND7

22
24
26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

CLK _CPU_ XDP
CLK _CPU_ XDP#

XDP _RST#_R
XDP _DBR ESET#_R

XDP _TDO
XDP_TR ST#
XDP _TDI
XDP_TMS

XDP _RST#_R

+5VS

CF G8 <5>
CF G9 <5>

CF G0 <5>
CF G1 <5>

CF G2 <5>
CF G3 <5>

CF G10 <5>
CF G11 <5>

CF G4 <5>
CF G5 <5>

CF G6 <5>
CF G7 <5>

+V CCP

1K_ 0402_5%@

R3 8

1 2
1 2

R3 9 0_040 2_5%

@

1 2

R4 2 0_0402_ 5%

PLT_ RST#

H_ CPUR ST#
XDP _DBRES ET#

5

+3VS

R3 4
1K_ 0402_5%

1 2

PLT_R ST# <14, 21,22, 27>

XDP _DBRESE T# <13>

DDR3 Compensation Signals

SM_ RCOMP0

SM_ RCOMP1 H_C ATER R#

SM_ RCOMP2

D D

1 2

R5 2 100_04 02_1%

1 2

R5 6 24.9_0 402_1%

1 2

R5 8 130_04 02_1%

Layout Note:Please these
resist ors near Processor

1

Processor Pullups

R4 4 49.9 _0402_1 %

H_ PRO CHOT# _D

H_ CPUR ST#_ R

1 2

1 2

R4 5 68_040 2_5%

1 2

R4 7 68_040 2_5%@

+VC CP

DDR Pullups

PM_EXTTS#0

1 2

R1

PM_EXTTS#1

1 2

R3

011 2 R em ove unin stall part s

XDP_TR ST#

Close to XDP

XDP _TDO

2

10K _0402_5%

10K _0402_5%

1 2

R5 9 51_04 02_5%

1 2

R1 0 51_04 02_5%

This s hall place near XDP

+V CCP

+V CCP

R8 96
10K _0402_5%

1 2

Compal Secret Data

FAN _PWM

FAN _PWM<28>

+VC CP

Q26

H_ PROC HOT#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PMBT3 904_SOT23

+3VS

CBE

123

2008/09/15 2009/09/03

1

2

Deciphered Date

4

+3VS

5

U5 0

P

INB

O

INA

G

TC7 SH00F UF_S SOP5

3

R8 91 0_04 02_5%

for RF

12

C1 316

4

1

@

2

47P _0402_50 V8J

C3

1 2

0.1U _0402 _10V6K@
JF AN1

1

1

2

4

2

G1

3

5

3

G2

ACE S_85 204-03001

CO NN@

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

LA -6 161 P

5

4 4 1Tues day, May 18, 2010

0. 5

1

2

3

4

5

U1 A

DMI _CRX_PTX _N0<13>
DMI _CRX_PTX _N1<13>
DMI _CRX_PTX _N2<13>
DMI _CRX_PTX _N3<13>

DMI_C RX_PTX_P 0<13>

A A

B B

DMI_C RX_PTX_P 1<13>
DMI_C RX_PTX_P 2<13>
DMI_C RX_PTX_P 3<13>

DMI _CTX_PRX _N0<13>
DMI _CTX_PRX _N1<13>
DMI _CTX_PRX _N2<13>
DMI _CTX_PRX _N3<13>

DMI_C TX_PRX_P 0<13>
DMI_C TX_PRX_P 1<13>
DMI_C TX_PRX_P 2<13>
DMI_C TX_PRX_P 3<13>

FDI _CTX_ PRX_N0< 13>
FDI _CTX_ PRX_N1< 13>
FDI _CTX_ PRX_N2< 13>
FDI _CTX_ PRX_N3< 13>
FDI _CTX_ PRX_N4< 13>
FDI _CTX_ PRX_N5< 13>
FDI _CTX_ PRX_N6< 13>
FDI _CTX_ PRX_N7< 13>

FDI _CTX_PRX _P0<13>
FDI _CTX_PRX _P1<13>
FDI _CTX_PRX _P2<13>
FDI _CTX_PRX _P3<13>
FDI _CTX_PRX _P4<13>
FDI _CTX_PRX _P5<13>
FDI _CTX_PRX _P6<13>
FDI _CTX_PRX _P7<13>

FD I_F SYN C0< 13>
FD I_F SYN C1< 13>

FD I_I NT<13>

FD I_L SYN C0<13>
FD I_L SYN C1<13>

FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7

FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7

FD I_F SYN C0
FD I_F SYN C1

FD I_I NT

FD I_L SY NC0
FD I_L SY NC1

F7

K8

F9

K9

H17
K15

J13

F10

G17
M15
G13

J11

L2
N7

M4

P1

N10

R7
U7

W8

K1
N5
N2
R2
N9
R8
U6

W10

AC7
AC9

AB5

AA1
AB2

J8

J4

J6

J2

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

FDI_FSYNC[0]
FDI_FSYNC[1]

FDI_INT

FDI_LSYNC[0]
FDI_LSYNC[1]

PEG_RCOMPO

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

C C

INT EL_A UBURN DALE _1288

PEG_ICOMPI

PEG_ICOMPO

PEG_RBIAS

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B12
A13
D12
B11

G40
G38
H34
P34
G28
H25
H24
D29
B26
D26
B23
D22
A20
D19
A17
B14

F40
J38
G34
M34
J28
G25
K24
B28
A27
B25
A24
B21
B19
B18
B16
D15

N40
L38
M32
D40
A38
G32
B33
B35
L30
A31
B32
L28
N26
M24
G21
J20

L40
N38
N32
B39
B37
H32
A34
D36
J30
B30
D33
N28
M25
N24
F21
L20

EXP _ICOMPI

EXP _RBIAS

49.9 _0402_1 %
R6 4

1 2

R6 5

1 2

750_ 0402_1%

U1 E

CF G0

CF G0<4>
CF G1<4>
CF G2<4>
CF G3<4>
CF G4<4>
CF G5<4>
CF G6<4>
CF G7<4>
CF G8<4>
CF G9<4>
CF G10<4>
CF G11<4>
CF G12<4>
CF G13<4>
CF G14<4>
CF G15<4>
CF G16<4>
CF G17<4>

T50P AD T51 PA D

CF G1
CF G2
CF G3
CF G4
CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17

AV71

AW70

AY69
BB69

AL4

CFG[0]

AM2

CFG[1]

AK1

CFG[2]

AK2

CFG[3]

AK4

CFG[4]

AJ2

CFG[5]

AT2

CFG[6]

AG7

CFG[7]

AF4

CFG[8]

AG2

CFG[9]

AH1

CFG[10]

AC2

CFG[11]

AC4

CFG[12]

AE2

CFG[13]

AD1

CFG[14]

AF8

CFG[15]

AF6

CFG[16]

AB7

CFG[17]

AU1

RSVD_TP[0]

T4

RSVD15

T2

RSVD16

U1

RSVD17

V2

RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

D8

RSVD23

B7

RSVD24

A10

RSVD26

B9

RSVD27

C5

RSVD_NCTF[7]

A6

RSVD_NCTF[8]

E3

RSVD_NCTF[6]

F1

RSVD_NCTF[5]

INT EL_A UBURN DALE _1288

RSVD_NCTF[3]
RSVD_NCTF[4]

RSVD_NCTF[2]
RSVD_NCTF[1]

RESERVED

DC_TEST_BV71
DC_TEST_BV69
DC_TEST_BV68

DC_TEST_BV5
DC_TEST_BV3

DC_TEST_BV1
DC_TEST_BT71
DC_TEST_BT69

DC_TEST_BT3

DC_TEST_BT1
DC_TEST_BR71

DC_TEST_BR1

DC_TEST_E71

DC_TEST_C71
DC_TEST_C69

DC_TEST_A71
DC_TEST_A69
DC_TEST_A68

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36
RSVD37

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58

RSVD_TP[2]
RSVD_TP[1]

RSVD62
RSVD63

RSVD64
RSVD65

DC_TEST_E1

DC_TEST_C3

DC_TEST_A5

W66
W64

AC69
AC71

AA71
AA69

R66
R64

BT5
BR5

BV6
BV8

AV69
AK71
AN69
AP66
AH66
AK66
AR71
AM66
AK69
AU71
AT70
AR69
AU69
AT67

AP2
AN7

AV4
AU2

BE69
BE71

BV71
BV69
BV68
BV5
BV3
BV1
BT71
BT69
BT3
BT1
BR71
BR1
E71
E1
C71
C69
C3
A71
A69
A68
A5

T116 P AD
T117 P AD

T118 P AD

T119 P AD

T120 P AD

T52 PA D

VSS _NCT F2_R <8>
VSS _NCT F6_R <8>

VSS _NCT F1_R <8>
VSS _NCT F7_R <8>

CFG Straps for PROCESSOR

CF G0

R6 8 3.01 K_040 2_1%@

1 2

PCI-Ex press Configuration Select

CFG0

Not ap plica ble f or Clarksfield Processor

CF G3

CFG3-P CI Ex press Static Lane Reversal

CFG3

CF G4

D D

ES1 sa mple n eed ne gative voltage
ES2 sa mple c ontact to GND

CFG4-D isplay Port Presence

CFG4

1: Single PEG
0: Bif urcation enabled

R6 9 3.01 K_040 2_1%@

1 2

1: Nor mal Operation
0: Lan e Numbers Reversed

15 -> 0, 14 ->1, .....

R7 0 3.01K _0402_1%

1 2

1: Dis abled ; No Physical Display Port
attach ed to Embedded Display Port

0: Ena bled; An external Display Port
device is c onnected to the Embedded
Display Port

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

LA -6 161 P

5

5 4 1Tues day, May 18, 2010

0. 5

1

2

3

4

5

AW2

BV10
BR10

BT12

BT15
BV15
BV12
BP12
BV17
BU16
BP15
BU19
BV22

BT22
BP19
BV19
BV20

BT20

BT48
BV48
BV50
BP49

BT47
BV52
BV54

BT54
BP53
BU53

BT59

BT57
BP56

BT55
BU60
BV59
BV61
BP60
BR66
BR64
BR62

BT61
BN68

BL69

BJ71

BF70
BG71
BC67
BK70
BK67
BD71
BD69

BV43
BV41
BV24

BU46

BT40

BT41

U1D

BU33

SB_CK[0]

BV34

SB_CK#[0]

BA2

SB_DQ[0]
SB_DQ[1]

BD1

SB_DQ[2]

BE4

SB_DQ[3]

AY1

SB_DQ[4]

BC2

SB_DQ[5]

BF2

SB_DQ[6]

BH2

SB_DQ[7]

BG4

SB_DQ[8]

BG1

SB_DQ[9]

BR6

SB_DQ[10]

BR8

SB_DQ[11]

BJ4

SB_DQ[12]

BK2

SB_DQ[13]

BU9

SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY - B

SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BT26

BV38
BU39
BT24

BP46
BT43

BV45
BU49

BB4
BL4
BT13
BP22
BV47
BV57
BU65
BF67

BE2
BM3
BU12
BT19
BT52
BV55
BU63
BG69

BD4
BN4
BV13
BT17
BT50
BU56
BV62
BJ69

BT34
BP30
BV29
BU30
BV31
BT33
BT31
BP26
BV27
BT27
BU42
BU26
BT29
BT45
BV26
BU23

U1C

A A

B B

C C

DD R_A _D[0 ..63]< 9>

DD R_A_B S0<9>
DD R_A_B S1<9>
DD R_A_B S2<9>

DD R_A_ CAS#<9>
DD R_A_ RAS#<9>
DD R_A_ WE#<9>

DD R_A _D0
DD R_A _D1
DD R_A _D2
DD R_A _D3
DD R_A _D4
DD R_A _D5
DD R_A _D6
DD R_A _D7
DD R_A _D8
DD R_A _D9
DD R_A _D10
DD R_A _D11
DD R_A _D12
DD R_A _D13
DD R_A _D14
DD R_A _D15
DD R_A _D16
DD R_A _D17
DD R_A _D18
DD R_A _D19
DD R_A _D20
DD R_A _D21
DD R_A _D22
DD R_A _D23
DD R_A _D24
DD R_A _D25
DD R_A _D26
DD R_A _D27
DD R_A _D28
DD R_A _D29
DD R_A _D30
DD R_A _D31
DD R_A _D32
DD R_A _D33
DD R_A _D34
DD R_A _D35
DD R_A _D36
DD R_A _D37
DD R_A _D38
DD R_A _D39
DD R_A _D40
DD R_A _D41
DD R_A _D42
DD R_A _D43
DD R_A _D44
DD R_A _D45
DD R_A _D46
DD R_A _D47
DD R_A _D48
DD R_A _D49
DD R_A _D50
DD R_A _D51
DD R_A _D52
DD R_A _D53
DD R_A _D54
DD R_A _D55
DD R_A _D56
DD R_A _D57
DD R_A _D58
DD R_A _D59
DD R_A _D60
DD R_A _D61
DD R_A _D62
DD R_A _D63

BF11
BE11

BH13

BN11

BG17
BK15

BG15
BH17
BK17
BN20
BN17
BK25
BH25
BJ20
BH21
BG24
BG25
BJ40

BM43

BF47

BF48
BN40
BH43
BN44
BN47
BN48
BN51
BH53

BJ55
BH48

BJ48
BM53
BN55

BF55
BN57
BN65

BJ61

BF57

BJ57
BK64
BK61

BJ63

BF64
BB64
BB66

BJ66

BF65
AY64
BC70

BT38

BH38

BF21

BK43

BL38

BF38

AT8

SA_DQ[0]

AT6

SA_DQ[1]

BB5

SA_DQ[2]

BB9

SA_DQ[3]

AV7

SA_DQ[4]

AV6

SA_DQ[5]

BE6

SA_DQ[6]

BE8

SA_DQ[7]
SA_DQ[8]
SA_DQ[9]

BK5

SA_DQ[10]
SA_DQ[11]

BF9

SA_DQ[12]

BF6

SA_DQ[13]

BK7

SA_DQ[14]

BN8

SA_DQ[15]
SA_DQ[16]

BN9

SA_DQ[17]
SA_DQ[18]
SA_DQ[19]

BK9

SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

BM34
BP35
BF20

BK36
BH36
BK24

BH40
BJ47

BF43
BL47

BB10
BJ10
BM15
BN24
BG44
BG53
BN62
BH59

AY5
BJ7
BN13
BL21
BH44
BK51
BP58
BE62

AY7
BJ5
BL13
BN21
BK44
BH51
BM60
BE64

BT36
BP33
BV36
BG34
BG32
BN32
BK32
BJ30
BN30
BF28
BH34
BH30
BJ28
BF40
BN28
BN25

DD R_A_ DM0
DD R_A_ DM1
DD R_A_ DM2
DD R_A_ DM3
DD R_A_ DM4
DD R_A_ DM5
DD R_A_ DM6
DD R_A_ DM7

DD R_A_ DQS# 0
DD R_A_ DQS# 1
DD R_A_ DQS# 2
DD R_A_ DQS# 3
DD R_A_ DQS# 4
DD R_A_ DQS# 5
DD R_A_ DQS# 6
DD R_A_ DQS# 7

DD R_A _DQS 0
DD R_A _DQS 1
DD R_A _DQS 2
DD R_A _DQS 3
DD R_A _DQS 4
DD R_A _DQS 5
DD R_A _DQS 6
DD R_A _DQS 7

DDR_ A_M A0
DDR_ A_M A1
DDR_ A_M A2
DDR_ A_M A3
DDR_ A_M A4
DDR_ A_M A5
DDR_ A_M A6
DDR_ A_M A7
DDR_ A_M A8
DDR_ A_M A9
DDR_ A_MA 10
DDR_ A_MA 11
DDR_ A_MA 12
DDR_ A_MA 13
DDR_ A_MA 14
DDR_ A_MA 15

M_ CLK_D DR0 <9>
M_ CLK_D DR#0 <9>
DDR_ CKE0 _DIM MA <9>

M_ CLK_D DR1 <9>
M_ CLK_D DR#1 <9>
DDR_ CKE1 _DIM MA <9>

DDR_ CS0_ DIMM A# <9>
DDR_ CS1_ DIMM A# <9>

M_ODT 0 <9>
M_ODT 1 <9>

DD R_A_ DM[0 ..7] <9>

DD R_A_ DQS# [0..7 ] <9>

DD R_A _DQS [0..7 ] <9>

DDR_ A_MA [0.. 15] <9>

INT EL_A UBURN DALE _1288

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

INT EL_A UBURN DALE _1288

Compal Secret Data

Deciphered Date

Title

Size D ocum ent N umber R ev

Cu sto m

4

Da te: She et o f

Compal Electronics, Inc.

Auburndale(3/5)-DDR3

LA -61 61P

5

6 4 1Tue sday , Ma y 18, 2010

0. 5

1

+GF X_CORE

22U_ 0805_ 6.3V6M

C1 7

1

2

C2 14

1

2

C2 18

1

2

C3 80

1

2

10U_ 0805_ 6.3V6M

1

2

1U_0 402_6 .3V6K

C3 5

10U_ 0805_6. 3V6M

1

2

+C PU_C ORE

@

+C PU_C ORE

1U_0 402_6 .3V6K

1

2

1

1U_0 402_6 .3V6KZ

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C3 0

C6 1

C5 5

C1 8

C2 13

C2 17

C2 21

1

2

+V CCP

1

2

C6 16

22U_ 0805_ 6.3V6M

C1 9

1

2

1

2

1U_0 402_6 .3V6K

C3 6

1

2

47P _0402_50 V8J

1U_0 402_6 .3V6K

10U_ 0805_ 6.3V6M

1

2

10U_ 0805_6. 3V6M

for RF

@

C6 23

1

2

C3 1

C6 2

C5 6

1

2

1U_0 402_6 .3V6K

U1 G

AN32

VAXG1

AN30

VAXG2

AN28

VAXG3

AN26

VAXG4

AN24

VAXG5

AN23

VAXG6

AN21

VAXG7

AN19

VAXG8

AL32

VAXG9

AL30

VAXG10

AL28

VAXG11

AL26

VAXG12

AL24

VAXG13

AL23

VAXG14

AL21

VAXG15

AL19

VAXG16

AK14

VAXG17

AK12

VAXG18

AJ10

VAXG19

AH14

VAXG20

AH12

VAXG21

AF28

VAXG22

AF26

VAXG23

AF24

VAXG24

AF23

VAXG25

AF21

VAXG26

AF19

VAXG27

AF17

VAXG28

AF15

VAXG29

AF14

VAXG30

AD28

VAXG31

AD26

VAXG32

AD24

VAXG33

AD23

VAXG34

AD21

VAXG35

AD19

VAXG36

AD17

VAXG37

W21

VTT1_1

W19

VTT1_2

U21

VTT1_3

U19

VTT1_4

U17

VTT1_5

U15

VTT1_6

U14

VTT1_7

U12

VTT1_8

R21

VTT1_9

R19

VTT1_10

R17

VTT1_11

AK62

VCAP2_1

AK60

VCAP2_2

AK59

VCAP2_3

AH60

VCAP2_4

AH59

VCAP2_5

AF60

VCAP2_6

AF59

VCAP2_7

AD60

VCAP2_8

AD59

VCAP2_9

AB60

VCAP2_10

AB59

VCAP2_11

AA60

VCAP2_12

AA59

VCAP2_13

W60

VCAP2_14

W59

VCAP2_15

U60

VCAP2_16

U59

VCAP2_17

R60

VCAP2_18

R59

VCAP2_19

INT EL_A UBURN DALE _1288

47P _0402_50 V8J

47P _0402_50 V8J

C5 7

1

@

2

1U_0 402_6 .3V6K

C6 43

C6 17

1

1

2

2

47P _0402_50 V8J

C5 8

1

@

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 45

1

2

1U_0 402_6 .3V6K

C1 6

1

2

1U_0 402_6 .3V6K

C1 79

1

2

1U_0 402_6 .3V6K

C2 15

1

2

1U_0 402_6 .3V6K

C2 19

1

2

10U_ 0805_ 6.3V6M

C2 9

1U_0 402_6 .3V6K

C3 4

1

2

10U_ 0805_6. 3V6M

C6 0

12P _0402_5 0V8J

47P _0402_50 V8J

C6 15

+

330U _D2_2 .5VM_ R6M

C1 313

1

2

1

2

1

2

+V CCP

1U_0 402_6 .3V6K

C3 2

for RF

1

2

12P _0402_5 0V8J

47P _0402_50 V8J

1

2

+VC AP2

12P _0402_50 V8J

C1 321

@

@

1U_0 402_6 .3V6K

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C2 12

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C2 16

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C2 20

1

2

10U_ 0805_ 6.3V6M

C2 8

1

2

1U_0 402_6 .3V6K

C3 3

1

1

2

2

10U_ 0805_6. 3V6M

C5 9

1

1

2

2

12P _0402_5 0V8J

C1 322

1

1

@

2

2

47P _0402_50 V8J

C5 3

C5 4

1

1

@

2

2

330U _D2_2 .5VM_ R6M

1

1

C1 312

+

2

2

A A

B B

C C

+GF X_CORE

12P _0402_50 V8J

C1 325

C1 326

1

@

@

2

for RF

+GF X_CORE

12P _0402_5 0V8J

C1 319

C1 320

1

1

@

@

2

2

D D

+V CCP

47P _0402_50 V8J

C5 2

C5 1

1

1

@

@

2

2

Follow SCH check list

GRAPHI CS

PEG & DMI

POWER

+C PU_C ORE

1U_0 402_6 .3V6K

C3 81

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 44

C6 46

1

1

2

2

SENSE

LINES

GRA PHI CS VIDs

DDR3 - 1.5V RAILS

1U_0 402_6 .3V6K

C3 82

1

2

1U_0 402_6 .3V6K

C6 47

1

2

VAXG_SENSE

VSSAXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VTT0_DDR
VTT0_DDR[1]
VTT0_DDR[2]
VTT0_DDR[3]
VTT0_DDR[4]
VTT0_DDR[5]
VTT0_DDR[6]
VTT0_DDR[7]
VTT0_DDR[8]
VTT0_DDR[9]

VTT1_12
VTT1_13
VTT1_14
VTT1_15
VTT1_16
VTT1_17
VTT1_18
VTT1_19
VTT1_20
VTT1_21

1U_0 402_6 .3V6K

C5 33

1

1

2

2

1U_0 402_6 .3V6K

C6 49

1

2

2

AF12
AF10

AF71
AG67
AG70
AH71
AN71
AM67
AM70

AH69
AL71
AL69

BU40
BU35
BU28
BN38
BM25
BL30
BJ38
BH32
BH28
BG43
BF16
BF15
BD35
BD33
BD32
BD30
BD28
BD26
BD24
BD23
BD21
BD19
BD17
BD15
BB35
BB33
BB32
BB30
BB28
BB26
BB24
BB23
BB21
BB19
BB17
BB15

AW32
AW30
AW28
AW26
AW24
AW23
AW21
AW19
AW17
AW15

AD15
AD14
AD12
AB12
AA12
W17
W15
W14
W12
R15

1U_0 402_6 .3V6K

C5 34

1

2

1U_0 402_6 .3V6K

C6 50

1

2

2

1 2

R7 00 4.7K _0402 _5%

VCC _AXG_ SENSE
VSS_A XG_SENS E

GFX VR_V ID_0 <39>
GFX VR_V ID_1 <39>
GFX VR_V ID_2 <39>
GFX VR_V ID_3 <39>
GFX VR_V ID_4 <39>
GFX VR_V ID_5 <39>
GFX VR_V ID_6 <39>

R7 05 4.7K _0402 _5%@

1 2

GFX VR_EN < 39>

GFX _DPR SLPVR

R1 478 0_ 0402_5%

1U_0 402_6 .3V6K

C2 0

1

2

330U _B2_ 2.5VM_R15M

C2 5

1

+

@

2

1U_0 402_6 .3V6K

C4 2

1

2

10U_ 0805_ 6.3V6M

C4 6

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C3 83

C6 13

1

1

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 52

C6 48

1

1

2

2

12

1U_0 402_6 .3V6K

C2 1

1

2

22U_ 0805_ 6.3V6M

C2 6

1

2

+VT T_DDR

1U_0 402_6 .3V6K

C4 3

10U_ 0805_ 6.3V6M

C4 7

1U_0 402_6 .3V6K

C6 14

1U_0 402_6 .3V6K

C6 53

1

2

GFX VR_E N

VCC _AXG_S ENSE <39>
VSS_A XG_SENS E <39>

+1.5 VS_C PU_V DDQ

1U_0 402_6 .3V6K

C2 2

1

1

2

2

22U_ 0805_ 6.3V6M

C2 7

1

2

1U_0 402_6 .3V6K

C4 4

1

1

2

2

10U_ 0805_ 6.3V6M

C4 8

1

1

2

2

1U_0 402_6 .3V6K

C6 12

1

1

2

2

1U_0 402_6 .3V6K

C6 51

1

1

2

2

+V CCP

12/05 HP

GFX VR_IMO N <39>

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C2 3

C2 4

1

2

+V CCP

12

L31
0_08 05_5%

+V CCP

10U_ 0805_ 6.3V6M

C4 9

1

2

1U_0 402_6 .3V6K

3

1 2

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53

J55

VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89

1U_0 402_6 .3V6K

1

1

C6 8

2

2

R1 483 4.7 K_04 02_5%@

1 2

R1 484 4. 7K_04 02_5% @

POWER

CPU CO RE SUP PLY

add 7p cs Cap s to f ollow Desig n guide add 7p cs Cap s to f ollow Desig n guide

1U_0 402_6 .3V6K

1

1

C6 9

1U_0 402_6 .3V6K

C7 1

C7 0

2

2

1U_0 402_6 .3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

GFX _DPR SLPVR

+C PU_C ORE

AF57
AF55
AF53
AF51
AF50
AF48
AF46
AF44
AF42
AF41
AD55
AD51
AD48
AD44
AD41
AB55
AB51
AB48
AB44
AB41
AA55
AA51
AA48
AA44
AA41

W55
W51
W48
W44
W41

U55
U51
U48
U44
U41
R55
R51
R48
R44
R41
P60
N55
N51
N48
N44

N42
M60
M51
M44

L55

K60

K51

K44

H60

H51

H44
G60
G55
G51
G44

F55

E60

E57

E53

E50

E46

E42

D59

D57

D55

D54

D52

D50

D48

D47

D45

D43

B60

B56

B53

B49

B46

B42

A57

A54

A50

A47

A43

+VCA P0 +VCA P1

+V CCP

VCAP0_1
VCAP0_2
VCAP0_3
VCAP0_4
VCAP0_5
VCAP0_6
VCAP0_7
VCAP0_8

VCAP0_9
VCAP0_10
VCAP0_11
VCAP0_12
VCAP0_13
VCAP0_14
VCAP0_15
VCAP0_16
VCAP0_17
VCAP0_18
VCAP0_19
VCAP0_20
VCAP0_21
VCAP0_22
VCAP0_23
VCAP0_24
VCAP0_25
VCAP0_26
VCAP0_27

VCAP1_1

VCAP1_2

VCAP1_3

VCAP1_4

VCAP1_5

VCAP1_6

VCAP1_7

VCAP1_8

VCAP1_9
VCAP1_10
VCAP1_11
VCAP1_12
VCAP1_13
VCAP1_14
VCAP1_15
VCAP1_16
VCAP1_17
VCAP1_18
VCAP1_19
VCAP1_20
VCAP1_21
VCAP1_22
VCAP1_23
VCAP1_24
VCAP1_25
VCAP1_26
VCAP1_27

INT EL_A UBURN DALE _1288

1U_0 402_6 .3V6K

1

1

1

C7 2

C9 3

C1 14

2

2

1U_0 402_6 .3V6K

2

U1H

+VC AP0

BD55
BD51
BD48
BB55
BB51
BB48
AY57
AY53
AY50
AW57
AW53
AW50
AU55
AU51
AU48
AR55
AR51
AR48

PR OC_DP RSLP VR<37>

AN57
AN53
AN50
AL57
AL53
AL50
AK57
AK53
AK50

+VC AP1

BD44
BD41
BD37
BB44
BB41
BB37
AY46
AY42
AY39
AW46
AW42
AW39
AU44
AU41
AU37
AR44
AR41
AR37
AN46
AN42
AN39
AL46
AL42
AL39
AK46
AK42
AK39

1U_0 402_6 .3V6K

1

1

C1 13

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

C9 4

2

2008/09/15 2009/09/03

T135
PA D

VCC SENS E<37>
VSS SENSE<3 7>

R1 481 0_ 0402_5%

Close to CPU

VCC SENS E

VSS SENSE

+1.5 VS_C PU_V DDQ

1U_0 402_6 .3V6K

1

1

C9 2

C1 40

2

2

1U_0 402_6 .3V6K

Compal Secret Data

Deciphered Date

VTT_S ENSE<34>

12

1 2

R7 5 1 00_04 02_1%

1 2

R7 6 1 00_04 02_1%

+1.8V S

0_08 05_5%

1U_0 402_6 .3V6K

C1 15

1U_0 402_6 .3V6K

4

H_ VID [0..6 ]<37>

0_04 02_5%

IMV P_IMON< 37>

VCC SENS E
VSS SENSE

L32

4

PSI #<37>

R7 2

C6 3

H_ VID 0
H_ VID 1
H_ VID 2
H_ VID 3
H_ VID 4
H_ VID 5
H_ VID 6

H_V TTVID 1

PM_ DPRS LPVR _R

12

0_04 02_5%

R7 3

R7 4 0 _0402 _5%

VSS_S ENSE_VT T

+C PU_C ORE

22U_ 0805_ 6.3V6M

1

1

C3 74.7U _0603 _6.3V6K

C3 8

2

2

+V DDQ_ CK

12

1

C5 0

2

1U_0 402_6 .3V6K

1

1

C6 4

2

2

1U_0 402_6 .3V6K

F68

A61
D61
D62
A62
B63
D64
D66

AN1

F66

A41

F64

12

F63

12

N13

R12

W39
W37

U37
R39
R37

BB14
BB12

1

C6 5

2

U1 F

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT[1]

PROC_DPRSLPVR

ISENSE

VCC_SENSE
VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

VCCPLL1
VCCPLL2
VCCPLL3
VCCPLL4
VCCPLL5

VDDQ_CK[1]
VDDQ_CK[2]

INT EL_A UBURN DALE _1288

VTT0_72
VTT0_73

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C6 6

C6 7

2

2

1U_0 402_6 .3V6K

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

SENSE LINESCPU VI DS

1.1V R AIL PO WER

1.8V

POWER

R7 7 0_040 2_5%

1 2

R7 8 0_040 2_5%

1 2

1U_0 402_6 .3V6K

1

1

2

1

1

C8 9

C8 6

1U_0 402_6 .3V6K

2

C8 8

2

2

1U_0 402_6 .3V6K

Compal Electronics, Inc.

Auburndale(4/5)-PWR

LA -6 161 P

5

VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_43
VTT0_44
VTT0_45
VTT0_46
VTT0_47
VTT0_48
VTT0_49
VTT0_50
VTT0_51
VTT0_52
VTT0_53
VTT0_54
VTT0_55
VTT0_56
VTT0_57
VTT0_58
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT0_63
VTT0_64
VTT0_65
VTT0_66
VTT0_67
VTT0_68
VTT0_69
VTT0_70
VTT0_71
VTT0_72
VTT0_73

1U_0 402_6 .3V6K

1

C8 7

2

5

+V CCP

AW14
AW12
AU60
AU59
AU12
AR60
AR59
AR12
AN60
AN59
AN35
AN33
AN17
AN15
AN14
AN12
AM10
AL60
AL59
AL17
AL15
AL14
AL12
AK35
AK33
AF39
AF37
AF35
AF33
AF32
AF30
AD39
BF60
BF59
BD60
BD59
BB60
BB59
AY60
AW60
AW35
AW33
AD37
AD35
AD33
AD32
AD30
W35
W33
W32
W30
W28
W26
W24
W23
U35
U33
U32
U30
U28
U26
U24
U23
R35
R33
R32
R30
R28
R26
R24
R23

VTT0_72

AY10

VTT0_73

AN9

+VC CP

1

C8 5

C9 1

2

1U_0 402_6 .3V6K

7 4 1Tues day, May 18, 2010

1U_0 402_6 .3V6K

1

C9 0

2

0. 5

1

2

3

4

5

U1 I

BU62

VSS1

BU58

VSS2

BU55

VSS3

BU51

VSS4

BU48

VSS5

BU44

VSS6

BU37

VSS7

BU32

A A

B B

C C

D D

VSS8

BU25

VSS9

BU21

VSS10

BU18

VSS11

BU14

VSS12

BU11

VSS13

BU7

VSS14

BP42

VSS15

BN64

VSS16

BN6

VSS17

BM70

VSS18

BM51

VSS19

BM44

VSS20

BM32

VSS21

BM24

VSS22

BM17

VSS23

BL57

VSS24

BL55

VSS25

BL48

VSS26

BL40

VSS27

BL28

VSS28

BL20

VSS29

BK63

VSS30

BK60

VSS31

BK53

VSS32

BK34

VSS33

BK10

VSS34

BJ64

VSS35

BJ21

VSS36

BJ9

VSS37

BJ1

VSS38

BH70

VSS39

BH57

VSS40

BH55

VSS41

BH47

VSS42

BH24

VSS43

BH20

VSS44

BH15

VSS45

BG51

VSS46

BG36

VSS47

BF62

VSS48

BF30

VSS49

BF13

VSS50

BF8

VSS51

BE70

VSS52

BE65

VSS53

BE9

VSS54

BE1

VSS55

BD57

VSS56

BD53

VSS57

BD50

VSS58

BD46

VSS59

BD42

VSS60

BD39

VSS61

BD14

VSS62

BB71

VSS63

BB62

VSS64

BB57

VSS65

BB53

VSS66

BB50

VSS67

BB46

VSS68

BB42

VSS69

BB39

VSS70

BB7

VSS71

BB1

VSS72

BA70

VSS73

AY71

VSS74

AY66

VSS75

AY62

VSS76

AY59

VSS77

AY55

VSS78

AY51

VSS79

AY48

VSS80

AR42

VSS140

AR39

VSS141

AR35

VSS142

AR33

VSS143

AR32

VSS144

AR30

VSS145

AR28

VSS146

AR26

VSS147

AR24

VSS148

AR23

VSS149

AR21

VSS150

AR19

VSS151

AR17

VSS152

AR15

VSS153

AR14

VSS154

AR4

VSS155

AR1

VSS156

AP70

VSS157

AP64

VSS158

AN62

VSS159

AN55

VSS160

AY44

VSS81

AY41

VSS82

AY37

VSS83

AY35

VSS84

AY33

VSS85

AY32

VSS86

AY30

VSS87

AY28

VSS88

AY26

VSS89

INT EL_A UBURN DALE _1288

VSS

1

VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220

AY24
AY23
AY21
AY19
AY17
AY15
AY14
AY12
AY8
AY4
AW67
AW62
AW59
AW55
AW51
AW48
AW44
AW41
AW37
AV9
AV1
AU70
AU62
AU57
AU53
AU50
AU46
AU42
AU39
AU35
AU33
AU32
AU30
AU28
AU26
AU24
AU23
AU21
AU19
AU17
AU15
AU14
AU4
AT64
AT10
AR62
AR57
AR53
AR50
AR46
AN51
AN48
AN44
AN41
AN37
AN5
AN4
AM64
AM8
AL62
AL55
AL51
AL48
AL44
AL41
AL37
AL35
AL33
AL1
AK70
AK64
AK55
AK51
AK48
AK44
AK41
AK37
AK32
AK30
AK28
AK26
AK24
AK23
AK21
AK19
AK17
AK15
AJ70
AH62
AH57
AH55
BV66
BV64
BT68
BR69
BR68
BR3
BN71
BN1
BL71
BL1
R14
H71
F71
E69
E68
A66
A64
E5
C68

U1J

AH53

VSS202

AH51

VSS203

AH50

VSS204

AH48

VSS205

AH46

VSS206

AH44

VSS207

AH42

VSS208

AH41

VSS209

AH39

VSS210

AH37

VSS211

AH35

VSS212

AH33

VSS213

AH32

VSS214

AH30

VSS215

AH28

VSS216

AH26

VSS217

AH24

VSS218

AH23

VSS219

AH21

VSS220

AH19

VSS221

AH17

VSS222

AH15

VSS223

AH4

VSS224

AG64

VSS225

AG9

VSS226

AG6

VSS227

AF69

VSS228

AF62

VSS229

AF1

VSS230

AE70

VSS231

AE64

VSS232

AD62

VSS233

AD57

VSS234

AD53

VSS235

AD50

VSS236

AD46

VSS237

AD42

VSS238

AD4

VSS239

AC67

VSS240

AC64

VSS241

AC10

VSS242

AC5

VSS243

AC1

VSS244

AB70

VSS245

AB62

VSS246

AB57

VSS247

AB53

VSS248

AB50

VSS249

AB46

VSS250

AB42

VSS251

AB39

VSS252

AB37

VSS253

AB35

VSS254

AB33

VSS255

AB32

VSS256

AB30

VSS257

AB28

VSS258

AB26

VSS259

AB24

VSS260

AB23

VSS261

AB21

VSS262

AB19

VSS263

AB17

VSS264

AB15

VSS265

AB14

VSS266

AB9

VSS267

AA66

VSS268

AA64

VSS269

AA62

VSS270

AA57

VSS271

AA53

VSS272

AA50

VSS273

AA46

VSS274

AA42

VSS275

AA39

VSS276

AA37

VSS277

AA35

VSS278

AA33

VSS279

AA32

VSS280

AA30

VSS281

AA28

VSS282

AA26

VSS283

AA24

VSS284

AA23

VSS285

AA21

VSS286

AA19

VSS287

F20

VSS374

F4

VSS375

E37

VSS376

E33

VSS377

E30

VSS378

E16

VSS379

E12

VSS380

D41

VSS381

D38

VSS382

D34

VSS383

D31

VSS384

D27

VSS385

D24

VSS386

D20

VSS387

D17

VSS388

D13

VSS389

D10

VSS390

D6

VSS391

B65

VSS392

B40

VSS415

INT EL_A UBURN DALE _1288

VSS

2

VSS404
VSS405
VSS406
VSS407
VSS408
VSS409
VSS410
VSS411
VSS412
VSS413
VSS393
VSS394
VSS395
VSS396
VSS397
VSS398
VSS399
VSS400
VSS401
VSS402
VSS403
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
VSS361
VSS362
VSS363
VSS364
VSS365
VSS366
VSS367
VSS368
VSS369
VSS370
VSS371
VSS372
VSS373

A40
A36
A33
A29
A26
A22
A19
A15
A12
A8
B62
B58
B55
B51
B48
B44
A59
A55
A52
A48
A45
AA17
AA15
AA14
AA4
W69
W62
W57
W53
W50
W46
W42
W6
W1
V70
U64
U62
U57
U53
U50
U46
U42
U39
U9
U4
T1
R70
R62
R57
R53
R50
R46
R42
R5
P4
N63
N57
N53
N50
N46
N30
N21
N15
M53
M42
M36
M1
L70
L57
L48
L47
L13
K64
K53
K43
K36
K34
K32
K25
K17
K11
K6
K4
J65
J57
J48
J47
J40
J9
H53
H43
H36
H1
G70
G57
G53
G48
G47
G43
G30
G24
G20
G15
F61
F48
F47
F28

+V CCP

1U_0 402_6 .3V6K

Add to f ollow de sign guide

1U_0 402_6 .3V6K

1

2

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C1 89

C1 42

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C3 03

C3 04

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C5 10

C5 09

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C6 18

C6 19

2

2

1U_0 402_6 .3V6K

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1U_0 402_6 .3V6K

1

C1 91

C1 41

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

C3 02

C1 92

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C3 07

C5 08

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C5 15

2

2

Issued Date

1U_0 402_6 .3V6K

1

1

C1 90

2

2

1U_0 402_6 .3V6K

1

1

C3 06

2

2

1U_0 402_6 .3V6K

1

C5 12

2

1

C6 36

C5 13

2

1U_0 402_6 .3V6K

CPU CORE

+C PU_C ORE

22U_ 0805_6. 3V6M

C2 01

C3 05

1

C5 11

2

1U_0 402_6 .3V6K

1

C6 28

2

22U_ 0805_6. 3V6M

C7 3

1

1

2

2

Inside cavity

330U _D2_2 .5VM_R6 M

C9 5

1

1

+

+

2

2

22U_ 0805_6. 3V6M

22U_ 0805_6. 3V6M

C1 01

1

1

2

2

C7 4

UL V@

330U _D2_2 .5VM_R6 M

C9 6

UL V@

C1 02

1

UL V@

2

BGA Ball Cracking Prevention and Detection

+3VS

12

VSS _NCT F1_R<5>

+3VS +3VS

12

VSS _NCT F6_R<5> VSS _NCT F7_R<5>

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

4

22U_ 0805_6. 3V6M

C7 5

1

2

330U _D2_2 .5VM_R6 M

C9 7

1

+

2

22U_ 0805_6. 3V6M

22U_ 0805_6. 3V6M

C1 03

C1 04

1

2

Under cavity

R8 0

CRA CK_B GA

100K _0402_5 %

3

Q3B

5

2N70 02DW -T/R7 _SOT363-6

4

CRA CK_B GA

R8 1
100K _0402_5 %

61

Q4A
2N70 02DW -T/R7 _SOT363-6

2

22U_ 0805_6. 3V6M

C7 6

1

1

2

2

330U _D2_2 .5VM_R6 M

C9 8

1

+

2

Under cavity

22U_ 0805_6. 3V6M

C1 05

1

2

22U_ 0805_6. 3V6M

22U_ 0805_6. 3V6M

C7 7

22U_ 0805_6. 3V6M

1

2

VSS _NCT F2_R<5>

22U_ 0805_6. 3V6M

C7 8

C7 9

1

1

2

2

22U_ 0805_6. 3V6M

C1 06

UL V@

Cu stom

22U_ 0805_6. 3V6M

C1 07

1

1

2

2

Title

Size D ocum ent N umber Re v

Da te: She et

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

LA -6 161 P

1

2

C1 08

+3VS

22U_ 0805_6. 3V6M

C8 0

1

2

12

R7 9
100K _0402_5 %

12

R8 2
100K _0402_5 %

22U_ 0805_6. 3V6M

C8 1

1

2

22U_ 0805_6. 3V6M

C1 09

1

2

61

2

CRA CK_B GA

3

5

4

5

22U_ 0805_6. 3V6M

C8 2

1

UL V@

2

22U_ 0805_6. 3V6M

C1 10

Q3A
2N70 02DW -T/R7 _SOT363-6

Q4B
2N70 02DW -T/R7 _SOT363-6

22U_ 0805_6. 3V6M

22U_ 0805_6. 3V6M

C8 3

1

2

C8 4

1

UL V@

UL V@

2

CRA CK_B GA <16, 28>

o f

8 4 1Tues day, May 18, 2010

0. 5

1

2

3

4

5

DDR3 SO-DIMM A

+V _DD R_CP U_REF

0.1U _0402 _16V4Z

2.2U _0805 _16V4Z

C1 11

1

2

A A

B B

C C

D D

C1 12

1

2

DDR_ CKE0 _DIM MA<6>

DD R_A_B S2<6>

M_ CLK_ DDR0<6>
M_ CLK_D DR#0<6>

DD R_A_B S0<6>

DD R_A _WE#<6>
DD R_A_ CAS#<6>

DDR_ CS1_ DIMM A#<6>

+3VS

1

2

1

2.2U _0402 _6.3V6M
C1 36

1

2

1 2

10K _0402_5%

0.1U _0402 _16V4Z
C1 37

DD R_A _D2
DD R_A _D5

DD R_A_ DM0

DD R_A _D6
DD R_A _D7

DD R_A _D9
DD R_A _D11

DD R_A_ DQS# 1
DD R_A _DQS 1

DD R_A _D8
DD R_A _D10

DD R_A _D17
DD R_A _D20

DD R_A_ DQS# 2
DD R_A _DQS 2

DD R_A _D16
DD R_A _D23

DD R_A _D24
DD R_A _D31

DD R_A_ DM3

DD R_A _D26
DD R_A _D27

DDR_ CKE0 _DIM MA

DD R_A_ BS2

DDR_ A_MA 12
DDR_ A_M A9

DDR_ A_M A8
DDR_ A_M A5

DDR_ A_M A3
DDR_ A_M A1

M _CLK_ DDR0
M _CLK_ DDR#0

DDR_ A_MA 10
DD R_A_ BS0

DD R_A _WE#
DD R_A_ CAS#

DDR_ A_MA 13
DDR_ CS1_ DIMM A#

DD R_A _D32
DD R_A _D33

DD R_A_ DQS# 4
DD R_A _DQS 4

DD R_A _D34
DD R_A _D35

DD R_A _D44
DD R_A _D45

DD R_A_ DM5

DD R_A _D42
DD R_A _D43

DD R_A _D50
DD R_A _D49

DD R_A_ DQS# 6
DD R_A _DQS 6

DD R_A _D54
DD R_A _D51

DD R_A _D56
DD R_A _D61

DD R_A_ DM7

DD R_A _D62
DD R_A _D58

+1.5 V + 1.5V

3A @

3A @ 1. 5 V

3A @3A @

JDI MM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

R9 5

1 2

10K _0402_5%

R9 6

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX _AS0 A626-U4 SN-7F~D

CO NN@

1. 5 V

1. 5 V1. 5 V

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

BOSS1
BOSS2

2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

A2
A0

VDD

CK1

VDD

BA1

VDD

S0#

VDD

NC

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA

SCL
VTT

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DD R_A _D0
DD R_A _D1

DD R_A_ DQS# 0
DD R_A _DQS 0

DD R_A _D4
DD R_A _D3

DD R_A _D12
DD R_A _D13

DD R_A_ DM1
DRA MRST#

DD R_A _D14
DD R_A _D15

DD R_A _D19
DD R_A _D21

DD R_A_ DM2

DD R_A _D22
DD R_A _D18

DD R_A _D25
DD R_A _D28

DD R_A_ DQS# 3
DD R_A _DQS 3

DD R_A _D29
DD R_A _D30

DDR_ CKE1 _DIM MA

DDR_ A_MA 15
DDR_ A_MA 14

DDR_A_MA 11
DDR_ A_M A7

DDR_A_MA6
DDR_ A_M A4

DDR_ A_M A2
DDR_ A_M A0

M _CLK_ DDR1
M _CLK_ DDR#1

DD R_A_ BS1
DD R_A_ RAS#

DDR_ CS0_ DIMM A#
M_OD T0

M_OD T1

DD R_A _D36
DD R_A _D38

DD R_A_ DM4

DD R_A _D37
DD R_A _D39

DD R_A _D41
DD R_A _D40

DD R_A_ DQS# 5
DD R_A _DQS 5

DD R_A _D46
DD R_A _D47

DD R_A _D55
DD R_A _D53

DD R_A_ DM6

DD R_A _D52
DD R_A _D48

DD R_A _D60
DD R_A _D57

DD R_A_ DQS# 7
DD R_A _DQS 7

DD R_A _D59
DD R_A _D63

PM_EX TTS#1_R
SMB _DATA_S3
SMB _CLK_S 3

0.

0. 65 A @0 . 75 V

65 A @0 . 75 V

0.0.

65 A @0 . 75 V6 5 A@ 0 .7 5 V

2

+0.7 5VS

DRA MRST# < 4>

DDR_ CKE1 _DIMM A <6>

M_ CLK_D DR1 <6>
M_C LK_DD R#1 <6>

DDR_ A_BS 1 <6>
DD R_A_ RAS# <6>

DDR_ CS0_ DIMM A# <6>
M_ODT 0 <6>

M_ODT 1 <6>

2.2U _0805 _16V4Z

0.1U _0402 _16V4Z
C1 17

C1 16

1

1

2

2

PM_EX TTS#1_R <4>
SMB_D ATA_S3 < 10,12, 22>
SMB _CLK_S3 < 10,12, 22>

DD R_A _D[0 ..63]<6>

DD R_A_ DM[0 ..7]<6>

DD R_A _DQS [0..7 ]<6>

DD R_A _DQS #[0.. 7]<6>

DDR_ A_MA [0.. 15]<6>

R9 4 0_040 2_5%

1 2

+V _DD R_CP U_REF+VR EF_C A

SMB _DATA_S3

SMB _CLK_S 3

+1.5 V

12

R8 3

1K_ 0402_1%

+V _D DR_CP U_RE F

12

R8 6

1K_ 0402_1%

+3VS

@

@

R1 495
10K _0402_5%

U5 9

@

1 2

1

SDA

2

SCL

3

T_CRIT_A

4

GND

NS_LM7 7CIMMX_3_ MSOP8P

reserv e for memory thermal sensor, HP.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

8

+VS

7

A0

6

A1

5

INT

2008/09/15 2009/09/03

0.1U _0402 _16V4Z

1

2

PM_EX TTS#1_R

+3VS

C1 338

@

0_04 02_5%

1 2

@

0_04 02_5%

1 2

Compal Secret Data

Deciphered Date

4

R1 496

R1 497

open

Lay ou t N ote:
Pl ace near JDI MM1

+1.5V

10U_ 0603_6. 3V6M

10U_ 0603_6. 3V6M

C1 21

1

2

C1 22

1

2

Lay ou t N ote:
Pl ace near JDI MB1

1

2

Title

Size D ocum ent N umber R ev

Cu sto m

LA -61 61P

Da te: She et o f

10U_ 0603_6. 3V6M

10U_ 0603_6. 3V6M

C1 24

C1 23

1

1

2

2

+0.7 5VS

10U_ 0603_6. 3V6M

10U_ 0603_6. 3V6M

C1 31

1U_0 402_6 .3V6K

C1 315

C1 314

1

1

2

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

10U_ 0603_6. 3V6M

10U_ 0603_6. 3V6M

C1 25

1

1

2

2

C1 33

C1 32

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

2

2

5

330U _B2_ 2.5VM_R15M

C1 18

C1 26

1

+

2

C1 34

1U_0 402_6 .3V6K

C1 35

10U_ 0805_6. 3V6M

1

1

2

2

9 4 1Tuesday, May 18, 2010

0. 5

1

A A

2

3

4

5

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0#

VSS_CPU

CPU_1#

VDD_SRC

0.1U _0402 _16V4Z
C1 67

+3V S_CK505

SMB _CLK_S 3
SMB _DATA_S3
RE F_0/ CPU_S EL

CLK _XTAL_IN
CLK_ XTAL_OUT

CK _P WRGD

R_ CLK_ BUF_B CLK CLK _BUF _BCL K
R_CL K_BU F_BC LK#

+3V S_CK505 _G +3VS +1.5V S

1 2

R1 43 0_06 03_5%@

1 2

R1 20 0_06 03_5%

10U_ 0805_ 10V4Z

0.1U _0402 _16V4Z
C1 64

C1 69

1

2

CPU_0

CPU_1

1

2

32

SCL

31

SDA

30
29
28
27
26
25

24
23
22
21
20
19
18
17

0.1U _0402 _16V4Z
C1 68

1

2

R1 07 33_0 402_5%

R1 10 0_04 02_5%
R1 12 0_04 02_5%

+1.0 5VS_ CK505
+3V S_CK50 5_G

instal l R12 0 for low power CLKGENEMI re quest , Compal SI, 1/19

1 2

1 2
1 2

1

C1 63

2

CLK _14M_ PCH

10P _0402 _50V8C@

CLK _BUF_ BCL K#

SMB _CLK_S3 < 9,12,2 2>
SMB_D ATA_S3 < 9,12,2 2>
CLK _14M_ PCH <12>

CLK _BUF_ BCLK < 12>
CLK _BUF_ BCLK # <12>

CK _P WRGD

33P _0402_50 V8J

C1 77

2

1

1 2

10K _0402_5%

61

Y114.3 18MH Z 16P F 7A 14300083

R1 15

+3V S_CK505

Q7A

2

2N70 02DW -7-F_S OT363-6

CLK_ XTAL_OUT

CLK _XTAL_IN

12

2

C1 78

33P _0402_50 V8J

1

CL K_EN# < 37>

+3V S_CK505 _G

CLK _BUF_ DOT96<12>
CLK _BUF_ DOT96 #<12>

CL K_BU F_CK SSCD< 12>
CL K_BU F_CK SSCD #<12>

CLK _DMI<12>
CLK _DMI#<12>

B B

CLK _BUF_ DOT96
CLK _BUF_ DOT 96#

CL K_B UF_CK SSCD
CL K_B UF_CK SSCD #

CLK _DMI
CLK _DMI#

CPU_1PIN 30 CPU_0

(De faul t)

0 133MHz

1

+1.0 5VS_ CK505+1.05VS

1 2

R1 18 0_06 03_5%

C C

1

2

133MHz

100MHz 100MHz

Close to U6

10U_ 0805_ 10V4Z

10U_ 0805_ 10V4Z

0.1U _0402 _16V4Z

C1 72

C1 71

C1 73

1

1

2

2

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

C1 74

C1 75

1

1

1

2

2

2

+1.05 VS

R1 465 10 K_0402_ 5%@

R1 466 10 K_0402_ 5%

CPU _STOP #

47P _0402_5 0V8J

C1 76

R1 06 0_04 02_5%

1 2

R1 08 0_04 02_5%

1 2

+3V S_CK505

R1 09 0_04 02_5%

1 2

R1 11 0_04 02_5%

1 2

R1 13 0_04 02_5%

1 2

R1 14 0_04 02_5%

1 2

+1.0 5VS_ CK505

1 2

1 2

1 2

10K _0402_5%

R1 16

L_CL K_BU F_DO T96
L_CL K_BU F_DO T96#

L_ CLK_ BUF_C KSS CD

L_CL K_BU F_CK SSCD #

L_CL K_DM I
L_CL K_DM I#

CPU _STOP #

RE F_0/ CPU_S EL

+3V S_CK505

FBM A-L11- 160808-301L MA20T_0603 ~D

U6

1

VDD_DOT

2

VSS_DOT

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

VSS_27

9

VSS_SATA

10

SRC_1/SATA

11

SRC_1#/SATA#

12

VSS_SRC

13

SRC_2

14

SRC_2#

15

VDD_SRC_IO

16

CPU_STOP#

SLG 8LV59 5VTR_QFN _32P_5X5

2nd So urce :
IDT IC S9LVS3 197BKL FT MLF 32P
REALTE K RTM8 90N-63 2-VB-G RT QFN 32P

+3VS

+3V S_CK505

R1 17

1 2

TGND

33

0.1U _0402 _16V4Z

47P _0402_5 0V8J

C1 65

C1 70

1

1

2

1

2

2

REF_0/CPU_SEL

CKPWRGD/PD#

0.1U _0402 _16V4Z
C1 66

1

2

VDD_CPU_IO

Close to U6

Close to U2 within 500mil

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Da te: She et o f

Compal Electronics, Inc.

CLOCK GENERATOR

LA -61 61P

5

10 41T uesd ay, M ay 1 8, 20 10

0. 5

1

PCH _RTCX 1

1 2

R1 23 10M _0402_5%

18P _0402_5 0V8J

1

1

C1 81

1 2

1 2

Y2

OSC4OSC

NC3NC

2

HDA _BIT _CLK_ CODE C

HD A_S DOUT _CODE C

A A

2

@

C1 86 47P _0402_5 0V8J

@

C1 88 47P _0402_5 0V8J

for RF

B B

C C

1 2

R1 76 51_0 402_5%

PCH _RTCX 2

32.7 68KH Z_12. 5PF_ Q13MC14 610002

1

C1 82
18P _0402_5 0V8J

2

for i- AMT setting. 11/20 HP

PCH _JTA G_TCK

+R TCVC C

HDA _BIT _CLK_ CODE C<23>

HD A_S YNC _CO DEC< 23>

SB_ SPKR<23>

HD A_RS T#_CO DEC<23>

HD A_S DIN0<23>

HD A_S DOUT_ CODE C<23>

1U_0 603_1 0V4Z

1 2

R1 26 20K_0 402_1%

1 2

R1 27 20K_0 402_1%

1U_0 603_1 0V4Z

KBC _SPI _CS0#_ R<28>

KBC _SPI _CS1#_ R<28>

R1 58

@

200_ 0402_5%

1 2

PCH _JTA G_TDI

12

R1 67

@

100_ 0402_1%

C1 80

1

12

2

1

12

C1 83

2

R1 30 33_0 402_5%

1 2

R1 32 33_0 402_5%

1 2

R1 34 33_0 402_5%

1 2

R1 37 33_0 402_5%

1 2

+3V ALW

11/20 HP

KBC _SPI _CLK_R<28>

KBC _SPI _SI_R<28>

+R TCVC C +3VS

CL RP1

SHO RT P ADS@

CL RP2

SHO RT P ADS@

1 2

R1 457 1K_ 0402_5%
R1 461 10 0K_0 402_5%

1 2

T147P AD

T148P AD

T149P AD

T150P AD

T121P AD

1 2

R1 44 0_04 02_5%

1 2

R1 48 0_04 02_5%

KBC _SPI _SO<28>

12

R1 57

200_ 0402_5%@

PCH _JTA G_TDO

12

R1 66

100_ 0402_1%@

Pre -Pr od uctio n Uni ts Pr odu ction

Ref .PCH Pin

ES1 AllES 2

R15 7

PCH _JT AG_TD O

D D

PCH _JT AG_TD I

PCH _JT AG_TM S

PCH _JT AG_TC K

1

R16 6

R15 8

R16 7

R15 6

R16 5

R17 6

Uns tuff

Uns tuff

200 ohm

100 ohm

200 ohm

51 ohm 5%

200 ohm

100 ohm

200 ohm

100 ohm

200 ohm

100 ohm

Uns tuff

Uns tuff

Uns tuff

Uns tuff

Uns tuff

Uns tuff100 ohm

51 ohm 5%51 ohm 5%

2

1 2

R1 21 1M_ 0402_5%

1 2

R1 24 330 K_0402_ 5%

PCH _RTCX 1
PCH _RTCX 2

PCH _RTCR ST#

PCH _SRT CRST#

S M_INT RUDE R#

PCH _INTV RME N

HDA _BIT _CLK

HD A_S YNC

SB_ SPKR

HDA _RST #

HD A_S DIN0

HD A_SD OUT

PCH _GPI O33AQU AWHI TE_BA TLED

PCH _JTA G_TCK

PCH _JTAG_T MS

PCH _JTA G_TDI

PCH _JTA G_TDO

KBC _SPI _CS0#

KBC _SPI _CS1#

+3V ALW+3 VALW+3V ALW

12

@

12

@

2

B13
D13

C14

D17

A16

A14

A30

D29

P1

C30

G30

F30

E32

F32

B29

H32

J30

M3

K3

K1

J2

J4

BA2

AV3

AY3

AY1

AV1

R1 56

200_ 0402_5%

PCH _JTAG_T MS

R1 65

100_ 0402_1%

RTCX1
RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_RST#

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

IBE XPEAK- M_FCBGA1 071

S M_INT RUDE R# SI RQ

U7 A

R1 22 10K_ 0402_5%

1 2

R1 25 10K_ 0402_5%@

RT CIH DA

SPI JTAG

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LP C

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SA TA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

12

LDRQ0#

SERIRQ

D33
B33
C32
A32

C34

A34
F34

AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

AF15

T3

Y9

V1

3

SB_ SPKRPCH _INTV RME N

R1 460 10 K_0402 _5%

GPI O23

SI RQ

SATA_ PRX_DTX_N0
SATA_ PRX_DTX_P0
SATA_ PTX_DRX_N0
SATA_ PTX_DRX_P0

SAT AICOMP IPCH _TRST #

R1 45 10K_ 0402_5%

1 2

GPI O21

HD D_HA LTLE D

3

12

1 2

R1 42 37.4 _0402_1 %

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LPC _LAD0 < 27,28>
LPC _LAD1 < 27,28>
LPC _LAD2 < 27,28>
LPC _LAD3 < 27,28>

LPC _LFRA ME# <27 ,28>

+3VS

SI RQ <27 ,28>

SATA_ PRX_DTX_N0 <19>
SATA_ PRX_DTX_P0 <1 9>
SATA_ PTX_DRX_N0 <19>
SATA_ PTX_DRX_P0 <1 9>

+1.0 5VS

+3VS

SAT A_LED# <2 0>

HD D_HA LTLED < 20>

4

11/20 HP

+R TCVC C +VR EG_511 25

R2 34 0_04 02_5%

1 2

1

C2 10

1U_0 603_1 0V4Z

2

+3VS

R1 47
10K _0402_5%

1 2

GPI O21

iAMT setting

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

4

D3 6

1

CHN2 02UP T_SC -70

AQU AWHI TE_BA TLED#<25,28>

5

JBATT1

3

2

R2 61
1K_ 0402_5%

RT C1 RT C2

1 2

W=2 0mi ls

L

for i- AMT setting. 11/20 HP

R1 459

330K _0402_5 % @

1 2

2

+ -

+3VS

R1 458

@

10K _0402_5%

1 2

AQU AWHI TE_BA TLED

61

Q86A
2N70 02DW H 2N SOT3 63-6

1

+

LOTES _AAA-BA T-019-K01 _2P

CO NN@

GPIO33 iAMT En able /Disable

Hi

Enable (Defau lt)

DisableLo

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

LA -61 61P

5

11 41T uesd ay, M ay 1 8, 20 10

2

-

0. 5

o f

1

A A

change from poert2 to port4. 11/20 HP

PCI E_PRX_D TX_N4<22>
PCIE _PRX_DTX _P4<22>

WLAN

GLAN

WWAN

B B

11/21 HP

12/05 HP

WWAN

C C

WLAN

PCI E_PT X_C_DRX_N 4<22>
PCI E_PTX _C_DRX_P4< 22>

PCI E_PRX_D TX_N6<21>
PCIE _PRX_DTX _P6<21>
PCI E_PT X_C_DRX_N 6<21>
PCI E_PTX _C_DRX_P6< 21>

PCI E_PRX_D TX_N7<22>
PCIE _PRX_DTX _P7<22>
PCI E_PT X_C_DRX_N 7<22>
PCI E_PTX _C_DRX_P7< 22>

+3VS

CLK _PCIE _MCA RD2#<22>
CLK _PCIE _MCA RD2<22>

CL KRE Q_WW AN#<22>

CLK _PCIE _MCA RD#<22>
CLK _PCIE _MCA RD<22>

CL KREQ _WLA N#< 22>

C1 93 0.1 U_040 2_16V4 Z

1 2

C1 94 0.1 U_040 2_16V4 Z

1 2

C1 97 0.1 U_040 2_16V4 Z

1 2

C1 98 0.1 U_040 2_16V4 Z

1 2

C1 301 0. 1U_04 02_16 V4Z

1 2

C1 302 0. 1U_04 02_16 V4Z

1 2

+3V ALW

R2 00 10K _0402_5%

R2 02 10K _0402_5%

+3VS

R2 05 10K_ 0402_5%

1 2

R1 479 0_ 0402_5%

1 2

R1 480 0_ 0402_5%

1 2

R2 08 0_04 02_5%

1 2

R2 09 0_04 02_5%

1 2

+3V ALW

+3V ALW

R2 13 10K _0402_5%

R7 01 10K _0402_5%

1 2

1 2

1 2

1 2

PCI E_PRX_ DTX_N4
PCI E_PRX_DT X_P4
PCI E_PTX _DRX_N4
PCI E_PTX_DR X_P4

PCI E_PRX_ DTX_N6
PCI E_PRX_DT X_P6
PCI E_PTX _DRX_N6
PCI E_PTX_DR X_P6

PCI E_PRX_ DTX_N7
PCI E_PRX_DT X_P7
PCI E_PTX _DRX_N7
PCI E_PTX_DR X_P7

CLK _PCIE _MCA RD2# _R
CLK _PCIE _MCA RD2_ R

CLK _PCIE _MCA RD#_ R
CL K_PC IE_M CARD _R

2

U7 B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBE XPEAK- M_FCBGA1 071

SMBus

PCI-E*

Link

Con trol ler

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From C LK BUF FER

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

B9

H14

C8

J14

C6

G8

M14

E10

G12

T13

T11

T9

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

AH51
AH53

AF38

T45

P43

T42

N50

LI D_S W_PC H#

SM BCLK

SMBDA TA

SML 0ALERT#

SML 0CLK

SML 0DATA

SML 1ALERT#

SML 1CLK

SML 1DATA

R1 462 10 K_04 02_5%

1 2

R_C LK_EXP#

R1 95 0_04 02_5%

R_C LK_EXP

R1 96 0_04 02_5%

R_ CLK_ DP#

R1 97 0_04 02_5%

R_ CLK_ DP

R1 98 0_04 02_5%

XTA L25_IN
XTAL25 _OUT

XCL K_RCOM P

R2 11 90.9 _0402_1 %

3

1 2
1 2

1 2
1 2

1 2

T55 PA D

T56 PA D

T139 PA D

T140 PA D

11/20 HP

CLK _DMI# < 10>
CLK _DMI <1 0>

CLK _BUF_ BCLK # <10>
CLK _BUF_ BCLK < 10>

CLK _BUF_ DOT96 # <10>
CLK _BUF_ DOT96 <10>

CL K_BU F_CK SSCD # < 10>
CL K_BU F_CK SSCD < 10>

CLK _14M_ PCH <10>

CL K_PCI _FB <1 4>

CLK_EX P# <4>
CLK_EX P <4>

CLK _DP# <4 >
CL K_DP <4>

+1.0 5VS

4

R1 83 10K _0402_5%

SMB _DATA_S3

SM BCLK

+3VS

SMBDA TA SMB _DATA_S3

1 2

R1 85 10K _0402_5%

1 2

Q8A

2N70 02DW -T/R7 _SOT363- 6

6 1

2

5

3

2N70 02DW -T/R7 _SOT363- 6

4

Q8B

SMB _CLK_S 3

Q2A

SML 1CLK

SML 1DATA

2N70 02DW -T/R7 _SOT363- 6

+3V ALW

4

2N70 02DW -T/R7 _SOT363-6

XTA L25_IN

XTAL25 _OUT

61

2

5

3

Q2B

R2 10 1M_0 402_5%

R2 63

1 2

0_04 02_5%

R2 64

1 2

0_04 02_5%

1 2

1 2

25MHZ_20PF_7A25000012

C1 99

1

18P _0402_50 V8J

2

5

+3V ALW

CAP _CLK

CAP _DAT

SM BCLKSMB _CLK_S 3

+3VS

SMBDA TA

SML 0CLK

SML 0DATA

SML 1CLK

SML 1DATA

SML 0ALERT#

SML 1ALERT#

LI D_S W_PC H#

SMB _CLK_S3 < 9,10,2 2>

SMB_ DATA_S3 < 9,10,2 2>

CAP _CLK <28 >

CAP _DAT <2 8>

Y3

C2 00

1

18P _0402_5 0V8J

2

1 2

R1 84 2.2K _0402_ 5%

1 2

R1 86 2.2K _0402_ 5%

1 2

R1 87 2.2K _0402_ 5%

1 2

R1 88 2.2K _0402_ 5%

1 2

R1 89 2.2K _0402_ 5%

1 2

R1 91 2.2K _0402_ 5%

R1 92 10K_ 0402_5%

1 2

R1 94 10K_ 0402_5%

1 2

R1 99 10K_ 0402_5%

1 2

+3VL

5.1K _0402 _5%

R6 95

1 2

R6 94

1 2

5.1K _0402 _5%

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

LA -61 61P

5

12 41T uesd ay, M ay 1 8, 20 10

0. 5

5

4

3

2

1

DMI _CTX_PRX _N0<5>
DMI _CTX_PRX _N1<5>
DMI _CTX_PRX _N2<5>
DMI _CTX_PRX _N3<5>

DMI_CT X_PRX_P0<5>
DMI_CT X_PRX_P1<5>
DMI_CT X_PRX_P2<5>

D D

PG D_I N<28,3 7>

C C

11/20 HP

DMI_CT X_PRX_P3<5>

DMI _CRX_PTX _N0<5>
DMI _CRX_PTX _N1<5>
DMI _CRX_PTX _N2<5>
DMI _CRX_PTX _N3<5>

DMI_CRX _PTX_P0<5>
DMI_CRX _PTX_P1<5>
DMI_CRX _PTX_P2<5>
DMI_CRX _PTX_P3<5>

+1.0 5VS

1 2

R2 20 49.9 _0402_1 %

XDP _DBRESE T#< 4>

VGATE<37>

R4 08 1K_0 402_5%

1 2

PM_ DRAM _PWR GD<4>

RP GOOD< 33>
PM_RS MRST#<28>

+3V ALW

SUS _PWR _ACK<28>

PM_ PWRB TN#_R<4>
ON /OFF BTN#<2 5,28>

AC_ PRES ENT< 28>

DMI _CTX_PRX _N0
DMI _CTX_PRX _N1
DMI _CTX_PRX _N2
DMI _CTX_PRX _N3

DMI_CT X_PRX_P0
DMI_CT X_PRX_P1
DMI_CT X_PRX_P2
DMI_CT X_PRX_P3

DMI _CRX_PTX _N0
DMI _CRX_PTX _N1
DMI _CRX_PTX _N2
DMI _CRX_PTX _N3

DMI_CRX _PTX_P0
DMI_CRX _PTX_P1
DMI_CRX _PTX_P2
DMI_CRX _PTX_P3

DMI _IRCO MP

SYS _RS T#

1 2

R2 23 0_04 02_5%

VGATE

1 2

PM_ DRAM _PW RGD

1 2
1 2

1 2

1 2

M_P WROK

AUX PWROK

10K _0402_5%

LOW _BAT_ R

IBE X_R#

1 2

R2 24 0_04 02_5%

R2 25 10K _0402_5%

R2 28 0_04 02_5%

R2 29 10K _0402_5 %

R1 467

R2 31 0_0 402_5%

U7C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBE XPEAK- M_FCBGA1 071

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Manag ement

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

PMSYNCH

SLP_LAN#

TP23

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7

FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7

FD I_I NT

FD I_F SYN C0

FD I_F SYN C1

FD I_L SY NC0

FD I_L SY NC1

PCI E_WA KE#

P M_CLK RUN#

SUS _CLK

SLP _S5#

SLP _LAN#

FDI _CTX_ PRX_N0 <5>
FDI _CTX_ PRX_N1 <5>
FDI _CTX_ PRX_N2 <5>
FDI _CTX_ PRX_N3 <5>
FDI _CTX_ PRX_N4 <5>
FDI _CTX_ PRX_N5 <5>
FDI _CTX_ PRX_N6 <5>
FDI _CTX_ PRX_N7 <5>

FDI _CTX_PRX _P0 <5>
FDI _CTX_PRX _P1 <5>
FDI _CTX_PRX _P2 <5>
FDI _CTX_PRX _P3 <5>
FDI _CTX_PRX _P4 <5>
FDI _CTX_PRX _P5 <5>
FDI _CTX_PRX _P6 <5>
FDI _CTX_PRX _P7 <5>

FD I_IN T <5>

FD I_F SYN C0 <5>

FD I_F SYN C1 <5>

FD I_L SYN C0 <5>

FD I_L SYN C1 <5>

PCI E_WA KE# <21 ,22>

PM _CLK RUN# <28>

T144 P AD

T58 PA D

SLP _S4# <30 ,36>

SLP _S3# <21 ,23,2 8,29, 30,32,3 4,35>

H_ PM_S YNC <4>

ENA BLT<18>
EN AVD D<18>

INV _PWM<18>

DD C2_C LK<18>
DD C2_DA TA< 18>

+3VS

Clo se PC H a nd m ini s pace 20mil

LVD S_AC LKN<18>
LVD S_ACLK P<1 8>

LVD S_A0 N<18 >
LVD S_A1 N<18 >
LVD S_A2 N<18 >

LVD S_A0P<18>
LVD S_A1P<18>
LVD S_A2P<18>

M_B LUE<1 9>
M_G REEN<19>
M_R ED<19>

3V DDC CL<19>
3V DDC DA<19>

CR T_H SYN C<19>
CR T_V SYNC<19>

1 2

R7 71 10K_ 0402_5%

1 2

R7 72 10K_ 0402_5%

R7 73 2.3 7K_04 02_1%

1 2

M_B LUE
M_G REEN
M_R ED

delete R84, R66,R67
11/20 HP

3V DDC CL
3V DDC DA

CR T_H SY NC
CR T_V SYN C

1K_0402_0.5%

DD C2_ CLK
DD C2_DA TA

T57P AD

R2 32

DA C_I REF

U7D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBE XPEAK- M_FCBGA 1071

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

R2 26

2.2K_0402_5%

R2 27

2.2K_0402_5%

DPD _AUX#
DPD _AUX

DPD _TXN0
DPD_ TXP0
DPD _TXN1
DPD_ TXP1
DPD _TXN2
DPD_ TXP2
DPD _TXN3
DPD_ TXP3

DP D_H PD

R2 35 100K_ 0402_5%

1 2

SDVO

Display Port B

Display Port C

+3VS

DP D_CT RLCLK < 17>

DPD _CTRL DATA < 17>

DPD _AUX# < 17>
DPD _AUX <17 >
DP D_H PD <17>

DPD _TXN0 <17>
DPD_T XP0 <17>
DPD _TXN1 <17>
DPD_T XP1 <17>
DPD _TXN2 <17>
DPD_T XP2 <17>
DPD _TXN3 <17>
DPD_T XP3 <17>

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digita l Disp lay In terface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

VGATE

B B

A A

5

P M_CLK RUN#

SYS _RS T#

LOW _BAT_ R

SLP _LAN#

IBE X_R#

PCI E_WA KE#

AC_ PRES ENT

1 2

R2 37 10K _0402_5 %

1 2

R2 38 10K _0402_5 %@

1 2

R2 39 10K _0402_5 %

1 2

R2 41 10K _0402_5 %@

1 2

R2 43 10K _0402_5 %

1 2

R2 45 1K _0402_5%

1 2

R2 46 10K _0402_5 %

+3VS

+3V ALW

SLP _S3#

SLP _S4#

SLP _S5#

1 2

R2 36 10K _0402_5 %

1 2

R2 40 10K _0402_5 %@

1 2

R2 42 10K _0402_5 %@

1 2

R2 44 10K _0402_5 %@

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

LA -61 61P

1

13 41T uesd ay, M ay 1 8, 20 10

0. 5

5

D D

PCI _PIRQ A#
PCI _PIRQ B#
PC I_P IRQC #
PC I_P IRQD #

PCI _REQ 0#
PCI _REQ 1#

C C

T114PA D
T115PA D

ACC EL_IN T#<22>

PC I_SE RR#<27, 28>

B B

A A

PLT_R ST#<4 ,21,2 2,27>

PCI _PIRQ E#
PCI _STOP#
PC I_P IRQD #
ACC EL_IN T#

PCI _REQ 2#
PCI _REQ 1#
PCI _FRA ME#
PC I_ TRDY#

PC I_I RD Y#
PC I_P ERR#
PCI _DEV SEL#
PC I_S ERR#

PCI _REQ 0#
PCI _PIRQ B#
PC I_P IRQF#
PCI _REQ 3#

PCI _PIRQ A#
PCI _LOCK #
PC I_P IRQC #
P CI_PI RQG#

PCI _REQ 2#
PCI _REQ 3#

PCI _GNT 0#

MOD EM_DIS ABLE

PCI _GNT 2#
PCI _GNT 3#

PCI _PIRQ E#
PC I_P IRQF#
P CI_PI RQG#
ACC EL_IN T#

PC I_S ERR#
PC I_P ERR#

PC I_I RD Y#
P CI_PA R

T138PA D

PCI _DEV SEL#
PCI _FRA ME#

PCI _LOCK #

PCI _STOP#
PC I_ TRDY#

CL K_PC I_KB C_R
CL K_P CI_FB _R

CLK _PCI_ DB_P

R1 367 8.2 K_040 2_5%

1 2

R1 368 8.2 K_040 2_5%

1 2

R1 369 8.2 K_040 2_5%

1 2

R1 370 8.2 K_040 2_5%

1 2

R1 371 8.2 K_040 2_5%

1 2

R1 372 8.2 K_040 2_5%

1 2

R1 374 8.2 K_040 2_5%

1 2

R1 376 8.2 K_040 2_5%

1 2

R1 379 8.2 K_040 2_5%

1 2

R1 380 8.2 K_040 2_5%

1 2

R1 381 8.2 K_040 2_5%

1 2

R1 382 8.2 K_040 2_5%

1 2

R1 385 8.2 K_040 2_5%

1 2

R1 387 8.2 K_040 2_5%

1 2

R1 389 8.2 K_040 2_5%

1 2

R1 390 8.2 K_040 2_5%

1 2

R1 383 8.2 K_040 2_5%

1 2

R1 384 8.2 K_040 2_5%

1 2

R1 386 8.2 K_040 2_5%

1 2

R1 388 8.2 K_040 2_5%

1 2

5

U7 E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

+3VS

IBE XPEAK- M_FCBGA1 071

PCI _GNT 0#

MOD EM_DIS ABLE

PCI _GNT 3#

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NV RAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

PC I

USB

R2 67 1K_04 02_5%@

1 2

R2 71 1K_04 02_5%@

1 2

R3 00 1K_04 02_5%@

1 2

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2

AV7

AY8
AY5

AV11
BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25

D25

N16
J16
F16
L16
E14
G16
F12
T15

CLK _PCI_ KBC<28>

CL K_PC I_DB<27>
CL K_PCI _FB<1 2>

4

Int el An ti- Theft Tech onlog y

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ ALE

R1 74 1K_ 0402_5%@

1 2

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Wea k i ntern al
PU, Do not pull low

NV _CLE

R1 90 1K_ 0402_5%@

1 2

NV_ ALE
NV _CLE

NV_ RCOM P

R2 57 32.4 _0402_1 %@

USB 20_N0
USB 20_P0
USB 20_N1
USB 20_P1

USB 20_N3
USB 20_P3

USB 20_N5
USB 20_P5
USB 20_N6
USB 20_P6

USB 20_N8
USB 20_P8
USB 20_N9
USB 20_P9
USB 20_N 10
USB 20_P10

USB 20_N 12
USB 20_P12

USB RBIA S

R2 59 22.6 _0402_1 %

USB _OC# 0

USB _OC# 2
FP R_ OFF
USB _OC# 4

LAN LINK _STATUS #
CPP E#

4

1 2

USB 20_N0 < 24>
USB 20_P0 <2 4>
USB 20_N1 < 24>
USB 20_P1 <2 4>

USB 20_N3 < 24>
USB 20_P3 <2 4>

USB 20_N5 < 24>
USB 20_P5 <2 4>
USB 20_N6 < 22>
USB 20_P6 <2 2>

USB 20_N8 < 26>
USB 20_P8 <2 6>
USB 20_N9 < 22>
USB 20_P9 <2 2>
USB 20_N1 0 <19>
USB 20_P10 < 19>

USB 20_N1 2 <18>
USB 20_P12 < 18>

1 2

ISO _PREP #

R2 66 22_0 402_5%

1 2

R2 74 22_0 402_5%

1 2

R2 76 22_0 402_5%

1 2

BUF _PLT_RS T#<4>

*

+1.8V S

+3VS

Power USB

USB_SB

USB_SB

Card Reader

WLAN

11/21 HP

BT

WWAN

FPR

USB_CAM

BT_ OFF <26>

FP R_O FF <19>

LAN LINK_ STATUS# < 21>

CL K_PC I_KB C_R

CLK _PCI_ DB_P
CL K_P CI_FB _R

R2 88 0_04 02_5%

1 2

4

12

@

R1 470

100K _0402_5 %

+3VS

T132
PA D

WWA N_TR ANSM IT_O FF#<20,22>

LA N_DIS #<21>

+3V ALW

12

R4 30
10K _0402_5%

12

R1 504
10K _0402_5%

@

2/2 4

L

CPU Type Detect :
High-->SV , Low-->ULV

+3VS

5

U1 0

1

P

IN1

O

2

IN2

G

SN7 4AHC1 G08D CKR_S C70-5@

3

R2 50 10K_0 402_5%

1 2

PC H_D DR_R ST<4>

WW AN_D ET#<22>

LA N_DI S#

NPC I_RST #<28>

WEB CAM _OFF<18>

CLK _PCIE _LAN _REQ#<21>

WLA N_TRA NSM IT_OFF#<22>

GPI O46

GPI O15

PLT_ RST#

3

PCH _XDP _GPIO0

OC P#<38>

RU NSC I_E C#<28>

CB _IN#<2 1>

R3 02 10K_0 402_5%@

RU NSC I_E C#

GPI O7

PC H_D DR_R ST

GPI O15

PCH _XDP _GPIO16

ALS _EN#

T134
PA D

WW AN_D ET#

GPI O24

WWA N_TR ANSM IT_O FF#

R1 482 0_0 402_5%@

1 2

STP _PCI#

SAT A_CLK REQ#

@

1 2

R2 78 10K_ 0402_5%

WEB CAM _OFF

T145
PA D
T146
PA D

CLK _PCIE _LAN _REQ#

GPI O46

2/24

GPI O48

PCH _XDP _GPIO49

T133
PA D

WLA N_TRA NSM IT_OFF#

PC H_NC TF6<16>
PC H_NC TF7<16>

PC H_NC TF19<1 6>

PC H_NC TF26<1 6>

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

U7 F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

MEM_LED / GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBE XPEAK- M_FCBGA 1071

2008/09/15 2009/09/03

GPIO

NCTF

RSVD

WLA N_TRA NSM IT_OFF#

WWA N_TR ANSM IT_O FF#

GPI O24

GPI O15

ISO _PREP #

USB _OC# 0

PC H_D DR_R ST

USB _OC# 4

CPP E#

USB _OC# 2

Compal Secret Data

2

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CPU

R2 69 10K_0 402_5%

1 2

R2 73 10K_0 402_5%

1 2

R2 77 10K_0 402_5%

1 2

R2 80 1K_04 02_5%

1 2

R2 83 10K_0 402_5%

1 2

R2 89 10K_0 402_5%

1 2

R2 91 10K_0 402_5%

1 2

R2 93 10K_0 402_5%

1 2

R2 95 10K_0 402_5%

1 2

R3 01 10K_0 402_5%

1 2

Deciphered Date

2

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

INIT3_3V#

TP24

1

CLK _PCIE _LAN #_R

AH45
AH46

AF48
AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

+3V ALW +3VS

CLK _PCIE _LAN _R

PC H_P ECI_ R

KB _RST#

H_T HERM TRIP#_L

T59 PA D

T60 PA D

T61 PA D

T62 PA D

T63 PA D

T64 PA D

T65 PA D

T66 PA D

T67 PA D

T68 PA D

T69 PA D

T70 PA D

T71 PA D

T72 PA D

T73 PA D

T74 PA D

T75 PA D

T76 PA D

T77 PA D

T78 PA D

T79 PA D

T80 PA D

T81 PA D

T82 PA D

T83 PA D

T84 PA D

NPC I_RST #

SAT A_CLK REQ#

PCH _XDP _GPIO49

ALS _EN#

RU NSC I_E C#

WEB CAM _OFF

PCH _XDP _GPIO16

GPI O48

STP _PCI#

GPI O7

R2 53

1 2

10K _0402_5%

0_04 02_5%

R2 54

1 2

R2 60

1 2

10K _0402_5%

1 2

R2 55 56_ 0402_5%

56_0 402_5%

Title

Size D ocum ent N umber R ev

Cu sto m

LA -61 61P

Da te: She et o f

R2 51 0_04 02_5%

R2 52 0_04 02_5%

R2 56

CLK _PCI_ KBC

1

2

CL K_PC I_FB

1

2

R2 68 10K_0 402_5%

1 2

R2 72 10K_0 402_5%

1 2

R2 75 10K_0 402_5%

1 2

R2 81 10K_0 402_5%

1 2

R2 85 10K_0 402_5%

1 2

R2 87 10K_0 402_5%@

1 2

R2 90 10K_0 402_5%

1 2

R2 96 10K_0 402_5%

1 2

R2 99 10K_0 402_5%

1 2

R3 04 10K_0 402_5%

1 2

+3VS

GATE A20 <28>

CLK _CPU_ BCLK # <4>

CL K_CPU _BCL K <4>

H_ PEC I <4>

+3VS

KB_ RST# <28>

H_ CPU PW RGD <4>

H_T HERM TRIP# <4>

12

+V CCP

C6 35
12P _0402_5 0V8J

C6 58
12P _0402_5 0V8J

12
12

for RF, SI

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

1

CLK _PCIE _LAN # <21>

CLK _PCIE _LAN < 21>

0. 5

14 41T uesd ay, M ay 1 8, 20 10

1

T123P AD

U7 J

AP51

VCCACLK[1]

AP53

VCCACLK[2]

1 2

A A

22U_ 0805_ 6.3V6M

B B

C C

+R TCVC C

D D

T111P AD

1 2

C2 72

1 2

C2 74

1 2

C2 78

1 2

C2 80

R1 256 0_04 02_5%

1 2

C2 47 0.1U _0402 _16V4Z

+1.0 5VS

1

C2 56

C2 55

2

22U_ 0805_6. 3V6M

C2 58

1 2

+V1 .05S_ VCCA _A_DPL

+V1 .05S_ VCCA _B_DPL

+1.0 5VS

1U_0 402_6 .3V4Z

C2 67

1

2

0.1U _0402 _16V4Z

+V1 .1A_I NT_V CCSUS

0.1U _0402 _16V4Z

+3V ALW

0.1U _0402 _16V4Z

+3VS

0.1U _0402 _16V4Z

+V CCP

C2 84

C2 90

1U_0 402_6 .3V4Z

1

2

0.1U _0402 _16V4Z

+1.8V S

C2 68

1

2

4.7U _0603 _6.3V6K

1

2

1U_0 402_6 .3V4Z

1

2

C2 52

1

2

1

C2 57

2

+VC CRTCEXT

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

C2 69

1

2

+VC CSST

0.

0. 2A @ 3. 3 V

2A @ 3. 3 V

0.0.

2A @ 3. 3 V2A @ 3. 3 V

0.

0. 4A @ 3. 3 V

4A @ 3. 3 V

0.0.

4A @ 3. 3 V4A @ 3. 3 V

0.

0. 1A @ 1. 1 V

1A @ 1. 1 V

0.0.

1A @ 1. 1 V1A @ 1. 1 V

0.1U _0402 _16V4Z
C2 86

C2 85

1

2

2m A

2m A @3 . 3V

@3 . 3V

2m A2m A

@3 . 3V@3 . 3V

0.1U _0402 _16V4Z

C2 91

1

2

AF23

AF24

AD38

AD39

AD41

1U_0 402_6 .3V4Z

AF43

AF41

AF42

AU24

BB51
BB53

BD51
BD53

AH23

AJ35

AH35

AF34

AH34

AF32

AT18

0.1U _0402 _16V4Z

1

AU18

2

VCCLAN[1]

VCCLAN[2]

Y20

DCPSUSBYP

VCCME[1]

VCCME[2]

VCCME[3]

VCCME[4]

VCCME[5]

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]

VCCIO[3]

VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

A12

VCCRTC

IBE XPEAK- M_FCBGA1 071

0.035A

0.072A

0.073A

>1mA

0.052A

0.344A

1.998A

3.208A

2mA

POWER

USB

Clock and Mi scella neous

PCI/GP IO/LPC

0.032A

SA TA

CPU

RTC PCI /GPIO/ LPC

0

.163A

>1mA

0.357A

6mA

HDA

>1mA

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]

VCC3_3[10]

VCC3_3[11]

VCC3_3[12]

VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1]
VCCSATAPLL[2]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

2

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23

V23

F24

K49

J38

L38

M36

N36

P36

U35

AD13

AK3
AK1

AH22

AT20

AH19

AD20

AF22

AD19
AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

+1.05 VS

IC H_V5 REF_ SUS

IC H_V 5RE F_RU N

+PC H_VCC 1_1_ 20
+PC H_VCC 1_1_ 21
+PC H_VCC 1_1_ 22
+PC H_VCC 1_1_ 23

1

C2 46
1U_0 402_6 .3V4Z

2

+3V ALW

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

C2 50

C2 51

1

1

2

2

+1.0 5VS

+3VS

1

C2 62

0.1U _0402 _16V4Z

2

+3VS

1 2

C2 70 0.1U_ 0402_ 16V4Z

T126 PAD
T127 PAD

+1.8V S

1U_0 402_6 .3V4Z

C2 79

1

2

<BO M Stru cture>

R3 05 0_04 02_5%

1 2

R3 06 0_04 02_5%

1 2

R3 07 0_04 02_5%

1 2

R3 08 0_04 02_5%

1 2

1 2

R3 11 0_04 02_5%

1

C2 89

1U_0 402_6 .3V4Z

2

+1.0 5VS

+1.0 5VS

+3V ALW

3

Don't need extra-power

+1.8V S

+1.05 VS

+1.0 5VS

1U_0 603_1 0V4Z

C2 40

1

2

+1.0 5VS

+1.0 5VS_AP LL

T124P AD

+1.0 5VS

1U_0 402_6 .3V4Z

C2 59

1

2

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

C2 64

C2 63

1

1

2

2

C2 710.1U _0402 _16V4Z

1 2

R3 03 0_04 02_5%

1 2

+1.0 5VS_ VCCF DIPLL

T125P AD

+1.05 VS

Don't need extra-power

L10

1 2

10UH _LB2 012T1 00MR_20%_08 05

1U_0 402_6 .3V4Z

L11

1 2

10UH _LB2 012T1 00MR_20%_08 05

1U_0 402_6 .3V4Z

+3VS

@

@

C2 41

C2 60

C2 65

C2 82

C2 88

1

2

1

2

1

2

U7 G

AB24

10U_ 0805_ 6.3V6M

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

1U_0 402_6 .3V4Z

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

10U_ 0603_6. 3V6M

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IBE XPEAK- M_FCBGA1 071

+V1 .05S_ VCCA _A_DPL

1

1

+

C2 81
220U _B2_ 2.5VM_R35M

2

2

+V1 .05S_ VCCA _B_DPL

1

1

+

C2 87
220U _B2_ 2.5VM_R35M

2

2

POWER

1.524A

0.042A

0.035A

6mA

4

L7

1 2

10U_ 0805_6. 3V6M

VCCADAC[1]

0.069A

VCCADAC[2]

VSSA_DAC[1]

CRTLVDS

VSSA_DAC[2]

0.030A

0.059A

VCCALVDS

VSSA_LVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

VCC3_3[2]

VCC3_3[3]

VCC3_3[4]

VCC CO RE

AE52

AF53

AF51

AH38

AH39

AP43
AP45
AT46
AT45

AB34

AB35

AD35

@

C2 42

1

2

+3VS

0.01 U_060 3_16V7K

AE50

10UH _LB2 012T1 00MR_20%_08 05

0.1U _0402 _16V4Z

@

C2 43

C2 44

1

1

2

2

1 2

C2 54 0.1U _0402 _16V4Z

+3VS

0.01 U_060 3_16V7K

C9 99

C9 98

1

1

@

@

2

2

0.01 U_060 3_16V7K

C1 000

1

2

5

+3VS

L43

1 2

0.1U H_ML F1608 DR10K T_10%

22U_ 0805_6. 3V6M

+1.8 VS

HVCMOS

+1.8V S

AT24

VCCVRM[2]

VCCDMI[1]

0.061A

DMI

VCCDMI[2]

VCCPNAND[1]

0.156A

NAND / SPI

0.085A

VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

PCI E*

FDI

AT16

AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

100_ 0402_5%

+VC CP

C2 61 1U_0 603_1 0V4Z

12

R3 09

C2 92

1U_0 402_6 .3V4Z

1 2

R6 71 0_040 2_5%

0.1U _0402 _16V4Z

C2 66

1

2

0.1U _0402 _16V4Z

C2 75

1

2

21

D2

CH75 1H-4 0PT_S OD323-2

IC H_V5 REF_ SUS

1

2

1 2

R6 72 0_040 2_5%@

1 2

R6 73 0_040 2_5%

1 2

1

C1 337

0.1U _0402 _16V4Z

2

add 0. 1uf(0 402) on +3VS to GND near D3 & R1386
and R1 386 ( for 3 3MHz h armonic)for EMI request, Compal SI, 1/19

100_ 0402_5%

R3 10

+1.8 VS

+3VS

+3VS

+5VS +3VS+3V ALW+5VA LW

12

+3VS+3VS

1

C1 336

0.1U _0402 _16V4Z

2

21

D3

CH75 1H-4 0PT_S OD323-2

IC H_V 5RE F_RU N

1

C2 93
1U_0 603_6. 3V6M

2

20 mi ls20 mi ls

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(5/6)-PWR

LA -61 61P

5

15 41T uesd ay, M ay 1 8, 20 10

0. 5

1

2

3

4

5

U7 I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

A A

B B

C C

D D

VSS[168]

B7

VSS[169]

BG12

VSS[170]

BB12

VSS[171]

BB16

VSS[172]

BB20

VSS[173]

BB24

VSS[174]

BB30

VSS[175]

BB34

VSS[176]

BB38

VSS[177]

BB42

VSS[178]

BB49

VSS[179]

BB5

VSS[180]

BC10

VSS[181]

BC14

VSS[182]

BC18

VSS[183]

BC2

VSS[184]

BC22

VSS[185]

BC32

VSS[186]

BC36

VSS[187]

BC40

VSS[188]

BC44

VSS[189]

BC52

VSS[190]

BH9

VSS[191]

BD48

VSS[192]

BD49

VSS[193]

BD5

VSS[194]

BE12

VSS[195]

BE16

VSS[196]

BE20

VSS[197]

BE24

VSS[198]

BE30

VSS[199]

BE34

VSS[200]

BE38

VSS[201]

BE42

VSS[202]

BE46

VSS[203]

BE48

VSS[204]

BE50

VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]

BF49

VSS[209]

BF51

VSS[210]

BG18

VSS[211]

BG24

VSS[212]

BG4

VSS[213]

BG50

VSS[214]

BH11

VSS[215]

BH15

VSS[216]

BH19

VSS[217]

BH23

VSS[218]

BH31

VSS[219]

BH35

VSS[220]

BH39

VSS[221]

BH43

VSS[222]

BH47

VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]

AF39

VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

IBE XPEAK- M_FCBGA1 071

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

U7H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBE XPEAK- M_FCBGA1 071

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

+3VS

12

R3 12

61

100K _0402_5 %

Q10A
2N70 02DW -T/R7 _SOT363-6

+3VS

+3VS

+3VS

12

12

12

2

R3 13

3

100K _0402_5 %

5

4

R3 14

61

100K _0402_5 %

Q11 A
2N70 02DW -T/R7 _SOT363- 6

2

R3 15

3

100K _0402_5 %

Q11 B
2N70 02DW -T/R7 _SOT363- 6

5

4

CRA CK_B GA

Q10B
2N70 02DW -T/R7 _SOT363-6

CRA CK_B GA

CRA CK_B GA

PC H_NC TF6<14>

PC H_NC TF7<14>

PC H_NC TF19< 14>

PC H_NC TF26< 14>

CRA CK_B GA <8,28 >

BGA Ball Cracking Prevention and Detection

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(6/6)-GND

LA -61 61P

5

16 41T uesd ay, M ay 1 8, 20 10

0. 5

5

D D

C C

4

DPD _CTRL DATA<13>

DP D_CT RLCLK<13>

DPD _AUX#<13>

+3VS

DPD _AUX<13>

21

F1

NAN OSMD C050F 0.5 A 13. 2V P OLY- FUSE

+3V S_DP

DPD _AUX#

DPD _AUX

3

2N70 02DW -7-F _SOT363-6

D DC_ EN

2N70 02DW -7-F_S OT363-6

D DC_ EN

+3VS

R1 101

@

100K _0402_5 %

1 2

R1 105

@

100K _0402_5 %

1 2

Q22A

61

2

Q5A

61

2

2

2N70 02DW -7-F_S OT363-6

2N70 02DW -7-F_S OT363-6

61

Q23A

5

3

4

Q23B

2

+3VS

R1 097

Q22B

2N70 02DW -7-F_S OT363-6

3

4

5

Q5B

2N70 02DW -7-F_S OT363-6

N294 41889DP D_C TRLCL K DPD _C_A UX

3

DP _EN

DPD _AUX #_1

2N70 02DW -7-F_S OT363-6

DP _EN

DPD _AUX_ 1

2N70 02DW -7-F_S OT363-6

5

2

6 1

Q24A

5

3

Q24B

4

4

1 2

1 2

DP _DC AD

100K _0402_5 %

R1 099
100K _0402_5 %

2

DPD _C_AU X#DPD _CTRL DATA N294 41921

1 2

61

+5VS+5VS

1 2

3

5

4

R1 107
10K _0402_5%

Q21B
2N70 02DW -7-F_S OT363-6

R1 106
10K _0402_5%

DP _EN D DC_ EN

2N70 02DW -7-F_S OT363-6
Q21A

1

C6 64

0.1U _0402 _16V4Z

C6 65

10U_ 0805_ 10V4Z

1

1

2

2

B B

A A

DPD_ TXP0<13>

DPD _TXN0<13>

DPD_ TXP1<13>

DPD _TXN1<13>

DPD_ TXP2<13>

DPD _TXN2<13>

DPD_ TXP3<13>

DPD _TXN3<13>

DPD_ TXP0

DPD _TXN0

DPD _TXN1

DPD_ TXP2

DPD _TXN2

DPD_ TXP3

DPD _TXN3

5

12

12

12

12

12

12

12

12

DP_ DATA 0R_P

C1 3040.1U _0402 _16V4Z

DP_ DATA 0R_N

C1 3050.1U _0402 _16V4Z

DP_ DATA 1R_PDPD_ TXP1

C1 3060.1U _0402 _16V4Z

DP_ DATA 1R_N

C1 3070.1U _0402 _16V4Z

DP_ DATA 2R_P

C1 3080.1U _0402 _16V4Z

DP_ DATA 2R_N

C1 3090.1U _0402 _16V4Z

DP_ DATA 3R_P

C1 3100.1U _0402 _16V4Z

DP_ DATA 3R_N

C1 3110.1U _0402 _16V4Z

4

12

12

R1 115

R1 114

1M_ 0402_5%

5.1M _0402_5%

DP _HP D
DPD _C_AU X#

DPD _C_A UX

DP _DC AD
DP_ DATA 3R_N

DP_ DATA 3R_P
DP_ DATA 2R_N

DP_ DATA 2R_P
DP_ DATA 1R_N

DP_ DATA 1R_P
DP_ DATA 0R_N

DP_ DATA 0R_P

3

JD P1

CO NN@

20

DP_PWR

19

RTN

18

HP_DET

17

AUX_CH-

16

GND

15

AUX_CH+

14

GND

13

CA_DET

12

LANE3-

11

LANE3_shield

10

LANE3+

9

LANE2-

8

LANE2_shield

7

LANE2+

6

LANE1-

5

LANE1_shield

4

LANE1+

3

LANE0-

2

LANE0_shield

1

LANE0+

MOLEX _105062-0001 _20P-T

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

24

GND

23

GND

22

GND

21

GND

2009/08/03 2009/09/03

DP _HP D

Compal Secret Data

Deciphered Date

2

12

R1 1170_04 02_5%

TR 2N700 2DW-7 -F 2 N SOT-3 63

3

Title

Size D ocum ent N umber R ev

Da te: She et o f

+5VS

5

4

Q12B

Compal Electronics, Inc.

Display Port Connector

LA -6 161 P

1

DP D_H PD <13>

0. 5

17 41T uesd ay, M ay 1 8, 20 10

5

4

3

2

1

LED/PANEL BD. CONN.

D D

C666 0 .1U_0603_50V

12

C667 68P_0402_50V8J

12

+3VS

R1120

10K_0402_5%

ENABLT<13>

LID_SW#<25,28>

+3VALW

C C

+3VL

5/11

INV_PWM

0.1U_0402_16V4Z

for E MI for R F

R1122
100K_0402_1%

R1123

10K_0402_5%

R1506

@

10K_0402_5%

C1318

12

12

12

1

2

D4

CH751 H-40_SC76

1

C1339

0.1U_0402_16V4Z

2

3/2 3 for EMI

D5

CH751 H-40_SC76

+5V_WEBCAM

21

21

USB20_N12_R

1 2

D6

@

4

VIN

3

IO2

CM1293A-02SR_SOT143-4

for E SD

IO1

GND

DISP LAY_OFF#

2

1

B+

+3VS

LCDVD D

INV_PWM<13>

USB20_P12_R

L38

@

1 2

LQM21FN4R7N00L_0805

33_0402_5%

R1121

1 2

+5V_WEBCAM

USB20_P12_R
USB20_N12_R

B+_LCD

BLON_PWM_R

USB20_P12<14>
USB20_N12<14>

JLVDS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

3132

ACES_88242-3001_30P

CONN@

R1471 0_0402_5%

1 2

L44

@

1

1

4

4

WCM2012F2S-900T04_0805

1 2

R1472 0_0402_5%

2

3

2

3

USB20_P12_R
USB20_N12_R

+3VS

R11182.2K_0402_5 %

LVDS_A0N <13>
LVDS_A0P <13>

LVDS_A1N <13>
LVDS_A1P <13>

LVDS_A2N <13>
LVDS_A2P <13>

LVDS_ACLK N <13>
LVDS_ACLKP <13>

B+_LCD B+

C1333

1U_0603_25V4Z

R11192.2K_0402_5 %

1 2

1 2

D

S

1 3

G

1

2

2

DDC2_ CLK <13>
DDC2_DAT A <13>

Q90
SI2307CDS -T1-GE3 1P

12

C1332

0.22U_0603_25V7K

R1487

220K_0402_1%

1 2

12

R1488

100K_0402_5%

12/10 HP

LCD POWER CIRCUIT

for R F

C1327

@

47P_0402_50V8J

R1126 47K_0402_5%

1 2

0.1U_0402_16V4Z

1

OUT

Q55
DTC124EKAGZT146_SC59-3

GND

3

Q6A

R1130

1 2

12

R1124
100_0402_1%

61

2

2

IN

B B

2N7002DW-7-F_SOT363-6

ENAVD D<13>

100K_0402_1%

A A

5

LCDVD DLCDV DD +3VS

Q53

D

S

SI2301 1P_SOT23

12

1

C681

2

1 3

G

2

R1125 1M_0402_5%

1 2

C676 0.2 2U_0402_10V4Z

1

C682

2.2U_0805_10V5R

2

4

1 2

5/18

+5VS

1

C683

4.7U_0805_10V4Z@

2

WEBCAM_OFF<1 4>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/03 2009/09/03

Compal Secret Data

Deciphered Date

+3VS

R1128
10K_0402_5%

1 2

2

+5VS +5V_WEBCAM

1U_0603_10V4Z

1

C677

2

1 2

100K_0402_5%

R1127

1 2

R1129 47K_0402_5%

3

Q6B
2N7002DW -7-F_SOT363-6

5

4

Title

LCD CONN & Q-Switch & GPIO Ext.

Size Doc ument Number Re v

Date: Sheet of

Q54
SI2301BDS_SOT23

S

D

13

G

2

1

2

C678

0.01U_0402_16V7K

C684

0.1U_0402_16V4Z

+5VS

12/05 HP

1

2

Compal Electronics, Inc.

LA-6161P

1

1

C679

C680

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

18 41T uesday, M ay 18, 2010

1

12

@

C1328

2

47P_0402_50V8J

for R F

0.5

1

Finger printer

2

3

4

5

A A

FP R_O FF< 14>

B B

C C

+3V ALW

1 2

R1 463
10K _0402_5%

R1 464
220K _0402_1 %

1 2

S

G

SI2 301BDS _SOT23

D

Q87

2

R6 38 0_04 02_5%

USB 20_P10<14>

13

C1 299

1

2

USB 20_N1 0<14>

C1 300

0.1U _0402 _10V6K

10U_ 0805_10 V4K

1

2

CR T_H SYN C< 13>

CR T_V SYNC<13>

1 2

R6 39 0_04 02_5%

1 2

+5V ALW

USB 20_N1 0_R

for ESD

CR T_H SY NC HS YN C_G_A

CR T_V SYN C

+F P_PW R

D3 5

4

VIN

3

IO2

PRT R5V0U2X_ SOT143-4

GR EEN

B LUE

USB 20_P 10_R
USB 20_N1 0_R

2

IO1

1

GND

+5VS +5 VS

5

P

A2Y

G

3

JF PR1

1
2
3
4

5
6

ACE S_87 151-04051_4 P

USB 20_P 10_R

R1 448

1 2

R1 450

1 2

R1 452

1 2

C2 73

0.1U _0402 _16V4Z

1 2

1

U4
SN7 4AHCT 1G12 5GW_SOT35 3-5

OE#

4

5

A2Y

3

C2 49

0.1U _0402 _16V4Z

1 2

1

P

OE#

G

U5
SN7 4AHCT 1G12 5GW_SOT35 3-5

CO NN@

close to JCRT1

0_06 03_5%

4

0_06 03_5%

0_06 03_5%

C1 296

1

2

VS YNC _G_A

VGA _RERE D

VGA _GR

VG A_BL

10P _0402_5 0V8J@

C1 298

10P _0402_5 0V8J@

C1 297

10P _0402_5 0V8J@

1

1

2

2

R2 17 0_0 402_5%

R2 06 0_0 402_5%

close to PCH (U7)

R1 449 0_ 0603_5%

1 2

1 2

1 2

@

1

C2 53

5P_ 0402_50 V8C

2

R1 451 0_ 0603_5%

R1 453 0_ 0603_5%

12

12

R1 454

1 2

D_ HS YN C

D_ VSY NC

75_0 402_1%

D3 2

2 1

RB4 91D_S C59-3

R1 455

75_0 402_1%

1 2

1 2

@

1

C2 76

5P_ 0402_50 V8C

2

F2

1.1A _6VD C_FU SE

R1 456

75_0 402_1%

21

VGA _R

VG A_G

VGA _B

2.2K _0402 _5%

D_ DDC DATA

D_ DDC CLK

R2 18

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

12

2.2K _0402 _5%

+C RTVD D+R CRT_ VCC+5VS

W=40mils

0.1U _0402 _16V4Z

JC RT1

SU YIN_ 07054 6FR01 5S29 0ZR

CO NN@

R1 93

C2 45

16

G

17

G

12

1

2

6 1

2N70 02DW -7-F_S OT363-6

+3VS+C RTV DD +C RTVD D

2

Q17A

2N70 02DW -7-F_S OT363-6

VGA _B
VG A_G
VGA _R

3

Q17B

D1 7

@

2.2K _0402 _5%

5

4

2

R2 15

1

3

+3VS

12

D1 8

@

DAN 217T1 46_SC59- 3

12

R2 16

2.2K _0402 _5%

1

2

3

3V DDC DA

3V DDC CL

D3 4

@

DAN 217T1 46_SC59- 3

Place close to
JCRT1

1

2

3

+C RTVD D

DAN 217T1 46_SC59- 3

3V DDC DA <13>

3V DDC CL <13>

close to PCH (U7)

2.5' SATA HDD Connector

CRT Termination/EMI Filter close to PCH (U7)

JH DD 1

1

GND

A+

A-

GND

B-

B+

GND

V33
V33

V33
GND
GND
GND

V5

26

V5

GND

25

V5

GND

GND

Reserved

D D

SAN TA_192701- 1_22P-T

24
23

NC
NC

CO NN@

GND

V12

V12

V12

SATA_ TXP0_C

C8 72 0.0 1U_04 02_16V7K

2

SATA_ TXN0_C

3
4

SAT A_RXN0

5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

1

1 2

C8 73 0.0 1U_04 02_16V7K

1 2

C8 70 0.0 1U_04 02_16V7K

1 2

C8 71 0.0 1U_04 02_16V7K

1 2

C2 39

1

2

10U_ 0805_ 10V4Z

0.1U _0402 _16V4Z

losely SATA

C2 38

1

2

0.1U _0402 _16V4Z

C2 11

1

2

Place component's
c
CONN.(JHDD1)

1

2

C2 48

0.1U _0402 _16V4Z

SATA_ PTX_DRX_P0
SATA_ PTX_DRX_N0

SATA_ PRX_DTX_N0
SATA_ PRX_DTX_P0SATA_ RXP0

+5VS

2

SATA_ PTX_DRX_P0 <1 1>
SATA_ PTX_DRX_N0 < 11>

SATA_ PRX_DTX_N0 < 11>
SATA_ PRX_DTX_P0 <1 1>

M_R ED<13>

M_G REEN<13>

M_B LUE<1 3>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

M_R ED

M_G REEN

M_B LUE

27P _0402_5 0V8J

1

2

C2 35

Compal Secret Data

1

2

C2 34

Deciphered Date

L2

1 2

HLC0 603CS CC27 NJT_ 0603

L3

1 2

HLC0 603CS CC27 NJT_ 0603

L4

1 2

HLC0 603CS CC27 NJT_ 0603

27P _0402_5 0V8J

27P _0402_5 0V8J

1

2

C2 37

4

RE D

GR EEN

18P _0402_5 0V8J

1

1

2

2

C2 36

C2 33

B LUE

18P _0402_5 0V8J

18P _0402_5 0V8J

1

2

C2 32

3/24 for EMI

Title

Size D ocum ent N umber Re v

Da te: She et o f

Compal Electronics, Inc.

WLAN/ODD/HDD

LA -61 61P

5

19 41T uesd ay, M ay 1 8, 20 10

0. 5

5

D D

HDD active LED

4

3

61

WW AN_TRANSMIT_OFF#<14,22>

WW_LED#<22>

WW_LED#

1 2

R1140 0_0402_5%

R1133 0_0402_5%

1 2

2

2

+3VS

Q13A
TR 2N 7002DW-7-F 2N SOT-363

12

R1131
47K_0402_5%

1

WL_LED#

R1132 0_0402_5%

1 2

BT_LED<26>

BT_LED

+3VS

12

R1136
1K_0402_5%

12

R1134

255_0402_1%

43

HT-29 7UY5/BP5_YELLOW -WHITE
D7

YELLO W

+3VS

12

R1135
255_0402_1%

21

WHITE

WL_LED#< 22>

whiteAMBER

HDD_H ALTLED#

C C

HDD_H ALTLED<11>

TR 2N 7002DW-7-F 2N SOT-363

HDD_H ALTLED

Q12A

R1139

@

10K_0402_5%

1 2

61

2

9/1 Del Q58

R1137
0_0402_5%

1 2

SATA_LED#<11>

SATA_LED#

+3VS

12

R1141

470_0402_5%

To LED small board

B B

GND
GND

ACES_85201-1005N CON N@

A A

JLED1

1
2
3
4
5
6
7
8
9

10

+3VS

APP_BUTTON_1

1
2
3
4
5
6
7
8
9
10
11
12

WL_BLUE_BTN

WL/BT_LED#

APP_BUTTON_1

APP_BUTTON_1_LED#

APP_BUTTON_2

APP_BUTTON_2_LED#

1

C687

0.1U_0402_16V4Z

2

WL_BLUE_BTN <28>

APP_BUTTON_1 <28>

APP_BUTTON_2 <28>

0.22U_0402_10V4 Z

APP_BUTTON_2

0.22U_0402_10V4 Z

C686

C689

2

1

2

1

61

Q14A

TR 2N 7002DW-7-F 2N SOT-363

2

+3VS

12

R1143

470_0402_5%

61

Q16A

TR 2N 7002DW-7-F 2N SOT-363

2

CH751 H-40_SC76

CH751 H-40_SC76

D8

2 1

D9

2 1

BT_LED

R1138 100K_0402_5%

R1142
1M_0402_5%

1 2

1

C685
1U_0402_6.3V6K

2

R1144
1M_0402_5%

1 2

1

C688
1U_0402_6.3V6K

2

WL/BT_LED#

3

Q13B
TR 2N 7002DW-7-F 2N SOT-363

5

4

1 2

APP_BUTTON_1_LED#

3

Q14B
TR 2N 7002DW-7-F 2N SOT-363

5

4

3

Q16B
TR 2N 7002DW-7-F 2N SOT-363

5

4

12/04 , HP

APP_BUTTON_2_LED#

CAPS_LED#<25>

3

Q15B
TR 2N 7002DW-7-F 2N SOT-363

CAPS_LOCK_KBC<28>

5

4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/03 2009/09/03

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet

Compal Electronics, Inc.

LEDS & LID

LA-6161P

1

0.5

of

20 41Tuesday, May 18, 2010

5

+3VS

13

D

12

LA N_DI S#

LAN_ X1
LAN_ X2

+3V _LAN

12

R1 148
10K _0402_5%

CLK _PCIE _LAN _REQ1 #

U5 7

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_N

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKTAL1

42

CKTAL2

23

GPO

24

NC

7

GND

14

GND

31

GND

47

GND

22

EGND

RTL 8111D L-VB-GR _LQFP48_7X 7

+3VS

R1 147

10K _0402_5%

D D

CLK _PCIE _LAN _REQ#<14>

12

2N70 02_SOT2 3-3

R1 150 0_04 02_5%

G

S

Q60

@

12

R1 145

10K _0402_5%

2

Pla ce Clo se to Chip

C4 79 0. 1U_04 02_16V7K

PCIE_ PRX_DTX_ P6<12>

PCI E_PRX_D TX_N6<12>

C C

+3VS

12

R1 027
1K_ 0402_5%

LA N_DI S#

R1 029

15K _0402_5%

B B

27P _0402_5 0V8J

+3V _LAN

12

12

LAN_ X1 LA N_X2

25MHZ_20PF_7A25000012

1

C1 276

2

12

C4 81 0. 1U_04 02_16V7K

12

PCI E_PTX _C_DRX_P6< 12>

PCI E_PT X_C_DRX_ N6<12>

CLK _PCIE _LAN< 14>

CLK _PCIE _LAN #<14>

PLT_R ST#<4 ,14,2 2,27>

R1 026 2. 49K_ 0402_1%

PCI E_WA KE#<13, 22>

LA N_DI S#<14>

R1 028
0_04 02_5%

CT RL15/ VDD3 3

R1 030

@

0_04 02_5%

Y4

12

PCI E_RX P6_LAN

PCI E_RX N6_LA N

CLK _PCIE _LAN _REQ1 #

1 2

R1 492 0_ 0402_5%@

CB _IN #

1 2

reserv e for switch WLAN
and on board LAN,
Compal SI 1/19

1

C1 249
27P _0402_5 0V8J

2

Close to Pin 39 for 8111DL Close to Pi n40 fo r 8111DL

Close to Pin 10,13, 30,36

2

2

C1 282

1

0.1U _0402 _16V4Z

2

C1 283

1

1

0.1U _0402 _16V4Z

+LA N_VDD 12

C1 284

0.1U _0402 _16V4Z

2

2

C1 285

C1 286

1

1

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

Close to Pin 1,37,29

2

C1 278

1

0.1U _0402 _16V4Z

RTL811 1DL

2

C1 279

1

0.1U _0402 _16V4Z

4

+3V _LAN

2

1

LED2/EEDI/AUX

C1 280

0.1U _0402 _16V4Z

LED3/EEDO

LED1/EESK

EECS

LED0

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

FB12

SROUT12

EVDD12
DVDD12
DVDD12
DVDD12
AVDD12

AVDD12

VDDSR
VDDSR

VDD33
VDD33

AVDD33
AVDD33

ENSR

2

C1 281

1

0.1U _0402 _16V4Z

LA N_D I

LA N_CS

33

LA N_D I

34

LAN LINK _STATUS #

35

LA N_CS

32

LAN _ACTI VITY #

38

LAN _MDI0 +

2

LAN _MDI0 -

3

LAN _MDI1 +

5

LAN _MDI1 -

6

LAN _MDI2 +

8

LAN _MDI2 -

9

LAN _MDI3 +

11

LAN _MDI3 -

12

4

VCT RL12

48

19
30
36
13
10

39

44
45

29
37

1
40
43

R1 024 3.6 K_0402_ 5%

1 2

R1 025 1K_ 0402_5%@

+3V_LAN

+LA N_VDD 12

+EV DD12
+LA N_VDD 12

for in ternal regular

Close to Pin 45,44

+3V _LAN

2

C1 247

CT RL15/ VDD3 3

1

change to 2 2U by realtek request

12

0.1U _0402 _25V6

@

10K _0402_5%

1 2

1

C1 248

2

R2 58

22U_ 0805_6. 3V6M

3

LAN _ACTI VITY #

+3V _LAN

LAN LINK _STATUS #

LAN LINK_ STATUS # <14>

+3V _LAN

12

R1 446
0_08 05_5%

2N70 02DW -7-F_S OT363-6

ADP _PRE S<28, 31,32,3 8>

SLP _S3#<13,2 3,28, 29,30 ,32,34,3 5>

2

+3V _LAN

1 2

300_ 0603_5%

+3V _LAN

1 2

300_ 0603_5%

For ESD

SI2 301BDS _SOT23

12

R1 146
47K _0402_5%

47K _0402_5%

LAN LED_A CT#

RJ4 5_MID I3-

RJ4 5_MID I3+

RJ4 5_MID I1-

RJ4 5_MID I2-

RJ4 5_MID I2+

RJ4 5_MID I1+

RJ4 5_MID I0-

RJ4 5_MID I0+

LAN LED_L INK#

10/100 and Giga Transformer

LAN _MDI3 ­LAN _MDI3 +

LAN _MDI2 ­LAN _MDI2 +

LAN _MDI1 ­LAN _MDI1 +

LAN _MDI0 ­LAN _MDI0 +

+3V_LAN

D

13

370mA

Th e + 3V _LA N R is ing ti me (1 0%~90 %) ne ed >1 mS an d <10 0mS

2

R1 149

S

Q5 9

G

12

R1 165

1

C4 80

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

3

1

2

2

C4 82

1

R1 166

LAN LED_A CT#

LAN LED_L INK#

2

D4 3

@

PAC DN042 _SOT 23~D

C1 042 0.01 U_040 2_16V7K

1 2

C1 277 0.01 U_040 2_16V7K

1 2

C1 291 0.01 U_040 2_16V7K

1 2

C1 292 0.01 U_040 2_16V7K

1 2

Swap t he si gnal 0<-->3 , 1<-->2 for layout routing, Compal SI 1/14

+3VALW

Q27A

2

6 1

3

5

Q27B
2N70 02DW -7-F_S OT363-6

4

LAN Conn.

JR J45

11

Yellow LED+

12

Yellow LED-

8

PR4-

DETECT PIN1

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

9

Green LED+

10

Green LED-

SAN TA_130452- 3_13P-T

U5 6

1

TCT1

MCT1

2

TD1+

MX1+

3

TD1-

MX1-

4

TCT2

MCT2

5

TD2+

MX2+

TD2-6MX2-

7

TCT3

MCT3

8

TD3+

MX3+

9

TD3-

MX3-

10

TCT4

MCT4

11

TD4+

MX4+

12

TD4-

MX4-

SUP ERWO RLD_S WG15 0401

2nd So urce :
HDT B A30-A6 6 1G LAN

+3V _LAN

15

SHLD1

13

14

SHLD1

C1 041 100 0P_0402_5 0V7K

24
23
22

C1 039 100 0P_0402_5 0V7K

21
20
19

C1 085 100 0P_0402_5 0V7K

18
17
16

C1 083 100 0P_0402_5 0V7K

15
14
13

R1 445

12

2

C7 19

1

12

12

12

12

10K _0402_5%

CB _IN #

0.1U _0402 _10V6K@

RJ4 5_MID I3­RJ4 5_MID I3+

RJ4 5_MID I2­RJ4 5_MID I2+

RJ4 5_MID I1­RJ4 5_MID I1+

RJ4 5_MID I0­RJ4 5_MID I0+

CB _IN# < 14>

1

R8 22 75_04 02_1%

1 2

R8 21 75_04 02_1%

1 2

R9 23 75_04 02_1%

1 2

R9 22 75_04 02_1%

1 2

C1 045

1000 P_1808_3K V7K

RJ 45_ GND

2

1

Close to Pin19

A A

+EV DD12

2

2

1

C1 290

C1 289

1

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

5

Close to Pin48

VCT RL12 +EV DD12

L42

1 2

4.7U H_100 8HC- 472EJ FS- A_5%_1008

Note 1 : The Trac e length
between L1 and 811 1DL's Pin
1 mus t be withi n 0.5 cm. C262
and C26 3 to L1 m ust be wit hin

0.5cm . Refer t o Layout guide
for more det ail.

2

1

2

C1 288

C1 287

1

22U_ 0805_6. 3V6M

R8 17

1 2

0_06 03_5%

12

R8 19
0_06 03_5%

0.1U _0402 _16V4Z

4

+LA N_VDD 12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

Compal Electronics, Inc.

GLAN RTL8111DL

LA -6 161 P

1

21 41T uesd ay, M ay 1 8, 20 10

0. 5

A

B

C

D

E

+3VS

1

ACCELEROMETER

1 1

0 0 1 1 1 0 1 b

U14

LIS302DL

+3VS

ACCEL_INT#<14>

SMB_DATA_S3<9,10,12>
SMB_CLK_S3<9,10,12>

R1176 10K_0402_5%

+3VS

2 2

12

L

1

VDD_IO

6

VDD

8

INT 1
INT 29GND

12

SDO

13

SDA / SDI / SDO

14

SCL / SPC

7

CS

Mus t b e pla ce d i n the c ent er of th e syste m.

HP302DLTR8_LGA14_3X5

GND
GND
GND

RSVD
RSVD

2
4
5
10

3
11

Mini-Express Card--WWAN

Full size

JWW AN1

1

1

3 3

PCIE_PTX_C_DRX_N7<12>

PCIE_PTX_C_DRX_P7<12>

4 4

11/21 HP

PCIE_PRX_DTX_N7<12>
PCIE_PRX_DTX_P7<12>

12/05 HP

R207 10K_0402_5%

+3VALW

CLKRE Q_WWAN#<12>

CLK_P CIE_MCARD2#<12>

CLK_P CIE_MCARD2<12>

R1468 0_0402_5%

1 2

R1469 0_0402_5%

1 2

+3V_WWAN

12

T129PAD
T130PAD

PCIE_C_RXN 7
PCIE_C_RXP7

R1174 0_0603_5%

1 2
1 2

R1175 0_0603_5%

T131PAD

3
5
7
9

WW AN_TRANSMIT_OFF#<14,20>

3
5
7
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

MOLEX_67910-5700CO NN@

2
4
6
8

10

+3VS

1

1

C738

C739

2

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

+3VS

Note2

1

+3V_WWAN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

M_WXMIT_OFF#

Compa l,SI 1/4

10K_0402_5%

@

WW_LED#

D14

CH751 H-40_SC76

R1173

21

M_WXMIT_OFF#

Clos e to JP14

+3VS

12

R1172
10K_0402_5%

12

USB20_N9 <14>
USB20_P9 <14>

WW_LED# <20>

2

C732

10P_0402_25V8J

@

for R F

12/04 , HP

10P_0402_25V8J

@

PCIE_PRX_DTX_N4<12>
PCIE_PRX_DTX_P4<12>

PCIE_PTX_C_DRX_N4<12>

PCIE_PTX_C_DRX_P4<12>

+3V_WWAN

1

2

C733

2

C726

0.01U_0402_16V7K

1

2

C734

39P_0402_50V8J

@

WWAN_DE T# <14>

1

1

2

2

C728

C727

4.7U_0805_10V4Z

0.1U_0402_16V4Z

+3VALW

+3VL

03/29

SPI_R ECOVERY<28>

02/23

1

1

2

2

C736

C735

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K

PCIE_WAKE#<13,21>

R1476 10K_0402_5%

CLKRE Q_WLAN#<12>

CLK_P CIE_MCARD#<12>

CLK_P CIE_MCARD<12>

1 2

R1505 0_0402_5%@

R1167 0_0402_5%

1 2

R1168 0_0402_5%

1 2

+3V_WWAN

1

2

C737

4.7U_0805_10V4Z

+1.5VS

1

1

1

2

2

C729

2

C730

C731

0.1U_0402_16V4Z

4.7U_0805_10V4Z

SPI_H OLD#_0<27>

SPI_CLK_JP<27>

SPI_S I_JP<27>

SPI_CS0#_JP<27>

SPI_SO_JP<27>

SPI_H OLD#_0

SPI_CLK_JP SPI_CLK_DB

SPI_S I_JP SPI_S I_DB

1 2

R1498 0_0402_5%@

1 2

R1499 0_0402_5%@

1 2

R1500 0_0402_5%@

1 2

R1501 0_0402_5%@

1 2

R1502 0_0402_5%@

SPI_HOLD#_MB

SPI_CS0#_D BSPI_CS0#_JP

SPI_SO_R0_DBSP I_SO_JP

02/23

WWLAN/WiMax Mini-Express Card

12

delete port 80

PCIE_C_RXN 4
PCIE_C_RXP4

+3VS

MC1_DISABLE<2 8>

PCIE_WAKE#

R1077

10K_0402_5%

half size

JWLAN 1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S40N-7F

CONN@

+3VALW

L

12

1000P_0402_50V7K

1 2

R1079 220K_0402_1%

WWAN power control by F10. 11/09

UIM_DATA

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

XMIT_D_OFF#

Pla ce C9 33 b etw ee n R 10 77.1 an d R 10 79. 2 for l imi t i nrush curr ent.

1

C933

2

SI2305DS-T1-E3_SOT23-3

JSIM1

4

GND

5

VPP

6

I/O

7

DET

R1177

47K_0402_5%

@

1 2

UIM_PWR

SPI_SO_R0_DB
SPI_CS0#_D B
SPI_S I_DB
SPI_CLK_D B

XMIT_D_OFF#
PLT_RST#

Add to prevent leakage issue.

2

Q77

TAITW_PMPAT6-06GLBS7N14N0CONN@

SPI_HOLD#_MB

WL_LED#

2 1

D12 CH751H-40_S C76

31

1 2

1

2

S DIO(B R) NUP4301MR6T1 TSOP-6@

J3
SHORT PAD S

04/19

U13

CH1

Vn

CH23CH3

02/23

PLT_RST# <4,14,21,27>

USB20_N6 <14>
USB20_P6 <14>

WL_LED# <20 >

+3V_WWAN

R1080

12

0_0805_5%

6

CH4

5

Vp

4

1

VCC

2

RST

3

CLK

1

C740

2

8

GND

9

GND

UIM_PWR
UIM_RSTUIM_VPP
UIM_CLK

18P_0402_50V8J

11/21 HP

12/04 , HP

WLAN _TRANSMIT_OFF# <14>

+3V_WWAN

D13

DAN217T146_SC59-3@

1

1

1

2

2

C741

C742

4.7U_0805_10V4Z

+3VS

+1.5VS

+3V_WWAN

3

2

0.1U_0402_16V4Z

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/08/03 2009/09/03

Compal Secret Data

Deciphered Date

Title

WLAN&WWAN Mini-Card/Accelerometer

Size Doc ument Number Re v

D

Date: Sheet

Compal Electronics, Inc.

LA-6161P

22 41T uesday, M ay 18, 2010

E

0.5

of

A

+3VS

R1334

BLM18BD601SN1D_0603

+3VS

R1340 0_0603_5%

1 2

1 1

2 2

MUTE_LED_CNTL<28>

3 3

CODEC POWER

.75V)

(4
300mA

+3VS_HDA

1

C880

2

0.1U_0402_16V4Z

@

33P_0402_50V8K

HDA_B IT_CLK_CODEC<11>

HDA_S DIN0<11>

HDA_S DOUT_CODEC<11>

HDA _SYNC_COD EC<11>

HDA_R ST#_CODEC<11>

+3VS_DVDD

EC_MUTE#<28>

W=40Mil

C1293

4.7K_0402_5%

+AVDD _CODEC

MUTE_LED_CNTL

1 2

SLP_S3#<1 3,21,28,29 ,30,32,34,35>

Reser ve CO DEC LDO for Codec.

+3VS_DVDD

12

1

1

C876

C877

2

2

0.1U_0402_16V4Z

R1342

C885

R1360

0.1U_0402_16V4Z

@

12

47_0402_5%

1 2

33_0402_5%

12

0.01U_0402_16V7K

MUTE_LED_CNTL

+3VS

EC_MUTE#

D15

CH751H-40PT_S OD323-2

delet e D16 , Com pal, SI 1/5

1 2

10K_0402_5%

+5VALW

1U_0402_6.3V6K

C881 10U_0805_10V4Z

12

R1346

12

R1349 0_0402_5%

R1350 10K_0402_5%

R1366

U58

1

2

3

G9191-475T1U_SOT23-5

HDA_B IT_CLK_CODEC

HDA_S DIN0_CODE C

HDA_S DOUT_CODEC

HD A_SYNC_CO DEC

HDA_R ST#_CODEC

C908

1 2

1 2

21

C892

4.7U_0603_6.3V6M

IN

OUT

GND

SHDN

BYP

12

5

4

2

1

12

R1443
0_0402_5%

1

0.1U_0402_16V4Z

2

B

U49

1

DVDD_CORE

9

DVDD

3

DVDD_IO

6

HDA_BITCLK

8

HDA_SDI

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

2

DMIC_CLK/GPIO1

4

DMIC0/GPIO2

46

DMIC1/GPIO0/SPDIF_OUT_1

48

SPDIF_OUT_0

47

EAPD

35

CAP-

36

CAP+

7

DVSS

33

AVSS

30

AVSS

26

AVSS

42

PVSS

49

DAP

92HD80B1X5NLGXYD38_QFN48_7X7

+VDDA _CODEC

1

@

C1295

C1294

2.2U_0805_16V4Z

2

AVDD
AVDD

PVDD
PVDD

SENSE_A
SENSE_B

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_or_F

HP1_PORT_B_L

HP1_PORT_B_R

PORT_C_L

PORT_C_R

VREFOUT_C

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

PORT_E_L

PORT_E_R

PORT_F_L

PORT_F_R

PC_BEEP

MONO_OUT

CAP2

VREFFILT

VREG

C

+AVDD _CODEC

R1442 0_0805_5%

12

+AVDD _CODEC +5VS

27
38

39
45

13

R1345 100K_0402_5%

14

C886 1000P_0402_50V7K@

MIC_EXTL

28

MIC_EXTR

29

+VREFOUT_EXTMIC

23

HP_OUTL

31

HP_OUTR

32

MIC_IN L

19

MIC_IN R MIC_IN _R

20

+VREFOUT _INTMIC

24

SPKL+

40

SPKL-

41

SPKR-

43

SPKR+

44

15
16

17
18

MONO_INR M ONO_IN

12

25

22

21

34

V-

37

2

1

C896

4.7U_0603_6.3V6M

R1339 0_0805_5%@

1

1

C879

C878

2

2

C897

1U_0402_6.3V6K

0.1U_0402_16V4Z

SENSEA

12

1 2

10U_0805_10V4Z

C888 2 .2U_0603_6.3V4Z
C889 2 .2U_0603_6.3V4Z

C890 2 .2U_0603_6.3V4Z
C891 2 .2U_0603_6.3V4Z

C893 0 .1U_0402_16V4Z

12

1

1 2

C898

C899

2

1U_0603_10V6K

10U_0805_10V4Z

1 2
1 2

1 2
1 2

2

1

1

2

12

1

C882

2

0.1U_0402_16V4Z

+AVDD _CODEC

MIC_SENSE<24>

+VDDA _CODEC

Reserv e COD EC LDO for Codec.

1

C884

C883

2

1U_0402_6.3V6K

10U_0805_10V4Z

MIC1

MIC_IN _L

R1352 100K_0402_5%

2

1

R1354

C895

0.1U_0402_16V4Z

10K_0402_5%

1 2

+AVDD _CODEC

R1363

10K_0402_5%

1 2

2N7002DW -7-F_SOT363-6

1 2

3

5

4

MIC1 <24>

+VREFOUT_EXTMIC <24>

HP_OUTL <24>
HP_OUTR <24>

MIC_IN _L <24>
MIC_IN _R <24>

+VREFOUT _INTMIC <24>

Inte rnal SPKR

+AVDD _CODEC

R1364

12

39.2K_0402_1%

Q84B

D

Ext MIC

HP Jack

Int MIC

+AVDD _CODEC

C894 0.1 U_0402_16V4Z

1 2

Q72B

12

R1361

2.49K_0402_1%

SENSEA

2

C743
1000P_0402_50V7K_X7R

1

for E SD

1 2

3

4

2N700 2DW-7-F_SOT363-6

PJSOT05C_SOT23

220P_0402_50V7K

R1351

10K_0402_5%

SB_SPKR

5

1

D37

2

3

SPKL+
SPKL­SPKR+
SPKR-

1

1

C904

C905
220P_0402_50V7K

2

2

C906

220P_0402_50V7K

SB_SPKR <11>

C900 1000P_04 02_50V7K

1 2

C901 1000P_04 02_50V7K

1 2

C902 1000P_04 02_50V7K

1 2

C903 1000P_04 02_50V7K

1 2

R1355 0_0603_5%

1 2

R1356 0_0603_5%

1 2

R1357 0_0603_5%

1 2

R1358 0_0603_5%

1 2

insta ll fo r ESD requ est, Comp al SI 1/19

E

1

D38

PJSOT05C_SOT23

2

3

1

1

C907

220P_0402_50V7K

2

2

92HD80 port define

Port A

Port B

Port C

Port D

Port E

Port F

DM0

GNDAGND

JSPK1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

E-T_3806K-F04N-03R_4P-T

CONN@

Ext MIC

Head phone

Int MIC

SPKR

X

X

Digital MIC

GNDA <24>

HP_DET#

HP de pop circuit

+5VALW

4 4

EC_MUTE#

2

A

HP_OUTL HP_OUTR

12

R1359
10K_0402_5%

@

61

Q72A

2N700 2DW-7-F_SOT363-6

+AVDD _CODEC

61

2

Q70A

@

2N700 2DW-7-F_SOT363-6

4

5

Q70B

@

3

2N7002DW-7-F_S OT363-6

61

2

Q71A

@

2N700 2DW-7-F_SOT363-6

4

5

Q71B

@

3

2N7002DW-7-F_S OT363-6

B

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HP_DET<24>

C

2N7002DW-7-F_SOT363-6

R1365

10K_0402_5%

2007/08/28 2009/09/03

1 2

HP_DET

2

Compal Secret Data

R1362

20K_0402_1%

61

Q84A

Deciphered Date

12

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet

Cod ec_ IDT9 2HD8 0

LA-61 61P

E

0.5

of

23 41T uesday, M ay 18, 2010

A

B

C

D

E

3

1

R1199

100K_0402_5%

1 2

R1200

560K_0402_5%

1 2

R1202

47K_0402_5%

1 2

chang e fro m 120 K to 47K, HP SI 1/28

EXT_MIC

+AVDD _CODEC

5

U17

1

P

IN+

O

3

IN-

G

2

LMV33 1IDCKRG4_SC70-5~D

4

MIC_SENSE <23>

+5VALW +5VALW

1 1

USB20_N1<14>
USB20_P1<14>

USB20_N3<14>

USB20_P3<14>
+5VALW
+5VALW

HP_DET<23>

USB20_N1

USB20_N3
USB20_P3

EXT_MIC
HP_DET

INT_MIC_1_2
INT_MIC_2_2

USB I/O connx2 , Aduio JACK
Card reader transfer conn

2 2

EXT_MIC EXT_MIC_1

3 3

12

C789 0.47U_0402_6.3V6K_X5R

L39 HLC 0603CSCCR11JT_0603

1 2

1

C790
68P_0402_50V8J

2

JUSB23

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 32

ACES_88242-3001_30P

CONN@

1 2

R1206 10K_0402_5%

USB20_N5
USB20_P5USB20_P1

USB20_N0
USB20_P0

SLP_S4

HP_OUTR
HP_OUTL

EXT_MICL_3

R1205 100K_0402_5%

+CODE C_REF

+AVDD _CODEC

1

C788

2

5

+

6

-

100P_0402_50V8J

USB20_N5 <14>
USB20_P5 <14>

USB20_N0 <14>
USB20_P0 <14>

SLP_S4 <30>

HP_OUTR <23>
HP_OUTL <23>

1 2

C787 15P_0402_50V8K

1 2

4

OUT

P

G

11

MIC1

7

U18B
TLV2464_TSSOP14

+5VALW+5VALW

+3VS

MIC1 <23>

To CODE-ext MIC input

+VREFOUT_EXTMIC<23>

To

CODE-ext MIC Bias

2.2K_0402_5%

1

C783

Place close to U18

+AVDD _CODEC

R1203

10K_0402_5%

R1204

10K_0402_5%

1U_0603_10V6K

+CODE C_REF

1 2

2

1

C7854.7U_0805_10V4Z

C7860.1U _0402_16V4Z

1

2

1 2

2

220P_0402_25V8J

C784

CHN20 2UPT_SC-70

AMP. FOR EXTERNAL MICROPHONE

3

2

R1201

+

-

D19

1

2

12

2

4

P

1

OUT

G

U18A
TLV2464_TSSOP14

11

@

1 2

+VREFOUT _INTMIC<23>

INT_MIC_1_4

R1210

R1209

3K_0402_5%

INT_MIC_2_2
INT_MIC_1_2

+AVDD _CODEC

4 4

R1214

3K_0402_5%

@

@

12

1

2

A

R1215

3K_0402_5%

@

C802
1U_0603_16V7_X7R

3K_0402_5%

1 2

1 2

L41
HLC06 03CSCCR10JT_0603

INT_MIC_1_3

12

1 2

C798 0.068U_0603_16V7K

1 2

1 2

10K_0402_5%

1

C801
68P_0402_50V8J

2

R1216

+CODE C_REF

1

C795

2

B

100P_0402_50V8J

@

1 2

C792 100P_0402_50V8J

1 2

R1208 100K_0402_5%

+AVDD _CODEC

1

C796

4

2

+

OUT

-

11

0.1U_0402_16V4Z

P

14

G

U18D
TLV2464_TSSOP14

MIC_IN _L<23>

12

13

AMP. FOR INTERNAL MICROPHONE

+AVDD _CODEC

3K_0402_5%

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

INT_MIC_2_2

R1211

@

@

2009/08/03 2009/09/03

12

1

2

R1212

12

3K_0402_5%

@

C799
1U_0603_16V6K_X5R

Compal Secret Data

Deciphered Date

1 2

C797 0.068U_0603_16V7K

INT_MIC_2_3

L40
HLC06 03CSCCR10JT_0603

1 2

D

R1213
10K_0402_5%

1 2

1

C800
68P_0402_50V8J

2

INT_MIC_2_4

Title

Size Doc ument Number Re v

Date: Sheet

C791 100P_0402_50V8J

1 2

R1207 100K_0402_5%

+CODE C_REF

+AVDD _CODEC

1

C793

2

100P_0402_50V8J

10

9

+

-

1

C794

4

2

P

8

OUT

TLV2464_TSSOP14

G

U18C

11

0.1U_0402_16V4Z

MIC_IN _R<23>

Compal Electronics, Inc.

AMP & Audio Jack

LA-6161P

E

0.5

of

24 41T uesday, M ay 18, 2010

For EMI

INT_KBD CONN.

JKB1

34

GND2

33

GND1

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

HRS_F H28-60(30)SB-1SH(86)

CONN@

+3VS

1

C803

2

1 2

KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9

KSO[0.. 11]<28>

KSI [0..7]<28>

KSO[0.. 11]

KSI [0..7]

0.1U_0402_16V4Z

R1217 470_0402_5%

20mil

+3VS

CAPS_LED#<20>

KB LED power

KSO11

KSO0

KSO2

KSO5

KSI_D_14

KSI_D_8

KSI_D_12

KSI_D_10

KSI_D_0

KSI_D_4

KSI_D_2

KSI_D_1

KSI_D_3

KSO3

KSO8

KSO4

KSO7

KSO6

KSO10

KSO1

KSI_D_5

KSI_D_6

KSI7

KSI_D_13

KSI_D_11

KSI_D_9

KSO9

Pin 1

C620 100P_0402_50V8J@

1 2

C656 100P_0402_50V8J@

1 2

C624 100P_0402_50V8J@

1 2

C621 100P_0402_50V8J@

1 2

C622 100P_0402_50V8J@

1 2

C625 100P_0402_50V8J@

1 2

C626 100P_0402_50V8J@

1 2

C627 100P_0402_50V8J@

1 2

C630 100P_0402_50V8J@

1 2

C629 100P_0402_50V8J@

1 2

C631 100P_0402_50V8J@

1 2

C632 100P_0402_50V8J@

1 2

C633 100P_0402_50V8J@

1 2

C634 100P_0402_50V8J@

1 2

C641 100P_0402_50V8J@

1 2

C637 100P_0402_50V8J@

1 2

C657 100P_0402_50V8J@

1 2

C638 100P_0402_50V8J@

1 2

C639 100P_0402_50V8J@

1 2

C640 100P_0402_50V8J@

1 2

C660 100P_0402_50V8J@

1 2

C642 100P_0402_50V8J@

1 2

C659 100P_0402_50V8J@

1 2

C654 100P_0402_50V8J@

1 2

C744 100P_0402_50V8J@

1 2

C745 100P_0402_50V8J@

1 2

C724 100P_0402_50V8J@

1 2

Pin1 reserve , so net name is reserve

or Fossil down contact

f

Power BTN/LED and Lid switch BD

JPWR 1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051CON N@

LID_SW#
STB_LED

AMBER_BATLED# <28>

AQUAWHITE_BATLED# <11,28>

add 0 .1U f or EM I req uest, Com pal S I 1/19

1

C1334

0.1U_0402_16V4Z

2

+3VL

LID_SW# <18,28>
STB_LED <28>

+3VL

12

R1218

100K_0402_5%

1

C805

1U_0603_10V4Z

2

ON/OFF BTN_KBC#

D20

D21

KSI_D_0

1

DAP202U_SOT323-3
D23

1

DAP202U_SOT323-3
D25

1

DAP202U_SOT323-3

1 2

R1219 100K_0402_5%@

2

KSI_D_8

3

KSI_D_1

2

KSI_D_9

3

KSI_D_2

2

KSI_D_10

3

ON/OFF BTN# <13,28>

2009/08/03 2009/09/03

KSI0

KSI1

KSI2

ON/OFF BTN_KBC# <28>

D28

@

21

CH751 H-40_SC76

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW

KSI3

1

KSI4

1

KSI5

1

KSI6

1

12/09 HP

Compal Secret Data

KSI_D_3

2

KSI_D_11

3

DAP202U_SOT323-3
D22

KSI_D_4

2

KSI_D_12

3

DAP202U_SOT323-3
D24

KSI_D_5

2

KSI_D_13

3

DAP202U_SOT323-3
D26

KSI_D_6

2

KSI_D_14

3

DAP202U_SOT323-3

Deciphered Date

T/P BOARD.

+5VS

TP_CLK<28>

TP_DATA<28>

3

Title

Size Doc ument Number Re v

LA-6161P

Date: Sheet of

JTPB1

1
2
3
4

5
6

CONN@

2

D27
PACD N042Y3R_SOT23-3

1

ACES_87151-04051_4P

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

+5VS

1

C804

0.1U_0402_16V4Z

2

25 41T uesday, M ay 18, 2010

0.5

5

4

3

2

1

@

+3VAUX_BT

USB20_N8_R

D D

C C

4

VIN

3

IO2

CM1293A-02SR_SOT143-4

GND

USB20_P8_R

2

IO1

1

For E SD

BT_OFF<14>

ACES_87213-0800G_8P

CONN@

JBT1

1
2
3
4
5
6
7
8

12

R1222
10K_0402_5%

1 2

220K_0402_1%

USB20_P8_R
USB20_N8_R

R1223

R1220 0_0402_5%
R1221 0_0402_5%

0.1U_0402_10V6K

1

2

Q63
SI2301BDS_SOT23

S

G

2

C1324

@

2N7002_SOT23-3

12
12

D

13

R1477
470_0402_5%

2

Q89

+3VAUX_BT

12

13

D

G

S

1

2

+3VAUX_BT+3VALW

C8140.1U_0402_16V4Z

USB20_P8 <14>
USB20_N8 <14>

BT_LED <20>

C8152.2U _0805_10V5R

1

2

D29

BT(SoftBreeze) Connector

B B

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/03 2009/09/03

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

USB & BT Connector

LA-6161P

26 41Tuesday, May 18, 2010

1

0.5

5

D D

4

3

2

1

C C

for R F

BIOS ROM(4MB)

4MB SPI ROM

+3VL

SPI_CS0#<28>

SPI_CLK<28>

SPI_SI<28>

1 2

B B

SPI_CLK_JP SPI_CLK

SPI_S I_JP SPI_SI

4MB SPI
ROM

A A

R633 0_0402_5%

1 2

R634 0_0402_5%

1 2

R635 0_0402_5%

1 2

R636 0_0402_5%

1 2

R637 0_0402_5%

@

47P_0402_50V8J

20mils

+3VL

05/10 Dele te SP I Soc ket f or MV.

0.1U_0402_16V4Z

C1323

1

2

1 2

R629 3.3K_0402_5%

SPI_H OLD#_1SPI_H OLD#_0

SPI_CS0#SPI_CS0#_JP

SPI_SO_R0SPI_SO_JP

20mil s

+3VL

+3VL_SPI PW R

1

20mils

C581

2

SPI_WP#

SPI_H OLD#_1

1 2

R631 3.3K_0402_5%

SPI_CS0#

SPI_CLK

SPI_WP#

25mA

SPI ROM SCKET

U35

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

MX25L3205DM2I-12G

2nd Source :
WINB OND 32 M W25Q32BV SSIG
EON 32M EN 25F32-100H IP

4

VSS

SPI_SO_R0 SPI_SOSPI_SI

2

Q

@

1 2

R632 0_0402_5%

1 2

R630 33_0402_5%

SPI_CLK

12

R627

10_0402_5%@

1

C582

4.7P_0402_50V8C

@

2

SPI_SO <28>

LPC Debug Port

39P_0402_50V8J

CLK_P CI_DB

1

C655

@

2

CLK_P CI_DB<14>

LPC_LFRAME#<11,28>
SIRQ<11,28>
PLT_RST#<4,14,21,22>
PCI_S ERR#<14,28>
LPC_LAD0<11,28>
LPC_LAD1<11,28>
LPC_LAD2<11,28>
LPC_LAD3<11,28>

8051TX<28>
8051RX<28>
8051_RECOVER #<28>
DEBUG_KBCRST<33>

SPI_CLK_JP<22>
SPI_CS0#_JP<22>
SPI_S I_JP<22>
SPI_SO_JP<22>
SPI_HOLD#_0<22>
SPI_CS1#<28>

8051_RECOVER #

CLK_P CI_DB

SIRQ

8051_RECOVER #
DEBUG_KBCR ST
SPI_CLK_JP
SPI_CS0#_JP
SPI_S I_JP
SPI_SO_JP
SPI_H OLD#_0

R628 100K_0402_5%

1 2

B+_DEBUG

JP31

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

CONN@

+3VL

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/03 2009/09/03

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

BIOS ROM/SW LPC DEBUG

LA-6161P

1

27 41T uesday, M ay 18, 2010

0.5

1

100K _0402_5%@

ROM _CS# 0

SPI _SI<27>

SPI _CS0#<27>

SPI _SO< 27>

KSI 0

KSI 1

PMC<32>

12

1U_0 603_1 0V4Z

C8 48

LPC _LFRA ME#< 11,27>

R1 242

PM _CLK RUN#<1 3>

CL K_PCI _KBC<14>

RU NSC I_E C#<14>

T136
PA D

NP CI_RS T#<14>

+3VL

12

1 2

R1 245 0_04 02_5%

1 2

R1 246 0_04 02_5%

1 2

R1 247 0_04 02_5%

KSO [0.. 11]<25>

KS I[0. .7]<25>

TP_ CLK<25>

TP_DA TA< 25>

SI RQ< 11,27>

LPC _LAD3<11 ,27>
LPC _LAD2<11 ,27>
LPC _LAD1<11 ,27>
LPC _LAD0<11 ,27>

+V CC0

OC P_A_ IN

+R TCVC C

1

2

0.1U _0402 _16V4Z

ROM _DATOU T

ROM _CS# 0

ROM _DAT IN

TP _CLK
TP_DAT A
SP_ CLK
SP _DATA

CLK _PCI_ KBC
RU NSC I_E C#

CR Y1
CR Y2

BAT_A LARM

ROM _CLK

1 2

R1 263 0_0 402_5%

R1 267 0_0 402_5%
R1 270 300 _0402_5%

R1 273 300 _0402_5%

12

1 2

1 2
1 2

R1 276
0_04 02_5%

+V CC0

1

C8 49

0.1U _0402 _16V4Z

2

ROM _CS1 #

AD C1
AD C

C8 31

KS O0
KS O1
KS O2
KS O3
KS O4
KS O5
KS O6
KS O7
KS O8
KS O9
KS O10
KS O11

KSI 0
KSI 1
KSI 2
KSI 3
KSI 4
KSI 5
KSI 6
KSI 7

0.1U _0402 _16V4Z

1

C8 32

2

128
127

97
96
95
94

21
20
19
18
17
16
13
12
10

9
8
7
6
5

29
28
27
26
25
24
23
22

35
36
61
62
66
67

55
57
54
76

51
50
48
46

52
53

70
71

68

1
2

3
30
31
32
33
34
43
44

+3VL

KSI 3

R1 39510K _0402 _5%

12

KSI 2

R1 39610K _0402 _5%

12

KSI 1

R1 39710K _0402 _5%

A A

B B

+5VS

R5 25 10K_04 02_5%

1 2

R5 26 10K_04 02_5%

1 2

R5 27 10K_04 02_5%@

1 2

R5 28 10K_04 02_5%@

1 2

C C

D D

Compal , SI 1/18

22P _0402_50 V8J

Y5

C8 43

1

2

R1 255

@

C8 40

@

R1 39810K _0402 _5%

R1 39910K _0402 _5%
R1 40010K _0402 _5%
R1 40110K _0402 _5%
R1 40210K _0402 _5%

4

1

IN

OUT

NC3NC

2

CLK _PCI_ KBC

10_0 402_5%

12

4.7P _040 2_50V8C

1

2

12

KSI 0

12

KSI 7

12

KSI 6

12

KSI 5

12

KSI 4

12

T141
PA D

T142
PA D

BIOS r equest. 11/20 Compal

TP _CLK

TP_DAT A

SP_ CLK

SP _DATA

22P _0402_50 V8J

KBC _SPI _CS1 #_R<11 >

C8 44

1

2

32.7 68KH Z 1TJ S125 DJ4A420P

1

KBC _SPI _SI_R<11 >

KBC _SPI _CS0 #_R<11 >

KBC _SPI _SO<1 1>

KBC _SPI _CLK_R<11>

SPI _CLK<27>

SPI _CS1#<27>

MC1 _DISA BLE<22>

OC P_A_ IN<38>

R1 279

0_04 02_5%@

2

07 /01 u pd ate

0.1U _0402 _16V4Z

1

1

1

C8 34

C8 33

2

0.1U _0402 _16V4Z

U2 1

FLDATAOUT
HSTDATAOUT/GPIO45
FLCS0#
HSTCS0#/GPIO44
FLDATAIN
HSTDATAIN/GPIO43

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#

LAD[3]
LAD[2]
LAD[1]
LAD[0]

LFRAME#
LRESET#

XTAL1
XTAL2

VCC0

Alarm [CKT#2]/GPIO36
HSTCLK/GPIO41
FLCLK
GPIO39
HSTCS1#/GPIO42
FLCS1#
GPIO38
GPIO37
ADC1/GPIO46
ADC_TO_PWM_IN

KBC 1098- NU_VTQ FP128_14X 14

ROM _CLK

C8 39

1

4.7P _040 2_50V8C@

2

C8 35

2

2

4.7U _0805 _10V4Z

Pow er Mgm t/S IRQ

LPC
Bus

2

Key boa rd/ Mou se Int erf ace

1

2

+3VL

12

R1 238

0_06 03_5%

1

C8 36

0.1U _0402 _16V4Z

2

14

106

119

49

VCC1

VCC139VCC158VCC184VCC1

VCC1

VCC2

ADP_PRES[CKT#2]/GPIO27/WK_SE05

Gen era l P urp ose I/ O I nte rface

SMSC_1098-NU_TQFP-128P

Access Bus I nterface

72

AGND

VSS11VSS37VSS47VSS56VSS

VSS82VSS

104

117

R1 275

0_04 02_5%

AVSS

45

12

1 2

R1 240 0_0 402_5%

1

C8 37

0.1U _0402 _16V4Z

2

CFETA/OUT7/nSMI

OUT10/PWM0

PWM_CHRGCTL

GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

GPIO24/KSO16

GPIO26/KSO17

32KHZ_OUT/GPIO22/WK_SE01

RESET_OUT#/GPIO06

ADC_TO_PWM_OUT/GPIO19

CFETB/GPIO10

PWR_LED#/8051TX

Mis cel lan eous

FDD_LED#/8051RX

AC[CKT#2]/GPIO23

ADC2/GPIO40

12/10 HP

3

+3VS

15

CAP

93

GPIO28

98

GPIO29

99

GPIO30

100

GPIO31

126

GPIO32

124

OUT0/(SCI)

125

OUT1/IRQ8#

123
122

OUT8/KBRST

121

OUT9/PWM2

120
118

107

GPIO01

79

GPIO02

80

GPIO03

81
83

85
86

GPIO08/RXD

87

GPIO09/TXD

88
89
90
91
92
101
102

103
105
4
74

111

AB1A_DATA

112

AB1A_CLK

109

AB1B_DATA

110

AB1B_CLK

73

GPIO25

108
59

NC_CLOCKI

75
60
78

PWRGD

77

VCC1_RST#

38

69

TEST PIN

BAT_LED#

Q/GPIO33

SP I_R ECOV ERY _R

116
113
115
114

41
42
65
64

GPIO34

63

GPIO35

40

AVCC

R1 486 0_ 0402_5%

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

L

C8 38 4.7 U_080 5_10V6K

1 2

T143P AD

MUT E_LE D_CNT L_R M UTE_L ED_CNT L

KB RST#

CH75 1H-4 0PT_S OD323-2

APP _BU TTON_1_R

CPU _SV_ ID_D ET
SLP _S3#

PM_ RSMRST#
CRA CK_B GA
BD _ID

AB 2A_DATA
AB2 A_CLK

PWR BTN_ OUT#

SMB _EC_ DA1
SMB _EC_ CK1

AB 1B_DATA
AB1 B_CLK

32K _CLK
PG D_I N
PW R_ GD

TEST

AD C2

LI D_SW #

C8 45220 0P_0402 _25V7K

12

C8 46220 0P_0402 _25V7K

12

C8 47220 0P_0402 _25V7K

12

R1 248 0 _0402_ 5%

D3 1

R1 249 0_ 0402_5%

1 2

R1 250 0_ 0402_5%

1 2

R1 251 0_ 0402_5%

1 2

R1 252 0_ 0402_5%

1 2

APP _BU TTON_2_R

CAP S_LO CK_K BC_R

R1 257 0_ 0402_5%

1 2

R2 48 0_040 2_5%

1 2

R1 261 1K_ 0402_5%

1 2

1 2

R1 503 0_ 0402_5%@

R1 262 100 K_0402_5 %

1 2

R1 264 30 0_040 2_5%

1 2

R1 268 0_ 0402_5%

1 2

1 2

C1 303

0.1U _0402 _10V6K

AD C

AD C1

AD C2

Issued Date

SUS _PWR _ACK < 13>
AC_ PRES ENT <13>

1 2

PC I_SE RR# <14 ,27>

KB C_PW R_ON < 33>
AQU AWHI TE_BA TLED# <11 ,25>

21

KB_ RST# <14>
FAN _PWM <4>
BAT_ PWM_OUT < 32>
CH GCTR L <32>

R1 290 0_ 0402_5%

1 2

ON/ OFFB TN_K BC# <25>

SLP _S3# <13 ,21,2 3,29, 30,32,3 4,35>
8051 _REC OVER# < 27>

PM_RS MRST# <13 >
CRA CK_B GA <8,16 >

CAP _DAT <12>
CAP _CLK <12 >
CEL LS <32>
EC_ MUTE# <23>
ADP _DET# < 38>
BAT _ID# <31>
GATEA 20 <14>

R1 253 0_ 0402_5%

1 2

ADP _PRES <21,31 ,32,38>

SMB _EC_DA 1 <31>
SMB _EC_CK 1 <31>

R1 307 0 _0402_ 5%

1 2

R1 308 0 _0402_ 5%

1 2

8051TX

+3VL

1 2

R1 485

@

CAP _CLK

C8 41

1

@

2

2009/08/03 2009/09/03

ADP _EN <38>
PG D_IN < 13,37>
PW R_G D < 29>
VC C1_ PWRG D <33,38>
OC P <38>

02/23

SP I_RE COVE RY <22>
AMB ER_BAT LED# <25>
8051TX <27>
8051RX <27>

+3VL

AC_ ADP_ PRES <3 1,32>
ADP _A_I D < 38>

LI D_SW # <18,25>

WL_ BLUE _BTNW L_BL UE_B TN_R

0_04 02_5%

SPI _CLK

4.7P _040 2_50V8C

C8 42

@

Compal Secret Data

CAP S_LO CK_KB C

4.7P _040 2_50V8C

1

2

Deciphered Date

4

APP _BUTT ON_1

APP _BUTT ON_2

PG D_I N

PM_ RSMRST#

4

compal , SI 12/24

WL_ BLUE _BTN

MUT E_LE D_CNTL <23>

APP _BUTTO N_1 <20>

ON /OFF BTN# <1 3,25>

APP _BUTTON _2 <20>

CAP S_LO CK_KBC <20>

APP _BUTT ON_1
APP _BUTT ON_2

for ESD

WL_ BLUE _BTN

APP _BUTT ON_1

APP _BUTT ON_2

LI D_SW #

CPU _SV_ ID_D ET

L

8051TX ST B_LED

WL_ BLUE _BTN <20>

R1 306 0_ 0402_5%

1 2

@

R1 277 10K _0402_5%

1 2

R1 278 10 K_04 02_5%

1 2

Title

Size D ocum ent N umber Re v

Da te: She et o f

5

R1 489 10 0K_0 402_5%
R1 490 10 0K_0 402_5%
R1 491 10 0K_0 402_5%

C1 329 0. 1U_04 02_16 V4Z @

C1 330 0. 1U_04 02_16 V4Z@

C1 331 0.1 U_040 2_16V4Z@

C1 335 0.1U _0402 _16V4Z

add 0. 1U fo r EMI request, Compal SI 1/19

R1 258 10 0K_0 402_5%@

R1 259 10 0K_0 402_5%@

1 2

1 2

1 2

1 2

1 2

1 2

12
12
12

+3VL

CP U Type Det ect : Hi gh --> SV , Lo w-- >LV

STB _LED <25>

Compal 12/24

KB RST#

R1 265 10K _0402_5%

VC C1_ PWR GD

R1 266 10K _0402_5%

CRA CK_B GA

R1 269 10K _0402_5%

BD _ID

R1 272 10K _0402_5%

KB C_P WR_O N

R1 274 10 K_0402 _5%

@

1 2

1 2

1 2

1 2

1 2

RP 11

4.7K _080 4_8P4R_ 5%

SMB _EC_ CK1
SMB _EC_ DA1
AB1 B_CLK
AB 1B_DATA

1 8
2 7
3 6
4 5

+3VL

+3VL

Compal Electronics, Inc.

KBC1098

LA -61 61P

5

28 41T uesd ay, M ay 1 8, 20 10

+3VL

0. 5

1

1.8V S_POK<3 5>

+5VS

A A

+1.5 VS_C PU_V DDQ

+0.75 VS

SLP _S3#<13,2 1,23, 28,30 ,32,34,3 5>

R1 294 34K _0402_1%

+3VS

+1.5V S

R1 295 75K _0402_1 %

R1 296 34K _0402_1 %

2

1 2

R1 281 3.3 K_040 2_5%

1 2

R1 285 76 .8K_0 402_1%

1 2

R1 288 11. 5K_04 02_1%

1 2

R1 291 3.3 K_040 2_5%

CH75 1H-4 0PT_S OD323-2

1 2

1 2

1 2

12

R1 299

34.8 K_040 2_1%

3

R1 280

1 2

1M_ 0402_1%

+5V ALW

8

D3 3

21

3300 P_0402_ 25V7K

1

C8 52

2

R1 286 10K _0402_5%

2VR EF_51 125

1

C8 51

3300 P_0402_ 25V7K

2

1 2

2VR EF_3 93

1 2

R1 287 34. 8K_04 02_1%

1 2

R1 289 49. 9K_04 02_1%

R1 297 10K _0402_5%

1 2

2VR EF_39 3

2VR EF_3 93

3

+

2

-

1

C8 50
1000 P_0402_ 50V7K

2

1 2

1M_ 0402_1%

5

+

6

-

U2 3A

P

G

LM3 93DT_SO8

4

R1 292

+5V ALW

8

4

1

O

U2 3B

P

7

O

G

LM3 93DT_SO8

4

1 2

SHO RT P ADS

J1

VCC P_POK<34>

+3VS

12

R1 282
10K _0402_5%

VC CP_E N <34>

U2 5

1

2

MC7 4VHC1 G08D FT2G_S C70-5

+3V ALW

IN1

IN2

5

6

7

8

Intel S3 power reduction circuit for Calpella. 11/09

SLP _S3#

12

R1 283

0_04 02_5%@

5

VCC

4

OUT

GND

3

12

R1 293

4.99 K_04 02_1%

12

R1 298

2.49 K_04 02_1%

PW R_G D <28>

VTT PWRG OOD <4>

12

R1 284

8.2K _0402 _5%

+3V ALW

5

VCC

IN1

OUT

IN2

GND

3

U2 4

4

MC7 4VHC1 G08D FT2G_S C70-5

VC CP_1. 5VSP WRG D <4>

1

2

B B

H1
HOL EA

1

CPU supportWWAN Card STANDOFF

H3
HOL EA

1

H4
HOL EA

1

H5
HOL EA

1

H6
HOL EA

1

WWLAN Card STANDOFF

H2
HOL EA

1

ZZZ

LA-6161P_PCB

C C

D D

H9
HOL EA

H1 6
HOL EA

H1 7
HOL EA

H1 0
HOL EA

1

H1 9
HOL EA

1

H1 8
HOL EA

1

1

FM1

1

H1 1

H1 2

HOL EA

1

1

FM2

FM3

1

1

H1 3

HOL EA

HOL EA

1

1

1

FM4

1

H1 4
HOL EA

1

H1 5
HOL EA

1

H2 0
HOL EA

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

3

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

2009/08/03 2009/09/03

Compal Secret Data

Deciphered Date

6

Title

Size D ocum ent N umber Re v

Da te: She et o f

7

Compal Electronics, Inc.

POK CKT

LA -61 61P

29 41T uesd ay, M ay 1 8, 20 10

8

0. 5

A

B

C

D

E

+3VALW to +3VS Transfer

B+

12

R1322

1 1

330K_0402_5%

61

SLP_S3

2N7002DW -7-F_SOT363-6

Q30A

2

SI7326DN-T1-E3_PAK1212-8

1

C859
10U_0805_10V4Z

2

R1323 0_0402_5%

RU NON

12

R1324
470_0402_5%

1

C862

0.01U_0402_25V7K

2

U28

4

1 2

Compa l, SI 1/11

+3VS+3VALW

1
2
35

1

1

2

2

C861

C860

10U_0805_10V4Z

0.1U_0402_16V4Z

+5VALW to +5VS Transfer

SI7326DN-T1-E3_PAK1212-8

U29

2 2

1

C863
10U_0805_10V4M

2

4

RU NON

+5VS+5VALW

1
2
35

1

2

1

C865
10U_0805_10V4Z

2

C864

0.1U_0402_16V4Z

+1.5V +1.5VS_ CPU_VDDQ

SI7326DN-T1-E3_PAK1212-8

U45

C1023

0.1U_0402_16V4Z

1

2

+1.5VS _CPU_VDDQ

Q52B

SLP_S3

2N7002DW -7-F_SOT363-6

0_0402_5%

RU NON

5

R1441

12

R1440

220_0402_5%

3

4

4

12

1
2
35

1

C505

0.01U_0402_16V7K

@

2

Add C6 26 ,C66 4 close t o JDI MA1;
C65 6, C65 7 cl ose to JDIMB1.

L

+1.5V

C1024 0.1U_0402_16V4Z

C1022

0.1U_0402_16V4Z

1

2

1 2

C1025 0.1U_0402_16V4Z

1 2

C1026 0.1U_0402_16V4Z

1 2

C1027 0.1U_0402_16V4Z

1 2

+0.75VS

SLP_S3

2

+1.5VS _CPU_VDDQ

12

R693

22_0402_5%

61

Q85A

2N7002DW-7-F_SOT363-6

Intel S3 power reduction circuit for Calpella. 11/09

+1.5V to +1.5VS Transfer

SI7326DN-T1-E3_PAK1212-8

Q64

@

@

0.1U_0402_16V7K

@

C866

10U_0805_6.3V4K

C867

1

1

R1327

2

3 3

2

@

1 2

0_0402_5%

RU NON

+1.5VS+1.5V

1
2
35

0.1U_0402_16V7K
C868

C869

10U_0805_6.3V4K

1

4

1

2

2

2 1

PAD-OP EN 2x2m

+1.5VS+1.5VS _CPU_VDDQ

J4

discharge circuit-2

+VCCP +GFX_CORE +1.5V

12

R1473

470_0402_5%

61

SLP_S3 SLP_S3

Q88A

2

2N7002DW-7-F_SOT363-6

2N7002DW -7-F_SOT363-6

Q88B

5

12

R1474

470_0402_5%

3

4

SLP_S3

12

R1475

470_0402_5%

3

Q86B
2N700 2DWH 2N SOT363-6

5

4

SLP_S4<24>

SLP_S4

SLP_S4#<13,36>

2N7002DW-7-F_SOT363-6

Discharge circuit-1

+1.8VS

12

R1328

470_0402_5%

61

Q15A
TR 2N 7002DW-7-F 2N SOT-363

4 4

2

+3VS +5VS

12

R1329

470_0402_5%

61

SLP_S3 SLP_S3SLP_S3

Q9A

2

2N7002DW -7-F_SOT363-6

2N7002DW-7-F_SOT363-6

Q9B

12

R1330

470_0402_5%

3

5

4

2N7002DW-7-F_SOT363-6

SLP_S3

Q7B

+1.5VS

12

R1331

470_0402_5%

3

5

4

SLP_S3#<1 3,21,23,28 ,29,32,34,35>

2N7002DW-7-F_SOT363-6

SLP_S3

Q85B

5

Q30B

5

+3VL

12

R1444
100K_0402_5%

3

4

+3VL

12

3

4

R1326
100K_0402_5%

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/08/03 2009/09/03

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

D

Date: Sheet of

Compal Electronics, Inc.

DC/DC Circuits

LA-6161P

E

30 41T uesday, M ay 18, 2010

0.5

A

B

C

D

12

CPU

PC 11

0.1 U_0603_25V 7K

VIN

B++ 51125_PWR

PD1 2

VIN

1SS 355_SOD323-2

PD7

2 1

B+_ DEBUG

12

12

BATT

PR 1

@15K _0402_5%

CH7 51H-40 PT_SOD323-2

B+_DEBUG

PD2 2

1SS 355_SOD323-2

PR2 3

100_080 5_5%

1 2

0.1U _0603_50V7 K

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

2VR EF_51125

PR2

12

470K_04 02_1%

1 2

3

+

2

-

PC 12

1000P _0402_50V7K

VL

8

P

O

PU1 03A

G

LM3 93DR_SO8

4

1

12

PH1
100 K_0402_1%_T SM0B104F4251 RZ

53.6 K_0603_1%

2VR EF_51125

12

12

75K_040 2_1%

21K_0 402_1%

PR 10

PR5

1 2

1 2

PR7

12

PR 15

150K_ 0402_1%

12

PC1 5

PR 3

PR3 7

0_0402_ 5%

1 2

PD8
RLZ 27V

2 1

12

VL

EN0 < 34>

1 2

13

2

G

D

PQ4
SSM3 K7002FU _SC70-3

S

100K_ 0402_5%

PC N1

6

1 1

2 2

PC N2
ACES _51976-00571 -001

GND
GND

3 3

4 4

GND
GND

ACES _87302-0441

1

1

EC_ SMD

2

2

EC_ SMC

3

3

4

4

5

5

6
7

5
4

4

3

3

2

2

1

1

12

2

3

PC 5

@10 0P_0402_50V8 J

1

PD 5

PJS OT24CH_SOT 23-3

3

1

PD 6

PJS OT24CH_SOT 23-3

A DPIN

2

3

PL3

1 2

1 2

PL4

1000P _0402_50V7K

SMB_ EC_DA1<29>

SMB_ EC_CK1 <29>

+3VL

PD1
@PJ SOT24C_SOT23 -3

1

VMB

HCB2 012KF-121 T50_0805

12

@10 0P_0402_50V8 J

PR9
100_040 2_5%

SMB_ EC_DA1

1

2

3

PD 4

HCB2 012KF-121 T50_0805

12

PC 6

BAV9 9WT1G_SC7 0-3

+3VL

12

PR 4 1K_040 2_1%

1 2

PR 6 210K_0 402_1%

2

BAT _ID#<29 >

1

PD 2

2

3

BAV9 9WT1G_SC7 0-3

12

PC 8

@10 0P_0402_50V8 J

12

PR 8

100_0 402_5%

SMB_ EC_CK1

1

PD 3

2

3

12

PC 9

BAV9 9WT1G_SC7 0-3

12

BATT_1

12

PC 7

PQ3

SSM3 K7002FU _SC70-3

ADP _SIGNAL <39>

12

PC 2

PC 1

100 P_0402_50V8J

0.0 1U_0402_50 V7K

13

D

2

G

S

1000P _0402_50V7K

PR1 1

12

PR 14

4

PL2

HCB2 012KF-121 T50_0805

1 2

PL1

HCB2 012KF-121 T50_0805

1 2

1
2
3 6

470K_04 02_5%

12

12

470K_ 0402_5%

PR 12

61

2

+3VL

1

5

PU1

74L VC1G14GW_ SOT353-5

P

NC

A2Y

G

3

12

PC 10

@10 0P_0402_50V8 J

PC 3

100 P_0402_50V8J

BATT

PQ1
AO4407A L_SO8

8
7

5

4

4.7 K_0402_5%

PQ2A
2N7 002KDW H-2N_SOT 363-6

+3VL

12

PR1 3

220K_04 02_5%

34

PQ2B

2N7 002KDW H-2N_SOT3 63-6

12

PC 4

<22 ,29,33>

ADP_ PRES

5

<29,33>

AC_ ADP_PR ES

1000P _0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/10 2009/09/03

Compal Secret Data

Deciphered Date

C

Title

Size Do cum ent Num ber R ev

Cu stom

Da te: Sh eet o f

Compal Electronics, Inc.

DCIN/BATT/CPU OTP

LA-6161P

D

31 40Tu esday, May 1 8, 201 0

A

VI N

PQ100
AO4407L _SO8

1
2
3 6

PC1 00

0.1U _0603_25V 7K

1 1

ADP_ EN#

2 2

P2

1 2

PR100

200K_04 02_5%

1 2

12

PR1 24

200K_ 0402_1%

1 2

PR1 27

12

0_0402_ 5%

PR1 31

41. 2K_0402_1%

3 3

VI N

4

12

PR1 05

1 2

PR1 21

255K_04 02_1%

5

+

6

-

2VREF_51125

VL

12

PR1 23

76. 8K_0402_1%

12

PR1 29

10K _0603_0.1%

3

+

2

-

P2

8
7

5

150K_ 0402_5%

SSM3 K7002FU _SC70-3

P2BATT

PR1 35

100K_04 02_1%

PR1 36 10 0K_0402_1%

12

PR1 41

24.3 K_0402_1%

8

P

7

O

G

PU1 02B
LM3 93DR_SO8

4

1 2

PR1 19

604K_04 02_1%

12

PC1 24

8

0.1 U_0402_10V 7K

PU1 02A

P

1

O

G

LM3 93DR_SO8

4

8
7

5

12

12

+3VL

PQ101
AO4407A L_SO8

4

1 2

PR1 02

200K_04 02_5%

12

PR103
150K_04 02_5%

13

D

PQ103

S

PR1 42

1M_0402 _5%

1 2

5

+

6

-

12

PR1 40

23.7K _0402_1%

2

G

8

P

G

LM3 93DR_SO8

4

BAT_PW M_OUT<29>

AC Detector
High 13.277

12

Low 10.770

PR1 25

22K_040 2_5%

Charge Detector
High 17.614
Low 17.201

+3VL

12

PR1 30

1
2
36

O

PU1 03B

22K_0 402_1%

P4

100K_04 02_5%

7

PR1 43

1 2

PR111

422K_04 02_1%

1U_ 0603_6.3V6M

ADP_PRES<22,29,32>

12

+3VL

VL

<14,22,29,30,31,35>

SLP_S3#

PC1 11

1U_ 0603_6.3V6M

1 2

PR1 10

12

12

PC116

PR1 12

1M_0402 _1%

AC_ADP_PRES<29,32>

1 2

56K_040 2_1%

12

453K_0 402_1%

43.2K _0402_1%

IADAPT<39>

2VREF_51125

CH GCTRL

B+

4 4

12

12

1 2

2200P _0402_50V7K

PC1 29 68P_0 402_50V8J

PC1 31

PC1 30 0.1U _0402_25V6

12/2 For RF request

12

12

1 2

PC1 34 68P_0 402_50V8J

PC1 332 200P_0402_5 0V7K

PC1 32 0. 1U_0402 _25V6

A

12

1 2

68P _0402_50V8J

PC1 37

PC1 35 0.1U _0402_25V6

12

12

68P _0402_50V8J

2200P _0402_50V7K

PC1 40

PC1 36

12

1 2

0.1 U_0402_25V 6

2200P _0402_50V7K

PC1 38

PC1 39

PR1 01

PR1 08

0_0402_ 5%

1 2

PR1 13

B

12

PC1 07

0.01 U_0402_16V 7K

BQ2 4740VREF

+3VL

VA DJ

12

PR1 28

1K_0402 _5%

1 2

B

C

B+

10

11

12

13

14

8

9

IADSLP

AGND

VREF

VDAC

VADJ

EXTPWR

ISYNSET

ACD ET

5

6

7

LPREF

ACSET

ACDET

PU1 00
BQ2 4740RH DR_QFN28_ 5X5

12

PC1 08

0.1 U_0603_50 V7K

4

PR1 34

0.01_ 2512_1%

1

2

PC1 01

1 2

1U_ 0603_6.3V6M

3

ACP

LPMD

4

3

2

ACN

PL100

HCB2 012KF-121 T50_0805

1 2

12

PC1 06
@0.1 U_0603_25V 7K

CH GEN#

1

29

TP

CHGEN

28

PVCC

BST _CHG

27

BTST

DH _CHG

26

HIDRV

LX_CHG

25

PH

RE GN

24

REGN

DL _CHG

23

LODRV

22

PGND

12

PC1 02

4.7 U_0805_25V 6-K

PC1 09
1U_ 0805_25V6K

1 2

PR1 37

0_0402_ 5%

1 2

PR138

0_0402_ 5%

1 2

PD1 01

LL4148_ LL34-2

12

PC1 03

4.7 U_0805_25V 6-K

PR1 06
10_0805 _1%

1 2

PC110

0.1U _0402_10V7 K

1 2

12

12

PC1 04

4.7 U_0805_25V 6-K

12

PR114
100K_04 02_5%

PC1 20

0.1 U_0603_50V 7K

CELLS

12

IADAP T

<29>

SRN

18

12

0.0 47U_0402_1 6V7K

SRP

19

DPMDET

CELLS

21

20

PC1 18

1U_ 0603_10V6K

1 2

SRSET <39>

12

PR117 210K_0 402_1%

12

PC1 22
1U_ 0603_6.3V6M

+3VL

PR1 33

100K_ 0402_5%

PR1 20

220K_ 0402_5%

2

G

12

PR1 32

470K_ 0402_5%

2007/05/29 2009/09/03

CH GCTRL <29>

+3VL

E

1 2

1 2

13

3

B

PQ108

2

MMBT3906_SOT23 -3

C

1

CH GEN#

D

PQ107

S

SSM3 K7002FU _SC70-3

Compal Secret Data

PR1 22

47K_040 2_5%

1 2

Deciphered Date

ACD ET

PR1 44

1 2

300K_ 0402_5%

C

BAT

SRSET

17

16

BATT

PC1 19

100 P_0402_50V8 J

IADAP T

IADAPT

15

12

12

PR1 18
147K_04 02_1%

PD1 02

1SS 355_SOD323-2

12

PC1 23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHG _B+

CHG _B+

578

3 6

241

578

3 6

241

12

PC1 21

PR1 47

11K_040 2_1%

1 2

P4

PQ102
AO4407A L_SO8

1
2
3 6

4

PR1 04
0_0402_ 5%

1 2

PQ105

AO4 466L 1 N SO8

10U H +-20% #919A Q-H-100M=P3 5 .3A

PL101

1 2

12

4.7 _1206_5%

PR1 39

12

12

PQ106

AO446 8L_SO8

@0. 1U_0603_25 V7K

PC1 12

PC1 26

4.7 U_0805_25V 6-K

1000P _0603_50V7K

12

1

2

PC1 28

3

1U_ 0603_6.3V6M

12

PR1 45

49. 9K_0402_1%

Title

Size Do cum ent Num ber R ev

LA-6161P

Da te: Sh eet o f

D

8
7

5

P2

PR1 09

0.01_ 1206_1%

1 2

12

PU1 04

+IN

V-

-IN

PC1 13

4.7 U_0805_25V 6-K

0.1U _0402_10V 7K

V+

OUT

1 2

PC1 17

5

4

12

+5VALW

PMC <29 >

LMV321AS5X-G_SOT23-5

1 2

PR1 46

39.2K _0402_1%

Compal Electronics, Inc.

Charger

D

BATT

12

PC1 14

4.7 U_0805_25V 6-K

32 40Tu esday, May 1 8, 201 0

12

PC1 27

PC1 15

4.7 U_0805_25V 6-K
@4. 7U_0805_25 V6-K

0.5

A

B

C

D

E

2VREF_51125

12

PC3 00

1U_ 0603_16V7

1 1

2

VFB1

VREG5

17

30.9K _0402_1%

1 2

20K_040 2_1%

1 2

115K_04 02_1%

ENT RIP1

1 2

1

ENTRIP1

VO1

PGOOD

VBST1

DRVH1

LL1

DRVL1

VCLK

18

PR3 01

PR3 03

PR3 05

24

23

22

21

20

19

+5VLP

BST_5V

UG_ 5V

LX_5V

PR3 07

0_0402_ 5%

1 2

+3VL

12

PR3 14
@100K_0 402_5%

+5VALWP

1 2

PC3 23

68P _0402_50V8J

PC3 11

0.1U _0402_10V7 K

1 2

12

12

PC3 05

0.1 U_0402_25V 6

0_0402_ 5%

1 2

RPG OOD < 14>

PC3 06

PR3 09

B++

12

12

PC3 07

2200P _0402_50V7K

PC3 08

4.7 U_0805_25V 6-K

4.7 U_0805_25V 6-K

PQ301

3 5

241

786

5

4

PQ303

123

IRF 8707GT RPBF 1N SO8

PL302

4.7U H_FDV E0630- H-4R7M=P3 _5.5A_20%

SIS 412DN- T1-GE 3 1N PO WERPAK1212-8

1 2

12

PR3 11
@4.7 _1206_5%

12

PC3 15
@680P_0 603_50V8J

1

+

PC3 13

2

150 U_B2_6.3VM_ R45M

+5VALWP

PR3 00

13.7K _0402_1%

+3VALWP

B+

PL300

HCB2 012KF-121 T50_0805

1 2

1 2

PC3 22

2 2

68P _0402_50V8J

4.7U H_FDV E0630- H-4R7M=P3 _5.5A_20%

+3VALWP

1

+

150 U_B2_6.3VM_ R45M

PC3 12

2

B++

12

12

PC3 02

2200P_ 0402_50V7K

PL301

12

PR3 10

@4.7 _1206_5%

@680P_0 603_50V8J

PC3 14

12

PC3 04

PC3 03

0.1 U_0402_25V 6

4.7 U_0805_25V 6-K

12

12

PQ300

SIS 412DN- T1-GE 3 1N POWE RPAK1212-8

UG1 _3V

3 5

241

578

PQ302

AO4 468L_SO8

3 6

241

PC3 09

4.7U _0805_6 .3V6K

PR3 08

0_0402_ 5%

1 2

+3VLP

12

1 2

PC310

51125_P WR

PR3 060 _0402_5%

1 2

0.1U _0402_10V 7K

604K_04 02_1%

1 2

@499K_0 402_1%

1 2

B+

1 2

PR3 02

20K_040 2_1%

1 2

PR304

105K_04 02_1%

1 2

BST_ 3V

UG_ 3V

LX_3V

LG_3V LG_5V

PR3 16

PR3 12

25

P PAD

7

VO2

8

VREG3

9

VBST2

10

DRVH2

11

LL2

12

DRVL2

12

ENT RIP2

5

6

3

4

VFB2

VREF

TONSEL

ENTRIP2

PU3 00

TPS 51125R GER QF N 24P

GND

VIN

SKIPSEL

EN0

15

16

14

13

51125_P WR

+3VEXTLP

12

3 3

2N7 002KDW H-2N_SOT3 63-6

4 4

ENT RIP1

61

PQ304A

SSM3 K7002FU _SC70-3

2

PQ305

ENT RIP2

34

PQ304B
2N7 002KDW H-2N_SOT 363-6

5

+5VALW P

PR3 17

100K_04 02_5%

1 2

2

G

PR3 18

330K_04 02_5%

100K_04 02_1%

PD3 01

1SS 355_SOD323-2

PD3 02

1SS 355_SOD323-2

13

D

S

12

PR3 21

VL

12

12

12

KBC_PWR_ON <29 >

DEBUG_KBCRST <28>

VCC1_PWRGD <29, 39>

+3VALW P

EN0 < 32>

A

B

PR3 15 100K _0402_1%

2VREF_51125

PJP300

1 2

PA D-OPE N 4x4m
PJP301

1 2

PA D-OPE N 4x4m

PJP302

2 1

PA D-OPE N 2x2m

PJP303

2 1

PA D-OPE N 2x2m

PJP304

2 1

PA D-OPE N 2x2m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC3 16

0.1 U_0603_25 V7K

(4.5A, 180mil s ,Via NO.= 9)

+5VALW

(3A,12 0mils ,Via NO.= 6)

+3VALW

+VREG_51125+3VLP

VL+5VLP

+3VL+3VEXTLP

2008/09/15 2009/09/03

C

12

PC3 17

PC3 18

10U _0805_10V6K

10U _0805_10V6K

P2

12

PR3 20

255K_ 0402_1%

12

12

PR3 22

11. 5K_0402_1%

1U_ 0603_10V6K

PC3 21

PC3 19

10U _0805_10V6K

DEBU G_KBC RST

PU3 02

1

+IN

2

V-

3

-IN

LMV321AS5X-G_SOT23-5

Compal Secret Data

Deciphered Date

D

V+

OUT

12

PR3 25

+5VLP

5

4

+5VLP

PU3 03

1

VIN

12

2

3

220K_ 0402_5%

12

PR3 26

470K_04 02_5%

PR3 31

1 2

680K_04 02_5%

Title

Size Do cum ent Num ber R ev

Cu stom

Da te: Sh eet o f

VOUT

GND

EN

FB

APL5317

PD3 04

12

1SS 355_SOD323-2

Compal Electronics, Inc.

3.3VALWP/5VALWP

LA-6161P

12

PR323

64.9K _0402_1%

5

4

12

12

PR3 27 2 0K_0402_1%

PR3 24 16 .5K_0402_1 %

33 40Tu esday, May 1 8, 201 0

E

12

PC3 20

2.2 U_0805_10V 6K

0.5

A

1 1

B+

PL401

HCB2 012KF-121 T50_0805

1 2

1 2

PC4 19

68P _0402_50V8J

2 2

SLP_S3#<14,22,29,30,31,33>

VCCP_EN<30>

3 3

12

PC4 16

0.1 U_0402_25 V6

+62 69_VCC

VCC P_B+

12

PC4 01

2200P _0402_50V7K

12

PC4 02

4.7 U_0805_25V 6-K

12

PC4 07

2.2 U_0805_10V 6K

1 2

PR4 06

@0_0402 _5%

1 2

PR4 28

0_0402_ 5%

12

PC4 03

4.7 U_0805_25V 6-K

12

PC4 04

4.7 U_0805_25V 6-K

PR4 05

0_0402_ 5%

1 2

12

<30>

VCC P_POK

PC4 11

@0. 1U_0402_10 V7K

PC4 14

+VC CP

+3VS

12

12

PR4 27

PR4 01

10K_04 02_5%

@10K_ 0402_5%

LX_ VCCP

16

15

17

PU4 01

GND

1

VIN

2

VCC

3

FCCM

4

EN

PGOOD

COMP5FB6FSET

12

FB _VCC P

PR4 09

12

25. 5K_0402_1%

PR4 10

12

33P _0402_50V8J

PC4 15

2200P_ 0603_50V7K

12

PR4 12

2.94K _0402_1%

4 4

DH _VC CP

14

UG

PHASE

7

12

49. 9K_0402_1%

1 2

PR4 11

2.21 K_0402_1%

B

1 2

PR4 02

2.2_ 0603_5%

+5VALW

BST _VCCP

13

BOOT

12

PVCC

PGND

LG

ISEN

PC4 06

2.2U _0805_10V6 K

DL _VCCP

11

10

SE_ VCCP

9

VO

8

ISL62 69ACR Z-T_QFN 16

+VC CP

12

PC4 13

0.0 1U_0402_1 6V7K

12

PC4 17

@0. 1U_0402_25 V6

12

PR4 03

0_0402 _5%

PR404

1 2

2.2_0 603_5%

1 2

8.06 K_0402_1%

1 2

PR413
10_0402 _5%

1 2

PR4 14
0_0402_ 5%

PR4 17

1 2

0_0603_ 5%

1 2

PC4 05

0.22 U_0603_10V 7K

+62 69_VCC

1 2

PR4 07

+VC CP

DH _VCC P1

VTT_SENSE <7>

578

3 6

241

3 5

241

C

AO4 474L_SO8

PQ401

12

PR4 08

2.2_1 206_5%

PQ402

AO N6718 L 1N D FN

PC4 12

1 2

680P_06 03_50V7K

PL402

0.36 UH 20% FDU10 40J-H- R36M=P 3 33A

1 2

PJP401

+VC CP

1 2

+

PC4 08

330 U_D2_2 V_Y

PA D-OPE N 4x4m

1

2

1

1

+

+

PC4 09

2

PC4 10

2

330 U_D2_2 V_Y

330 U_D2_2 V_Y

+1.05VS

1

+

PC4 18

2

220 U_B2_2.5VM_ R25M

D

(18A,7 20mils ,Via NO.= 36)

+VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

C

Title

Size Do cum ent Num ber R ev

Da te: Sh eet o f

Compal Electronics, Inc.

1.05V_VCCP

LA-6161P

D

34 40Tu esday, May 1 8, 201 0

0.5

A

PR6 10

0_0805_ 5%

+1.5V

+1.5 VS_CP U_VDDQ

1 2

1 2

PR612

@0_0805 _5%

12

1 1

+5VALW

PC6 01

10U _0805_6.3V6 M

12

PD6 01

1SS 355_SOD323-2

<14,22,29,30,31,33>

SLP_S3#

2 2

1 2

1 2

PR604

20K_040 2_1%

12

PR6 02

10K_0 402_5%

13

D

2

G

S

PQ602

PC6 06

SSM3 K7002FU_ SC70-3

.1U _0402_16V 7K

B

PU6 01

VIN1VCNTL

2

+1.5V

12

12

PC6 02

10U _0805_6.3V6 M

12

PR6 01

PR6 11

1K_04 02_1%

@1K_0 402_1%

GND

3

VREF

4

VOUT

G29 92F1U_SO8

12

13

D

2

G

S

PQ601

SSM3 K7002FU _SC70-3

12

0.1 U_0402_10V 7K

PC6 04

PR6 05

0_0402_ 5%

1 2

12

PC6 05

10U _0805_6.3V6M

PR6 03

1K_04 02_1%

NC

NC

NC

TP

+0.75VSP

6

5

7

8

9

C

D

+5VALW

12

PC6 03

1U_ 0603_10V6K

12

316K_04 02_1%

PR6 08

12

PC6 11

0.1 U_0402_25V 6

402K_04 02_1%

12

PC6 10

10U _0805_10V6K

+1.8VSP

PL601

+5VALW

3 3

HCB1 608KF-121 T30_0603

1 2

1 2

12

0.1U _0402_16V7 K

1 2

PC6 09

10U _0805_10V6K

PR6 07

PC6 13

1 2

1 2

PR6 09

0_0402_ 5%

PU6 02

1

EN/SYNC

FB

2

GND

3

4

5

GND

SW

SW

IN

BS

MP2 121DQ-LF -Z_QFN10_3X3

IN

POK

TP

10

9

8

7

6

11

PC6 08

@0. 1U_0402_16 V7K

1.8VS_POK
<30>

PL602

1.2U H +-30 % 1231 AS-H-1R 2N=P3 2.9A

1 2

12

12

PD6 02

@B340A_ SMA2

PR6 06

4.7_1 206_5%

12

PC6 12
680P_06 03_50V7K

12

PC6 15

22U _0805_6.3V6 M

+1.8VSP

12

22U _0805_6.3V6 M

PC6 14

PJP601

+0.75VSP

4 4

1 2

PA D-OPE N 3x3m

A

(2A,80 mils , Via NO.= 4)

+0.75VS

+1.8VSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

C

PJP602

1 2

PA D-OPE N 3x3m

(1.5A, 60mils ,Via NO.= 3)

+1.8VS

Title

Size Do cum ent Num ber R ev

LA-6161P

Da te: Sh eet

Compal Electronics, Inc.

0.75VSP/1.8VSP

D

35 40Tu esday, May 1 8, 201 0

0.5

o f

A

1 1

PR8 01

0_0402_ 5%

SLP_S4#<14,25>

2 2

+5VALW

+5VALW

1 2

@0.1 U_0402_16V 7K

PR8 06

316_040 2_1%

1 2

PC8 07

1U_ 0603_10V6K

PC8 01

12

12

+1.5V

PR8 08

+1.5V

PC8 09

@10 P_0402_50V8J

255K_04 02_1%

1 2

1 2

PR8 05 0_0402_5 %

10K_040 2_1%

1 2

1 2

PR8 03

12

2

3

4

5

6

PU8 01

TON

VOUT

VDD

FB

PGOOD

PR8 101 0K_0402_1%

B

BST_1.5V

14

1

15

NC

BOOT
UGATE

EN/DEM

PHASE

VDDP

LGATE

GND7PGND

RT8209B GQW_W QFN14_3P5X3P 5

8

CS

PR8 02

2.2_0 402_5%

1 2

UG_ 1.5V

13

LX_1.5V

12

11

1 2

+5VALW

10

LG_ 1.5V

9

PC8 06

0.1U _0402_10V7 K

1 2

PR8 07

12.4K _0402_1%

12

PR8 04

0_0402_ 5%

1 2

PC8 08

4.7U _0805_10V6 K

UG1 _1.5V

C

+1.5V_B+

12

12

12

PL801

HCB 1608KF-121 T30_0603

1 2

12

D

B+

1 2

PC8 13

PQ801

SIS 412DN- T1-GE 3 1N POWE RPAK1212-8

3 5

241

68P _0402_50V8J

PC8 03

PC8 02

0.1 U_0402_25 V6

2200P_ 0402_50V7K

2.2U H 20% FDVE06 30-H-2 R2M=P3 8.3A

1 2

PC8 04

PL802

PC8 05

4.7 U_0805_25V 6-K

4.7 U_0805_25V 6-K

+1.5V

12

PR8 09
@4.7 _1206_5%

12

PC8 12

IR FH370 7TRPB F 1N P QFN

PQ802

3 5

241

@680P_0 603_50V8J

1

12

+

2

PC8 10

PC8 11

220 U_B2_2.5VM _R25M

4.7 U_0805_6 .3V6K

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/10/31 2009/09/03

Compal Secret Data

Deciphered Date

C

Title

Size Do cum ent Num ber R ev

Da te: Sh eet o f

Compal Electronics, Inc.

1.5VP

LA-6161P

D

36 40Tu esday, May 1 8, 201 0

0.5

8

H H

VGATE<12,14 >

12

12

CLK _EN#<1 1>

PG D_I N<14, 29>

1 2

PR2 19 0_04 02_5%

PC2 15 33P_ 0402_50 V8J

1 2

PC2 16 33P_ 0402_50V 8J

CPU _CSN 2-1

1 2

PC2 17 33P _0402_ 50V8J

1 2

PC2 19 33P_ 0402_50 V8J

1 2

CP U_ GNDS NS

12

12

PR2 25 0_0 402_5%

PR2 26 0_0 402_5%

VSS SENSE

VC CSEN SE<7>

<7>

G G

F F

PR2 20 47 0_040 2_1%

C PU_C SP2

E E

CP U_C SN2

CP U_C SN1

C PU_C SP1

D D

C C

B B

A A

12

100 P_040 2_50V8J

PR2 21 47 0_0402 _1%

12

12

PR2 22 470_ 0402_1%

100 P_040 2_50V8J

12

PR2 23 470 _0402_1 %

8

PC2 12

PC2 20

PR2 03 0_04 02_5%

1 2

PR2 04 0_04 02_5%

1 2

PR205 220_0402_5%

1 2

PC2 10

0.2 2U_0 603_10V7 K

CPU _MO DE

CPU _CSP 2-2

CPU _CSN 1-1

CPU _CSP 1-2

C PU_V SNS

CPU _TH ERM

CPU _VR_T T#

20K _0402_1 %

1 2

PR2 27

12

PR2 43

CPU _CSN 2-1

CPU _CSP 2-2

7

PC2 08 2.2U _0603 _10V6K

1 2

1 2

PC2 09

41

GND

1

MODE

2

GND

3

CSP2

4

CSN2

5

CSN1

6

CSP1

7

GNDSNS

8

VSNS

9

THERM

10

VR_TT#

1 2

PR2 29 6 8_04 02_5%

1 2

PR2 28 0_ 0402_5 %

<4>

+V CCP

H_P ROCH OT#

12

12

PR2 44

PC2 28

@0_ 0402_5%

12. 4K_040 2_1%

VSS SENS E

PR2 64 @0_ 0402_5%

1 2

PR2 65 @0_ 0402_5%

1 2

PR2 66 @0_ 0402_5%

1 2

7

+3V ALW

12

PR2 01

PR2 02

47K _0402_1 %

1 2

@1K _0402_5 %

1 2

@1K _0402_5 %

PR2 06

12

68P _0402_ 50V8J

PR2 09 5.2 3K_04 02_1%

1 2

1 2

PR2 11 0_0402_ 5%

PR2 10 249K _0402_1 %

CPU _CLK _EN #

CP U_V REF

CP U_D ROO P

39

40

VREF

IMON11DPRSLPVR12PSI#13VID614VID515VID416VID317VID218VID119VID0

CPU _IM ON

0_0 402_5%

1 2

PR2 30

IMV P_IMON

0.0 33U_ 0402_16 V7K

<7>

CP U_V R_O N

C PU_I SLEW

CPU _TON SEL CP U_V REF

CPU _5V FILT

35

36

37

38

ISLEW

V5FILT

DROOP

PR OC_D PRS LPVR

<7>

VR_ON

TONSEL

PU2 01

TPS 5162 1RHAR _QFN40_ 6X6

PSI #_1

1 2

PR2 67 0_0 402_5%

H_V ID5

H_ VID 6

H_ VID 4<7>

<7>

<7>

PSI#

<7>

CPU _5V FILTPSI #_1

34

CLK_EN#

H_ VID 3<7>

6

+5V ALW

HGA TE_C PU2

0_0 402_5%

0_0 402_5%

1 2

PR2 13

1 2

PR2 12

CPU _TR IPSEL

CPU _OSR SEL

C PU_P GOOD

31

32

33

PGOOD

H_ VID 2

<7>

30

OSRSEL

TRIPSEL

DRVH2

29

1 2

VBST2

PR2 18 2. 2_0603 _5%

28

LL2

LGA TE_C PU2

27

DRVL2

26

V5IN

25

PGND

LGA TE_C PU1

24

DRVL1

PHA SE_C PU1

23

LL1

22

VBST1

PR2 24 2.2_ 0603_5%

21

DRVH1

20

H_ VID 0

H_ VID 1<7>

<7>

H _VID 0

H _VID 1

H _VID 2

H _VID 3

H _VID 4

H _VID 5

H _VID 6

PR OC_ DPRS LPVR

PSI # PSI #

Arr and ale

SV
LV
ULV

6

+5V ALW

1 2

PC2 18 4.7U _06 03_10V6K

12

1 2

PD2 02

HGA TE_C PU1

VID (6 -0) : 01 0011 1
VID (6 -0) : 00 1111 1
VID (6 -0) : 00 1011 1

PD2 01

1 2

1SS 355_S OD323-2

1 2

PC2 14

0.2 2U_0 603_10V 7K

+5V ALW

1 2

PC2 21

0.2 2U_0 603_10V 7K

1SS 355_ SOD323-2

PR2 46

12

PR2 48

12

PR2 50

12

PR2 52

12

PR2 54

12

PR2 56

12

PR2 58

12

PR2 60

12

PR2 62

12

5

+5V ALW

1K_ 0402_5%

1K_ 0402_5%

1K_ 0402_5%

@1K _0402_5 %

@1K _0402_5 %

1K_ 0402_5%

@1K _0402_5 %

1K_ 0402_5%

@1K _0402_5 %

5

4

4

+VC CP

PQ20 1

TPC A803 0-H 1N SO P-ADV

123 5

Pha se_C PU2

PQ2 03

123 5

TPC A803 6-H 1N S OP-ADV

4

4

H _VID 0

H _VID 1

H _VID 2

H _VID 3

H _VID 4

H _VID 5

H _VID 6

PR OC_ DPRS LPVR

4

CPU_B+

12

12

PC2 01

1 2

PC2 32

0.1 U_04 02_25V6

68P _0402_ 50V8J

12

PR2 14

4.7 _1206_ 5%

C PU_S NB2

12

PC2 11

680 P_0402 _50V7K

PC2 33

PQ2 05

TPC A803 0-H 1N SO P-ADV

123 5

12

C PU_S NB1

PQ2 07

123 5

TPC A803 6-H 1N SO P-ADV

PR2 47 @1K _0402_5 %

12

PR2 49 @1K _0402_5 %

12

PR2 51 @1K _0402_5 %

12

PR2 53 1K_ 0402_5%

12

PR2 55 1K_ 0402_5%

12

PR2 57 @1K _0402_5 %

12

PR2 59 1K_ 0402_5%

12

PR2 61 @1K _0402_5 %

12

PR2 63 1K_ 0402_5%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

12

2008/09/15 2009/09/03

12

PC2 30

PC2 05

4.7 U_08 05_25V6- K

220 0P_040 2_50V7K

CPU _CSP 2-1

12

PR2 15

17. 8K +- 1% 0603

C PU_C SP2

12

PC2 22

1 2

0.1 U_04 02_25V6

68P _0402_ 50V8J

PR2 40

4.7 _1206_5 %

PC2 27

680 P_0402_ 50V7K

3

12

PC2 07

PC2 06

4.7 U_08 05_25V6- K

PL20 2

0.3 6UH 20% FD U104 0J-H- R36M=P3 33A

1

2

1 2

PR2 17 2 8.7K _0402_1 %

12

PC2 23

220 0P_040 2_50V7K

12

PR2 41

17. 8K +- 1% 0603

PR2 45

C PU_C SP1

Compal Secret Data

PC2 02

4.7 U_08 05_25V6- K

4

3

PR2 16

69. 8K_040 2_1%

1 2

100 K_04 02_1%_ TSM0B104 F4251RZ

CPU _SN- 2

1 2

PC2 13

0.0 33U_ 0402_16 V7K

12

PC2 24

PC2 31

4.7 U_08 05_25V6- K

4.7 U_08 05_25V6- K

0.3 6UH 20% FD U104 0J-H- R36M=P3 33A

1

CPU _CSP 1-1

2

PR2 42

69. 8K_040 2_1%

1 2

100 K_04 02_1%_T SM0B104F 4251RZ

CPU _SN- 1

1 2

28. 7K_040 2_1%

1 2

PC2 29

0.0 33U_ 0402_16 V7K

Deciphered Date

3

4.7 U_08 05_25V6- K

PL20 3

PC2 04

PH2 01

1 2

12

PC2 25

4.7 U_08 05_25V6- K

1 2

HCB 2012 KF-121 T50_0805

1 2

HCB 2012 KF-121 T50_0805

1 2

1

+

2

68U _25V_ M_R0.3 6

PC2 26

4.7 U_08 05_25V6- K

4

3

PH2 02

PL2 01

PL2 04

CP U_C SN2

CP U_C SN1

CPU_B+

2

B+

1

+

PC2 03

2

68U _25V_ M_R0.3 6

+C PU_C ORE

Compal Electronics, Inc.

Title

Size Doc ume nt N umber R ev

C

L A-61 61P

Dat e: Shee t

2

CPU_CORE

1

37 40Tue sday , M ay 18, 201 0

o f

1

5

VL

C

ADP_P RES

D D

C C

IADAPT<33>

ADP_PR ES<33>

ADP_ SIGNAL<32>

PR1022

100_0402_5%

1 2

PQ1009

2

B

MMBT3904WH SOT323-3

E

3 1

PR1013

10K_0402_1%

1 2

2

G

PQ1008

@SSM3K70 02FU_SC70-3

VIN

PR1067

110K_0402_1%

1 2

13

D

S

BQ24740 VREF

12

PR1000

511K_0402_1%

12

PR1018
105K_0402_1%

PQ1003

NDS0610 _NL_SOT23-3

12

PR1030

68K_0402_5%

12

PR1040
33K_0402_5%

12

PR1045

B B

A A

4.7K_04 02_5%

1SS355_ SOD323-2

5

PR1046

8.66K_0 402_1%

12

PD1004

2VREF_5 1125

12

PR1063

12

PR1065

12

12

12

130K_0402_1%

10K_0402_1%

PR1042

PR1059

8.06K_0 402_1%

E

3

PQ1006

C

MMBT3906_SOT23-3

1

ADP_ A_ID

45.3K_0 402_1%

+3VL

B

2

PR1062

1M_0402_5%

1 2

VL

8

5

P

+

6

-

G

4

1 2

PR1066

10K_0402_5%

O

PU1001B
LM393DR_ SO8

ADP_ A_ID

4

PC1000

0.1U_06 03_16V7K

1 2

PU1000

1

+IN

2

V-

3

-IN

LMV321AS5X-G_SOT23-5

1SS355_ SOD323-2

D

S

13

G

2

7

4

5

V+

4

OUT

PD1000

12

+3VL

12

PR1064

22K_0402_5%

ADP_ A_ID <29>

12

PR1017
2K_0402_5%

1 2

12

PR1025

3.9K_04 02_5%

ADP_DET# <29>

3

+5VS

12

PC1001

0.01U_0 402_16V7K

PD1001
1SS355_ SOD323-2

1

PC1003

2

3900P_0 402_50V7K

PR1028

100K_0402_5%

1 2

1 2

PR1032

100_0402_5%

OCP_ A_IN

2

B

12

PD1003
GLZ4.7B _LL34-2

SRSET <33>

C

PQ1005
MMBT3904W H SOT323-3

E

3 1

OCP_ A_IN <29>

OCP<29>

12

PR1031

80.6K_0 402_1%

ADP_EN # <33>

12

34

5

PQ1007B

2N7002K DW-2N_SOT363-6

VCC1 _PWRGD <29,34>

61

2

PQ1007A

2N7002K DW-2N_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/03

3

ADP_E N <29>

Compal Secret Data

Deciphered Date

2

PR1029

100K_0402_1%

1 2

PC1004

0.01U_0 402_16V7K

2

PR1033 @0_0402_1%

1 2

PR1034 200K_0402_1%

1 2

8

3

+

2

-

4

1 2

12

PR1027 100K_0402_1%

PR1026

100K_0402_1%

Cust om

1

+3VS

PR1019
10K_0402_5%

1 2

1 2

PR1020
0_0402_5%

13

D

2

G

S

PQ1004
SSM3K700 2FU_SC70-3

PR1035

P

O

G

PU1001 A
LM393DR_ SO8

Title

Size D ocumen t Number Re v

Dat e: Sheet

10K_0402_5%

1

1 2

<BOM Str ucture>

+3VL

+3VS

Compal Electronics, Inc.

ADP_OCP

LA-6161P

o f

38 40Tuesd ay, Ma y 18, 2010

1

OCP# <15>

5

D D

4

<7>

<7>

<7>

<7>

<7>

<7>

<7>

3

2

1

GFX VR_EN <7>

GFX VR_V ID_2

GFX VR_V ID_1

0_0 402_5%

PR7 04

PR7 03

1 2

1 2

1 2

@0_ 0402_5%

GFX _EN

GFX _VID0

32

EN

1

PWRGD

2

IMON

3

CLKEN#

4

FBRTN

5

FB

ADP 3211 AMNR 2G_QFN3 2_5X5

6

COMP

7

GPU

8

ILIM

IREF9RPM10RT11RAMP12LLINE13CSREF14CSFB15CSCOMP

GFX _IR EF

GFX_ RPM

1 2

1 2

PR7 21 80 .6K_0 402_1%

PR7 22 237 K_0402_1 %

GF X_RAMP-1

12

PC7 18

100 0P_040 2_50V7K

GFX VR_V ID_0

0_0 402_5%

0_0 402_5%

PR7 06

PR7 05

1 2

1 2

GFX _VID1

GFX _VID2

VID031VID130VID229VID328VID427VID526VID6

PU7 01

GFX_R T

GF X_RAMP

12

1 2

PR7 23 340 K_0402_1 %

12

+GFX_CORE

12

@10 K_0402_ 1%

PR7 01

+VCCP

12

PR7 13

12

1 2

PC7 11

PR7 18

1 2

PC7 08

0.0 56U_ 0402_16 V7K

470 P_0402 _50V8J

PR7 31 100_ 0402_5%

@30 0K_0402 _1%

12

PR7 15

6.9 8K_040 2_1%

GF X_COMP-1

1 2

PC7 14

PC7 13

47P _0402_ 50V8J

1 2

PR7 19

20K _0402_1 %

12

+GFX_B+

GF X_IMON

GF X_FB

GF X_COMP

GFX _VCC

GFX_ ILIM

1 2

GFX _CSCO MP

PR7 20 10. 7K_040 2_1%

PR7 30 1K _0402 _1%

PR7 14

0_0 402_5%

1 2

1 2

PC7 10

100 0P_040 2_50V7K

100 _0402_5 %

PR7 32

12

1 2

VSS _AXG_SEN SE

<7>

0_0 402_5%

PR7 24

220 P_0402 _50V7K

1 2

1K_ 0402_1%

1 2

PR7 25 0_04 02_5%

VCC _AXG _SENSE

<7>

GFX VR_IM ON<7>

C C

B B

GFX VR_V ID_3

0_0 402_5%

0_0 402_5%

PR7 08

PR7 07

1 2

GFX _VID3

GFX _VID4

GFX _CSCO MP

PR7 26 422 K_0402_1 %

GFX VR_V ID_6

GFX VR_V ID_5

GFX VR_V ID_4

0_0 402_5%

0_0 402_5%

0_0 402_5%

PR7 10

PR7 09

PR7 11

1 2

1 2

1 2

GFX _VID5

GFX _VID6

25

DRVH

PVCC

DRVL

PGND

AGND

AGND

16

GFX _CSF B

GFX _CSCO MP

12

PC7 19

100 0P_040 2_50V7K

+5VALW

24

VCC

GFX_ BOOST

23

BST

22

21

SW

20

19

18

17

33

12

PC7 16
120 0P_040 2_50V7K

PR7 12

10_ 0603_1%

1 2

12

GFX _VCC

GFX _DR VH

GFX _SW

GFX _DRV L

PC7 01
1U_ 0805_ 25V6K

PR7 16

2.2 _0603_ 5%

1 2

PH7 01

1 2

71. 5K_040 2_1%

12

PC7 17
680 P_0402 _50V7K

PR7 27

PC7 09

0.2 2U_0 603_25V 7K

GFX_ BOOST-1

1 2

+5VALW

12

PC7 12

2.2 U_06 03_10V6 K

220 K_04 02_5% _ERTJ0E V224J~D

12

12

PR7 28
165 K_0402 _1%

PR7 29

54. 9K_060 3_1%

+GFX_B+

12

12

5

4

5

4

12

68P _0402 _50V8J

PQ70 1

AO4 474L_SO 8

123

12

PR7 17

4.7 _1206_ 5%

12

PQ7 02

PC7 15
680 P_0603 _50V7K

AON 6718 L_DF N8-5

123

1 2

PC7 20

786

PC7 03

PC7 02

220 0P_040 2_50V7K

0.1 U_04 02_25V6

.56 UH +-20 % ET QP4L R56 WF C 21A

1

2

PL70 2

12

PC7 05

PC7 04

4.7 U_08 05_25V6- K

4.7 U_08 05_25V6- K

4

3

PL70 1

HCB 2012 KF-121T 50_0805

1 2

12

PC7 06

4.7 U_08 05_25V6- K

B+

+GFX_CORE

+GFX_CORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/09/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ze D ocum ent Num ber Re v

Si

C

L A-61 61P

Dat e: Shee t

GFX _CORE

1

39 40Tue sday , M ay 18, 201 0

o f

V

ersion chang e list (P.I.R. List) Pow er section Page 1 of 1

5

4

3

2

1

Item Reason for change PG# Modif y List

1

Tune L oadlin e and transi ent response of GFX.

2

Tune L oadlin e and transi ent response of CPU.

D D

3

Add bo ost re sistan ce for RF team.

Modify the t hrottl ing setting level and

4

action speed.

IN AC mode, the pe rformance will reduce

5

throug h IADA PT wit hout PQ1008.

OTP se tting is set ted sa me with other project.

6

3

7

30uF E SR=9mO hm can pass VCCP rippe spec.

8

CPU th ermal protec tion fine-tune.

9

For UL V CPU, need reserv ed some components.

10

For CP U accu racy get better.

C C

11 For Electrical Noise Issue.

1

1 For EMI request.

P39

Change PR729 to 54 .9k, PC716 to 1200pF,
and PC 717 to 680pF.

P37

Change PR209 to 5.23k.

P36

Change PR802 to 2.2ohm.

Change PR101 3 to 1 0k, PR1000 to 511k,

P38

PR1018 to 10 5k, an d PC1000 to 0.1uF.

P38

Add PQ 1008.

P31

Change PR5 t o 53.6 k and PR10 to 19.1k.

Change PR408 , PR40 9, and PR410 to

P34

P31

P37

P37

P37

P32

30uF_9 mOhm.

3

Change PR10 to 21K from 19.1K 03/26 P V

Add PR 264, P R265, PR266 locations which is
reserved.

Change PR215 and P R241 to 0603 size

nd kee p 17.8K

a

Add PC 204, w hcih is 68u

Add sn abber, PR139 to 4. 7ohm, PC126 to 1n

Date

01/27 SI

0

1/27 SI

01/28

01/29

02/01

02/02

03/26 PV

03/26 PV

03/31

03/31PVPV

Phase

SI01/28

SI

SI

SI

SI

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

2005/03/10 2009/09/03

Deciphered Date

2

Compal Electronics, Inc.

Title

Changed - List Power History

Size Do cu ment Number Rev

Cus tom

DB- 580

Date : Sheet

of

40 <Page Count>Tuesda y, May 18, 2 010

1

5

V ersio n C h an ge L is t

V ersio n C h an ge L is t ( P . I. R . L ist ) for H W C ircu it

V ersio n C h an ge L is tV ersio n C h an ge L is t

I t em

I t em I s su e D

P a ge #

I

D D

C C

B B

g e #

t e mIt e m

P aP a

g e #g e#

2 8

2 8

2 82 8

1111

2 8

2 8 PW

2 82 8

2222

2 2

2 2 WWWW W A N

2 22 2

3333

2 3

2 3 A u d

2 32 3

4444

2 2

2 2 W L

2 22 2

5555

1 1, 21

1 1, 21

1 1, 211 1 , 2 1

6666

2 3

2 3 A u d

2 32 3

7777

3 0

3 0 D C

3 03 0

8888

1 4

1 4 G L

1 41 4

9999

1 4

1 4

1 41 4

1 0

1 0

1 01 0

9999 T r a

1 1

1 1

1 11 1

2 4

2 4 A ud

2 42 4

1 2

1 2

1 21 2

2 2

2 2 SSSS P I

2 22 2

1 3

1 3

1 31 3

1 4

1 4

1 41 4

1 4

1 4

1 41 4

2 2 SSSS P I

2 22 2

1 5

1 5 CCCC om p a l

1 51 5

1 8

1 8 L C D

1 81 8

1 6

1 6

1 61 6

TTTT it le

it le

it leit le

Q u i ck

Q u i ck lo ok /w e b

l o ok /w eb

Q u i ckQ u i ck

l o ok /w eb l oo k /w e b

P W R L E D

R L E D

P WPW

R L E DR L E D

W A N

W A NW A N

A u d io

i o

A u dA ud

i oi o

W L A N

A N

W LW L

A NA N

A u d io

i o

A u dA ud

i oi o

D C -D C

-D C

D CD C

-D C- D C

G L A N

A N

G LG L

A NA N

T ra

T ra n sf o rm er

n s fo r m e r

T raT r a

n s fo r m e rn sf or m e r

T ra n sf o rm er

n s fo r m e r

T raT r a

n s fo r m e rn sf or m e r

A u d io

i o

A u dA ud

i oi o

P I

P I P I

CCCC P U

P U

P UP U

P I

P I P I

L C D

L C DL C D

( P . I. R . L ist ) for H W C ircu it

( P . I. R . L ist ) for H W C ircu it ( P . I. R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR e q

D a t e

D a t eD a t e

1 2

1 2 /2 4

/ 2 4

1 21 2

/ 2 4/ 2 4

1 2

1 2 /2 4

/ 2 4 CCCC om p a l

1 21 2

/ 2 4/ 2 4

1 / 4

1 / 4 CCCC om p a l

1 / 41/ 4

1 / 5

1 / 5 CCCC om p a l

1 / 51/ 5
1 / 6

1 / 6 CCCC om p a l

1 / 61/ 6

1 / 6

1 / 6 CCCC om p a l

1 / 61/ 6

1 / 6

1 / 6 CCCC om p a l

1 / 61/ 6

1 /

1 / 11

1 1 CCCC om p a l

1 /1 /

1 111

1 /

1 / 13

1 3 CCCC om p a l

1 /1 /

1 313

1 /

1 / 14

1 4 CCCC om p a l

1 /1 /

1 414

1 /

1 / 21

2 1 H P

1 /1 /

2 121

1 /

1 / 28

2 8 H P

1 /1 /

2 828

2 /

2 / 23

2 3 CCCC om p a l

2 /2 /

2 323

2 /

2 / 24

2 4 CCCC om p a l

2 /2 /

2 424

3 /

3 / 12

1 2 C ha

3 /3 /

1 212

3 / 23

2 3 FFFF o r E M I's r e qu es t

3 /3 /

2 323

u e stu e st

O w n

O w n e r

e r

O w nO w n

e re r

CCCC om p a l

o m p a l

o m p a lo m p a l

o m p a l PPPP W R L E D c an 't f la sh in S 3. O T S # 6 03 77 4

o m p a lo m p a l
o m p a l th e L E D p a n e l w a s a ut o t u r n o n w h h en

o m p a lo m p a l

o m p a l au di o n o f un c t ti o n . O TS # 6 0 3 7

o m p a lo m p a l
o m p a l D e

o m p a lo m p a l

o m p a l re s is t a nc e to o s m a ll w ill im pa ct t he S M T l

o m p a lo m p a l

o m p a l P C _B E

o m p a lo m p a l

o m p a l po we r d o w n s e qu e n ce h a v v p ro b

o m p a lo m p a l

o m p a l Sy st em c an 't w a k e u p f ro m S 3 & S 5 .

o m p a lo m p a l
o m p a l E M I

o m p a lo m p a l

H P re se r ve m em o ry t h e rm al s en so r b y H

H PH P
H P f

H PH P

o m p a l F o r S PI R O M R ec ov

o m p a lo m p a l

o m p a l

o m p a lo m p a l

o m p a l

o m p a lo m p a l

CCCC om p a l

o m p a l3 /

o m p a lo m p a l

4

I s su e D e sc rip ti on

I s su e DI s su e D

T h e L E D S t at u s a bo ut W ir e le ss /Q uic kL oo k 3

T h e L E D S t at u s a bo ut W ir e le ss /Q uic kL oo k 3 /

T h e L E D S t at u s a bo ut W ir e le ss /Q uic kL oo k 3T h e L E D S t at u s a bo ut W ir e le ss /Q uic kL oo k 3

Q uic kW e b i s a bn or m a l . O T S #

Q uic kW e b i s a bn or m a l . O T S # 6 03 77 8

Q uic kW e b i s a bn or m a l . O T S #Q uic kW e b i s a bn or m a l . O T S #

W R L E D c an 't fl a sh in S 3. O T S # 6 03 77 4 C ha n g e

W R L E D c an 't fl a sh in S 3. O T S # 6 03 77 4W R L E D c an 't fl a sh in S 3. O T S # 6 03 77 4

th e L E D p an el w as a u to t u r n o n w h h e n p lu g in A C.

th e L E D p an el w as a u to t u r n o n w h h e nth e L E D p an el w as a u to t u r n o n w h h e n

OOOO T S # 6 0 37 86

T S # 6 03 78 6

T S # 6 03 78 6TS # 6 0 3 7 86

a u d i o n o f un ct tio n . O TS # 6 03 7 77

a u d i o n o f un ct tio n . O TS # 6 03 7au di o n o f un c t ti o n . O TS # 6 0 3 7
D e b u g p or t 8 0 i s n ot u se d

D eD e

re si st an ce t o o s ma ll w il l im p a ct t h e S M T l in e

re si st an ce t o o s ma ll w il l im p a ct t h e S M T lre si st an ce t o o s ma ll w il l im p a ct t h e S M T l

y ie ld r at e

y i e l d ra te

y i e l d ra te y ie ld r a te

P C_ B E E P n o s ou n d in D O S m od e. O TS # 6 0 4 31 4

P C_ B EP C_ B E

p ow e r d ow n s eq u e nc e h av v p ro b le m w it h + 5V S &

p ow e r d ow n s eq u e nc e h av v p ro bp ow e r d ow n s eq u e nc e h av v p ro b

+ 3 V S . ( + 5V S g oe s to l o w a ft e

+ 3 V S . ( + 5V S g oe s to l o w a ft e r + 3V S)

+ 3 V S . ( + 5V S g oe s to l o w a ft e+ 3 V S . ( + 5 V S g o e s t o l o w a ft e
S y s te m ca n't w ak e u p f ro m S 3 & S 5. OT S# 6 05 64 7

S y s te m ca n't w ak e u p f ro m S 3 & S 5.Sy st em c a n ' t w a k e u p f ro m S 3 & S 5 .
E M I no is e

E M I E M I

re se rv e m e m o r y t h e rm al s en so r b y H P r eq u e st

re se rv e m e m o r y t h e rm al s en so r b y Hre se rv e m e m o r y t h e rm al s en so r b y H

f or t h e m ic d e te c tio n c o m p a r at o r

o r t h e m ic d et ec tio n c o m p a ra to r c h a n

f f

o r t h e m ic d et ec tio n c o m p a ra to ro r t h e m ic d et ec tio n c o m p a ra to r

F or S P I R O M R ec o v e r y

F or S P I R O M R ec o vF o r S PI R O M R ec o v

F or C P

F or C P U T y p e D e t ec t

F or C PF o r C P

C a n 't p ow er o n w it h I n te l's W L A N c a rd .

C a n 't p ow er o n w it h I n te l's W LC a n 't p ow er o n w it h I n te l's W L

o r E M I' s r eq ue st a d d 0 .1 u

o r E M I' s r eq ue sto r E M I' s r eq ue st

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt i on

b u g p or t 8 0 i s n ot u s e d d e le te

b u g p or t 8 0 i s n ot u s e db ug p o r t 8 0 is n o t u sed

E P n o s ou n d in D O S m od e. O T S # 6 0 4 31 4 i n s ta ll Q 7 2 a nd c ha n ge R 13 52 f ro m 4 .7 K t o 1 00 K ,

E P n o s ou n d in D O S m od e. O T S # 6 0 4 31 4E P n o s ou n d in D O S m od e. O T S # 6 0 4 31 4

n o i se S w ap t h e

n o i sen o i se

er y

er ye ry

U T yp e D et ec t

U T yp e D et ec tU T yp e D et ec t

3

S o

S o lu tio n D es cr ip tio n

S oS o

/

A P P _ B U T T O N _ 1 A P P _B U T T O

A P P _ B U T T O N _ 1 A P P _B U T T O N _2 a dd 1 0 0 k o hm p u ll

/ /

A P P _ B U T T O N _ 1 A P P _B U T T OA P P _ B U T T O N _ 1 A P P _B U T T O

6 0 37 7 8

6 0 37 7 86 03 7 78

p l u g in A C.

p l u g in A C. p l ug in A C.

7 7 dddd ele t D 16

7 77 7

in e

in ei ne

le m w it h + 5V S &

le m w it h + 5V S &l e m w it h + 5 V S &

r + 3V S)

r + 3V S)r + 3V S)

O T S# 60 5 6 47 rrrr em o v e R 14 82

O T S# 60 5 6 47O T S# 60 5 6 47

P r eq ues t rrrr es erv e U 5 9 , R 1 4 9 6, R 1 4 97 ,C 13 38 ,R 14 95

P r eq ues tP r e qu e st

A N c a r d .

A N c a r d .A N ca rd .

h ig h t o

h ig h t o +3 V L

h ig h t o h ig h t o
C ha ng e S T B _ L ED s ig n a l fr o m K B C p in 1 0 5 t o p in 11 5

C ha ng e C h a n g e
cccc or r ec t t h e J W W A N 1 p in 24 p ow er ra il fr o m

o r re ct th e J W W A N 1 p in 24 p o w e r r a i l f ro m

o r re ct th e J W W A N 1 p in 24 p o w e r r a i l f ro m o r re ct th e J W W A N 1 p in 24 p o w e r r a i l f ro m

+ 3V S

+ 3V S t o + 3V _ W W A N

+ 3V S + 3V S

e l et D 1 6

e l et D 1 6e l e t D 1 6

d e l et e s ig n a l o f P C I_ R S T # ,C LK _ P C I _ D EB U G ,

d e l et e d el et e

L P C _ L F R A M E # ,L P C_ L

L P C _ L F R A M E # ,L P C_ L A D 3 ,2 ,1 ,0 a nd r e m o ve C 13 17 , R 27 0

L P C _ L F R A M E # ,L P C_ LL P C _ L F R A M E # ,L P C_ L

c h a n

c h a n ge R 14 5 7 , R 14 5 8 ,R 1 0 2 7 f ro m 0 2 0 1 t o 0 40 2

c h a nc ha n

in st all Q 72 a n d c ha ng e R 1 3 5 2 f ro m 4 .7 K t o 1 0 0K ,

in st all Q 72 a n d c ha ng e R 1 3 5 2 f ro m 4 .7 K t o 1 0 0K , in st all Q 72 a n d c ha ng e R 1 3 5 2 f ro m 4 .7 K t o 1 0 0K ,

c h a n

c h a n ge C 8 9 5 f ro m 0 .1 U to 0 .0 1U

c h a nc ha n

c h a n g

c h a n g e R 13 2 3 f ro m 3 3 0 K t o 0 o hm

c h a n gch an g

e m o v e R 1 4 82

e m o v e R 1 4 82e m o ve R 14 82

S w ap t h e s ig n a l o f M I D 0 < -- > 3 , M I D 1< -- >2 t o im pr ov e

S w ap t h eS w a p th e

t h e l a y ou t ro ut i n g . (a vo id t h e t ra ce ro ut i n g u n de r

t h e l a y ou t ro ut i n g . (a vo id t h e t ra ce ro ut i n g u n de r th e T )

t h e l a y ou t ro ut i n g . (a vo id t h e t ra ce ro ut i n g u n de r t h e l a y ou t ro ut i n g . (a vo id t h e t ra ce ro ut i n g u n de r

e s er ve U 59 ,R 1 4 96 ,R 1 4 97 ,C 13 38 ,R 14 95

e s er ve U 59 ,R 1 4 96 ,R 1 4 97 ,C 13 38 ,R 14 95e s er ve U 59 ,R 1 4 96 ,R 1 4 97 ,C 13 38 ,R 14 95

c h a n ge R 12 0 2 f ro m 1 20 K t o 4 7 K

c h a nc ha n

R es

R es er v e R 1 4 98 , R 1 4 9 9, R 1 5 0 0, R 1 5 01 , R 1 5 02 , R 15 0 3 .

e r ve R 14 9 8 , R 14 9 9 , R 15 0 0 , R 15 0 1 , R 15 0 2 , R 15 03 .

R esR e s

e r ve R 14 9 8 , R 14 9 9 , R 15 0 0 , R 15 0 1 , R 15 0 2 , R 15 03 .e r ve R 14 9 8 , R 14 9 9 , R 15 0 0 , R 15 0 1 , R 15 0 2 , R 15 03 .

A dd R 15 04 w hi c h i s p ul l d o w n t o G N D a nd c o nn ec t

A dd R 15 04 w hi c h i s p ul l d o w n t o G N D a nd c o nn ec t to

A dd R 15 04 w hi c h i s p ul l d o w n t o G N D a nd c o nn ec t A dd R 15 04 w hi c h i s p ul l d o w n t o G N D a nd c o nn ec t

G P I O

G P I O 46 .

G P I OG PI O

C ha n g e p ow er p i n + 3V L fr o m p in 4 7 t o 5 1 .

n g e p ow er p in + 3V L fr o m p in 4 7 t o 5 1 .C a n 't p ow er o n w it h I n te l's W L

C haC ha

n g e p ow er p in + 3V L fr o m p in 4 7 t o 5 1 .n g e p ow er p in + 3V L fr o m p in 4 7 t o 5 1 .

a d d 0 .1 u F ( C 1 3 39 ) o n E N A B L T t o G N D n ea r R 1 1 2 2.

a d d 0 .1 ua dd 0 .1 u

2

lu ti o n D e sc ri p t io n

lu ti o n D e sc ri p t io nlu tio n D es cr ip tio n

N _2 a dd 1 00 k o h m p u l l

N _2 a dd 1 00 k o h m p u l l N _ 2 a d d 1 00 k o hm p ul l

+ 3 V L

+ 3 V L+ 3 V L

S T B _ L E D si g na l f ro m K B C p in 1 0 5 t o p in 11 5

S T B _ L E D si g na l f ro m K B C p in 1 0 5 t o p in 11 5S T B _ L E D si g na l f ro m K B C p in 1 0 5 t o p in 11 5

to + 3V _ W W A N

to + 3V _ W W A Nt o + 3 V _ W W A N

si gn al of P CI _R ST # ,C L K _P CI _D E B U G ,

si gn al of P CI _R ST # ,C L K _P CI _D E B U G ,si gn al of P CI _R ST # ,C L K _P CI _D E B U G ,

A D 3 ,2 ,1 ,0 a n d re m ov e C 1 3 17 , R 2 7 0

A D 3 ,2 ,1 ,0 a n d re m ov e C 1 3 17 , R 2 7 0A D 3 ,2 ,1 ,0 a n d re m ov e C 1 3 17 , R 2 7 0

g e R 1 4 57 , R 1 4 5 8, R 1 0 2 7 f ro m 0 2 0 1 t o 0 40 2

g e R 1 4 57 , R 1 4 5 8, R 1 0 2 7 f ro m 0 2 0 1 t o 0 40 2g e R 1 4 57 , R 1 4 5 8, R 1 0 2 7 f ro m 0 2 0 1 t o 0 40 2

g e C 89 5 f ro m 0 . 1 U t o 0 .0 1U

g e C 89 5 f ro m 0 . 1 U t o 0 .0 1Ug e C 89 5 fr om 0 .1 U t o 0 .0 1U

e R 1 3 23 f ro m 3 3 0 K t o 0 o hm

e R 1 3 23 f ro m 3 3 0 K t o 0 o hme R 1 3 23 f ro m 3 3 0 K t o 0 o hm

s i g n al o f M I D 0 < -- > 3 , M I D 1< -- >2 t o i m pr o ve

s i g n al o f M I D 0 < -- > 3 , M I D 1< -- >2 t o i m pr o ve s i g n al o f M I D 0 < -- > 3 , M I D 1< -- >2 t o i m pr o ve

g e R 1 2 02 f ro m 1 2 0K t o 4 7K

g e R 1 2 02 f ro m 1 2 0K t o 4 7Kg e R 1 2 02 f ro m 1 2 0K t o 4 7K

4 6 .

4 6 .4 6 .

F ( C 1 3 39 ) o n E N A B L T t o G N D n ea r R 1 1 2 2.

F ( C 1 3 39 ) o n E N A B L T t o G N D n ea r R 1 1 2 2. F ( C 1 3 39 ) o n E N A B L T t o G N D n ea r R 1 1 2 2.

1

th e T )

th e T )th e T )

to

toto

R ev .

R ev .P a

R ev .R e v .

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .3

0 .3

0 .30 .3

0 .3

0 .3

0 .30 .3

0 .4

0 .42 2

0 .40 .4

0 .4

0 .4

0 .40 .4

1 9

1 9 CCCC R T

1 91 9

1 7

1 7

1 71 7

1 8

1 8 L C D

1 81 8

1 8

1 8

1 81 8

A A

R T

R TR T

L C D

L C DL C D

5

3 /

3 / 24

2 4 CCCC om p a l

3 /3 /

2 424

5 /

5 / 18

1 8 CCCC om p a l

5 /5 /

1 818

o m p a l FFFF o r E M I's r e qu es t

o m p a lo m p a l

o m p a l F in e tu ne L ED p ow er o n s

o m p a lo m p a l

o r E M I' s r eq ue st C ha ng e C 2

o r E M I' s r eq ue sto r E M I' s r eq ue st

F in e t u n e L E D p ow er o n s eq u e nce .

F in e t u n e L E D p ow er o n sF in e t u n e L E D p ow er o n s

4

C ha ng e C 2 32 , C 23 3, C 23 6 f ro m 6 .8 p F t o 1 8p F.

C ha ng e C 2C h a n g e C 2

eq ue nc e . C h

eq ue nc e .eq ue n c e.

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C h a ng e C 67 6 t o 0 .2 2 u F a n d C 6 8 2 t o 2 .2 u F .

a n ge C 67 6 t o 0 . 2 2 u F a n d C 6 8 2 t o 2 .2 u F.

C hC h

a n ge C 67 6 t o 0 . 2 2 u F a n d C 6 8 2 t o 2 .2 u F.a ng e C 6 7 6 t o 0 .2 2 u F a nd C 68 2 t o 2 .2 u F.

2007/08/02 2009/09/15

Compal Secret Data

3 2 , C 2 3 3 , C 2 3 6 f ro m 6 .8 p F t o 1 8p F .

3 2 , C 2 3 3 , C 2 3 6 f ro m 6 .8 p F t o 1 8p F .3 2 , C 2 3 3, C 2 3 6 f ro m 6 .8 pF t o 1 8 p F .

Deciphered Date

2

0 .4

0 .4

0 .40 .4

0 .5

0 .5

0 .50 .5

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-1

LA-6161P

1

41 41T uesday, M ay 18, 2010

0.5