Compal LA-6161P Fossil 2.0 UMA Schematic
A
1 1
B
C
D
E
Compal Confidential
Schematics Document
2 2
INTEL Auburndale BGA with IBEX core logic
Fo
3 3
ssil 2.0 UMA
LA-6161P
2010-05-18
REV:0.5
4 4
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/09/15 2009/09/03
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
LA-6161P
E
1 41Tuesday, May 18, 2010
0.5
A
Compal Confidential
File Name : LA-6161P
B
C
Fossil 2.0 UMA
D
XDP Conn.
Page 4
E
Accelerometer
LI S30 2DLTR
DD R3-SO-DIMM X 1DDR3 1066/1333MHz 1.5V
Mobile
1 1
Single Channel
BANK 2 , 3
Arrandale CPU
Page 9
Fan C ontrol
Page 22
Page 4
BG A 1288pins
LVDS
Display port
Page 18
Page 17
DDI_D
FDI
Page 4,5,6,7,8
DM I X4
BT(SoftBreeze) Conn USB x 1
page 26
CRT
Page 19
2 2
WWAN
+SIM Card
USB*1
Page 22
USB2.0
PCI-E BUS
10/100/1 000 LAN
RT L8151DH-GR
Page 21
3 3
RJ45 CONN
Page 21
WLAN Card
PCIE*1
Page 22
DDI
USB2.0
Intel Ibex Peak M
Azalia
10 71pi ns
25mm*27mm
SATA0
Page 11,12,13,14,15,16
ONFI Interface
USB conn x 3(For I/O)
page 24
CardReader Controller
RealTe k RTS5159
USB x1(Camara)
FPR conn x1
Audio CKT
IDT 92HD80
Page 18
Page 19
Page 23
daughter board
SD/MM C Slot
sub/B Page 3
daughter board
Audio Jack
sub/B Page 2
SPI BUS
RTC CKT.
Page 11
Power OK CKT.
4 4
Power On/Off CKT.
DC/DC Interface CKT.
Page 29
Page 25
Page 30
LED
LED Board
Page 20
A
Touch Pad CONN.
Page 25
SP I ROM 4 M B
MX25L6445EM2I-10G
B
Page 27
SMSC KBC 1098
page 28
Int.KBD
Page 25
SPI BUS
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/09/15 2009/09/03
Compal Secret Data
Deciphered Date
D
Page 19
CK505
Clock Generator
SL G8SP5 85V T R
Page 11
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
LA-6161P
E
2 41Tues day, May 18, 2010
0.5
SATA HDD Connector
A
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1
( O MEANS ON X MEANS OFF )
+RTCVCC
power
plane
O
O
O
O
O
O
+B
+3VL +0.75V
O
O
O
O
O
X
+5VALW
+3VALW
O
O
O
O
X
X X X
+1.5V
O
X X
X
+5VS
+3VS
+1.5VS
+VCCP
+CPU_CORE
1.05VS
+
+1.8VS
OO
OO
X
X
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
ULV@ : means just install for ULV CPU
CONN@ : means ME part.
Lay out Note s
L
07/ 24 upda te
: Q ues ti on Are a Mar k.( Wait che ck)
Install below 45 level BOM structure for ver. 0.1
4
5@ : means just put it in the BOM of 45 level.
Install below 43 level BOM structure for ver. 0.1
DEBUG@ : means just build when PCIE port 80 CARD function enable.
Remove before MP
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
SMSC1098
Calpella
Calpella
Calpella
BATT
V
X
X
X
THERMAL
SODIMM CLK CHIP
XDP G-SENSOR
X
X X
V V
X
X
X X
MINI CARD
X
V V
X
X
X X
DOCK
X
V
X
X
SENSOR
NIC
X X
X
V
X
X
X
V
X
V
X
V
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/09/15 2009/09/03
A
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Notes List
LA-6161P
3 41Tues day, May 18, 2010
0.5
Layout rule 1 0mil w idth ：trace
length < 0.5 ", spa cing 20mil
A A
H_ PECI<14>
to power; PU to VCCP at power side also
H_ PROCH OT#<37>
H_T HERM TRIP#<14>
H_ CPUR ST#
H_ PM_S YNC<13>
H_ CPU PW RGD
H_ CPU PW RGD< 14>
B B
PM_ DRAM _PWR GD<13>
from power
VTT PWRG OOD<29>
BUF _PLT_R ST#< 14>
C C
PM_ PWRB TN#_R
1
R22 0_040 2_1%
1 2
R52 0_040 2_1%
1 2
R74 9.9_0 402_1%
1 2
R94 9.9_0 402_1%
1 2
T48PA D
R1 4
1 2
0_04 02_5%
R1 5
1 2
0_04 02_5%
R1 7
1 2
0_04 02_5%
R1 8
@
1 2
0_04 02_5%
R1 9
1 2
0_04 02_5%
R2 1
1 2
0_04 02_5%
R2 2
1 2
0_04 02_5%
R2 6
1 2
0_04 02_5%
R3 2
1 2
0_04 02_5%@
1 2
1.5K _0402 _1%
750_ 0402_1%
@
1 2
R2 0 1K_ 0402_5%
H_CO MP3
H_CO MP2
H_CO MP1
H_CO MP0
TP_ SKTOCC#
H_ CATE RR#
H_P ECI_I SO
H_ PRO CHOT# _D
H_T HERM TRIP# _R
H_ CPUR ST#_ R
H_ PM_ SYNC _R
SYS _AGE NT_P WROK
VC CPW RGOO D_0
VD DPW RGO OD_R
H_ PWRG D_XD P_RH_P WRGD _XDP
PLT _RST#_R
R3 3
12
R3 5
+VC CP
U1 B
AD71
COMP3
AC70
COMP2
AD69
COMP1
AE66
COMP0
M71
PROC_DETECT
N61
CATERR#
N19
PECI
N67
PROCHOT#
N17
THERMTRIP#
N70
RESET_OBS#
M17
PM_SYNC
AM7
VCCPWRGOOD_1
Y67
VCCPWRGOOD_0
AM5
SM_DRAMPWROK
H15
VTTPWRGOOD
Y70
TAPPWRGOOD
G3
RSTIN#
INT EL_A UBURN DALE _1288
2nd So urce :
SV - i 5-540M CPU : 2.53 G (K0 )
SV - i 5-450M CPU : 2.4G (K0)
SV - i 3-350M CPU : 2.26G (K0)
SV- i3 -370M CPU : 2.4G (K0)
ULV -U 3400 C PU : 1 .06G (K0)
Misc
Thermal Power Management
Intel S3 power reduction circuit for Calpella. 11/09
VD DPW RGO OD_R
1 2
R1 2 1.5K_ 0402_1%
1 2
R1 3 750_04 02_1%
Clocks
DDR3
Misc
JTAG & MBP
2
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
VC CP_1. 5VSP WRG D < 29>
AK7
AK8
K71
J70
L21
J21
Y2
W4
BJ12
BV33
BP39
BV40
AV66
AV64
U71
U69
T67
N65
P69
T69
T71
P71
T70
W71
J69
J67
J62
K65
K62
J64
K69
M69
CL K_CP U_BC LK
CLK _CPU_ BCLK #
CLK _CPU_ XDP
CLK _CPU_ XDP#
CLK_EX P
CLK_ EXP#
SM_ DRAMR ST#
SM_ RCOMP0
SM_ RCOMP1
SM_ RCOMP2
PM_EXTTS#0
PM_EXTTS#1
XDP _PRD Y#
XDP _PREQ#
XDP _TCK
XDP_TMS
XDP_TR ST#
XDP _TDI
XDP _TDO
XDP _TDI_M
XDP _DBRES ET#
XDP_B PM#0
XDP_B PM#1
XDP_B PM#2
XDP_B PM#3
XDP_B PM#4
XDP_B PM#5
XDP_B PM#6
XDP_B PM#7
R1 6
1 2
R1 493 0_ 0402_5%@
R1 494 0_ 0402_5%@
0.1U _0402 _16V4Z
CLK _CPU_ BCLK < 14>
CLK _CPU_ BCLK # < 14>
CLK_EX P <12>
CLK_EX P# <12>
CL K_DP <12 >
CLK _DP# <1 2>
T49 PA D
0_04 02_5%
PM_EX TTS#1_R <9>
1 2
1 2
reserv e for ESD, Compal SI 1/19
ESD re que st to add
+VC CP
1
C1
2
@
CF G12<5>
CF G13<5>
CF G14<5>
CF G15<5>
3
from DDR
XDP _PRE Q#_R
X DP_PR DY#_ R
XDP_B PM#0
XDP_B PM#1
XDP_B PM#2
XDP_B PM#3
XDP_B PM#4
XDP_B PM#5
XDP_B PM#6
XDP_B PM#7
H_ CPU PW RGD
PM_ PWRB TN#_R<13>
H_P WRGD _XDP
Add te st p oints
Intel S3 power reduction circuit for Calpella. 11/09
XDP _PRE Q#_R
CF G17<5>
CF G16<5>
1 2
1 2
1 2
1 2
R3 6
1 2
1K_ 0402_5%
R3 7
1 2
0_04 02_5%
X DP_PR DY#_ R
XDP _BPM#4_R
R4 30_04 02_5%
XDP _BPM#5_R
R4 80_04 02_5%
XDP _BPM#6_R
R4 00_04 02_5%
XDP _BPM#7_R
R4 10_04 02_5%
H_ CPU PW RGD_ R
PM_ PWRB TN#_R
T112PA D
T113PA D
XDP _TCK
R2 3 0_04 02_5%
1 2
R2 4 0_04 02_5%@
1 2
R2 5 0_04 02_5%
1 2
R2 7 0_04 02_5%@
1 2
R2 8 0_04 02_5%
1 2
R2 9 0_04 02_5%@
1 2
R3 0 0_04 02_5%
1 2
R3 1 0_04 02_5%@
1 2
PWM Fan Control circuit
SM_ DRAMR ST#
R1 092
100K _0402_5 %
@
4
R4 6 0_040 2_5%
1 2
12
2
CPU XDP Connector
JP4
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAM TE_BSH- 030-01-L-D -A CO NN@
R1 093
@
61
Q52A
2N70 02DW -7-F_S OT363-6
C6 470P _0402_5 0V7K
1 2
1K_ 0402_5%
12
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
+1.5 V
DRA MRST# <9>
PC H_D DR_RS T <14>
2
GND1
4
6
8
GND3
10
12
14
GND5
16
18
20
GND7
22
24
26
GND9
28
30
32
GND11
34
36
38
GND13
40
42
44
46
48
50
GND15
52
TD0
54
TRST#
56
TDI
58
TMS
60
GND17
CLK _CPU_ XDP
CLK _CPU_ XDP#
XDP _RST#_R
XDP _DBR ESET#_R
XDP _TDO
XDP_TR ST#
XDP _TDI
XDP_TMS
XDP _RST#_R
+5VS
CF G8 <5>
CF G9 <5>
CF G0 <5>
CF G1 <5>
CF G2 <5>
CF G3 <5>
CF G10 <5>
CF G11 <5>
CF G4 <5>
CF G5 <5>
CF G6 <5>
CF G7 <5>
+V CCP
1K_ 0402_5%@
R3 8
1 2
1 2
R3 9 0_040 2_5%
@
1 2
R4 2 0_0402_ 5%
PLT_ RST#
H_ CPUR ST#
XDP _DBRES ET#
5
+3VS
R3 4
1K_ 0402_5%
1 2
PLT_R ST# <14, 21,22, 27>
XDP _DBRESE T# <13>
DDR3 Compensation Signals
SM_ RCOMP0
SM_ RCOMP1 H_C ATER R#
SM_ RCOMP2
D D
1 2
R5 2 100_04 02_1%
1 2
R5 6 24.9_0 402_1%
1 2
R5 8 130_04 02_1%
Layout Note:Please these
resist ors near Processor
1
Processor Pullups
R4 4 49.9 _0402_1 %
H_ PRO CHOT# _D
H_ CPUR ST#_ R
1 2
1 2
R4 5 68_040 2_5%
1 2
R4 7 68_040 2_5%@
+VC CP
DDR Pullups
PM_EXTTS#0
1 2
R1
PM_EXTTS#1
1 2
R3
011 2 R em ove unin stall part s
XDP_TR ST#
Close to XDP
XDP _TDO
2
10K _0402_5%
10K _0402_5%
1 2
R5 9 51_04 02_5%
1 2
R1 0 51_04 02_5%
This s hall place near XDP
+V CCP
+V CCP
R8 96
10K _0402_5%
1 2
Compal Secret Data
FAN _PWM
FAN _PWM<28>
+VC CP
Q26
H_ PROC HOT#
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PMBT3 904_SOT23
+3VS
CBE
123
2008/09/15 2009/09/03
1
2
Deciphered Date
4
+3VS
5
U5 0
P
INB
O
INA
G
TC7 SH00F UF_S SOP5
3
R8 91 0_04 02_5%
for RF
12
C1 316
4
1
@
2
47P _0402_50 V8J
C3
1 2
0.1U _0402 _10V6K@
JF AN1
1
1
2
4
2
G1
3
5
3
G2
ACE S_85 204-03001
CO NN@
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
Compal Electronics, Inc.
Auburndale(1/5)-Thermal/XDP
LA -6 161 P
5
4 4 1Tues day, May 18, 2010
0. 5
1
2
3
4
5
U1 A
DMI _CRX_PTX _N0<13>
DMI _CRX_PTX _N1<13>
DMI _CRX_PTX _N2<13>
DMI _CRX_PTX _N3<13>
DMI_C RX_PTX_P 0<13>
A A
B B
DMI_C RX_PTX_P 1<13>
DMI_C RX_PTX_P 2<13>
DMI_C RX_PTX_P 3<13>
DMI _CTX_PRX _N0<13>
DMI _CTX_PRX _N1<13>
DMI _CTX_PRX _N2<13>
DMI _CTX_PRX _N3<13>
DMI_C TX_PRX_P 0<13>
DMI_C TX_PRX_P 1<13>
DMI_C TX_PRX_P 2<13>
DMI_C TX_PRX_P 3<13>
FDI _CTX_ PRX_N0< 13>
FDI _CTX_ PRX_N1< 13>
FDI _CTX_ PRX_N2< 13>
FDI _CTX_ PRX_N3< 13>
FDI _CTX_ PRX_N4< 13>
FDI _CTX_ PRX_N5< 13>
FDI _CTX_ PRX_N6< 13>
FDI _CTX_ PRX_N7< 13>
FDI _CTX_PRX _P0<13>
FDI _CTX_PRX _P1<13>
FDI _CTX_PRX _P2<13>
FDI _CTX_PRX _P3<13>
FDI _CTX_PRX _P4<13>
FDI _CTX_PRX _P5<13>
FDI _CTX_PRX _P6<13>
FDI _CTX_PRX _P7<13>
FD I_F SYN C0< 13>
FD I_F SYN C1< 13>
FD I_I NT<13>
FD I_L SYN C0<13>
FD I_L SYN C1<13>
FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7
FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7
FD I_F SYN C0
FD I_F SYN C1
FD I_I NT
FD I_L SY NC0
FD I_L SY NC1
F7
K8
F9
K9
H17
K15
J13
F10
G17
M15
G13
J11
L2
N7
M4
P1
N10
R7
U7
W8
K1
N5
N2
R2
N9
R8
U6
W10
AC7
AC9
AB5
AA1
AB2
J8
J4
J6
J2
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
PEG_RCOMPO
DMI Intel(R) FDI
PCI EXPRESS -- GRAPHICS
C C
INT EL_A UBURN DALE _1288
PEG_ICOMPI
PEG_ICOMPO
PEG_RBIAS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
B12
A13
D12
B11
G40
G38
H34
P34
G28
H25
H24
D29
B26
D26
B23
D22
A20
D19
A17
B14
F40
J38
G34
M34
J28
G25
K24
B28
A27
B25
A24
B21
B19
B18
B16
D15
N40
L38
M32
D40
A38
G32
B33
B35
L30
A31
B32
L28
N26
M24
G21
J20
L40
N38
N32
B39
B37
H32
A34
D36
J30
B30
D33
N28
M25
N24
F21
L20
EXP _ICOMPI
EXP _RBIAS
49.9 _0402_1 %
R6 4
1 2
R6 5
1 2
750_ 0402_1%
U1 E
CF G0
CF G0<4>
CF G1<4>
CF G2<4>
CF G3<4>
CF G4<4>
CF G5<4>
CF G6<4>
CF G7<4>
CF G8<4>
CF G9<4>
CF G10<4>
CF G11<4>
CF G12<4>
CF G13<4>
CF G14<4>
CF G15<4>
CF G16<4>
CF G17<4>
T50P AD T51 PA D
CF G1
CF G2
CF G3
CF G4
CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17
AV71
AW70
AY69
BB69
AL4
CFG[0]
AM2
CFG[1]
AK1
CFG[2]
AK2
CFG[3]
AK4
CFG[4]
AJ2
CFG[5]
AT2
CFG[6]
AG7
CFG[7]
AF4
CFG[8]
AG2
CFG[9]
AH1
CFG[10]
AC2
CFG[11]
AC4
CFG[12]
AE2
CFG[13]
AD1
CFG[14]
AF8
CFG[15]
AF6
CFG[16]
AB7
CFG[17]
AU1
RSVD_TP[0]
T4
RSVD15
T2
RSVD16
U1
RSVD17
V2
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
D8
RSVD23
B7
RSVD24
A10
RSVD26
B9
RSVD27
C5
RSVD_NCTF[7]
A6
RSVD_NCTF[8]
E3
RSVD_NCTF[6]
F1
RSVD_NCTF[5]
INT EL_A UBURN DALE _1288
RSVD_NCTF[3]
RSVD_NCTF[4]
RSVD_NCTF[2]
RSVD_NCTF[1]
RESERVED
DC_TEST_BV71
DC_TEST_BV69
DC_TEST_BV68
DC_TEST_BV5
DC_TEST_BV3
DC_TEST_BV1
DC_TEST_BT71
DC_TEST_BT69
DC_TEST_BT3
DC_TEST_BT1
DC_TEST_BR71
DC_TEST_BR1
DC_TEST_E71
DC_TEST_C71
DC_TEST_C69
DC_TEST_A71
DC_TEST_A69
DC_TEST_A68
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
RSVD_TP[2]
RSVD_TP[1]
RSVD62
RSVD63
RSVD64
RSVD65
DC_TEST_E1
DC_TEST_C3
DC_TEST_A5
W66
W64
AC69
AC71
AA71
AA69
R66
R64
BT5
BR5
BV6
BV8
AV69
AK71
AN69
AP66
AH66
AK66
AR71
AM66
AK69
AU71
AT70
AR69
AU69
AT67
AP2
AN7
AV4
AU2
BE69
BE71
BV71
BV69
BV68
BV5
BV3
BV1
BT71
BT69
BT3
BT1
BR71
BR1
E71
E1
C71
C69
C3
A71
A69
A68
A5
T116 P AD
T117 P AD
T118 P AD
T119 P AD
T120 P AD
T52 PA D
VSS _NCT F2_R <8>
VSS _NCT F6_R <8>
VSS _NCT F1_R <8>
VSS _NCT F7_R <8>
CFG Straps for PROCESSOR
CF G0
R6 8 3.01 K_040 2_1%@
1 2
PCI-Ex press Configuration Select
CFG0
Not ap plica ble f or Clarksfield Processor
CF G3
CFG3-P CI Ex press Static Lane Reversal
CFG3
CF G4
D D
ES1 sa mple n eed ne gative voltage
ES2 sa mple c ontact to GND
CFG4-D isplay Port Presence
CFG4
1: Single PEG
0: Bif urcation enabled
R6 9 3.01 K_040 2_1%@
1 2
1: Nor mal Operation
0: Lan e Numbers Reversed
15 -> 0, 14 ->1, .....
R7 0 3.01K _0402_1%
1 2
1: Dis abled ; No Physical Display Port
attach ed to Embedded Display Port
0: Ena bled; An external Display Port
device is c onnected to the Embedded
Display Port
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/09/03
Compal Secret Data
Deciphered Date
4
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
Compal Electronics, Inc.
Auburndale(2/5)-DMI/PEG/FDI
LA -6 161 P
5
5 4 1Tues day, May 18, 2010
0. 5
1
2
3
4
5
AW2
BV10
BR10
BT12
BT15
BV15
BV12
BP12
BV17
BU16
BP15
BU19
BV22
BT22
BP19
BV19
BV20
BT20
BT48
BV48
BV50
BP49
BT47
BV52
BV54
BT54
BP53
BU53
BT59
BT57
BP56
BT55
BU60
BV59
BV61
BP60
BR66
BR64
BR62
BT61
BN68
BL69
BJ71
BF70
BG71
BC67
BK70
BK67
BD71
BD69
BV43
BV41
BV24
BU46
BT40
BT41
U1D
BU33
SB_CK[0]
BV34
SB_CK#[0]
BA2
SB_DQ[0]
SB_DQ[1]
BD1
SB_DQ[2]
BE4
SB_DQ[3]
AY1
SB_DQ[4]
BC2
SB_DQ[5]
BF2
SB_DQ[6]
BH2
SB_DQ[7]
BG4
SB_DQ[8]
BG1
SB_DQ[9]
BR6
SB_DQ[10]
BR8
SB_DQ[11]
BJ4
SB_DQ[12]
BK2
SB_DQ[13]
BU9
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY - B
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
BT26
BV38
BU39
BT24
BP46
BT43
BV45
BU49
BB4
BL4
BT13
BP22
BV47
BV57
BU65
BF67
BE2
BM3
BU12
BT19
BT52
BV55
BU63
BG69
BD4
BN4
BV13
BT17
BT50
BU56
BV62
BJ69
BT34
BP30
BV29
BU30
BV31
BT33
BT31
BP26
BV27
BT27
BU42
BU26
BT29
BT45
BV26
BU23
U1C
A A
B B
C C
DD R_A _D[0 ..63]< 9>
DD R_A_B S0<9>
DD R_A_B S1<9>
DD R_A_B S2<9>
DD R_A_ CAS#<9>
DD R_A_ RAS#<9>
DD R_A_ WE#<9>
DD R_A _D0
DD R_A _D1
DD R_A _D2
DD R_A _D3
DD R_A _D4
DD R_A _D5
DD R_A _D6
DD R_A _D7
DD R_A _D8
DD R_A _D9
DD R_A _D10
DD R_A _D11
DD R_A _D12
DD R_A _D13
DD R_A _D14
DD R_A _D15
DD R_A _D16
DD R_A _D17
DD R_A _D18
DD R_A _D19
DD R_A _D20
DD R_A _D21
DD R_A _D22
DD R_A _D23
DD R_A _D24
DD R_A _D25
DD R_A _D26
DD R_A _D27
DD R_A _D28
DD R_A _D29
DD R_A _D30
DD R_A _D31
DD R_A _D32
DD R_A _D33
DD R_A _D34
DD R_A _D35
DD R_A _D36
DD R_A _D37
DD R_A _D38
DD R_A _D39
DD R_A _D40
DD R_A _D41
DD R_A _D42
DD R_A _D43
DD R_A _D44
DD R_A _D45
DD R_A _D46
DD R_A _D47
DD R_A _D48
DD R_A _D49
DD R_A _D50
DD R_A _D51
DD R_A _D52
DD R_A _D53
DD R_A _D54
DD R_A _D55
DD R_A _D56
DD R_A _D57
DD R_A _D58
DD R_A _D59
DD R_A _D60
DD R_A _D61
DD R_A _D62
DD R_A _D63
BF11
BE11
BH13
BN11
BG17
BK15
BG15
BH17
BK17
BN20
BN17
BK25
BH25
BJ20
BH21
BG24
BG25
BJ40
BM43
BF47
BF48
BN40
BH43
BN44
BN47
BN48
BN51
BH53
BJ55
BH48
BJ48
BM53
BN55
BF55
BN57
BN65
BJ61
BF57
BJ57
BK64
BK61
BJ63
BF64
BB64
BB66
BJ66
BF65
AY64
BC70
BT38
BH38
BF21
BK43
BL38
BF38
AT8
SA_DQ[0]
AT6
SA_DQ[1]
BB5
SA_DQ[2]
BB9
SA_DQ[3]
AV7
SA_DQ[4]
AV6
SA_DQ[5]
BE6
SA_DQ[6]
BE8
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
BK5
SA_DQ[10]
SA_DQ[11]
BF9
SA_DQ[12]
BF6
SA_DQ[13]
BK7
SA_DQ[14]
BN8
SA_DQ[15]
SA_DQ[16]
BN9
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
BK9
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
BM34
BP35
BF20
BK36
BH36
BK24
BH40
BJ47
BF43
BL47
BB10
BJ10
BM15
BN24
BG44
BG53
BN62
BH59
AY5
BJ7
BN13
BL21
BH44
BK51
BP58
BE62
AY7
BJ5
BL13
BN21
BK44
BH51
BM60
BE64
BT36
BP33
BV36
BG34
BG32
BN32
BK32
BJ30
BN30
BF28
BH34
BH30
BJ28
BF40
BN28
BN25
DD R_A_ DM0
DD R_A_ DM1
DD R_A_ DM2
DD R_A_ DM3
DD R_A_ DM4
DD R_A_ DM5
DD R_A_ DM6
DD R_A_ DM7
DD R_A_ DQS# 0
DD R_A_ DQS# 1
DD R_A_ DQS# 2
DD R_A_ DQS# 3
DD R_A_ DQS# 4
DD R_A_ DQS# 5
DD R_A_ DQS# 6
DD R_A_ DQS# 7
DD R_A _DQS 0
DD R_A _DQS 1
DD R_A _DQS 2
DD R_A _DQS 3
DD R_A _DQS 4
DD R_A _DQS 5
DD R_A _DQS 6
DD R_A _DQS 7
DDR_ A_M A0
DDR_ A_M A1
DDR_ A_M A2
DDR_ A_M A3
DDR_ A_M A4
DDR_ A_M A5
DDR_ A_M A6
DDR_ A_M A7
DDR_ A_M A8
DDR_ A_M A9
DDR_ A_MA 10
DDR_ A_MA 11
DDR_ A_MA 12
DDR_ A_MA 13
DDR_ A_MA 14
DDR_ A_MA 15
M_ CLK_D DR0 <9>
M_ CLK_D DR#0 <9>
DDR_ CKE0 _DIM MA <9>
M_ CLK_D DR1 <9>
M_ CLK_D DR#1 <9>
DDR_ CKE1 _DIM MA <9>
DDR_ CS0_ DIMM A# <9>
DDR_ CS1_ DIMM A# <9>
M_ODT 0 <9>
M_ODT 1 <9>
DD R_A_ DM[0 ..7] <9>
DD R_A_ DQS# [0..7 ] <9>
DD R_A _DQS [0..7 ] <9>
DDR_ A_MA [0.. 15] <9>
INT EL_A UBURN DALE _1288
D D
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/09/03
INT EL_A UBURN DALE _1288
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
4
Da te: She et o f
Compal Electronics, Inc.
Auburndale(3/5)-DDR3
LA -61 61P
5
6 4 1Tue sday , Ma y 18, 2010
0. 5
1
+GF X_CORE
22U_ 0805_ 6.3V6M
C1 7
1
2
C2 14
1
2
C2 18
1
2
C3 80
1
2
10U_ 0805_ 6.3V6M
1
2
1U_0 402_6 .3V6K
C3 5
10U_ 0805_6. 3V6M
1
2
+C PU_C ORE
@
+C PU_C ORE
1U_0 402_6 .3V6K
1
2
1
1U_0 402_6 .3V6KZ
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C3 0
C6 1
C5 5
C1 8
C2 13
C2 17
C2 21
1
2
+V CCP
1
2
C6 16
22U_ 0805_ 6.3V6M
C1 9
1
2
1
2
1U_0 402_6 .3V6K
C3 6
1
2
47P _0402_50 V8J
1U_0 402_6 .3V6K
10U_ 0805_ 6.3V6M
1
2
10U_ 0805_6. 3V6M
for RF
@
C6 23
1
2
C3 1
C6 2
C5 6
1
2
1U_0 402_6 .3V6K
U1 G
AN32
VAXG1
AN30
VAXG2
AN28
VAXG3
AN26
VAXG4
AN24
VAXG5
AN23
VAXG6
AN21
VAXG7
AN19
VAXG8
AL32
VAXG9
AL30
VAXG10
AL28
VAXG11
AL26
VAXG12
AL24
VAXG13
AL23
VAXG14
AL21
VAXG15
AL19
VAXG16
AK14
VAXG17
AK12
VAXG18
AJ10
VAXG19
AH14
VAXG20
AH12
VAXG21
AF28
VAXG22
AF26
VAXG23
AF24
VAXG24
AF23
VAXG25
AF21
VAXG26
AF19
VAXG27
AF17
VAXG28
AF15
VAXG29
AF14
VAXG30
AD28
VAXG31
AD26
VAXG32
AD24
VAXG33
AD23
VAXG34
AD21
VAXG35
AD19
VAXG36
AD17
VAXG37
W21
VTT1_1
W19
VTT1_2
U21
VTT1_3
U19
VTT1_4
U17
VTT1_5
U15
VTT1_6
U14
VTT1_7
U12
VTT1_8
R21
VTT1_9
R19
VTT1_10
R17
VTT1_11
AK62
VCAP2_1
AK60
VCAP2_2
AK59
VCAP2_3
AH60
VCAP2_4
AH59
VCAP2_5
AF60
VCAP2_6
AF59
VCAP2_7
AD60
VCAP2_8
AD59
VCAP2_9
AB60
VCAP2_10
AB59
VCAP2_11
AA60
VCAP2_12
AA59
VCAP2_13
W60
VCAP2_14
W59
VCAP2_15
U60
VCAP2_16
U59
VCAP2_17
R60
VCAP2_18
R59
VCAP2_19
INT EL_A UBURN DALE _1288
47P _0402_50 V8J
47P _0402_50 V8J
C5 7
1
@
2
1U_0 402_6 .3V6K
C6 43
C6 17
1
1
2
2
47P _0402_50 V8J
C5 8
1
@
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C6 45
1
2
1U_0 402_6 .3V6K
C1 6
1
2
1U_0 402_6 .3V6K
C1 79
1
2
1U_0 402_6 .3V6K
C2 15
1
2
1U_0 402_6 .3V6K
C2 19
1
2
10U_ 0805_ 6.3V6M
C2 9
1U_0 402_6 .3V6K
C3 4
1
2
10U_ 0805_6. 3V6M
C6 0
12P _0402_5 0V8J
47P _0402_50 V8J
C6 15
+
330U _D2_2 .5VM_ R6M
C1 313
1
2
1
2
1
2
+V CCP
1U_0 402_6 .3V6K
C3 2
for RF
1
2
12P _0402_5 0V8J
47P _0402_50 V8J
1
2
+VC AP2
12P _0402_50 V8J
C1 321
@
@
1U_0 402_6 .3V6K
1
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C2 12
1
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C2 16
1
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C2 20
1
2
10U_ 0805_ 6.3V6M
C2 8
1
2
1U_0 402_6 .3V6K
C3 3
1
1
2
2
10U_ 0805_6. 3V6M
C5 9
1
1
2
2
12P _0402_5 0V8J
C1 322
1
1
@
2
2
47P _0402_50 V8J
C5 3
C5 4
1
1
@
2
2
330U _D2_2 .5VM_ R6M
1
1
C1 312
+
2
2
A A
B B
C C
+GF X_CORE
12P _0402_50 V8J
C1 325
C1 326
1
@
@
2
for RF
+GF X_CORE
12P _0402_5 0V8J
C1 319
C1 320
1
1
@
@
2
2
D D
+V CCP
47P _0402_50 V8J
C5 2
C5 1
1
1
@
@
2
2
Follow SCH check list
GRAPHI CS
PEG & DMI
POWER
+C PU_C ORE
1U_0 402_6 .3V6K
C3 81
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C6 44
C6 46
1
1
2
2
SENSE
LINES
GRA PHI CS VIDs
DDR3 - 1.5V RAILS
1U_0 402_6 .3V6K
C3 82
1
2
1U_0 402_6 .3V6K
C6 47
1
2
VAXG_SENSE
VSSAXG_SENSE
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36
VTT0_DDR
VTT0_DDR[1]
VTT0_DDR[2]
VTT0_DDR[3]
VTT0_DDR[4]
VTT0_DDR[5]
VTT0_DDR[6]
VTT0_DDR[7]
VTT0_DDR[8]
VTT0_DDR[9]
VTT1_12
VTT1_13
VTT1_14
VTT1_15
VTT1_16
VTT1_17
VTT1_18
VTT1_19
VTT1_20
VTT1_21
1U_0 402_6 .3V6K
C5 33
1
1
2
2
1U_0 402_6 .3V6K
C6 49
1
2
2
AF12
AF10
AF71
AG67
AG70
AH71
AN71
AM67
AM70
AH69
AL71
AL69
BU40
BU35
BU28
BN38
BM25
BL30
BJ38
BH32
BH28
BG43
BF16
BF15
BD35
BD33
BD32
BD30
BD28
BD26
BD24
BD23
BD21
BD19
BD17
BD15
BB35
BB33
BB32
BB30
BB28
BB26
BB24
BB23
BB21
BB19
BB17
BB15
AW32
AW30
AW28
AW26
AW24
AW23
AW21
AW19
AW17
AW15
AD15
AD14
AD12
AB12
AA12
W17
W15
W14
W12
R15
1U_0 402_6 .3V6K
C5 34
1
2
1U_0 402_6 .3V6K
C6 50
1
2
2
1 2
R7 00 4.7K _0402 _5%
VCC _AXG_ SENSE
VSS_A XG_SENS E
GFX VR_V ID_0 <39>
GFX VR_V ID_1 <39>
GFX VR_V ID_2 <39>
GFX VR_V ID_3 <39>
GFX VR_V ID_4 <39>
GFX VR_V ID_5 <39>
GFX VR_V ID_6 <39>
R7 05 4.7K _0402 _5%@
1 2
GFX VR_EN < 39>
GFX _DPR SLPVR
R1 478 0_ 0402_5%
1U_0 402_6 .3V6K
C2 0
1
2
330U _B2_ 2.5VM_R15M
C2 5
1
+
@
2
1U_0 402_6 .3V6K
C4 2
1
2
10U_ 0805_ 6.3V6M
C4 6
1
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C3 83
C6 13
1
1
2
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C6 52
C6 48
1
1
2
2
12
1U_0 402_6 .3V6K
C2 1
1
2
22U_ 0805_ 6.3V6M
C2 6
1
2
+VT T_DDR
1U_0 402_6 .3V6K
C4 3
10U_ 0805_ 6.3V6M
C4 7
1U_0 402_6 .3V6K
C6 14
1U_0 402_6 .3V6K
C6 53
1
2
GFX VR_E N
VCC _AXG_S ENSE <39>
VSS_A XG_SENS E <39>
+1.5 VS_C PU_V DDQ
1U_0 402_6 .3V6K
C2 2
1
1
2
2
22U_ 0805_ 6.3V6M
C2 7
1
2
1U_0 402_6 .3V6K
C4 4
1
1
2
2
10U_ 0805_ 6.3V6M
C4 8
1
1
2
2
1U_0 402_6 .3V6K
C6 12
1
1
2
2
1U_0 402_6 .3V6K
C6 51
1
1
2
2
+V CCP
12/05 HP
GFX VR_IMO N <39>
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C2 3
C2 4
1
2
+V CCP
12
L31
0_08 05_5%
+V CCP
10U_ 0805_ 6.3V6M
C4 9
1
2
1U_0 402_6 .3V6K
3
1 2
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
J55
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
1U_0 402_6 .3V6K
1
1
C6 8
2
2
R1 483 4.7 K_04 02_5%@
1 2
R1 484 4. 7K_04 02_5% @
POWER
CPU CO RE SUP PLY
add 7p cs Cap s to f ollow Desig n guide add 7p cs Cap s to f ollow Desig n guide
1U_0 402_6 .3V6K
1
1
C6 9
1U_0 402_6 .3V6K
C7 1
C7 0
2
2
1U_0 402_6 .3V6K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
GFX _DPR SLPVR
+C PU_C ORE
AF57
AF55
AF53
AF51
AF50
AF48
AF46
AF44
AF42
AF41
AD55
AD51
AD48
AD44
AD41
AB55
AB51
AB48
AB44
AB41
AA55
AA51
AA48
AA44
AA41
W55
W51
W48
W44
W41
U55
U51
U48
U44
U41
R55
R51
R48
R44
R41
P60
N55
N51
N48
N44
N42
M60
M51
M44
L55
K60
K51
K44
H60
H51
H44
G60
G55
G51
G44
F55
E60
E57
E53
E50
E46
E42
D59
D57
D55
D54
D52
D50
D48
D47
D45
D43
B60
B56
B53
B49
B46
B42
A57
A54
A50
A47
A43
+VCA P0 +VCA P1
+V CCP
VCAP0_1
VCAP0_2
VCAP0_3
VCAP0_4
VCAP0_5
VCAP0_6
VCAP0_7
VCAP0_8
VCAP0_9
VCAP0_10
VCAP0_11
VCAP0_12
VCAP0_13
VCAP0_14
VCAP0_15
VCAP0_16
VCAP0_17
VCAP0_18
VCAP0_19
VCAP0_20
VCAP0_21
VCAP0_22
VCAP0_23
VCAP0_24
VCAP0_25
VCAP0_26
VCAP0_27
VCAP1_1
VCAP1_2
VCAP1_3
VCAP1_4
VCAP1_5
VCAP1_6
VCAP1_7
VCAP1_8
VCAP1_9
VCAP1_10
VCAP1_11
VCAP1_12
VCAP1_13
VCAP1_14
VCAP1_15
VCAP1_16
VCAP1_17
VCAP1_18
VCAP1_19
VCAP1_20
VCAP1_21
VCAP1_22
VCAP1_23
VCAP1_24
VCAP1_25
VCAP1_26
VCAP1_27
INT EL_A UBURN DALE _1288
1U_0 402_6 .3V6K
1
1
1
C7 2
C9 3
C1 14
2
2
1U_0 402_6 .3V6K
2
U1H
+VC AP0
BD55
BD51
BD48
BB55
BB51
BB48
AY57
AY53
AY50
AW57
AW53
AW50
AU55
AU51
AU48
AR55
AR51
AR48
PR OC_DP RSLP VR<37>
AN57
AN53
AN50
AL57
AL53
AL50
AK57
AK53
AK50
+VC AP1
BD44
BD41
BD37
BB44
BB41
BB37
AY46
AY42
AY39
AW46
AW42
AW39
AU44
AU41
AU37
AR44
AR41
AR37
AN46
AN42
AN39
AL46
AL42
AL39
AK46
AK42
AK39
1U_0 402_6 .3V6K
1
1
C1 13
2
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
C9 4
2
2008/09/15 2009/09/03
T135
PA D
VCC SENS E<37>
VSS SENSE<3 7>
R1 481 0_ 0402_5%
Close to CPU
VCC SENS E
VSS SENSE
+1.5 VS_C PU_V DDQ
1U_0 402_6 .3V6K
1
1
C9 2
C1 40
2
2
1U_0 402_6 .3V6K
Compal Secret Data
Deciphered Date
VTT_S ENSE<34>
12
1 2
R7 5 1 00_04 02_1%
1 2
R7 6 1 00_04 02_1%
+1.8V S
0_08 05_5%
1U_0 402_6 .3V6K
C1 15
1U_0 402_6 .3V6K
4
H_ VID [0..6 ]<37>
0_04 02_5%
IMV P_IMON< 37>
VCC SENS E
VSS SENSE
L32
4
PSI #<37>
R7 2
C6 3
H_ VID 0
H_ VID 1
H_ VID 2
H_ VID 3
H_ VID 4
H_ VID 5
H_ VID 6
H_V TTVID 1
PM_ DPRS LPVR _R
12
0_04 02_5%
R7 3
R7 4 0 _0402 _5%
VSS_S ENSE_VT T
+C PU_C ORE
22U_ 0805_ 6.3V6M
1
1
C3 74.7U _0603 _6.3V6K
C3 8
2
2
+V DDQ_ CK
12
1
C5 0
2
1U_0 402_6 .3V6K
1
1
C6 4
2
2
1U_0 402_6 .3V6K
F68
A61
D61
D62
A62
B63
D64
D66
AN1
F66
A41
F64
12
F63
12
N13
R12
W39
W37
U37
R39
R37
BB14
BB12
1
C6 5
2
U1 F
PSI#
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VTT_SELECT[1]
PROC_DPRSLPVR
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
VCCPLL1
VCCPLL2
VCCPLL3
VCCPLL4
VCCPLL5
VDDQ_CK[1]
VDDQ_CK[2]
INT EL_A UBURN DALE _1288
VTT0_72
VTT0_73
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
1
C6 6
C6 7
2
2
1U_0 402_6 .3V6K
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
SENSE LINESCPU VI DS
1.1V R AIL PO WER
1.8V
POWER
R7 7 0_040 2_5%
1 2
R7 8 0_040 2_5%
1 2
1U_0 402_6 .3V6K
1
1
2
1
1
C8 9
C8 6
1U_0 402_6 .3V6K
2
C8 8
2
2
1U_0 402_6 .3V6K
Compal Electronics, Inc.
Auburndale(4/5)-PWR
LA -6 161 P
5
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_43
VTT0_44
VTT0_45
VTT0_46
VTT0_47
VTT0_48
VTT0_49
VTT0_50
VTT0_51
VTT0_52
VTT0_53
VTT0_54
VTT0_55
VTT0_56
VTT0_57
VTT0_58
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT0_63
VTT0_64
VTT0_65
VTT0_66
VTT0_67
VTT0_68
VTT0_69
VTT0_70
VTT0_71
VTT0_72
VTT0_73
1U_0 402_6 .3V6K
1
C8 7
2
5
+V CCP
AW14
AW12
AU60
AU59
AU12
AR60
AR59
AR12
AN60
AN59
AN35
AN33
AN17
AN15
AN14
AN12
AM10
AL60
AL59
AL17
AL15
AL14
AL12
AK35
AK33
AF39
AF37
AF35
AF33
AF32
AF30
AD39
BF60
BF59
BD60
BD59
BB60
BB59
AY60
AW60
AW35
AW33
AD37
AD35
AD33
AD32
AD30
W35
W33
W32
W30
W28
W26
W24
W23
U35
U33
U32
U30
U28
U26
U24
U23
R35
R33
R32
R30
R28
R26
R24
R23
VTT0_72
AY10
VTT0_73
AN9
+VC CP
1
C8 5
C9 1
2
1U_0 402_6 .3V6K
7 4 1Tues day, May 18, 2010
1U_0 402_6 .3V6K
1
C9 0
2
0. 5
1
2
3
4
5
U1 I
BU62
VSS1
BU58
VSS2
BU55
VSS3
BU51
VSS4
BU48
VSS5
BU44
VSS6
BU37
VSS7
BU32
A A
B B
C C
D D
VSS8
BU25
VSS9
BU21
VSS10
BU18
VSS11
BU14
VSS12
BU11
VSS13
BU7
VSS14
BP42
VSS15
BN64
VSS16
BN6
VSS17
BM70
VSS18
BM51
VSS19
BM44
VSS20
BM32
VSS21
BM24
VSS22
BM17
VSS23
BL57
VSS24
BL55
VSS25
BL48
VSS26
BL40
VSS27
BL28
VSS28
BL20
VSS29
BK63
VSS30
BK60
VSS31
BK53
VSS32
BK34
VSS33
BK10
VSS34
BJ64
VSS35
BJ21
VSS36
BJ9
VSS37
BJ1
VSS38
BH70
VSS39
BH57
VSS40
BH55
VSS41
BH47
VSS42
BH24
VSS43
BH20
VSS44
BH15
VSS45
BG51
VSS46
BG36
VSS47
BF62
VSS48
BF30
VSS49
BF13
VSS50
BF8
VSS51
BE70
VSS52
BE65
VSS53
BE9
VSS54
BE1
VSS55
BD57
VSS56
BD53
VSS57
BD50
VSS58
BD46
VSS59
BD42
VSS60
BD39
VSS61
BD14
VSS62
BB71
VSS63
BB62
VSS64
BB57
VSS65
BB53
VSS66
BB50
VSS67
BB46
VSS68
BB42
VSS69
BB39
VSS70
BB7
VSS71
BB1
VSS72
BA70
VSS73
AY71
VSS74
AY66
VSS75
AY62
VSS76
AY59
VSS77
AY55
VSS78
AY51
VSS79
AY48
VSS80
AR42
VSS140
AR39
VSS141
AR35
VSS142
AR33
VSS143
AR32
VSS144
AR30
VSS145
AR28
VSS146
AR26
VSS147
AR24
VSS148
AR23
VSS149
AR21
VSS150
AR19
VSS151
AR17
VSS152
AR15
VSS153
AR14
VSS154
AR4
VSS155
AR1
VSS156
AP70
VSS157
AP64
VSS158
AN62
VSS159
AN55
VSS160
AY44
VSS81
AY41
VSS82
AY37
VSS83
AY35
VSS84
AY33
VSS85
AY32
VSS86
AY30
VSS87
AY28
VSS88
AY26
VSS89
INT EL_A UBURN DALE _1288
VSS
1
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
AY24
AY23
AY21
AY19
AY17
AY15
AY14
AY12
AY8
AY4
AW67
AW62
AW59
AW55
AW51
AW48
AW44
AW41
AW37
AV9
AV1
AU70
AU62
AU57
AU53
AU50
AU46
AU42
AU39
AU35
AU33
AU32
AU30
AU28
AU26
AU24
AU23
AU21
AU19
AU17
AU15
AU14
AU4
AT64
AT10
AR62
AR57
AR53
AR50
AR46
AN51
AN48
AN44
AN41
AN37
AN5
AN4
AM64
AM8
AL62
AL55
AL51
AL48
AL44
AL41
AL37
AL35
AL33
AL1
AK70
AK64
AK55
AK51
AK48
AK44
AK41
AK37
AK32
AK30
AK28
AK26
AK24
AK23
AK21
AK19
AK17
AK15
AJ70
AH62
AH57
AH55
BV66
BV64
BT68
BR69
BR68
BR3
BN71
BN1
BL71
BL1
R14
H71
F71
E69
E68
A66
A64
E5
C68
U1J
AH53
VSS202
AH51
VSS203
AH50
VSS204
AH48
VSS205
AH46
VSS206
AH44
VSS207
AH42
VSS208
AH41
VSS209
AH39
VSS210
AH37
VSS211
AH35
VSS212
AH33
VSS213
AH32
VSS214
AH30
VSS215
AH28
VSS216
AH26
VSS217
AH24
VSS218
AH23
VSS219
AH21
VSS220
AH19
VSS221
AH17
VSS222
AH15
VSS223
AH4
VSS224
AG64
VSS225
AG9
VSS226
AG6
VSS227
AF69
VSS228
AF62
VSS229
AF1
VSS230
AE70
VSS231
AE64
VSS232
AD62
VSS233
AD57
VSS234
AD53
VSS235
AD50
VSS236
AD46
VSS237
AD42
VSS238
AD4
VSS239
AC67
VSS240
AC64
VSS241
AC10
VSS242
AC5
VSS243
AC1
VSS244
AB70
VSS245
AB62
VSS246
AB57
VSS247
AB53
VSS248
AB50
VSS249
AB46
VSS250
AB42
VSS251
AB39
VSS252
AB37
VSS253
AB35
VSS254
AB33
VSS255
AB32
VSS256
AB30
VSS257
AB28
VSS258
AB26
VSS259
AB24
VSS260
AB23
VSS261
AB21
VSS262
AB19
VSS263
AB17
VSS264
AB15
VSS265
AB14
VSS266
AB9
VSS267
AA66
VSS268
AA64
VSS269
AA62
VSS270
AA57
VSS271
AA53
VSS272
AA50
VSS273
AA46
VSS274
AA42
VSS275
AA39
VSS276
AA37
VSS277
AA35
VSS278
AA33
VSS279
AA32
VSS280
AA30
VSS281
AA28
VSS282
AA26
VSS283
AA24
VSS284
AA23
VSS285
AA21
VSS286
AA19
VSS287
F20
VSS374
F4
VSS375
E37
VSS376
E33
VSS377
E30
VSS378
E16
VSS379
E12
VSS380
D41
VSS381
D38
VSS382
D34
VSS383
D31
VSS384
D27
VSS385
D24
VSS386
D20
VSS387
D17
VSS388
D13
VSS389
D10
VSS390
D6
VSS391
B65
VSS392
B40
VSS415
INT EL_A UBURN DALE _1288
VSS
2
VSS404
VSS405
VSS406
VSS407
VSS408
VSS409
VSS410
VSS411
VSS412
VSS413
VSS393
VSS394
VSS395
VSS396
VSS397
VSS398
VSS399
VSS400
VSS401
VSS402
VSS403
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
VSS361
VSS362
VSS363
VSS364
VSS365
VSS366
VSS367
VSS368
VSS369
VSS370
VSS371
VSS372
VSS373
A40
A36
A33
A29
A26
A22
A19
A15
A12
A8
B62
B58
B55
B51
B48
B44
A59
A55
A52
A48
A45
AA17
AA15
AA14
AA4
W69
W62
W57
W53
W50
W46
W42
W6
W1
V70
U64
U62
U57
U53
U50
U46
U42
U39
U9
U4
T1
R70
R62
R57
R53
R50
R46
R42
R5
P4
N63
N57
N53
N50
N46
N30
N21
N15
M53
M42
M36
M1
L70
L57
L48
L47
L13
K64
K53
K43
K36
K34
K32
K25
K17
K11
K6
K4
J65
J57
J48
J47
J40
J9
H53
H43
H36
H1
G70
G57
G53
G48
G47
G43
G30
G24
G20
G15
F61
F48
F47
F28
+V CCP
1U_0 402_6 .3V6K
Add to f ollow de sign guide
1U_0 402_6 .3V6K
1
2
1
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
1
C1 89
C1 42
2
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
1
C3 03
C3 04
2
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
1
C5 10
C5 09
2
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
1
C6 18
C6 19
2
2
1U_0 402_6 .3V6K
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1U_0 402_6 .3V6K
1
C1 91
C1 41
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
C3 02
C1 92
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
1
C3 07
C5 08
2
2
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
1
C5 15
2
2
Issued Date
1U_0 402_6 .3V6K
1
1
C1 90
2
2
1U_0 402_6 .3V6K
1
1
C3 06
2
2
1U_0 402_6 .3V6K
1
C5 12
2
1
C6 36
C5 13
2
1U_0 402_6 .3V6K
CPU CORE
+C PU_C ORE
22U_ 0805_6. 3V6M
C2 01
C3 05
1
C5 11
2
1U_0 402_6 .3V6K
1
C6 28
2
22U_ 0805_6. 3V6M
C7 3
1
1
2
2
Inside cavity
330U _D2_2 .5VM_R6 M
C9 5
1
1
+
+
2
2
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C1 01
1
1
2
2
C7 4
UL V@
330U _D2_2 .5VM_R6 M
C9 6
UL V@
C1 02
1
UL V@
2
BGA Ball Cracking Prevention and Detection
+3VS
12
VSS _NCT F1_R<5>
+3VS +3VS
12
VSS _NCT F6_R<5> VSS _NCT F7_R<5>
2008/09/15 2009/09/03
Compal Secret Data
Deciphered Date
4
22U_ 0805_6. 3V6M
C7 5
1
2
330U _D2_2 .5VM_R6 M
C9 7
1
+
2
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C1 03
C1 04
1
2
Under cavity
R8 0
CRA CK_B GA
100K _0402_5 %
3
Q3B
5
2N70 02DW -T/R7 _SOT363-6
4
CRA CK_B GA
R8 1
100K _0402_5 %
61
Q4A
2N70 02DW -T/R7 _SOT363-6
2
22U_ 0805_6. 3V6M
C7 6
1
1
2
2
330U _D2_2 .5VM_R6 M
C9 8
1
+
2
Under cavity
22U_ 0805_6. 3V6M
C1 05
1
2
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C7 7
22U_ 0805_6. 3V6M
1
2
VSS _NCT F2_R<5>
22U_ 0805_6. 3V6M
C7 8
C7 9
1
1
2
2
22U_ 0805_6. 3V6M
C1 06
UL V@
Cu stom
22U_ 0805_6. 3V6M
C1 07
1
1
2
2
Title
Size D ocum ent N umber Re v
Da te: She et
Compal Electronics, Inc.
Auburndale(5/5)-GND/Bypass
LA -6 161 P
1
2
C1 08
+3VS
22U_ 0805_6. 3V6M
C8 0
1
2
12
R7 9
100K _0402_5 %
12
R8 2
100K _0402_5 %
22U_ 0805_6. 3V6M
C8 1
1
2
22U_ 0805_6. 3V6M
C1 09
1
2
61
2
CRA CK_B GA
3
5
4
5
22U_ 0805_6. 3V6M
C8 2
1
UL V@
2
22U_ 0805_6. 3V6M
C1 10
Q3A
2N70 02DW -T/R7 _SOT363-6
Q4B
2N70 02DW -T/R7 _SOT363-6
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C8 3
1
2
C8 4
1
UL V@
UL V@
2
CRA CK_B GA <16, 28>
o f
8 4 1Tues day, May 18, 2010
0. 5
1
2
3
4
5
DDR3 SO-DIMM A
+V _DD R_CP U_REF
0.1U _0402 _16V4Z
2.2U _0805 _16V4Z
C1 11
1
2
A A
B B
C C
D D
C1 12
1
2
DDR_ CKE0 _DIM MA<6>
DD R_A_B S2<6>
M_ CLK_ DDR0<6>
M_ CLK_D DR#0<6>
DD R_A_B S0<6>
DD R_A _WE#<6>
DD R_A_ CAS#<6>
DDR_ CS1_ DIMM A#<6>
+3VS
1
2
1
2.2U _0402 _6.3V6M
C1 36
1
2
1 2
10K _0402_5%
0.1U _0402 _16V4Z
C1 37
DD R_A _D2
DD R_A _D5
DD R_A_ DM0
DD R_A _D6
DD R_A _D7
DD R_A _D9
DD R_A _D11
DD R_A_ DQS# 1
DD R_A _DQS 1
DD R_A _D8
DD R_A _D10
DD R_A _D17
DD R_A _D20
DD R_A_ DQS# 2
DD R_A _DQS 2
DD R_A _D16
DD R_A _D23
DD R_A _D24
DD R_A _D31
DD R_A_ DM3
DD R_A _D26
DD R_A _D27
DDR_ CKE0 _DIM MA
DD R_A_ BS2
DDR_ A_MA 12
DDR_ A_M A9
DDR_ A_M A8
DDR_ A_M A5
DDR_ A_M A3
DDR_ A_M A1
M _CLK_ DDR0
M _CLK_ DDR#0
DDR_ A_MA 10
DD R_A_ BS0
DD R_A _WE#
DD R_A_ CAS#
DDR_ A_MA 13
DDR_ CS1_ DIMM A#
DD R_A _D32
DD R_A _D33
DD R_A_ DQS# 4
DD R_A _DQS 4
DD R_A _D34
DD R_A _D35
DD R_A _D44
DD R_A _D45
DD R_A_ DM5
DD R_A _D42
DD R_A _D43
DD R_A _D50
DD R_A _D49
DD R_A_ DQS# 6
DD R_A _DQS 6
DD R_A _D54
DD R_A _D51
DD R_A _D56
DD R_A _D61
DD R_A_ DM7
DD R_A _D62
DD R_A _D58
+1.5 V + 1.5V
3A @
3A @ 1. 5 V
3A @3A @
JDI MM1
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
R9 5
1 2
10K _0402_5%
R9 6
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
GND2
FOX _AS0 A626-U4 SN-7F~D
CO NN@
1. 5 V
1. 5 V1. 5 V
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
BOSS1
BOSS2
2
VSS
DQ4
DQ5
VSS
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
VDD
BA1
VDD
S0#
VDD
NC
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA
SCL
VTT
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
DD R_A _D0
DD R_A _D1
DD R_A_ DQS# 0
DD R_A _DQS 0
DD R_A _D4
DD R_A _D3
DD R_A _D12
DD R_A _D13
DD R_A_ DM1
DRA MRST#
DD R_A _D14
DD R_A _D15
DD R_A _D19
DD R_A _D21
DD R_A_ DM2
DD R_A _D22
DD R_A _D18
DD R_A _D25
DD R_A _D28
DD R_A_ DQS# 3
DD R_A _DQS 3
DD R_A _D29
DD R_A _D30
DDR_ CKE1 _DIM MA
DDR_ A_MA 15
DDR_ A_MA 14
DDR_A_MA 11
DDR_ A_M A7
DDR_A_MA6
DDR_ A_M A4
DDR_ A_M A2
DDR_ A_M A0
M _CLK_ DDR1
M _CLK_ DDR#1
DD R_A_ BS1
DD R_A_ RAS#
DDR_ CS0_ DIMM A#
M_OD T0
M_OD T1
DD R_A _D36
DD R_A _D38
DD R_A_ DM4
DD R_A _D37
DD R_A _D39
DD R_A _D41
DD R_A _D40
DD R_A_ DQS# 5
DD R_A _DQS 5
DD R_A _D46
DD R_A _D47
DD R_A _D55
DD R_A _D53
DD R_A_ DM6
DD R_A _D52
DD R_A _D48
DD R_A _D60
DD R_A _D57
DD R_A_ DQS# 7
DD R_A _DQS 7
DD R_A _D59
DD R_A _D63
PM_EX TTS#1_R
SMB _DATA_S3
SMB _CLK_S 3
0.
0. 65 A @0 . 75 V
65 A @0 . 75 V
0.0.
65 A @0 . 75 V6 5 A@ 0 .7 5 V
2
+0.7 5VS
DRA MRST# < 4>
DDR_ CKE1 _DIMM A <6>
M_ CLK_D DR1 <6>
M_C LK_DD R#1 <6>
DDR_ A_BS 1 <6>
DD R_A_ RAS# <6>
DDR_ CS0_ DIMM A# <6>
M_ODT 0 <6>
M_ODT 1 <6>
2.2U _0805 _16V4Z
0.1U _0402 _16V4Z
C1 17
C1 16
1
1
2
2
PM_EX TTS#1_R <4>
SMB_D ATA_S3 < 10,12, 22>
SMB _CLK_S3 < 10,12, 22>
DD R_A _D[0 ..63]<6>
DD R_A_ DM[0 ..7]<6>
DD R_A _DQS [0..7 ]<6>
DD R_A _DQS #[0.. 7]<6>
DDR_ A_MA [0.. 15]<6>
R9 4 0_040 2_5%
1 2
+V _DD R_CP U_REF+VR EF_C A
SMB _DATA_S3
SMB _CLK_S 3
+1.5 V
12
R8 3
1K_ 0402_1%
+V _D DR_CP U_RE F
12
R8 6
1K_ 0402_1%
+3VS
@
@
R1 495
10K _0402_5%
U5 9
@
1 2
1
SDA
2
SCL
3
T_CRIT_A
4
GND
NS_LM7 7CIMMX_3_ MSOP8P
reserv e for memory thermal sensor, HP.
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
8
+VS
7
A0
6
A1
5
INT
2008/09/15 2009/09/03
0.1U _0402 _16V4Z
1
2
PM_EX TTS#1_R
+3VS
C1 338
@
0_04 02_5%
1 2
@
0_04 02_5%
1 2
Compal Secret Data
Deciphered Date
4
R1 496
R1 497
open
Lay ou t N ote:
Pl ace near JDI MM1
+1.5V
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C1 21
1
2
C1 22
1
2
Lay ou t N ote:
Pl ace near JDI MB1
1
2
Title
Size D ocum ent N umber R ev
Cu sto m
LA -61 61P
Da te: She et o f
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C1 24
C1 23
1
1
2
2
+0.7 5VS
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C1 31
1U_0 402_6 .3V6K
C1 315
C1 314
1
1
2
2
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C1 25
1
1
2
2
C1 33
C1 32
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
1
2
2
5
330U _B2_ 2.5VM_R15M
C1 18
C1 26
1
+
2
C1 34
1U_0 402_6 .3V6K
C1 35
10U_ 0805_6. 3V6M
1
1
2
2
9 4 1Tuesday, May 18, 2010
0. 5
1
A A
2
3
4
5
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
VDD_CPU
CPU_0#
VSS_CPU
CPU_1#
VDD_SRC
0.1U _0402 _16V4Z
C1 67
+3V S_CK505
SMB _CLK_S 3
SMB _DATA_S3
RE F_0/ CPU_S EL
CLK _XTAL_IN
CLK_ XTAL_OUT
CK _P WRGD
R_ CLK_ BUF_B CLK CLK _BUF _BCL K
R_CL K_BU F_BC LK#
+3V S_CK505 _G +3VS +1.5V S
1 2
R1 43 0_06 03_5%@
1 2
R1 20 0_06 03_5%
10U_ 0805_ 10V4Z
0.1U _0402 _16V4Z
C1 64
C1 69
1
2
CPU_0
CPU_1
1
2
32
SCL
31
SDA
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0.1U _0402 _16V4Z
C1 68
1
2
R1 07 33_0 402_5%
R1 10 0_04 02_5%
R1 12 0_04 02_5%
+1.0 5VS_ CK505
+3V S_CK50 5_G
instal l R12 0 for low power CLKGENEMI re quest , Compal SI, 1/19
1 2
1 2
1 2
1
C1 63
2
CLK _14M_ PCH
10P _0402 _50V8C@
CLK _BUF_ BCL K#
SMB _CLK_S3 < 9,12,2 2>
SMB_D ATA_S3 < 9,12,2 2>
CLK _14M_ PCH <12>
CLK _BUF_ BCLK < 12>
CLK _BUF_ BCLK # <12>
CK _P WRGD
33P _0402_50 V8J
C1 77
2
1
1 2
10K _0402_5%
61
Y114.3 18MH Z 16P F 7A 14300083
R1 15
+3V S_CK505
Q7A
2
2N70 02DW -7-F_S OT363-6
CLK_ XTAL_OUT
CLK _XTAL_IN
12
2
C1 78
33P _0402_50 V8J
1
CL K_EN# < 37>
+3V S_CK505 _G
CLK _BUF_ DOT96<12>
CLK _BUF_ DOT96 #<12>
CL K_BU F_CK SSCD< 12>
CL K_BU F_CK SSCD #<12>
CLK _DMI<12>
CLK _DMI#<12>
B B
CLK _BUF_ DOT96
CLK _BUF_ DOT 96#
CL K_B UF_CK SSCD
CL K_B UF_CK SSCD #
CLK _DMI
CLK _DMI#
CPU_1PIN 30 CPU_0
(De faul t)
0 133MHz
1
+1.0 5VS_ CK505+1.05VS
1 2
R1 18 0_06 03_5%
C C
1
2
133MHz
100MHz 100MHz
Close to U6
10U_ 0805_ 10V4Z
10U_ 0805_ 10V4Z
0.1U _0402 _16V4Z
C1 72
C1 71
C1 73
1
1
2
2
0.1U _0402 _16V4Z
0.1U _0402 _16V4Z
C1 74
C1 75
1
1
1
2
2
2
+1.05 VS
R1 465 10 K_0402_ 5%@
R1 466 10 K_0402_ 5%
CPU _STOP #
47P _0402_5 0V8J
C1 76
R1 06 0_04 02_5%
1 2
R1 08 0_04 02_5%
1 2
+3V S_CK505
R1 09 0_04 02_5%
1 2
R1 11 0_04 02_5%
1 2
R1 13 0_04 02_5%
1 2
R1 14 0_04 02_5%
1 2
+1.0 5VS_ CK505
1 2
1 2
1 2
10K _0402_5%
R1 16
L_CL K_BU F_DO T96
L_CL K_BU F_DO T96#
L_ CLK_ BUF_C KSS CD
L_CL K_BU F_CK SSCD #
L_CL K_DM I
L_CL K_DM I#
CPU _STOP #
RE F_0/ CPU_S EL
+3V S_CK505
FBM A-L11- 160808-301L MA20T_0603 ~D
U6
1
VDD_DOT
2
VSS_DOT
3
DOT_96
4
DOT_96#
5
VDD_27
6
27MHZ
7
27MHZ_SS
8
VSS_27
9
VSS_SATA
10
SRC_1/SATA
11
SRC_1#/SATA#
12
VSS_SRC
13
SRC_2
14
SRC_2#
15
VDD_SRC_IO
16
CPU_STOP#
SLG 8LV59 5VTR_QFN _32P_5X5
2nd So urce :
IDT IC S9LVS3 197BKL FT MLF 32P
REALTE K RTM8 90N-63 2-VB-G RT QFN 32P
+3VS
+3V S_CK505
R1 17
1 2
TGND
33
0.1U _0402 _16V4Z
47P _0402_5 0V8J
C1 65
C1 70
1
1
2
1
2
2
REF_0/CPU_SEL
CKPWRGD/PD#
0.1U _0402 _16V4Z
C1 66
1
2
VDD_CPU_IO
Close to U6
Close to U2 within 500mil
D D
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/09/03
Compal Secret Data
Deciphered Date
4
Title
Size D ocum ent N umber R ev
Da te: She et o f
Compal Electronics, Inc.
CLOCK GENERATOR
LA -61 61P
5
10 41T uesd ay, M ay 1 8, 20 10
0. 5
1
PCH _RTCX 1
1 2
R1 23 10M _0402_5%
18P _0402_5 0V8J
1
1
C1 81
1 2
1 2
Y2
OSC4OSC
NC3NC
2
HDA _BIT _CLK_ CODE C
HD A_S DOUT _CODE C
A A
2
@
C1 86 47P _0402_5 0V8J
@
C1 88 47P _0402_5 0V8J
for RF
B B
C C
1 2
R1 76 51_0 402_5%
PCH _RTCX 2
32.7 68KH Z_12. 5PF_ Q13MC14 610002
1
C1 82
18P _0402_5 0V8J
2
for i- AMT setting. 11/20 HP
PCH _JTA G_TCK
+R TCVC C
HDA _BIT _CLK_ CODE C<23>
HD A_S YNC _CO DEC< 23>
SB_ SPKR<23>
HD A_RS T#_CO DEC<23>
HD A_S DIN0<23>
HD A_S DOUT_ CODE C<23>
1U_0 603_1 0V4Z
1 2
R1 26 20K_0 402_1%
1 2
R1 27 20K_0 402_1%
1U_0 603_1 0V4Z
KBC _SPI _CS0#_ R<28>
KBC _SPI _CS1#_ R<28>
R1 58
@
200_ 0402_5%
1 2
PCH _JTA G_TDI
12
R1 67
@
100_ 0402_1%
C1 80
1
12
2
1
12
C1 83
2
R1 30 33_0 402_5%
1 2
R1 32 33_0 402_5%
1 2
R1 34 33_0 402_5%
1 2
R1 37 33_0 402_5%
1 2
+3V ALW
11/20 HP
KBC _SPI _CLK_R<28>
KBC _SPI _SI_R<28>
+R TCVC C +3VS
CL RP1
SHO RT P ADS@
CL RP2
SHO RT P ADS@
1 2
R1 457 1K_ 0402_5%
R1 461 10 0K_0 402_5%
1 2
T147P AD
T148P AD
T149P AD
T150P AD
T121P AD
1 2
R1 44 0_04 02_5%
1 2
R1 48 0_04 02_5%
KBC _SPI _SO<28>
12
R1 57
200_ 0402_5%@
PCH _JTA G_TDO
12
R1 66
100_ 0402_1%@
Pre -Pr od uctio n Uni ts Pr odu ction
Ref .PCH Pin
ES1 AllES 2
R15 7
PCH _JT AG_TD O
D D
PCH _JT AG_TD I
PCH _JT AG_TM S
PCH _JT AG_TC K
1
R16 6
R15 8
R16 7
R15 6
R16 5
R17 6
Uns tuff
Uns tuff
200 ohm
100 ohm
200 ohm
51 ohm 5%
200 ohm
100 ohm
200 ohm
100 ohm
200 ohm
100 ohm
Uns tuff
Uns tuff
Uns tuff
Uns tuff
Uns tuff
Uns tuff100 ohm
51 ohm 5%51 ohm 5%
2
1 2
R1 21 1M_ 0402_5%
1 2
R1 24 330 K_0402_ 5%
PCH _RTCX 1
PCH _RTCX 2
PCH _RTCR ST#
PCH _SRT CRST#
S M_INT RUDE R#
PCH _INTV RME N
HDA _BIT _CLK
HD A_S YNC
SB_ SPKR
HDA _RST #
HD A_S DIN0
HD A_SD OUT
PCH _GPI O33AQU AWHI TE_BA TLED
PCH _JTA G_TCK
PCH _JTAG_T MS
PCH _JTA G_TDI
PCH _JTA G_TDO
KBC _SPI _CS0#
KBC _SPI _CS1#
+3V ALW+3 VALW+3V ALW
12
@
12
@
2
B13
D13
C14
D17
A16
A14
A30
D29
P1
C30
G30
F30
E32
F32
B29
H32
J30
M3
K3
K1
J2
J4
BA2
AV3
AY3
AY1
AV1
R1 56
200_ 0402_5%
PCH _JTAG_T MS
R1 65
100_ 0402_1%
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_RST#
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
IBE XPEAK- M_FCBGA1 071
S M_INT RUDE R# SI RQ
U7 A
R1 22 10K_ 0402_5%
1 2
R1 25 10K_ 0402_5%@
RT CIH DA
SPI JTAG
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
FWH4 / LFRAME#
LDRQ1# / GPIO23
LP C
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SA TA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
12
LDRQ0#
SERIRQ
D33
B33
C32
A32
C34
A34
F34
AB9
AK7
AK6
AK11
AK9
AH6
AH5
AH9
AH8
AF11
AF9
AF7
AF6
AH3
AH1
AF3
AF1
AD9
AD8
AD6
AD5
AD3
AD1
AB3
AB1
AF16
AF15
T3
Y9
V1
3
SB_ SPKRPCH _INTV RME N
R1 460 10 K_0402 _5%
GPI O23
SI RQ
SATA_ PRX_DTX_N0
SATA_ PRX_DTX_P0
SATA_ PTX_DRX_N0
SATA_ PTX_DRX_P0
SAT AICOMP IPCH _TRST #
R1 45 10K_ 0402_5%
1 2
GPI O21
HD D_HA LTLE D
3
12
1 2
R1 42 37.4 _0402_1 %
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LPC _LAD0 < 27,28>
LPC _LAD1 < 27,28>
LPC _LAD2 < 27,28>
LPC _LAD3 < 27,28>
LPC _LFRA ME# <27 ,28>
+3VS
SI RQ <27 ,28>
SATA_ PRX_DTX_N0 <19>
SATA_ PRX_DTX_P0 <1 9>
SATA_ PTX_DRX_N0 <19>
SATA_ PTX_DRX_P0 <1 9>
+1.0 5VS
+3VS
SAT A_LED# <2 0>
HD D_HA LTLED < 20>
4
11/20 HP
+R TCVC C +VR EG_511 25
R2 34 0_04 02_5%
1 2
1
C2 10
1U_0 603_1 0V4Z
2
+3VS
R1 47
10K _0402_5%
1 2
GPI O21
iAMT setting
2008/09/15 2009/09/03
Compal Secret Data
Deciphered Date
4
D3 6
1
CHN2 02UP T_SC -70
AQU AWHI TE_BA TLED#<25,28>
5
JBATT1
3
2
R2 61
1K_ 0402_5%
RT C1 RT C2
1 2
W=2 0mi ls
L
for i- AMT setting. 11/20 HP
R1 459
330K _0402_5 % @
1 2
2
+ -
+3VS
R1 458
@
10K _0402_5%
1 2
AQU AWHI TE_BA TLED
61
Q86A
2N70 02DW H 2N SOT3 63-6
1
+
LOTES _AAA-BA T-019-K01 _2P
CO NN@
GPIO33 iAMT En able /Disable
Hi
Enable (Defau lt)
DisableLo
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et
Compal Electronics, Inc.
IBEX-M(1/6)-HDA/JTAG/SATA
LA -61 61P
5
11 41T uesd ay, M ay 1 8, 20 10
2
-
0. 5
o f
1
A A
change from poert2 to port4. 11/20 HP
PCI E_PRX_D TX_N4<22>
PCIE _PRX_DTX _P4<22>
WLAN
GLAN
WWAN
B B
11/21 HP
12/05 HP
WWAN
C C
WLAN
PCI E_PT X_C_DRX_N 4<22>
PCI E_PTX _C_DRX_P4< 22>
PCI E_PRX_D TX_N6<21>
PCIE _PRX_DTX _P6<21>
PCI E_PT X_C_DRX_N 6<21>
PCI E_PTX _C_DRX_P6< 21>
PCI E_PRX_D TX_N7<22>
PCIE _PRX_DTX _P7<22>
PCI E_PT X_C_DRX_N 7<22>
PCI E_PTX _C_DRX_P7< 22>
+3VS
CLK _PCIE _MCA RD2#<22>
CLK _PCIE _MCA RD2<22>
CL KRE Q_WW AN#<22>
CLK _PCIE _MCA RD#<22>
CLK _PCIE _MCA RD<22>
CL KREQ _WLA N#< 22>
C1 93 0.1 U_040 2_16V4 Z
1 2
C1 94 0.1 U_040 2_16V4 Z
1 2
C1 97 0.1 U_040 2_16V4 Z
1 2
C1 98 0.1 U_040 2_16V4 Z
1 2
C1 301 0. 1U_04 02_16 V4Z
1 2
C1 302 0. 1U_04 02_16 V4Z
1 2
+3V ALW
R2 00 10K _0402_5%
R2 02 10K _0402_5%
+3VS
R2 05 10K_ 0402_5%
1 2
R1 479 0_ 0402_5%
1 2
R1 480 0_ 0402_5%
1 2
R2 08 0_04 02_5%
1 2
R2 09 0_04 02_5%
1 2
+3V ALW
+3V ALW
R2 13 10K _0402_5%
R7 01 10K _0402_5%
1 2
1 2
1 2
1 2
PCI E_PRX_ DTX_N4
PCI E_PRX_DT X_P4
PCI E_PTX _DRX_N4
PCI E_PTX_DR X_P4
PCI E_PRX_ DTX_N6
PCI E_PRX_DT X_P6
PCI E_PTX _DRX_N6
PCI E_PTX_DR X_P6
PCI E_PRX_ DTX_N7
PCI E_PRX_DT X_P7
PCI E_PTX _DRX_N7
PCI E_PTX_DR X_P7
CLK _PCIE _MCA RD2# _R
CLK _PCIE _MCA RD2_ R
CLK _PCIE _MCA RD#_ R
CL K_PC IE_M CARD _R
2
U7 B
BG30
PERN1
BJ30
PERP1
BF29
PETN1
BH29
PETP1
AW30
PERN2
BA30
PERP2
BC30
PETN2
BD30
PETP2
AU30
PERN3
AT30
PERP3
AU32
PETN3
AV32
PETP3
BA32
PERN4
BB32
PERP4
BD32
PETN4
BE32
PETP4
BF33
PERN5
BH33
PERP5
BG32
PETN5
BJ32
PETP5
BA34
PERN6
AW34
PERP6
BC34
PETN6
BD34
PETP6
AT34
PERN7
AU34
PERP7
AU36
PETN7
AV36
PETP7
BG34
PERN8
BJ34
PERP8
BG36
PETN8
BJ36
PETP8
AK48
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P
P9
PCIECLKRQ0# / GPIO73
AM43
CLKOUT_PCIE1N
AM45
CLKOUT_PCIE1P
U4
PCIECLKRQ1# / GPIO18
AM47
CLKOUT_PCIE2N
AM48
CLKOUT_PCIE2P
N4
PCIECLKRQ2# / GPIO20
AH42
CLKOUT_PCIE3N
AH41
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
AM51
CLKOUT_PCIE4N
AM53
CLKOUT_PCIE4P
M9
PCIECLKRQ4# / GPIO26
AJ50
CLKOUT_PCIE5N
AJ52
CLKOUT_PCIE5P
H6
PCIECLKRQ5# / GPIO44
AK53
CLKOUT_PEG_B_N
AK51
CLKOUT_PEG_B_P
P13
PEG_B_CLKRQ# / GPIO56
IBE XPEAK- M_FCBGA1 071
SMBus
PCI-E*
Link
Con trol ler
PEG_A_CLKRQ# / GPIO47
PEG
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
From C LK BUF FER
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
Clock Flex
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
SML1ALERT# / GPIO74
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
B9
H14
C8
J14
C6
G8
M14
E10
G12
T13
T11
T9
H1
AD43
AD45
AN4
AN2
AT1
AT3
AW24
BA24
AP3
AP1
F18
E18
AH13
AH12
P41
J42
AH51
AH53
AF38
T45
P43
T42
N50
LI D_S W_PC H#
SM BCLK
SMBDA TA
SML 0ALERT#
SML 0CLK
SML 0DATA
SML 1ALERT#
SML 1CLK
SML 1DATA
R1 462 10 K_04 02_5%
1 2
R_C LK_EXP#
R1 95 0_04 02_5%
R_C LK_EXP
R1 96 0_04 02_5%
R_ CLK_ DP#
R1 97 0_04 02_5%
R_ CLK_ DP
R1 98 0_04 02_5%
XTA L25_IN
XTAL25 _OUT
XCL K_RCOM P
R2 11 90.9 _0402_1 %
3
1 2
1 2
1 2
1 2
1 2
T55 PA D
T56 PA D
T139 PA D
T140 PA D
11/20 HP
CLK _DMI# < 10>
CLK _DMI <1 0>
CLK _BUF_ BCLK # <10>
CLK _BUF_ BCLK < 10>
CLK _BUF_ DOT96 # <10>
CLK _BUF_ DOT96 <10>
CL K_BU F_CK SSCD # < 10>
CL K_BU F_CK SSCD < 10>
CLK _14M_ PCH <10>
CL K_PCI _FB <1 4>
CLK_EX P# <4>
CLK_EX P <4>
CLK _DP# <4 >
CL K_DP <4>
+1.0 5VS
4
R1 83 10K _0402_5%
SMB _DATA_S3
SM BCLK
+3VS
SMBDA TA SMB _DATA_S3
1 2
R1 85 10K _0402_5%
1 2
Q8A
2N70 02DW -T/R7 _SOT363- 6
6 1
2
5
3
2N70 02DW -T/R7 _SOT363- 6
4
Q8B
SMB _CLK_S 3
Q2A
SML 1CLK
SML 1DATA
2N70 02DW -T/R7 _SOT363- 6
+3V ALW
4
2N70 02DW -T/R7 _SOT363-6
XTA L25_IN
XTAL25 _OUT
61
2
5
3
Q2B
R2 10 1M_0 402_5%
R2 63
1 2
0_04 02_5%
R2 64
1 2
0_04 02_5%
1 2
1 2
25MHZ_20PF_7A25000012
C1 99
1
18P _0402_50 V8J
2
5
+3V ALW
CAP _CLK
CAP _DAT
SM BCLKSMB _CLK_S 3
+3VS
SMBDA TA
SML 0CLK
SML 0DATA
SML 1CLK
SML 1DATA
SML 0ALERT#
SML 1ALERT#
LI D_S W_PC H#
SMB _CLK_S3 < 9,10,2 2>
SMB_ DATA_S3 < 9,10,2 2>
CAP _CLK <28 >
CAP _DAT <2 8>
Y3
C2 00
1
18P _0402_5 0V8J
2
1 2
R1 84 2.2K _0402_ 5%
1 2
R1 86 2.2K _0402_ 5%
1 2
R1 87 2.2K _0402_ 5%
1 2
R1 88 2.2K _0402_ 5%
1 2
R1 89 2.2K _0402_ 5%
1 2
R1 91 2.2K _0402_ 5%
R1 92 10K_ 0402_5%
1 2
R1 94 10K_ 0402_5%
1 2
R1 99 10K_ 0402_5%
1 2
+3VL
5.1K _0402 _5%
R6 95
1 2
R6 94
1 2
5.1K _0402 _5%
D D
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/09/03
Compal Secret Data
Deciphered Date
4
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(2/6)-PCI-E/SMBUS/CLK
LA -61 61P
5
12 41T uesd ay, M ay 1 8, 20 10
0. 5
5
4
3
2
1
DMI _CTX_PRX _N0<5>
DMI _CTX_PRX _N1<5>
DMI _CTX_PRX _N2<5>
DMI _CTX_PRX _N3<5>
DMI_CT X_PRX_P0<5>
DMI_CT X_PRX_P1<5>
DMI_CT X_PRX_P2<5>
D D
PG D_I N<28,3 7>
C C
11/20 HP
DMI_CT X_PRX_P3<5>
DMI _CRX_PTX _N0<5>
DMI _CRX_PTX _N1<5>
DMI _CRX_PTX _N2<5>
DMI _CRX_PTX _N3<5>
DMI_CRX _PTX_P0<5>
DMI_CRX _PTX_P1<5>
DMI_CRX _PTX_P2<5>
DMI_CRX _PTX_P3<5>
+1.0 5VS
1 2
R2 20 49.9 _0402_1 %
XDP _DBRESE T#< 4>
VGATE<37>
R4 08 1K_0 402_5%
1 2
PM_ DRAM _PWR GD<4>
RP GOOD< 33>
PM_RS MRST#<28>
+3V ALW
SUS _PWR _ACK<28>
PM_ PWRB TN#_R<4>
ON /OFF BTN#<2 5,28>
AC_ PRES ENT< 28>
DMI _CTX_PRX _N0
DMI _CTX_PRX _N1
DMI _CTX_PRX _N2
DMI _CTX_PRX _N3
DMI_CT X_PRX_P0
DMI_CT X_PRX_P1
DMI_CT X_PRX_P2
DMI_CT X_PRX_P3
DMI _CRX_PTX _N0
DMI _CRX_PTX _N1
DMI _CRX_PTX _N2
DMI _CRX_PTX _N3
DMI_CRX _PTX_P0
DMI_CRX _PTX_P1
DMI_CRX _PTX_P2
DMI_CRX _PTX_P3
DMI _IRCO MP
SYS _RS T#
1 2
R2 23 0_04 02_5%
VGATE
1 2
PM_ DRAM _PW RGD
1 2
1 2
1 2
1 2
M_P WROK
AUX PWROK
10K _0402_5%
LOW _BAT_ R
IBE X_R#
1 2
R2 24 0_04 02_5%
R2 25 10K _0402_5%
R2 28 0_04 02_5%
R2 29 10K _0402_5 %
R1 467
R2 31 0_0 402_5%
U7C
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
RI#
IBE XPEAK- M_FCBGA1 071
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Manag ement
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
WAKE#
SLP_S4#
SLP_S3#
SLP_M#
PMSYNCH
SLP_LAN#
TP23
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
BJ14
BF13
BH13
BJ12
BG14
J12
Y1
P8
F3
E4
H7
P12
K8
N2
BJ10
F6
FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7
FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7
FD I_I NT
FD I_F SYN C0
FD I_F SYN C1
FD I_L SY NC0
FD I_L SY NC1
PCI E_WA KE#
P M_CLK RUN#
SUS _CLK
SLP _S5#
SLP _LAN#
FDI _CTX_ PRX_N0 <5>
FDI _CTX_ PRX_N1 <5>
FDI _CTX_ PRX_N2 <5>
FDI _CTX_ PRX_N3 <5>
FDI _CTX_ PRX_N4 <5>
FDI _CTX_ PRX_N5 <5>
FDI _CTX_ PRX_N6 <5>
FDI _CTX_ PRX_N7 <5>
FDI _CTX_PRX _P0 <5>
FDI _CTX_PRX _P1 <5>
FDI _CTX_PRX _P2 <5>
FDI _CTX_PRX _P3 <5>
FDI _CTX_PRX _P4 <5>
FDI _CTX_PRX _P5 <5>
FDI _CTX_PRX _P6 <5>
FDI _CTX_PRX _P7 <5>
FD I_IN T <5>
FD I_F SYN C0 <5>
FD I_F SYN C1 <5>
FD I_L SYN C0 <5>
FD I_L SYN C1 <5>
PCI E_WA KE# <21 ,22>
PM _CLK RUN# <28>
T144 P AD
T58 PA D
SLP _S4# <30 ,36>
SLP _S3# <21 ,23,2 8,29, 30,32,3 4,35>
H_ PM_S YNC <4>
ENA BLT<18>
EN AVD D<18>
INV _PWM<18>
DD C2_C LK<18>
DD C2_DA TA< 18>
+3VS
Clo se PC H a nd m ini s pace 20mil
LVD S_AC LKN<18>
LVD S_ACLK P<1 8>
LVD S_A0 N<18 >
LVD S_A1 N<18 >
LVD S_A2 N<18 >
LVD S_A0P<18>
LVD S_A1P<18>
LVD S_A2P<18>
M_B LUE<1 9>
M_G REEN<19>
M_R ED<19>
3V DDC CL<19>
3V DDC DA<19>
CR T_H SYN C<19>
CR T_V SYNC<19>
1 2
R7 71 10K_ 0402_5%
1 2
R7 72 10K_ 0402_5%
R7 73 2.3 7K_04 02_1%
1 2
M_B LUE
M_G REEN
M_R ED
delete R84, R66,R67
11/20 HP
3V DDC CL
3V DDC DA
CR T_H SY NC
CR T_V SYN C
1K_0402_0.5%
DD C2_ CLK
DD C2_DA TA
T57P AD
R2 32
DA C_I REF
U7D
T48
L_BKLTEN
T47
L_VDD_EN
Y48
L_BKLTCTL
AB48
L_DDC_CLK
Y45
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
AP39
LVD_IBG
AP41
LVD_VBG
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
LVDSA_DATA#0
BA52
LVDSA_DATA#1
AY48
LVDSA_DATA#2
AV47
LVDSA_DATA#3
BB48
LVDSA_DATA0
BA50
LVDSA_DATA1
AY49
LVDSA_DATA2
AV48
LVDSA_DATA3
AP48
LVDSB_CLK#
AP47
LVDSB_CLK
AY53
LVDSB_DATA#0
AT49
LVDSB_DATA#1
AU52
LVDSB_DATA#2
AT53
LVDSB_DATA#3
AY51
LVDSB_DATA0
AT48
LVDSB_DATA1
AU50
LVDSB_DATA2
AT51
LVDSB_DATA3
AA52
CRT_BLUE
AB53
CRT_GREEN
AD53
CRT_RED
V51
CRT_DDC_CLK
V53
CRT_DDC_DATA
Y53
CRT_HSYNC
Y51
CRT_VSYNC
AD48
DAC_IREF
AB51
CRT_IRTN
IBE XPEAK- M_FCBGA 1071
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ46
BG46
BJ48
BG48
BF45
BH45
T51
T53
BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
Y49
AB49
BE44
BD44
AV40
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
U50
U52
BC46
BD46
AT38
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
R2 26
2.2K_0402_5%
R2 27
2.2K_0402_5%
DPD _AUX#
DPD _AUX
DPD _TXN0
DPD_ TXP0
DPD _TXN1
DPD_ TXP1
DPD _TXN2
DPD_ TXP2
DPD _TXN3
DPD_ TXP3
DP D_H PD
R2 35 100K_ 0402_5%
1 2
SDVO
Display Port B
Display Port C
+3VS
DP D_CT RLCLK < 17>
DPD _CTRL DATA < 17>
DPD _AUX# < 17>
DPD _AUX <17 >
DP D_H PD <17>
DPD _TXN0 <17>
DPD_T XP0 <17>
DPD _TXN1 <17>
DPD_T XP1 <17>
DPD _TXN2 <17>
DPD_T XP2 <17>
DPD _TXN3 <17>
DPD_T XP3 <17>
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digita l Disp lay In terface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
VGATE
B B
A A
5
P M_CLK RUN#
SYS _RS T#
LOW _BAT_ R
SLP _LAN#
IBE X_R#
PCI E_WA KE#
AC_ PRES ENT
1 2
R2 37 10K _0402_5 %
1 2
R2 38 10K _0402_5 %@
1 2
R2 39 10K _0402_5 %
1 2
R2 41 10K _0402_5 %@
1 2
R2 43 10K _0402_5 %
1 2
R2 45 1K _0402_5%
1 2
R2 46 10K _0402_5 %
+3VS
+3V ALW
SLP _S3#
SLP _S4#
SLP _S5#
1 2
R2 36 10K _0402_5 %
1 2
R2 40 10K _0402_5 %@
1 2
R2 42 10K _0402_5 %@
1 2
R2 44 10K _0402_5 %@
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/09/15 2009/09/03
Compal Secret Data
Deciphered Date
2
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(3/6)-DMI/GPIO/LVDS
LA -61 61P
1
13 41T uesd ay, M ay 1 8, 20 10
0. 5
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