COMPAL LA-6132P Schematics

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COMPAL CONFIDENTIAL

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MODEL NAME :

1 1

PCB NO : BOM P/N :

LA-6132P ( DA80000I500) DAZ0DD00200 43185331L01 (K325)

NLM01

43185331L02 (K125) 43185331L03 (V105)

M10 Andros

AMD ASB2/ RS880M / SB820M

2 2

2010-05-11

REV : 1.0(A00)

@ : Nopop Component

3 3

WWAN@: WWAN function NONWWAN@: NON WWAN function CONN@: Connector only

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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Title

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Compal Electronics, Inc.

Cover Sheet

LA-6132P

145Tuesday, May 11, 2010

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Thermal Sensor

EMC1402 x 2

1 1

2 2

(CPU/NB)

Page 8/13 Page 16 Page 18

GPP PCIE0

LAN Atheros AR8132

RJ45 conn.

Page 20

DC/DC

3 3

(Power Control)

Clock Generator

Page 20

Page 30

SB820M Internal CKG

LVDS conn.

HDMI conn.

CRT conn.

Mini Card

WLAN WWAN

Power Button

Spread Spectrum

ECS2P8211

Page 27

Page 22

Page 24

GPP PCIE1 GPP PCIE2

LVDS

TMDS

VGA

PCI Express

Mini Card

Page 28 Page 28

Sub/B

LPC BUS

AMD ASB2

K325 / 2C / 1.3G / 2M K125 / 1C / 1.7G / 1M

Page 6,7,8,9

Hyper Transport Link

HT3 16x16 1.0GHz up to 1.6GHz

AMD-RS880M

BGA 528

Page 12,13,14,15

A-Link Express

4 x PCIE

AMD-SB820M

BGA 605

Page 16,17,18,19

DDR3 BUS

SidePort

USB2.0

DDR3-SO-DIMM X2

DDR3 64x16Mb 128MB LFB

USB port2

USB port0,1

USB port4

USB port5

USB port6

USB port8

USB port9

Page 10, 11

Dual Channel DDRIII 800MHz

Page 14

USB conn.

USB conn. x 2

Sub/B & Page 23

Mini Card WLAN

Mini Card WWAN

Bluetooth conn.

CardBus Realtek RTS5138

Camera

Page 33

Page 28

Page 21

Page 27

SIM conn.

Page 28

3 in 1 conn.

Page 21

EC

Power Circuit

+3VALW / +5VALW +1.1VALW +0.75VS +1.5V +1.8V +2.5VDDA / +CPU_VDDR +CPU_CORE / +VDDNB +NB_CORE

Page 36~43

4 4

BATT IN &OTP

Page 33

DC IN & DECTOR

Page 34

CHARGER

Page 35

ENE KB926

T/P conn.

Page 31

Page 26

AZ-Audio I/F

Int. KBD

Page 26

SPI ROM

Page 31

CODEC Realtek ALC259

Sub/B

Audio Jack x 2

Digital MIC

Sub/B

Camera side

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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Compal Electronics, Inc.

Block Diagram

Block Diagram LA-6132P

LA-6132P

245Monday, May 03, 2010

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SB820M

POWER STATES

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M1

S4 (Suspend to DISK) / M1 ON ON ONOFF

S5 (SOFT OFF) / M1 ON ON ONOFFLOW LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

Signal

SLP

S3#

S4#

HIGH HIGH HIGH

HIGH

LOW HIGH HIGH HIGH ON ON ON ONOFF

LOW

LOW HIGH HIGHLOW

LOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP S5#

HIGH

S4 STATE#

SLP M#

HIGH

ALWAYS PLANE

ON

M PLANE

ON

SUS

RUN

PLANE

ON ON ON

OFF

CLOCKS

USB PORT#

0 1 2 3 4 5 6 7

DESTINATION USB (Right) USB (Right) USB (Left)

None

MINI CARD - WLAN MINI CARD - WWAN Bloetooth

None

Card Reader8

C C

PM TABLE

State

power plane

B+ +5VALW +3VALW +1.1VALW

+1.5V

+5VS +3VS +1.8VS +1.5VS +1.1VS +0.75VS +2.5VDDA +CPU_VDDR +NB_CORE +CPU_CORE +VDDNB

9

11 12 13

Camera

None10 None None None

RS880M

S0

S3

B B

S5 S4/AC

S5 S4/AC don't exist

ON

ON ON

ON

OFF

OFFOFF

OFFON

OFF

PCIE Lane 1 Lane 2 Lane 3 Lane 4 Lane 5

DESTINATION 10 / 100 LAN MINI CARD - WLAN MINI CARD - WWAN None None

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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Compal Electronics, Inc.

Index and Config.

LA-6132P

345Monday, May 03, 2010

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ADAPTER

EN_INVPWR

INVPWR_B+SI3457

(QV6)

D D

VR_ON

ISL6265

+CPU_CORE

(PU14)

BATTERY

+PWR_SRC

+VDDNB

CHARGER

TPS51427

(PU2)

MAINPWON

C C

TPS51218

(PU15)

TPS2062

(UI13)

+5VALW

TPS2062

(UI14)

TPS2062

(UI15)

NTMS4920

(QZ3)

TPS51218

(PU10)

TPS51218

(PU7)

+3VALW

NTMS4920

(QZ8)

SI3456DY

(QZ11)

APL5912

(PU11)

SUSP#

B B

+NB_CORE

A A

USB_EN#

+USB_VCCA

+5V_ESAUSB

USB_PWR_EN#

USB_EN#

+USB_SIDE _PWR

CAM_ON/OFF#

SUSP

+5VS

SI2301 (QO4)

+5VS_CAM

SYSON

+1.5V

SI4634DY

(QZ12)

SUSP

+1.5VS

APL5912

(PU12)

SUSP#

+CPU_VDDR

(0.9V)

APL5331

(PU8)

SUSP

+0.75VS

POK

+1.1VALW

SI4634DY

(QZ15)

SUSP

+1.1VS

SUSP

+3VS

APL5508

(PU13)

+2.5VDDA

EN_WOL#

+3V_LAN

AO3413

(QV8)

ENVDD LCD_VCC_TEST_EN

+LCD_VDD

SUSP#

+1.8VS

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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Compal Electronics, Inc.

Power Rail

Power Rail LA-6132P

LA-6132P

445Monday, May 03, 2010

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1K

D D

AN4

ASB2

AN5

CPU_SIC CPU_SID

1K

2.2K

+1.5V

+3VS

MMBT3904 MMBT3904

UT5 @

8

(CPU_Thermal)

7

SMBUS Address [TBD]

2.2K

AD22

MEM_SMBCLK

AE22

C C

MEM_SMBDATA

10K

+3VALW

10K

F5

SB_SMB_CLK1

F4

SB 820M

SB_SMB_DAT1

10K

+3VALW

10K

D25

SB_SMB_CLK2

F23

SB_SMB_DAT2

1K

+1.5V

202 200

8 7

JDIMMA

JDIMMB

UT7 (NB_Thermal)

SMBUS Address [TBD]

1K

B26

SB_SMB_CLK3

F26

B B

SB_SMB_DAT3

0R @ 0R @

4.7K

77

EC_SMB_CK1

78

EC_SMB_DA1

KB 926

79

EC_SMB_CK2

80

EC_SMB_DA2

A A

100R 100R

2.2K @

+5VALW

PJBATT

7

(BattERy conn)

6

+3VALW +3VS

2.2K

SMBUS Address [TBD]

0R @ 0R @

WWAN_SMB_CK_R WWAN_SMB_DA_R

LAN_SMB_CK_R LAN_SMB_DA_R

30 32

JWLAN1

JWWAN1

UL10 (LAN)

SMBUS Address [TBD]

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SMBus Topology

LA-6132P

545Monday, May 03, 2010

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D D

C C

B B

4

UU1A

K325@

UU1A

K325@

H_CADIP0<12> H_CADIN0<12> H_CADIP1<12> H_CADIN1<12> H_CADIP2<12> H_CADIN2<12> H_CADIP3<12> H_CADIN3<12> H_CADIP4<12> H_CADIN4<12> H_CADIP5<12> H_CADIN5<12> H_CADIP6<12> H_CADIN6<12> H_CADIP7<12> H_CADIN7<12> H_CADIP8<12> H_CADIN8<12> H_CADIP9<12> H_CADIN9<12> H_CADIP10<12> H_CADIN10<12> H_CADIP11<12> H_CADIN11<12> H_CADIP12<12> H_CADIN12<12> H_CADIP13<12> H_CADIN13<12> H_CADIP14<12> H_CADIN14<12> H_CADIP15<12> H_CADIN15<12>

H_CLKIP0<12> H_CLKIN0<12> H_CLKIP1<12> H_CLKIN1<12>

H_CTLIP0<12> H_CTLIN0<12> H_CTLIP1<12> H_CTLIN1<12>

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15

H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1

H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1

H2 H1 K2 K1 K3

K4 M2 M1

P2

P1

P3

P4

T2

T1

T3

T4

G6

G5

H4

H3

J6 J5 L6

L5 P6 P5 R7 R6 U6 U5

W7 W6

M3 M4 M8 M7

V2 V1 Y6 Y5

ASB2_BGA812

L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15

L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1

L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1

3

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12

HT LINK

L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

2

H_CADOP0

AK1

H_CADON0

AK2

H_CADOP1

AF4

H_CADON1

AF3

H_CADOP2

AF1

H_CADON2

AF2

H_CADOP3

AD4

H_CADON3

AD3

H_CADOP4

AB4

H_CADON4

AB3

H_CADOP5

AB1

H_CADON5

AB2

H_CADOP6

Y4

H_CADON6

Y3

H_CADOP7

Y1

H_CADON7

Y2

H_CADOP8

AH1

H_CADON8

AH2

H_CADOP9

AK3

H_CADON9

AK4

H_CADOP10

AH3

H_CADON10

AH4

H_CADOP11

AE9

H_CADON11

AE8

H_CADOP12

AE6

H_CADON12

AE5

H_CADOP13

AC7

H_CADON13

AC6

H_CADOP14

AB9

H_CADON14

AB8

H_CADOP15

AB6

H_CADON15

AB5

H_CLKOP0

AD1

H_CLKON0

AD2

H_CLKOP1

AF6

H_CLKON1

AF5

H_CTLOP0

V4

H_CTLON0

V3

H_CTLOP1

Y8

H_CTLON1

Y9

H_CADOP0 <12> H_CADON0 <12> H_CADOP1 <12> H_CADON1 <12> H_CADOP2 <12> H_CADON2 <12> H_CADOP3 <12> H_CADON3 <12> H_CADOP4 <12> H_CADON4 <12> H_CADOP5 <12> H_CADON5 <12> H_CADOP6 <12> H_CADON6 <12> H_CADOP7 <12> H_CADON7 <12> H_CADOP8 <12> H_CADON8 <12> H_CADOP9 <12> H_CADON9 <12> H_CADOP10 <12> H_CADON10 <12> H_CADOP11 <12> H_CADON11 <12> H_CADOP12 <12> H_CADON12 <12> H_CADOP13 <12> H_CADON13 <12> H_CADOP14 <12> H_CADON14 <12> H_CADOP15 <12> H_CADON15 <12>

H_CLKOP0 <12> H_CLKON0 <12> H_CLKOP1 <12> H_CLKON1 <12>

H_CTLOP0 <12> H_CTLON0 <12> H_CTLOP1 <12> H_CTLON1 <12>

1

UU1

V105@UU1

K125@UU1

K125@

ASB2_BGA812

V105@UU1

ASB2_BGA812

SA00003RI0L SA00003TL0L

V105 PART NO. need apply again

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ASB2 HT I/F & FAN

LA-6132P

645Tuesday, May 04, 2010

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UU1B

K325@

UU1B

K325@

DDR_A_MA0<10> DDR_A_MA1<10> DDR_A_MA2<10> DDR_A_MA3<10> DDR_A_MA4<10> DDR_A_MA5<10> DDR_A_MA6<10>

D D

C C

B B

A A

DDR_A_MA7<10> DDR_A_MA8<10> DDR_A_MA9<10> DDR_A_MA10<10> DDR_A_MA11<10> DDR_A_MA12<10> DDR_A_MA13<10> DDR_A_MA14<10> DDR_A_MA15<10>

DDR_A_BS0<10> DDR_A_BS1<10> DDR_A_BS2<10>

DDR_A_DQS0<10> DDR_A_DQS#0<10> DDR_A_DQS1<10> DDR_A_DQS#1<10> DDR_A_DQS2<10> DDR_A_DQS#2<10> DDR_A_DQS3<10> DDR_A_DQS#3<10> DDR_A_DQS4<10> DDR_A_DQS#4<10> DDR_A_DQS5<10> DDR_A_DQS#5<10> DDR_A_DQS6<10> DDR_A_DQS#6<10> DDR_A_DQS7<10> DDR_A_DQS#7<10>

M_CLK_DDR1<10> M_CLK_DDR#1<10> M_CLK_DDR0<10> M_CLK_DDR#0<10>

DDR_CKE0_DIMMA<10> DDR_CKE1_DIMMA<10>

M_ODT0<10> M_ODT1<10>

DDR_CS0_DIMMA#<10> DDR_CS1_DIMMA#<10>

DDR_A_RAS#<10> DDR_A_CAS#<10> DDR_A_WE#<10>

DDR_A_RST#<10>

DDR_A_EVENT#<10>

CPU_MEMHOT#<18>

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR0 M_CLK_DDR#0

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

M_ODT0 M_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_RST# DDR_A_EVENT#

5

AC26

W29

AB29

Y30

U27

V30 U28 R27 R26

P27

AC28

T30

P28

AG28

M29

P30

AE28 AC29

R29

H27 H29

L29

L28

F29 G29

J29

K30

E12

F12 G17 H17

E25

F25

E28

F28

AG26 AH26 AH22 AG22 AG15 AH15

AJ11

AK12

J27 J26

E20

E19 D18

F19

P26 M26 W27 W26

AB27 AB26

Y28

Y27

AH17 AG17 AK18

AJ17

M28 M30

AG29

AJ30

AF27

AJ29

AF29 AH30 AE29 AH29

AC27 AF30 AE27

L27 M32

RU64

2.2K_0402_5%

QU6

MMBT3904_NL_SOT23-3

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_CHECK0 MA_CHECK1 MA_CHECK2 MA_CHECK3 MA_CHECK4 MA_CHECK5 MA_CHECK6 MA_CHECK7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 MA_DQS_H8 MA_DQS_L8

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3 MA_CLK_H4 MA_CLK_L4 MA_CLK_H5 MA_CLK_L5 MA_CLK_H6 MA_CLK_L6 MA_CLK_H7 MA_CLK_L7

MA_CKE0 MA_CKE1

MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1

MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1

MA_RAS_L MA_CAS_L MA_WE_L

MA_RESET_L FREE|MA_EVENT_L

ASB2_BGA812

+1.5V +1.5V

12

2

DDRIII CHANNEL A

RU65

2.2K_0402_5%

31

QU7

MMBT3904_NL_SOT23-3

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 MA_DM8

12

RU66

2.2K_0402_5%

2

31

MMBT3904_NL_SOT23-3

QU8

+3VS

F11 E11 E14 E15 H12 G12 H14 H15 E17 D16 F22 D20 F15 G15 G20 G22 G23 D22 G26 F26 E22 H22 D24 H25 H26 F27 E29 F30 E26 D26 G28 D28 AJ28 AJ26 AG25 AJ25 AK30 AH27 AF25 AF23 AG23 AJ23 AF20 AF19 AK24 AF22 AJ20 AG20 AG19 AF17 AG14 AF14 AK20 AH19 AF15 AK14 AH12 AG12 AF12 AF11 AJ14 AJ12 AH11 AG11

G14 H19 E23 E27 AJ27 AK22 AK16 AL12 H30

12

2

31

4

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_EVENT#

DDR_B_EVENT#

SB_MEMHOT#

3

Processor DDR3 Memory Interface

DDR_A_D0 <10> DDR_A_D1 <10> DDR_A_D2 <10> DDR_A_D3 <10> DDR_A_D4 <10> DDR_A_D5 <10> DDR_A_D6 <10> DDR_A_D7 <10> DDR_A_D8 <10> DDR_A_D9 <10> DDR_A_D10 <10> DDR_A_D11 <10> DDR_A_D12 <10> DDR_A_D13 <10> DDR_A_D14 <10> DDR_A_D15 <10> DDR_A_D16 <10> DDR_A_D17 <10> DDR_A_D18 <10> DDR_A_D19 <10> DDR_A_D20 <10> DDR_A_D21 <10> DDR_A_D22 <10> DDR_A_D23 <10> DDR_A_D24 <10> DDR_A_D25 <10> DDR_A_D26 <10> DDR_A_D27 <10> DDR_A_D28 <10> DDR_A_D29 <10> DDR_A_D30 <10> DDR_A_D31 <10> DDR_A_D32 <10> DDR_A_D33 <10> DDR_A_D34 <10> DDR_A_D35 <10> DDR_A_D36 <10> DDR_A_D37 <10> DDR_A_D38 <10> DDR_A_D39 <10> DDR_A_D40 <10> DDR_A_D41 <10> DDR_A_D42 <10> DDR_A_D43 <10> DDR_A_D44 <10> DDR_A_D45 <10> DDR_A_D46 <10> DDR_A_D47 <10> DDR_A_D48 <10> DDR_A_D49 <10> DDR_A_D50 <10> DDR_A_D51 <10> DDR_A_D52 <10> DDR_A_D53 <10> DDR_A_D54 <10> DDR_A_D55 <10> DDR_A_D56 <10> DDR_A_D57 <10> DDR_A_D58 <10> DDR_A_D59 <10> DDR_A_D60 <10> DDR_A_D61 <10> DDR_A_D62 <10> DDR_A_D63 <10>

DDR_A_DM0 <10> DDR_A_DM1 <10> DDR_A_DM2 <10> DDR_A_DM3 <10> DDR_A_DM4 <10> DDR_A_DM5 <10> DDR_A_DM6 <10> DDR_A_DM7 <10>

DDR_A_EVENT# DDR_B_EVENT#

SB_MEMHOT#

RU1 1K_0402_5%RU1 1K_0402_5% RU2 1K_0402_5%RU2 1K_0402_5%

RU68 2.2K_0402_5%RU68 2.2K_0402_5%

DDR_A_EVENT# <10>

DDR_B_EVENT# <11>

SB_MEMHOT# <16>

12 12

12

+1.5V

+3VS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

UU1C

K325@

UU1C

K325@

DDR_B_MA0<11> DDR_B_MA1<11> DDR_B_MA2<11> DDR_B_MA3<11> DDR_B_MA4<11> DDR_B_MA5<11> DDR_B_MA6<11> DDR_B_MA7<11> DDR_B_MA8<11> DDR_B_MA9<11> DDR_B_MA10<11> DDR_B_MA11<11> DDR_B_MA12<11> DDR_B_MA13<11> DDR_B_MA14<11> DDR_B_MA15<11>

DDR_B_BS0<11> DDR_B_BS1<11> DDR_B_BS2<11>

DDR_B_DQS0<11> DDR_B_DQS#0<11> DDR_B_DQS1<11> DDR_B_DQS#1<11> DDR_B_DQS2<11> DDR_B_DQS#2<11> DDR_B_DQS3<11> DDR_B_DQS#3<11> DDR_B_DQS4<11> DDR_B_DQS#4<11> DDR_B_DQS5<11> DDR_B_DQS#5<11> DDR_B_DQS6<11> DDR_B_DQS#6<11> DDR_B_DQS7<11> DDR_B_DQS#7<11>

M_CLK_DDR3<11> M_CLK_DDR#3<11> M_CLK_DDR2<11> M_CLK_DDR#2<11>

DDR_CKE2_DIMMB<11> DDR_CKE3_DIMMB<11>

M_ODT2<11> M_ODT3<11>

DDR_CS2_DIMMB#<11> DDR_CS3_DIMMB#<11>

DDR_B_RAS#<11> DDR_B_CAS#<11> DDR_B_WE#<11>

DDR_B_RST#<11>

DDR_B_EVENT#<11>

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7

M_CLK_DDR3 M_CLK_DDR#3 M_CLK_DDR2 M_CLK_DDR#2

DDR_CKE2_DIMMB DDR_CKE3_DIMMB

M_ODT2 M_ODT3

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_RST# DDR_B_EVENT#

AC33

W33

AD32

AJ33

AE33 AD33

AN30 AM30 AN26 AM26

AL20 AM20 AM14 AN14

AD31 AD30 AB31 AB30 AB33 AB32 AA32 AA33 AN21 AM21 AN22 AM22

AH33 AK32 AH31 AK31

AF31

AJ32 AF33 AK33

AF32 AH32 AG33

M33

Y32 Y33 Y31

V31 V33 U33 V32 T33

T31 T32

P31 P33

R33

G33 H31 K32 L33 F32 G32 K31 K33

B16 A15 A21 B20 B28 A28 D33 D32

J33

H32

A22 A23 C22 B22

P32 N33

L32

ASB2_BGA812

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_CHECK0 MB_CHECK1 MB_CHECK2 MB_CHECK3 MB_CHECK4 MB_CHECK5 MB_CHECK6 MB_CHECK7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 MB_DQS_H8 MB_DQS_L8

MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3 MB_CLK_H4 MB_CLK_L4 MB_CLK_H5 MB_CLK_L5 MB_CLK_H6 MB_CLK_L6 MB_CLK_H7 MB_CLK_L7

MB_CKE0 MB_CKE1

MB0_ODT0 MB0_ODT1 MB1_ODT0 MB1_ODT1

MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 MB1_CS_L1

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L FREE|MB_EVENT_L

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35

DDRIII CHANNEL B

MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 MB_DM8

A14 C14 A17 B18 A13 B14 A16 C16 A19 C20 C24 A25 A18 C18 B24 A24 C26 A27 A30 B30 A26 B26 A29 C30 B32 C32 F31 F33 A31 B31 D31 E33 AM32 AM31 AN29 AK28 AL33 AL32 AL30 AM29 AM28 AN27 AN25 AL24 AL28 AN28 AL26 AM25 AN23 AL22 AN18 AM18 AN24 AM24 AN19 AL18 AN16 AM16 AM12 AN12 AN17 AL16 AL14 AN13

D14 A20 C28 C33 AN31 AK26 AN20 AN15 H33

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

1

DDR_B_D0 <11> DDR_B_D1 <11> DDR_B_D2 <11> DDR_B_D3 <11> DDR_B_D4 <11> DDR_B_D5 <11> DDR_B_D6 <11> DDR_B_D7 <11> DDR_B_D8 <11> DDR_B_D9 <11> DDR_B_D10 <11> DDR_B_D11 <11> DDR_B_D12 <11> DDR_B_D13 <11> DDR_B_D14 <11> DDR_B_D15 <11> DDR_B_D16 <11> DDR_B_D17 <11> DDR_B_D18 <11> DDR_B_D19 <11> DDR_B_D20 <11> DDR_B_D21 <11> DDR_B_D22 <11> DDR_B_D23 <11> DDR_B_D24 <11> DDR_B_D25 <11> DDR_B_D26 <11> DDR_B_D27 <11> DDR_B_D28 <11> DDR_B_D29 <11> DDR_B_D30 <11> DDR_B_D31 <11> DDR_B_D32 <11> DDR_B_D33 <11> DDR_B_D34 <11> DDR_B_D35 <11> DDR_B_D36 <11> DDR_B_D37 <11> DDR_B_D38 <11> DDR_B_D39 <11> DDR_B_D40 <11> DDR_B_D41 <11> DDR_B_D42 <11> DDR_B_D43 <11> DDR_B_D44 <11> DDR_B_D45 <11> DDR_B_D46 <11> DDR_B_D47 <11> DDR_B_D48 <11> DDR_B_D49 <11> DDR_B_D50 <11> DDR_B_D51 <11> DDR_B_D52 <11> DDR_B_D53 <11> DDR_B_D54 <11> DDR_B_D55 <11> DDR_B_D56 <11> DDR_B_D57 <11> DDR_B_D58 <11> DDR_B_D59 <11> DDR_B_D60 <11> DDR_B_D61 <11> DDR_B_D62 <11> DDR_B_D63 <11>

DDR_B_DM0 <11> DDR_B_DM1 <11> DDR_B_DM2 <11> DDR_B_DM3 <11> DDR_B_DM4 <11> DDR_B_DM5 <11> DDR_B_DM6 <11> DDR_B_DM7 <11>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

ASB2 DDRIII MEMORY I/F

LA-6132P

745Tuesday, May 04, 2010

1

1.0

of

5

+1.1VS

+1.5V

+CPU_VDDR

D D

CPU_ALERT#

C C

B B

A A

CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO

+1.5V

12

RU6

+1.5V

12

RU14

CPU_SID

+1.5V

12

RU22

CPU_SIC

RU60

1 2

VGATE<26,42>

0_0402_5%

CPU_PWRGD<16>

LDT_STOP#<13,16>

LDT_RST#<16>

Layout : Resistor placed close to CPU, trace reference to GND, keep spacing 15mil to other signal.

+1.5V

@

12

1 2

RU57 10_0402_5%@ RU57 10_0402_5%@

1 2

RU58 10_0402_5%@ RU58 10_0402_5%@

1 2

RU59 10_0402_5%@ RU59 10_0402_5%@

+1.5V

12

RU4

@

2.2K_0402_5%

2

1K_0402_5%

QU2

@ QU2

@

3 1

MMBT3904_NL_SOT23-3

+1.5V

12

RU15

2.2K_0402_5%

1K_0402_5%

DU1 CH751H-40PT_SOD323-2DU1 CH751H-40PT_SOD323-2

1K_0402_5%

DU2 CH751H-40PT_SOD323-2DU2 CH751H-40PT_SOD323-2

@

RU50220_0402_5%~D

12

2.2K_0402_5%

2

QU4

3 1

MMBT3904_NL_SOT23-3

2 1

+1.5V

12

RU20

2.2K_0402_5%

2

QU5

3 1

MMBT3904_NL_SOT23-3

2 1

+1.5VS

12

@RU60

@

RU28

RU28 300_0402_5%~D

300_0402_5%~D

+1.5VS

12

RU36

RU36 300_0402_5%~D

300_0402_5%~D

+1.5VS

12

RU46

RU46 300_0402_5%~D

300_0402_5%~D

@

RU53220_0402_5%~D

RU54300_0402_5%~D RU54300_0402_5%~D

RU51220_0402_5%~D

RU52220_0402_5%~D

12

5

+3VS

12

RU7

SMB_ALERT#

CPU_PWRGD

LDT_STOP#

LDT_RST#

RU55300_0402_5%~D

CPU_VLDT_SENSE CPU_VDDIO_FB_H CPU_VDDR_SENSE

4.7K_0402_5%

+2.5VDDA

SMB_ALERT# <13,18,26>

EC_SMB_DA2

1 2

FBM_L11_201209_300L_0805

1

+

150U_B2_6.3VM_R45M

2

EC is PU to 3VALW

EC_SMB_CK2

CPU_SVC_R CPU_SVC CPU_SVD_R

HDT Connector

CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO

+1.5V

4

LU1

CU1

CLK_HT_CPU_P<16>

CLK_HT_CPU_N<16>

EC_SMB_DA2 <20,26,28>

EC_SMB_CK2 <20,26,28>

TU21TU21 TU22TU22 TU23TU23

CPU_VDD0_RUN_FB_L CPU_VDD0_RUN_FB_H CPU_VDDNB_RUN_FB_H

Place close to CPU

RU44

1 2

0_0402_5%

RU45

1 2

0_0402_5%

RU47

1 2

0_0402_5%

VID Override Circuit

SB_PWRGD<13,18,26>

LDT_RST#

JPTU1 CONN@

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423 26

SAMTEC_ASP-68200-07

4

LAYOUT: ROUTE VDDA TRACE APPROX. 50 mils WIDE (USE 2x25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.

1

CU3

CU2

2

4.7U_0603_6.3V6K

1 2

CU5

169_0402_1%~D

1 2

CU6 3900P_0402_50V7K~DCU6 3900P_0402_50V7K~D

+1.5VS

12

RU38

RU39

1K_0402_5%

+3VALW

SB_PWRGD

2 1

HDT_RST#

1

CU4

2

0.22U_0603_10V7K~D

0.22U_0603_10V7K~D 3900P_0402_50V7K~D

3900P_0402_50V7K~D

12

RU5

SB_SMB_CLK3<18>

SB_SMB_DAT3<18>

TSI to SB SMBUS3

PLACE THEM CLOSE TO CPU WITHIN 1"

12

@

RU40

2.2K_0402_5%

1K_0402_5%

CPU_PWRGD_SVID_REGCPU_PWRGD

Close to LDT_RST# trace

5

UU6

P

B

4

Y

A

G

NC7SZ08P5X_NL_SC70-5

3

@

+CPU_VDDA

3300P_0402_50V7K~D

CPU_VDD0_RUN_FB_L<42> CPU_VDD0_RUN_FB_H<42>

CPU_VDDNB_RUN_FB_H<42>

CU72 0.1U_0402_16V7K

12

@

TU4TU4 TU5TU5

TU8TU8 TU9TU9 TU11TU11 TU12TU12

CPU_SVD

HDT_RST#

3

CPU_CLKIN_SC_P CPU_CLKIN_SC_N

CPU_PWRGD LDT_STOP# LDT_RST#

@

CPU_SIC

RU90_0402_5%@RU90_0402_5%

1 2

CPU_SID

RU120_0402_5%@RU120_0402_5%

1 2

@

CPU_ALERT#

CPU_TDI CPU_TRST# CPU_TCK CPU_TMS CPU_DBREQ#

CPU_VDD0_RUN_FB_L CPU_VLDT_SENSE CPU_VDD0_RUN_FB_H CPU_VDDNB_RUN_FB_H CPU_VDDIO_FB_H CPU_VDDR_SENSE

+CPU_M_VREF

RU21 39.2_0402_1%RU21 39.2_0402_1%

1 2

CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1

CPU_TEST9_ANALOGIN

CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0

CPU_TEST7_ANALOG_T CPU_TEST6_DIECRACKMON CPU_TEST3 CPU_TEST2

CPU_SVC <42> CPU_SVD <42> CPU_PWRGD_SVID_REG <42>

+1.5V

RU49

RU56

UU1D

K325@

UU1D

K325@

A8

VDDA_1

B8

VDDA_2

A6

CLKIN_H

A7

CLKIN_L

D10

PWROK

E9

LDTSTOP_L

F9

RESET_L

AN4

SIC

AN5

SID

AM2

RSVD_SA0

AN3

ALERT_L

AM8

TDI

AL8

TRST_L

AK8

TCK

AN8

TMS

G9

DBREQ_L

D2

VSS_SENSE

E2

VLDT_SENSE

E1

VDD_SENSE

D1

VDDNB_SENSE

D3

VDDIO_SENSE

C2

VDDR_SENSE

A11 AM9 AN9

AH7

A9 B9 A5 B6

G8

F8 C8 D9

E8

C6

AK5 AJ7

M_VREF M_ZN_H M_ZN_L

BYPASSCLK_H BYPASSCLK_L PLLTEST0 PLLTEST1

ANALOGIN

BP3 BP2 BP1 BP0

ANALOG_T DIECRACKMON GATE0 DRAIN0

ASB2_BGA812

M_ZP M_ZN

LAYOUT:PLACE CLOSE TO CPU

1

CU7

@

2

1 2

1K_0402_1%~D

CU8

1 2

1K_0402_1%~D

0.1U_0402_16V7K

1

CU9

2

0.01U_0402_16V7K

+CPU_M_VREF

1

2

RSVD|CORE_TYPE

MISC

THERMTRIP_L

PROCHOT_L

CPU_PRESENT_L

FBCLKOUT_H

FBCLKOUT_L

SCANSHIFTEN

PLLCHRZ_H

SINGLECHAIN

ANALOGOUT

1000P_0402_50V7K

SVC SVD

THERMDC THERMDA

TDO

DBRDY

RSVD3

HTREF1 HTREF0

SCANCLK1

TSTUPD

SCANEN

SCANCLK2

PLLCHRZ_L

BURNIN_L

DIG_T

M_TEST

CT1

@

2

+1.5V +1.5V

12

RU62

1K_0402_5%

CPU_CORE_TYPE

M31

CPU_SVC_R

C1

CPU_SVD_R

B2

THERMDC_CPU

AL6

THERMDA_CPU

AM5

CPU_THERMTRIP#_R

AK6

CPU_PROCHOT#_R

AN6

CPU_TDO

AN7

CPU_DBRDY

H9

RSVD3

AM6

CPU_PRESENT_L

AJ9

CPU_HTREF1

V10

CPU_HTREF0

V9

CPU_TEST29_H_FBCLKOUT_P

B10

CPU_TEST29_L_FBCLKOUT_N

A10

CPU_TEST24_SCANCLK1

AK7

CPU_TEST23_TSTUPD

AG8

CPU_TEST22_SCANSHIFTEN

AK9

CPU_TEST21_SCANEN

AH9

CPU_TEST20_SCANCLK2

AM7

CPU_TEST28_H_PLLCHRZ_P

G11

CPU_TEST28_L_PLLCHRZ_N

H11

CPU_TEST27_SINGLECHAIN

AJ8

CPU_TEST26_BURNIN_L

AM4

CPU_TEST10_ANALOGOUT

D7

CPU_TEST8_DIG_T

B5

AG9

+3VS

THERMDA_CPU

1

2

2200P_0402_50V7K

THERMDC_CPU SMB_ALERT#

0.1U_0402_16V7K

THERM#

+3VS

THERM# CPU_PROCHOT#

RT2

1 2

0_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

12

RU63

RU63 1K_0402_5%

1K_0402_5%

SB_SMB_CLK3 SB_SMB_DAT3

CT2

@ CT2

@

RT1

1 2

10K_0402_5%

@RT2

@

RU10

1 2 1 2

RU23

1

2

@RT1

@

1

CPU_PROCHOT#_R

1 2

RU67 0_0402_5%RU67 0_0402_5%

10K_0402_5%

QU1

H_THERMTRIP# <18>

CPU_PROCHOT#

RU61 1K_0402_5%RU61 1K_0402_5%

1 2

place them to CPU within 1.5"

RU24 510_0402_1%RU24 510_0402_1%

1 2

RU25 1K_0402_5%RU25 1K_0402_5%

1 2

RU26 1K_0402_5%RU26 1K_0402_5%

1 2

RU27 300_0402_5%~D@RU27 300_0402_5%~D@

1 2

RU29 510_0402_1%RU29 510_0402_1%

1 2

RU30 1K_0402_5%RU30 1K_0402_5%

1 2

RU31 1K_0402_5%RU31 1K_0402_5%

1 2

RU32 1K_0402_5%RU32 1K_0402_5%

1 2

RU33 1K_0402_5%RU33 1K_0402_5%

1 2

RU34 1K_0402_5%RU34 1K_0402_5%

1 2

RU35 300_0402_5%~D@RU35 300_0402_5%~D@

1 2

RU37 300_0402_5%~D@RU37 300_0402_5%~D@

1 2

RU41 1K_0402_5%RU41 1K_0402_5%

1 2

RU42 1K_0402_5%RU42 1K_0402_5%

1 2

RU43 0_0402_5%RU43 0_0402_5%

1 2

RU48 300_0402_5%~D@RU48 300_0402_5%~D@

1 2

EC_SMB_CK2

8

EC_SMB_DA2

7 6 5

CPU_PROCHOT# <16>

+1.5V

+1.1VS

EC_SMB_CK2 <20,26,28> EC_SMB_DA2 <20,26,28>

SMB_ALERT# <13,18,26>

TU1TU1

+1.5V

12

RU11

1K_0402_5%

300_0402_5%~D

1 2

RU13 0_0402_5%RU13 0_0402_5%

TU2TU2

CPU_PRESENT_L

TU3TU3

RU1844.2_0402_1%~D RU1844.2_0402_1%~D RU1944.2_0402_1%~D RU1944.2_0402_1%~D

1 2

80.6_0402_1%~D

TU6TU6 TU7TU7

TU10TU10

1 2 3 4

EMC1402-1-ACZL-TR_MSOP8

VLDT

+1.1VS

route as differential as short as possible testpoint under package

CPU_TEST25_H_BYPASSCLK_H CPU_TEST26_BURNIN_L

CPU_TEST27_SINGLECHAIN

CPU_TEST25_L_BYPASSCLK_L CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST23_TSTUPD CPU_TEST22_SCANSHIFTEN

CPU_TEST15_BP1 CPU_TEST14_BP0

CPU_TEST18_PLLTEST1 CPU_TEST19_PLLTEST0

CPU_TEST9_ANALOGIN

CPU_TEST10_ANALOGOUT

UT5

@UT5

@

VDD DP DN THERM#

SB_PROCHOT#<17>

+1.5V

RU3

1 2 2

3 1

MMBT3904_NL_SOT23-3

SMCLK

SMDATA

ALERT#

GND

SMBus Address: 1001110X (b)

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

ASB2 CTRL & EMC1402

LA-6132P

845Tuesday, May 04, 2010

1

VLDT

1.0

of

5

4

3

2

1

CPU BOTTOMSIDE DECOUPLING

+CPU_CORE

1

CU10

CU11

+CPU_CORE

D D

1

+

CU18

2

C C

+

CU19

CU14

2

@

330U_X_2VM_R6M

+

330U_X_2VM_R6M

2

+CPU_CORE

1

CU23

2

+1.5V

1

CU30

2

+1.5V

1

CU38

2

22U_0805_6.3V6M~D

CU24

22U_0805_6.3V6M~D

CU31

@

22U_0805_6.3V6M~D

CU39

@

22U_0805_6.3V6M~D

1

CU15

2

22U_0805_6.3V6M~D

1

CU25

2

22U_0805_6.3V6M~D

1

CU32

2

10U_0603_6.3V6M

1

CU40

2

10U_0603_6.3V6M

CU12

22U_0805_6.3V6M~D

CU26

22U_0805_6.3V6M~D

CU33

0.22U_0603_10V7K~D

CU41

0.22U_0603_10V7K~D

1

CU16

2

22U_0805_6.3V6M~D

1

CU27

2

22U_0805_6.3V6M~D

1

CU34

2

0.22U_0603_10V7K~D

1

CU42

2

0.22U_0603_10V7K~D

1

CU17

CU13

2

4.7U_0603_6.3V6K

0.22U_0603_10V7K~D

1

CU28

CU29

2

4.7U_0603_6.3V6K

0.22U_0603_10V7K~D

1

CU36

CU35

2

0.1U_0402_16V7K

0.22U_0603_10V7K~D

1

CU44

CU43

2

0.1U_0402_16V7K

0.22U_0603_10V7K~D

1

+VDDNB

2

180P_0402_50V8J~D

CU20

1

2

180P_0402_50V8J~D

1

CU37

2

0.01U_0402_16V7K

1

2

180P_0402_50V8J~D

1

CU21

2

22U_0805_6.3V6M~D

180P_0402_50V8J~D

1

CU22

2

22U_0805_6.3V6M~D

Place close to CPU

+CPU_VDDR

1

CU45

+1.1VS

CU51

2

1

2

B B

CU47

CU46

2

4.7U_0603_6.3V6K

1

CU52

CU53

2

10U_0603_6.3V6M

CU48

2

0.22U_0603_10V7K~D

1

CU54

2

10U_0603_6.3V6M

1

CU49

CU50

2

0.22U_0603_10V7K~D

1

2

Placement need check

CU56

CU55

2

0.22U_0603_10V7K~D

1

2

0.22U_0603_10V7K~D

1

CU57

2

180P_0402_50V8J~D

+1.1VS

1

CU58

@

2

180P_0402_50V8J~D

1

CU60

CU59

@

2

4.7U_0603_6.3V6K

22U_0805_6.3V6M~D

1

CU61

@

2

4.7U_0603_6.3V6K

1

2

4.7U_0603_6.3V6K

DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.5V

1

A A

1

CU63

CU62

Need discuss with AMD

2

4.7U_0603_6.3V6K

2

CU64

4.7U_0603_6.3V6K

5

CU65

2

4.7U_0603_6.3V6K

1

CU66

2

4.7U_0603_6.3V6K

1

CU67

2

0.22U_0603_10V7K~D

1

CU68

2

0.22U_0603_10V7K~D

CU69

CU70

2

180P_0402_50V8J~D

1

CU71

2

180P_0402_50V8J~D

4

180P_0402_50V8J~D

+CPU_CORE

UU1E

K325@

UU1E

AA30 AB28 AE32 AC30 AC32 AE26 AE30 AF28 AG30 AG32 AD25 AA25 AC25

AB25

3

M10 M12

N11 N24

M27 U26

N32 U32 N30

R28 R30 R32 U29 U30 W28 W30 W32

N25 M25

D4 D5 D6 E5 E6 E7 F5 F6 F7 H7 H8

J8

E4 J10 J12 J14 J18 J20 J21 J23

J9 K10 K12 K14 K18 K20 K21 K23

N4 L11 L13

L7 L9

R4

M5

W4

N9 P15 P18

Y26

P29

Y29

V25 P25

K25 L25 T25 Y25

K325@

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43

ASB2_BGA812

UU1F

K325@

UU1F

K325@

VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 VDDIO_14 VDDIO_15 VDDIO_16 VDDIO_17 VDDIO_18 VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36 VDDIO_37 VDDIO_38

ASB2_BGA812

POWER1

POWER2

PROGEN_L

VDD_85 VDD_84 VDD_83 VDD_82 VDD_81 VDD_80 VDD_79 VDD_78 VDD_77 VDD_76 VDD_75 VDD_74 VDD_73 VDD_72 VDD_71 VDD_70 VDD_69 VDD_68 VDD_67 VDD_66 VDD_65 VDD_64 VDD_63 VDD_62 VDD_61 VDD_60 VDD_59 VDD_58 VDD_57 VDD_56 VDD_55 VDD_54 VDD_53 VDD_52 VDD_51 VDD_50 VDD_49 VDD_48 VDD_47 VDD_46 VDD_45 VDD_44

VLDT_A_1 VLDT_A_2 VLDT_A_3 VLDT_A_4 VLDT_B_1 VLDT_B_2 VLDT_B_3 VLDT_B_4

VDDR_1 VDDR_2 VDDR_3 VDDR_4 VDDR_5 VDDR_6 VDDR_7 VDDR_8

VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDNB_6

FREE_1 FREE_2 FREE_3 FREE_4 FREE_5 FREE_6 FREE_7 FREE_8 FREE_9

AE12 AD9 AE21 AD21 AD18 AD14 AD12 AD11 AC5 AE18 AC24 AC12 AC10 AB13 AB11 AE14 AA24 AA12 AA10 Y19 Y16 Y14 W5 W20 W18 W15 AE23 V24 V19 V16 V14 T20 T18 T15 T10 R5 R19 R16 R14 AC4 P24 P20

VLDT already check with AMD need 1.1V

+1.1VS

F1 F2

1.5A

F3 F4 AL1 AL2 AL3 AL4

+CPU_VDDR

A12 B12 C12

0.9V, 1.5A

D12 AK10 AL10 AM10 AN10

+VDDNB

0.9V,4A

A3 A4 B3 B4 C3 C4

+CPU_VDDR

B11

G7 B7 AH8 AJ6 B25 AM3 AN11 P9 P8

18A

+1.5V

3A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B1

N2 N22 N23

B13 B15 B17

M21

B19 B21 B23 B27 B29 B33

C10

P10 P14 P16 P19

P7 C31 D11 D13 D15

R1 D17 D19 D21 D23 D25 D27 R15 R18

R2 R20 D29 D30

D8

E30 E32 F14 F17

R8

T14 T16 F20 T19 T24

T9

U1

F23

N1

G1 G19

G2 G25 G27 N10

2

UU1G

K325@

UU1G

K325@

VSS_1 VSS_28 VSS_29 VSS_30 VSS_2 VSS_3 VSS_4 VSS_27 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_12 VSS_13 VSS_14 VSS_15 VSS_36 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_37 VSS_38 VSS_39 VSS_40 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_115

ASB2_BGA812

GND1

VSS_45 VSS_44 VSS_43 VSS_42 VSS_26 VSS_25 VSS_41 VSS_24 VSS_23 VSS_22 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114

W19 W1 V20 V18 M11 L8 V15 L4 L30 L26 L24 L23 L22 L21 L2 L12 L10 L1 K9 M6 K24 K22 K16 M22 K13 M24 K11 M23 J7 W16 J4 W14 J32 J30 M13 J28 U8 J25 U4 J24 U7 U2 J2 J16 J13 J11 J1 H6 H5 H28 H23 H20 J22 M9 G4 G30 N12

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

UU1H

K325@

UU1H

K325@

AM19

VSS_207

AF7

VSS_167

AF26

VSS_166

AE7

VSS_165

AF8

VSS_168

AF9

VSS_169

AG1

VSS_170

AG2

VSS_171

AG27

VSS_172

AG4

VSS_173

AG5

VSS_174

AG6

VSS_175

AG7

VSS_176

AE4

VSS_164

AE25

VSS_163

AE24

VSS_162

AE22

VSS_161

AE20

VSS_160

AE2

VSS_159

AE16

VSS_158

AE13

VSS_157

AH14

VSS_177

AE11

VSS_156

AE10

VSS_155

AE1

VSS_154

AD24

VSS_153

AD23

VSS_152

AD22

VSS_151

AH20

VSS_178

AH23

VSS_179

AH25

VSS_180

AH28

VSS_181

AD20

VSS_150

AD16

VSS_149

AD13

VSS_148

AD10

VSS_147

AC9

VSS_146

AC8

VSS_145

A2

VSS_214

AC23

VSS_144

AH5

VSS_182

AJ1

VSS_183

AJ15

VSS_184

W2

VSS_116

A32

VSS_213

W8

VSS_117

Y10

VSS_118

Y15

VSS_119

Y18

VSS_120

AJ19

VSS_185

AJ2

VSS_186

AJ22

VSS_187

AJ4

VSS_188

Y20

VSS_121

Y24

VSS_122

AK11

VSS_189

AK13

VSS_190

Y7

VSS_123

AA1

VSS_124

AA11

VSS_125

ASB2_BGA812

Compal Electronics, Inc.

ASB2 PWR & GND

LA-6132P

1

GND2

VSS_191 VSS_192 VSS_193 VSS_194 VSS_126 VSS_127 VSS_128 VSS_195 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_137 VSS_138 VSS_205 VSS_206 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_215

AK15 AK17 AK19 AK21 AA2 AA22 AA23 AK23 AA4 AA9 AB10 AB12 AB21 AB22 AB23 AB24 AK25 AK27 AK29 AJ5 AH6 AL31 AM1 AM13 AB7 AC1 AM15 AM17 AC11 AC13 AC2 AC21 AC22 AM23 AM27 AM33 AN2 AN32 AM11

945Monday, May 03, 2010

1.0

5

DDR_A_MA0<7> DDR_A_MA1<7> DDR_A_MA2<7> DDR_A_MA3<7> DDR_A_MA4<7> DDR_A_MA5<7> DDR_A_MA6<7> DDR_A_MA7<7> DDR_A_MA8<7> DDR_A_MA9<7> DDR_A_MA10<7>

D D

C C

B B

A A

DDR_A_MA11<7> DDR_A_MA12<7> DDR_A_MA13<7> DDR_A_MA14<7> DDR_A_MA15<7>

DDR_A_DQS0<7> DDR_A_DQS#0<7> DDR_A_DQS1<7> DDR_A_DQS#1<7> DDR_A_DQS2<7> DDR_A_DQS#2<7> DDR_A_DQS3<7> DDR_A_DQS#3<7> DDR_A_DQS4<7> DDR_A_DQS#4<7> DDR_A_DQS5<7> DDR_A_DQS#5<7> DDR_A_DQS6<7> DDR_A_DQS#6<7> DDR_A_DQS7<7> DDR_A_DQS#7<7>

+0.75VS

CU73

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

Layout Note: Place near JDIMMA

+1.5V

0.1U_0402_16V7K

@

1

CD4

2

0.1U_0402_16V7K

CD42

1

2

1

CU75

2

0.22U_0603_10V7K~D

0.1U_0402_16V7K

@

1

CD5

2

0.1U_0402_16V7K

CD43

1

2

1

CU76

2

0.22U_0603_10V7K~D

0.1U_0402_16V7K

@

1

CD3

2

+1.5V

0.1U_0402_16V7K

CD41

1

2

Layout Note: Place near JDIMMA.203,204

1

CU74

2

0.22U_0603_10V7K~D

5

0.1U_0402_16V7K

@

1

CD6

2

0.1U_0402_16V7K

CD44

1

2

4.7U_0603_6.3V6K

CD52

1

2

0.22U_0603_10V7K~D

0.1U_0402_16V7K

@

1

CD38

2

0.1U_0402_16V7K

CD45

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K CD53

CD53

1

2

0.1U_0402_16V7K

@

1

CD39

2

0.1U_0402_16V7K

0.1U_0402_16V7K CD47

CD47

CD46

1

2

@

10U_0603_6.3V6M

CD16

1

2

@

+1.5V

1

+

CD15

2

+1.5V

10U_0603_6.3V6M

1

2

1

2

4

+V_DDR_REF_DQ

330U_X_2VM_R6M

10U_0603_6.3V6M

CD48

1

2

@

4

2.2U_0603_6.3V6K

1

CD2

CD1

2

@

+3VS

1000P_0402_50V7K

0.01U_0402_16V7K

1

CD37

2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7> DDR_A_WE#<7>

DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

0.1U_0402_16V7K

2.2U_0603_6.3V6K

1

CD17

CD18

2

DDR_CKE0_DIMMA

DDR_CS1_DIMMA#

RD2 0_0402_5%RD2 0_0402_5% RD3 0_0402_5%RD3 0_0402_5%

1

2

+1.5V

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 M_CLK_DDR0

M_CLK_DDR#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

1 2 1 2

+0.75VS

3

JDIMMA

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F

CONN@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

A15 A14

A11

A7 A6

A4 A2

A0

S0#

G2

+1.5V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DDR_A_RST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63 DDR_A_EVENT#

MEM_SMBDATA MEM_SMBCLK

+0.75VS

DDR_A_RST# <7>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7>

M_CLK_DDR#1 <7>

DDR_A_BS1 <7>

DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>

M_ODT0 <7> M_ODT1 <7>

1000P_0402_50V7K

CD40

DDR_A_EVENT# <7> MEM_SMBDATA <11,13,18> MEM_SMBCLK <11,13,18>

0.01U_0402_16V7K

1

CD7

2

2.2U_0603_6.3V6K

1

CD8

2

SP07000J500

REVERSE TYPE

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

+1.5V +1.5V+V_DDR_REF_DQ +V_DDR_REF_CA

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

12

1

@

2

12

+V_DDR_REF_CA

RD1

RD1 1K_0402_5%

1K_0402_5%

RD7

RD7 1K_0402_5%

1K_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMM A

LA-6132P

RD6

RD6 1K_0402_5%

1K_0402_5%

RD8

RD8 1K_0402_5%

1K_0402_5%

1

DDR_A_D0 <7> DDR_A_D1 <7> DDR_A_D2 <7> DDR_A_D3 <7> DDR_A_D4 <7> DDR_A_D5 <7> DDR_A_D6 <7> DDR_A_D7 <7> DDR_A_D8 <7> DDR_A_D9 <7> DDR_A_D10 <7> DDR_A_D11 <7> DDR_A_D12 <7> DDR_A_D13 <7> DDR_A_D14 <7> DDR_A_D15 <7> DDR_A_D16 <7> DDR_A_D17 <7> DDR_A_D18 <7> DDR_A_D19 <7> DDR_A_D20 <7> DDR_A_D21 <7> DDR_A_D22 <7> DDR_A_D23 <7> DDR_A_D24 <7> DDR_A_D25 <7> DDR_A_D26 <7> DDR_A_D27 <7> DDR_A_D28 <7> DDR_A_D29 <7> DDR_A_D30 <7> DDR_A_D31 <7> DDR_A_D32 <7> DDR_A_D33 <7> DDR_A_D34 <7> DDR_A_D35 <7> DDR_A_D36 <7> DDR_A_D37 <7> DDR_A_D38 <7> DDR_A_D39 <7> DDR_A_D40 <7> DDR_A_D41 <7> DDR_A_D42 <7> DDR_A_D43 <7> DDR_A_D44 <7> DDR_A_D45 <7> DDR_A_D46 <7> DDR_A_D47 <7> DDR_A_D48 <7> DDR_A_D49 <7> DDR_A_D50 <7> DDR_A_D51 <7> DDR_A_D52 <7> DDR_A_D53 <7> DDR_A_D54 <7> DDR_A_D55 <7> DDR_A_D56 <7> DDR_A_D57 <7> DDR_A_D58 <7> DDR_A_D59 <7> DDR_A_D60 <7> DDR_A_D61 <7> DDR_A_D62 <7> DDR_A_D63 <7>

DDR_A_DM0 <7> DDR_A_DM1 <7> DDR_A_DM2 <7> DDR_A_DM3 <7> DDR_A_DM4 <7> DDR_A_DM5 <7> DDR_A_DM6 <7> DDR_A_DM7 <7>

1

1.0

10 45Tuesday, May 04, 2010

1.0

of

5

DDR_B_MA0<7> DDR_B_MA1<7> DDR_B_MA2<7> DDR_B_MA3<7> DDR_B_MA4<7> DDR_B_MA5<7> DDR_B_MA6<7> DDR_B_MA7<7> DDR_B_MA8<7> DDR_B_MA9<7> DDR_B_MA10<7> DDR_B_MA11<7> DDR_B_MA12<7>

D D

C C

B B

A A

DDR_B_MA13<7> DDR_B_MA14<7> DDR_B_MA15<7>

DDR_B_DQS0<7> DDR_B_DQS#0<7> DDR_B_DQS1<7> DDR_B_DQS#1<7> DDR_B_DQS2<7> DDR_B_DQS#2<7> DDR_B_DQS3<7> DDR_B_DQS#3<7> DDR_B_DQS4<7> DDR_B_DQS#4<7> DDR_B_DQS5<7> DDR_B_DQS#5<7> DDR_B_DQS6<7> DDR_B_DQS#6<7> DDR_B_DQS7<7> DDR_B_DQS#7<7>

+1.5V

0.1U_0402_16V7K

@

1

CD21

2

+1.5V

0.1U_0402_16V7K

CD59

1

2

Layout Note: Place near JDIMMB.203,204

+0.75VS

1

CU77

2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7

0.1U_0402_16V7K

@

1

CD22

CD23

2

0.1U_0402_16V7K

CD60

CD61

1

2

1

CU79

CU78

2

0.22U_0603_10V7K~D

5

Layout Note: Place near JDIMMB

0.1U_0402_16V7K

@

1

CD24

2

0.1U_0402_16V7K

CD62

1

2

CD68

1

CU80

2

0.22U_0603_10V7K~D

0.1U_0402_16V7K

@

1

CD56

CD57

2

0.1U_0402_16V7K

CD63

CD64

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K CD69

CD69

1

2

+1.5V

1

2

+1.5V

10U_0603_6.3V6M

@

CD27

1

2

10U_0603_6.3V6M

CD29

1

2

@

CD33

1

+

2

1

2

1

2

+V_DDR_REF_DQ

330U_X_2VM_R6M

10U_0603_6.3V6M

@

CD28

1

2

4

2.2U_0603_6.3V6K

CD19

@

+3VS

1 2

RD4 4.7K_0402_5%RD4 4.7K_0402_5%

0.01U_0402_16V7K

1

CD20

2

DDR_CKE2_DIMMB<7>

DDR_CS3_DIMMB#<7>

0_0402_5%

1000P_0402_50V7K

1

CD55

2

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7> DDR_B_WE#<7>

DDR_B_CAS#<7>

+3VS

RD5

12

0.1U_0402_16V7K

CD35

3

+1.5V +1.5V

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 M_CLK_DDR2

M_CLK_DDR#2 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

+0.75VS

2.2U_0603_6.3V6K

1

CD36

2

JDIMMB

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U8RN-7F

CONN@

DC020811210

REVERSE TYPE

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

DDR_B_RST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_CKE3_DIMMB

74 76

DDR_B_MA15

78

A15 A14

A11

A7 A6

A4 A2

A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 M_CLK_DDR3

M_CLK_DDR#3 DDR_B_BS1

DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT2 M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63 DDR_B_EVENT#

MEM_SMBDATA MEM_SMBCLK

+0.75VS

DDR_B_RST# <7>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>

M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>

M_ODT2 <7> M_ODT3 <7>

1000P_0402_50V7K

0.01U_0402_16V7K

1

CD58

CD25

2

DDR_B_EVENT# <7>

MEM_SMBDATA <10,13,18> MEM_SMBCLK <10,13,18>

2.2U_0603_6.3V6K

1

CD26

2

+V_DDR_REF_CA

1

@

2

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

1

DDR_B_D0 <7> DDR_B_D1 <7> DDR_B_D2 <7> DDR_B_D3 <7> DDR_B_D4 <7> DDR_B_D5 <7> DDR_B_D6 <7> DDR_B_D7 <7> DDR_B_D8 <7> DDR_B_D9 <7> DDR_B_D10 <7> DDR_B_D11 <7> DDR_B_D12 <7> DDR_B_D13 <7> DDR_B_D14 <7> DDR_B_D15 <7> DDR_B_D16 <7> DDR_B_D17 <7> DDR_B_D18 <7> DDR_B_D19 <7> DDR_B_D20 <7> DDR_B_D21 <7> DDR_B_D22 <7> DDR_B_D23 <7> DDR_B_D24 <7> DDR_B_D25 <7> DDR_B_D26 <7> DDR_B_D27 <7> DDR_B_D28 <7> DDR_B_D29 <7> DDR_B_D30 <7> DDR_B_D31 <7> DDR_B_D32 <7> DDR_B_D33 <7> DDR_B_D34 <7> DDR_B_D35 <7> DDR_B_D36 <7> DDR_B_D37 <7> DDR_B_D38 <7> DDR_B_D39 <7> DDR_B_D40 <7> DDR_B_D41 <7> DDR_B_D42 <7> DDR_B_D43 <7> DDR_B_D44 <7> DDR_B_D45 <7> DDR_B_D46 <7> DDR_B_D47 <7> DDR_B_D48 <7> DDR_B_D49 <7> DDR_B_D50 <7> DDR_B_D51 <7> DDR_B_D52 <7> DDR_B_D53 <7> DDR_B_D54 <7> DDR_B_D55 <7> DDR_B_D56 <7> DDR_B_D57 <7> DDR_B_D58 <7> DDR_B_D59 <7> DDR_B_D60 <7> DDR_B_D61 <7> DDR_B_D62 <7> DDR_B_D63 <7>

DDR_B_DM0 <7> DDR_B_DM1 <7> DDR_B_DM2 <7> DDR_B_DM3 <7> DDR_B_DM4 <7> DDR_B_DM5 <7> DDR_B_DM6 <7> DDR_B_DM7 <7>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMM B

DDRIII DIMM B LA-6132P

LA-6132P

11 45Tuesday, May 04, 2010

1

1.0

of

5

UN2B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

D D

PCIE_NRX_LANTX_P0<20> PCIE_NTX_LANRX_P0 <20> PCIE_NRX_LANTX_N0<20>

PCIE_NRX_WLANTX_P1<28> PCIE_NRX_WWANTX_P2<28>

C C

B B

PCIE_NRX_WWANTX_N2<28>

PCIE_NRX_STX_P0<16> PCIE_NRX_STX_N0<16> PCIE_NRX_STX_P1<16> PCIE_NRX_STX_N1<16> PCIE_NRX_STX_P2<16> PCIE_NRX_STX_N2<16> PCIE_NRX_STX_P3<16> PCIE_NRX_STX_N3<16>

PCIE_NRX_LANTX_P0 PCIE_NRX_LANTX_N0 PCIE_NRX_WLANTX_P1 PCIE_NRX_WLANTX_N1 PCIE_NRX_WWANTX_P2 PCIE_NRX_WWANTX_N2

PCIE_NRX_STX_P0 PCIE_NRX_STX_N0 PCIE_NRX_STX_P1 PCIE_NRX_STX_N1 PCIE_NRX_STX_P2 PCIE_NRX_STX_N2 PCIE_NRX_STX_P3 PCIE_NRX_STX_N3

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS880M_FCBGA528

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)

4

GFX_TX0P

GFX_TX0N

GFX_TX1P

GFX_TX1N

GFX_TX2P

GFX_TX2N

GFX_TX3P

GFX_TX3N

GFX_TX4P

GFX_TX4N

GFX_TX5P

GFX_TX5N

GFX_TX6P

GFX_TX6N

GFX_TX7P

GFX_TX7N

GFX_TX8P

GFX_TX8N

GFX_TX9P

GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

HDMI_TXD2P_C

A5

HDMI_TXD2N_C

B5

HDMI_TXD1P_C

A4

HDMI_TXD1N_C

B4

HDMI_TXD0P_C

C3

HDMI_TXD0N_C

B2

HDMI_CLKP_C

D1

HDMI_CLKN_C

D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

PCIE_NTX_LANRX_P0_C

AC1

PCIE_NTX_LANRX_N0_C

AC2

PCIE_NTX_WLANRX_P1_C

AB4

PCIE_NTX_WLANRX_N1_C

AB3

PCIE_NTX_WWANRX_P2_C

AA2

PCIE_NTX_WWANRX_N2_C

AA1 Y1 Y2 Y4 Y3 V1 V2

PCIE_NTX_SRX_P0_C

AD7

PCIE_NTX_SRX_N0_C

AE7

PCIE_NTX_SRX_P1_C

AE6

PCIE_NTX_SRX_N1_C

AD6

PCIE_NTX_SRX_P2_C

AB6

PCIE_NTX_SRX_N2_C

AC6

PCIE_NTX_SRX_P3_C

AD5

PCIE_NTX_SRX_N3_C

AE5

PCE_PCAL

AC8

PCE_NCAL

AB8

CN1 0.1U_0402_16V7KCN1 0.1U_0402_16V7K CN2 0.1U_0402_16V7KCN2 0.1U_0402_16V7K CN3 0.1U_0402_16V7KCN3 0.1U_0402_16V7K CN4 0.1U_0402_16V7KCN4 0.1U_0402_16V7K CN5 0.1U_0402_16V7KCN5 0.1U_0402_16V7K CN6 0.1U_0402_16V7KCN6 0.1U_0402_16V7K CN7 0.1U_0402_16V7KCN7 0.1U_0402_16V7K CN8 0.1U_0402_16V7KCN8 0.1U_0402_16V7K

RN1 1.27K_0402_1%~DRN1 1.27K_0402_1%~D

1 2

RN2

1 2

Place < 100mils from pin AC8 and AB8

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

CN9 0.1U_0402_16V7KCN9 0.1U_0402_16V7K

1 2

CN10 0.1U_0402_16V7KCN10 0.1U_0402_16V7K

1 2

CN11 0.1U_0402_16V7KCN11 0.1U_0402_16V7K

1 2

CN12 0.1U_0402_16V7KCN12 0.1U_0402_16V7K

1 2

CN13 0.1U_0402_16V7KCN13 0.1U_0402_16V7K

1 2

CN14 0.1U_0402_16V7KCN14 0.1U_0402_16V7K

1 2

CN15 0.1U_0402_16V7KCN15 0.1U_0402_16V7K

1 2

CN16 0.1U_0402_16V7KCN16 0.1U_0402_16V7K

1 2

CN20 0.1U_0402_16V7KCN20 0.1U_0402_16V7K

1 2

CN17 0.1U_0402_16V7KCN17 0.1U_0402_16V7K

1 2

CN18 0.1U_0402_16V7KCN18 0.1U_0402_16V7K

1 2

CN21 0.1U_0402_16V7KCN21 0.1U_0402_16V7K

1 2

CN22 0.1U_0402_16V7KCN22 0.1U_0402_16V7K

1 2

CN19 0.1U_0402_16V7KCN19 0.1U_0402_16V7K

1 2

2K_0402_1%~D

+1.1VS

3

HDMI_TXD2P HDMI_TXD2N HDMI_TXD1P HDMI_TXD1N HDMI_TXD0P HDMI_TXD0N HDMI_CLKP HDMI_CLKN

HDMI_TXD2P <22> HDMI_TXD2N <22> HDMI_TXD1P <22> HDMI_TXD1N <22> HDMI_TXD0P <22> HDMI_TXD0N <22> HDMI_CLKP <22> HDMI_CLKN <22>

HDMI

PCIE_NTX_LANRX_P0 PCIE_NTX_LANRX_N0 PCIE_NTX_WLANRX_P1 PCIE_NTX_WLANRX_N1 PCIE_NTX_WWANRX_P2 PCIE_NTX_WWANRX_N2

PCIE_NTX_SRX_P0 <16> PCIE_NTX_SRX_N0 <16> PCIE_NTX_SRX_P1 <16> PCIE_NTX_SRX_N1 <16> PCIE_NTX_SRX_P2 <16> PCIE_NTX_SRX_N2 <16> PCIE_NTX_SRX_P3 <16> PCIE_NTX_SRX_N3 <16>

2

PCIE_NTX_LANRX_N0 <20> PCIE_NTX_WLANRX_P1 <28> PCIE_NTX_WLANRX_N1 <28>PCIE_NRX_WLANTX_N1<28> PCIE_NTX_WWANRX_P2 <28> PCIE_NTX_WWANRX_N2 <28>

UN2A

H_CADOP0<6> H_CADON0<6> H_CADOP1<6> H_CADON1<6> H_CADOP2<6> H_CADON2<6> H_CADOP3<6> H_CADON3<6> H_CADOP4<6> H_CADON4<6> H_CADOP5<6> H_CADON5<6> H_CADOP6<6> H_CADON6<6> H_CADOP7<6> H_CADON7<6>

H_CADOP8<6> H_CADON8<6> H_CADOP9<6> H_CADON9<6> H_CADOP10<6> H_CADON10<6> H_CADOP11<6> H_CADON11<6> H_CADOP12<6> H_CADON12<6> H_CADOP13<6> H_CADON13<6> H_CADOP14<6> H_CADON14<6> H_CADOP15<6> H_CADON15<6>

H_CLKOP0<6> H_CLKON0<6> H_CLKOP1<6> H_CLKON1<6>

H_CTLOP0<6> H_CTLON0<6> H_CTLOP1<6> H_CTLON1<6>

RN3 301_0402_1%~DRN3 301_0402_1%~D

1 2

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7

H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1

H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1

HT_RXCALP HT_RXCALN

Place < 100mils from pin C23 and A24 Place < 100mils from pin B25 and B24

UN2A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCTL1N

C23

HT_RXCALP

A24

HT_RXCALN

RS880M_FCBGA528

HT_TXCALP HT_TXCALN

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H24 H25 L21 L20

M24 M25 P19 R18

B24 B25

PART 1 OF 6

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7

H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15

H_CLKIP0

H_CLKIN0

H_CLKIP1

H_CLKIN1

H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1

HT_TXCALP

HT_TXCALN

1

H_CADIP0 <6> H_CADIN0 <6> H_CADIP1 <6> H_CADIN1 <6> H_CADIP2 <6> H_CADIN2 <6> H_CADIP3 <6> H_CADIN3 <6> H_CADIP4 <6> H_CADIN4 <6> H_CADIP5 <6> H_CADIN5 <6> H_CADIP6 <6> H_CADIN6 <6> H_CADIP7 <6> H_CADIN7 <6>

H_CADIP8 <6> H_CADIN8 <6> H_CADIP9 <6> H_CADIN9 <6> H_CADIP10 <6> H_CADIN10 <6> H_CADIP11 <6> H_CADIN11 <6> H_CADIP12 <6> H_CADIN12 <6> H_CADIP13 <6> H_CADIN13 <6> H_CADIP14 <6> H_CADIN14 <6> H_CADIP15 <6> H_CADIN15 <6>

H_CLKIP0 <6> H_CLKIN0 <6> H_CLKIP1 <6> H_CLKIN1 <6>

H_CTLIP0 <6> H_CTLIN0 <6> H_CTLIP1 <6> H_CTLIN1 <6>

RN4 301_0402_1%~DRN4 301_0402_1%~D

1 2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

RS880M HT / PCIE / HDMI

LA-6132P

12 45Tuesday, May 04, 2010

1

1.0

of

5

STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO. 1 Disable 0 Enable

+3VS +3VS

12

RN5

RN5 3K_0402_5%~D

3K_0402_5%~D

D D

VGA_CRT_VSYNC

12

RN55

RN55 3K_0402_5%~D

3K_0402_5%~D

@

+1.1VS

LN3

1 2

MBK1608221YZF_2P_0603

+1.8VS

C C

B B

A A

1 2

BLM18EG221SN1D_2P_0603

+1.8VS

1 2

BLM18EG221SN1D_2P_0603

+1.8VS

1 2

BLM18EG221SN1D_2P_0603

15mil

LN6

15mil

LN7

15mil

LN8

15mil

LDT_STOP#<8,16>

RS880M: Enables Side port memory

Enables Memory SIDE PORT 1 = Memory Side port Not available 0 = Memory Side port available Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]

12

RN6

@RN6

@

3K_0402_5%~D

VGA_CRT_HSYNC

12

RN9

RN9 3K_0402_5%~D

3K_0402_5%~D

1.1V 65mA

+NB_PLLVDD

1

CN26

2.2U_0603_10V6K~D

2

1.8V 20mA

+NB_PLLVDD18

1

CN30

2.2U_0603_10V6K~D

2

1.8V 120mA

+NB_PCIEPLL

1

CN31

2.2U_0603_10V6K~D

2

1.8V 20mA

+NB_HTPLL

1

CN33

2.2U_0603_10V6K~D

2

+3VS

RN23

RN26

ALLOW_LDTSTOP<16>

+1.8VS

RN56

@ RN56

@

300_0402_5%~D

LDT_STOP#

5

Need CIS symbol

Check List: R=140 ohm

1 2

RN10 140_0402_1%~DRN10 140_0402_1%~D

1 2

RN11 150_0402_1%RN11 150_0402_1%

1 2

RN12 150_0402_1%RN12 150_0402_1%

NB_PWRGD_SB<18>

12

RN54

4.7K_0402_5%

12

0.1U_0402_16V7K

NC7SZ08P5X_NL_SC70-5

12

4.7K_0402_5%

1 2

1

CN90

2

@

RN37 0_0402_5%

1 2

CLK_NB_GFX_CLK_P CLK_NB_GFX_CLK_N

RN53

LDDC_CLK_MCH

LDDC_DATA_MCH

2

B

1

A

4

+3VS

LN1

BLM18EG221SN1D_2P_0603

1 2

+1.8VS

BLM18EG221SN1D_2P_0603

1 2

VGA_CRT_R VGA_CRT_G VGA_CRT_B

RN14 0_0402_5%RN14 0_0402_5%

RN32

0_0402_5%

+1.8VS

5

UN5

P

4

Y

G

3

+AVDD

RN7

+AVDDDI

1 2

0_0603_5%

LN2

+AVDDQ

CLK_HTREFCLK_P<16> CLK_HTREFCLK_N<16>

CLK_NB_REFCLK_P<16> CLK_NB_REFCLK_N<16>

CLK_SB_CLK_P<16> CLK_SB_CLK_N<16>

+1.8VS +3VS

RN30

1K_0402_1%~D

1 2

NB_ALLOW_LDTSTOP

12

RN36

2.2K_0402_5%

NB_LDTSTOP#

3.3V 110mA

1

CN23

2.2U_0603_10V6K~D

2

1.8V 20mA

1

CN24

0.1U_0402_16V7K

2

1.8V 4mA

1

CN25

2.2U_0603_10V6K~D

2

VGA_CRT_R<24> VGA_CRT_G<24> VGA_CRT_B<24>

VGA_CRT_HSYNC<24> VGA_CRT_VSYNC<24> VGA_DDC_CLK<24> VGA_DDC_DATA<24>

RN13 715_0402_1%RN13 715_0402_1%

1 2

LDDC_CLK_MCH<27> LDDC_DATA_MCH<27>

HDMICLK_UMA<22> HDMIDAT_UMA<22>

PLT_RST#<16,20,26,28>

CLK_NB_GFX_CLK_P CLK_NB_GFX_CLK_N

12

15mil

VGA_CRT_R VGA_CRT_G VGA_CRT_B

VGA_CRT_HSYNC VGA_CRT_VSYNC VGA_DDC_CLK VGA_DDC_DATA

DAC_RST

+NB_PLLVDD +NB_PLLVDD18

+NB_HTPLL +NB_PCIEPLL

PLT_RST# NB_PWRGD NB_LDTSTOP# NB_ALLOW_LDTSTOP

CLK_HTREFCLK_P CLK_HTREFCLK_N

CLK_NB_REFCLK_P CLK_NB_REFCLK_N

CLK_SB_CLK_P CLK_SB_CLK_N

LDDC_CLK_MCH

LDDC_DATA_MCH HDMICLK_UMA HDMIDAT_UMA

QN1

for NB_PWRGD glitch (panel flash issue)

AMD suggest

4

3

UN2C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

A8

DDC_CLK0/AUX0P(NC)

B8

DDC_DATA0/AUX0N(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS880M_FCBGA528

+1.8VS

12

RN28

300_0402_5%~D

NB_PWRGD

13

D

S

SB_PWRGD<8,18,26>

SB_PWRGD#

2

G

SSM3K7002FU_SC70-3

SB_PWRGD

10K_0402_5%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

RN33

PART 3 OF 6

2

G

12

CRT/TVOUT

PM

CLOCKs PLL PWR

MIS.

+3VS

RN29

RN29 10K_0402_5%

10K_0402_5%

1 2

13

D

S

TXOUT_L2N(DBG_GPIO0) TXOUT_L3N(DBG_GPIO2)

TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

SUS_STAT#(PWM_GPIO5)

QN2

SSM3K7002FU_SC70-3

TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)

TXOUT_L3P(NC)

TXOUT_U0P(NC) TXOUT_U0N(NC)

TXOUT_U2P(NC) TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC) VSSLTP18(NC)

VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)

VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)

TMDS_HPD(NC)

HPD(NC)

THERMALDIODE_P THERMALDIODE_N

TESTMODE

CT3

2

DFT_GPIO1: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected

LVDS_A0+

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

A13 B13

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

E9 F7 G12

D9 D10

D12 AE8

AD8 D13

LVDS_A0LVDS_A1+ LVDS_A1LVDS_A2+ LVDS_A2-

LVDS_ACLK+ LVDS_ACLK-

+LPVDD

+LVDDR18D

ENVDD NB_LCD_PWM ENBKL

SUS_STAT#_NB

12

1.8V 15mA

RN25

1.8K_0402_5%~D

LVDS_A0+ <27> LVDS_A0- <27> LVDS_A1+ <27> LVDS_A1- <27> LVDS_A2+ <27> LVDS_A2- <27>

LVDS_ACLK+ <27> LVDS_ACLK- <27>

1.8V 300mA

RN16

@

SUS_STAT#_NB

15mil

CN28

0.1U_0402_16V7K

RN18

RN17

@

4.7K_0402_5%

1 2

RN19 0_0402_5%RN19 0_0402_5% RN20 0_0402_5%RN20 0_0402_5%

RN21 0_0402_5%RN21 0_0402_5%

1 2

12 12

12

1

CN27

2.2U_0603_10V6K~D

2

1

2

4.7K_0402_5%

HDMI_HPD <22>

NB_THRMDA

NB_THRMDC

DN1

@ DN1

@

2 1

CH751H-40PT_SOD323-2

1 2

RN8 3K_0402_5%~D@RN8 3K_0402_5%~D@

BLM18EG221SN1D_2P_0603

1 2

BLM18EG221SN1D_2P_0603

1 2

1

CN29

4.7U_0603_6.3V6K

2

ENVDD <27> NB_LCD_PWM <27> ENBKL <27>

SUS_STAT# <18>

LN4

LN5

External Thermal Sensor EMC1402 for RS880M

UT7

NB_THRMDA

1

2

2200P_0402_50V7K

NB_THRMDC SMB_ALERT#

0.1U_0402_16V7K

THERM#_NB

+3VS

1

CT4

2

RT3

1 2

10K_0402_5%

UT7

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

SMCLK

SMDATA

ALERT#

GND

8 7 6 5

MEM_SMBCLK MEM_SMBDATA

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

RS880M SYSTEM I/F

LA-6132P

1

PLT_RST# <16,20,26,28>

SCHOTTKY BARRIER DIODE

+1.8VS

MEM_SMBCLK <10,11,18>

MEM_SMBDATA <10,11,18>

SMB_ALERT# <8,18,26>

13 45Tuesday, May 04, 2010

1

1.0

of

5

UN4

+SPM_VREF1 +SPM_VREF2

SPM_A0

D D

12

@

RN38

100_0402_5%~D

C C

+1.5V_SPM_VDDQ

RN44 10K_0402_5%RN44 10K_0402_5%

SP_DDR3_RST#<18>

B B

1 2

SPM_A1 SPM_A2 SPM_A3 SPM_A4 SPM_A5 SPM_A6 SPM_A7 SPM_A8 SPM_A9 SPM_A10 SPM_A11 SPM_A12 SPM_A13

SPM_BA0 SPM_BA1 SPM_BA2

SPM_CLKP SPM_CLKN SPM_CKE

SPM_ODT SPM_CS# SPM_RAS# SPM_CAS# SPM_WE#

SPM_DQS_P0 SPM_DQS_P1

SPM_DM0 SPM_DM1

SPM_DQS_N0 SPM_DQS_N1

RN45

12

UN4

M8 H1

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7

K7

K9

K1

L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

J1

L1

J9

L9

243_0402_1%

K4W1G1646E-HC12_FBGA96

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

4

SPM_DQ0

E3

SPM_DQ1

F7

SPM_DQ2

F2

SPM_DQ3

F8

SPM_DQ4

H3

SPM_DQ5

H8

SPM_DQ6

G2

SPM_DQ7

H7

SPM_DQ8

D7

SPM_DQ9

C3

SPM_DQ10

C8

SPM_DQ11

C2

SPM_DQ12

A7

SPM_DQ13

A2

SPM_DQ14

B8

SPM_DQ15

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.5V_SPM_VDDQ

40.2_0402_1%~D

+1.5V_SPM_VDDQ +1.5V_SPM_VDDQ +1.5V_SPM_VDDQ

CN36

CN39

RN39

1 2 1 2

RN40

1

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

3

UN2D

SPM_A0 SPM_A1 SPM_A2 SPM_A3 SPM_A4 SPM_A5 SPM_A6 SPM_A7 SPM_A8 SPM_A9 SPM_A10 SPM_A11 SPM_A12 SPM_A13

SPM_BA0 SPM_BA1 SPM_BA2

SPM_RAS# SPM_CAS# SPM_WE# SPM_CS# SPM_CKE SPM_ODT

SPM_CLKP SPM_CLKN

MEMCOMPP MEMCOMPN

12

RN41

1K_0402_1%~D

+SPM_VREF1 +SPM_VREF2 +SPM_VREF

12

RN46

1K_0402_1%~D

UN2D

AB12 AE16

V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14

Y14 AD16

AE17 AD17

W12

Y12 AD18 AB13 AB18

V14

V15

W14

AE12 AD12

RS880M_FCBGA528

MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)

MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)

MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)

MEM_CKP(NC) MEM_CKN(NC)

MEM_COMPP(NC) MEM_COMPN(NC)

CN37

CN40

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)

MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)

MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)

MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

MEM_VREF(NC)

1

2

1

2

RN42

0.1U_0402_16V7K

RN47

0.1U_0402_16V7K

12

1K_0402_1%~D

12

1K_0402_1%~D

2

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23 AE18

SPM_DQ0 SPM_DQ1 SPM_DQ2 SPM_DQ3 SPM_DQ4 SPM_DQ5 SPM_DQ6 SPM_DQ7 SPM_DQ8 SPM_DQ9 SPM_DQ10 SPM_DQ11 SPM_DQ12 SPM_DQ13 SPM_DQ14 SPM_DQ15

SPM_DQS_P0 SPM_DQS_N0 SPM_DQS_P1 SPM_DQS_N1

SPM_DM0 SPM_DM1

+VDD_MUX_IOPLLVDD

+SPM_VREF

1

CN38

2

0.1U_0402_16V7K

1

CN41

2

0.1U_0402_16V7K

BLM18EG221SN1D_2P_0603

1

CN34

2.2U_0603_10V6K~D

2

12

RN43

12

RN48

1.8V 15mA

LN10

1K_0402_1%~D

12

1.1V 26mA

BLM18EG221SN1D_2P_0603

+1.8V_IOPLLVDD

+1.1VS

1

LN9

1

CN35

2.2U_0603_10V6K~D

2

+1.8VS

12

SA00003570L

RN49

1 2

0_0805_5%

1

CN42

2

A A

CN44

CN43

2

0.1U_0402_16V7K

1

CN45

2

1U_0402_6.3V6K

1

CN46

2

1U_0402_6.3V6K

1

CN47

2

10U_0603_6.3V6M

1

2

0_0805_5%

10U_0603_6.3V6M

+1.5VS+1.5V_SPM_VDDQ

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

RS880M SidePort DDR III

LA-6132P

14 45Tuesday, May 04, 2010

1

1.0

of

5

+1.1VS

LN11

+1.1VS_VDDHT

1 2

0_0805_5%

CN48

LN13

1 2

0_0805_5%

LN14

1 2

0_0805_5%

+1.8VS_VDDA18PCIE

12

1

CN75

2

CN86

CN48

+1.1VS_VDDHTRX

CN56

+1.1VS_VDDHTTX

CN61

CN76

4.7U_0603_6.3V6K

+1.8VS_VDD18NB

1

2

1U_0402_6.3V6K

D D

+1.1VS

VDDHTTX already check with AMD need 1.1V

C C

+1.1VS

0805/220Ohm/2000mA MPN:BLM21PG221SN1D CPN:SM010026280 220 ohm 2A need SYMBOL

+1.8VS

LN15

BLM21PG221SN1D_0805

RN51

1 2

0_0603_5%

1

CN49

2

4.7U_0603_6.3V6K

1

CN57

2

4.7U_0603_6.3V6K

1.1V-1.2V 400mA

1

CN62

2

4.7U_0603_6.3V6K

1

CN77

2

4.7U_0603_6.3V6K

+1.8VS

1.1V 600mA

1

CN50

2

0.1U_0402_16V7K

1.1V 700mA

1

CN58

2

0.1U_0402_16V7K

1

CN63

2

0.1U_0402_16V7K

1.8V 700mA

1

CN78

2

0.1U_0402_16V7K

1.8V 10mA

1.8V 25mA

1

CN87

2

CN51

0.1U_0402_16V7K

CN59

0.1U_0402_16V7K

CN64

0.1U_0402_16V7K

CN79

0.1U_0402_16V7K

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1

CN65

2

0.1U_0402_16V7K

1

CN80

2

0.1U_0402_16V7K

40mil

1

2

60mil

1

2

15mil 15mil

0.1U_0402_16V7K

4

AE25 AD24 AC23 AB22 AA21

AE11 AD11

UN2E

J17

VDDHT_1

K16

VDDHT_2

L16

VDDHT_3

M16

VDDHT_4

P16

VDDHT_5

R16

VDDHT_6

T16

VDDHT_7

H18

VDDHTRX_1

G19

VDDHTRX_2

F20

VDDHTRX_3

E21

VDDHTRX_4

D22

VDDHTRX_5

B23

VDDHTRX_6

A23

VDDHTRX_7 VDDHTTX_1

VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5

Y20

VDDHTTX_6

W19

VDDHTTX_7

V18

VDDHTTX_8

U17

VDDHTTX_9

T17

VDDHTTX_10

R17

VDDHTTX_11

P17

VDDHTTX_12

M17

VDDHTTX_13

J10

VDDA18PCIE_1

P10

VDDA18PCIE_2

K10

VDDA18PCIE_3

M10

VDDA18PCIE_4

L10

VDDA18PCIE_5

W9

VDDA18PCIE_6

H9

VDDA18PCIE_7

T10

VDDA18PCIE_8

R10

VDDA18PCIE_9

Y9

VDDA18PCIE_10

AA9

VDDA18PCIE_11

AB9

VDDA18PCIE_12

AD9

VDDA18PCIE_13

AE9

VDDA18PCIE_14

U10

VDDA18PCIE_15

F9

VDD18_1

G9

VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)

RS880M_FCBGA528

PART 5/6

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12

POWER

VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)

VDD33_1(NC) VDD33_2(NC)

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11 H12

CN60

CN66

20mil

CN82

15mil

CN88

3

100mil

1

CN52

2

0.1U_0402_16V7K

520mil

1

CN67

2

0.1U_0402_16V7K

1

CN83

2

0.1U_0402_16V7K

1

CN89

2

0.1U_0402_16V7K

1

CN53

2

0.1U_0402_16V7K

1

CN68

2

0.1U_0402_16V7K

1

CN81

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1.1V 2.5A

+1.1VS_VDDPCIE

1

CN54

2

1U_0402_6.3V6K

1.1V 12A

1

CN69

2

0.1U_0402_16V7K

1.5V 100mA

1

CN84

2

0.1U_0402_16V7K

+3VS_VDD33NB

3.3V 60mA

1

CN55

2

1U_0402_6.3V6K

1

CN70

2

0.1U_0402_16V7K

1

CN85

2

0.1U_0402_16V7K

1

2

4.7U_0603_6.3V6K

1

CN71

2

0.1U_0402_16V7K

+VDD_MEM

1

2

1 2

LN12

0_1206_5%

1

CN72

2

0.1U_0402_16V7K

RN50

1 2

0_0603_5%

4.7U_0603_6.3V6K

RN52

0_0603_5%

+1.1VS

12

1

CN73

2

0.1U_0402_16V7K

+3VS

2

+NB_CORE

1

CN74

2

10U_0603_6.3V6M

+1.5VS

1

2

10U_0603_6.3V6M

UN2F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS880M_FCBGA528

PART 6/6

GROUND

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

1

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

B B

RS880M POWER TABLE

PIN NAME

VDDHT VDDHTRX VDDHTTX VDDA18PCIE VDD18 VDD18_MEM VDDPCIE VDDC VDD_MEM VDD33

A A

IOPLLVDD18

RS880M

+1.1V +1.1V +1.2V +1.8V +1.8V +1.8V +1.1V +1.1V

+1.5V(1.8V)

+3.3V +1.8V

PIN NAME

IOPLLVDD AVDD AVDDDI AVDDQ PLLVDD PLLVDD18 VDDA18PCIEPLL VDDA18HTPLL VDDLTP18 VDDLT18 VDDLT33

RS880M

+1.1V +3.3V +1.8V +1.8V +1.1V +1.8V +1.8V +1.8V +1.8V +1.8V NC

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

RS880M Power/GND

LA-6132P

15 45Monday, May 03, 2010

1

1.0

5

CS1

1 2

150P_0402_50V8J~D

A_RST#

CS2 0.1U_0402_16V7KCS2 0.1U_0402_16V7K

PCIE_NRX_STX_P0<12> PCIE_NRX_STX_N0<12> PCIE_NRX_STX_P1<12> PCIE_NRX_STX_N1<12> PCIE_NRX_STX_P2<12> PCIE_NRX_STX_N2<12> PCIE_NRX_STX_P3<12>

D D

it can be swap if need

AMD

SB_GPIO_PCIE_RST#<18>

C C

B B

A A

SB_GPIO_PCIE_RST#

A_RST#

CLK_NB_REFCLK_P<13> CLK_NB_REFCLK_N<13>

CLK_HTREFCLK_P<13> CLK_HTREFCLK_N<13>

CLK_PCIE_LAN_P<20> CLK_PCIE_LAN_N<20>

CLK_PCIE_WLAN_P<28> CLK_PCIE_WLAN_N<28>

CLK_PCIE_WWAN_P<28> CLK_PCIE_WWAN_N<28>

PCIE_NRX_STX_N3<12>

PCIE_NTX_SRX_P0<12> PCIE_NTX_SRX_N0<12> PCIE_NTX_SRX_P1<12> PCIE_NTX_SRX_N1<12> PCIE_NTX_SRX_P2<12> PCIE_NTX_SRX_N2<12> PCIE_NTX_SRX_P3<12> PCIE_NTX_SRX_N3<12>

CS11

0.1U_0402_16V7K

12

RS5

@

100K_0402_5%

CLK_SB_CLK_P<13> CLK_SB_CLK_N<13>

CLK_HT_CPU_P<8> CLK_HT_CPU_N<8>

Place close to US3

RF reserved

12

2 1

RS6 0_0402_5%

CS13 10P_0402_50V8J~D@CS13 10P_0402_50V8J~D@

CLK_48M<21>

+PCIE_VDDR

+3VALW

B A

CLK_SB_CLK_P CLK_SB_CLK_N

CLK_NB_REFCLK_P CLK_NB_REFCLK_P_R CLK_NB_REFCLK_N

CLK_HTREFCLK_P CLK_HTREFCLK_N

CLK_HT_CPU_P CLK_HT_CPU_N

CLK_PCIE_LAN_P CLK_PCIE_LAN_N

CLK_PCIE_WLAN_P CLK_PCIE_WLAN_N

CLK_PCIE_WWAN_N CLK_PCIE_WWAN_N_R

12

1 2

CS3 0.1U_0402_16V7KCS3 0.1U_0402_16V7K

1 2

CS4 0.1U_0402_16V7KCS4 0.1U_0402_16V7K

1 2

CS5 0.1U_0402_16V7KCS5 0.1U_0402_16V7K

1 2

CS6 0.1U_0402_16V7KCS6 0.1U_0402_16V7K

1 2

CS8 0.1U_0402_16V7KCS8 0.1U_0402_16V7K

1 2

CS9 0.1U_0402_16V7KCS9 0.1U_0402_16V7K

1 2

CS10 0.1U_0402_16V7KCS10 0.1U_0402_16V7K

1 2

RS1 590_0402_1%RS1 590_0402_1% RS4 2K_0402_1%~DRS4 2K_0402_1%~D

5

US8

P

PLT_RST#

4

Y

G

NC7SZ08P5X_NL_SC70-5

3

12

@

RS9 0_0402_5%RS9 0_0402_5%

1 2

RS10 0_0402_5%RS10 0_0402_5%

1 2

RS94 0_0402_5%RS94 0_0402_5%

1 2

RS95 0_0402_5%RS95 0_0402_5%

1 2

RS13 0_0402_5%RS13 0_0402_5%

1 2

RS14 0_0402_5%RS14 0_0402_5%

1 2

RS15 0_0402_5%RS15 0_0402_5%

1 2

RS16 0_0402_5%RS16 0_0402_5%

1 2

RS18 0_0402_5%RS18 0_0402_5%

1 2

RS19 0_0402_5%RS19 0_0402_5%

1 2

RS20 0_0402_5%RS20 0_0402_5%

1 2

RS21 0_0402_5%RS21 0_0402_5%

1 2

RS22 0_0402_5%RS22 0_0402_5%

1 2

RS23 0_0402_5%RS23 0_0402_5%

1 2

12P_0402_50V8J

25MHz_12P_X5H025000FC1H-H

12P_0402_50V8J

CS16

CS17

4

RS2

33_0402_5%~D

12

12 12

PLT_RST# <13,20,26,28>

RS7

33_0402_5%~D

12

YS2

1 2

12

A_RST#_R

PCIE_NRX_STX_P0_C PCIE_NRX_STX_N0_C PCIE_NRX_STX_P1_C PCIE_NRX_STX_N1_C PCIE_NRX_STX_P2_C PCIE_NRX_STX_N2_C PCIE_NRX_STX_P3_C PCIE_NRX_STX_N3_C

PCIE_NTX_SRX_P0 PCIE_NTX_SRX_N0 PCIE_NTX_SRX_P1 PCIE_NTX_SRX_N1 PCIE_NTX_SRX_P2 PCIE_NTX_SRX_N2 PCIE_NTX_SRX_P3 PCIE_NTX_SRX_N3

PCIE_CAL_P PCIE_CAL_N

CLK_SB_CLK_P_R CLK_SB_CLK_N_R

CLK_NB_REFCLK_N_R CLK_HTREFCLK_P_R

CLK_HTREFCLK_N_R CLK_HT_CPU_P_R

CLK_HT_CPU_N_R

CLK_PCIE_LAN_P_R CLK_PCIE_LAN_N_R

CLK_PCIE_WLAN_P_R CLK_PCIE_WLAN_N_R

CLK_PCIE_WWAN_P_RCLK_PCIE_WWAN_P

CLK_48M_RCLK_48M

SB25M_X1

12

RS27

RS27 1M_0402_5%~D

1M_0402_5%~D

SB25M_X2

US3A

P1

PCIE_RST#

L1

A_RST#

AD26

A_TX0P

AD27

A_TX0N

AC28

A_TX1P

AC29

A_TX1N

AB29

A_TX2P

AB28

A_TX2N

AB26

A_TX3P

AB27

A_TX3N

AE24

A_RX0P

AE23

A_RX0N

AD25

A_RX1P

AD24

A_RX1N

AC24

A_RX2P

AC25

A_RX2N

AB25

A_RX3P

AB24

A_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

SB820M_FCBGA605~D

3

Part 1 of 5

SB820M

Part 1 of 5

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI EXPRESS INTERFACES

PCI INTERFACELPC

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

LDRQ1#/CLK_REQ6#/GPIO49

CLOCK GENERATOR

ALLOW_LDTSTP/DMA_ACTIVE#

CPU

INTRUDER_ALERT#

RTC

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

STOP# PERR# SERR# REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44 GNT2#/GPO45

CLKRUN#

LOCK#

INTE#/GPIO32

INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

PROCHOT#

LDT_PG

LDT_STP#

LDT_RST#

32K_X1 32K_X2

RTCCLK

VDDBT_RTC_G

W2

PCICLK1

W1

PCICLK2

W3

PCICLK3

W4

PCICLK4

Y1

PCIRST#

V2

AA1 AA4

SB_GPIO2_R

AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2

PCI_AD23

AE9

PCI_AD24

AD9

PCI_AD25

AC11

PCI_AD26

AF6

PCI_AD27

AF4

PCI_AD28

AF3

PCI_AD29

AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5

PAR

AF5 AE6 AE4 AE11 AH5 AH4

PCI_ROM_DAT

AC12 AD12 AJ5 AH6

PCI_ROM_CLK

AB12

EC_CLKRUN#

AB11

LOCK#

AD7 AJ6

GPIO33

AG6 AG4

PCI_PIRQH#

AJ4

CLK_PCI_ECLPC_CLK0_R CLK_PCI_EC

H24

CLK_DEBUG_PORT

H25

LPC_AD0

J27

LPC_AD1

J26

LPC_AD2

H29

LPC_AD3

H28

LPC_FRAME#

G28

LDRQ0#

J25

LDRQ1#

AA18

IRQ_SERIRQ

AB19

ALLOW_LDTSTOP

G21 H21 K19 G22

LDT_RST#

J24

SB_32KHI

C1

SB_32KH0

C2

RTC_CLK

D2 B2

+VBAT_IN

B1

1

CS18

2

@

0.1U_0402_16V7K

PCICLK1 <17> PCICLK2 <17> PCICLK3 <17> PCICLK4 <17>

RS3 33_0402_5%~DRS3 33_0402_5%~D

1 2

PCI_AD23 <17> PCI_AD24 <17> PCI_AD25 <17> PCI_AD26 <17> PCI_AD27 <17> PCI_AD28 <17> PCI_AD29 <17>

TS10TS10

TS11TS11 TS1TS1

RS100 20K_0402_5%RS100 20K_0402_5%

1 2

TS2TS2

RS24

1 2

LPC_LAD0 <26,28> LPC_LAD1 <26,28> LPC_LAD2 <26,28> LPC_LAD3 <26,28>

LPC_LFRAME# <26,28>

TS3TS3 TS4TS4

IRQ_SERIRQ <26>

ALLOW_LDTSTOP <13> CPU_PROCHOT# <8> CPU_PWRGD <8> LDT_STOP# <8,13> LDT_RST# <8>

RS26 10K_0402_5%@RS26 10K_0402_5%@

1 2

RS105 510_0402_1%RS105 510_0402_1%

1

CS19

2

1U_0402_6.3V6K

2

PCI_RST#

1

CS7

CS7 150P_0402_50V8J~D

150P_0402_50V8J~D

2

PCI_AD27 SB_GPIO27# PCI_AD26 SB_GPIO26#

PCI_AD29 SB_MEMHOT#

EC_CLKRUN# <26>

22_0402_5%~D

PCI_RST#

1 2

RS108 0_0402_5%RS108 0_0402_5%

1 2

RS109 0_0402_5%RS109 0_0402_5%

1 2

RS110 0_0402_5%RS110 0_0402_5%

1 2

RS99 0_0402_5%RS99 0_0402_5%

18P_0402_50V8J

20M_0402_5%~D

18P_0402_50V8J

RS113 0_0402_5%

CLK_PCI_EC <17,26>

For Compal LPC debug card

Place close to US3

+RTC_CELL

1

PJP1

1

JUMP_43X39@

2

RTC RESET

2

CS14

12

RS17

12

CS15

1 2

@

CLK_PCI_EC

SB_GPIO2#SB_GPIO2_R

SB_32KHI

12

SB_32KH0

CLK_DEBUG_PORT <17>

CLK_DEBUG_PORT_1CLK_DEBUG_PORT

CS12 10P_0402_50V8J~D@CS12 10P_0402_50V8J~D@

1

SB_GPIO27# <20> SB_GPIO26# <28> SB_GPIO2# <28>

SB_MEMHOT# <7>

YS1

4

OUT

1

IN

32.768KHZ_12.5PF_1TJS125BJ4A421P

need check foot print and replace to SJ100003P00

1 2

NB GPP PORT 0 LAN

NB GPP PORT 1 WLAN

NB GPP PORT 2 WWAN

3

NC

2

NC

CLK_DEBUG_PORT_1 <28>

EMI reserved

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

SB820M PCIE/PCI/LPC/CKG/RTC

LA-6132P

16 45Tuesday, May 04, 2010

1

of

1.0

5

4

3

PULL HIGH

SB_HD _SDOUT

LOW POWER MODE

PCICLK1

ALLOW PCIE Gen2

DEFAULT

PCICLK2

Watchdog Timer Enabled

2

PCICLK3 PCICLK4

USE DEBUG STRAP

non_Fusion CLOCK MODE

DEFAULT

CLK_PCI_EC

EC ENABLED

CLK_DEBUG _PORT

CLKGEN ENABLED

DEFAULT

1

GPIO200

H,H = Reserved H,L = SPI ROM

GPIO199

L,H = LPC ROM (Default)

PERFORMANCE

PULL

MODE

D D

SATA HDD

+3VS

12

RS111

RS111 10K_0402_5%

10K_0402_5%

12 12

1 2

12

RS54

10K_0402_5%

SATA_STX_DRX_P0_C SATA_STX_DRX_N0_C

SATA_SRX_DTX_N0 SATA_SRX_DTX_P0

SATA_CALP SATA_CALN

SATA_ACT#_R

SATA_X1

12

RS50

@RS50

@

1M_0402_5%~D

SATA_X2

SB_SI_SPI_SO SB_SO_SPI_SI SB_SPI_CLK SB_SPI_CS#

12

RS55

RS55 10K_0402_5%

10K_0402_5%

12

RS60

2.2K_0402_5%

@

CS20 0.01U_0402_16V7KCS20 0.01U_0402_16V7K

SATA_STX_DRX_P0<29> SATA_STX_DRX_N0<29>

SATA_SRX_DTX_N0<29> SATA_SRX_DTX_P0<29>

C C

+AVDD_SATA

25MHz_12P_X5H025000FC1H-H

B B

DEBUG STRAPS

PCI_AD29<16> PCI_AD28<16> PCI_AD27<16> PCI_AD26<16> PCI_AD25<16> PCI_AD24<16> PCI_AD23<16>

A A

1 2

CS21 0.01U_0402_16V7KCS21 0.01U_0402_16V7K

1 2

SATA_ACT#_R

RS47 1K_0402_1%~DRS47 1K_0402_1%~D RS48 931_0402_1%RS48 931_0402_1%

SATA_ACT#_R<25>

@ CS24

@

22P_0402_50V8J

@ CS25

@

22P_0402_50V8J

12

RS53

10K_0402_5%

PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

CS24

12

@ YS3

@

CS25

12

YS3

AH9

AJ9 AJ8

AH8

AH10

AJ10

AG10 AF10

AG12 AF12

AJ12

AH12 AH14

AJ14

AG14 AF14

AG17 AF17

AJ17

AH17

AJ18

AH18 AH19

AJ19

AB14 AA14

AD11

AD16

AC16

J5 E2 K4 K9

G2

12

RS56

RS56 10K_0402_5%

10K_0402_5%

12

RS61

2.2K_0402_5%

@

US3B

SATA_TX0P SATA_TX0N

SATA_RX0N SATA_RX0P

SATA_TX1P SATA_TX1N

SATA_RX1N SATA_RX1P

SATA_TX2P SATA_TX2N

SATA_RX2N SATA_RX2P

SATA_TX3P SATA_TX3N

SATA_RX3N SATA_RX3P

SATA_TX4P SATA_TX4N

SATA_RX4N SATA_RX4P

SATA_TX5P SATA_TX5N

SATA_RX5N SATA_RX5P

SATA_CALRP SATA_CALRN

SATA_ACT#/GPIO67

SATA_X1

SATA_X2

SPI_DI/GPIO164 SPI_DO/GPIO163 SPI_CLK/GPIO162 SPI_CS1#/GPIO165 ROM_RST#/GPIO161

SB820M_FCBGA605~D

12

RS57

RS57 10K_0402_5%

10K_0402_5%

12

RS62

2.2K_0402_5%

@

SB820M

Part 2 of 5

SERIAL ATA

HW MONITOR

SPI ROM

12

RS58

RS58 10K_0402_5%

10K_0402_5%

12

RS63

2.2K_0402_5%

@

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FC_OE#/GPIOD145

FC_AVD#/GPIOD146

FC_WE#/GPIOD148 FC_CE1#/GPIOD149 FC_CE2#/GPIOD150

FC_INT1/GPIOD144

FC_INT2/GPIOD147 FC_ADQ0/GPIOD128

FC_ADQ1/GPIOD129 FC_ADQ2/GPIOD130 FC_ADQ3/GPIOD131 FC_ADQ4/GPIOD132 FC_ADQ5/GPIOD133 FC_ADQ6/GPIOD134 FC_ADQ7/GPIOD135 FC_ADQ8/GPIOD136 FC_ADQ9/GPIOD137

FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142

FLASH

FC_ADQ15/GPIOD143

FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173

TEMPIN3/TALERT#/GPIO174

TEMP_COMM

VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

+3VS+3VS+3VS+3VS+3VS +3VS+3VS

12

RS59

RS59 10K_0402_5%

10K_0402_5%

12

RS64

2.2K_0402_5%

@

AH28 AG28 AF26

AF28 AG29 AG26 AF27 AE29 AF29 AH27

AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26

W5 W6

SB_PROCHOT#_R

Y9 W7

V9 W8

B6 A6 A5 B5

TEMP_COMM

C7 A3

Connect C7 and D8, then go to GND directly.

B4 A4 C5 A7

LOM_POWER EN_WOL#

B7 B8 A8

G27

NC1

Y2

NC2

SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

5

4

LOW

DEFAULT

SB_HD_SDOUT<18> PCICLK1<16> PCICLK2<16> PCICLK3<16> PCICLK4<16> CLK_PCI_EC<16,26>

CLK_DEBUG_PORT<16>

GP199<18> GP200<18>

RS103 0_0402_5%RS103 0_0402_5%

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+VDDIO_AZ

12

RS29

RS29 10K_0402_5%

10K_0402_5%

@

12

RS38

RS38 10K_0402_5%

10K_0402_5%

FORCE PCIE Gen1

Watchdog Timer Disabled

DEFAULT

IGNORE DEBUG STRAP

DEFAULT

FUSION CLOCK MODE

REQUIRED STRAPS

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW

CS26

1 2

SB_PROCHOT#_R

RS51

@

PULL HIGH

PULL LOW

2

12

RS32

RS32 10K_0402_5%

10K_0402_5%

@

12

RS41

RS41 10K_0402_5%

10K_0402_5%

RS52

@

1 2

10K_0402_5%

SPI_HOLD# SB_SPI_CS# SB_SPI_CLK SB_SO_SPI_SI SB_SI_SPI_SO

PCI_AD27 PCI_AD26

USE PCI PLL

DEFAULT

BYPASS PCI PLL

12

RS30

RS30 10K_0402_5%

10K_0402_5%

12

RS39

RS39 10K_0402_5%

10K_0402_5%

@

EN_WOL# <26,30>

0.1U_0402_16V7K

12

RS31

RS31 10K_0402_5%

10K_0402_5%

@

12

RS40

RS40 10K_0402_5%

10K_0402_5%

@

EC DISABLED

DEFAULT

12

RS33

RS33 10K_0402_5%

10K_0402_5%

12

RS42

RS42 10K_0402_5%

10K_0402_5%

@

+3VS

12

10K_0402_5%

RS101

RS102

2

QS1

3 1

MMBT3904_NL_SOT23-3

+3VALW

20mils

8 3 7 1 6 5

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

CLKGEN DISABLED

12

RS34

RS34 10K_0402_5%

10K_0402_5%

@

12

RS43

RS43 10K_0402_5%

10K_0402_5%

SB_PROCHOT# <8>

US9

VCC W HOLD S C D

MX25L8005M2C-15G_SO8

@

VSS

4

2

Q

PCI_AD25 PCI_AD24

USE FC PLL

DEFAULT

BYPASS FC PLL

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

L,L = FWH ROM

12

RS35

RS35 10K_0402_5%

10K_0402_5%

12

RS44

RS44 10K_0402_5%

10K_0402_5%

@

12

RS36

RS36 10K_0402_5%

10K_0402_5%

12

RS45

2.2K_0402_5%

@

check list: LCP ROM: GP199=NC, GP200=PD Datasheet: LCP ROM: GP199=PU, GP200=PD

12

RS37

RS37 10K_0402_5%

10K_0402_5%

@

12

RS46

2.2K_0402_5%

PCI_AD23

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

Compal Electronics, Inc.

SB820M SATA/FLASH/Strap

LA-6132P

DISABLE PCI MEM BOOT

DEFAULT

ENABLE PCI MEM BOOT

1

17 45Tuesday, May 04, 2010

1.0

of

5

4

3

2

1

SSIC circuit for EMI

+3VS_SSIC+3VS

NONWWAN@

1 2

RS117 0_0402_5%

SSEXTR

12

RS115

HDA_BITCLK

RS115

2.2K_0402_5%

NONWWAN@

US10

NONWWAN@US10

NONWWAN@

1

CLKIN

2

RESERVED

3

NC

4

GND

P3P8211

NONWWAN@

1 2

RS119 33_0402_5%~D

D D

Use PCS3P73Z21BWG footprint for layout first It modify pinout for ECS2P8211

C C

HDA_BITCLK

HDA_BITCLK_SSIC

Bypass Schematics

+3VS_SSIC

8

VDD

7

SSEXTR

6

RESERVED

5

MODOUT

12

CS22 8.2P_0402_50V8D~D

NONWWAN@

Place CS22 closed to US10

HDA_BITCLK_SSICHDA_BITCLK_SSIC_R

Place CS80 close to US3

RS68 33_0402_5%~DRS68 33_0402_5%~D

HDA_SDOUT<25>

SB_HD_SDOUT<17>

RS71 10K_0402_5%@RS71 10K_0402_5%@

1 2

RS72 10K_0402_5%@RS72 10K_0402_5%@

B B

A A

1 2

RS73 10K_0402_5%@RS73 10K_0402_5%@

1 2

RS98 10K_0402_5%RS98 10K_0402_5%

1 2

RS106 10K_0402_5%RS106 10K_0402_5%

1 2

RS107 10K_0402_5%RS107 10K_0402_5%

1 2

+3VALW

RS81 10K_0402_5%RS81 10K_0402_5%

1 2

RS82 10K_0402_5%RS82 10K_0402_5%

1 2

RS83 10K_0402_5%RS83 10K_0402_5%

1 2

RS85 10K_0402_5%RS85 10K_0402_5%

1 2

GbE Controller Disabled

RS77 10K_0402_5%RS77 10K_0402_5%

1 2

RS78 10K_0402_5%RS78 10K_0402_5%

1 2

RS74 10K_0402_5%RS74 10K_0402_5%

1 2

RS75 10K_0402_5%RS75 10K_0402_5%

1 2

RS76 10K_0402_5%RS76 10K_0402_5%

1 2

SB_HD_SDOUT

SB_SPKR SB_HD_BITCLK SB_HD_SDIN0

SB_HD_SDIN1 SB_HD_SDIN2 SB_HD_SDIN3

SB_SMB_CLK1 SB_SMB_DAT1 SB_SMB_CLK2 SB_SMB_DAT2

GBE_MDIO GBE_PHY_INTR GBE_COL GBE_CRS GBE_RXERR

5

WWAN@

1 2

RS112 0_0402_5%

NONWWAN@

CS81

0.1U_0402_16V7K

1 2

CS82

0.01U_0402_16V7K

1 2

SSEXTR

HDA_BITCLK_SSIC_R

HDA_BITCLK_SSIC <25>

MEM_SMBCLK<10,11,13>

MEM_SMBDATA<10,11,13>

NONWWAN@CS82

NONWWAN@

MEM_SMBCLK MEM_SMBDATA

RF reserved

+3VS

@

CS80 27P_0402_50V8J

HDA_BITCLK

RS79 10K_0402_5%@RS79 10K_0402_5%@

1 2

RS80 4.7K_0402_5%RS80 4.7K_0402_5%

1 2

RS84 2.2K_0402_5%RS84 2.2K_0402_5%

1 2

RS86 2.2K_0402_5%RS86 2.2K_0402_5%

1 2

CPU_MEMHOT#<7>

Need confirm with BIOS team

sideport

RS25 22_0402_5%~DRS25 22_0402_5%~D

1 2

RS28 22_0402_5%~DRS28 22_0402_5%~D

1 2

SMB_ALERT#<8,13,26> EC_LID_OUT#<26>

12

HDA_SDIN0<25>

HDA_SYNC<25> HDA_RST#<25>

RS104 0_0402_5%RS104 0_0402_5%

SB_GPIO_PCIE_RST#<16>

SP_DDR3_RST#<14>

RS67 33_0402_5%~DRS67 33_0402_5%~D RS96 33_0402_5%~DRS96 33_0402_5%~D

RS69 33_0402_5%~DRS69 33_0402_5%~D RS70 33_0402_5%~DRS70 33_0402_5%~D

SB_SHUTDOWN# SUS_STAT#

MEM_SMBCLK MEM_SMBDATA

ACIN<26,34>

4

1 2

SB_RI#<26>

SIO_SLP_S3#<26>

SIO_SLP_S5#<26> PBTN_OUT#<26> SB_PWRGD<8,13,26>

SUS_STAT#<13>

GATEA20<26> KB_RST#<26> SIO_EXT_SCI#<26> SIO_EXT_SMI#<26>

PCIE_WAKE#<20,26,28> H_THERMTRIP#<8>

NB_PWRGD_SB<13> EC_RSMRST#<26>

CLKREQ_LAN#<20>

SB_SPKR<25>

CLKREQ_WWAN#<28> CLKREQ_WLAN#<28>

USB_OC2#<23> USB_OC1#<23> USB_OC0#<23>

1 2 1 2

ACIN

MEM_SMBCLK_R MEM_SMBDATA_R

1 2

2

G

TS5TS5 TS6TS6 TS7TS7

AMD

TS12TS12

AMD

RS660_0402_5% RS660_0402_5%

AMD

TS13TS13

TS8TS8 TS9TS9

13

D

SSM3K7002FU_SC70-3

S

CPU_MEMHOT#_R

SB_RI# SIO_SLP_S3#

SIO_SLP_S5# PBTN_OUT# SB_PWRGD SUS_STAT# SB_TEST0 SB_TEST1 SB_TEST2 GATEA20 KB_RST# SIO_EXT_SCI# SIO_EXT_SMI#

COLD_RST_TP PCIE_WAKE#

H_THERMTRIP# NB_PWRGD_SB

EC_RSMRST#

SB_GPIO_PCIE_RST#

CLKREQ_LAN#

SB_SPKR MEM_SMBCLK_R MEM_SMBDATA_R

SB_SMB_CLK1

SB_SMB_DAT1

CLKREQ_WWAN# CLKREQ_WLAN#

SB_SHUTDOWN#

SP_DDR3_RST#

SMB_ALERT#_R

EC_LID_OUT#

USB_OC3#

USB_OC2#

USB_OC1#

USB_OC0#

SB_HD_BITCLK

SB_HD_SDOUT

SB_HD_SDIN0

SB_HD_SDIN1

SB_HD_SDIN2

SB_HD_SDIN3

SB_HD_SYNC

SB_HD_RST#

GBE_COL

GBE_CRS

GBE_MDIO

GBE_RXERR

GBE_PHY_INTR

PS2_DAT

PS2_CLK

AC_OK#

QS2

US3D

J2

PCI_PME#/GEVENT4#

K1

RI#/GEVENT22#

D3

SPI_CS3#/GBE_STAT1/GEVENT21#

F1

SLP_S3#

H1

SLP_S5#

F2

PWR_BTN#

H5

PWR_GOOD

G6

SUS_STAT#

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0#

AE21

KBRST#/GEVENT1#

K2

LPC_PME#/GEVENT3#

J29

LPC_SMI#/GEVENT23#

H2

GEVENT5#

J1

SYS_RESET#/GEVENT19#

H6

WAKE#/GEVENT8#

F3

IR_RX1/GEVENT20#

J6

THRMTRIP#/SMBALERT#/GEVENT2#

AC19

NB_PWRGD

G1

RSMRST#

AD19

CLK_REQ4#/SATA_IS0#/GPIO64

AA16

CLK_REQ3#/SATA_IS1#/GPIO63

AB21

SMARTVOLT1/SATA_IS2#/GPIO50

AC18

CLK_REQ0#/SATA_IS3#/GPIO60

AF20

SATA_IS4#/FANOUT3/GPIO55

AE19

SATA_IS5#/FANIN3/GPIO59

AF19

SPKR/GPIO66

AD22

SCL0/GPIO43

AE22

SDA0/GPIO47

F5

SCL1/GPIO227

F4

SDA1/GPIO228

AH21

CLK_REQ2#/FANIN4/GPIO62

AB18

CLK_REQ1#/FANOUT4/GPIO61

E1

IR_LED#/LLB#/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN#/GPIO51

H4

DDR3_RST#/GEVENT7#

D5

GBE_LED0/GPIO183

D7

GBE_LED1/GEVENT9#

G5

GBE_LED2/GEVENT10#

K3

GBE_STAT0/GEVENT11#

AA20

CLK_REQG#/GPIO65/OSCIN/IDLEEXT#

H3

BLINK/USB_OC7#/GEVENT18#

D1

USB_OC6#/IR_TX1/GEVENT6#

E4

USB_OC5#/IR_TX0/GEVENT17#

D4

USB_OC4#/IR_RX0/GEVENT16#

E8

USB_OC3#/AC_PRES/TDO/GEVENT15#

F7

USB_OC2#/TCK/GEVENT14#

E7

USB_OC1#/TDI/GEVENT13#

F8

USB_OC0#/TRST#/GEVENT12#

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GPIO167

M2

AZ_SDIN1/GPIO168

M1

AZ_SDIN2/GPIO169

M4

AZ_SDIN3/GPIO170

N2

AZ_SYNC

P2

AZ_RST#

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST#

V7

GBE_PHY_INTR

E23

PS2_DAT/SDA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2#/GBE_STAT2/GPIO166

G29

FC_RST#/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

SB820M_FCBGA605~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

SB820M

Part 4 of 5

GBE LAN

HD AUDIO

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

GPIO

USB OC

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200

EMBEDDED CTRL

USB_RCOMP

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB_HSD13P USB_HSD13N

USB 1.1USB MISCEMBEDDED CTRL

USB_HSD12P USB_HSD12N

USB_HSD11P

USB_HSD11N USB_HSD10P

USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB 2.0

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217

KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226

USB_FSD1N

USB_FSD0N

A10 G19

J10 H11

H9 J8

B12 A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

D25 F23 B26 E26 F25 E22 F22 E21

G24 G25 E28 E29 D29 D28 C29 C28

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

USB_RCOMP

SB_SMB_CLK2 SB_SMB_DAT2 SB_SMB_CLK3 SB_SMB_DAT3

2

1 2

USB20_P9 <27> USB20_N9 <27>

USB20_P8 <21> USB20_N8 <21>

USB20_P6 <28> USB20_N6 <28>

USB20_P5 <28> USB20_N5 <28>

USB20_P4 <28> USB20_N4 <28>

USB20_P2 <23> USB20_N2 <23>

USB20_P1 <23> USB20_N1 <23>

USB20_P0 <25> USB20_N0 <25>

SB_SMB_CLK3 <8>

SB_SMB_DAT3 <8>

GP199 <17> GP200 <17>

RS6511.8K_0402_1%~D RS6511.8K_0402_1%~D

Camera

Card Reader (Sub-board)

Bluetooth

MiniCard- WWAN (Sub-board)

MiniCard- WLAN

USB Port 2

USB Port 1 (Sub-board)

USB Port 0 (Sub-board)

Low Voltage SMBUS for CPU TSI

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

SB820M USB/ACPI/AZ/GPIO

LA-6132P

18 45Tuesday, May 11, 2010

1

of

1.0

5

+3VS

RS87

1 2

0_0603_5%

D D

+1.1VS

LS2

1 2

FBMJ2125HS420-T_2P_0805

New PART FBMJ2125HS420-T 42 ohm 4A

+1.1VS

C C

FBMJ2125HS420-T_2P_0805

New PART FBMJ2125HS420-T 42 ohm 4A

0805/220Ohm/2000mA MPN:BLM21PG221SN1D CPN:SM010026280 220 ohm 2A need SYMBOL

B B

A A

LS3

1 2

+3VALW +3VALW_AVDDUSB

LS4

1 2

BLM21PG221SN1D_0805

+3VS

BLM18EG221SN1D_2P_0603

+3VS

BLM18EG221SN1D_2P_0603

CS38

+PCIE_VDDR

1

CS41

2

+AVDD_SATA

1

CS46

2

1

CS54

2

LS7

1 2

LS10

1 2

1

CS27

2

22U_0805_6.3V6M~D

1

CS42

CS43

@

2

1U_0402_6.3V6K

22U_0805_6.3V6M~D

1

CS47

CS48

2

1U_0402_6.3V6K

22U_0805_6.3V6M~D

1

CS56

CS55

2

10U_0603_6.3V6M

1

CS65

CS64

2

@

2.2U_0402_6.3V6M~D

1

CS73

CS72

2

@

2.2U_0402_6.3V6M~D

1

CS29

CS28

2

0.1U_0402_16V7K

1

CS44

2

1U_0402_6.3V6K

1

CS49

2

1U_0402_6.3V6K

1

CS57

2

1U_0402_6.3V6K

3.3V 11mA

+3VS_VDDPL_PCIE

1

2

0.1U_0402_16V7K

+3VS_VDDPL_SATA

1

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1.1V 690mA

1

CS45

2

0.1U_0402_16V7K

1

CS50

2

0.1U_0402_16V7K

1

2

1U_0402_6.3V6K

+1.1VALW

BLM18EG221SN1D_2P_0603

3.3V 15mA

1

2

0.1U_0402_16V7K

1.1V 1.35A

1

2

0.1U_0402_16V7K

3.3V 534mA

LS5

1 2

RS89

1 2

0_0603_5%

Not use Flash I/O

+1.1VALW_VDDAN_USB

CS60

0.15mA

+VDDIO_18_FC

+3VS_VDDPL_PCIE

+3VS_VDDPL_SATA

+3VALW_AVDDUSB

1.1V 88mA

1

CS61

2

2.2U_0402_6.3V6M~D

4

1

2

0.1U_0402_16V7K

US3C

AH1

VDDIO_33_PCIGP_1

V6

VDDIO_33_PCIGP_2

Y19

VDDIO_33_PCIGP_3

AE5

VDDIO_33_PCIGP_4

AC21

VDDIO_33_PCIGP_5

AA2

VDDIO_33_PCIGP_6

AB4

VDDIO_33_PCIGP_7

AC8

VDDIO_33_PCIGP_8

AA7

VDDIO_33_PCIGP_9

AA9

VDDIO_33_PCIGP_10

AF7

VDDIO_33_PCIGP_11

AA19

VDDIO_33_PCIGP_12

AF22

VDDIO_18_FC_1

AE25

VDDIO_18_FC_2

AF24

VDDIO_18_FC_3

AC22

VDDIO_18_FC_4

POWER

AE28

VDDPL_33_PCIE

U26

VDDAN_11_PCIE_1

V22

VDDAN_11_PCIE_2

V26

VDDAN_11_PCIE_3

V27

VDDAN_11_PCIE_4

V28

VDDAN_11_PCIE_5

V29

VDDAN_11_PCIE_6

W22

VDDAN_11_PCIE_7

W26

VDDAN_11_PCIE_8

AD14

VDDPL_33_SATA

AJ20

VDDAN_11_SATA_1

AF18

VDDAN_11_SATA_4

AH20

VDDAN_11_SATA_2

AG19

VDDAN_11_SATA_3

AE18

VDDAN_11_SATA_5

AD18

VDDAN_11_SATA_6

AE16

VDDAN_11_SATA_7

A18

VDDAN_33_USB_S_1

A19

VDDAN_33_USB_S_2

A20

VDDAN_33_USB_S_3

B18

VDDAN_33_USB_S_4

B19

VDDAN_33_USB_S_5

B20

VDDAN_33_USB_S_6

C18

VDDAN_33_USB_S_7

C20

VDDAN_33_USB_S_8

D18

VDDAN_33_USB_S_9

D19

VDDAN_33_USB_S_10

D20

VDDAN_33_USB_S_11

E19

VDDAN_33_USB_S_12

C11

VDDAN_11_USB_S_1

D11

VDDAN_11_USB_S_2

SB820M_FCBGA605~D

+3VALW_PLL_USB+3VALW_AVDDUSB

RS97

1 2

0_0603_5%

CS66

+1.1VALW_VDDCR_USB

CS74

SB820M

1

CS67

2

2.2U_0402_6.3V6M~D

1

CS75

2

0.1U_0402_16V7K

Part 3 of 5

PCI/GPIO I/O

FLASH I/O

VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2

GBE LAN

PCI EXPRESSSERIAL ATA

CORE S5

VDDCR_11_USB_S_1 VDDCR_11_USB_S_2

USB I/O

PLL CLKGEN I/O

+3VALW_PLL_USB+3VALW_AVDDUSB

1

2

0.1U_0402_16V7K

1

CS76

2

0.1U_0402_16V7K

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8

CORE S03.3V_S5 I/O

VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDRF_GBE_S

VDDIO_33_GBE_S

VDDIO_GBE_S_1 VDDIO_GBE_S_2

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDCR_11_S_1 VDDCR_11_S_2

VDDIO_AZ_S

VDDPL_33_SYS VDDPL_11_SYS_S VDDPL_33_USB_S

VDDAN_33_HWM_S

VDDXL_33_S

LS11

1 2

BLM18EG221SN1D_2P_0603

1

2

10U_0603_6.3V6M

3

+1.1VS_VDD_SB+3VS_VDDIO_SB

N13 R15 N17 U13 U17 V12 V18 W12 W18

+1.1VS_CKVDD

K28 K29 J28 K26 J21 J20 K21 J22

V1

2mA

M10

L7

82mA

L9

M6 P8

21mA

+3VALW_SB

A21 D21 B21 K10 L10 J9 T6 T8

+1.1VALW_SB

F26 G26

+VDDIO_AZ

M8

+1.1VALW_VDDCR_USB

A11 B11

1.1V 58mA

+3VS_VDDPL

M21

+1.1VALW_VDDPL

L22

+3VALW_PLL_USB

F19

+3VALW_HWM

D6

+3VALW_VDDXL

L20

+1.1VALW

1

CS30

CS31

2

0.1U_0402_16V7K

1

CS34

CS35

2

0.1U_0402_16V7K

Not use GBE LAN

1

CS51

CS52

2

@

0.1U_0402_16V7K

+VDDIO_AZ

3.3V 46mA

1.1V 65mA

3.3V 16mA

3.3V 12mA

3.3V 5mA

1

CS32

2

0.1U_0402_16V7K

1.1V 382mA

1

CS40

2

0.1U_0402_16V7K

+3VALW_SB

1

CS53

2

2.2U_0402_6.3V6M~D

1.1V 115mA

3.3V 15mA

1

CS62

2

@

+3VS_VDDPL

1

CS68

CS69

2

@

0.1U_0402_16V7K

+1.1VALW_VDDPL

1

CS78

CS77

2

@

0.1U_0402_16V7K

1.1V 790mA3.3V 78mA

1

CS39

CS33

2

1U_0402_6.3V6K

1

CS36

CS37

2

1U_0402_6.3V6K

3.3V 49mA

2.2U_0402_6.3V6M~D

1 2

BLM18EG221SN1D_2P_0603

1

CS63

2

0.1U_0402_16V7K

2.2U_0402_6.3V6M~D

1 2

BLM18EG221SN1D_2P_0603

1

2

2.2U_0402_6.3V6M~D

1 2

BLM18EG221SN1D_2P_0603

1

2

2.2U_0402_6.3V6M~D

1

2

1

2

+1.1VALW_SB

CS58

LS6

LS8

LS12

1

2

RS88

1 2

0_0805_5%

10U_0603_6.3V6M

LS1

FBMJ2125HS420-T_2P_0805

22U_0805_6.3V6M~D

RS90

1 2

0_0603_5%

1 2

1

CS59

2

1U_0402_6.3V6K

+3VALW

+3VS

+1.1VALW

12

New PART FBMJ2125HS420-T 42 ohm 4A

RS91

0_0603_5%

+1.1VS

+3VALW

+1.1VALW

US3E

Y14

VSSIO_SATA_1

Y16

VSSIO_SATA_2

AB16

VSSIO_SATA_3

AC14

VSSIO_SATA_4

AE12

VSSIO_SATA_5

AE14

VSSIO_SATA_6

AF9

VSSIO_SATA_7

AF11

VSSIO_SATA_8

AF13

VSSIO_SATA_9

AF16

VSSIO_SATA_10

AG8

VSSIO_SATA_11

AH7

VSSIO_SATA_12

AH11

VSSIO_SATA_13

AH13

VSSIO_SATA_14

AH16

VSSIO_SATA_15

AJ7

VSSIO_SATA_16

AJ11

VSSIO_SATA_17

AJ13

VSSIO_SATA_18

AJ16

VSSIO_SATA_19

A9

VSSIO_USB_1

B10

VSSIO_USB_2

K11

VSSIO_USB_3

B9

VSSIO_USB_4

D10

VSSIO_USB_5

D12

VSSIO_USB_6

D14

VSSIO_USB_7

D17

VSSIO_USB_8

E9

VSSIO_USB_9

F9

VSSIO_USB_10

F12

VSSIO_USB_11

F14

VSSIO_USB_12

F16

VSSIO_USB_13

C9

VSSIO_USB_14

G11

VSSIO_USB_15

F18

VSSIO_USB_16

D9

VSSIO_USB_17

H12

VSSIO_USB_18

H14

VSSIO_USB_19

H16

VSSIO_USB_20

H18

VSSIO_USB_21

J11

VSSIO_USB_22

J19

VSSIO_USB_23

K12

VSSIO_USB_24

K14

VSSIO_USB_25

K16

VSSIO_USB_26

K18

VSSIO_USB_27

H19

VSSIO_USB_28

Y4

EFUSE

D8

VSSAN_HWM

M19

VSSXL

P21

VSSIO_PCIECLK_1

P20

VSSIO_PCIECLK_2

M22

VSSIO_PCIECLK_3

M24

VSSIO_PCIECLK_4

M26

VSSIO_PCIECLK_5

P22

VSSIO_PCIECLK_6

P24

VSSIO_PCIECLK_7

P26

VSSIO_PCIECLK_8

T20

VSSIO_PCIECLK_9

T22

VSSIO_PCIECLK_10

T24

VSSIO_PCIECLK_11

V20

VSSIO_PCIECLK_12

J23

VSSIO_PCIECLK_13

SB820M_FCBGA605~D

LS9

@LS9

+3VALW_HWM

1

CS71

CS70

@

2

@

0.1U_0402_16V7K

+VDDIO_AZ +3VALW

+VDDIO_AZ

1

CS79

2

@

1 2

BLM18EG221SN1D_2P_0603

1

2

Not use HWM

2.2U_0402_6.3V6M~D

12

RS93

RS93 150_0402_1%

150_0402_1%

2.2U_0402_6.3V6M~D

1

SB820M

GROUND

VSSIO_PCIECLK_14 VSSIO_PCIECLK_15 VSSIO_PCIECLK_16 VSSIO_PCIECLK_17 VSSIO_PCIECLK_18 VSSIO_PCIECLK_19 VSSIO_PCIECLK_20 VSSIO_PCIECLK_21 VSSIO_PCIECLK_22 VSSIO_PCIECLK_23 VSSIO_PCIECLK_24 VSSIO_PCIECLK_25 VSSIO_PCIECLK_26 VSSIO_PCIECLK_27

Part 5 of 5

+3VALW

RS92

1 2

0_0402_5%

@

CODEC VDDIO=+3VS

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52

VSSPL_SYS

AJ2 A28 A2 E5 D23 E25 E6 F24 N15 R13 R17 T10 P10 V11 U15 M18 V19 M11 L12 L18 J7 P3 V4 AD6 AD4 AB7 AC9 V8 W9 W10 AJ28 B29 U4 Y18 Y10 Y12 Y11 AA11 AA12 G4 J4 G8 G9 M12 AF25 H7 AH29 V10 P6 N4 L4 L8

M20

H23 H26 AA21 AA23 AB23 AD23 AA26 AC26 Y20 W21 W20 AE26 L21 K20

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

SB820M Power/GND

LA-6132P

19 45Monday, May 03, 2010

1

1.0

of

A

B

C

D

E

+3VS

1 2

RL4 4.7K_0402_5%@RL4 4.7K_0402_5%@

Vendor suggest

1 1

CLK_PCIE_LAN_P<16>

CLK_PCIE_LAN_N<16> PCIE_NTX_LANRX_P0<12> PCIE_NTX_LANRX_N0<12>

PCIE_NRX_LANTX_P0<12> PCIE_NRX_LANTX_N0<12>

EC_SMB_CK2<8,26,28> EC_SMB_DA2<8,26,28>

2 2

Place Close to Chip

+1.2_AVDDL

1

CL22

3 3

2

1U_0402_6.3V6K

YL1

25MHZ_12PF_X5H025000FC1H-H

LAN_X1 LAN_X2

1 2

1

CL16

CL16 15P_0402_50V8J

15P_0402_50V8J

2

1

CL24

CL23

2

0.1U_0402_16V7K

PLT_RST#

CL49 0.1U_0402_16V7KCL49 0.1U_0402_16V7K

+2.5V_VDDH

PCIE_WAKE#<18,26,28>

RL10 0_0402_5%RL10 0_0402_5%

1 2

RL9 0_0402_5%RL9 0_0402_5%

PCIE_NTX_LANRX_P0 PCIE_NTX_LANRX_N0 PCIE_NRX_LANTX_P0 PCIE_NRX_LANTX_P0_C PCIE_NRX_LANTX_N0 PCIE_NRX_LANTX_N0_C

1 2

12

CL8 0.1U_0402_16V7KCL8 0.1U_0402_16V7K

12

CL6 0.1U_0402_16V7KCL6 0.1U_0402_16V7K

Place Close to Chip

EC_SMB_CK2 EC_SMB_DA2

1

CL25

2

0.1U_0402_16V7K

CL26

1

CL17

CL17 15P_0402_50V8J

15P_0402_50V8J

2

1

CL27

2

0.1U_0402_16V7K

RL12 0_0402_5%@ RL12 0_0402_5%@

RL14 0_0402_5%@ RL14 0_0402_5%@

1 2 1 2

+3V_LAN

+2.5V_VDDH/VDD17

12

CLK_PCIE_LAN_P_CCLK_PCIE_LAN_P CLK_PCIE_LAN_N_CCLK_PCIE_LAN_N

RL13 2.37K_0402_1%RL13 2.37K_0402_1%

+1.8_VDD/LX

LAN_RST# PCIE_WAKE#

LAN_X1 LAN_X2

LAN_SMB_CK_R LAN_SMB_DA_R

12

Closed to PIN8 Closed to Pin16, Pin36, Pin39,Pin22

LL1

4.7UH_1008HC-472EJFS-A_5%_1008

LL1

Closed to PIN40

+2.5V_VDDH/VDD17+1.8_VDD/LX +AVDD_CEN

12

CL33

1

2

CL34

10U_0805_10V4Z

1

2

0.1U_0402_16V7K

1 2

RL6 0_0603_5%RL6 0_0603_5%

Closed to transformer

CL35

1

2

1U_0402_6.3V6K

UL10

1

LX

2

VDD3V

6

VDD17

5

VDD25V

3

PERSTn

4

WAKEn

7

SEL_25 MHz

41

REFCLKP

40

REFCLKN

43

RX_P

AR8132 10/100 LAN

44 38 37

10 31

33

12 34

49

AR8132 10/100 LAN

RX_N TX_P TX_N

9

XTLO XTLI

SMCLK SMDATA

RBIAS TESTMODE

GND

AR8132-AL1E_QFN48_6X6

SA000036Y00

Atheros

+3V_LAN

100P_0402_50V8J

29

TWSI_CLK

30

TWSI_DATA

LED0 LED1 LED2

CLKREQn

TRXP0 TRXN0 TRXP1 TRXN1

AVDD_ REG

AVDDL

DVDDL

DVDDL DVDD_REG DVDD_REG

VDD11_ REG

AVDDL AVDDL AVDDL AVDDL

VDDHO

AVDDH

LAN_ACTIVITY LAN_ACTIVITY_R

5.1K_0402_5%

LAN_SK_LAN_LINK100#

RL22 510_0402_1%RL22 510_0402_1%

LAN_SK_LAN_LINK10#

2

CL46

@CL46

@

1

LAN_ACTIVITY

47

LAN_SK_LAN_LINK100#

48

LAN_SK_LAN_LINK10#

26

CLKREQ_LAN#_R CLKREQ_LAN#

27

LAN_MDI0+

13

LAN_MDI0-

14

LAN_MDI1+

17

LAN_MDI1-

18

AVDDVCO1

11

AVDDVCO2

42

28 32 45 46

8 16 22 36 39

15 19 25

20

NC

21

NC

23

NC

24

NC

35

NC

1 2

510_0402_1%

12

RL17

1 2

+3V_LAN_LED

100P_0402_50V8J @

+1.2_DVDDL

+1.2_AVDDL

+2.5V_VDDH

RL16

CL47

RL15 0_0402_5%RL15 0_0402_5%

2

CL36

@

1

100P_0402_50V8J

2

1

12

SB_GPIO27#<16>

PLT_RST#<13,16,26,28>

RJ45_MIDI1-

RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+

CLKREQ_LAN# <18>

DL2

CH751H-40PT_SOD323-2

DL3

CH751H-40PT_SOD323-2

SC1H751H010

SCHOTTKY BARRIER DIODE

JLAN1

13

Unused

12

Yellow LED+

14

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Orange LED-

10

Green LED+

9

Green LED-

FOX_JM3611A-R5A53-7F

DC234004G00

+3V_LAN

21

12

RL25

RL25 10K_0402_5%

10K_0402_5%

LAN_RST#

CONN@JLAN1

CONN@

GND GND

LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1-

+1.2_AVDDL

If overclocking, RL24 stuffed and RL23 removed. If not overclocking, RL23 suffed and RL24 removed. AR8132:CL48=0.1uF.

15 16

Place Close to Chip

RL1 49.9_0402_1%RL1 49.9_0402_1%

1 2

RL2 49.9_0402_1%RL2 49.9_0402_1%

1 2

RL3 49.9_0402_1%RL3 49.9_0402_1%

1 2

RL5 49.9_0402_1%RL5 49.9_0402_1%

1 2

RL23 0_0603_5%RL23 0_0603_5%

Closed to PIN11

Closed to PIN42

0.1U_0402_16V7K

Closed to Pin28, Pin32, Pin45

Closed to PIN5, PIN19, PIN25

1 2

RL24 0_0603_5%@RL24 0_0603_5%@

0.1U_0402_16V7K

Closed to PIN2

1

CL50

CL19

2

0.1U_0402_16V7K

1

CL29

CL28

2

0.1U_0402_16V7K

1

2

1

CL18

2

1

CL48

2

1U_0402_6.3V6K

10U_0805_10V4Z

1

CL12

2

+1.2_DVDDL

1

CL20

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

CL30

2

0.1U_0402_16V7K

1

CL1

2

AVDDVCO1

AVDDVCO2

+3V_LAN

0.1U_0402_16V7K

1

CL13

CL14

2

Closed to PIN46

1

CL21

2

+2.5V_VDDH

Closed to PIN15

1

CL31

2

1U_0402_6.3V6K

CL4

TRL1

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+ TD-8TX-

350uH_NS0013LF

SP050001210

0.1U_0402_16V7K

A

LAN_MDI1+ LAN_MDI1-

LAN_MDI0+ LAN_MDI0-

4 4

CL38

1

2

+AVDD_CEN

1

CL40

2

0.1U_0402_16V7K

RX+ RX-

TX+

RJ45_MIDI1+

16

RJ45_MIDI1-

15 14

CT

13

NC

12

NC

RJ45_CT1

11

CT

RJ45_MIDI0+

10

RJ45_MIDI0-

9

RL18 75_0402_5%RL18 75_0402_5%

1 2

RL19 75_0402_5%RL19 75_0402_5%

B

+TRCTRJ45_CT0

1

CL45

CL45 1000P_1206_2KV7K

1000P_1206_2KV7K

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

LAN_AR8132

LAN_AR8132 LA-6132P

LA-6132P

20 45Tuesday, May 04, 2010

E

of

1.0

5

D D

4

3

2

1

+3VS +3VSIN

C C

USB20_N8<18> USB20_P8<18>

RB1

1 2

0_0805_5%

For EMI

RB6 0_0402_5%RB6 0_0402_5%

1 2

RB7 0_0402_5%RB7 0_0402_5%

1 2

1

CB1

0.1U_0402_16V7K

2

+3VSIN

+CARD_3V

1

CB2

4.7U_0603_6.3V6K

2

@

+CRREFE

1 2

CB6 100P_0402_50V8J

1 2

RB2 6.2K_0402_1%~DRB2 6.2K_0402_1%~D

USB20_N8_R USB20_P8_R

+3VSIN +CARD_3V

+V18CR MSBS_XD6

12

CB7 1U_0402_6.3V6KCB7 1U_0402_6.3V6K

XDCD SDWP_MSCLK_XDRDY

MSINS_XDRE SD1_XDCE SD0_MSD7_XDCLE SD7_MSD3_XDALE

1 2

3 4

5 6

7 8

9 10 11 12

UB11

REFE DM

DP 3V3_IN

CARD_3V3 V18

XD_CD# SP1

SP2 SP3 SP4 SP5

GPIO0

CLK_IN

XD_D7

SP14 SP13 SP12 SP11 SP10

SP9 SP8 SP7 SP6

EPAD

RTS5138-GR_QFN24_4X4

25

17 24 23 22

21 20 19 18 16 15 14 13

CLK_48M XD7

SD2_MSD5_XD5 SD3_MSD1_XD4 SD4_MSD4_XD3 SDCMD_XD2 SD5_MSD0_XD1 SDCLK_MSD2_XD0 SD6_MSD6_XDWP SDCD_XDWE

CLK_48M <16>

CB3 0.1U_0402_16V7KCB3 0.1U_0402_16V7K

SDCLK_MSD2_XD0 SD5_MSD0_XD1 SDCMD_XD2 SD4_MSD4_XD3 SD3_MSD1_XD4 SD2_MSD5_XD5 MSBS_XD6 XD7

SDCD_XDWE SD6_MSD6_XDWP SD7_MSD3_XDALE XDCD SDWP_MSCLK_XDRDY MSINS_XDRE SD1_XDCE SD0_MSD7_XDCLE

+CARD_3V

12

+CARD_3V +CARD_3V

JCARD1

CONN@

JCARD1

3

XD-VCC

32

XD-D0

10

XD-D1

9

XD-D2

8

XD-D3

7

XD-D4

6

XD-D5

5

XD-D6

4

XD-D7

34

XD-WE

33

XD-WP

35

XD-ALE

40

XD-CD

39

XD-R/B

38

XD-RE

37

XD-CE

36

XD-CLE

11

7IN1 GND

31

7IN1 GND

41

7IN1 GND

42

7IN1 GND

TAITW_R015-B10-LM_NR

CONN@

7 IN 1 CONN

SD-WP-SW

SD-VCC

MS-VCC

SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7

SD-CMD

SD-CD-SW

MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3

MS-INS

MS-BS

21 28

SDCLK_MSD2_XD0

20

SD0_MSD7_XDCLE

14

SD1_XDCE

12

SD2_MSD5_XD5

30

SD3_MSD1_XD4

29

SD4_MSD4_XD3

27

SD5_MSD0_XD1

23

SD6_MSD6_XDWP

18

SD7_MSD3_XDALE

16

SDCMD_XD2

25

SDCD_XDWE

1

SDWP_MSCLK_XDRDY

2

SDWP_MSCLK_XDRDY

26

SD5_MSD0_XD1

17

SD3_MSD1_XD4

15

SDCLK_MSD2_XD0

19

SD7_MSD3_XDALE

24

MSINS_XDRE

22

MSBS_XD6

13

+CARD_3V

CB4 0.1U_0402_16V7KCB4 0.1U_0402_16V7K

+CARD_3V

CB5

12 12

0.1U_0402_16V7K

SP07000GW00

USB20_N8_R USB20_P8_R

1

AMD@

CB10

0.1U_0402_16V7K

B B

0.1U_0402_16V7K

AMD@

CB11

0.1U_0402_16V7K

2

Place close to UB11 for AMD

CLK_48M

@

RB8

22_0402_5%~D

@

CB12

10P_0402_50V8J~D

Place close to JCARD1 for EMI

12

1

2

12

RB4

@ RB4

@

10_0402_5%

1

CB8

@ CB8

@

22P_0402_50V8J

2

SDWP_MSCLK_XDRDYSDCLK_MSD2_XD0

12

RB5

@ RB5

@

10_0402_5%

1

CB9

@ CB9

@

22P_0402_50V8J

2

Place closed to UB11

(For RF request)

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Card Reader RTS5138

LA-6132P

21 45Tuesday, May 04, 2010

1

1.0

of

5

4

3

2

1

HDMI_TXD2P<12>

D D

C C

B B

HDMI_TXD2N<12> HDMI_TXD1P<12> HDMI_TXD1N<12> HDMI_TXD0P<12> HDMI_TXD0N<12> HDMI_CLKP<12> HDMI_CLKN<12>

2N7002DW-7-F_SOT363-6~D

HDMICLK_UMA<13>

2N7002DW-7-F_SOT363-6~D

HDMIDAT_UMA<13>

QV3B

HDMI_TXD2P HDMI_TXD2N HDMI_TXD1P HDMI_TXD1N HDMI_TXD0P HDMI_TXD0N HDMI_CLKP HDMI_CLKN

+3VS +5VS

@

QV3A

2

1 2

RV16 0_0402_5%RV16 0_0402_5%

+3VS +5VS

@

5

4

1 2

RV21 0_0402_5%RV21 0_0402_5%

+5VS

+3VS

RV1

C

E

HDMI_HPD<13>

12

RV13

4.7K_0402_5%

61

12

RV18

4.7K_0402_5%

3

HDMI_SCL_SINK

HDMI_SDA_SINK

3 1

12

RV1

91K_0402_5%~D

1 2

2

B

QV1

QV1 MMBT3904_SOT23-3~D

MMBT3904_SOT23-3~D

RV5

2.7K_0402_5%~D

HDMI_HPD_SINK HDMI_HPD_SINK

12

RV3

RV3 200K_0402_5%

200K_0402_5%

@

Place close JHDMI1

RV14 0_0402_5%

@

HDMI_CLKP

HDMI_CLKN

HDMI_TXD2P

HDMI_TXD2N

HDMI_TXD1P

HDMI_TXD1N

HDMI_TXD0P

HDMI_TXD0N

1 2

LV1

1

4

1 2

RV15

RV17 0_0402_5%@RV17 0_0402_5%@

1 2

1

4

1 2

RV19 0_0402_5%@ RV19 0_0402_5%@

RV20 0_0402_5%@RV20 0_0402_5%@

1 2

1

4

1 2

RV22 0_0402_5%@ RV22 0_0402_5%@

RV23

@

1 2

1

4

1 2

RV24 0_0402_5%@ RV24 0_0402_5%@

LV2

LV3

LV4

2

WCM-2012-900T_4P

3

0_0402_5%@

2

WCM-2012-900T_4P

3

2

WCM-2012-900T_4P

3

0_0402_5%

2

WCM-2012-900T_4P

3

HDMI_OUT_CLK+_CONN

HDMI_OUT_CLK-_CONN

HDMI_OUT_D2+_CONN

HDMI_OUT_D2-_CONN

HDMI_OUT_D1+_CONN

HDMI_OUT_D1-_CONN

HDMI_OUT_D0+_CONN

HDMI_OUT_D0-_CONN

@ RV53

@

1 2

RV54 0_0402_5%RV54 0_0402_5%

100K_0402_5%

RV53

0_0402_5%

RV9

12

13

D

QV2

2

SSM3K7002FU_SC70-3

G

S

12

PAD-OPEN 43x79

CV9

1U_0402_6.3V6K

1 2

RV2 715_0402_1%RV2 715_0402_1% RV4 715_0402_1%RV4 715_0402_1% RV6 715_0402_1%RV6 715_0402_1% RV7 715_0402_1%RV7 715_0402_1% RV8 715_0402_1%RV8 715_0402_1% RV10 715_0402_1%RV10 715_0402_1% RV11 715_0402_1%RV11 715_0402_1% RV12 715_0402_1%RV12 715_0402_1%

PLACE PULL DOWN RESISTORS CLOSE TO DIFFERENTIAL PAIRS CONNECTED TO SOLID GROUND FLOOD WHICH IS CONTROLLED BY THE FET AVOID STUBS TO ALL DIFFERENTIAL TRACES

+5VS

@

12

PJP61

HDMI_SDA_SINK HDMI_SCL_SINK HDMI_HPD_SINK

HDMI_OUT_CLK-_CONN HDMI_OUT_CLK+_CONN HDMI_OUT_D0-_CONN HDMI_OUT_D0+_CONN HDMI_OUT_D1-_CONN HDMI_OUT_D1+_CONN HDMI_OUT_D2-_CONN HDMI_OUT_D2+_CONN

1 2

CV10 1U_0603_10V6K@CV10 1U_0603_10V6K@

12 12 12 12 12 12 12 12

21

FV1

FV1 2A_8VDC_SMD1812P200TF

2A_8VDC_SMD1812P200TF

+5VS_HDMI

HDMI_HPD_SINK

JHDMI1

CONN@JHDMI1

CONN@

18

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

DDC/CEC_GND

SUYIN_100042MR019S153ZL

DC232000900

HDMI_OUT_CLK-_CONN HDMI_OUT_CLK+_CONN HDMI_OUT_D0-_CONN HDMI_OUT_D0+_CONN HDMI_OUT_D1-_CONN HDMI_OUT_D1+_CONN HDMI_OUT_D2-_CONN HDMI_OUT_D2+_CONN

13

CEC

14

Reserved

2

GND

5

GND

8

GND

11

GND

20

GND

21

GND

22

GND

23

GND

17

TV1

PAD

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

HDMI Conn.

HDMI Conn. LA-6132P

LA-6132P

22 45Tuesday, May 04, 2010

1

1.0

of

5

4

3

2

1

+USB_SIDE_PWR

CI1

0.1U_0402_16V7K

VCC

D+

OE#

D=1D D=2D

S

D-

0.1U_0402_16V7K

10 9 8 7 6

1 2

+3VALW

PWRSHARE_OE#

1 2

RI3 100K_0402_5%RI3 100K_0402_5%

PWRSHARE_OE# <26> PWSUSB_P1 <25> PWSUSB_N1 <25>

RI2

75K_0402_1%

RI2

75K_0402_1%

D D

49.9K_0402_1%

1 2

RI4

1 2

RI5

49.9K_0402_1%

1 2

RI1

43.2K_0402_1%

USB20_P1<18> USB20_N1<18>

USB_CHARGE_D+ USB_CHARGE_D-

UI12

1

1D+

2

1D-

3

2D+

4

2D-

5

GND

TS3USB221RSER_QFN10_2x1P5~D

S Function

OE#

H

Disconnect

X

L

H

USB CONN

USB20_N2<18> USB20_P2<18>

USB20_P2

USB20_N2 USB20_P2

WCM2012F2S-900T04_0805

1 2

RI7 0_0402_5%RI7 0_0402_5%

LI1

@ LI1

@

1

4

1 2

RI6 0_0402_5%RI6 0_0402_5%

2

3

1

CI12

AMD@

2

+USB_VCCA

USB20_N2_RUSB20_N2 USB20_P2_R

DL1

0.1U_0402_16V7K

0.1U_0402_16V7K PJDLC05_SOT23-3

PJDLC05_SOT23-3

1

2

150U_B2_6.3VM_R35M

2

3

1

+

CI2

0.1U_0402_16V7K

1

2

1

2

AMD@

CI13

CI3

0.1U_0402_16V7K

0.1U_0402_16V7K JUSB1

CONN@JUSB1

CONN@

4

VCC

3

D-

2

D+

1

GND

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S50TZL

DC233003W00

(For ESD request)

OC1# OUT1 OUT2 OC2#

+5V_ESAUSB

8 7 6 5

80 mils

+USB_VCCA

USB_OC2#

8 7 6 5

USB_OC0#

USB_OC2# <18>

USB_OC0# <18>

RTCVREF RTCVREF RTCVREF RTCVREF

C C

SDMK0340L-7-F

RI8

10K_0402_5%

USB_DETECT#

USB_DETECT# <25>

12

2.2U_0603_10V7K~D

CI11

220K_0402_5%

12

RI9

12

SDMK0340L-7-F

DI1

2 1

UI16

TC7SZ14FU_SSOP5~D

1 2

5

P

NC A

G

3

1

CI10

0.1U_0402_16V7K

2

CLOSE TO UI16

4

Y

RI11

100K_0402_5%

+5VALW

51ON#

13

D

QI1

2

2N7002LT1G_SOT23-3

G

S

12

S

51ON# <31,34>

10U_1206_16V4Z

CI4

1

CI5

2

From connector detect

2 1

DI2

SDMK0340L-7-F

B B

Power share

1 2

RI10 0_0402_5%RI10 0_0402_5%

USB_DET#_DELAY

USB_DET#_DELAY <26>

10U_1206_16V4Z

CI7

+5VALW

1

2

@ FUSEI1

@

1 2

PJP62 PAD-OPEN 43x79

PAD-OPEN 43x79

1 2

0.1U_0402_16V7K

1

2

FUSEI2

@FUSEI2

@

5A_32V_0467005.NR~D

1 2

PJP63 JUMP_43X79

JUMP_43X79

1 2

1

CI6

2

0.1U_0402_16V7K

FUSEI1

5A_32V_0467005.NR~D

@PJP62

@

@PJP63

@

+5VALW_F2

80 mils

+5VALW_F1

USB_EN#<26>

2.0A

UI13

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062ADR_SO8~D

SA00002AS0L

CIS LINK OK

ESATA

UI14

1

GND

2 3 4

OC1#

IN

OUT1 OUT2

EN1#

OC2#

EN2#

TPS2062ADR_SO8~D

FUSEI3

@FUSEI3

@

5A_32V_0467005.NR~D

1 2

+5VALW

10U_1206_16V4Z

1

CI8

2

A A

PJP64 PAD-OPEN 43x79

PAD-OPEN 43x79

1 2

0.1U_0402_16V7K

1

CI9

2

@PJP64

@

+5VALW_F3

USB_PWR_EN#<26>

UI15

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062ADR_SO8~D

OC1# OUT1 OUT2

OC2#

+USB_SIDE_PWR

USB_OC1#

8 7 6 5

USB_OC1# <18>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc. USB/POWER Share

USB/POWER Share

LA-6132P

23 45Tuesday, May 04, 2010

1

1.0

of

5

4

3

2

1

D D

C R T

Intel USE BLM15BB470SS1D (47 OHM BEAD)

FOOT PRINT is Different

VGA_CRT_R<13>

VGA_CRT_G<13>

VGA_CRT_B<13>

C C

B B

VGA_DDC_DATA<13>

VGA_DDC_CLK<13>

VGA_CRT_R

VGA_CRT_G

VGA_DDC_DATA

VGA_DDC_CLK

RV29

150_0402_1%

RV29

150_0402_1%

RV30

150_0402_1%

RV30

150_0402_1%

12

AMD Check List: R=140 ohm

Need CIS symbol

+3VS +CRT_VCC +CRT_VCC+3VS+3VS

4.7K_0402_5%

12

+3VS

12

RV56

AMD@

CV38

0.1U_0402_16V7K

1 2

RV55

VGA_DDC_DATA

VGA_DDC_CLK

140_0402_1%~D

4.7K_0402_5%

RV51 0_0603_5%

RV52 0_0603_5%

CV33

1

2

@

G

2

S

G

2

QV4

QV4 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

13

D

S

D

S

QV5

QV5 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

@

1 2

@

1 2

4.7P_0402_50V8C

RV28

140_0402_1%~D

RV28

RV25 0_0402_5%RV25 0_0402_5%

RV26 0_0402_5%RV26 0_0402_5%

RV27 0_0402_5%RV27 0_0402_5%

4.7P_0402_50V8C

CV34

1

2

@

12

RV31

13

D

AMD@

CV39

0.1U_0402_16V7K

1 2

CV35

SE00000AY80 change to 6P_0402 Need apply CIS symbol

4.7K_0402_5%

12

RV32

CRT_DDC_DATA_C

CRT_DDC_CLK_C

CRT_DDC_DATA_C

CRT_DDC_CLK_C

CRT_R_RL

CRT_G_RL

6P_0402_50V

CV12

1

2

@

6P_0402_50V

CV13

1

2

@

VGA_CRT_HSYNC<13>

VGA_CRT_VSYNC<13>

1 2

LV5 47NH_LQG15HN47NJ02D_5%LV5 47NH_LQG15HN47NJ02D_5%

1 2

LV6 47NH_LQG15HN47NJ02D_5%LV6 47NH_LQG15HN47NJ02D_5%

1 2

LV7 47NH_LQG15HN47NJ02D_5%LV7 47NH_LQG15HN47NJ02D_5%

6P_0402_50V

CV14

1

2

@

For EMI

74AHCT1G125GW_SOT353-5

VGA_CRT_VSYNC

Place close to JCRT1 for AMD

AMD@

CV40

0.1U_0402_16V7K

+3VS

1 2

2

3

+CRT_VCC

UV18

+CRT_VCC

1

4.7P_0402_50V8C

1

2

1

5

P

A2Y

G

3

1

5

P

A2Y

G

3

CRT_R_L

CRT_G_L

CRT_B_LCRT_B_RLVGA_CRT_B

CV19

0.1U_0402_16V7K

1 2

CV20

0.1U_0402_16V7K

1 2

AMD@

CV41

0.1U_0402_16V7K

1 2

RV35

1 2

10K_0402_5%

3

DV1

DV1 DAN217_SC59-3

DAN217_SC59-3

AMD@

CV15

4

OE#

4

OE#

UV19

UV19 74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

2

DV2

DV2 DAN217_SC59-3

DAN217_SC59-3

AMD@

1

CV16

4.7P_0402_50V8C

CV16

4.7P_0402_50V8C

1

2

D_CRT_HSYNC

D_CRT_VSYNC

AMD@

CV42

0.1U_0402_16V7K

1 2

2

3

DV3

DV3 DAN217_SC59-3

DAN217_SC59-3

AMD@

1

CV17

4.7P_0402_50V8C

CV17

4.7P_0402_50V8C

1

2

1 2

+5VS +5VS_CRT

RB491D_SC59-3~D

MSEN#<26>

RV33

0_0603_5%

RV34

0_0603_5%

15P_0402_50V8J

1

2

2 1 3

NC

DV4

MSEN#

CRT_R_L

CRT_DDC_DATA_C

CRT_G_L HSYNC_L

CRT_B_L VSYNC_L

CRT_DDC_CLK_C

CV21

15P_0402_50V8J

1

2

W=40mils

5A_125V_R451005.MRL~D

CV18

100P_0402_50V8J

CV18

100P_0402_50V8J

1

2

HSYNC_LVGA_CRT_HSYNC

VSYNC_L

CV22

FV2

1 2

+CRT_VCC

W=40milsW=40mils

1

CV11

CV11 1U_0603_10V6K

1U_0603_10V6K

2

JCRT1

CONN@

JCRT1

CONN@

6

11

1 7

12

2 8

G

13

G

3 9

14

4 10 15

5

SUYIN_070546FR015M21TZR

DC060004300

16 17

2

A A

CRT_DDC_DATA_C CRT_DDC_CLK_C

3

1

DV8

DV8 DAN217_SC59-3

DAN217_SC59-3

AMD@

Place close to JCRT1 for AMD

5

3

1

2

DV9

DV9 DAN217_SC59-3

DAN217_SC59-3

AMD@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

VGA Conn.

VGA Conn. LA-6132P

LA-6132P

24 45Monday, May 10, 2010

1

1.0

of

A

B

C

D

E

Power LED

1 1

RO1 100K_0402_5%RO1 100K_0402_5%

PWR_LED#<26>

2 2

+5VALW

DO1

HT-210UD5-BP5_AMBER-WHITE

White

12

QO1A

2

G

12

RO2 100K_0402_5%RO2 100K_0402_5%

QO1B

5

G

61

D

DMN66D0LDW-7_SOT363-6

S

RO3

1 2

820_0402_5%

34

D

DMN66D0LDW-7_SOT363-6

S

PWR_LED#_D

BATT_LOW_LED#_D

White

2

1

3

Amber

+5VALW

BATT_LOW_LED#<26>

BATT CHARGE

+5VALW

12

RO4

100K_0402_5%

QO2A

2

G

12

RO5

100K_0402_5%

QO2B

5

G

61

D

DMN66D0LDW-7_SOT363-6

S

BATT_LOW_LED#_D

12

RO6

RO6 300_0402_5%~D

300_0402_5%~D

34

D

DMN66D0LDW-7_SOT363-6

S

JWTB1

CONN@JWTB1

CONN@

1

41 42 43 44 45 46

HD LED

QO3A

2

G

+5VS

12

QO3B

RO8 100K_0402_5%RO8 100K_0402_5%

5

G

61

D

DMN66D0LDW-7_SOT363-6

S

RO9

1 2

820_0402_5%

34

D

DMN66D0LDW-7_SOT363-6

S

SATA_LED#_D

DO3

HT-121BP_WHITE

21

+5VS

3 3

SATA_ACT#_R<17>

2

G1

3

G2

4

G3

5

G4

6

G5

7

G6

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

STARC_107K40-000001-G2

PWSUSB_N1 <23> PWSUSB_P1 <23>

USB20_N0 <18> USB20_P0 <18>

DMIC_CLK <27> DMIC_DATA <27>

HDA_BITCLK_SSIC <18> HDA_SYNC <18> SB_SPKR <18> HDA_RST# <18>

HDA_SDIN0 <18>

HDA_SDOUT <18> BEEP# <26>

EC_EAPD <26> EC_MUTE# <26>

+5V_ESAUSB

+USB_SIDE_PWR

+5VS

+3VS

USB_DETECT# <23>

SP01000XE00

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

WTB Conn/LED

LA-6132P

25 45Tuesday, May 04, 2010

E

1.0

of

A

CLK_PCI_EC

12

RE2

@ RE2

@

10_0402_5%

@

27P_0402_50V8J

1

CE7

@ CE7

@

22P_0402_50V8J

2

EC_CLKRUN#_REC_CLKRUN#

PLT_RST#

CE25

@ CE25

@

0.1U_0402_16V7K

Place close to EC (For ESD request)

1 2

RE20 20M_0603_5%@ RE20 20M_0603_5%@

32.768KHZ_12.5P_1TJE125DP1A000M

1 2

1

CE12

XE1

2

47K_0402_5%

1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2

1 2

1 2 1 2

@

1 2

@

1 2

1 2 1 2

+3VALW

12

RE8

2

CE8

1

SIO_EXT_SMI# SIO_EXT_SCI#

PCIE_WAKE# EC_MUTE# LID_SW# KSO1 KSO2 MSEN#

ACIN_EC

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

BT_RADIO_OFF# BT_DET#

A

EC_RST#

1 2

RE33 0_0402_5%

1 1

0.1U_0402_16V7K

EC_CLKRUN#<16>

2 2

+3VALW

RE11 8.2K_0402_5%@ RE11 8.2K_0402_5%@ RE12 8.2K_0402_5%@ RE12 8.2K_0402_5%@

+3VALW

RE13 10K_0402_5%RE13 10K_0402_5% RE14 10K_0402_5%@RE14 10K_0402_5%@ RE15 10K_0402_5%RE15 10K_0402_5% RE16 47K_0402_5%RE16 47K_0402_5% RE17 47K_0402_5%RE17 47K_0402_5%

3 3

4 4

RE31 10K_0402_5%RE31 10K_0402_5%

RE32 10K_0402_5%RE32 10K_0402_5%

+5VALW

RE18 4.7K_0402_5%RE18 4.7K_0402_5% RE19 4.7K_0402_5%RE19 4.7K_0402_5%

+3VALW

RE21 2.2K_0402_5%

RE21 2.2K_0402_5% RE22 2.2K_0402_5%

RE22 2.2K_0402_5%

+3VS

RE23 2.2K_0402_5%RE23 2.2K_0402_5% RE24 2.2K_0402_5%RE24 2.2K_0402_5%

+3VS

RE26 4.7K_0402_5%RE26 4.7K_0402_5% RE27 10K_0402_5%RE27 10K_0402_5%

B

+3VALW +3VALW

CE4

0.1U_0402_16V7K

CE4

CE2

0.1U_0402_16V7K

CE2

0.1U_0402_16V7K

CE1

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

1

2

1

2

4.7U_0603_6.3V6K

1

CE13

CE13 27P_0402_50V8J

27P_0402_50V8J

2

GATEA20 KB_RST# IRQ_SERIRQ LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0

CLK_PCI_EC PLT_RST# EC_RST# SIO_EXT_SCI# EC_CLKRUN#_R

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SIO_SLP_S3# SIO_SLP_S5# SIO_EXT_SMI# SMB_ALERT# BT_RADIO_OFF# CE_ENABLE

INVT_PWM FAN_SPEED1 CAM_ON/OFF# EC_TX EC_RX ON/OFF_EC# PWR_LED# BT_DET#

XCLKI XCLKO

GATEA20<18> KB_RST#<18>

IRQ_SERIRQ<16>

LPC_LFRAME#<16,28>

LPC_LAD3<16,28> LPC_LAD2<16,28> LPC_LAD1<16,28> LPC_LAD0<16,28>

CLK_PCI_EC<16,17> PLT_RST#<13,16,20,28>

SIO_EXT_SCI#<18>

2

1

EC_SMB_CK1<33> EC_SMB_DA1<33> EC_SMB_CK2<8,20,28> EC_SMB_DA2<8,20,28>

SIO_SLP_S3#<18> SIO_SLP_S5#<18> SIO_EXT_SMI#<18> SMB_ALERT#<8,13,18> BT_RADIO_OFF#<28> CE_ENABLE<27>

INVT_PWM<27>

FAN_SPEED1<29>

CAM_ON/OFF#<27>

EC_TX<28>

EC_RX<28> ON/OFF_EC#<31> PWR_LED#<25>

BT_DET#<28>

0.1U_0402_16V7K

CE3

0.1U_0402_16V7K

CE3

0.1U_0402_16V7K

1

2

UE20

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

KB926QFD3_LQFP128_14X14

1

2

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

9

VCC

PS2 Interface

E0 version: SA00001J5A0

C

+EC_AVCC

22

33

96

111

125

67

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D

DA Output

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

GPO

GPIO

GPI

GND

AGND

GND

11

24

35

69

94

113

ECAGND

1

CE5

0.1U_0402_16V7K

2

ECAGND

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B AD4/GPIO42

SELIO2#/AD5/GPIO43

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

CAPS_LED#/GPIO53 SUSP_LED#/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10 GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

SB_PWRGD_EC

FBMA-L11-160808-601LMT_2P

1

CE6

4.7U_0603_6.3V6K

2

RE3 0_0402_5%RE3 0_0402_5%

DBC_ENABLE

21

BEEP#

23

USB_PWR_EN#

26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64

ADP_I

65

AD_BID

66

MSEN#

75

VGATE

76

68

EN_DFAN1

70

IREF

71

CHGVADJ

72

EC_MUTE#

83

USB_EN#

84 85

USB_DET#_DELAY

86

TP_CLK

87

TP_DATA

88

BT_OFF#

97

EN_WOL#

98 99

LID_SW#

109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

WLAN_RADIO_OFF#

73

PS_ID

74

FSTCHG

89

EN_INVPWR

90

PWRSHARE_OE#

91

BATT_LOW_LED#

92

LCD_TEST

93

SYSON

95

VR_ON

121 127

EC_RSMRST#

100

EC_LID_OUT#

101

EC_ON

102

SB_RI#

103

SB_PWRGD_EC

104

BKOFF#

105

WWAN_RADIO_OFF#

106

LCD_VCC_TEST_EN

107

PSID_DISABLE#

108

110

EC_ENBKL

112

EC_EAPD

114 115

SUSP#

116

PBTN_OUT#

117

PCIE_WAKE#

118

V18R

124

CE10

0.1U_0402_16V7K

RE25

RE25 0_0402_5%

0_0402_5%

1 2

LE1

2 1

DE2 CH751H-40PT_SOD323-2DE2 CH751H-40PT_SOD323-2

1

2

+3VALW

12

DBC_ENABLE <27> BEEP# <25> USB_PWR_EN# <23> ACOFF <34,35>

BATT_TEMP <33> BATT_OVP <33> ADP_I <35>

MSEN# <24> VGATE <8,42>

EN_DFAN1 <29> IREF <35> CHGVADJ <35>

EC_MUTE# <25> USB_EN# <23>

USB_DET#_DELAY <23>

BT_OFF# <28> EN_WOL# <17,30>

LID_SW# <31>

FRD#SPI_SO <31> FWR#SPI_SI <31> SPI_CLK <31> FSEL#SPICS# <31>

WLAN_RADIO_OFF# <28> PS_ID <34>

FSTCHG <35> EN_INVPWR <27> PWRSHARE_OE# <23> BATT_LOW_LED# <25> LCD_TEST <27> SYSON <39> VR_ON <42>

EC_RSMRST# <18> EC_LID_OUT# <18> EC_ON <31> SB_RI# <18>

BKOFF# <27> WWAN_RADIO_OFF# <28> LCD_VCC_TEST_EN <27> PSID_DISABLE# <34>

EC_ENBKL <27> EC_EAPD <25>

SUSP# <30,35,40,41,43> PBTN_OUT# <18> PCIE_WAKE# <18,20,28>

1

CE11

4.7U_0603_6.3V6K

2

CE14

0.47U_0603_16V7K@

SB_PWRGD <8,13,18>

1

2

D

ACINACIN_EC

BOARD ID Table

4.7K_0402_5%

TP_CLK TP_DATA

ACIN <18,34>

EC Team request

ID

0 1 2 3

ACIN

AD_BID

@

RE9

CE9

RE4

Board ID

12

RE5

@

0_0402_5%

33K_0402_5%

BOARD ID

0.1(X00)

0.2(X01)

0.3(X02)

1.0(A00)

+5VS

12

RE10

4.7K_0402_5%

TP_CLK <31> TP_DATA <31>

KEYBOARD CONN.

1

2

0.1U_0402_16V7K

KSI1 KSI0

1

@ CE20

@

22P_0402_50V8J

2

KSO7

1

@ CE22

@

22P_0402_50V8J

2

KSO15

1

@ CE24

@

22P_0402_50V8J

2

100K_0402_5%

12

RE6

18K_0402_5%

100K 100K 100K

CE20

KSO8

CE22

CE24

NC

KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1

RE1

E

RE7

@

8.2K_0402_5%

RbRa

8.2K 18K NC

1

CE21

@ CE21

@

22P_0402_50V8J

2

1

CE23

@ CE23

@

22P_0402_50V8J

2

Ra

1 2 12

Rb

0

0.25V

0.50V

3.3V

ACES_88514-2401

26

GND2

25

GND1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JKB1

DC020906103

For EMI

Vab

0V

CONN@JKB1

CONN@

*

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B

C

D

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

ENE-KB926/KB Conn

LA-6132P

26 45Tuesday, May 04, 2010

E

1.0

of

A

LCD POWER CIRCUIT

1 1

SSM3K7002FU_SC70-3

ENVDD<13>

LCD_VCC_TEST_EN<26>

2 2

BKOFF#<26>

EC_ENBKL<26>

ENBKL<13>

3 3

INVT_PWM<26> NB_LCD_PWM<13>

4 4

LCD_VCC_TEST_EN

RV43

1 2

4.7K_0402_5%

BKOFF# BL_OFF#

EC_ENBKL

1 2

RV45 0_0402_5%RV45 0_0402_5%

A

2 1

CH751H-40PT_SOD323-2

2 1

CH751H-40PT_SOD323-2

1 2

RV61 0_0402_5%

@

BKOFF#

@

RV47 0_0402_5%

1 2

+3VS

5

1

P

INA

2

INB

G

74AHC1G32GW_SOT353-5~D

3

1 2

RV50 0_0402_5%

@

+LCDVDD +5VALW +3VS

12

RV36

100_0805_5%

13

D

QV7

DV5

DV10

CV29 0.1U_0402_16V7K

UO21

4

O

2

G

S

2

G

12

RV41

RV41 10K_0402_5%

10K_0402_5%

@

12

DV6

CH751H-40PT_SOD323-2

DV7

@ DV7

@

CH751H-40PT_SOD323-2

+3VS

RV48

RV48 10K_0402_5%

10K_0402_5%

@

1 2

1

100P_0402_50V8J

2

CV32

B

12

RV37

RV37 47K_0402_5%

47K_0402_5%

RV38 56K_0402_5%RV38 56K_0402_5%

13

D

QV9

SSM3K7002FU_SC70-3

S

+3VS+3VS

21

LCD_PWM

12

RV44

4.7K_0402_5%

B

12

1

CV24

0.1U_0402_16V7K

2

0.1U_0402_16V7K

W=60mils

QV8

AO3413_SOT23-3

S

G

USB20_N9<18>

USB20_P9<18>

2

4.7U_0805_10V4Z

CO5

W=60mils

D

1 3

+LCDVDD

0.1U_0402_16V7K

1

2

+5VS +5VS_CAM

CV28

CV27

2

RO12

@ RO12

@

1 2

0_0603_5%

SI2301BDS-T1-E3_SOT23-3

S

12

1

RO13

2

100K_0402_5%

1 2

RV49 1K_0402_5%RV49 1K_0402_5%

RO10 0_0402_5%RO10 0_0402_5%

@ LO1

@

RO11 0_0402_5%RO11 0_0402_5%

QO4

G

2

CAM_ON/OFF#<26>

C

@ LV8

@

FBMA-L11-201209-221LMA30T_0805

B+

40mil

1000P_0402_50V7K

1

2

EN_INVPWR<26>

1 2

LO1

1

4

WCM2012F2S-900T04_0805

1 2

+5VS_CAM

D

13

CAM_ON/OFF

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

G

C

2

3

W=20mils

1

2

13

D

S

CV25

USB20_N9_RUSB20_N9

USB20_P9_RUSB20_P9

CO4

0.1U_0402_16V7K

@

QO5

QO5 2N7002_SOT23-3

2N7002_SOT23-3

12

RV39

RV39 100K_0402_5%

100K_0402_5%

PWR_SRC_ON

1 2

RV42 100K_0402_5%RV42 100K_0402_5%

FBMA-L11-201209-221LMA30T_0805

B+

QV6

SI3457BDV-T1-E3_TSOP6

D

6

S

4 5

2 1

G

3

D

1 3

2

USB20_P9_R USB20_N9_R

AMD@

CE_ENABLE<26>

DBC_ENABLE<26>

CE_ENABLE Pin.34 DBC_ENABLE Pin.37

QV10

QV10 2N7002W-7-F_SOT323-3

2N7002W-7-F_SOT323-3

S

G

CO6

D

LV8

12

INVPWR_B+

40mil

INVPWR_B+

1

CV23

0.1U_0603_50V4Z

2

DO4

PJDLC05_SOT23-3

3

1

2

AMD@

0.1U_0402_16V7K

Place close to JLVDS1 for AMD

+5VS_CAM

DMIC_CLK<25>

DMIC_DATA<25>

1 2

RV57 0_0402_5%RV57 0_0402_5%

DBC_ENABLE

1 2

RV58 0_0402_5%RV58 0_0402_5%

D

2

CO7

AMD@

100P_0402_50V8J

CE_ENABLE_RCE_ENABLE

DBC_ENABLE_R

1

2

E

+5VALW

INVPWR_B+

12

100K_0402_5%

QV11

2N7002W-7-F_SOT323-3

EN_INVPWR

RV59

12

13

D

2

G

S

2

G

RV60

RV60 820_0805_1%

820_0805_1%

13

D

QV12

QV12 2N7002W-7-F_SOT323-3

2N7002W-7-F_SOT323-3

S

Discharg Circuit

+3VS

1

CV26

0.1U_0402_16V7K

2

Closed to JLVDS1

JLVDS1

CONN@JLVDS1

CONN@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

STARC_107K40-000001-G2

SP01000XE00

0.1U_0603_50V4Z

G1 G2 G3 G4 G5 G6

LCD_TEST<26> LDDC_CLK_MCH<13> LDDC_DATA_MCH<13> LVDS_A0-<13> LVDS_A0+<13>

LVDS_A1-<13>

LO2

1 2

1

CO2

100P_0402_50V8J

2

RV46 0_0402_5%RV46 0_0402_5%

INVPWR_B+

68P_0402_50V8J

LVDS_A1+<13> LVDS_A2-<13>

LVDS_A2+<13> LVDS_ACLK-<13>

LVDS_ACLK+<13>

1 2

CV30

0.1U_0402_16V7K

USB20_P9_R USB20_N9_R

FBMA-L10-160808-301LMT_2P

CO3

+LCDVDD

+3VS

DMIC_CLK_R

1

CV31

2

W=60mils

1

2

LCD_PWM BL_OFF#_RBL_OFF#

1

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LVDS/Cam Conn

LA-6132P

27 45Tuesday, May 04, 2010

E

of

41 42 43 44 45 46

1.0

A

WWAN PCIE MiniCard

JWWAN1

CONN@JWWAN1

PCIE_WAKE#<18,20,26>

1 1

CLKREQ_WWAN#<18>

CLK_PCIE_WWAN_N<16> CLK_PCIE_WWAN_P<16>

PCIE_NRX_WWANTX_N2<12> PCIE_NRX_WWANTX_P2<12>

PCIE_NTX_WWANRX_N2<12> PCIE_NTX_WWANRX_P2<12>

PCIE_WAKE#

+3VS

check layout symbol

2 2

CONN@

1

3

5

7

9

9 111112 131314 151516

171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

53

GND1

GND2

55

NC

BELLW_80052-1021

DC040006S00

2

4

6

8

10

12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54 56

NC

WLAN/WIMAX PCIE Mini Card

+3V_WLAN

+3VS

RM5 0_1206_5%RM5 0_1206_5%

3 3

BT_RADIO_OFF# BT_ACTIVE_OFF

PCIE_NRX_WLANTX_N1<12> PCIE_NRX_WLANTX_P1<12>

PCIE_NTX_WLANRX_N1<12> PCIE_NTX_WLANRX_P1<12>

BT_RADIO_OFF# BT_DISABLE

4 4

USB20_P4<18>

USB20_N4<18>

12

CLK_DEBUG_PORT_1<16>

BT_RADIO_OFF#

RM16 0_0402_5%

RM16 0_0402_5% RM17 0_0402_5%

RM17 0_0402_5%

CLK_PCIE_WLAN_N<16> CLK_PCIE_WLAN_P<16>

RM18 0_0402_5%

EC_TX<26>

EC_RX<26>

1 2

USB20_P4 USB20_P4_R

40 mils 20 mils

1

2

CM18

CM15

CM16

0.01U_0402_25V7K

0.047U_0402_16V4Z

@

1 2

@

1 2

CLKREQ_WLAN#<18>

PLT_RST# BT_DISABLEB#

@

1 2

RM9 100K_0402_5%RM9 100K_0402_5%

RM12 0_0402_5%RM12 0_0402_5%

1

4

WCM2012F2S-900T04_0805

RM13 0_0402_5%RM13 0_0402_5%

A

CM18

CM17

4.7U_0805_10V4Z

0.1U_0402_16V7K

@

RM19 0_0402_5%

1 2

RM20 0_0402_5%RM20 0_0402_5%

1 2

COEX2_WLAN_ACTIVE

CLKREQ_WLAN#

1 2

RM6 0_0402_5%RM6 0_0402_5%

PCIE_NRX_WLANTX_N1 PCIE_NRX_WLANTX_P1

PCIE_NTX_WLANRX_N1 PCIE_NTX_WLANRX_P1

+3V_WLAN

RM10 0_0402_5%RM10 0_0402_5%

1 2

RM11 0_0402_5%RM11 0_0402_5%

1 2

LM2

@ LM2

@

1

2

3

4

1 2

+1.5VS

1

2

PCIE_WAKE#BT_ACTIVE

1

2

CM19

0.01U_0402_25V7K

BT_DISABLEB#

JWLAN1

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

ACES_88910-5204

SP01000I100

2

USB20_N4_RUSB20_N4

3

+1.5VS

1

2

CM20

0.1U_0402_16V7K

CONN@JWLAN1

CONN@

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

GND1

GND2

B

CM23

AMD@

+UIM_PWR

@

1 2 1 2

@

1

CM24

2

AMD@

0.1U_0402_16V7K

WWAN_RADIO_OFF# <26>

UIM_DATA UIM_CLK UIM_RESET UIM_VPP

WWAN_RADIO_OFF# WWAN_RST#

WWAN_SMB_CK_R WWAN_SMB_DA_R

Place close to JWWAN1 for AMD

1

2

CM21

4.7U_0805_10V4Z

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

B

2

CM22

0.047U_0402_16V4Z

+3V_WLAN

+1.5VS

SP01000MO0L CIS LINK OK

For Compal LPC debug card

WLAN_RADIO_OFF#

WLAN_RST#

WLAN_SMB_CLK_R WLAN_SMB_DAT_R

+1.5VS

1

CM2

2

WWAN@ CM2

WWAN@

0.1U_0402_16V7K

CM7

1

2

WWAN@ CM7

WWAN@

4.7U_0805_10V4Z

EC_SMB_CK2 <8,20,26> EC_SMB_DA2 <8,20,26>

USB20_P5<18>

USB20_N5<18>

PWR Rail

CM5

WWAN@ CM5

WWAN@

0.047U_0402_16V4Z

1

2

0.1U_0402_16V7K

1

2

CM1

WWAN@ CM1

WWAN@

0.01U_0402_25V7K

CM6

WWAN@ CM6

WWAN@

0.01U_0402_25V7K

RM10_0402_5%@RM10_0402_5% RM20_0402_5%@RM20_0402_5%

USB20_N5_R USB20_P5_R

1

2

1

2

+3.3V

+3.3Vaux

+1.5V

LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0

WLAN_RADIO_OFF# <26>

0_0402_5% @

RM7

1 2

RM8

1 2

0_0402_5% @

AMD@

CM25

0_0402_5% @

1

AMD@

CM26

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

USB20_N4_R USB20_P4_R

Place close to JWLAN1 for AMD

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

1

CM4

CM3

2

WWAN@ CM4

WWAN@

WWAN@ CM3

WWAN@

4.7U_0805_10V4Z

0.047U_0402_16V4Z

+3VS

1

CM9

CM8

WWAN@ CM8

WWAN@

0.1U_0402_16V7K

Voltage Tolerance

+-9%

+-5%

EC_SMB_CK2 <8,20,26> EC_SMB_DA2 <8,20,26>

C

110 mils

+

2

WWAN@

WWAN@ DM1

WWAN@

CH751H-40PT_SOD323-2

330U_D2E_6.3VM_R25M

USB20_P5 USB20_P5_R

CH751H-40PT_SOD323-2

SB_GPIO2#<16>

PLT_RST#<13,16,20,26>

WWAN@ DM2

WWAN@

CH751H-40PT_SOD323-2

SC1H751H010

SCHOTTKY BARRIER DIODE

WWAN@

RM3 0_0402_5%

1 2

LM1

@ LM1

@

1

4

WCM2012F2S-900T04_0805

1 2

RM4 0_0402_5%

WWAN@

Primary Power Aux Power

Peak Normal Normal

1000 750

330

500

LPC_LFRAME# <16,26> LPC_LAD3 <16,26> LPC_LAD2 <16,26> LPC_LAD1 <16,26> LPC_LAD0 <16,26>

SB_GPIO26#<16>

PLT_RST#<13,16,20,26>

250

375

DM3

CH751H-40PT_SOD323-2

DM4

CH751H-40PT_SOD323-2

SC1H751H010

SCHOTTKY BARRIER DIODE

D

+3VS

WWAN@

12

RM14

DM1

DM2

2

3

250 (Wake enable) 5 (Not wake enable)

RM14 10K_0402_5%

10K_0402_5%

WWAN_RST#

21

2

USB20_N5_RUSB20_N5

3

NA

+3V_WLAN

12

RM15

RM15 2K_0402_1%~D

2K_0402_1%~D

WLAN_RST#

21

D

E

SIM Card

UM22

@UM22

@

UIM_RESET

UIM_CLK

33P_0402_50V8J

CM10

1

@

2

UIM_VPP UIM_DATA

USB20_P6_R USB20_N6_R

USB20_P6<18>

USB20_N6<18>

BT_DET#<26>

BT_OFF#<26>

BT_RADIO_OFF#<26>

BT_DET# COEX2_WLAN_ACTIVE BT_OFF# USB20_P6_R

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

1

2

3

33P_0402_50V8J

CM11

1

SRV05-4.TCT_SOT23-6~D

2

JSIM1

CONN@JSIM1

CONN@

4

GND

5

VPP

6

I/O

7

DET

TAITW_PMPAT6-06GLBS7N14N0

6

5

4

VCC RST CLK

GND GND

SP07000FV00

Place close to JBT1 for AMD

AMD@

1

2

LO3

@ LO3

@

1

4

JBT1

112 334 556 778 9910 111112 131314

GND15GND

CIS LINK OK

AMD@

CO9

0.1U_0402_16V7K

2

3

CONN@JBT1

CONN@

2 4 6 8 10 12 14

16

E

AMD@

CO8

RO14 0_0402_5%RO14 0_0402_5%

1 2

USB20_P6 USB20_P6_R

1

4

WCM2012F2S-900T04_0805

1 2

RO15 0_0402_5%RO15 0_0402_5%

Bluetooth

TYCO_3-2041112-4~D

SP01000WS0L

Compal Electronics, Inc.

WLAN/WWAN/BT

LA-6132P

CM12

@

2

3

1

2

+UIM_PWR

1 2 3

8 9

1

2

BT_ACTIVE

USB20_N6_RBT_RADIO_OFF#

28 45Tuesday, May 04, 2010

UIM_VPP

+UIM_PWR

UIM_DATA

33P_0402_50V8J

CM13

1

@

2

CM14

1

2

UIM_RESET UIM_CLK

0.1U_0402_16V7K

USB20_N6_RUSB20_N6

of

1U_0603_10V6K

WWAN@

+3VS

1.0

5

4

3

2

Pleace near HDD CONN (JHDD1)

+5VS

1

HDD Connector

1

JHDD1

CONN@ JHDD1

CONN@

D D

23

GND

24

GND

SUYIN_127043FR022G196ZR

C C

DC010005A00

GND

GND GND GND

GND

DAS/DSS

GND

V33 V33 V33

V12 V12 V12

1 2

A+

3

A-

4 5

B-

6

B+

7

8 9 10 11 12 13 14

V5

15

V5

16

V5

17 18 19 20 21 22

Near CONN side.

SATA_SRX_DTX_N0_R SATA_SRX_DTX_P0_R

+3VSHDD

+5VS

40 mils

CH5 0.01U_0402_16V7KCH5 0.01U_0402_16V7K

1 2

CH6 0.01U_0402_16V7KCH6 0.01U_0402_16V7K

1 2

SATA_STX_DRX_P0 <17> SATA_STX_DRX_N0 <17>

SATA_SRX_DTX_N0 <17> SATA_SRX_DTX_P0 <17>

1

CH2

CH1

+3VS +3VSHDD

CH2

2

10U_0805_10V4Z

0.1U_0402_16V7K

CH3

2

PJP65

JUMP_43X118

112

Open

1

CH4

2

0.1U_0402_16V7K

2

10U_0805_10V4Z

1

2

1

2

1000P_0402_50V7K

0.1U_0402_16V7K

@CH8

@

@CH7

@

1

CH8

CH7

2

0.1U_0402_16V7K

@CH9

@

1

CH9

2

FAN Control circuit

+FAN_POWER

40mil

1

B B

A A

5

CF1

10U_1206_16V4Z

EN_DFAN1<26>

1

CF2

2

EN_DFAN1

4

+5VS

1000P_0402_50V7K

CF3 10U_1206_16V4ZCF3 10U_1206_16V4Z

1 2

UF23

1

VEN

2

VIN

3

VO

4

VSET

RT9027BPS SO 8P

8

GND

7

GND

6

GND

5

GND

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

FAN_SPEED1<26>

3

+3VS

12

RF1

RF1 10K_0402_5%

10K_0402_5%

1

CF4

0.01U_0402_16V7K

2

+FAN_POWER

2

CONN@

JFAN1

40mil

JFAN1

1

2

3

4

GND

5

GND

ACES_85204-0300N

SP02000JR00 CIS SYMBOL OK

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

FAN/HDD

FAN/HDD LA-6132P

LA-6132P

29 45Tuesday, May 04, 2010

1

1.0

of

5

4

3

2

1

DC/DC Interface

RTCVREF +COINCELL

+RTC_CELL+COINCELL

@

RZ28

1 2

0_0402_5%

2

D D

BAT54CW_SOT323-3~D

3

DZ3

+RTC_CELL

1

CZ24

CZ24 1U_0603_10V6K

1U_0603_10V6K

2

0_0402_5%

+3VALW to +3LAN Transfer

SUSP#<26,35,40,41,43>

1 2

RZ8 10K_0402_5%RZ8 10K_0402_5%

B+_BIAS

470K_0402_5%

2

G

W=40mils

+3VALW

1U_0603_10V6K

1

2

12

RZ13

13

D

QZ13

QZ13 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

CZ11

EN_WOL

QZ11

SI3456BDV-T1-E3 1N TSOP6

D

6

S

45 2 1

G

3

1 2

2200P_0402_50V7K

12

RZ14

1.5M_0402_5%

CZ15

W=40mils

22U_0805_6.3V6M~D

1

CZ9

CZ10

2

@

+3V_LAN

0.1U_0402_16V7K

CZ12

C C

EN_WOL#<17,26>

B B

SB00000N90L (NTMS4920NR2G)

+5VALW

12

RZ7

RZ7 100K_0402_5%

100K_0402_5%

SUSP

13

D

2

G

S

SUSP <38>

SSM3K7002FU_SC70-3

QZ6

SUSP

B+_BIAS +5VALW

12

RZ3

RZ3 100K_0402_5%

100K_0402_5%

5V_RUN_ENABLE

13

D

QZ5

SSM3K7002FU_SC70-3

2

G

S

B+_BIAS

12

RZ10

RZ10 100K_0402_5%

100K_0402_5%

3.3V_RUN_ENABLE

13

D

QZ10

2

SSM3K7002FU_SC70-3

G

S

B+_BIAS

12

RZ15

RZ15 100K_0402_5%

100K_0402_5%

1.5V_RUN_ENABLE

13

D

QZ14

2

SSM3K7002FU_SC70-3

G

S

+5VRUN Source

QZ3

NTMS4107NR2G_SO8~D

8 7

5

4

12

1

CZ4

RZ29

@

CZ4

0.1U_0402_25V6

2

390K_0402_5%

+3.3V_RUN Source

QZ8

NTMS4107NR2G_SO8~D

8 7

5

4

12

RZ30

1

2

2M_0402_5%~D

+1.5V_RUN Source

QZ12

SI4634DY-T1-E3_SO8~D

8 7 6 5

4

12

RZ31

1

2

2M_0402_5%~D

+5VS

1 2 36

CZ2

10U_0805_10V4Z

CZ2

10U_0805_10V4Z

1

2

1 2 36

10U_0805_10V4Z

1

CZ5

2

CZ8

0.01U_0402_25V7K

rDS=5.2mOHM

1 2 3

CZ18

CZ19

0.1U_0402_25V6

12

RZ6

RZ6 20K_0402_5%

20K_0402_5%

+3VS+3VALW

12

@

RZ12

RZ12 20K_0402_5%

20K_0402_5%

+1.5VS+1.5V

10U_0805_10V4Z

1

2

12

RZ16

20K_0402_5%

Discharg Circuit

+1.5VS +3VS+5VS

2

G

12

@

RZ23

RZ23 1K_0402_5%

1K_0402_5%

+1.5V_RUN_CHG

SSM3K7002FU_SC70-3

@

QZ19

13

D

S

12

@

RZ19

RZ19 1K_0402_5%

1K_0402_5%

+5V_RUN_CHG

SSM3K7002FU_SC70-3

@

QZ18

13

D

2

G

S

A A

S

2

G

12

RZ24

RZ24 39_0402_5%

39_0402_5%

+3.3V_RUN_CHG

SSM3K7002FU_SC70-3

13

D

S

+1.1VS

@

12

RZ20

RZ20 39_0402_5%

39_0402_5%

+1.1V_RUN_CHG

SSM3K7002FU_SC70-3

@

QZ20

SUSPSUSPSUSPSUSP SUSP

@

13

D

2

G

S

QZ21

+0.75VS

2

G

12

RZ18

RZ18 22_0603_5%

22_0603_5%

+DDRVTT_CHG

SSM3K7002FU_SC70-3

QZ23

13

D

S

2

G

B+_BIAS

12

RZ21

RZ21 470K_0402_5%

470K_0402_5%

1.1V_RUN_ENABLE

13

D

QZ16

QZ16 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

+1.1V_RUN Source

QZ15

+1.1VALW

SI4634DY-T1-E3_SO8~D

8 7 6 5

12

RZ32

2M_0402_5%~D

rDS=5.2mOHM

1 2 3

4

1

CZ21

0.1U_0402_25V6

2

10U_0805_10V4Z

1

CZ20

2

+1.1VS

12

RZ25

RZ25 20K_0402_5%

20K_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

DC/DC (Power control)

LA-6132P

30 45Tuesday, May 04, 2010

1

1.0

of

A

B

C

D

E

RZ26

100K_0402_5%

+3VALW

12

1

CZ23

2

1000P_0402_50V7K

ON/OFF_EC# <26> 51ON# <23,34>

12

DZ2

RLZ20A_LL34

MB_Power On/Off SW

JPWR1

H19

H3

H2

H_2P8H3H_2P8

H_2P8H2H_2P8

H10

H10 H_3P2

H_3P2

H13

H13 H_2P2

H_2P2

H15

H15 H_4P0

H_4P0

1

H11

H11 H_3P2

H_3P2

1

H16

H16 H_4P0

H_4P0

1

1 1

H5

H6

H_2P8H5H_2P8

H_2P8H6H_2P8

1

H12

H12 H_3P2

H_3P2

1

@

H7 H_2P8H7H_2P8

1

FD2@FD2

FD1@FD1

@

1

ZZZ

PCB

DAZ0DD00200 (DA80000I510)

H8 H_2P8H8H_2P8

1

H9 H_2P8H9H_2P8

FD3@FD3

@

1

H19 H_2P8

H_2P8

1

@

1

FD4@FD4

1

CONN@

ACES_88514-0401

SP01000R400

CIS SYMBOL OK

+3VALW

1

CZ25

0.1U_0402_25V6

2

Place closed to JPWR1

JPWR1

1 2 3 4

GND GND

ON/OFFBTN# LID_SW#

+3VALW

DZ1

1 2 3 4

5 6

2

3

1

LID_SW# ON/OFFBTN#

DZ4

PJSOT24C_SOT23-3

LID_SW# <26>

CZ22

0.1U_0402_25V6

1

2

DZ1

2

1

3

DAN202UT106_SC70-3

QZ24

QZ24 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

EC_ON<26>

RZ27

10K_0402_5%

1 2

13

D

2

G

S

(For ESD request)

H17

H17 H_3P4x3P9

2 2

H_3P4x3P9

H18

H18 H_3P4

H_3P4

1

Vendor pin defined

1. VDD

2. PS2CLK

3. PS2DATA

4. GND

+5VS

CE15

1U_0402_6.3V6K

Touch/B Connector

TP_CLK<26>

2

TP_DATA<26>

1

3

DE1

@

PJDLC05_SOT23-3

1

2

1

CE16

2

100P_0402_50V8J

1

CE17

2

100P_0402_50V8J

CONN@

JTP1

1

VCC

2

NC

3

Num_Lock

4

GND

5

GND

6

GND

ACES_88514-0401

SP01000R400

3 3

System SPI Flash ROM (16Mb)

CE18

+3VALW

1

2

0.1U_0402_16V7K

D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SW/ROM/TP/PWR/SCREW

LA-6132P

31 45Tuesday, May 11, 2010

E

of

1.0

UE24

FSEL#SPICS#

FSEL#SPICS#<26>

FWR#SPI_SI<26>

FRD#SPI_SO<26>

SPI_CLK<26>

Close KB926 pin 126

4 4

A

FSEL#SPICS# FWR#SPI_SI FRD#SPI_SO

SPI_CLK SPI_CLK_R

33_0402_5%~D

12

RE30

B

1

CE19

CE19 33P_0402_50V8J

33P_0402_50V8J

2

+3VALW

FRD#SPI_SO

1 2

RE28

10K_0402_5%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

UE24

1

CS#

VCC

2

SO

HOLD#

3

WP#

SCLK

4

GND

MX25L1605DM2I-12G_SO8

8 7 6 5

SI

RE29 10K_0402_5%RE29 10K_0402_5%

1 2

SPI_CLK_R

FWR#SPI_SI

SA00002TO00

CIS symbol need apply

C

5

4

3

2

1

Power block

D D

Battery OVP

Page 33

Turn Off

DC IN

Input Switch

Page 34

B+

CPU OTP

Page 33

Turn Off

+3VALWP TDC= 5.47A Ipeak= 7.81A +5VALWP TDC= 6.22A Ipeak= 8.88A

TPS51427

MAINPWON

Page 36

CHARGER CC:0A~3A CV:14.8V(8cell)

C C

ISL6251AHAZ-T

Page 35

Battery

B B

+3VALW for Vin +5VALW for VCNTL

+1.8VP TDC= 0.87A Ipeak= 1.25A APL5912

+3VS for Vin

+2.5VDDAP TDC= 0.18A Ipeak= 0.25A APL5508

+1.1VALWP TDC= 6.7A Ipeak= 9.55A TPS51218DSCR

+1.5VP TDC= 6.95A Ipeak= 9.93A TPS51218DSCR

SUSP#

Page 40

Page 41

SYSON

Page 37

SYSON

Page 39

+1.5VP for Vin +3VALW for VCNTL

+CPU_CORE

+0.75VSP TDC= 0.35A Ipeak= 0.5A APL5331

SUSP

Page 38

TDC=12.6A

VR_ON

Ipeak=18A +VDDNBP(0.9v)

TDC=2.8A

+1.5V for Vin +5VALW for VCNTL

+CPU_VDDRP TDC= 1.05A Ipeak= 1.5A APL5912

Page 41

SUSP#

Ipeak=4A

A A

5

ISL6265AHRTZ-T

Page 42

4

3

+NB_COREP TDC= 8.4A Ipeak= 12A TPS51218DSCR

2

SUSP#

Page 43

Title

POWER BLOCK DIAGRAM

Size Document Number Rev

Date: Sheet

Date: Sheet of

LA-6132P

1

32 45Tuesday, April 06, 2010

of

32 45Tuesday, April 06, 2010

of

32 45Tuesday, April 06, 2010

A

B

C

D

1

@

PD1

PJSOT24C_SOT23-3

BATT+

1 1

PC1

12

BATT+

12

100P_0402_50V8J

PJPB1 battery connector

SMART

Battery:

1.BAT+

2.BAT+

3.ID

4.B/I

2 2

5.TS

PL1

1 2

SMB3025500YA_2P

PC2

0.01U_0402_25V7K

BATT++

12

PC3

1000P_0402_50V7K

PJBATT

ME@ PJBATT

ME@

1

2

3

4

5

6

7

7 GND GND

8

9

10 11

SUYIN_200275MR009G186ZL

6.SMD

7.SMC

12

PC4

100P_0402_50V8J

BATT++

+3VALWP

PR1

PR1 47K_0402_5%

47K_0402_5%

1 2

PR9

1 2

100_0402_1%

PR12

1 2

100_0402_1%

3S <35>

PJSOT24C_SOT23-3

2

3

1K_0402_1%~D

EC_SMB_DA1 <26>

EC_SMB_CK1 <26>

PR5

1

PD2

@ PD2

@

PJSOT24C_SOT23-3

2

3

PJSOT24C_SOT23-3

CPU OTP

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C

VL VS

Place clsoe to EC pin

PR2

BATT_TEMP

1 2

1K_0402_1%~D

12

PR7

1 2

6.49K_0402_1%~D

PC5

@ PC5

@

0.1U_0402_16V7K

1 2

BATT_TEMP <26>

+3VALWP

PC6

1000P_0402_50V7K

12

PR3

10.7K_0402_1%~D

PR8

61.9K_0402_1%

OTP_IN OTP_IN+

12

61.9K_0402_1%

1 2

PR10

1 2

VL

150K_0402_1%

12

PH1

PH1 100K_0402_1%_TH11-4H104FT

100K_0402_1%_TH11-4H104FT

150K_0402_1%

PR11

PR4

1 2

147K_0402_1%~D

OTP_IN-

12

PC7

PC7 1U_0603_10V6K~D

1U_0603_10V6K~D

3 2

8

P

+

-

G

PU1A

4

LM358ADR_SO8

0

1 2

OTP_OUT

1

PC400

0.1U_0603_25V7K

PD3

1 2

1SS355TE-17_SOD323-2

VL

PR6

205K_0402_1%~D

1 2

MAINPWON <34,36>

8.GND

9.GND

COIN RTC Battery

PJRTC

ME@ PJRTC

ME@

2

4

2

NC2

1

PQ1

TP0610K-T1-E3_SOT23-3

PR14

1 2

B+

100_0805_5%~D

+5VALW

3 3

PR17

220K_0402_5%

PC11

0.1U_0603_25V7K

PC11

12

1 2

12

PR20

1 2

TP0610K-T1-E3_SOT23-3

PR15

1 2

470K_0402_5%~D

PD4

PD4 1SS355TE-17_SOD323-2

1SS355TE-17_SOD323-2

2

G

220K_0402_5%

13

2

13

D

PQ2

RHU002N06_SOT323-3

S

PC8

0.1U_0805_25V7M~D

1 2

B+_BIAS

3

1

NC1

ACES_85204-0200N

+COINCELL

VS

12

PC9

PU1B

LM358ADR_SO8

PR18

BATT_OVP<26>

10K_0402_1%~D

12

8

5

P

+

7

0

6

-

G

4

BATT+

12

PR13

PR13 453K_0402_1%~D

453K_0402_1%~D

12

PR16

PR16 499K_0402_1%

499K_0402_1%

0.01U_0402_25V7K

12

PR19

120K_0402_1%

12

PC10

0.01U_0402_25V7K

LI-3S :13.5V----BATT-OVP=1.5V

BATT-OVP=0.111*BATT+

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/2/6 2010/2/6

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN / OTP

LA-6132P

D

33 45Tuesday, May 04, 2010

of

0.2

A

ADPIN

PL2

DC_IN_S1

ME@

PJDCIN

1 1

2 2

PJDCIN

1

2

3

4

5

6

7

GND

8

GND

ACES_88299-0600

VIN

RLS4148_LL34-2

PD6

12

PC13

PC13 1000P_0402_50V7K

1000P_0402_50V7K

PL3

FBM-L11-160808-601LMT 0603~D

PR29

1 2

1K_1206_5%

PR31

12

PR31

1 2

1K_1206_5%

PR34

1 2

1K_1206_5%

PR35

1 2

1K_1206_5%

DTC115EUA_SC70-3

ACOFF<26,35>

PQ6

DOCK_PSID

12

PR36

PR38

100K_0402_5%

13

2

1 2

SMB3025500YA_2P

12

PC14

PC14 100P_0402_50V8J

100P_0402_50V8J

PQ3

PQ3 TP0610K-T1-E3_SOT23-3

TP0610K-T1-E3_SOT23-3

100K_0402_5%

2

PL2

2

12

PR40

PR40 100K_0402_5%

100K_0402_5%

13

B

12

PC15

PC15 100P_0402_50V8J

100P_0402_50V8J

13

PQ7

PQ7 DTC115EUA_SC70-3

DTC115EUA_SC70-3

Vin Detector Max. typ. Min.

VIN

L-->H 18.234 17.841 17.449 H-->L 17.597 17.210 16.813

12

PC16

PC16 1000P_0402_50V7K

1000P_0402_50V7K

B+

ACIN

Precharge detector

Min. typ. Max. H-->L 14.589V 14.84V 15.243V L-->H 15.562V 15.97V 16.388V

BATT ONLY

Precharge detector

Min. typ. Max. H-->L 6.138V 6.214V 6.359V L-->H 7.196V 7.349V 7.505V

PC18

DOCK_PSID

12

0.1U_0402_16V7K

2

3

@

1

PD8

PD8 SM24_SOT23

SM24_SOT23

C

VIN

12

PR23

82.5K_0402_1%~D

1 2

22K_0402_1%

12

PR27

20.5K_0402_1%~D

PR39

100K_0402_1%

PR42

15K_0402_1%~D

2200P_0402_50V7K~D

PR26

12

PC19

1000P_0402_50V7K

1 2

@

PC12

@ PR21

@

1 2

56K_0402_5%~D

PR22

1 2

1M_0402_1%~N

VS

PU4A

3 2

PR30

10K_0402_5%

8

+

-

4

12

PQ4

2

B

N40N41 N35

FDV301N_NL_SOT23-3~D

PR21

12

PC17

0.01U_0402_25V7K

P

1

O

G

LM393DR_SO8

RTCVREF

3.3V

@

PR32

1 2

0_0402_5%

D

S

D

S

1 3

G

2

C

PQ5

PQ5 MMST3904-7-F_SOT323~D

MMST3904-7-F_SOT323~D

E

3 1

PD5

RLZ4.3B_LL34

1 2

33_0402_5%~D

PR37

VIN

12

PR24

10K_0402_5%

12

+5VALW

12

PR28

PR28 10K_0402_5%

10K_0402_5%

2

3

PD7

1

DA204U_SOT323~D

+5VALW

12

PR41

D

PR25

1 2

1K_0402_1%~D

10K_0402_1%~D

PR43

@

1 2

10K_0402_1%~D

ACIN

+3VALW

PD9

@PD9

@

PR33

2.2K_0402_5%~D

1 2

+5VALW

ACIN <18,26>

PACIN <35>

PS_ID <26>

2

3

1

DA204U_SOT323~D

PSID_DISABLE# <26>

VL

VIN

3 3

PD11

BATT+

CHGRTCP

51ON#<23,31>

4 4

A

RLS4148_LL34-2

PR48

1 2

200_0603_5%

100K_0402_1%

PR51

1 2

22K_0402_1%

RTCVREF

3.3V

12

PC25

10U_0805_10V4Z

12

PR50

12

PC20

0.22U_0603_25V7K

PU5

PU5 APL5156 SOT89 3P

APL5156 SOT89 3P

3

OUT

GND

1

PQ8

TP0610K-T1-E3_SOT23-3

N1

2

IN

N2

2

12

PR54

PR54 200_0603_5%

200_0603_5%

12

PC26

PC26 1U_0805_25V4Z

1U_0805_25V4Z

68_1206_5%

13

PR45

PD10

RLS4148_LL34-2

1 2 12

12

PR46

PR46 68_1206_5%

68_1206_5%

12

PC21

0.1U_0603_25V7K

B

12

PR49

100K_0402_1%

PD12

MAINPWON<33,36> ACON<35>

VS

2 3

RB715F_SOT323-3

1

12

PC22

0.1U_0603_25V7K

LM393DR_SO8

RTCVREF

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/2/6 2010/2/6

Compal Secret Data

Deciphered Date

C

VS

7

O

PU4B

34K_0402_1%

PR44

2.2M_0402_5%

8

5

P

+

6

-

G

4

PR55

12

PC23

1000P_0402_50V7K

12

PR52

PR52 191K_0402_1%

191K_0402_1%

PRG++

PQ9

13

D

RHU002N06_SOT323-3

2

G

S

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

B+

12

PR47

PR47 499K_0402_1%

499K_0402_1%

12

PC24

12

PC24

0.01U_0402_25V7K

PACIN <35>

+5VALW

34 45Tuesday, May 04, 2010

PR53

499K_0402_1%

PR56

47K_0402_5%

13

PQ10

PQ10 DTC115EUA_SC70-3

DTC115EUA_SC70-3

2

Compal Electronics, Inc.

DCIN & DETECTOR

LA-6132P

D

0.2

of

A

B

C

D

Iada=0~3.34A(65W)

ADP_I = 19.9*Iadapter*Rsense

PQ11

AO4407A_SO8

PQ16

2

13

PQ17

PQ17 DTC115EUA_SC70-3

DTC115EUA_SC70-3

PACIN

1 2

ACON

ACOFF

AO4407A_SO8

8 7

5

1 3

PR77

22K_0402_5%

2

4

12

PC31

150K_0402_1%

13

1 2 36

0.1U_0603_25V7K

PR70

2

G

PQ25

PQ25 DTC115EUA_SC70-3

DTC115EUA_SC70-3

VIN

1 1

12

PR58

PR58 47K_0402_1%

47K_0402_1%

DTA144EUA_SC70-3

2

13

D

2

G

PQ21

S

2 2

3 3

S

RHU002N06_SOT323-3

PACIN<34>

ACON<34> IREF<26>

ACOFF<26,34>

CP mode

PQ12

P2

SI4459ADY-T1-GE3_SO8

1 2 3 6

12

PR59

PR59 200K_0402_1%

200K_0402_1%

6251VDD

12

13

D

PQ23

PQ23 RHU002N06_SOT323-3

RHU002N06_SOT323-3

S

4

PR67

1 2

47K_0402_5%

3S<33>

PR80

150K_0402_1%

100K_0402_1%

8 7

5

PC32

1 2

5600P_0402_25V7K

1SS355TE-17_SOD323-2

FSTCHG<26>

13

2

PC39

1 2

0.01U_0402_25V7K

12

PR81

6251VREF

CP = 90%*Iadapter (rating); CP = 3.003A

PR57

P3

PQ19

PQ19 DTC115EUA_SC70-3

DTC115EUA_SC70-3

1 2

ADP_I<26>

12

PC43

0.01U_0402_25V7K

PR83

1 2

11.5K_0402_1%

0.02_2512_1%

1 2

12

PR62

1 2

PD15

PR66

10K_0402_5%

12

PC34

1 2

0.1U_0402_16V7K

PC38

1 2

6800P_0402_25V7K

PR73

PR73 10K_0402_1%

10K_0402_1%

PC41

1 2

0.1U_0402_16V7K

12

PR84

2.74K_0402_1%~D

PR57

4 3

PQ14 TP0610K-T1-E3_SOT23-3PQ14 TP0610K-T1-E3_SOT23-3

100K_0402_1%

6251VDD

12

PR68

100K_0402_1%

PR75

1 2

100_0402_1%

6251VREF

2

6251_EN

6251ACLIM

12

PC33

2.2U_0603_6.3V6K

B+

PQ17toRP9

13

PR64

12

100K_0402_1%

PU6

1

VDD

2

ACSET

3

EN

4

CELLS

5

ICOMP

6

VCOMP

7

ICM

8

VREF

9

CHLIM

10

ACLIM

11

VADJ

12

GND

ISL6251AHAZ-T_QSOP24

PR60

1 2

10_1206_5%

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

CSIN CSIP

DCIN

PQ15

13

DTC115EUA_SC70-3

24

23

22

21

20

19

18

17

16

15

14

13

PD14

1

2

RB715F_SOT323-3

PC35

DCIN

0.1U_0603_25V7K

BST_CHG BST_CHGA

6251VDDP

DL_CHG

PC36

0.047U_0603_16V7K

1 2

PR71 20_0603_5%PR71 20_0603_5%

PR72 20_0603_5%PR72 20_0603_5%

PC40

0.1U_0603_25V7K

1 2

LX_CHG

DH_CHG

PR79

1 2

2.2_0603_5%

1 2

12

1 2

PR74

PC47

4.7U_0805_6.3V6K

FSTCHG

2

SUSP#

3

SUSP#<26,30,40,41,43>

PR69

1 2

20_0603_5%

12

2.2_0603_5%

12

0.1U_0603_25V7K

PD17

PD17 RB751V-40TE17_SOD323-2

RB751V-40TE17_SOD323-2

PR82

1 2

4.7_0603_5%

PC42

6251VDD

12

PC27

10U_1206_25V6M

CSON

CSOP

12

PC28

PC29

10U_1206_25V6M

SI4128DY-T1-GE3

12

PC30

0.1U_0603_25V7K

578

PQ24

2200P_0402_25V7K

DTC115EUA_SC70-3

PQ22

SI4128DY-T1-GE3

3 6

241

10UH_PCMB063T-100MS_4A_20%

12

PR78

4.7_1206_5%

12

PC44

PC44 680P_0603_50V_NPO

680P_0603_50V_NPO

3 6

241

AO4407A_SO8

1 2 3 6

PR63

10K_0402_1%

PQ18

PL4

1 2

PQ13

4

1 2

13

8 7

5

PR61

1 2

47K_0402_1%

1 2

1SS355TE-17_SOD323-2

PD16

1SS355TE-17_SOD323-2

1 2

2

0.02_2512_1%

CHG

1 2

PD13

PC37

0.1U_0603_25V7K

PR76

VIN

ACOFF

1 2

200K_0402_1%

12

4 3

D

S

PR65

PQ20

13

RHU002N06_SOT323-3

PACIN

2

G

12

PC45

10U_1206_25V6M

VIN

PC46

BATT+

12

10U_1206_25V6M

Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)

Vaclim=2.39*((2.74K//152K)/((2.74K//152K)+(11.5K//152K)))

CC=0.6~3.3A IREF=1*Icharge IREF=0.6V~3.3V

CHGVADJ CV mode

0V

CHGVADJ<26>

3.99V per cell

PR85

1 2

18.2K_0402_1%

PR86

31.6K_0402_1%

12

1.91V

3.3V

4 4

-

A

4.2V per cell

4.35V per cell

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2010/2/62009/2/6

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CHARGER

LA-6132P

D

35 45Tuesday, May 04, 2010

0.2

of

5

4

3

2

1

TPS51427_B+

PR87

0_0805_5%~D

PJP5

2

B+

12

D D

+3VALWP

C C

B B

PC49

PC50

1000P_0402_50V7K

12

PC64

0.1U_0402_10V7K~D

JUMP_43X118

12

1000P_0402_50V7K

PC65

PJP6

112

PJP7

112

JUMP_43X118

1

+

2

330U_D3L_6.3VM_R25M

@

PC95

0.1U_0603_25V7K

2

12

PR92

0_0402_5%

@ PR94

@

10K_0402_5%

1 2

1SS355TE-17_SOD323-2

+3VALW+3VALWP

12

PC53

PC52

PC51

PR94

PC52

0.1U_0603_25V7K

4.7U_0805_25V6-K~D

PL6

VS

PD19

PL6

4.7_1206_5%

680P_0402_50V7K~D

GLZ5.1B_LL34-2

1 2

12

3.3UH_PCMB064T-3R3MS_7A_20%

12

PC54

4.7U_0805_25V6-K~D

12

PR88

PC67

PD18

2200P_0402_50V7K~D

241

1 2

100K_0402_1%

200K_0402_1%

MAINPWON<33,34>

PR98

786

123

12

578

PQ26

PQ26 AO4466_SO8

AO4466_SO8

3 6

5

PQ29

PQ29 AO4710_SO8

AO4710_SO8

4

PR99

1 2

PR104

806K_0603_1%~D

PR106

0_0402_5%

0.22U_0603_25V7K

0.22U_0603_25V7K PC72

PC72

1 2

VL

1 2

12

+3VALWP Thermal Design Current=5.47A Peak Current=7.81A OCP min=10.15A Fsw=300KHZ Delta I=2.7692 A

A A

OCP setting resistor: PR101

5

2

4

PQ30

PQ30 TP0610K-T1-E3_SOT23-3

TP0610K-T1-E3_SOT23-3

1 3

0_0805_5%~D

1 2

VL

PQ27

AO4466_SO8

PR90

0_0603_5%

PC66

0.1U_0603_25V7K

1 2

0_0402_5%

@ PR107

@

1 2

47K_0402_5%

12

PC74

0.047U_0603_16V7K

0.1U_0603_25V7K

DH3

BST3A

12

LX3

DL3

FB3

VL

2VREF_TPS51427

PC71

1 2

0.22U_0603_10V7K

@

PR102

PR103

1 2

PR107

12

PC75

@PC75

@

0.047U_0402_16V7K~D

PC59

1 2

PU2

33

TP

26

DRVH2

24

VBST2

25

LL2

23

DRVL2

30

VOUT2

32

REFIN2

1

VREF2

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

0_0402_5%

1 2

PC73

2VREF_TPS51427

PC60

1 2

3

6

VIN

V5FILT

TONSE

VREF3

2

5

12

PR105

1 2

0_0402_5%

1U_0603_10V6K~D

2VREF_TPS51427

12

PC61

1U_0603_10V6K~D

7

19

LDO

V5DRV

15

DRVH1

17

VBST1

16

LL1

18

DRVL1

22

PGND

10

VOUT1

11

FB1

9

VSW

29

SKIPSEL

28

PGOOD2

13

PGOOD1

12

TRIP1

31

TRIP2

GND

TPS51427_QFN32_5X5

21

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K PC62

PC62

1U_0603_10V6K~D

1 2

DH5

BST5A

0_0603_5%

0.1U_0603_25V7K

LX5

DL5

FB5

1 2

0_0402_5%

ILM1

ILIM2

PR91

PR97

PC63

@

PR96

12

1 2

12

0_0402_5%

AO4466_SO8

AO4710_SO8

PR100

12

324K_0402_1%~D

PR101

12

280K_0402_1%

+5VALWP Thermal Design Current=6.22A Peak Current=8.88A OCP min=11.55A Fsw=400KHZ Delta I=2.82 A

OCP setting resistor: PR100

Security Classification

2009/2/6 2010/2/6

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/2/6 2010/2/6

3

Compal Secret Data

Deciphered Date

2

PQ28

578

3 6

241

786

5

4

123

VL

Title

Size Document Number Rev

Custom

Custom Date: Sheet

Date: Sheet

TPS51427_B+

12

PC56

PC55

4.7U_0805_25V6-K~D

PL5

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

12

PR89

4.7_1206_5%

12

PC68

680P_0402_50V7K~D

+3VALW

12

PR119

10K_0402_1%~D

+5VALWP

Compal Electronics, Inc.

+5VALWP/+3VALWP

LA-6132P

12

PC58

PC57

2200P_0402_50V7K~D

PR93

61.9K_0402_1%

1 2

PC96

PR95

@

1 2

10K_0402_5%

POK <37>

PJP8

2

112

JUMP_43X118

1

12

0.1U_0603_25V7K

1

+

PC69

2

0.1U_0603_25V7K

36 45Tuesday, May 04, 2010

+5VALWP

12

PC70

0.1U_0402_10V7K~D

330U_D3L_6.3VM_R25M

0.1U_0402_10V7K~D

+5VALW

0.1

of

A

1 1

B

C

+1.1VALWP_B+

2

PJP10

112

JUMP_43X118

D

B+

PC78

12

PC79

10U_1206_25V6M

PC80

@

12

10U_1206_25V6M

12

PC76

2200P_0402_50V7K~D

12

PC77

0.1U_0603_25V7K

+1.5VP

12

@

PR120

0_0402_5%

2 2

PR110

1 2

68.1K_0402_1%

PC82

68.1K_0402_1%

12

PR111

POK<36>

3 3

1 2

0_0402_5%

@

0.1U_0402_16V7K

PR114

1 2

20K_0402_1%~D

PC97

@ PC97

@

1 2

0.1U_0603_25V7K

PR108

@ PR108

@

100K_0402_1%

PG_1.1VALWP

TRIP_1.1VALWP EN_1.1VALWP FB_1.1VALWP RF_1.1VALWP

12

PR113

PR113 470K_0402_5%~D

470K_0402_5%~D

PR115

11.5K_0402_1%

PU7

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51218DSCR_SON10_3X3~D

12

VBST

DRVH

V5IN

DRVL

PC81

PR109

1 2

2.2_0603_5%

BST_1.1VALWP

10

UG_1.1VALWP

9

SW_1.1VALWP

8

SW

TP

7 6 11

V5IN_1.1VALWP LG_1.1VALWP

PC81

1 2

0.22U_0603_25V7K

+5VALW

1

PC83

PC83 1U_0603_6.3V6M~D

1U_0603_6.3V6M~D

2

8

D6D5D7D

PQ31

PQ31 FDS6298_SO8~D

FDS6298_SO8~D

4

G

S

3

2

1

786

5

PQ32

PQ32 SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8

4

123

12

PR112

4.7_1206_5%

12

PC88

PC88 680P_0603_50V_NPO

680P_0603_50V_NPO

PL7

1 2

1UH_PCMC063T-1R0MN_11A_20%

12

PC84

0.1U_0402_10V7K~D

+1.1VALWP

1

PC85

2

10U_0805_6.3V6M~D

1

+

PC86

PC86 330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

PJP11

PJP11 JUMP_43X118

JUMP_43X118

2

112

PJP12

PJP12 JUMP_43X118

JUMP_43X118

2

112

+1.1VALWP

+1.1VALW

+1.1VALWP Thermal Design Current=6.7A Peak Current=9.55A OCP min=12.42A Fsw=290KHZ

Delta I=3.5791A L/S MOS Rds(on)=5.5m (Typ) ; 6.7m (Max)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2008/6/05

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

+1.1VALWP

Tuesday, May 04, 2010

LA-6132P

D

of

37 45

of

37 45

of

37 45

0.2Custom

A

B

C

D

+1.5VP

1

PJP13

1

JUMP_43X79

2

PC89

PQ33

2

G

12

0.1U_0402_16V7K

2

1 2

13

D

S

+0.75VSP

PR116

PR118

12

1K_0402_1%~D

12

1K_0402_1%~D

PJP14

2

JUMP_43X118

PC91

112

12

1 1

4.7U_0805_6.3V6K

SSM3K7002F_SC59-3

PR117

SUSP<30>

2 2

1 2

10K_0402_1%

SSM3K7002F_SC59-3

PC92

PU8

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

12

PC93

10U_0603_6.3V6M~D

0.1U_0402_16V7K

+0.75VS

NC NC NC TP

+0.75VSP

6 5 7 8 9

+3VALW

12

PC90

1U_0603_10V6K~D

+0.75VSP Thermal Design Current=0.35A Peak Currnet=0.5A OCP min=0.65A

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2008/6/05

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

+0.75VSP

Tuesday, May 04, 2010

LA-6132P

D

of

38 45

of

38 45

of

38 45

0.1Custom

5

D D

4

3

+1.5VP_B+

2

PJP17

2

112

JUMP_43X118

1

B+

PC101

12

PC102

10U_1206_25V6M

12

PC99

2200P_0402_50V7K~D

PC100

12

0.1U_0603_25V7K

+1.5VP

4

D6D5D7D

G

S

3

2

786

5

8

PQ35

PQ35 FDS6298_SO8~D

FDS6298_SO8~D

S

1

PQ36

PQ36 SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8

123

PL8

1 2

1UH_PCMC063T-1R0MN_11A_20%

12

PR128

4.7_1206_5%

12

PC112

PC112 680P_0402_50V7K~D

680P_0402_50V7K~D

12

PC107

PC106

0.1U_0402_10V7K~D

1

+

PC87

2

10U_0805_6.3V6M~D

+1.5VP

1

+

PC94

330U 2.5V Y D2 LESR15M CX H1.9

2

330U 2.5V Y D2 LESR15M CX H1.9

PJP19

PJP19 JUMP_43X118

JUMP_43X118

2

112

PJP20

PJP20 JUMP_43X118

JUMP_43X118

2

112

+1.5VP

+1.5V

12

@

PR121

0_0402_5%

C C

PR126

PR127

1 2

SYSON<26>

0_0402_5%

@

PC104

0.1U_0402_16V7K

PR130

14.3K_0402_1%

1 2

PC98

@ PC98

B B

@

1 2

0.1U_0603_25V7K

68.1K_0402_1%

12

1 2

@

100K_0402_1%

PG_1.5VP

EN_1.5VP

FB_1.5VP

RF_1.5VP

12

PR129

470K_0402_5%~D

PR131

16.5K_0402_1%

PR124

TRIP_1.5VP

TPS51218DSCR_SON10_3X3~D

12

PC103

PR125

1 2

2.2_0603_5%

PU10

1

VBST

PGOOD

2

TRIP

DRVH

3

EN

4 5

SW

V5IN

VFB

DRVL

RF

TP

2.2_0603_5%

BST_1.5VP

10

UG_1.5VP

9

SW_1.5VP

8

V5IN_1.5VP

7

LG_1.5VP

6 11

1 2

0.22U_0603_25V7K

+5VALW

1

PC105

1U_0603_6.3V6M~D

2

PC103

+1.5VP Thermal Design Current=6.95A Peak Current=9.93A OCP min=12.9A Fsw=290KHZ

A A

Delta I=4.7745A L/S MOS Rds(on)=5.5m (Typ) ; 6.7m (Max)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Custom

+1.5VP

Tuesday, May 04, 2010

LA-6132P

of

39 45

1

Size Document Number Rev

Date: Sheet

2

Date: Sheet

A

1 1

B

C

D

+3VALW

+5VALW

12

PC113

PC113 1U_0402_6.3V6K

1U_0402_6.3V6K

6

PU11

7

POK

PR132

SUSP#<26,30,35,41,43>

2 2

1 2

10K_0402_1%

PC117

2.2U_0402_6.3V6M

12

@ PR134

@

47K_0402_5%

PR134

8

EN

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

APL5912KAI-TRL_SO8

1

PJP21

JUMP_43X79

2

12

PC114

4.7U_0805_6.3V6K

PR133

1.58K_0402_1%

12

PR135

1.27K_0402_1%

12

PC115

0.01U_0402_25V7K

12

PC116

PC116 22U_0805_6.3V6M

22U_0805_6.3V6M

+1.8VP

PJP22

112

JUMP_43X79

2

+1.8VS

+1.8VP Thermal Design Current=0.87A Peak Currnet=1.25A OCP min=1.62A

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2008/6/05

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

+1.8VP

Size Document Number Rev

Tuesday, May 04, 2010

Date: Sheet

LA-6132P

D

of

40 45

of

40 45

of

40 45

0.1Custom

5

D D

4

3

2

1

+1.5V

+5VALW

12

PC118

PC118 1U_0402_6.3V6K

1U_0402_6.3V6K

6

PU12

7

POK

PR136

SUSP#<26,30,35,40,43>

C C

1 2

10K_0402_1%

PC122

2.2U_0402_6.3V6M

12

@

47K_0402_5%

PR138

8

EN

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

APL5912KAI-TRL_SO8

1

PJP23

PJP23 JUMP_43X79

JUMP_43X79

2

12

PC119

4.7U_0805_6.3V6K

PR137

1.05K_0402_1%~D

@

PR139

3.32K_0402_1%

for 1.05V

12

PC120

0.01U_0402_25V7K

12

PR167

8.25K_0402_1%

for 0.9V

12

PC121

PC121 22U_0805_6.3V6M

22U_0805_6.3V6M

+CPU_VDDRP

PJP24

112

JUMP_43X79

2

+CPU_VDDR

+CPU_VDDRP Thermal Design Current=1.05A Peak Currnet=1.5A OCP min=1.95A

PU13

APL5508-25DC-TRL_SOT89-3

+3VS

B B

12

PC124

PC124 1U_0402_6.3V6K

1U_0402_6.3V6K

2

IN

GND

3

OUT

1

12

PC123

4.7U_0805_6.3V6K

12

@

PR140

150_1206_5%

+2.5VDDAP

PJP25

112

JUMP_43X79

2

+2.5VDDA

+2.5VDDAP Thermal Design Current=0.18A Peak Currnet=0.25A OCP min=0.33A

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

+2.5VDDAP/+CPU_VDDRP

LA-6132P

1

0.1

of

41 45Tuesday, May 04, 2010

of

41 45Tuesday, May 04, 2010

of

41 45Tuesday, May 04, 2010

5

PR142

D D

CPU_B+

+5VS

1 2

10_0603_5%

0.1U_0603_16V7K~N

1 2

10_0603_5%

+5VS +3VS

0.1U_0603_25V7K

12

PR149

PR149 0_0402_5%

0_0402_5%

12

PR153

@PR153

PR152

105K_0402_1%

C C

VGATE

VGATE<8,26>

CPU_PWRGD_SVID_REG<8>

B B

PR178

255_0402_1%

A A

CPU_SVD<8>

CPU_SVC<8>

VR_ON<26>

113K_0402_1%

DIFF_0

PC146

12

4700P_0402_50V7K~D

PR180

12

1K_0402_1%~D

PR162

5

12

FB_0

54.9K_0402_1%

@

10K_0402_1%

1 2

PR163

4.02K_0402_1%

PC147

12

180P_0402_50V8J~N

PC152

PR181

12

1000P_0402_50V7K

12

CPU_VDD0_RUN_FB_H<8>

CPU_VDD0_RUN_FB_L<8>

CPU_VDD0_RUN_FB_H<8>

COMP0

12

1000P_0402_50V7K

PR156

0_0402_5%

+CPU_CORE

VW0

PC148

PR182

PR150

@PR150

@

105K_0402_1%

12

PR155

@ PR155

@

105K_0402_1%

PR171

0_0402_5%

12

PR161

0_0402_5%

12

6.81K_0402_1%

12

PR166

10_0402_5%

PR170

1 2

10_0402_1%

12

PR146

1 2 3 4 5 6 7 8

9 10 11 12

PC134

PC130

12

PU14

OFS/VFIXEN PGOOD PWROK SVD SVC ENABLE RBIAS OCSET VDIFF0 FB0 COMP0 VW0

ISP0 ISN0

PR165

0_0402_5%

PR168

0_0402_5%

4

12

48

VIN

ISP0

13

12

47

VCC

ISN0

14

VSEN0

RTN0

0_0402_5%

+1.8VS

0_0402_5%

PR175

46

FB_NB

VSEN0

15

PR169

PC125

33P_0402_50V8J~N

12

PC126

PR141

44.2K_0402_1%

1000P_0402_50V7K

45

44

FSET_NB

COMP_NB

ISL6265AHRTZ-T_TQFN48_6X6

RTN1

RTN0

17

16

RTN1

12

VSEN1

12

PC126

12

1000P_0402_50V7K

PC129

12

PR143

12

22K_0402_1%

PR147

0_0402_5%

43

40

41

42

RTN_NB

VSEN_NB

OCSET_NB

VDIFF1

FB1

VSEN1

19

20

18

PGND_NB

COMP121ISP1

3

578

12

PR145

+VDDNBP

1 2

10_0402_5%

12

PR148

12

11.3K_0402_1%

39

38

37

BOOT_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

VW1

ISN1

22

23

24

ISP0

ISN0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PVCC

0_0402_5%

TP

49

PHASE_NB

LGATE_NB PHASE_NB UGATE_NB

PR151

10_0402_5%

36 35 34 33 32 31 30 29 28 27 26 25

CPU_VDDNB_RUN_FB_H <8>

12

PR154

BOOT_NB BOOT0 UGATE0 PHASE0

LGATE0

1U_0603_10V6K~D

3

UGATE_NB

PQ40

3 6

578

3 6

3 5

5

4

PHASE_NB

PC131

PR172

BOOT_NB

1 2

0_0603_5%

LGATE_NB

CPU_VDDNB_RUN_FB_L

1 2

UGATE0

PHASE0

+5VS

BOOT0

12

PC140

2008/2/5 2009/2/5

PC131

1 2

0.22U_0603_10V7K

PC137

PR157

1 2

0_0603_5%

0.22U_0603_10V7K

FDS6676AS_SO8

LGATE0

Compal Secret Data

Deciphered Date

241

D8D7D6D

S1S2S3G

2

PQ37

PQ37 AO4466_SO8

AO4466_SO8

12

PQ38

AO4712_SO8

12

PQ39

PQ39 SI7686DP-T1-E3_SO8

SI7686DP-T1-E3_SO8

5

PQ41

D8D7D6D

FDS6676AS_SO8

S1S2S3G

4

2

CPU_B+

PL10

1

+

2

12

PC127

10U_1206_25V6M

3.3UH_PCMC063T-3R3MN_6A_20%

1 2

PR144

4.7_1206_5%

PC133

PC133 680P_0603_50V_NPO

680P_0603_50V_NPO

CPU_B+

12

PC136

PC135

10U_1206_25V6M

12

PR159

4.7_1206_5%

12

PC138

PC138 680P_0603_50V_NPO

680P_0603_50V_NPO

+CPU_CORE Thermal Design Current=12.6A Peak Current=18A OCP min=24A Fsw=300KHZ

Title

Size Document Number Rev

Custom

Date: Sheet

1

PL9

HCB4532KF-800T90_1812

1 2

PC128

PC128 100U_25V_M

100U_25V_M

1

+

PC132

PC132 220U_D2_4VM

220U_D2_4VM

2

+VDDNBP(0.9v) TDC=2.8A Peak Current=4A OCP min=5.2A Iripple= 0.8671 Fsw=300KHZ

PJP15

+VDDNBP

0.36UH_PCMC104T-R36MN1R17_30A_20%

ISP0_1

PR158

3.65K_0805_1%

1 2

@

PR164

10_0402_5%

ISP0

Compal Electronics, Inc.

+CPU_CORE/+VDDNBP

Tuesday, May 04, 2010

2

PL11

1 2

PR160

1 2

47K_0402_1%

PC139

0.1U_0603_16V7K~N

12

@

12

10K_0603_5%_TSM1A103J4302RE

LA-6132P

JUMP_43X118

4 3

PH2

1

+VDDNBP

112

12

ISN0

B+

+VDDNB

+CPU_CORE

of

42 45

of

42 45

of

42 45

0.22

A

1 1

B

C

+NB_COREP_B+

PJP26

2

JUMP_43X118

D

112

B+

12

PC155

PC154

2200P_0402_50V7K~D

+3VALW

12

@

PR188

@

PR122

0_0402_5%

2 2

PR190

1 2

86.6K_0402_1%

PC160

86.6K_0402_1%

12

PR191

SUSP#<26,30,35,40,41>

3 3

1 2

0_0402_5%

@PC160

@

0.1U_0402_16V7K

PR194

1 2

20K_0402_1%~D

PC108

@ PC108

@

1 2

0.1U_0603_25V7K

PR188

100K_0402_1%

PU15

PG_NB_COREP BST_NB_COREP TRIP_NB_COREP EN_NB_COREP

RF_NB_COREP

12

PR193

470K_0402_5%~D

PR195

11.3K_0402_1%

PU15

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51218DSCR_SON10_3X3~D

12

VBST

DRVH

V5IN

DRVL

10 9 8

SW

7 6 11

TP

PR189

1 2

2.2_0603_5%

UG_NB_COREP SW_NB_COREP V5IN_NB_COREPFB_NB_COREP LG_NB_COREP

PC159

1 2

0.22U_0603_25V7K

+5VALW

1

PC161

PC161 1U_0603_6.3V6M~D

1U_0603_6.3V6M~D

2

8

PQ45

D6D5D7D

FDS6298_SO8~D

4

G

S

3

2

1

786

5

PQ46

SI4634DY-T1-E3_SO8

4

123

12

PR192

4.7_1206_5%

12

PC167

PC167 680P_0402_50V7K~D

680P_0402_50V7K~D

2200P_0402_50V7K~D

PL13

1 2

1UH_PCMC063T-1R0MN_11A_20%

PC156

0.1U_0603_25V7K

+NB_COREP

12

PC157

10U_1206_25V6M

12

PC158

@

10U_1206_25V6M

12

PC162

0.1U_0402_10V7K~D

1

PC163

2

10U_0805_6.3V6M~D

PJP27

PJP27 JUMP_43X118

JUMP_43X118

112

PJP28

PJP28 JUMP_43X118

JUMP_43X118

112

+NB_COREP

1

+

PC164

330U_D2_2.5VY_R9M

2

+NB_CORE

+NB_COREP Thermal Design Current=8.4A Peak Current=12A OCP min=15.6A Fsw=290KHZ

Delta I=3.8833A

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2008/6/05

Compal Secret Data

Deciphered Date

C

L/S MOS Rds(on)=5.5m (Typ) ; 6.7m (Max)

Compal Electronics, Inc.

Title

+NB_COREP

Size Document Number Rev

Tuesday, May 04, 2010

Date: Sheet

LA-6132P

D

43 45

0.2Custom

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1

Request

Item Issue DescriptionDate

DCIN & DETECTOR341 2009/12/30

D D

36

+CPU_CORE /+VDDNBP

+5VALWP/+3VALWP

+1.1VALWP37

2009/12/30 Compal HW modify +1.1VALWP power sequence

2 42 2009/12/30

3

Owner

Compal

Dell has seen a couple of field return systems at the other ODM with the ESD damaged N-FET of PSID signal.

Over component rated voltage spec.

Change PQ4 from SB00000960L (S TR SSM3K7002FU 1N SC70-3) to SB503010010 (S TR FDV301N 1N SOT23-3)

Change PC134 from SE026104KN0 (S CER CAP .1U 16V K X7R 0603) to SE042104K80(S CER CAP .1U 25V K X7R 0603)

1 Add PR119 (P/N :SD034100280) (S RES 1/16W 10K +-1% 0402) pull up +3VALW at POK

2. Change +1.1VALWP enable signal name from "SYSON" to "POK" at Node PR111.1

36

4

+5VALWP/+3VALWP

C C

+1.1VALWP37

Compal2009/12/30

For QAD Temp/Volt margin test

+1.5VP39

+NB_COREP43

5

35

CHARGER

2009/12/30

Compal

To prevent PQ5 damage issue

1. [+3VALWP portion] Add @PC95 parallel at @PR94 [+5VALWP portion] Add @PC96 parallel at PR95

2. [+1.1VALWP portion] Add @PC97 parallel at PR114

3. [+1.5VP portion] Add @PC98 parallel at PR130

4. [+NB_COREP portion] Add @PC108 parallel at PR194

Change PQ12 from SB00000DL00 (S TR AO4407A 1P SO8) to SB00000I600 (S TR SI4459ADY-T1-GE3 1P SO8)

Solution Description Rev.Page# Title

X01

6

40

41

B B

7

8

37

+1.8VP

+2.5VDDAP /+CPU_VDDRP

+NB_COREP43

+1.1VALWP

2010/02/05

Compal

HW modify +1.8VP, +CPU_VDDRP power sequence

HW modify power budget for +NB_COREP portion +NB_COREP output change from 1.2v to 1.1v

AMD measure (location :LN12) VDDPCIE Vmin under Spec follow AMD suggestion to adjust voltage level to meet spec.

942

+CPU_CORE /+VDDNBP

2010/03/08

Compal

change N0 suffix P/N to meet Dell suffix P/N (80 or 8L)

[+1.8VP portion] PC117 and [+CPU_VDDRP portion] PC122 from SE076104K80 (S CER CAP .1U 16V K X7R 0402) to SE00000888L (S CER CAP 2.2U 6.3V M X5R 0402)

Change PR195 from SD00000QM80 (S RES 1/16W 14.3K +-1% 0402) to SD034113280 (S RES 1/16W 11.3K +-1% 0402)

Change PR115 from SD034113280 (S RES 1/16W 11.3K +-1% 0402) to SD034115280 (S RES 1/16W 11.5K +-1% 0402)

1. Change PC130, PC139 from SE026104KN0 (S CER CAP .1U 16V K X7R 0603) to SE026104K8L (S CER CAP .1U 16V K X7R 0603)

Change

X01

X02

2. Change PC125 from SE068330KN0 (S CER CAP 33P 50V J NPO 0402) to SE071330J80 (S CER CAP 33P 50V J NPO 0402)

A A

3. Change PC147 from SE071181JN0 (S CER CAP 180P 50V J NPO 0402)to SE071181J8L (S CER CAP 180P 50V J NPO 0402)

Compal Electronics, Inc.

Title

PWR-PIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PWR-PIR

Size Document Number Rev

LA-6132P

Date: Sheet

Date: Sheet of

Tuesday, April 06, 2010 4544

1

of

0.1

5

4

3

2

1

Version Change List ( P. I. R. List )

Item

1

2

D D

3

4

5

6

7

8

9

10

11

16 SB 2010/01/19 HW POP RS27Boou up issue

17 SB 2010/01/19 HW UNPOP RS34, POP RS43Boou up issue

17 2010/01/19 HW ADD RS111SATA LED active

17 2010/01/19 HW UNPOP YS3, RS50, CS24, CS25Disable function

19 2010/01/19 HW Change RS92 to 0 ohm, UNPOP RS93CODEC voltage

SATA

SB

CODEC

23 2010/01/19 ESD POP DL1ESD requestUSB

26 2010/01/19 ESD ADD CE25EC

30 2010/01/19 HW Boot up issue Change CZ4, CZ8, CZ19, CZ21 to 0.1U PWR

24 2010/01/22 SafetyVGA

30 PWR 2010/01/22 Sourcer

27 LVDS 2010/01/22 EC Reserve LVDS VDD control by EC

Request Owner

12

13

C C

14

15

16

26 2010/01/27 ESD ADD CE25 location for ESDEC ESD request

26,27 2010/01/27 DELL Add CE_ENABLE and DBC_ENABLELVDS Add LCD panel feature

X'tal 2010/01/27

USB 2010/01/27 DELL Delete eSATA function Delete eSATA function and follow NLM00 change sleep charge function to USB117,25

17

18

19

20

21

26 2010/01/27 EC POP RE1, RE7 UNPOP RE4EC Change board version to 0.2(X01)

18 2010/01/28 EMIHDA Reserve SSIC for EMI concern Add US10, RS112, RS115, RS117, RS118, RS119 and CS81, CS82 X01

18,26 ACIN 2010/02/02 HW

28 WLAN 2010/02/03 HW

Vendor For X'tal EA test result Change CE12, CE13, CS14, CS15, CS16, CS17, CL16, CL17 for vendor recommended16,20,26

Sourcer2010/01/27PWR30 Modify QZ3, QZ8 to NTMS4920NR2GFDS8878/NTMS4107 will EOL

22

23

B B

13,30 Sequence 2010/02/05 HW POP RN29, RN33, QN1, QN2, and Change CZ21 to 2.2U, CZ8 to 0.01USolve NB_PWRGD sequence issue X01

23 PWR Rail 2010/03/17 HW Solve Sleeping charge issue Change +5V_ESAUSB to +USB_SIDE_PWR24 X02

27 New Panel 2010/03/17 SED25 Enable New Panel feature POP RV57, RV58 X02

30 PWR 2010/03/18 HW26 Change component for voltage issue Change CZ4, CZ19, CZ21 to 0.1U/25V, CZ8 to 0.01U/25V Change RZ21 to 470k OHM X02

27 26 EC 2010/03/23 EC For EC team common design Add RE33 and UNPOP

28 28 WLAN 2010/03/23 RF For RF team common design Add RM18 to disable BT,and support BT365 module, POP RM17

29 31 PWR button 2010/03/25 ESD For ESD issue from power button Add CZ25, DZ4

30 18,21 RF issue 2010/03/25 RF For RF issue Add CS22, RB8, CB12, Change RS119 to 33 OHM and Del RS118, RB3

31 27 LVDS 2010/03/25 HW For reserve LVDS pannel sequence Add QV11, QV12, RV59, RV60, RV61

33 2010/05/03 RF For RF team common design16,28 BT Add RM19, RM20, RS113 and UNPOP RM18, RM19, RS113 A00

34 18 SSIC 2010/05/11 RF For WWAN & NON-WWAN design Change SSIC BOM structure & CS22 to 8.2p for RF A00

A A

Issue DescriptionDate

ESD request

Safety request reserve fuse to meet LPS specification

Prevent ACIN signal to drop down from SB and EC code Reserve BT_RADIO_OFF# to ON/OFF all BT function Add 0 ohm to prevent different PANEL spec.

Solution DescriptionPage# Title

Add FV2

Modify QZ3, QZ8 to NTMS4107Fairchild FDS8878 will EOL

Change RV40 to DV10

Add RS25, RS28 (22ohm) on signal MEM_SMBCLK/MEM_SMBDATA SMbus waveform fixedHW2010/01/25SMbus18

Add RE32, DE2 and QS2 X01

Add NET BT_RADIO_OFF# to control on/off BT function X01

Reserve RV57, RV5827 LVDS 2010/02/04 HW

Change RM15 to 2k OHMWLAN32 28 2010/03/25 RF Solve Athros B95 WLAN Card issue

Rev.

X01

X02

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

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4

3

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Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

HW PIR

HW PIR LA-6132P

LA-6132P

45 45Tuesday, May 11, 2010

1

1.0

COMPAL LA-6132P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual