Compal LA-6121P Schematics

A

1 1

B

C

D

E

Compal confidential

2 2

Schematics Document

Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic

2010-04-08

3 3

NCL50 REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Montevina UMA LA6121P

E

0.2

1 46Wednesday, April 14, 2010

0.2

A

B

C

D

E

Compal confidential

1 1

LVDS Panel Interface

CRT

2 2

P19

P18

RTL8103EL (10/100M)

P25

Thermal Sensor EMC1402

Fan conn

PCI-E BUS*2

Mini-Card

WLAN

P26

Montevina 14" UMA

Mobile Penryn/Merom

P06

DMI X4

P26

uFCPGA-478 CPU

H_A#(3..35)

H_D#(0..63)

FSB

667/800/1066 MHz 1.05V

Intel Cantiga MCH

FCBGA 1329

P9,10, 11, 12, 13, 14

Intel ICH9-M

mBGA-676

P20,21,22,23

P6, 7, 8

C-Link

CK505

Clock Generator SLG8SP553V

DDR3 800/1066MHz

1.5V

Dual Channel

USB2.0 X12

Azalia

SATA Master-1

SATA Slave

72QFN

P17

DDR3 SO-DIMM X2

BANK 0, 1, 2, 3

USB conn x3

BT Conn

USB Camera

P15, 16

P30

P19

CardReader RTS5159

P27

3 in1 Slot

P27

RJ45/11 CONN

3 3

P25

LPC BUS

Audio CKT AMP & Audio Jack

Codec_AL272

P28 P28

SATA HDD Connector

P24

TPA6017A2

ENE

KB926

Touch Pad CONN.

USB Board Conn USB conn x3

4 4

RTC CKT.

P21

LED

P32

PCB

ZZZ3

DC/DC Interface CKT.

P33

A

B

P32

SPI ROM SST25VF080

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P30

C

SPI

P31

Int.KBD

P31

Compal Secret Data

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

SATA ODD Connector

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

P24

Compal Electronics, Inc.

Montevina UMA LA6121P

Block Diagram

E

0.2

2 46Thursday, April 15, 2010

0.2

A

Symbol Note :

Voltage Rails

power plane

State

O MEANS ON X MEANS OFF

+B

+5VALW

+3VALW

+1.8V

+1.5V

+5VS

+3VS

+1.5VS

+VCCP

+CPU_CORE

+0.75VS

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

45@ : means need be mounted when 45 level assy or rework stage.

DEBUG@ : means just reserve for debug.

BATT @ : means need be mounted when 45 level assy or rework stage.

CONN@ : means ME part

USB assignment:

USB-0 Right side daughter board

USB-2 Left side

USB-3 X

USB-4 Camera

USB-5 WLAN

USB-6 Bluetooth

USB-7 Cardreader

USB-8 X

USB-9 X

USB-10 X

USB-11 X

PCIe assignment:

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

O

X

XX

O

X

O

X

PCIe-1 X

PCIe-2 X

PCIe-3 WLAN

PCIe-4 GLAN (Realtek)

PCIe-5 X

PCIe-6 X

I2C / SMBUS ADDRESSING

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

DEVICE

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

SMBUS Control Table

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

ICH_SMBCLK

ICH_SMBDATA

DDC2_CLK

DDC2_DATA

SOURCE

KB926

ICH9

Cantiga

INVERTER BATT

X V

X

SERIAL EEPROM

Thermal Sensor

X

V

X

SODIMM CLK CHIP

X

V V V

X

MINI CARD

X

LCD

X

V

43184330L01

：：：：

UMA GL PR FF-

43184330L01

：：：：

Main@/DEBUG@/NewC@

PCB

：：：：

DA60000GI00 --->M/B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

Montevina UMA LA6121P

3 46Wednesday, April 14, 2010

0.2

5

4

3

2

1

40mA

D D

20mA

10mA

AC

VIN

0.35A

2A

INVPWR_B+

B++

LVDS CON

1.7A

+3VALW

177mA

ICH9

LAN

250mA

278mA

3.35A5.89A

+3VS

1500mA

250mA

C C

B+

+5VALW

7A

+1.5V

1.3A0.58A

+5VS

DDR3

1.8A

1A

+VDDA ALC272

+5VAMP

ODD

+3VAUX_BT

+3VALW_EC

SPI ROM

RTS5159

ICH9

+LCDVDD

+3VS_CK505

Mini card (WLAN)

LVDS CON

B B

3.7 X 3=11.1V

DC BATT

B+++

A A

5

CPU_B+ +VCC_CORE

12.11A1.9A

4.7A

+1.8V

1.05V_B+

10mA2A

4

+1.5VS

34A/1.025V

+0.75VS

3.7A

CPU

2.2A0.3A

MCH

+VCCP

3

657mA

1.56A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ICH_VCC1_5 ICH9

ICH9

1.17A

1.26A

2.3A

ICH9

MCH

CPU

2007/08/28 2006/03/10

700mA

Compal Secret Data

Deciphered Date

2

SATA

Web Camera

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Montevina UMA LA6121P

Date: Sheet of

Power delevry

1

4 46Wednesday, April 14, 2010

0.2

A

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

Montevina UMA LA6121P

5 46Wednesday, April 14, 2010

0.2

5

D D

4

3

ITP-XDP Connector

PV：：：： follow check list ver:1.5 change to 51 ohm

04/29 MV1 R2~R8 change to 54.9 Ohm, follow checklist 2.0

2

XDP_DBRESET#

Change value in 5/02

XDP_TDI

XDP_TMS

XDP_TDO

R2 54.9_0402_1%R2 54.9_0402_1%

R3 54.9_0402_1%R3 54.9_0402_1%

R4 54.9_0402_1%R4 54.9_0402_1%

R1

@R1

@

1 2

1

1K_0402_5%

+3VS

+VCCP

H_A#[3..16]9

H_ADSTB#09

H_REQ#09 H_REQ#19 H_REQ#29 H_REQ#39 H_REQ#49

C C

B B

A A

H_A#[17..35]9

H_ADSTB#19

H_A20M#21

H_FERR#21

H_IGNNE#21

H_STPCLK#21 H_INTR21 H_NMI21 H_SMI#21

+VCCP

B

E

H_PROCHOT# OCP#

H_IERR#

E

3 1

Q1

@

Q1

@

MMBT3904_NL_SOT23-3

+VCCP

12

@

R17

R17 56_0402_5%

56_0402_5%

2

C

R18

R18 56_0402_5%

56_0402_5%

1 2

5

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1

H_A20M# H_FERR# H_IGNNE#

H_STPCLK# H_INTR H_NMI H_SMI#

JCPU1A

J4 L5 L4

K5

M3

N2

J1

N3 P5 P2

L2

P4 P1 R1

M1

K3 H2 K2

J3 L1

Y2 U5 R3

W6

U4 Y5 U1 R4 T5

T3 W2 W5

Y4

U2

V4 W3

AA4 AB2 AA3

V1

A6

A5

C4

D5

C6

B4

A3

M4

N5

T2

V3

B2

D2

D22

D3

F6

Penryn

OCP# 22

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

ADDR GROUP_0

ADDR GROUP_1

THERMAL

ICH

THERMTRIP#

RESERVED

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA THERMDC

H CLK

BCLK[0] BCLK[1]

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

AD4 AD3 AD1 AC4 AC2 AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21 A24

H_THERMDC_R

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm.

04/29 MV1 change R14、、、、R15 to 0 ohm

4

H_ADS# 9 H_BNR# 9

H_BPRI# 9

H_DEFER# 9 H_DRDY# 9 H_DBSY# 9

H_BR0# 9

H_INIT# 21

H_LOCK# 9

H_RESET# 9

H_RS#0 9

H_RS#1 9

H_RS#2 9

H_TRDY# 9

H_HIT# 9 H_HITM# 9

T1T1

Place TP with a GND 0.1" away

PV：：：：Checklist Ver 1.5 change to 56 ohm

XDP_DBRESET# 22

R13 56_0402_1%R13 56_0402_1%

1 2

R14 0_0402_5%R14 0_0402_5%

1 2

R15 0_0402_5%R15 0_0402_5%

1 2

H_THERMTRIP# 9,21

CLK_CPU_BCLK 17 CLK_CPU_BCLK# 17

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

+VCCP

03/18 PV：：：：Delete XDP connector

+3VS

1

C2

2

H_THERMDAH_THERMDA_R H_THERMDC

+3VS

0.1U_0402_16V4ZC20.1U_0402_16V4Z

C3

1 2

2200P_0402_50V7K

R16

1 2

10K_0402_5%

H_THERMDA

H_THERMDC

THERM#

1

2

3

4

PWM Fan Control circuit

Modify as KSWAA, need double check the CONN pin define. 10/24 Prince

EN_DFAN131

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

+5VS

1A

+FAN1

1

10mil

C63

C63 10U_0805_10V4Z

10U_0805_10V4Z

2

Compal Secret Data

Deciphered Date

U6

1

EN

GND

2

VIN

GND

3

VOUT

GND

4

VSET

GND

APL5607KI-TRG_SO8

C62

10U_0805_10V4Z

8 7 6 5

2

1

BAS16_SOT23-3

U1

VDD

DP

DN

THERM#

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

12

D34

D34 1SS355_SOD323-2

1SS355_SOD323-2

12

D11

@

XDP_TRST#

XDP_TCK

SMCLK

SMDATA

ALERT#

GND

@

+FAN1

2

C168

C168 1000P_0402_25V8J@

1000P_0402_25V8J@

1

Title

Size Document Number Rev

Custom

Date: Sheet of

R7 54.9_0402_1%R7 54.9_0402_1%

1 2

R8 54.9_0402_1%R8 54.9_0402_1%

1 2

This shall place near CPU

SMB_EC_CK2

8

SMB_EC_DA2

7

R6 10K_0402_5%

6

1 2

5

ACES_85205-03001

1 2

10K_0402_5%

1

C60

@

2

0.01U_0402_16V7K

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Montevina UMA LA6121P

SMB_EC_CK2 31

SMB_EC_DA2 31

04/29 MV1 reserve 10K for 2nd source

JP2

1

2

3

4

GND

5

GND

R50

1

+3VS

CONN@

+3VS

FAN_SPEED1 31

6 46Thursday, April 15, 2010

0.2

5

4

3

2

1

H_D#[0..15]9

D D

H_DSTBN#09 H_DSTBP#09 H_DINV#09 H_D#[16..31]9

C C

* Route the TEST3 and TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.

B B

CPU_BSEL CPU_BSEL2 CPU_BSEL1

R21 1K_0402_5%@R21 1K_0402_5%@ R22 1K_0402_5%@R22 1K_0402_5%@

166

H_DSTBN#19 H_DSTBP#19 H_DINV#19

1 2 1 2

CPU_BSEL017 CPU_BSEL117 CPU_BSEL217

T2T2 T3T3 T4T4 T5T5 T6T6

0 1

200

266

0 0

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

+V_CPU_GTLREF

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

10

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn

CPU_BSEL0

H_D#32

Y22

MISC

DATA GRP 0

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP# PSI#

AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI#

1

0

H_D#[32..47] 9

H_DSTBN#2 9 H_DSTBP#2 9 H_DINV#2 9 H_D#[48..63] 9

H_DSTBN#3 9 H_DSTBP#3 9 H_DINV#3 9

H_DPRSTP# 9,21,41

H_DPSLP# 21 H_DPWR# 9 H_PWRGOOD 21

H_CPUSLP# 9

H_PSI# 41

R24

R23

12

54.9_0402_1%

Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

+V_CPU_GTLREF

27.4_0402_1%

12

+VCCP

R25

12

54.9_0402_1%

12

R27

R27 1K_0402_1%

1K_0402_1%

12

R29

R29 2K_0402_1%

2K_0402_1%

27.4_0402_1%

+VCC_CORE +VCC_CORE

R26

12

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

JCPU1C

A7

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VCCSENSE

VSSSENSE

A9 A10 A12 A13 A15 A17 A18 A20

B7

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10 C12 C13 C15 C17 C18

D9 D10 D12 D14 D15 D17 D18

E7

E9 E10 E12 E13 E15 E17 E18 E20

F7

F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

AF20

+VCCPA

G21

+VCCPB

V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

1 2 1 2

VCCSENSE

VSSSENSE

R19

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

R20

CPU_VID0 41 CPU_VID1 41 CPU_VID2 41 CPU_VID3 41 CPU_VID4 41 CPU_VID5 41 CPU_VID6 41

VCCSENSE 41

VSSSENSE 41

Length match within 25 mils. The trace width/space/other is 20/7/25.

+VCC_CORE

R28 100_0402_1%R28 100_0402_1%

1 2

R30 100_0402_1%R30 100_0402_1%

1 2

+VCCP

10U_0603_6.3V6MC710U_0603_6.3V6M

VCCSENSE

VSSSENSE

1

+

C6

C6 330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

2

1

C7

2

0.01U_0402_16V7KC80.01U_0402_16V7K

+1.5VS

1

C8

2

Near pin B26

Close to CPU pin within

A A

Close to CPU pin AD26 within 500mils.

500mils.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Montevina UMA LA6121P

1

0.2

7 46Thursday, April 15, 2010

0.2

5

D D

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

C C

B B

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

.

4

Place these capacitors on L8 (North side,Secondary Layer)

Mid Frequence Decoupling

Near CPU CORE regulator

+VCC_CORE

C41

11/21 Change ESR=7m ohm

+VCCP

1

C45

0.1U_0402_10V6K

2

3

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C9

10U_0805_6.3V6M

C17

10U_0805_6.3V6M

C25

10U_0805_6.3V6M

C33

10U_0805_6.3V6M

1

C10

10U_0805_6.3V6M

2

1

C18

10U_0805_6.3V6M

2

1

C26

10U_0805_6.3V6M

2

1

C34

10U_0805_6.3V6M

2

ESR <= 1.5m ohm Capacitor > 1980uF

1

@

+

C42

2

330U_D2E_2.5VM_R9M

Inside CPU center cavity in 2 rows

1

C46

0.1U_0402_10V6K

2

1

+

C43

330U_D2E_2.5VM_R9M

1

2

+

C44

2

330U_D2E_2.5VM_R9M

C47

0.1U_0402_10V6K

1

+

2

330U_D2E_2.5VM_R9M

1

2

1

C11

10U_0805_6.3V6M

2

1

C19

10U_0805_6.3V6M

2

1

C27

10U_0805_6.3V6M

2

1

C35

10U_0805_6.3V6M

2

C48

0.1U_0402_10V6K

1

C12

10U_0805_6.3V6M

2

1

C20

10U_0805_6.3V6M

2

1

C28

10U_0805_6.3V6M

2

1

C36

10U_0805_6.3V6M

2

1

C49

0.1U_0402_10V6K

2

1

C13

10U_0805_6.3V6M

2

1

C21

10U_0805_6.3V6M

2

1

C29

10U_0805_6.3V6M

2

1

C37

10U_0805_6.3V6M

2

1

C50

0.1U_0402_10V6K

2

1

C14

10U_0805_6.3V6M

2

1

C22

10U_0805_6.3V6M

2

1

C30

10U_0805_6.3V6M

2

1

C38

10U_0805_6.3V6M

2

1

C15

10U_0805_6.3V6M

2

1

C23

10U_0805_6.3V6M

2

1

C31

10U_0805_6.3V6M

2

1

C39

10U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

1

C16

10U_0805_6.3V6M

C24

10U_0805_6.3V6M

C32

10U_0805_6.3V6M

C40

10U_0805_6.3V6M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Montevina UMA LA6121P

1

0.2

8 46Wednesday, April 14, 2010

0.2

5

U2A

H_D#[0..63]7

D D

C C

+H_SWNG H_RCOMP

0.1U_0402_16V4Z

+H_VREF

1

C58

2

H_RESET# H_CPUSLP#

+H_VREF

H_RESET#6

H_CPUSLP#7

B B

Layout note:

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20

+VCCP

12

R46

1K_0402_1%

A A

12

R52

2K_0402_1%

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8

H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

12

24.9_0402_1%

H_RCOMP

R54

U2A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

+VCCP

221_0603_1%

100_0402_1%

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

HOST

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

+V_DDR_MCH_REF generated by DC-DC

12

R47

+H_SWNG

12

1

C59

R55

2

0.1U_0402_16V4Z

PV

：：：：

follow check list ver:1.5 change to 10K ohm

Near B3 pinwithin 100 mils from NB

5

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

4

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

4

H_A#[3..35] 6

SMRCOMP_VOH

80% of 1.5V VCC_SM

20% of 1.5V VCC_SM

SMRCOMP_VOL

H_ADS# 6 H_ADSTB#0 6 H_ADSTB#1 6 H_BNR# 6 H_BPRI# 6 H_BR0# 6 H_DEFER# 6 H_DBSY# 6 CLK_MCH_BCLK 17 CLK_MCH_BCLK# 17 H_DPWR# 7 H_DRDY# 6 H_HIT# 6 H_HITM# 6 H_LOCK# 6 H_TRDY# 6

H_DINV#0 7 H_DINV#1 7 H_DINV#2 7 H_DINV#3 7

H_DSTBN#0 7 H_DSTBN#1 7 H_DSTBN#2 7 H_DSTBN#3 7

H_DSTBP#0 7 H_DSTBP#1 7 H_DSTBP#2 7 H_DSTBP#3 7

H_REQ#0 6 H_REQ#1 6 H_REQ#2 6 H_REQ#3 6 H_REQ#4 6

H_RS#0 6 H_RS#1 6 H_RS#2 6

PLT_RST#20,25,26

H_THERMTRIP#6,21

DPRSLPVR22,41

V_DDR_MCH_REF

1

C57

2

0.1U_0402_16V4Z

+1.5V

1

C51

2.2U_0603_6.3V4Z

2

1

C53

2

2.2U_0603_6.3V4Z

R41 100_0402_5%R41 100_0402_5% R42 0_0402_5%R42 0_0402_5%

C52

0.01U_0402_25V7K

2

1

C54

2

0.01U_0402_25V7K

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_7

PM_BMBUSY#22

H_DPRSTP#7,21,41

1 2 1 2

+1.5V

12

R45

R45 10K_0402_1%

10K_0402_1%

12

R48

R48 10K_0402_1%

10K_0402_1%

12

R31

R31 1K_0402_1%

1K_0402_1%

12

R32

3.01K_0402_1%

12

R33

R33 1K_0402_1%

1K_0402_1%

R38 10K_0402_5%R38 10K_0402_5%

R39 10K_0402_5%R39 10K_0402_5%

R40 10K_0402_5%R40 10K_0402_5%

MCH_CLKSEL017 MCH_CLKSEL117 MCH_CLKSEL217

PM_EXTTS#015 PM_EXTTS#116 PM_PWROK22,31

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

T7T7 T8T8 T9T9 T10T10 T11T11 T12T12 T13T13 T14T14 T15T15 T16T16 T17T17 T18T18 T19T19

Delete them for placement. 11/23

T22T22 T23T23

T24T24

T25T25 T26T26 T27T27 T28T28

1 2

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK

THERMTRIP# DPRSLPVR

@

1

C55

2

0.1U_0402_16V4Z

3

CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

CFG511 CFG611 CFG711 CFG811

CFG911 CFG1011 CFG1111 CFG1211 CFG1311 CFG1411 CFG1511 CFG1611 CFG1711 CFG1811 CFG1911 CFG2011

Issued Date

U2B

M36

RESERVED

N36

RESERVED

R33

RESERVED

T33

RESERVED

AH9

RESERVED

AH10

RESERVED

AH12

RESERVED

AH13

RESERVED

K12

RESERVED

AL34

RESERVED

AK34

RESERVED

AN35

RESERVED

AM35

RESERVED

T24

RESERVED

B31

RESERVED

B2

RESERVED

M1

RESERVED

AY21

RESERVED

BG23

RESERVED

BF23

RESERVED

BH18

RESERVED

BF18

RESERVED

+3VS

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC

BF48

NC

BD48

NC

BC48

NC

BH47

NC

BG47

NC

BE47

NC

BH46

NC

BF46

NC

BG45

NC

BH44

NC

BH43

NC

BH6

NC

BH5

NC

BG4

NC

BH3

NC

BF3

NC

BH2

NC

BG2

NC

BE2

NC

BG1

NC

BF1

NC

BD1

NC

BC1

NC

F1

NC

A47

NC

CANTIGA ES_FCBGA1329

2007/08/28 2006/03/10

RSVD

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_DRAMRST#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

CFG

DMI

PM

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

NC

Compal Secret Data

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

Deciphered Date

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

2

M_CLK_DDR0

AP24

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

V_DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17

TP_SM_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33 B32 G33 F33 E33

delete test point for Placement.11/17

C34

CL_CLK0

AH37

CL_DATA0

AH36

M_PWROK

AN36

CL_RST#

AJ35

+CL_VREF

AH34

0621 add CLK and DAT for DVI

N28

Delete them for placement. 11/23

M28 G36 E36

CLKREQ#_7

K36

MCH_ICH_SYNC#

H36

TSATN#

B12

B28 B30 B29 C29 A28

T29T29

T45T45 T51T51

T52T52

R737 56_0402_5%R737 56_0402_5%

1 2

T53T53

M_CLK_DDR0 15 M_CLK_DDR1 15 M_CLK_DDR2 16 M_CLK_DDR3 16

M_CLK_DDR#0 15 M_CLK_DDR#1 15 M_CLK_DDR#2 16 M_CLK_DDR#3 16

DDR_CKE0_DIMMA 15 DDR_CKE1_DIMMA 15 DDR_CKE2_DIMMB 16 DDR_CKE3_DIMMB 16

DDR_CS0_DIMMA# 15 DDR_CS1_DIMMA# 15 DDR_CS2_DIMMB# 16 DDR_CS3_DIMMB# 16

M_ODT0 15 M_ODT1 15 M_ODT2 16 M_ODT3 16

R34 80.6_0402_1%R34 80.6_0402_1%

1 2

R35 80.6_0402_1%R35 80.6_0402_1%

1 2

Follow Design Guide For Cantiga: 80.6ohm

R36 0_0402_5%@R36 0_0402_5%@

1 2

R37 499_0402_1%R37 499_0402_1%

1 2

SM_DRAMRST# 15,16

CLK_MCH_DREFCLK 17

CLK_MCH_DREFCLK# 17

MCH_SSCDREFCLK 17

MCH_SSCDREFCLK# 17

CLK_MCH_3GPLL 17 CLK_MCH_3GPLL# 17

DMI_TXN0 22 DMI_TXN1 22 DMI_TXN2 22 DMI_TXN3 22

DMI_TXP0 22 DMI_TXP1 22 DMI_TXP2 22 DMI_TXP3 22

DMI_RXN0 22 DMI_RXN1 22 DMI_RXN2 22 DMI_RXN3 22

DMI_RXP0 22 DMI_RXP1 22 DMI_RXP2 22 DMI_RXP3 22

CH751H-40PT_SOD323-2

SM_PWROK

CL_CLK0 22 CL_DATA0 22 M_PWROK 22,31 CL_RST# 22

C56

0.1U_0402_16V4Z

T60T60 T61T61

CLKREQ#_7 17 MCH_ICH_SYNC# 22

+VCCP

TSATN# 31

R1120

R1120 10K_0402_5%~D

10K_0402_5%~D

D25

2 1

+VCCP

12

1

2

*R44*Follow Intel feedback

+1.5V

12

R43

R43 1K_0402_1%

1K_0402_1%

R44

R44 499_0402_1%

499_0402_1%

0830 Add pull-up and pull-down resistor.

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

Montevina UMA LA6121P

1

+1.5V

SYSON 31,33,39

DDR3_SM_PWROK 39

9 46Thursday, April 15, 2010

1

0.2

5

D D

DDR_A_D[0..63]15 DDR_B_D[0..63]16

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U2D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA ES_FCBGA1329

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

4

BD21 BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 15 DDR_A_BS1 15 DDR_A_BS2 15

DDR_A_RAS# 15 DDR_A_CAS# 15 DDR_A_WE# 15

DDR_A_DM[0..7] 15

DDR_A_DQS[0..7] 15

DDR_A_DQS#[0..7] 15

DDR_A_MA[0..14] 15

3

U2E

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U2E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTIGA ES_FCBGA1329

2

DDR_B_BS0

BC16

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS#

SB_CAS#

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

BB17 BB33

AU17 BG16 BF14

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_BS1 DDR_B_BS2

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

1

DDR_B_BS0 16 DDR_B_BS1 16 DDR_B_BS2 16

DDR_B_RAS# 16 DDR_B_CAS# 16 DDR_B_WE# 16

DDR_B_DM[0..7] 16

DDR_B_DQS[0..7] 16

DDR_B_DQS#[0..7] 16

DDR_B_MA[0..14] 16

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR3 A/B CH

Montevina UMA LA6121P

1

0.2

10 46Thursday, April 15, 2010

0.2

5

R148

1 2

100K_0402_5%

Follow Intel DG & Checklist

D D

ENBKL

INV_PWM_GL4019

ENBKL31

+3VS

DDC2_CLK19

DDC2_DATA19

ENAVDD19

LVDS_ACLK-19 LVDS_ACLK+19

LVDS_A0-19 LVDS_A1-19 LVDS_A2-19

LVDS_A0+19 LVDS_A1+19 LVDS_A2+19

For make layout clearance, del TP for channel B. 11/02

ENBKL

R58 10K_0402_5%R58 10K_0402_5%

R59 10K_0402_5%R59 10K_0402_5%

DDC2_CLK DDC2_DATA

ENAVDD

R60 2.4K_0402_1%R60 2.4K_0402_1%

LVDS_ACLKLVDS_ACLK+

LVDS_A0LVDS_A1LVDS_A2-

LVDS_A0+ LVDS_A1+ LVDS_A2+

1 2

delete test point

TV_LUMA

TV_CRMA

12

75_0402_1%

R63

150_0402_1%

12

R67

HSYNC

VSYNC

1.02K_0402_1%

12

R70

12

75_0402_1%

C C

Follow Intel DG & Checklist

11/10 Disable TV out

+3VS

M_BLUE18 M_GREEN18 M_RED18

Follow Intel DG & Checklist

3VDDCCL18 3VDDCDA18

CRT_HSYNC18

CRT_VSYNC18

B B

M_BLUE M_GREEN M_RED

3VDDCCL 3VDDCDA

CRT_HSYNC

CRT_VSYNC

75_0402_1%

R62

R61

R64 2.2K_0402_5%@R64 2.2K_0402_5%@

1 2

R406 0_0402_5%R406 0_0402_5%

1 2

150_0402_1%

12

R65

R66

R68

1 2

30.1_0402_1%

30.1_0402_1% R69

R69

1 2

30.1_0402_1%

TV_COMPS

75_0402_1%

150_0402_1%

11/02 11/02 11/02

12

4

U2C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

3

2

1

Strap Pin Table

R57

1 2

49.9_0402_1%

PEGCOMP trace width and spacing is 20/25 mils.

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

PEG_COMPI

PEG_COMPO

LVDS

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

TV VGA

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13

PCI-EXPRESS GRAPHICS

PEG_TX#_14 PEG_TX#_15

+VCC_PEG

CFG[2:0] FSB Freq select

CFG[4:3]

CFG5 (DMI select)

CFG6

CFG7

(Intel Management Engine Crypto strap)

CFG8

CFG9 (PCIE Graphics

Lane Reversal)

CFG10

(PCIE Lookback enable)

CFG11

CFG[13:12] (XOR/ALLZ)

CFG[15:14]

CFG16 (FSB Dynamic ODT)

CFG[18:17]

CFG19 (DMI Lane Reversal)

CFG20

(PCIE/SDVO concurrent)

+3VS

12

R71

@R71

@

4.02K_0402_1%

CFG59

CFG5

R74

@R74

@

2.21K_0402_1%

12

000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz

Others = Reserved

Reserved

0 = DMI x 2

1 = DMI x 4

0 = The iTPM Host Interface is enable

*

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in

order

*

0 = Enable

1 = Disable

Reserved

00 = Reserved

01 = XOR Mode Enabled

10 = All Z Mode Enabled

*

(Default)11 = Normal Operation

*

Reserved

0 = Disabled

1 = Enabled

*

Reserved

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

R72

@R72

CFG169

CFG199

CFG209

@

@R73

@

@R75

@

R73

R75

*

1 2

4.02K_0402_1%

1 2

4.02K_0402_1%

1 2

4.02K_0402_1%

*

+3VS

R76

@R76

@

@R77

@

@R78

@

@R80

@

@R82

@

@R85

@

@R87

@

R77

R78

R80

R82

R85

R87

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

11 46Thursday, April 15, 2010

0.2

04/29 MV-1 Delete CFG5 CFG7

、、、、

CFG12

@R79

CFG69

CFG79

CFG89

CFG99

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

CFG109

2

@

@R81

@

@R83

@

@R84

@

@R86

@

、、、、

CFG13

、、、、

CFG16

R79

1 2

2.21K_0402_1%

R81

1 2

2.21K_0402_1%

R83

1 2

2.21K_0402_1%

R84

1 2

2.21K_0402_1%

R86

1 2

2.21K_0402_1%

Title

Cantiga(3/6)-VGA/LVDS/TV

Size Document Number Rev

Custom

Montevina UMA LA6121P

Date: Sheet of

CFG119

CFG129

CFG139

CFG149

CFG159

CFG179

CFG189

Compal Electronics, Inc.

1

5

+3VS_DAC_BG

0.022U_0402_16V7K

0.1U_0402_16V4Z

1

2

0.022U_0402_16V7K

1

2

+3VS

220U_6.3V

0.1U_0402_16V4Z

C69

1

2

R91

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

C76

1

2

R96

@ R96

@

1 2

0_0603_5%

R97

1 2

0_0603_5%

1

C94

+

2

R103

1 2

0_0603_5%

C102

1U_0603_10V4Z

C70

1

2

12

@

C68

0_0603_5%

R89

D D

C C

B B

+3VS_DAC_CRT

C75

12

@ R92

@

0_0603_5%

R92

+1.5VS

+VCCP

pull low when no HDMI on 09/22

+3VS

R88

1 2

BLM18PG181SN1D_0603

10U_0805_10V4Z

+3VS

1

C89

0.1U_0402_16V4Z

2

R100

1 2

0_0805_5%

C95

1

2

+1.05VS_A_SM_CK

C103

1

2

+1.8V_TXLVDS

+1.5VS_PEG_BG

10U_0805_10V4Z

C96

4.7U_0805_10V4Z

1U_0603_10V4Z

10U_0805_10V4Z

C104

1

2

**RED Mark: Means UMA & dis@ Power select** ~It check by INTEL Graphics Disable Guidelines~

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.05VS_HPLL

+1.05VS_MPLL

1

C88

1000P_0402_50V7K

2

+1.05VS_PEGPLL

+1.05VS_A_SM

1

C97

2

1U_0603_10V4Z

0.1U_0402_16V4Z

C105

1

2

+3VS_TVDAC

R124

1 2

0_0402_5%

+1.5VS_TVDAC

+1.5VS_QDAC

+1.05VS_HPLL

+1.05VS_PEGPLL

+1.8V_LVDS

4

U2H

73mA

B27

VCCA_CRT_DAC

A26

VCCA_CRT_DAC

2.68mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

414uA

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM_CK

AN28

VCCA_SM_CK

AP25

VCCA_SM_CK

AN25

VCCA_SM_CK

AN24

VCCA_SM_CK

AM28

VCCA_SM_CK_NCTF

AM26

VCCA_SM_CK_NCTF

AM25

VCCA_SM_CK_NCTF

AL25

VCCA_SM_CK_NCTF

AM24

VCCA_SM_CK_NCTF

AL24

VCCA_SM_CK_NCTF

AM23

VCCA_SM_CK_NCTF

AL23

VCCA_SM_CK_NCTF

B24

VCCA_TV_DAC

A24

VCCA_TV_DAC

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS

L37

VCCD_LVDS

60.31mA

CANTIGA ES_FCBGA1329

64.8mA

24mA

139.2mA

720mA

26mA

TVA 24.15mA TVB 39.48mA TVX 24.15mA

50mA

58.67mA

48.363mA

157.2mA

50mA

852mA

CRTPLLA PEGA SMTV

A LVDSHDA

POWER

A CK

105.3mA

1732mA

D TV/CRT

LVDS

AXF

SM CK

118.8mA

VCC_TX_LVDS

HV

PEG

DMI

456mA

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

VTT

VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT

321.35mA

VCC_AXF VCC_AXF VCC_AXF

124mA

VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK

VCC_HV VCC_HV VCC_HV

VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG

VCC_DMI VCC_DMI VCC_DMI VCC_DMI

VTTLF VTTLF VTTLF

VTTLF

3

Change the size H to L.10/29

+VCCP

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

220U_6.3V

1

C3200

C72

1

+

2

0.47U_0603_10V7K

4.7U_0805_10V4Z

1

C80

C81

2

+V1.05VS_AXF

+1.5V_SM_CK

+1.8V_TXLVDS

+3VS_HV

<BOM Structure>C107

C107

+VCC_PEG

+1.05VS_DMI

0.47U_0603_10V7K

C111

C110

1

2

1

2

0.47U_0603_10V7K

C112

1

2

+1.05VS_DPLLA

1 2

R90

10U_0805_10V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

C82

2

0.1U_0402_16V4Z

220U_6.3V

1

C77

1

+

2

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z C87

10U_0805_10V4Z

C87

10U_0805_10V4Z

C86

1

2

+1.05VS_HPLL

+1.05VS_MPLL

C99

0.1U_0402_16V4Z

+1.05VS_PEGPLL

0.1U_0402_16V4Z

@

C73

220U_6.3V

10U_FLC-453232-100K_0.25A_10%

C74

1

2

R94

1 2

10U_FLC-453232-100K_0.25A_10%

0.1U_0402_16V4Z

0.1U_0402_16V4Z C91

C91

C90

1

2

1

2

0.1U_0402_16V4Z

10U_0805_10V4Z

C106

1

2

+VCCP+1.05VS_DPLLB

R98

1 2

MBK2012121YZF_0805

10U_0805_10V4Z

R101

1 2

MBK2012121YZF_0805

C100

10U_0805_10V4Z

L1

1 2

BLM18PG121SN1D_0603

C108

+VCCP

+3VS

+VCCP

+VCCP_D

D3

2 1

CH751H-40PT_SOD323-2

R105

1 2

10_0402_5%

10U_0805_10V4Z

1

2

+1.5VS_TVDAC

+V1.05VS_AXF

10U_0805_10V4Z

1

2

+1.5V_SM_CK

@

C83

1

2

1

C92

2

+VCC_PEG

1

+

C98

2

+1.05VS_DMI

1

2

R106

1 2

0_0402_5%

C78

10U_0805_10V4Z

0.022U_0402_16V7K

220U_6.3V

C109

1

C84

C93

C101

R104

1 2

0_0603_5%

0.1U_0402_16V4Z

+VCCP

R93

1 2

1U_0603_10V4Z

0_0603_5%

C79

1

2

+1.5V

R95

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0_0805_5%

0_0805_5%

C85

1

2

+1.5VS

R99

1 2

0.1U_0402_16V4Z

0_0805_5%

1

2

+VCCP

R102

1 2

0_0805_5%

10U_0805_10V4Z

1

2

+VCCP

+3VS_HV

+1.8V_LVDS

R107

@R109

@

10U_0805_10V4Z

R109

12

0_0603_5%

1

2

@R114

@

R114

12

0_0603_5%

+1.5VS_QDAC

C119

1

2

0.022U_0402_16V7K

0.1U_0402_16V4Z

@

C120

@

220U_D2_4VM

1

C121

1

2

C121

+

2

4

+3VS_TVDAC

0.022U_0402_16V7K

@R113

@

A A

R113

0.022U_0402_16V7K

12

0_0603_5%

C117

1

2

0.1U_0402_16V4Z

C118

1

2

R111

1 2

BLM18PG181SN1D_0603

5

+3VS

R112

1 2

100_0603_1%

+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

1 2

1U_0603_10V4Z

0_0603_5%

C113

C114

1

2

Title

Size Document Number Rev

Custom

Date: Sheet of

@R110

@

+1.8V

R110

12

Compal Electronics, Inc.

Cantiga(4/6)-PWR

Montevina UMA LA6121P

40 mils

0_0603_5%

1000P_0402_50V7K

+1.8V_TXLVDS

C116

1

2

R108

1 2

0_0603_5%

@

220U_6.3V

1

C115

+

2

12 46Wednesday, April 14, 2010

1

+1.8V

0.2

5

4

3

2

1

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

+VCCP

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

0.1U_0402_16V4Z

1

C127

2

0.22U_0402_10V4Z

C139 0.1U_0402_16V4ZC139 0.1U_0402_16V4Z

1

2

4.7U_0603_6.3V6M

1

2

C140 0.1U_0402_16V4ZC140 0.1U_0402_16V4Z

1

2

C129

C128

2

C144 1U_0603_10V4ZC144 1U_0603_10V4Z

C142 0.22U_0603_10V7KC142 0.22U_0603_10V7K

C141 0.22U_0603_10V7KC141 0.22U_0603_10V7K

1

2

C145 1U_0603_10V4ZC145 1U_0603_10V4Z

C143 0.47U_0402_6.3V6KC143 0.47U_0402_6.3V6K

1

2

U2G

0421 Change size to B2 for DFX

Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA

U2F

+VCCP

D D

0.22U_0402_10V4Z

220U_6.3V

C C

B B

0.22U_0402_10V4Z

10U_0805_10V4Z

1

C131

C124

1

+

2

0.1U_0402_16V4Z

C133

C132

1

2

C125

1

2

U2F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33

VCC

AC33

VCC

AA33

VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC

AH28

VCC

AF28

VCC

AC28

VCC

AA28

VCC

AJ26

VCC

AG26

VCC

AE26

VCC

AC26

VCC

AH25

VCC

AG25

VCC

AF25

VCC

AG24

VCC

AJ23

VCC

AH23

VCC

AF23

VCC

T32

VCC

CANTIGA ES_FCBGA1329

VCC CORE

POWER

VCC NCTF

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

+VCCP

request

1U_0603_10V4Z

+1.5V

1

C134

2

330U_B2_2.5VM_R15M

1

@+C126

@

+

2

10U_0805_10V4Z

330U_6.3V

1

+

C135

2

10U_0805_10V4Z

C122

C126

1

2

0317 change value

1

C137

C136

2

10U_0805_10V4Z

0.01U_0402_16V7K

C130

C123

1

2

1

+VCCP

0.1U_0402_16V4Z

1

C138

2

T42PAD T42PAD T43PAD T43PAD

AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32

AW32

AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29

AW29

AV29 AU29 AT29 AR29 AP29

BA36 BB24

BD16

BB21 AW16 AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21 AG21 AE21 AC21 AA21

AH20 AF20 AE20 AC20 AB20 AA20

AM15

AL15 AE15

AJ15

AH15 AG15

AF15 AB15 AA15

AN14 AM14

AJ14

AH14

Y26

Y24

Y21

T17 T16

Y15 V15 U15

U14 T14

3000mA

VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM

VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC

6326.84mA

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

VCC_AXG_SENSE VSS_AXG_SENSE

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

VCC SM LF

A A

CANTIGA ES_FCBGA1329

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

Montevina UMA LA6121P

1

0.2

13 46Wednesday, April 14, 2010

0.2

5

U2I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

D D

C C

B B

A A

VSS

AD47

VSS

AB47

VSS

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA ES_FCBGA1329

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

4

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

3

U2J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

BA16

AU16 AN16

BG15 AC15

W15

BG14 AA14

BG13 BC13 BA13

AN13

AJ13

AE13

BF12

AV12

AT12

AM12

AA12

BD11 BB11

AY11 AN11 AH11

BG10 AV10

AT10

AJ10 AE10 AA10

AM9

R17 M17 H17 C17

N16 K16 G16 E16

A15

C14

N13

L13 G13 E13

J12 A12

Y11 N11 G11 C11

M10 BF9 BC9 AN9

AD9

G9

B9 BH8 BB8 AV8 AT8

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CANTIGA ES_FCBGA1329

VSS NCTF

VSS SCB

NC

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS

2

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1

NC

D2

NC

C3

NC

B4

NC

A5

NC

A6

NC

A43

NC

A44

NC

B45

NC

C46

NC

D47

NC

B47

NC

A46

NC

F48

NC

E48

NC

C48

NC

B48

NC

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

Montevina UMA LA6121P

1

0.2

14 46Wednesday, April 14, 2010

0.2

5

DDR_A_DQS#[0..7]10

DDR_A_D[0..63]10

DDR_A_DM[0..7]10

DDR_A_DQS[0..7]10

DDR_A_MA[0..14]10

D D

C C

B B

A A

Layout Note: Place near JDIMM1

+1.5V

2.2U_0805_16V4Z

C152

1

2

Layout Note: Place near JDIMM1.203 & JDIMM1.204

+0.75VS

1U_0603_10V4Z

C159

1

2

2.2U_0805_16V4Z

C147

1

2

1U_0603_10V4Z

C160

1

2

5

2.2U_0805_16V4Z

C153

C154

1

2

1U_0603_10V4Z

10U_0805_6.3V6M

C161

C162

C163

1

2

C163

1

2

2.2U_0805_16V4Z

1

2

2.2U_0805_16V4Z

Layout Note: Place these 4 caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

2.2U_0805_16V4Z

C155

C158

1

2

Modify+0.75V to +0.75VS 09/22

+1.5V

12

R1108

1K_0402_1%

0.1U_0402_16V4Z

12

C165

C164

1

2

R1109

R1109 1K_0402_1%

1K_0402_1%

2

0.1U_0402_16V4Z

C148

C156

1

2

+V_DDR3_DIMM_REF

4

+V_DDR3_DIMM_REF

330U_6.3V

0.1U_0402_16V4Z

C149

1

2

1

C150

C157

1

+

2

0.1U_0402_10V6K

0.1U_0402_10V6K C166

C166

1

2

DDR_CKE0_DIMMA9

DDR_A_BS210

M_CLK_DDR09

M_CLK_DDR#09

DDR_A_BS010

DDR_A_WE#10

DDR_A_CAS#10

DDR_CS1_DIMMA#9

Modify net name 09/23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2.2U_0603_6.3V4Z

1

2

DDR_A_D0

C167

DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

+1.5V

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR#0 M_CLK_DDR#1

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D59

R116 10K_0402_5%R116 10K_0402_5%

1 2

+3VS

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

1

C171

2

3

2

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

10K_0402_5%

12

R115

C172

2006/02/13 2006/03/10

VTT1

205

G1

TYCO_C-2013289

CONN@

SO-DIMM A

Compal Secret Data

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

A15 A14

VDD4

A11

A7

VDD6

A6 A4

VDD8

A2 A0

VDD10

CK1 CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

G2

Deciphered Date

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 SM_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

R1107 0_0402_5%@R1107 0_0402_5%@

DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55DDR_A_D50

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62DDR_A_D58 DDR_A_D63

PM_EXTTS#0 CLK_SMBDATA

2

1 2

+0.75VS

1

SM_DRAMRST# 9,16

DDR_CKE1_DIMMA 9

M_CLK_DDR1 9 M_CLK_DDR#1 9

DDR_A_BS1 10 DDR_A_RAS# 10

DDR_CS0_DIMMA# 9 M_ODT0 9

M_ODT1 9

+V_DDR3_DIMM_REF

2.2U_0805_16V4Z

1

2

PM_EXTTS#0 9

+1.5V

0.1U_0402_16V4Z

1

C146

C151

2

CLK_SMBDATA 16,17 CLK_SMBCLK 16,17

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

Montevina UMA LA6121P

1

0.2

15 46Thursday, April 15, 2010

0.2

5

DDR_B_DQS#[0..7]10

DDR_B_D[0..63]10

DDR_B_DM[0..7]10

DDR_B_DQS[0..7]10

DDR_B_MA[0..14]10

D D

Layout Note: Place near JDIMM2

+1.5V

2.2U_0805_16V4Z

C C

B B

A A

Layout Note: Place near JDIMM2.203 & JDIMM2.204

+0.75VS

1U_0603_10V4Z

C175

C174

1

2

1U_0603_10V4Z

C186

C185

1

2

5

2.2U_0805_16V4Z

C176

1

2

1U_0603_10V4Z

C187

1

2

2.2U_0805_16V4Z

C183

C177

1

2

10U_0805_6.3V6M

C189

C188

1

2

Layout Note: Place these 4 caps near Command and Control signals of DIMMB

2.2U_0805_16V4Z

C184

1

2

0.1U_0402_16V4Z

C178

1

2

4

0.1U_0402_16V4Z

C180

C179

1

2

C181

1

2

+1.5V

+3VS

C192

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+V_DDR3_DIMM_REF

JDIMM2

VREF_DQ1VSS1

3

DDR_B_D0

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C173

1

2

DDR_CKE2_DIMMB9 DDR_CKE3_DIMMB 9

DDR_B_BS210

M_CLK_DDR29

M_CLK_DDR#29

DDR_B_BS010

DDR_B_WE#10

DDR_B_CAS#10

DDR_CS3_DIMMB#9

+3VS

1

2

C1403

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

3

DDR_B_D1

DDR_B_DM0

C182

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

R1111 10K_0402_5%R1111 10K_0402_5%

R1112 10K_0402_5%R1112 10K_0402_5%

12

Compal Secret Data

2006/02/13 2006/03/10

Compal Secret Data

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_C-2013310

CONN@

SO-DIMM B

Deciphered Date

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

SM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_CKE3_DIMMB

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202

SCL

204

206

G2

2

R1110 0_0402_5%@R1110 0_0402_5%@

DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_EXTTS#1 CLK_SMBDATA

+0.75VS

SM_DRAMRST# 9,15

1 2

M_CLK_DDR3 9 M_CLK_DDR#3 9

DDR_B_BS1 10 DDR_B_RAS# 10

DDR_CS2_DIMMB# 9 M_ODT2 9

M_ODT3 9

+V_DDR3_DIMM_REF

PM_EXTTS#1 9

CLK_SMBDATA 15,17 CLK_SMBCLK 15,17

Title

Size Document Number Rev

Date: Sheet of

1

+1.5V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

C191

C190

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

Montevina UMA LA6121P

16 46Thursday, April 15, 2010

1

0.2

5

PCI

FSC

FSB

CLKSEL2

CLKSEL1

00

0

1

D D

0

1

0

1

0

1

FSA

CPU_BSEL07

C C

FSB

CPU_BSEL17

B B

FSC

CPU_BSEL27

FSA

CLKSEL0

0

1

0

1

0

1

0

1

R128

1 2

2.2K_0402_5%

2.2K_0402_5% R138

R138

1 2

0_0402_5%

R154

1 2

0_0402_5%

R164

1 2

10K_0402_5%

10K_0402_5% R171

R171

1 2

0_0402_5%

CPU MHz

266

133

200

166

333

100

400

+VCCP

1 2

R129

R129 1K_0402_5%

1K_0402_5%

12

@

R139

R139 1K_0402_5%

1K_0402_5%

@

R143

R143 1K_0402_5%

1K_0402_5%

1 2

R150

R150 1K_0402_5%

1K_0402_5%

12

@

R157

R157 0_0402_5%

0_0402_5%

12

@

R163

R163 1K_0402_5%

1K_0402_5%

1 2

R165

R165 1K_0402_5%

1K_0402_5%

12

@

R174

R174 0_0402_5%

0_0402_5%

MHz

100

R123

@ R123

@

1 2

56_0402_5%

SRC

REF

MHz

33.3

14.318 96.0 48.0

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

Reserved

+VCCP

MCH_CLKSEL0 9

MCH_CLKSEL1 9

MCH_CLKSEL2 9

DOT_96 MHz

96.0

NB

CPU

CLK_ENABLE#41

CK_PWRGD22

CLK_14M_ICH22

CLK_DEBUG_PORT_126

CLK_PCI_EC31

CLK_PCI_ICH20

Change 33M and 48M damping to 39M by EMI request

add 48MHZ for cardreader 09/22

ITP_EN

PCI_CLK3

A A

0 = SRC8/SRC8# 1 = ITP/ITP# 0 = Enable DOT96 & SRC1(UMA) 1 = Enable SRC0 & 27MHz(DIS)

+3VS +3VS

12

R180

R180 10K_0402_5%

10K_0402_5%

ITP_EN PCI_CLK3

12

@

R182

R182 10K_0402_5%

10K_0402_5%

5

12

@

R181

R181 10K_0402_5%

10K_0402_5%

12

R183

R183 10K_0402_5%

10K_0402_5%

4

USB MHz

48.0

CLKREQ#_79

CLK_MCH_BCLK9 CLK_CPU_BCLK#6 CLK_CPU_BCLK6

VGATE22,41

R141 0_0402_5%@R141 0_0402_5%@ R142 0_0402_5%@R142 0_0402_5%@ R140 0_0402_5%R140 0_0402_5%

No Debug port anymore

R147 33_0402_1%R147 33_0402_1%

R393 39_0402_1%R393 39_0402_1%

R158 33_0402_1%R158 33_0402_1%

R161 33_0402_1%R161 33_0402_1%

CLK_SD_48M27

CLK_48M_ICH22

CLK_MCH_DREFCLK9 CLK_MCH_DREFCLK#9

4

+3VS

Routing the trace at least 10mil

Y1

1 2

2

C213

18P_0402_50V8J

1

Vendor suggests 22pF

R126 475_0402_1%R126 475_0402_1%

1 2

R130 0_0402_5%R130 0_0402_5%

1 2

R132 0_0402_5%R132 0_0402_5%

1 2

R134 0_0402_5%R134 0_0402_5%

1 2

R136 0_0402_5%R136 0_0402_5%

1 2

1 2 1 2 1 2

1 2

T44T44

1 2

R169 33_0402_1%R169 33_0402_1%

1 2

R167 39_0402_1%R167 39_0402_1%

1 2

R173 0_0402_5%R173 0_0402_5%

1 2

R175 0_0402_5%R175 0_0402_5%

1 2

NB (UMA)

ICH_SMBDATA22,26

SB, MINI PCI

ICH_SMBCLK22,26

3

+3VS_CK505

R121

1 2

0_0805_5%

CLK_XTAL_OUT

CLK_XTAL_IN

14.318MHZ_16PF_7A14300083

2

C214

C214 18P_0402_50V8J

18P_0402_50V8J

1

R_CKPWRGD FSB

CLK_XTAL_OUT CLK_XTAL_IN

FSC REF1 CLK_SMBDATA CLK_SMBCLK

PCI2_1

27_SEL PCI_CLK3 ITP_EN

T82T82

Q3B

3

2N7002DW-7-F_SOT363-6

1

C199

10U_0805_10V4Z

2

R_CLKREQ#_7 R_MCH_BCLK# R_MCH_BCLK R_CPU_BCLK# R_CPU_BCLK

U3

+3VS_CK505

1

CKPWRGD/PD#

2

FS_B/TEST_MODE

3

VSS_REF

4

XTAL_OUT

5

XTAL_IN

6

VDD_REF

7

REF_0/FS_C/TEST_

8

REF_1

9

SDA

10

SCL

11

NC

12

VDD_PCI

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

+3VS_CK505

FSA

R_CLK_48M_CRUSB

+1.05VS_CK505

R_MCH_DREFCLK R_MCH_DREFCLK# SSCDREFCLK#

+3VS

Q3A

6 1

5

2N7002DW-7-F_SOT363-6

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C200

0.1U_0402_16V4Z

2

+VCCP

+3VS_CK505

72

71

70

69

68

67

66

CPU_0

CPU_1

CPU_0#

CPU_1#

VSS_CPU

VDD_CPU

VDD_CPU_IO

VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_9624SRC_0#/DOT_96#25VSS_IO26VDD_PLL327LCDCLK/27M28LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#

+3VS

R178

2.2K_0402_5%

2

2007/08/28 2006/03/10

3

R122

1 2

0_0805_5%

+1.05VS_CK505

65

64

63

CLKREQ_7#

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

+3VS

1

C201

0.1U_0402_16V4Z

2

+1.05VS_CK505

1

C206

2

10U_0805_10V4Z

62

61

60

59

58

57

56

SRC_7

SRC_6

SRC_7#

VSS_SRC

CLKREQ_6#

VDD_SRC_IO

+1.05VS_CK505

R179

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

Compal Secret Data

1

C202

0.1U_0402_16V4Z

2

Place close to U51

0.1U_0402_16V4Z

1

C207

2

0.1U_0402_16V4Z

R_MCH_3GPLL R_MCH_3GPLL# R_CLKREQ#_6 R_CLK_PCIE_MCARD2 R_CLK_PCIE_MCARD2#

+3VS_CK505

55

SRC_6#

VDD_SRC

PCI_STOP#

CPU_STOP#

VDD_SRC_IO

SRC_10#

SRC_10

CLKREQ_10#

SRC_11

SRC_11#

CLKREQ_11#

SRC_9#

SRC_9

CLKREQ_9#

VSS_SRC

CLKREQ_4#

SRC_4#

SRC_4

VDD_SRC_IO

CLKREQ_3#

SLG8SP553VTR_QFN72_10x10

36

R_PCIE_SATA# R_PCIE_SATA

R_PCIE_ICH# R_PCIE_ICH

SSCDREFCLK

CLK_SMBDATA 15,16

CLK_SMBCLK 15,16

Deciphered Date

1

2

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

2

1

C203

0.1U_0402_16V4Z

2

10U_0805_10V4Z

1

C209

C208

2

0.1U_0402_16V4Z

R127 0_0402_5%R127 0_0402_5%

1 2

R131 0_0402_5%R131 0_0402_5%

1 2

R133 475_0402_1%R133 475_0402_1%

1 2

R135 0_0402_5%R135 0_0402_5%

1 2

R137 0_0402_5%R137 0_0402_5%

1 2

+1.05VS_CK505

H_STP_PCI# H_STP_CPU#

1

C204

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C210

1

C211

2

0.1U_0402_16V4Z

H_STP_PCI# 22 H_STP_CPU# 22

1

C205

0.1U_0402_16V4Z

2

1

C212

2

CLK_MCH_3GPLL 9 CLK_MCH_3GPLL# 9CLK_MCH_BCLK#9

CLKREQ#_6 26

CLK_PCIE_MCARD2 26 CLK_PCIE_MCARD2# 26

1

XDP/ITP

3G_PLL

MiniCard_2(WLAN)

delete TV on 09/17 need check clkreq#

delete clock for cardreader on 09/18

R_CLK_PCIE_LAN# R_CLK_PCIE_LAN

R152 0_0402_5%R152 0_0402_5% R153 0_0402_5%R153 0_0402_5%

CLKREQ#_9

R190 475_0402_1%R190 475_0402_1%

1 2 1 2 1 2

CLK_PCIE_LAN# 25

CLK_PCIE_LAN 25

LAN_CLKREQ# 25

delete New card on 09/17 need check clkreq#

R_CLKREQ#_C

R166 0_0402_5%R166 0_0402_5%

1 2

R168 0_0402_5%R168 0_0402_5%

1 2

R170 0_0402_5%R170 0_0402_5%

1 2

R172 0_0402_5%R172 0_0402_5%

1 2

R176 0_0402_5%R176 0_0402_5%

1 2

R177 0_0402_5%R177 0_0402_5%

1 2

2

R162 475_0402_1%R162 475_0402_1%

1 2

CLK_PCIE_SATA# 21 CLK_PCIE_SATA 21

CLK_PCIE_ICH# 22 CLK_PCIE_ICH 22

MCH_SSCDREFCLK# 9 MCH_SSCDREFCLK 9

CLKREQ#_C 22

CLKREQ#_9

R191 10K_0402_5%

1 2

@

SATA

ICH

NB_SSC (UMA)

02/13 Add 12P on CLK_14M_ICH for WWAN noise

C215

@C215

@

5P_0402_50V8C

C216

12P_0402_50V8J

C217

@C217

@

4.7P_0402_50V8C

4.7P_0402_50V8C C218

@C218

@

4.7P_0402_50V8C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Clock Generator CK505

Montevina UMA LA6121P

12

1

CLK_48M_ICH

CLK_14M_ICH

CLK_PCI_ICH

CLK_PCI_EC

LAN

0.2

17 46Thursday, April 15, 2010

0.2

A

1 1

CRT Connector

+5VS +5VS

C221

0.1U_0402_16V4Z

1 2

1

5

U4

U4 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

2 2

CRT_HSYNC11

CRT_VSYNC11

CRT_HSYNC

CRT_VSYNC

P

A2Y

G

3

4

OE#

B

C222

0.1U_0402_16V4Z

1 2

HSYNC_G_A

1

5

P

A2Y

G

3

VSYNC_G_A D_VSYNC

4

OE#

U5

U5 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

R184

1 2

R189

1 2

0_0603_5%

RED

GREEN

BLUE

D_HSYNC

1

C223

5P_0402_50V8C

2

C

D4

2 1

RB491D_SC59-3

1

C224

5P_0402_50V8C

2

F1

1.1A_6VDC_FUSE

2.2K_0402_5%

D_DDCDATA

D_DDCCLK

21

R185

W=40mils

0.1U_0402_16V4Z

0.1U_0402_16V4Z C220

C220

JCRT1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

16

GND

17

GND

SUYIN_070546FR015S265ZR

CONN@

12

2.2K_0402_5%

R186

12

D

+CRTVDD+RCRT_VCC+5VS

1

2

+3VS+CRTVDD +CRTVDD

2

6 1

Q5A

2N7002DW-7-F_SOT363-6

E

BLUE GREEN RED

D5

@D5

@

+3VS

12

R187

2.2K_0402_5%

5

3

4

Q5B

1

2

3

DAN217T146_SC59-3

R188

2.2K_0402_5%

3VDDCDA

3VDDCCL

@D6

@

D6

1

2

3

D7

@D7

@

2

DAN217T146_SC59-3

3VDDCDA 11

3VDDCCL 11

Place close to JCRT1

1

3

+CRTVDD

DAN217T146_SC59-3

CRT Termination/EMI Filter

3 3

M_RED11

M_GREEN11

M_BLUE11

4 4

A

B

12

R195

R196

150_0402_1%

M_RED

M_GREEN

2.2P_0402_50V8C

12

R197

150_0402_1%

2.2P_0402_50V8C

1

2

C225

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C226

1

2

C227

C

11/07 Change CRT lounting NB-->Docking-->CRT connector

L2

1 2

NBQ100505T-800Y-N_2P

L3

1 2

NBQ100505T-800Y-N_2P

L4

1 2

NBQ100505T-800Y-N_2P

2.2P_0402_50V8C

2007/08/28 2006/07/26

2.2P_0402_50V8C

1

2

C228

C229

Compal Secret Data

Deciphered Date

RED

GREEN

BLUEM_BLUE

2.2P_0402_50V8C

1

2

C230

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

CRT Connector

Montevina UMA LA6121P

18 46Thursday, April 15, 2010

E

0.2

5

INVPWR_B++LCDVDD+3VS

C236

C235

D D

C C

C235

12

680P_0402_50V7K

USB20_P422 USB20_N422

DMIC_DAT28 DMIC_CLK28

BKOFF#31

DDC2_CLK11

DDC2_DATA11

C237

1

12

2

680P_0402_50V7K

USB20_P4 USB20_N4

DMIC_DAT DMIC_CLK

INV_PWM_R

BKOFF#

DDC2_CLK DDC2_DATA

1

C434

C434 680P_0402_50V7K

680P_0402_50V7K

2

LVDS CONN & USB Camera + Dig Mic

JLVDS1

680P_0402_50V7K

+5VS

delete Pin28 LOG PWR.10/26

JLVDS1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

39 GND141GND2

ACES_87142-4041-BS

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

4

LVDS_A2LVDS_A2+

LVDS_A1LVDS_A1+

LVDS_A0LVDS_A0+

LVDS_ACLKLVDS_ACLK+

delete DAC_BRIG 10/26

INV_PWM_R

+3VS

R596

1 2 1 2

LVDS_A2- 11 LVDS_A2+ 11

LVDS_A1- 11 LVDS_A1+ 11

LVDS_A0- 11 LVDS_A0+ 11

LVDS_ACLK- 11 LVDS_ACLK+ 11

0_0402_5%@

INV_PWM_GL40 11 INV_PWM 31

R5940_0402_5% R5940_0402_5%

3

C231

0.1U_0402_16V4Z

BKOFF#

R245

10K_0402_5%

1 2

1

2

1

C232

0.1U_0402_16V4Z

2

C71

@C71

@

470P_0402_50V7K~D

1

2

02/20 Change to 0805 size

470_0805_5%

@

470_0805_5%

Limited Current < 1A

2

+5VALW+LCDVDD+LCDVDD

12

R198

61

2

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6 Q8A

Q8A

ENAVDD11

100K_0402_5%

R201

12

R199

1M_0402_5%

5

12

R200

100K_0402_5%

3

Q8B

Q8B 2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

4

Avoid Panel display garbage after power on.

C233

4.7U_0805_10V4Z

12

1

+LCDVDD

1

2

D

1 3

C238

0.047U_0402_16V7K

Q7

Q7 AO3413_SOT23-3

AO3413_SOT23-3

+3VS

S

G

C234

1

2

01/03 Change to 0.047u to meet T1 timing

4.7U_0805_10V4Z

0308_Install all cap for EMI request.

INVPWR_B+B+

DDC2_CLK DDC2_DATA

C1401 100P_0402_50V8J@ C1401 100P_0402_50V8J@

1 2

C1402 100P_0402_50V8J@ C1402 100P_0402_50V8J@

1 2

0831 EMI request

R202

2.2K_0402_5%

DDC2_CLK DDC2_DATA

+3VS

1 2

R203

2.2K_0402_5%

1 2

Must close JLVDS1pin 24、、、、26

DMIC_CLK

DMIC_DAT

1

C302

220P_0402_25V8J

2

C303

220P_0402_25V8J

@

L5 0_0805_5%

1 2

L6

1 2

FBMA-L11-201209-221LMA30T_0805

0308_Reserve L10 and install L11.

11/09 EMI reserver

B B

delete +5VS transfer to +USB_CAM.10/26

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LCD CONN.

Montevina UMA LA6121P

19 46Thursday, April 15, 2010

1

0.2

5

+3VS

R272 8.2K_0402_5%R272 8.2K_0402_5%

1 2

R273 8.2K_0402_5%R273 8.2K_0402_5%

1 2

R274 8.2K_0402_5%R274 8.2K_0402_5%

1 2

R275 8.2K_0402_5%R275 8.2K_0402_5%

1 2

R276 8.2K_0402_5%R276 8.2K_0402_5%

D D

C C

1 2

R277 8.2K_0402_5%R277 8.2K_0402_5%

1 2

R278 8.2K_0402_5%R278 8.2K_0402_5%

1 2

R279 8.2K_0402_5%R279 8.2K_0402_5%

1 2

+3VS

R281 8.2K_0402_5%R281 8.2K_0402_5%

1 2

R282 8.2K_0402_5%R282 8.2K_0402_5%

1 2

R283 8.2K_0402_5%R283 8.2K_0402_5%

1 2

R284 8.2K_0402_5%R284 8.2K_0402_5%

1 2

R285 8.2K_0402_5%R285 8.2K_0402_5%

1 2

R286 8.2K_0402_5%R286 8.2K_0402_5%

1 2

R287 8.2K_0402_5%R287 8.2K_0402_5%

1 2

R288 8.2K_0402_5%R288 8.2K_0402_5%

R289 8.2K_0402_5%R289 8.2K_0402_5%

R290 8.2K_0402_5%R290 8.2K_0402_5%

R292 8.2K_0402_5%R292 8.2K_0402_5%

R293 8.2K_0402_5%R293 8.2K_0402_5%

12

1 2

PCI_DEVSEL#

PCI_STOP#

PCI_TRDY#

PCI_FRAME#

PCI_PLOCK#

PCI_IRDY#

PCI_SERR#

PCI_PERR#

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

PCI_PIRQE#

PCI_PIRQF#

PCI_PIRQG#

PCI_PIRQH#

PCI_REQ0#

PCI_REQ1#

PCI_REQ2#

PCI_REQ3#

4

U12B

D11

AD0

C8

AD1

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

D9

E12

E9 C9

E10

B7 C7 C5

G11

F8

F11

E7 A3 D2

F10

D5

D10

B3 F7 C3 F3 F4 C1

G7

H7 D1

G5

H6

G1

H3

J5

E1

J6

C4

ICH9-M ES_FCBGA676

PCI

AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

Interrupt I/F

PIRQA# PIRQB# PIRQC# PIRQD#

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2 PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

3

PCI_REQ0#

F1

PCI_GNT0#

G4

PCI_REQ1#

B6 A7

PCI_REQ2#

F13 F12

PCI_REQ3#

E6

PCI_GNT3#

F6

D8 B4 D6 A5

PCI_IRDY#

D3 E3

PCI_RST#

R1

PCI_DEVSEL#

C6

PCI_PERR#

E4

PCI_PLOCK#

C2

PCI_SERR#

J4

PCI_STOP#

A4

PCI_TRDY#

F5

PCI_FRAME#

D7

PLT_RST#

C14

CLK_PCI_ICH

D4

PCI_PME#

R2

3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistance.

PCI_PIRQE#

H4

PCI_PIRQF#

K6

PCI_PIRQG#

F2

PCI_PIRQH#

G2

PCI_RST# 31

PCI_SERR# 31

PLT_RST# 9,25,26 CLK_PCI_ICH 17 PCI_PME# 31

2

Place closely pin D4

CLK_PCI_ICH

12

@

R280

R280 10_0402_5%

10_0402_5%

1

@

C425

8.2P_0402_50V

2

1

Delete GS function

B B

PCI_GNT3#

A A

Low= A16 swap override Enble High= Default

R294

@R294

@

1 2

5

1K_0402_5%

*

A16 swap override Strap

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

SPI_CS1#_R22

4

1

01

1

SPI_CS1#_R

PCI_GNT0#

Boot BIOS Location

SPI

PCI

LPC

*

@

R295

1 2

R296

@

1 2

1K_0402_5%

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

Montevina UMA LA6121P

20 46Thursday, April 15, 2010

1

0.2

5

+RTCVCC

1 2

R297 1M_0402_5%R297 1M_0402_5%

1 2

R299 330K_0402_5%R299 330K_0402_5%

1 2

R300 330K_0402_5%R300 330K_0402_5%

1 2

D D

C C

R302 180K_0402_5%R302 180K_0402_5%

HDA_BITCLK_CODEC28

add pull high to +3VS 09/22

P- HDD

B B

Add 12p on HDA_SDOUT and HDA_SDOUT

HDA_SDOUT_CODEC

C312 12P_0402_50V8J@C312 12P_0402_50V8J@

SM_INTRUDER#

LAN100_SLP

ICH_INTVRMEN

ICH_SRTCRST#

C426

0.1U_0402_16V4Z

+RTCVCC

12P_0402_50V8J

C331

1 2

R312 33_0402_5%R312 33_0402_5%

HDA_SYNC_CODEC28

HDA_RST#_CODEC28

HDA_SDIN028

delete MDC and HDMI on 09/17

1 2

HDA_SDOUT_CODEC28

1

2

0_0402_5%

R307

1 2

20K_0402_5%

1U_0603_10V4Z

HDA_BITCLK

R316 33_0402_5%R316 33_0402_5%

R317 33_0402_5%R317 33_0402_5%

SATA_LED#32

SATA_RXN0_C24

SATA_RXP0_C24 SATA_TXN024 SATA_TXP024

12

@

R303

0_0402_5%

C427

1 2

+3VS

12

@

R304

1

2

1 2

R321 33_0402_5%R321 33_0402_5%

SATA_TXN0 SATA_TXP0

12

CLRP2

CLRP2 SHORT PADS

SHORT PADS

R313

1 2

10K_0402_5%

4

ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

+1.5VS

R311

24.9_0402_1%

1 2

T55PAD T55PAD T56PAD T56PAD

0.01U_0402_16V7K

C431

1 2

C433

1 2

0.01U_0402_16V7K

Low = Internal VR Disabled High = Internal VR Enabled(Default)

High = Internal VR Enabled(Default)

ICH_RTCX1 ICH_RTCX2

ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER#

ICH_INTVRMEN LAN100_SLP

GLAN_COMP

HDA_BITCLK HDA_SYNC

HDARST#

HDA_SDIN0

HDA_SDOUT

SATA_LED#

SATA_TXN0_C SATA_TXP0_C

AH4

AG4 AH3

AG5

AG7

AG8

AJ16

AH16

AF17

AG17

AH13

AJ13

AG14

AF14

C23 C24

A25 F20 C22

B22 A22

E25

C13

F14 G13 D14

D13 D12 E13

B10

B28 B27

AF6

AE7

AF4

AE5

AE8

U12A

RTCX1 RTCX2

RTCRST# SRTCRST# INTRUDER#

INTVRMEN LAN100_SLP

GLAN_CLK

LAN_RSTSYNC

LAN_RXD0 LAN_RXD1 LAN_RXD2

LAN_TXD_0 LAN_TXD_1 LAN_TXD_2

GPIO56

GLAN_COMPI GLAN_COMPO

HDA_BIT_CLK HDA_SYNC

HDA_RST#

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDOUT

HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34

SATALED#

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

ICH9-M ES_FCBGA676

3

RTC

LAN / GLAN

IHDA

LPCCPU

SATA

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT# INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATA_CLKN SATA_CLKP

SATARBIAS#

SATARBIAS

NMI

LPC_AD0

K5

LPC_AD1

K4

LPC_AD2

L6

LPC_AD3

K2

LPC_FRAME#

K3

J3 J1

GATEA20

N7

H_A20M#

AJ27

AJ25

H_DPSLP#

AE23

R_H_FERR#

AJ26

H_PWRGOOD

AD22

H_IGNNE#

AF25

H_INIT#

AE22

H_INTR

AG25

KB_RST#

L3

H_NMI

AF23

H_SMI#

AF24

H_STPCLK#

AH27

THRMTRIP_ICH#

AG26

AG27

AH11 AJ11

SATA_ITX_DRX_N4

AG12

SATA_ITX_DRX_P4

AF12

AH9 AJ9 AE10 AF10

CLK_PCIE_SATA#

AH18

CLK_PCIE_SATA

AJ18 AJ7 AH7

R309

R310

C790 0.01U_0402_16V7KC790 0.01U_0402_16V7K C816 0.01U_0402_16V7KC816 0.01U_0402_16V7K

R322

1 2

24.9_0402_1%

Within 500 mils

2

PV

：：：：

follow check list ver:1.5 change to 8.2K ohm

GATEA20

KB_RST#

@R305

H_DPRSTP#

LPC_AD[0..3] 26,31

LPC_FRAME# 26,31

T54 PADT54 PAD

GATEA20 31 H_A20M# 6

1 2

0_0402_5%

1 2

56_0402_5%

H_PWRGOOD 7

H_IGNNE# 6

H_INIT# 6 H_INTR 6

KB_RST# 31

H_NMI 6 H_SMI# 6

H_STPCLK# 6

R319 54.9_0402_1%R319 54.9_0402_1%

1 2

1 2 1 2

02/13 Reserve cap on HDA_BITCLK for WWAN noise issue

HDA_BITCLK_CODEC

H_DPSLP#

H_DPRSTP#H_DPRSTP_R#

H_FERR#

3/28 add 56ohm

+VCCP

C67 33P_0402_50V8KC67 33P_0402_50V8K

1 2

@

@R306

@

H_DPRSTP# 7,9,41

H_DPSLP# 7

within 2" from R379

12

R315

R315 56_0402_5%

56_0402_5%

placed within 2" from ICH9M

SATA_DTX_C_IRX_N4 24 SATA_DTX_C_IRX_P4 24 SATA_ITX_RPI_DRX_N4 24 SATA_ITX_RPI_DRX_P4 24

CLK_PCIE_SATA# 17 CLK_PCIE_SATA 17

+3VS

R298

1 2

8.2K_0402_5%

R301

1 2

10K_0402_5%

+VCCP

R305

1 2

56_0402_5%

R306

1 2

56_0402_5%

+VCCP

R308

R308 56_0402_5%

56_0402_5%

1 2

H_THERMTRIP# 6,9

1

H_FERR# 6

ODD

XOR CHAIN ENTRANCE STRAP:RSVD

RTC Battery

+3VS

BATT1

R325

@R325

@

1 2

R326

@R326

@

1 2

A A

ICH_RSVD HDA_SDOUT_CODEC

0

1

1 1

1K_0402_5%

HDA_SDOUT_CODEC

ICH_RSVD

0

1

0

5

ICH_RSVD 22

R328

1 2

10M_0402_5%

1

C436

15P_0402_50V8J

2

Y2

1 4

2 3

32.768KHZ_12.5P_MC-146

0821 Change C436 and C437 to 15PF

32.768KHZ_12.5P_MC-146

4

ICH_RTCX1

ICH_RTCX2

1

C437

15P_0402_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

BATT1

- +

ML1220T13RE

@

Compal Secret Data

Deciphered Date

560_0603_5%

12

1 2

Change BATT1 P/N : SP093PA0200 (Panasonic) SP093MX0000 (MAXELL)

R249

+RTC_BATT

R250

560_0603_5%

1 2

2

Modify as NBLB2. 11/02

D12

2

1

BAS40-04_SOT23

Title

Size Document Number Rev

Custom

Date: Sheet of

+CHGRTC

3

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

Montevina UMA LA6121P

12

C193

0.1U_0402_16V4Z

+RTCVCC

1

21 46Thursday, April 15, 2010

0.2

5

04/29 MV-1 add R337 clock REQ pull high

+3VS

1 2

R333 10K_0402_5%R333 10K_0402_5%

1 2

R334 8.2K_0402_5%@R334 8.2K_0402_5%@

1 2

R335 10K_0402_5%R335 10K_0402_5%

1 2

R336 8.2K_0402_5%@ R336 8.2K_0402_5%@

1 2

D D

C C

B B

A A

R337 10K_0402_5%R337 10K_0402_5%

1 2

R338 8.2K_0402_5%@ R338 8.2K_0402_5%@

1 2

R341 8.2K_0402_5%R341 8.2K_0402_5%

1 2

R344 8.2K_0402_5%R344 8.2K_0402_5%

1 2

R356 8.2K_0402_5%R356 8.2K_0402_5%

1 2

R349 8.2K_0402_5%R349 8.2K_0402_5%

1 2

R350 8.2K_0402_5%R350 8.2K_0402_5%

1 2

R351 8.2K_0402_5%R351 8.2K_0402_5%

1 2

R352 8.2K_0402_5%R352 8.2K_0402_5%

1 2

R357 8.2K_0402_5%R357 8.2K_0402_5%

1 2

R358 8.2K_0402_5%R358 8.2K_0402_5%

1 2

R359 10K_0402_5%R359 10K_0402_5%

1 2

R361 8.2K_0402_5%@ R361 8.2K_0402_5%@

1 2

R362 8.2K_0402_5%R362 8.2K_0402_5%

1 2

R365 10K_0402_5%@R365 10K_0402_5%@

+3VALW

1 2

R369 10K_0402_5%R369 10K_0402_5%

1 2

R371 8.2K_0402_5%R371 8.2K_0402_5%

1 2

R372 1K_0402_5%R372 1K_0402_5%

1 2

R374 10K_0402_5%R374 10K_0402_5%

1 2

R375 10K_0402_5%R375 10K_0402_5%

1 2

R376 10K_0402_5%R376 10K_0402_5%

1 2

R377 10K_0402_5%R377 10K_0402_5%

1 2

R378 10K_0402_5%R378 10K_0402_5%

1 2

R379 10K_0402_5%R379 10K_0402_5%

1 2

R373 10K_0402_5%R373 10K_0402_5%

1 2

R380 8.2K_0402_5%R380 8.2K_0402_5%

1 2

R381 8.2K_0402_5%R381 8.2K_0402_5%

+3VS +3VS

R745

@R745

@

10K_0402_5%

1 2

DIS/UMA

R746

R746 10K_0402_5%

10K_0402_5%

1 2

USB_OC#5 USB_OC#1 USB_OC#2 USB_OC#4

USB_OC#11 USB_OC#8 USB_OC#7 USB_OC#9

WXMIT_OFF# USB_OC#0 USB_OC#10 USB_OC#6

SIRQ

PM_CLKRUN#

OCP#

THERM_SCI#

CLKREQ#_C

PM_BMBUSY#

EC_SCI#

GPIO6

GPIO22

GPIO18

GPIO19

GPIO20

GPIO21

GPIO36

GPIO37

GPIO39

GPIO48

GPIO57

GPIO49

LINKALERT#

ICH_LOW_BAT#

ICH_PCIE_WAKE#

ICH_RI#

XDP_DBRESET#

S4_STATE#

ME_EC_CLK1

ME_EC_DATA1

GPIO10

EC_LID_OUT#

EC_SMI#

GPIO14

@R747

@

10K_0402_5%

1 2

R748

R748 10K_0402_5%

10K_0402_5%

1 2

RP27

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

RP28

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

RP29

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

5

Board ID

R747

17/14

+3VALW

10K_0402_5%

H_STP_PCI#17 H_STP_CPU#17

VGATE17,41

Delete GPIO6 function for cardreader on 09/18

EC_SCI#31 EC_SMI#31

Delete GPIO6 function for cardreader on 09/18

+3VS

delete New card function for GPIO48 on 09/17

11/17 Swap PCIE LAN and New card

WLAN

LAN

R331 2.2K_0402_5%R331 2.2K_0402_5% R332 2.2K_0402_5%R332 2.2K_0402_5%

ICH_SMBCLK17,26

ICH_SMBDATA17,26

+3VS

12

R340

@R340

@

R339

@R339

@

R366 Low High -->No

-->default boot

10K_0402_5%

R345 0_0402_5%R345 0_0402_5%

R353

100K_0402_5%

1 2

R364 8.2K_0402_5%R364 8.2K_0402_5%

+3VS

SB_SPKR28

GLAN_RXN25 GLAN_RXP25

delete New Card on 09/17

Delete HDCP ROM.11/09

SPI_CS1#_R20

Delete WXMIT_OFF# for WWAN. 1104

4

1 2 1 2

T57PAD T57PAD

XDP_DBRESET#6

PM_BMBUSY#9

EC_LID_OUT#31

1 2

ICH_PCIE_WAKE#25,26 SIRQ31 THERM_SCI#31

1 2

R225 0_0402_5%R225 0_0402_5%

1 2

R226 0_0402_5%@R226 0_0402_5%@

1 2

R366 1K_0402_5%@ R366 1K_0402_5%@

MCH_ICH_SYNC#9

ICH_RSVD21

OCP#6

T62PAD T62PAD

CLKREQ#_C17

1 2

R347

1 2

10K_0402_5%

T59PAD T59PAD

05/08 MV-1 Delete R739

delete TV on 09/17

PCIE_RXN326 PCIE_RXP326 PCIE_TXN326 PCIE_TXP326

GLAN_TXN25 GLAN_TXP25

C448 0.1U_0402_16V4ZC448 0.1U_0402_16V4Z C449 0.1U_0402_16V4ZC449 0.1U_0402_16V4Z

C452 0.1U_0402_16V4ZC452 0.1U_0402_16V4Z C453 0.1U_0402_16V4ZC453 0.1U_0402_16V4Z

4

1 2 1 2

T64PAD T64PAD T72PAD T72PAD

T73PAD T73PAD T74PAD T74PAD

ICH_SMBCLK ICH_SMBDATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1

ICH_RI#

SUS_STAT# XDP_DBRESET#

PM_BMBUSY#

EC_LID_OUT#

H_STP_PCI# R_STP_CPU#

PM_CLKRUN#

ICH_PCIE_WAKE# SIRQ THERM_SCI#

VGATE

OCP#

EC_SCI#_SB EC_SMI# EC_SCI#_GPIO12

17/14 GPIO18 GPIO20 GPIO22 DIS/UMA

CLKREQ#_C GPIO38 GPIO39 GPIO48 GPIO49 GPIO57

SB_SPKR MCH_ICH_SYNC# ICH_RSVD

USB_OC#029

USB_OC#229

12

G16

A13 E17

C17

B18

F19

R4

G19

M6

A17

A14 E19

L4

E20

M5

AJ23

D21

A20

AG19

GPIO6

AH21 AG21

A21 C12 C21

AE18

K1

AF8

AJ22

A9

D19

T47PAD T47PAD

L1 AE19 AG22 AF21 AH24

A8

M7

AJ24

B21

AH20

AJ20 AJ21

PCIE_RXN3 PCIE_RXP3 PCIE_C_TXN3 PCIE_C_TXP3

GLAN_RXN GLAN_RXP GLAN_TXN_C GLAN_TXP_C

SPI_CS1#_R

USB_OC#0

USB_OC#1

USB_OC#2

WXMIT_OFF# USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11

USBRBIAS

Within 500 mils

R384

22.6_0402_1%

3

U12C

SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1

RI#

SUS_STAT#/LPCPD# SYS_RESET#

PMSYNC#/GPIO0

SMBALERT#/GPIO11

STP_PCI# STP_CPU#

CLKRUN#

WAKE# SERIRQ THRM#

VRMPWRGD

TP11

GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5

SPKR MCH_SYNC# TP3 TP8 TP9 TP10

ICH9-M ES_FCBGA676

SMB

U12D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9-M ES_FCBGA676

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

clocks

SYS / GPIOGPIOMISC

Power MGT

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

Controller Link

PCI - Express

SPI

USB

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

MEM_LED/GPIO24

WOL_EN/GPIO9

DMI0RXN DMI0RXP

DMI0TXN DMI0TXP

DMI1RXN DMI1RXP

DMI1TXN DMI1TXP

DMI2RXN DMI2RXP

DMI2TXN DMI2TXP

DMI3RXN DMI3RXP

DMI3TXN DMI3TXP

DMI_CLKN DMI_CLKP

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P

2007/08/28 2006/03/10

GPIO21

AH23

GPIO19

AF19

GPIO36

AE21

GPIO37

AD20

CLK_14M_ICH

H1

CLK_48M_ICH

AF3

ICH_SUSCLK

P1

SLP_S3#

C16

SLP_S4#

E16

SLP_S5#

G17

S4_STATE#

C10

PM_PWROK

G20

R348 0_0402_5%R348 0_0402_5%

M2

1 2

ICH_LOW_BAT#

B13

PWRBTN_OUT#

R3

D20

R_EC_RSMRST#

D22

CK_PWRGD

R5

M_PWROK

R6

B16

CL_CLK0

F24 B19

CL_DATA0

F22 C19

CL_VREF0_ICH

C25

CL_VREF1_ICH

A19

CL_RST#

F21 D18

Change XMIT_OFF to EC contral.01/11

A16

GPIO10

C18

GPIO14

C11

LAN_WOL_EN

C20

DMI_RXN0

V27

DMI_RXP0

V26

DMI_TXN0

U29

DMI_TXP0

U28

DMI_RXN1

Y27

DMI_RXP1

Y26

DMI_TXN1

W29

DMI_TXP1

W28

DMI_RXN2

AB27

DMI_RXP2

AB26

DMI_TXN2

AA29

DMI_TXP2

AA28

DMI_RXN3

AD27

DMI_RXP3

AD26

DMI_TXN3

AC29

DMI_TXP3

AC28

CLK_PCIE_ICH#

T26

CLK_PCIE_ICH

T25

AF29

DMI_IRCOMP

AF28

USB20_N0

AC5

USB20_P0

AC4

USB20_N1

AD3

USB20_P1

AD2

USB20_N2

AC1

USB20_P2

AC2 AA5 AA4

USB20_N4

AB2

USB20_P4

AB3

USB20_N5

AA1

USB20_P5

AA2

USB20_N6

W5

USB20_P6

W4

USB20_N7

Y3

USB20_P7

Y2 W1 W2 V2 V3 U5 U4 U1 U2

Compal Secret Data

R370

100K_0402_5%

R382 24.9_0402_1%R382 24.9_0402_1%

modify cardreader from PCIE to USB on 0918

Deciphered Date

2

Modify back to GPIO19 on 09/22

CLK_14M_ICH 17 CLK_48M_ICH 17

ICH_SUSCLK 31

SLP_S3# 31 SLP_S4# 31,33 SLP_S5# 31

PM_PWROK 9,31

PWRBTN_OUT# 31

R354 100_0402_5%R354 100_0402_5% R355 10K_0402_5%R355 10K_0402_5%

CK_PWRGD 17

M_PWROK 9,31

CL_CLK0 9

CL_DATA0 9

CL_RST# 9

T63 PADT63 PAD

12

+3VALW

DMI_RXN0 9 DMI_RXP0 9 DMI_TXN0 9 DMI_TXP0 9

DMI_RXN1 9 DMI_RXP1 9 DMI_TXN1 9 DMI_TXP1 9

DMI_RXN2 9 DMI_RXP2 9 DMI_TXN2 9 DMI_TXP2 9

DMI_RXN3 9 DMI_RXP3 9 DMI_TXN3 9 DMI_TXP3 9

CLK_PCIE_ICH# 17 CLK_PCIE_ICH 17

1 2

USB20_N0 29 USB20_P0 29 USB20_N1 29 USB20_P1 29 USB20_N2 29 USB20_P2 29

USB20_N4 19 USB20_P4 19 USB20_N5 26 USB20_P5 26 USB20_N6 29 USB20_P6 29

USB20_N7 27 USB20_P7 27

2

Place closely pin AF3

R346 10K_0402_5%R346 10K_0402_5%

1 2

DPRSLPVR 9,41

11/17 Add +3VALW GD to

R_EC_RSMRST# 37

1 2 1 2

EC_RSMRST# to fix Battery mode can't boot issue

EC_RSMRST# 31

12

1

C442

C443

PM_PWROK R_EC_RSMRST#

CH751H-40PT_SOD323-2

R363

R363 453_0402_1%

453_0402_1%

2

NA lead free

0.1U_0402_16V4Z

12

1

R368

R368 453_0402_1%

453_0402_1%

2

0.1U_0402_16V4Z

2 1

#PV PWROK sequence issue

Within 500 mils

+1.5VS

USB-0 Daughter board

USB-1 Daughter board

USB-2 On Mather board

USB-4 Camera

USB-5 WLAN

USB-6 Bluetooth

USB-6 Cardreader

Title

ICH9(3/4)_DMI,USB,GPIO,PCIE

Size Document Number Rev

Custom

Montevina UMA LA6121P

Date: Sheet of

1

Place closely

+3VS

+3VALW

1

pin H1

CLK_14M_ICH

12

R343

@R343

@

10_0402_5%

1

C441

@C441

@

4.7P_0402_50V8C

2

22 46Thursday, April 15, 2010

CLK_48M_ICH

12

R342

@R342

@

10_0402_5%

1

C440

@C440

@

4.7P_0402_50V8C

2

R360

1 2

3.24K_0402_1%

R367

1 2

3.24K_0402_1%

D22

Compal Electronics, Inc.

0.2

5

+RTCVCC

20 mils

1

C454

2

0.1U_0402_16V4Z

40 mils

1

+

C459

2

220U_6.3V

10U_0805_10V4Z

1

C477

2

1U_0603_10V4Z

1

C483

2

1

C487

2

10U_0805_10V4Z

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

1

2

1

2

1

2

+1.5VS

C488

C462

R387

1 2

+5VS +3VS

R386

100_0402_5%

R388

10_0402_5%

+1.5VS

0316 change design

+1.5VS

12

+3VALW+5VALW

12

R389

1 2

CHB1608U301_0603

+3VS

C485

0.1U_0402_16V4Z

CHB1608U301_0603

21

D9

CH751H-40_SC76

ICH_V5REF_RUN

20 mils

1

C465

0.1U_0402_10V6K

2

21

D10

CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C472

0.1U_0402_10V6K

2

+1.5VS

0.1U_0402_16V4Z

1

R390 CHB1608U301_0603R390 CHB1608U301_0603

1 2

+1.5VS

2

5

C458

1

C476

2

D D

C C

B B

A A

ICH_V5REF_RUN

ICH_V5REF_SUS

10U_0805_10V4Z

1

C456

C460

2

2.2U_0603_6.3V4Z

+1.5VS

C478

1U_0603_10V4Z

+1.5VS

C481

1U_0603_10V4Z

C484

0.1U_0402_16V4Z

VCC_LAN1_05_INT_ICH_1

T69T69

VCC_LAN1_05_INT_ICH_2

T70T70

R391

1 2

+1.5VS

CHB1608U301_0603

0316 change design

1

2

1

2

1

2

1

2

C489

4.7U_0805_10V4Z

1

+3VS

2

4

U12F

A23

VCCRTC

A6

V5REF

AE1

V5REF_SUS

AA24

VCC1_5_B[01]

AA25

VCC1_5_B[02]

AB24

VCC1_5_B[03]

AB25

VCC1_5_B[04]

AC24

VCC1_5_B[05]

AC25

VCC1_5_B[06]

AD24

VCC1_5_B[07]

AD25

VCC1_5_B[08]

AE25

VCC1_5_B[09]

AE26

VCC1_5_B[10]

AE27

VCC1_5_B[11]

AE28

VCC1_5_B[12]

AE29

VCC1_5_B[13]

F25

VCC1_5_B[14]

G25

VCC1_5_B[15]

H24

VCC1_5_B[16]

H25

VCC1_5_B[17]

J24

VCC1_5_B[18]

J25

VCC1_5_B[19]

K24

VCC1_5_B[20]

K25

VCC1_5_B[21]

L23

VCC1_5_B[22]

L24

VCC1_5_B[23]

L25

VCC1_5_B[24]

M24

VCC1_5_B[25]

M25

VCC1_5_B[26]

N23

VCC1_5_B[27]

N24

VCC1_5_B[28]

N25

VCC1_5_B[29]

P24

VCC1_5_B[30]

P25

VCC1_5_B[31]

R24

VCC1_5_B[32]

R25

VCC1_5_B[33]

R26

VCC1_5_B[34]

R27

VCC1_5_B[35]

T24

VCC1_5_B[36]

T27

VCC1_5_B[37]

T28

VCC1_5_B[38]

T29

VCC1_5_B[39]

U24

VCC1_5_B[40]

U25

VCC1_5_B[41]

V24

VCC1_5_B[42]

V25

VCC1_5_B[43]

U23

VCC1_5_B[44]

W24

VCC1_5_B[45]

W25

VCC1_5_B[46]

K23

VCC1_5_B[47]

Y24

VCC1_5_B[48]

Y25

VCC1_5_B[49]

AJ19

VCCSATAPLL

AC16

VCC1_5_A[01]

AD15

VCC1_5_A[02]

AD16

VCC1_5_A[03]

AE15

VCC1_5_A[04]

AF15

VCC1_5_A[05]

AG15

VCC1_5_A[06]

AH15

VCC1_5_A[07]

AJ15

VCC1_5_A[08]

AC11

VCC1_5_A[09]

AD11

VCC1_5_A[10]

AE11

VCC1_5_A[11]

AF11

VCC1_5_A[12]

AG10

VCC1_5_A[13]

AG11

VCC1_5_A[14]

AH10

VCC1_5_A[15]

AJ10

VCC1_5_A[16]

AC9

VCC1_5_A[17]

AC18

VCC1_5_A[18]

AC19

VCC1_5_A[19]

AC21

VCC1_5_A[20]

G10

VCC1_5_A[21]

G9

VCC1_5_A[22]

11mA

AC12

VCC1_5_A[23]

AC13

VCC1_5_A[24]

AC14

VCC1_5_A[25]

AJ5

VCCUSBPLL

AA7

VCC1_5_A[26]

AB6

VCC1_5_A[27]

AB7

VCC1_5_A[28]

AC6

VCC1_5_A[29]

AC7

VCC1_5_A[30]

A10

VCCLAN1_05[1]

A11

VCCLAN1_05[2]

A12

VCCLAN3_3[1]

B12

VCCLAN3_3[2]

23mA

A27

VCCGLANPLL

80mA

D28

VCCGLAN1_5[1]

D29

VCCGLAN1_5[2]

E26

VCCGLAN1_5[3]

E27

VCCGLAN1_5[4]

1mA

A26

VCCGLAN3_3

ICH9-M ES_FCBGA676

4

11mA

G3: 6uA

2mA

646mA

47mA

1342mA

VCCA3GP

ARX

212mA

ATX

ATXARX

USB CORE

1634mA

11mA

GLAN POWER

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16]

CORE

VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]

23mA

V_CPU_IO[1]

48mA

V_CPU_IO[2]

2mA

VCCP_CORE

308mA

PCI

11mA

VCCSUSHDA

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04]

VCCPSUS

VCCSUS3_3[05]

VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

VCCPUSB

VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]

19/73/73mA19/78/78mA

VCCCL3_3[1] VCCCL3_3[2]

VCCDMIPLL

VCC_DMI[1] VCC_DMI[2]

VCC3_3[01] VCC3_3[02] VCC3_3[07]

VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]

VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14]

VCCHDA

VCCCL1_05

VCCCL1_5

3

A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

R29

W23 Y23

AB23 AC23

AG29 AJ6 AC10

AD19 AF20 AG24 AC20

B9 F9 G3 G6 J2 J7 K7

AJ4

AJ3

AC8 F17

AD8

F18

A18 D16 D17 E22

AF1

T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7

G22 G23

A24 B24

+VCCP

0.1U_0402_16V4Z

VCCSUS1_5_ICH_1

VCCSUS1_5_ICH_2

0.1U_0402_16V4Z

VCCCL1_05_ICH

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

0.1U_0402_16V4Z

1

C457

C455

2

R385

1

C464

2

+3VS

0.1U_0402_16V4Z

1

2

1 2

12

@

0.1U_0402_16V4Z

R385

1 2

CHB1608U301_0603

1

C463

10U_0805_10V4Z

2

+VCCP

0.1U_0402_16V4Z

1

C470

2

R212

@R212

@

0_0402_5%

R742 0_0603_5%R742 0_0603_5%

1 2

R740 0_0603_5%R740 0_0603_5%

1 2

R741

R741 150_0402_1%

150_0402_1%

Compal Secret Data

C471

Deciphered Date

+1.5VS

+3VALW

0.01U_0402_16V7K

1

C461

2

22U_0805_6.3VAM

0.1U_0402_16V4Z

1

C469

2

+3VS

1

2

1

2

1

2

+1.5VS

C473

1

C475

T65T65

2

T66T66

T67T67

T68T68

+3VALW

1

C480

C479

2

+3VALW

1

C482

4.7U_0603_6.3V6M

2

T71T71

@

C486

C486 1U_0603_10V4Z

1U_0603_10V4Z

2007/08/28 2006/03/10

+VCCP

4.7U_0603_6.3V6M

C466

1

2

0.1U_0402_16V4Z

C467

1

2

(DMI)

0.1U_0402_16V4Z

2

C468

1

2

1

C474

2

+3VS

U12E

AA26

VSS[001]

AA27

VSS[002]

AA3

VSS[003]

AA6

VSS[004]

AB1

VSS[005]

AA23

VSS[006]

AB28

VSS[007]

AB29

VSS[008]

AB4

VSS[009]

AB5

VSS[010]

AC17

VSS[011]

AC26

VSS[012]

AC27

VSS[013]

AC3

VSS[014]

AD1

VSS[015]

AD10

VSS[016]

AD12

VSS[017]

AD13

VSS[018]

AD14

VSS[019]

AD17

VSS[020]

AD18

VSS[021]

AD21

VSS[022]

AD28

VSS[023]

AD29

VSS[024]

AD4

VSS[025]

AD5

VSS[026]

AD6

VSS[027]

AD7

VSS[028]

AD9

VSS[029]

AE12

VSS[030]

AE13

VSS[031]

AE14

VSS[032]

AE16

VSS[033]

AE17

VSS[034]

AE2

VSS[035]

AE20

VSS[036]

AE24

VSS[037]

AE3

VSS[038]

AE4

VSS[039]

AE6

VSS[040]

AE9

VSS[041]

AF13

VSS[042]

AF16

VSS[043]

AF18

VSS[044]

AF22

VSS[045]

AH26

VSS[046]

AF26

VSS[047]

AF27

VSS[048]

AF5

VSS[049]

AF7

VSS[050]

AF9

VSS[051]

AG13

VSS[052]

AG16

VSS[053]

AG18

VSS[054]

AG20

VSS[055]

AG23

VSS[056]

AG3

VSS[057]

AG6

VSS[058]

AG9

VSS[059]

AH12

VSS[060]

AH14

VSS[061]

AH17

VSS[062]

AH19

VSS[063]

AH2

VSS[064]

AH22

VSS[065]

AH25

VSS[066]

AH28

VSS[067]

AH5

VSS[068]

AH8

VSS[069]

AJ12

VSS[070]

AJ14

VSS[071]

AJ17

VSS[072]

AJ8

VSS[073]

B11

VSS[074]

B14

VSS[075]

B17

VSS[076]

B2

VSS[077]

B20

VSS[078]

B23

VSS[079]

B5

VSS[080]

B8

VSS[081]

C26

VSS[082]

C27

VSS[083]

E11

VSS[084]

E14

VSS[085]

E18

VSS[086]

E2

VSS[087]

E21

VSS[088]

E24

VSS[089]

E5

VSS[090]

E8

VSS[091]

F16

VSS[092]

F28

VSS[093]

F29

VSS[094]

G12

VSS[095]

G14

VSS[096]

G18

VSS[097]

G21

VSS[098]

G24

VSS[099]

G26

VSS[100]

G27

VSS[101]

G8

VSS[102]

H2

VSS[103]

H23

VSS[104]

H28

VSS[105]

H29

VSS[106]

ICH9-M ES_FCBGA676

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

Montevina UMA LA6121P

1

VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]

1

H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

23 46Wednesday, April 14, 2010

0.2

5

HDD Connector

JP3

1

GND

2

A+

3

A-

Reserved

23

NC

24

NC

SANTA_191901-1

CONN@

GND

GND GND GND

GND

BB+

V33 V33 V33

V5 V5 V5

V12 V12 V12

D D

4 5 6 7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

0.01U_0402_16V7K

SATA_RXN0 SATA_RXP0 SATA_RXP0_C

0.01U_0402_16V7K

+3VS_HDD1

+5VS

SATA_TXP0 SATA_TXN0

SATA_RXN0_C

C494

12

C495

12

Near CONN side.

SATA_RXN0_C 21

SATA_RXP0_C 21

SATA_TXP0 21

SATA_TXN0 21

4

Pleace near HDD CONN (JP3)

+5VS

1

C490

2

Pleace near HDD CONN

R392

@R392

@

1 2

+3VS

0_0805_5%

C491

10U_0805_10V4Z

C496

@C496

@

1

C492

C493

2

1

2

0.1U_0402_16V4Z

@C497

@

1000P_0402_50V7K

C497

0.1U_0402_16V4Z

+3VS_HDD1

1

C498

@C498

@

2

0.1U_0402_16V4Z

3

1

2

0.1U_0402_16V4Z

1

2

1U_0603_10V4Z

2

1

C C

B B

CD-ROM Connector

JP5

1

GND

2

A+

3

A-

4

15

GND

14

GND

SANTA_204901-1

CONN@

GND

GND GND

B-

B+

DP +5V +5V

MD

5 6 7

8 9 10 11 12 13

SATA_DTX_IRX_N4 SATA_DTX_IRX_P4

+5VS

1 2

C788 0.01U_0402_16V7KC788 0.01U_0402_16V7K

1 2

C789 0.01U_0402_16V7KC789 0.01U_0402_16V7K

Near CONN side.

SATA_ITX_RPI_DRX_P4 SATA_ITX_RPI_DRX_N4

SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4

SATA_ITX_RPI_DRX_P4 21

SATA_ITX_RPI_DRX_N4 21

SATA_DTX_C_IRX_N4 21 SATA_DTX_C_IRX_P4 21

+5VS

Placea caps. near ODD CONN.

1

C513

C512

2

0.1U_0402_16V4Z

1

C514

2

1U_0603_10V4Z

1

C515

2

10U_0805_10V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HDD & CDROM

Montevina UMA LA6121P

1

0.2

24 46Thursday, April 15, 2010

0.2

5

3/30 Remove CL3 when use AR8132

+3VALW

SI3445ADV-T1-E3_TSOP6

D D

C C

1 2

RL1 0_1206_5%

@

S

4 5

QL1

G

3

2

CL8

0.1U_0402_16V4Z

1

+3VS

R314

R314 1K_0402_5%

1K_0402_5%

1 2

ISOLATE#

12

R3101

R3101 15K_0402_5%

15K_0402_5%

+3V_LAN

R397

R397 0_0402_5%

0_0402_5%

1 2

ENSWREG

R398

R398 0_0402_5%

0_0402_5%

@

1 2

+3V_LAN

RL18 0_0603_5%RL18 0_0603_5%

1 2

4.7U_0603_6.3V6K

D

6

2 1

Place Close to Pin 2

10K_0402_5%

1 2

RL6

+3VS

1 2

Add Lan_clkeq# pull high. 1204

+LAN_VDDREG

12

C630

1

CL3

2

10U_0805_10V4Z

GLAN_RXP22

GLAN_RXN22

R467

R467 10K_0402_5%

10K_0402_5%

LAN_CLKREQ#

1

CL10

0.1U_0402_16V4Z

2

60mil

1

CL4

CL4 10U_0805_10V4Z

10U_0805_10V4Z

2

LAN_POWER_OFF 31

ICH_PCIE_WAKE#22,26

+3V_LAN

1

CL1

CL2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

1U_0402_6.3V4Z

CL15 0.1U_0402_16V7KCL15 0.1U_0402_16V7K

1 2

CL14 0.1U_0402_16V7KCL14 0.1U_0402_16V7K

1 2

GLAN_TXP22 GLAN_TXN22

LAN_CLKREQ#17

PLT_RST#9,20,26

CLK_PCIE_LAN17 CLK_PCIE_LAN#17

+3V_LAN

R318 1K_0402_5%R318 1K_0402_5% R395 10K_0402_5%R395 10K_0402_5%

+3V_LAN

R396 1K_0402_5%R396 1K_0402_5%

RL15 2.49K_0402_1%

R561

1 2

0_0402_5%

+LAN_VDDREG

1 2

4

GLAN_RXP_C

GLAN_RXN_C

GLAN_TXP GLAN_TXN

LAN_CLKREQ#

PLT_RST#

CLK_PCIE_LAN CLK_PCIE_LAN#

LAN_XTALI

LAN_XTALO

ICH_PCIE_WAKE#_R

ISOLATE#

12 12 12

ENSWREG

60mil

U44

22

HSOP

23

HSON

17

HSIP

18

HSIN

16

CLKREQB

25

PERSTB

19

REFCLK_P

20

REFCLK_N

43

CKXTAL1

44

CKXTAL2

28

LANWAKEB

26

ISOLATEB

14

NC/SMBCLK

15

NC/SMBDATA

38

GPO/SMBALERT

33

ENSWREG

34

VDDREG

35

VDDREG

46

RSET

24

GND

49

PGND

RTL8111E-GR_QFN48_6X6

LED3/EEDO LED1/EESK

LED0

EECS/SCL

EEDI/SDA

MDIP0 MDIN0 MDIP1 MDIN1

NC/MDIP2

NC/MDIN2

NC/MDIP3

NC/MDIN3

DVDD10 DVDD10 DVDD10

DVDD33 DVDD33

AVDD33 AVDD33 AVDD33 AVDD33

EVDD10

AVDD10 AVDD10 AVDD10 AVDD10

REGOUT

3

31 37 40

R466 10K_0402_5%R466 10K_0402_5%

1 2

30

R394 10K_0402_5%R394 10K_0402_5%

1 2

32

MDI0+

1

MDI0-

2

MDI1+

4

MDI1-

5

MDI2+

7

MDI2-

8

MDI3+

10

MDI3-

11

13 29 41

27 39

12 42 47 48

21

3 6 9 45

+LAN_VDD10_L

36

MDI0+ 26 MDI0- 26 MDI1+ 26 MDI1- 26 MDI2+ 26 MDI2- 26 MDI3+ 26 MDI3- 26

+LAN_VDD10

+3V_LAN

+LAN_EVDD10

+LAN_VDD10

LL1

1 2

S INDUC_ 4.7UH +-20% SIA4012-4R7M

C502

22U_0805_6.3V6M

2

+3VALW +3VALW +3VALW

1

C1409

0.1U_0402_25V4K

2

+LAN_VDD10

1

2

1

C629

0.1U_0402_16V4Z

2

RL19 0_0603_5%RL19 0_0603_5%

1 2

1U_0402_6.3V4Z

1

C1410

0.1U_0402_25V4K

2

CL22

+LAN_EVDD10

1

2

1

2

1

CL43

0.1U_0402_16V4Z

2

C1411

0.1U_0402_25V4K

1

B B

LAN_XTALI

LAN_XTALO

Y3

1 2

25MHZ_20P

CL32

CL32 27P_0402_50V8J

27P_0402_50V8J

1

CL33

CL33 27P_0402_50V8J

27P_0402_50V8J

2

4

1

2

A A

5

+3V_LAN

1

CL30

2

0.1U_0402_16V4Z

Issued Date

1

CL31

2

0.1U_0402_16V4Z

3

CL29

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

CL21

2

0.1U_0402_16V4Z

2007/08/28 2006/07/26

+LAN_VDD10

1

CL23

CL24

2

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

1

CL25

2

0.1U_0402_16V4Z

1

CL26

2

0.1U_0402_16V4Z

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

WLAN, WWAN, New Card

Montevina UMA LA6121P

25 46Thursday, April 15, 2010

1

0.2

A

B

C

D

E

Need to confirm EC GPIO PIN 09/22

+3VL

+3VALW

+3VL

12

R149

1 1

2 2

C1124

C1125

C1122

C1123

1 2

0.01U_0402_16V7K

R149

10K_0402_5%

11223

SW5

SW5 1BS003-1211L_3P

1BS003-1211L_3P

left OFF right ON(09/05/26)

left OFF right ON(09/05/26)left OFF right ON(09/05/26)

Place close to TCT pin

2

12

@

R145

3

DAN217T146_SC59-3

D8

1

@

10K_0402_5%

KILL_SW# 31

KILL SWITCH

T89

1

TCT1

MDI3-25 MDI3+25

MDI2-25 MDI2+25

MDI1-25 MDI1+25

MDI0-25 MDI0+25

MDI3MDI3+

MDI2-

MDI1MDI1+

MDI0MDI0+

2 3 4 5 6 7 8

9 10 11 12

MCT1

TD1+

MX1+

TD1-

MX1-

TCT2

MCT2

TD2+

MX2+

TD2-

MX2-

TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

350uH_GSL5009LF

MCT3

C1126

C1127

C1128

C1129

1 2

24

MDO3-

23

MDO3+

22

MCT2

21

MDO2-

20

MDO2+MDI2+

19

MCT1

18

MDO1-

17

MDO1+

16

MCT0

15

MDO0-

14

MDO0+

13

R5 75_0402_5%R5 75_0402_5%

0.01U_0402_16V7K

R9 75_0402_5%R9 75_0402_5%

0.01U_0402_16V7K

R10 75_0402_5%R10 75_0402_5%

0.01U_0402_16V7K

R12 75_0402_5%R12 75_0402_5%

0.01U_0402_16V7K

12

0.1U_0402_16V4Z

4.7U_0805_10V4Z

PCIE_RXN322 PCIE_RXP322

+3VS_WLAN

1

C566

C567

2

BT_OFF#29,31

BT_OFF#_C29

ICH_PCIE_WAKE#22,25

WLAN_ACTIVE29

BT_ACTIVE29

CLKREQ#_617

CLK_PCIE_MCARD2#17 CLK_PCIE_MCARD217

CLK_DEBUG_PORT_117

RJ45_GND

BT_OFF#

BT_OFF#_C

ICH_PCIE_WAKE#

WLAN_ACTIVE BT_ACTIVE

CLKREQ#_6

PLT_RST#9,20,25

R423 0_0402_5%R423 0_0402_5%

1 2

R425 0_0402_5%R425 0_0402_5%

1 2

PCIE_TXN322

PCIE_TXP322

EC_TX31 EC_RX31

C665

1 2

1000P_1808_3KV7K

0.01U_0402_16V7K

1

2

10K_0402_5%@

R438

1 2

R439

1 2

0_0402_5%

R424 0_0402_5%@ R424 0_0402_5%@

1 2

R430 0_0402_5%@ R430 0_0402_5%@

1 2

CLK_PCIE_MCARD2# CLK_PCIE_MCARD2

PLT_RST#

PCIE_C_RXN3 PCIE_C_RXP3

PCIE_TXN3 PCIE_TXP3

+3VS_WLAN

EC_TX EC_RX

12

R1094

R1094 100K_0402_5%

100K_0402_5%

C569

0.1U_0402_16V4Z

BTOFF#

4.7U_0805_10V4Z

1

C570

2

+1.5VS_WLAN

1

C571

2

JP7

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

GND2

FOX_AS0B226-S40N-7F_52P

CONN@

Mini Card

---WLAN

R431 0_0805_5%R431 0_0805_5%

+1.5VS

+3VS +3VS_WLAN

02/13 Change WLAN and WWAN 0402 resistor to 0805, and WLAN change to +3VS power plane

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

+3VS_WLAN

+1.5VS_WLAN

R699 0_0402_5%R699 0_0402_5% R700 0_0402_5%R700 0_0402_5% R701 0_0402_5%R701 0_0402_5% R702 0_0402_5%R702 0_0402_5% R703 0_0402_5%R703 0_0402_5%

XMIT_OFF# PLT_RST#

R426 0_0805_5%R426 0_0805_5%

ICH_SMBCLK ICH_SMBDATA

1 2

R432 0_0805_5%R432 0_0805_5%

1 2

1 2 1 2 1 2 1 2 1 2

1 2

USB20_N5 22 USB20_P5 22

+1.5VS_WLAN

+3VS_WLAN

+1.5VS_WLAN

ICH_SMBCLK 17,22 ICH_SMBDATA 17,22

+1.5VS_WLAN

LPC_FRAME# 21,31 LPC_AD3 21,31 LPC_AD2 21,31 LPC_AD1 21,31 LPC_AD0 21,31

Change to IAT50 footprint, because of error layout symbol. 1202

Modify as B3B5. 11/11

3 3

LAN Conn.

JRJ45

MDO3-

MDO3+

MDO1-

MDO2-

MDO2+

MDO1+

MDO0-

MDO0+

4 4

A

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

TYCO_1734819_8P-T

CONN@

CL41

0.1U_0402_16V4Z

1

2

10

GND

9

GND

LANGND

1

CL42

4.7U_0805_10V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

04/29 MV-1 add clock REQ pull high

+3VS

R11

10K_0402_5%

CLKREQ#_6

D23

CH751H-40_SC76

1 2

WL_OFF#31

01/03 Prevent WLAN leakage

2007/08/28 2006/07/26

C

R433

@R433

@

10K_0402_5%

21

Compal Secret Data

Deciphered Date

12

2

G

R435

1 2

0_0402_5%

+3VALW

12

@

R434

R434 100K_0402_5%

100K_0402_5%

13

D

@

Q10

Q10 2N7002_SOT23-3

2N7002_SOT23-3

S

D

XMIT_OFF#

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

WLAN, WWAN, New Card

Montevina UMA LA6121P

26 46Thursday, April 15, 2010

E

0.2

5

4

3

2

1

SD,MMC,MS muti-function pin define

Realtek Recommend

MODE_SEL

12

1

R516

C609

@

47P_0402_50V8J

D D

+3VS_CR_VCC

0.1U_0402_16V4Z

C6151U_0603_10V4Z C6151U_0603_10V4Z

+VCC_OUT

USB20_N722 USB20_P722

R527

6.19K_0402_1%

C627

@

1U_0603_10V4Z

W=40mils

4

0.1U_0402_16V4Z

2

C616

1

+3V3_IN CARD_RST# MODE_SEL CARD_XTLO CARD_XTLI

USB20_N7 USB20_P7

12

AGND1

12

R530

R530 0_0402_5%

0_0402_5%

+VCC_OUT

Add C822 4.7u and reserve C808 10u for cost down Michael 2008/5/30

12

R533

0_0805_5%

+3VS_CR_VCC

U36

1 3 7

9 11 33

8 44 45 47 48

4

5 14

2

12 32

6 46

R532

1 2

0_0603_5%

4.7U_0805_10V4Z

1

C612

1U_0603_10V4Z

2

+3VS_CR_VCC

C C

B B

100K_0402_5%

Internal 200K pull up

1U_0603_10V4Z

CLK_SD_48M17

4/2 Add by Vivian

A A

1

C613

2

0.1U_0402_16V4Z

R518 0_0603_5%R518 0_0603_5%

1 2

@

C619

12

1 2

R520 0_0603_5%

4.7U_0805_10V4Z

R524

1 2

0_0603_5%

12

R525

499K_0402_1%

@

R528

1 2

0_0402_5%

C878

12

5

+3VALW

+3VS_CR_VCC

R521

100P_0402_50V8J @

1

C614

0.1U_0402_16V4Z

2

C617

CARD_RST#

CLK_SD_48M

C618

1

0.1U_0402_16V4Z

2

@

Y8

CARD_XTLI

1

2

Y8

1 2

12MHZ_18PF_X5H012000FI1H

R531

@

270K_0402_5%

C621

@

6P_0402_50V8J

+3VS

AV_PLL

CARD_XTLO

C622

6P_0402_50V8J

W=40mils

2

1

@

2

1

2

@

AV_PLL NC NC CARD_3V3 D3V3 D3V3

3V3_IN RST# MODE_SEL XTLO XTLI

DM DP GPIO0

RREF

DGND DGND

AGND AGND

S IC RTS5159-GR LQFP 48P CARD READER

C623

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R516

0_0402_5%

2

10

VREG

22

MS_D4

30

NC

EEDI

XTAL_CTR

MS_D5

EEDO

EECS EESK

SD_CMD

43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18

13 24

15 16 17 36

XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10

SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6

XD_RDY_SP14

MS_INS#_SP9

XD_D5_SP5

XD_D4/SD_DAT1_SP4

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

2/17 Change Part number of U25 from SA00001NK10 to SA00002YP00

+VCC_3IN1

40mil

1

C624

@

2

10U_0805_10V4Z

C625

2

EMI

0.1U_0402_16V4Z

Change to KIUN0 CONN, need double confirm pin define.10/23 prince

2009/02/04 2010/02/04

3

MS_CLK SD_CLK

12

R515

@

C610

@

1

@

2

10_0402_5%

10P_0402_50V8J

AV_PLL 20mil (+1.8V internal regulator)

AV_PLL

SDDAT2_XDRE# SDDAT3_XDWE#

SDCLK_MSCLK SDDAT6_MSD3 MS_INS# SDDAT7_MSD2 SDDAT0_MSD0 SP6 MS_BS XDD4_SDDAT1 SD_CD# SD_WP

CARD_EEDI

R526 0_0402_5%R526 0_0402_5%

1 2

CARD_EEDO CARD_EECS CARD_EESK SD_CMD

SD_CLK MS_CLK

12

@

R529

100K_0402_5%

1

@

C626

2

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

R522 0_0402_5%R522 0_0402_5%

1 2

R523 0_0402_5%R523 0_0402_5%

1 2

12

@

R534

100K_0402_5%

1

@

C628

2

0.1U_0402_16V4Z

10_0402_5%

10P_0402_50V8J

+3VS_CR_VCC

12

R517

1

C611

2

SD_CLK

MS_CLK

0.1U_0402_16V4Z

SD_WP XDD4_SDDAT1 SDDAT0_MSD0

MS_BS SD_CLK SP6 SDDAT0_MSD0

SDDAT7_MSD2

MS_INS# SDDAT6_MSD3 SD_CMD MS_CLK

SDDAT3_XDWE#

SDDAT2_XDRE# SD_CD#

2

@

+3VS_CR_VCC

C620

@

MDIO PIN Name SP1

SP2

SP3

SP4

SP5

SP6

SP7

SP8

SP9

SP10

SP12

SP13

SP14

SP15

SP16

SP17

SP18

SP19

U24

8

VCC

7

1

2

NC

6

NC

5

GND

AT93C46-10SI-2.7_SO8

@

+VCC_3IN1

Title

Size Document Number Rev

Custom

Date: Sheet of

SD Card PIN Name

MMC Card PIN Name

SDWP#

SDCD#

SDCDAT1

SDCDAT0

SDCDAT7

SDCDAT6

SDCCLKSP11

SDCDAT5

SDCDAT4

SDCDAT3

SDCDAT2

CARD_EECS

1

CS

CARD_EESK

2

SK

CARD_EEDO

3

DI

CARD_EEDI

4

DO

3 in 1 Card Reader

250mA

JREAD1

1

SD-WP

2

SD-DAT1

3

SD-DAT0

4

SD-GND

5

MS-GND

6

MS-BS

7

SD-CLK

8

MS-DAT1

9

MS-DAT0

10

SD-VCC

11

MS-DAT2

12

SD-GND

13

MS-INS

14

MS-DAT3

15

SD-CMD

16

MS-SCLK

17

MS-VCC

18

SD-DAT3

19

MS-GND

20

SD-DAT2

21

SD-CD

TAITW_R009-025-LR_NR

CONN@

Compal Electronics, Inc.

RTS5159 Cardreader

Montevina UMA LA6121P

1

MS Card PIN Name

MSWR

MSBS

MSCDAT1

MSCDAT0

MSCDAT2

MS_INS#

MSCDAT3

MSCCLK

MSCDAT6

MSCDAT7

GND1 GND2

27 46Thursday, April 15, 2010

22 23

0.2

5

U39

VIN3VOUT

@

R1422

1

2

1 2

20K_0402_1%

20K_0402_1% R892

R892

1 2

R013

1 2

5.1K_0402_1%

1 2

10K_0402_5%

0.1U_0402_16V7K

1

C1440

2

10U_0805_10V4Z

C025

2.2U_0603_10V6K

2.2U_0603_10V6K C024

C024

2.2U_0603_10V6K

1

C1775

C1774

D D

+VDDA

FBM-L11-160808-800LMT_0603

C C

MIC_L

R252 1K_0402_5%R252 1K_0402_5%

MIC_R

R253 1K_0402_5%R253 1K_0402_5%

HDA_RST#_CODEC21

HDA_SYNC_CODEC21

HDA_SDOUT_CODEC21

B B

@

2

4.7U_0805_10V4Z

L108

1 2

C1450

1 2

MONO_IN

DMIC_DAT19

MIC_JD29 HP_JD29

R1441 0_0603_5%R1441 0_0603_5%

1 2

R1105 0_0603_5%R1105 0_0603_5%

1 2

R1106 0_0603_5%R1106 0_0603_5%

1 2

R117 0_0603_5%R117 0_0603_5%

1 2

R118 0_0603_5%R118 0_0603_5%

1 2

GNDAGND

EC Beep

EC_BEEP31

R1431

1 2

47K_0402_5%

A A

47K_0402_5%

C1412

1 2

1U_0402_6.3V6K

ICH Beep

C1416

SB_SPKR22

R1432

1 2

47K_0402_5%

1 2

1U_0402_6.3V6K

5

1

EN

2

GND

RT9198-4GPBG_SOT23-5

@

40mil

1

C1470

2

0.1U_0402_16V7K

MIC_LEFT

MIC_RIGHT

SENSE_A

SENSE_B

EAPD

Modify as NAT10

+VDDA

R1429

R1429 10K_0402_5%

10K_0402_5%

1 2

R1183

1 2

560_0402_5%

R1188

1 2

560_0402_5%

10K_0402_5%

NC

+AVDD_HD

0.1U_0402_16V7K

U38

AVDD125AVDD2

14

LINE2_L

15

LINE2_R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

LINE1_VREFO

20

LINE2_VREFO

19

MIC2_VREFO

21

MIC1_L

22

MIC1_R

12

PCBEEP_IN

11

RESET#

10

SYNC

5

SDATA_OUT

2

GPIO0/DMIC_DATA1/2

3

GPIO1/DMIC_DATA3/4

13

SENSE A

34

SENSE B

47

EAPD

48

SPDIFO1

4

DVSS1

7

DVSS2

R1433

4

5

38

ALC272-GR_LQFP48_7X7

2

B

1 2

C1776

@

LOUT1_L

LOUT_R

LOUT2_L

LOUT2_R

SPDIFO2

DMIC_CLK1/2

DMIC_CLK3/4

SDATA_IN

MONO_OUT

MIC1_VREFO

HPOUT_R

HPOUT_L

R1430

R1430 10K_0402_5%

10K_0402_5%

1 2

1

C

Q21

E

2SC2411K_SC59

3

D21

D21 RB751V_SOD323

RB751V_SOD323

2 1

1

2

1

BITCLK

VREF

JDREF

CPVEE

AVSS1 AVSS2

1U_0402_6.3V6K

+DVDD_IO

DVDD

NC

CBN

CBP

C1788

1 2

1U_0402_6.3V6K

4

+VDDA+5VS

1

C1777

@

2

4.7U_0805_10V4Z

9

0.1U_0402_16V7K

+3VS_HD_DVDD

1

C3199

2

0.1U_0402_16V7K

DVDD_IO

LINEL

35

LINER LINE_OUTR

36

39

41

45

46

43

44

6

SDIN_CODEC

8

C1042

30

2.2U_0603_10V6K

29

37

28

10mil

HP_RIGHT

32

HP_LEFT

33

27

R893 20K_0402_1%R893 20K_0402_1%

40

1 2

31

26 42

C1789

MONO_IN

1 2

R1376

2.4K_0402_5%

4

+DVDD_IO

20mil

1

C1398

C1397

2

0.1U_0402_16V7K

C1784 1000P_0402_50V7K@C1784 1000P_0402_50V7K@

R1427 0_0402_5%R1427 0_0402_5%

@

R410

1 2

10_0402_5%

C023 10P_0402_50V8J

HDA_BITCLK_CODEC

R08

1 2

33_0402_5%

12

+MIC1_VREFO

2

C1414

1

2.2U_0603_10V6K

R1428 0_0402_5%R1428 0_0402_5%

1 2

@C1787

@

R020

1 2

0_0805_5%

1 2

R1290 0_0603_5%R1290 0_0603_5%

1 2

R1300 0_0603_5%@R1300 0_0603_5%@

R1280

1 2

0_0603_5%

1

2

0.1U_0402_16V7K

1 2

1000P_0402_50V7K

1 2

C1785

@C1785

@

C1786

@C1786

@

1000P_0402_50V7K

1 2

R1360 75_0603_1%R1360 75_0603_1%

1 2

R1361 75_0603_1%R1361 75_0603_1%

1 2

1000P_0402_50V7K

1 2

C1787

1

C66

2

10U_0805_10V6K

DMIC_CLK 19

HDA_BITCLK_CODEC 21

HDA_SDIN0 21

2

1

+3VS_HD_DVDD

+3VS

LINE_OUTL

C1413

C1413 1U_0402_6.3V6K

1U_0402_6.3V6K

4.7K_0402_5%

+5VS+VDDA

+1.5VS

HP_R

HP_L

EC_MUTE#31

3

HP_R 29

HP_L 29

LINE_OUTR

LINE_OUTL

EC_MUTE#

Low-->mute

BYPASS

2

C506

0.22U_0603_10V7K

1

C504

1 2

0.22U_0603_10V7K

C503

1 2

0.1U_0603_50V4Z

C505

1 2

0.1U_0603_50V4Z

R2405

100K_0402_5%

D15

21

CH751H-40PT_SOD323-2

SPKR+

R1281

SPKL+

R1282 0_0603_5%R1282 0_0603_5%

LINE_C_OUTR

LINE_C_OUTL

+3VS

12

Low-->mute

0_0603_5%

1 2 1 2

R429

1 2

4.99K_0603_1%

R428

1 2

10K_0603_1%

R427

1 2

10K_0603_1%

EAPD

need double confirm Pin1 define.

SPKR_R SPKL_R

LINE_OUT#

1 2

D18

@

2

MUTE# BYPASS

LINE_OUT

MUTE#

R251

R251 1K_0402_5%

1K_0402_5%

2

1

PJDLC05_SOT23-3

3

Change to Digital GND from Jeson&Bill's sugestion. 1201

+MIC1_VREFO

12

R1349

MIC_R

Issued Date

R1349

4.7K_0402_5%

MIC_L

3

R1348

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+MIC1_VREFO

@

1

C304

220P_0402_25V8J

2009/02/04 2010/02/04

MIC_R 29

MIC_L 29

2

Compal Secret Data

Deciphered Date

2

R436

1 2

15K_0603_1%

R437

LINE_OUT SPKR+

U40

1

SD#

2

BYPASS

3

INP

4

INN

APA0715QBI-TRG_TDFN8_3X3

@

C1492

R437

1 2

15K_0603_1%

9

GND2

8

OUTN

7

GND1

6

VDD

5

OUTP

1

@

2

C1493

47P_0402_50V8J

Title

Size Document Number Rev

Custom

Date: Sheet of

1

SPKL+LINE_OUT#

+5VAMP +5VS

SPKL+

SPKR+

JP13

1

2

3

GND

4

GND

ACES_88231-02001

CONN@

Compal Electronics, Inc.

0.1U_0402_16V4Z

1

C1496

C1495

10U_0805_10V4Z

HD Audio ALC272

2

1

2

28 46Thursday, April 15, 2010

R1958

R1958 0_1206_5%

0_1206_5%

1 2

0.2

5

U13

80 mils

USB_EN#

1

C275

0.1U_0402_16V

D D

C C

2

USB20_P222

USB20_N222

USB20_P2

USB20_N2

+5VALW

USB_P2

4

3

PRTR5V0U2X_SOT143-4@

U13

1

GND

2

IN

3

IN

4

EN#

RT9711PS SO 8P

1 2

R125 0_0402_5%R125 0_0402_5%

1 2

R144 0_0402_5%R144 0_0402_5%

4

1

D46

VIN

GND

IO2

3

2

L7 WCM2012F2S-900T04_0805@ L7 WCM2012F2S-900T04_0805@

USB_N2

2

IO1

1

OUT OUT OUT OC#

8 7 6 5

USB_P2 USB_N2

modify on 09/17 and need to confirm with ME

+USB_AS+5VALW

4

0.1U_0402_16V

1

+

C444

150U_B2_6.3VM_R45M

2

+USB_AS

C274

USB_EN#

USB_OC#2 22

W=60mils

12

R156

R156 470_0603_5%

470_0603_5%

13

D

2

G

12

R159

R159 100K_0402_5%

100K_0402_5%

@

JUSB1

1

GND

2

USB_P

3

USB_N

4

VCC

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S52KZL

CONN@

S

3

Q20

Q20 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

9

GND

10

GND

ACES_87213-0800G

CONN@

BT Connector

+3VAUX_BT

JP61

1

2

USB20_P6_R

3

USB20_N6_R

4

5

6

7

8

R1088 0_0402_5%R1088 0_0402_5% R1089 0_0402_5%R1089 0_0402_5%

12 12

2

USB20_P6 22 USB20_N6 22 BT_ACTIVE 26

WLAN_ACTIVE 26

1

+5VALW

D47

0.1U_0402_16V4Z

1

C1387

2

4

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

+3VAUX_BT

1

C1388

2

4.7U_0805_10V4Z

Title

Size Document Number Rev

Date: Sheet of

1

0612 no install

1

+

C273

@+C273

@

150U_B2_6.3V-M~D

B B

A A

2

5

C64

470P_0402_50V7K~D

2

USB/B to M/B Conn.

JP8

MIC_R28 MIC_L28 MIC_JD28

HP_L28 HP_R28 HP_JD28

USB20_N122

USB20_P122

USB20_N022

USB_OC#022

USB_EN#31

USB20_P022

USB_OC#0

USB_EN#

+5VALW

MIC_R MIC_L MIC_JD

HP_L HP_R HP_JD

USB20_N1 USB20_P1

USB20_N0 USB20_P0

4

JP8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

GND1

24

GND2

ACES_87213-2200G

CONN@

+3VS

R602

10K_0402_5%

3

10K_0402_5%

1 2

Q14

2N7002_SOT23-3

BT_OFF#

2007/08/28 2006/07/26

R603

10K_0402_5%

BT_OFF#26,31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

R235

1 2

0_0603_5%

+3VS

1

C1386

@C1386

@

1U_0603_10V4Z

2

1 2

BT_OFF

13

D

2

G

S

R1092 10K_0402_5%R1092 10K_0402_5%

BT_OFF

Compal Secret Data

12

1 2

2N7002_SOT23-3

R155

1 2

0_0402_5%

Deciphered Date

AO3413_SOT23-3

S

R1090

R1090 100K_0402_5%

100K_0402_5%

R604

10K_0402_5%

Q15

2

G

Q105

G

2

+3VS

2

D

13

0.01U_0402_16V7K

C1390

1 2

13

D

S

+5VALW

USB20_N6_R

1

2

0.1U_0402_16V4Z

BT_OFF#_C

USB20_P6_R

2

IO1

1

C1389

BT_OFF#_C 26

Compal Electronics, Inc.

USB, BT, eSATA

Montevina UMA LA6121P

0.2

29 46Thursday, April 15, 2010

1

0.2

5

4

3

2

1

D D

0.1U_0402_16V4Z

FSEL#31

SPI_CLK31

C307

12

C307

12

22P_0402_50V8J

C308

12

22P_0402_50V8J

C309

12

22P_0402_50V8J

R230

SPI_FSEL#

33_0402_5%

R231

SPI_CLK_R

33_0402_5%

R232

C C

SPI_FWR#

12/27EMI request

33_0402_5%

+3VL

20mils

1

C712

2

1 2

R553 10_0402_5%R553 10_0402_5%

1 2

R554 10_0402_5%R554 10_0402_5%

1 2

R556 10_0402_5%R556 10_0402_5%

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH WIESO_G6179-100000_8P

SPI_FSEL#

SPI_CLK_R

SPI ROM

U27

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

D

W25Q16BVSSIG_SO8

4

SPI_SOSPI_FWR#

2

Q

1 2

R555 0_0402_5%R555 0_0402_5%

FRD#

FRD# 31FWR#31

Remove LPC Debug Port

20090618

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

BIOS ROM

Montevina UMA LA6121P

1

0.2

30 46Thursday, April 15, 2010

0.2

+3VL_EC

0.1U_0402_16V4Z

1

C715

2

0.1U_0402_16V4Z

SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2

1

C716

2

1000P_0402_50V7K

R573 2.2K_0402_5%R573 2.2K_0402_5% R577 2.2K_0402_5%R577 2.2K_0402_5% R574 2.2K_0402_5%R574 2.2K_0402_5% R575 2.2K_0402_5%R575 2.2K_0402_5%

03/28 PV2 Change SM bus power to +3VL

CLK_PCI_EC17

1 2

+3VL

R578 47K_0402_5%R578 47K_0402_5%

C721 0.1U_0402_16V4ZC721 0.1U_0402_16V4Z

SYSON

2

C1415

C1415 1U_0402_6.3V6K

1U_0402_6.3V6K

1

11/07 Add SYSON and SUSP# PD

SUSP#

12

R581

8.2K_0402_5%

PCI_PME#20

Delete cap sensor function 09/22

EC_PME# PCI_RST#

1

C324

0.1U_0402_16V4Z

2

03/13 PV2 Add EMI solution

1

C325

0.1U_0402_16V4Z

2

EC_TX

@R233

@

EC DEBUG port

R233

ICH_SUSCLK22

0.1U_0402_16V4Z

C717

1 2 1 2 1 2 1 2

12

1

2

PCI_RST#

R713

R713 100K_0402_5%

100K_0402_5%

0_0805_5%

1000P_0402_50V7K

1

C719

C718

2

04/22 MV1 Change SMbus1 power to +3VL

+3VL +3VS

R576

@R576

C722

@C722

@

1 2

15P_0402_50V8J

@

1 2

33_0402_5%

EC_SCI#22

12

J1

11/09 Delete CLKRUN#

JOPENJ1JOPEN

11/17 Change to +3VALW

11/09 Add HDA_RST# to EC

Del HDA_RST#_EC to EC 9/29 Prince

+3VL

11/15 Delete PCI_PME#

R589

@R589

@

1 2

+3VL +3VL

12

R1100

4.7K_0402_5%

+3VL

ON/OFFBTN32

ON/OFFBTN

32.768KHZ_12.5P_1TJS125DJ2A073

R605

@R605

@

1 2

0_0402_5%

R584 47K_0402_5%R584 47K_0402_5% R599 47K_0402_5%R599 47K_0402_5%

+3VL

@R585

@

10K_0402_5%

1 2

0_0402_5%

R1099

4.7K_0402_5%

1 2

INV_PWM19

R593

1 2

4.7K_0402_5%

C723

C723 15P_0402_50V8J

15P_0402_50V8J

1 2

Y5

3

NC

2

NC

1 2

C725

C725 15P_0402_50V8J

15P_0402_50V8J

ICH_SUSCLK_RICH_SUSCLK

R585

EC_PME#

OUT

IN

GATEA2021 KB_RST#21 SIRQ22

LPC_FRAME#21,26

LPC_AD321,26 LPC_AD221,26 LPC_AD121,26 LPC_AD021,26

PCI_RST#20

+3VS

1 2 1 2

SMB_EC_CK134

SMB_EC_DA134

SMB_EC_CK26 SMB_EC_DA26

SLP_S3#22 SLP_S5#22 EC_SMI#22

NUM_LED#32

4

1

@R592

@

1 2

0_0402_5%

+3VL +3VL_EC

R572

1 2

0_0805_5%

9

22

U30

GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_EC

PCI_RST# ECRST#

10K_0402_5%

12

R590

@ R590

@

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2

SLP_S3# SLP_S5#

T95T95

T96T96

12

@

R595

R595 20M_0402_5%

20M_0402_5%

EC_SMI#

ESB_CLK_R ESB_DAT_R

ON/OFFBTN

NUM_LED#

CRY2

CRY1

T85T85

T86T86

FAN_SPEED16

EC_TX26 EC_RX26

R592

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

+3VL_EC

+EC_AVCC

33

VCC

PWM Output

DA Output

PS2 Interface

Int. K/B

Int. K/B Matrix

Matrix

SPI Device Interface

SM Bus

GPIO

GND

11

24

12

L30

L30 0_0603_5%

0_0603_5%

1 2

C726 0.1U_0402_16V4ZC726 0.1U_0402_16V4Z

EC pin16/19/25/31/21/23/26/76/68/70/85/98/109/106/107/108/118. EC demand to change for common design. 1204

EC Pin26/28 design follow Danny's suggestion.2010/1/5

EC Pin99/106 design follow Danny's suggestion.2010/1/11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_AVCC

67

96

111

125

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SPI Flash ROM

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

GPO

GPI

GND

AGND

KB926QFE0_LQFP128_14X14

35

69

94

113

ECAGND

EC_SEL

High

Low

21

EC_BEEP

23

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

SELIO2#/AD5/GPIO43

IREF/DA2/GPIO3E

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C

PSDAT2/GPIO4D

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

CAPS_LED#/GPIO53

SUSP_LED#/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

L31

1 2

C791 100P_0402_50V8JC791 100P_0402_50V8J

26

ACOFF

27

63 64

ADP_I

65 66

AD3/GPIO3B

75

AD4/GPIO42

DA3/GPIO3F

SPIDI/RD#

SPIDO/WR#

SPICS#

GPXO10 GPXO11

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

0_0603_5%

AC_IN ACIN

2007/08/28 2006/07/26

NMI_DBG#

76

68

EN_DFAN1

70

IREF

71

CHGVADJ

72

PWR delete 2nd batt.1204

EC_MUTE#

83

USB_EN#

84 85

WL_BT_LED#

86

TP_CLK

87

TP_DATA

88

DEL AC_LED# 9/29 Prince

97 98 99

LID_SW#

109

119 120 126 128

73 74

FSTCHG

89

BATT_CHG_LED#

90

CAPS_LED#

91

BATT_LOW_LED#

92

ON/OFFBTN_LED#

93 95

VR_ON

121

AC_IN

127

EC_RSMRST#

100

R588

101

EC_ON

102 103

PM_PWROK_R

104 105 106

R_M_PWROK

107 108

SLP_S4#

110

ENBKL

112 114

THERM_SCI#

115

SUSP#

116

PWRBTN_OUT#

117

EC_PME#

118

124

1

2

For C Revision

+3VL

12

R715

R715 150K_0402_5%

150K_0402_5%

EC_VERSION

KB926D3

KB926E0

T90T90

BATT_TEMP

T87T87

T92T92 T93T93

Change CHGVADJ from Pin68 to 72, follow EC's suggestion.01/20

T91T91

IREF 36

R591 0_0603_5%@ R591 0_0603_5%@

1 2

LAN_POWER_OFF

BT_OFF#

R227 33_0402_5%R227 33_0402_5% R228 47_0402_5%R228 47_0402_5% R229 33_0402_5%R229 33_0402_5%

1 2

EC_SEL

C724

4.7U_0603_6.3V6K

2 1

Compal Secret Data

WL_BT_LED# 32

T84T84

LID_SW# 32

1 2 1 2 1 2

VR_ON 41

R586 10K_0402_5%R586 10K_0402_5%

0_0402_5%

WL_OFF# 26

D13

CH751H-40PT_SOD323-2

EC_RSMRST# 22

1 2

R597 0_0402_5%R597 0_0402_5%

SLP_S4# 22,33

SUSP# 33,38

PWRBTN_OUT# 22

NMI_DBG# PCI_SERR#

04/29 MV1 Change to 150K

Deciphered Date

+3VL

Follow EC's request.01/18

12

R1091

@ R1091

@

100K_0402_5%

EC_SEL

12

R1093

R1093 100K_0402_5%

100K_0402_5%

EC_BEEP 28

KILL_SW# 26

ACOFF 35,36

ADP_I 36

EN_DFAN1 6

CHGVADJ 36

EC_MUTE# 28 USB_EN# 29

C720

1 2

BATT_TEMP 34

TSATN# 9

0.01U_0402_16V7K

ECAGND

PWR delete BATT_OVP. 11/03

Follow Danny's suggestion.01/14

R579 4.7K_0402_5%R579 4.7K_0402_5%

1 2

R580 4.7K_0402_5%R580 4.7K_0402_5%

1 2

TP_CLK 32 TP_DATA 32

02/13 Correct AC_LED control by EC

LAN_POWER_OFF 25

BT_OFF# 26,29

change STD_ADP to BATT_CHG_LED#. 10/25

T94T94 T97T97

FSTCHG 36 BATT_CHG_LED# 32 CAPS_LED# 32 BATT_LOW_LED# 32 ON/OFFBTN_LED# 32

12

EC_LID_OUT# 22 EC_ON 34

M_PWROK

R598

1 2

0_0402_5%@

ENBKL 11

11/07 Add SLP_S4# to South bridge

THERM_SCI# 22

+3VL

12

R714

10K_0402_5%

11/09 don't stuff when use C0

FRD# FWR# SPI_CLK FSEL#

R1131

D14

CH751H-40PT_SOD323-2

FRD# 30 FWR# 30 SPI_CLK 30 FSEL# 30

11/09 PU +5VL move to M/B

10K_0402_5%

1 2

R1132

R1133

100K_0402_5%

R254

100_0402_5%

1 2 1 2

0_0402_5%

M_PWROK 9,22

PM_PWROK

21

1

12

C1408

2

4.7U_0603_6.3V6K

PM_PWROK

BKOFF# 19

PV PWROK sequence issue

Current limit

PCI_SERR# 20

11/07 Correct direction pretect leakage

ACIN 36

Vendor Recommend

Title

Size Document Number Rev

Date: Sheet of

KSO15

C792 100P_0402_50V8J@C792 100P_0402_50V8J@

KSO10

C793 100P_0402_50V8J@C793 100P_0402_50V8J@

KSO11

C794 100P_0402_50V8J@C794 100P_0402_50V8J@

KSO14

C795 100P_0402_50V8J@C795 100P_0402_50V8J@

KSO13

C796 100P_0402_50V8J@C796 100P_0402_50V8J@

KSO12

C797 100P_0402_50V8J@C797 100P_0402_50V8J@

KSO3

C798 100P_0402_50V8J@C798 100P_0402_50V8J@

KSO6

C799 100P_0402_50V8J@C799 100P_0402_50V8J@

KSO8

C800 100P_0402_50V8J@C800 100P_0402_50V8J@

KSO7

C801 100P_0402_50V8J@C801 100P_0402_50V8J@

KSO4

C802 100P_0402_50V8J@C802 100P_0402_50V8J@

KSO2

C803 100P_0402_50V8J@C803 100P_0402_50V8J@

+5VS

SPI_CLK

SYSON9,33,39

PM_PWROK 9,22

KSI0

C804 100P_0402_50V8J@C804 100P_0402_50V8J@

KSO1

C805 100P_0402_50V8J@C805 100P_0402_50V8J@

KSO5

C806 100P_0402_50V8J@C806 100P_0402_50V8J@

KSI3

C807 100P_0402_50V8J@C807 100P_0402_50V8J@

KSI2

C808 100P_0402_50V8J@C808 100P_0402_50V8J@

KSO0

C809 100P_0402_50V8J@C809 100P_0402_50V8J@

KSI5

C810 100P_0402_50V8J@C810 100P_0402_50V8J@

KSI4

C811 100P_0402_50V8J@C811 100P_0402_50V8J@

KSO9

C812 100P_0402_50V8J@C812 100P_0402_50V8J@

KSI6

C813 100P_0402_50V8J@C813 100P_0402_50V8J@

KSI7

C814 100P_0402_50V8J@C814 100P_0402_50V8J@

KSI1

C815 100P_0402_50V8J@C815 100P_0402_50V8J@

2

C818

C818 22P_0402_50V8J

22P_0402_50V8J

1

INT_KB_Conn.

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

ACES_88514-2601 CONN@

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

27 28

ME ask to make a U-turn.(05/27)

Compal Electronics, Inc.

EC KB926/KB Conn.

Montevina UMA LA6121P

For EMI

1 2

JP19

1

2

3

4

5

6

7

8

9

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

GND1 GND2

SWAP follow Braxton

31 46Thursday, April 15, 2010

0.2

A

B

C

D

E

Need to confirm LED courlor

System LED

LED2

Blue

21

B

43

A

Amber

+5VS

Modify as NBLB2.

BLUE

BATT_CHG_LED#

BATT_LOW_LED#

D53

90.9_0402_1%

21

HT-191NB_BLUE_0603

HT-297UD/CB _BLUE/AMB_0603

R1098

12

BATT_CHG_LED#31

1 1

BATT_LOW_LED#31

SATA_LED#21

R120

100_0402_5%

R146

120_0402_5%

HDD LED

12

+5VALW

R971

R971 0_0603_5%

0_0603_5%

1 2

R970 0_0603_5%

Battery Charge LED

+3VS

R972

0_0603_5%

@

1 2

@

+5VS

1 2

R973

R973 0_0603_5%

0_0603_5%

+3VALW

ON/OFFBTN_LED#

LED1

Blue

90.9_0402_1%

21

HT-191NB_BLUE_0603

R1101

12

+5VALW

System Power LED

BT/WLAN LED

R151

LED3

21

Amber

JP60

1

2

3

4

5

6

7

8

9

GND

10

GND

CONN@

5

6

SMT1-05_4P

SW8

4

3

WL_BT_LED#

ON/OFFBTN_LED#

ON/OFFBTN

+5VS

CAPS_LED# NUM_LED#

HT-191UD_Amber_0603

+5VALW

ACES_85201-08051

WL_BT_LED#31

2 2

ON/OFFBTN_LED#31

ON/OFFBTN31

CAPS_LED#31 NUM_LED#31

ON/OFFBTN

3 3

2

1

R151

12

150_0402_5%

Modify as new ID.2009/12/28.

ON/OFFBTN_LED#

ON/OFFBTN

2

3

D31

PSOT24C_SOT23

1

Modify as NBLB2, need double confirm CONN pin define. 10/24 Prince

To TP/B Conn.

JP23

8

GND

7

GND

6

5

4

3

2

1

ACES_85201-0605N

CONN@

+5VS

C701

0.1U_0402_16V4Z

TP_CLK

TP_DATA

SWL#

SWR#

C880

1 2

C881

1 2

C882

1 2

C879

1 2

TP Pin1

TP Pin6

100P_0402_50V8J@

SWR#

SWL#

2

3

D29

@

PSOT24C_SOT23

1

Update Footprint

SWL#

Left Switch

2

1

SMT1-05_4P

2

1

5

6

+5VS

TP_CLK31 TP_DATA31

TP_DATA

TP_CLK

3

D30

@

PSOT24C_SOT23

SW7

4

3

TP_CLK TP_DATA SWL# SWR#

4/2 Add by Vivian

SW6

5

SWR#

Right Switch

2

1

SMT1-05_4P

6

4

3

SWL#

10K_0402_5%

10K_0402_5% R600

R600

SWR#

10K_0402_5%

10K_0402_5% R601

R601

+5VS

12

LID switch Modify as KCL00

+3VL

A3212ELHLT-T SOT23W

4 4

A3212ELHLT-T SOT23W

1

C4

0.1U_0402_16V4Z

2

U7

VCC

2 3

1

OUT

LID_SW#

GND

A

LID_SW# 31

+3VL

12

B

R2406

R2406 100K_0402_5%

100K_0402_5%

LID_SW#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

KBD, ON/OFF, SW, CIR

Montevina UMA LA6121P

32 46Thursday, April 15, 2010

E

0.2

5

4

3

2

1

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

B+

Q34A

C760

1

2

61

2

D D

12

R223

330K_0402_5%

SUSP

2N7002DW-7-F_SOT363-6

U32

8

D

7

D

6

D

5

D

AO4466_SO8

10U_0805_10V4Z

RUNON

12

1

2

+1.5V to +1.5VS Transfer

B+

2

G

1

C766

10U_0805_10V4Z

2

RUNON_1.5VS

13

D

Q44

S

2N7002_SOT23-3

C C

12

R647

330K_0402_5%

SUSP

U34

8

D

7

D

6

D

5

D

AO4466_SO8

12

R1113

R1113 1K_0402_5%

1K_0402_5%

1

C1406

0.1U_0402_25V4K

2

+5VS+5VALW +3VS+3VALWB+

1

S

2

S

3

S

4

G

C761

R224

470_0402_5%

C65

4700P_0402_25V7K

1

S

2

S

3

S

4

G

1

2

+1.5VS+1.5V

1

C762

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

01/03 Sparate+5VS and +3VS power timing

C1404

0.1U_0402_16V4Z

2

1

U33

RUNON_3VS

8

S

D

7

S

D

6

S

D

5

G

D

AO4466_SO8

12

R638

470_0402_5%

1

C765

0.01U_0402_16V7K

2

U47

1

IN

OUT

2

GND

3

SHDN

BYP

G916-390T1UF_SOT23-5

12

R636

330K_0402_5%

SUSP

2N7002DW-7-F_SOT363-6

C1405

10U_0805_10V4Z

SLP_S4#22,31

5

Q34B

R1115

@ R1115

@

10K_0402_5%

1 2

R1116

R1116 0_0402_5%

0_0402_5%

1

C759

10U_0805_10V4Z

2

3

4

1 2

1 2 3 4

1

2

0.1U_0402_16V4Z

5

4

10U_0805_10V4Z

1

C764

C763

2

12

R1114

47K_0402_1%

12

R1117

100K_0402_1%

+1.8V+3VALW

1

2

C1407

10U_0805_10V4Z

VOUT=1.25(1+R912/R913)

VOUT=1.25(1+100k/215k)=1.83V

DEL DIM LED 9/30 Prince

DIM LED

+3VL

12

R639

100K_0402_5%

SYSON#40 SUSP 40

SYSON9,31,39

SYSON#

Q13A

2

12

R640

100K_0402_5%

SUSP

61

3

Q13B

SUSP#

5

4

2N7002DW-7-F_SOT363-6

SUSP# 31,38

H1

Discharge circuit

R643

470_0402_5%

Q12A

2

+1.5V

Q12B

12

R646

470_0402_5%

3

5

4

2N7002DW-7-F_SOT363-6

Be used for Stand off. 11/06

12

61

2N7002DW-7-F_SOT363-6

+VCCP +0.75VS

12

R645

470_0402_5%

3

Q9B

5

4

2N7002DW-7-F_SOT363-6

470_0402_5%

Q9A

SUSP

2

R644

+1.5VS

12

61

2N7002DW-7-F_SOT363-6

B B

+5VS +3VS

12

R641

470_0402_5%

61

Q6A

SUSP SYSON#SUSP

2

SUSP SUSP

2N7002DW-7-F_SOT363-6

R642

470_0402_5%

Q6B

5

12

3

4

2N7002DW-7-F_SOT363-6

H_4P0H1H_4P0

1

FM1FM1

1

H2

1

H_3P1X3P6N

H12

H12 H_3P0

H_3P0

1

FM2FM2

1

H3 H_3P1NH3H_3P1N

1

FM3FM3

H4

H5

H_4P0H4H_4P0

H_4P0H5H_4P0

1

FM4FM4

1

Delete H8/9/10/11/13/14/15/22 for layout demand. 11/28

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

2

Add H22. 1202

Title

Size Document Number Rev

Date: Sheet of

H7

H6

H_1P1H7H_1P1

H_4P0H6H_4P0

1

H17

H16

H16 H_3P0

H_3P0

1

H21

H20

H20 H_3P0

H_3P0

1

H21 H_3P0

H_3P0

1

H19

H19 H_3P0

H_3P0

1

Compal Electronics, Inc.

DC/DC Interface

Montevina UMA LA6121P

1

H_4P0X5P0N

1

H18

H18 H_3P0

H_3P0

1

H23

H23 H_3P0

H_3P0

H22

H22 H_3P0

H_3P0

1

33 46Thursday, April 15, 2010

1

0.2

A

B

C

D

PR9

68_1206_5%

13

VIN

PD2

PD2 LL4148_LL34-2

LL4148_LL34-2

1 2

12

PC9

0.1U_0603_25V7K

+3VLP

12

PR13

PR13 68_1206_5%

68_1206_5%

VS

VINADPIN

PL1

SMB3025500YA_2P

+3VALW

SMB3025500YA_2P

12

PC5

100P_0402_50V8J

PR28

1 2

1K_0402_1%

1 2

PR27

@PR27

@

100K_0402_1%

12

PC3

PC3 100P_0402_50V8J

100P_0402_50V8J

+3VL

12

PC4

PC4 1000P_0402_50V7K

1000P_0402_50V7K

EC_ON31

BATT++

12

PC17

1000P_0402_50V7K

PL25

HCB4532KF-800T90_1812

1 2

PC18

1000P_0402_50V7K

12

PC19

DC_IN_S1

PJPDC1

1 1

2 2

4

3

2

1

@

SINGA_4TRJWT-R2513

12

PC2

1000P_0402_50V7K

DC040003600

PJP3

SUYIN_200275MR009G180ZR

1

2

3

4

5

6

7

8

9

10

G1

11

G2

PR34

1 2

PR33

1 2

100K_0402_1%@

1K_0402_1%

PR296

10K_0402_5%

BATT+

0.01U_0402_50V7K

BATT+

2

G

1 2

PH1 under CPU botten side :

CPU thermal protection at 92 degree C Recovery at 70 degree C

PH4 near main Battery CONN : Reverse

BAT. thermal protection at 90 degree C Recovery at 53 degree C

PD3

LL4148_LL34-2

100K_0402_1%

PR14

22K_0402_1%

1 2

13

D

PQ309

PQ309 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PR15

12

N1

12

+CHGRTC

PC13

0.22U_0603_25V7K

PQ1

TP0610K-T1-E3_SOT23-3

2

PJP602

1 2

PAD-OPEN 3x3m

12

PR32

PR36

3 3

4 4

PR36

100_0402_1%

SMB_EC_CK1 31

SMB_EC_DA1 31

1 2

PR31

6.49K_0402_1%

12

PR35

1K_0402_1%

A

6.49K_0402_1%

+3VL

BATT_TEMP 31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2007/05/29 2008/05/29

MAINPWON37

VL

PC20

0.1U_0603_25V7K

Compal Secret Data

Deciphered Date

12

PR42

PR42 10K_0402_1%

10K_0402_1%

1 2

12

PR41

@PR41

@

47K_0402_1%

Title

Size Document Number Rev

Date: Sheet of

C

PU3

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

8

7

6

5

PR40

PR40 22K_0402_1%

22K_0402_1%

1 2

PR43

14K_0402_1%

1 2

P/N:SD034140280

12

PH4

PH4 100K_0402_1%_NCP15WF104F03RC@

100K_0402_1%_NCP15WF104F03RC@

Compal Electronics, Inc.

DC Connector/CPU_OTP

Montevina Blade UMA LA4105P

12

PH1

PH1 100K_0402_1%_NCP15WF104F03RC

100K_0402_1%_NCP15WF104F03RC

D

1.0

34 46Thursday, April 15, 2010

A

PR8

1K_1206_5%

A A

PD1

VIN

12

LL4148_LL34-2

1K_1206_5%

1 2

PR19

1K_1206_5%

1 2

PR24

1K_1206_5%

1 2

PR38

1K_1206_5%

1 2

PQ7

TP0610K-T1-E3_SOT23-3

13

12

PR20

12

PR23

100K_0402_5%

2

100K_0402_5%

B+

B

C

D

12

PR37

13

PQ4

PQ4 DTC115EUA_SC70-3

ACOFF31,36

B B

2

DTC115EUA_SC70-3

2

PR37

100K_0402_5%

13

PQ3

PQ3 DTC115EUA_SC70-3

DTC115EUA_SC70-3

ACIN

Precharge detector

Min. typ. Max. H-->L 14.589V 14.84V 15.243V L-->H 15.562V 15.97V 16.388V

BATT ONLY

Precharge detector

Min. typ. Max. H-->L 6.138V 6.214V 6.359V L-->H 7.196V 7.349V 7.505V

PR25

255K_0402_1%

47K_0402_5%

13

B+

12

PR21

PR21 511K_0402_1%

511K_0402_1%

12

PR30

12

PQ6

PQ6 DTC115EUA_SC70-3

DTC115EUA_SC70-3

2

N1

8

3

P

+

1

O

2

-

PU12A

G

4

LM393DR_SO8

PC15

0.01U_0402_25V7K

LM393DR_SO8

PACIN 36

+5VALW

PR26

N1

7

O

PU12B

34K_0402_1%

PR79

PR79 10K_0402_5%

10K_0402_5%

PR26

2.2M_0402_5%

PC161

8

P

+

-

G

4

PR29

12

1

2

0.01U_0402_25V7K

5

6

12

PC16

1000P_0402_50V7K

12

PR39

150K_0402_1%

PRG++

13

D

PQ5

2

SSM3K7002FU_SC70-3

G

S

VL

12

PR22

100K_0402_1%

PD4

EN0_TRIP37

C C

ACON36

2

3

RB715F_SOT323-3

6251VREF36

1

12

PC14

0.1U_0603_25V7K

LM393DR_SO8

12

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/2/6 2010/2/6

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DCIN & DETECTOR

LA-5442P

D

35 46Thursday, April 15, 2010

0.1

4

D D

3

2

1

Iada=0~3.42A(65W)

AO4407A_SO8

PQ19

2

13

PQ20

PQ20 DTC115EUA_SC70-3

DTC115EUA_SC70-3

PACIN

ACON

ACOFF

AO4407A_SO8

8 7

5

1 3

PR89

22K_0402_5%

1 2

2

VIN

12

PR71

PR71 47K_0402_1%

47K_0402_1%

DTA144EUA_SC70-3

2

G

PACIN35

ACOFF31,35

DTA144EUA_SC70-3

2

13

D

PQ24

PQ24 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

ACON35

C C

B B

ADP_I = 19.9*Iadapter*Rsense

PQ14

4

150K_0402_1%

13

P2

1 2 36

12

PC48

0.1U_0603_25V7K

12

PR81

35

PACIN_1

13

D

2

G

S

PQ28

PQ28 DTC115EUA_SC70-3

DTC115EUA_SC70-3

PR72

PR72 200K_0402_1%

200K_0402_1%

IREF31

PQ15

S TR P1403EVG_SO8

1 2 3 6

4

FSTCHG31

PQ26

PQ26 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

150K_0402_1%

140K_0402_1%

6251VREF

8 7

5

1 2

PC49

5600P_0402_25V7K

PC57

1 2

0.01U_0402_25V7K

PR91

12

PR93

1SS355TE-17_SOD323-2

ADP_I31

12

PC64

1 2

11.5K_0402_1%

CP = 85%*Iada (Acer criteria); CP = 2.95A

2.2U_0603_6.3V6K

12

10

11

12

B+

RB751V-40_SOD323-2

PU5

1

VDD

2

ACSET

ACPRN

3

EN

CSON

4

CELLS

CSOP

5

ICOMP

6

VCOMP

7

PHASE

ICM

8

UGATE

VREF

9

CHLIM

BOOT

ACLIM

VADJ

LGATE

PGND

GND

ISL6251AHAZ-T_QSOP24

P3

PD11

1 2

PR78

10K_0402_5%

1 2

.1U_0402_16V7K

PC53

@ PC53

@

680P_0402_50V7K

CSON

1 2

PC56 6800P_0402_25V7KPC56 6800P_0402_25V7K

1 2

PR85 10K_0402_1%

1 2

PC59

100P_0402_50V8J

@

.1U_0402_16V7K

12

0.01U_0402_25V7K

PR95

PC51

PC60

1 2

12

1

2

2.37K_0402_1%

PR96

PR70 0.02_1206_1%PR70 0.02_1206_1%

4

3

6251VDD

PC50

ACSETIN

12

PR80

6251_EN CSON

100K_0402_1%

PR87

100_0402_1%

1 2

6251VREF35

6251aclim

DCIN

CSIN

CSIP

VDDP

PD5

24

23

22

21

20

19

18

17

16

15

14

13

1 2

VIN

1 2 12

PR222

10_1206_5%

DCIN

DCINDCIN

ACPRN

BST_CHG

6251VDDP

DL_CHG

PL2

FBMA-L11-321611-121LMA_2

CSIN

CSIP

12

PC214

1000P_0402_25V8J

PC67

0.1U_0603_25V7K

12

20_0603_5%

1 2

PC55

0.047U_0603_16V7K

1 2

PR83

20_0603_5%

12

PR84 20_0603_5%PR84 20_0603_5%

PC58 0.1U_0603_25V7K

1 2

2.2_0603_5%

PR92

2.2_0603_5%

1 2

2.2_0603_5%

PC66

4.7U_0805_6.3V6K

LX_CHG

28.2

DH_CHG

191K_0402_1%

PR221

ACSETIN

PR223

14.3K_0402_1%

PR82

PR86

0.1U_0603_25V7K

BST_CHGA

12

PD13

PD13 RB751V-40_SOD323-2

RB751V-40_SOD323-2

1 2

PR94

4.7_0603_5%

PC61

PC44

10U_1206_25V6M

12

6251VDD

CSOP

B+

CHG_B+

12

PC45

10U_1206_25V6M

PC46

0.1U_0603_25V7K

PQ25

AO4466_SO8

PQ27

AO4468L_SO8

PC47

12

2200P_0402_25V7K

DTC115EUA_SC70-3

578

3 6

241

S COIL 10UH +-30% SIL1045RA-100PF 4.5A

12

578

12

3 6

241

10K_0402_1%

PR90

4.7_1206_5%

PC65

680P_0402_50V7K

AO4407A_SO8

1 2 3 6

4

PR76

1 2

13

PQ22

PL5

1 2

PQ16

47K_0402_1%

CHG

1 2

8 7

5

PR73

PD9

1SS355TE-17_SOD323-2

1 2

PD12

1SS355TE-17_SOD323-2

1 2

2

PC52

PR88 0.02_1206_1%PR88 0.02_1206_1%

1

2

VIN

ACOFF

200K_0402_1%

12

0.1U_0603_25V7K

4

3

PR77

1 2

13

D

S

VIN

PACIN

PQ23

2

G

SSM3K7002FU_SC70-3

G

SSM3K7002FU_SC70-3

12

PC62

PC63

10U_1206_25V6M

PC68

10U_1206_25V6M

BATT+

12

CP mode

Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)

Vaclim=2.39*((11.5K//152K)/((2.37K//152K)+(11.5K//152K)))

CHGVADJ

CC=0.6~4.48A

IREF=0.7224*Icharge

A A

IREF=0.43V~3.24V

0V

1.882V

3.294V

CV mode

4V per cell

4.2V per cell

4.35V per cell

CHGVADJ31

-

4

PR97

18.2K_0402_1%

1 2

PR99

31.6K_0402_1%

3

6251VDD

12

47K_0402_1%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PR225

ACPRN

2

MMBT3904W_SOT323-3

Issued Date

12

PR226

PR226 10K_0402_1%

10K_0402_1%

C

PQ38

B

E

3 1

12

PR227

PR227 20K_0402_1%

20K_0402_1%

2

10K_0402_1%

1 2

PR224

PACIN

Compal Secret Data

ACIN 31

Deciphered Date

Compal Electronics, Inc.

Title

2010/2/62009/2/6

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER

ULV

1

0.1

36 46Thursday, April 15, 2010

0.1

A

B

C

D

E

2VREF_51125

12

PC302

1U_0603_10V6K

1 1

PR301

13.7K_0402_1%

1 2

PR303

B+

2 2

PL301

HCB2012KF-121T50_0805

1 2

PC316

OCP= 4.8A

Imax= 3A

Ipeak= 4.3A

F=305KHz

Rdsonmax= 19.6m

3 3

4 4

ENTRIP1

PQ305

SSM3K7002FU_SC70-3

B++

+3VLP

12

PC301

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

2200P_0402_50V7K

+3VALWP

ENTRIP1

13

D

S

12

PC303

4.7U_0805_25V6-K

3.3UH_SIQB74B-4R7PF_5.9A_20%

1

+

2

ENTRIP2

2

G

13

PL302

PC309

220U_6.3VM_R15

2

G

PQ307

PQ307 DTC115EUA_SC70-3

DTC115EUA_SC70-3

12

13

D

PQ306

PQ306 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

1 2

PR313

100K_0402_5%

2

12

PC54

@

PQ301

1

D1

2

D1

3

G2

4

S2

AO4932_2N_SO8

12

0.1U_0603_25V7K

1G 1S/2D 1S/2D 1S/2D

LG_3V

VL

PR605

1 2

100K_0402_1%

42.2K_0402_1%

42.2K_0402_1% PR314

PR314

UG1_3V

8 7 6 5

PR315

MAINPWON 34

VS

12

PC306

4.7U_0805_10V6K

PR307

1 2

0_0402_5%

PC307

0.1U_0402_10V7K

LX_3V

12

4.7_1206_5%

12

PC314

B++

PR309

1 2

499K_0402_1%

EN0_TRIP35

680P_0603_50V7K

Issued Date

1 2

+5VALWP

+3VALWP

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR303

20K_0402_1%

1 2

PR305

100K_0402_1%

1 2

25

BST_3V

UG_3V

10

11

12

PR311

100K_0402_1%

2VREF_51125

PJP302

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP303

PJP303

PAD-OPEN 4x4m

7

8

9

1U_0603_10V6K

PR302

30.9K_0402_1%

1 2

PR304

20K_0402_1%

1 2

PR306

ENTRIP1

130K +-1% 0402

1 2

1

2

VFB1

ENTRIP1

24

VO1

23

PGOOD

22

VBST1

21

DRVH1

20

LL1

19

DRVL1

VREG5

VCLK

17

18

TPS51125RGER_QFN24_4X4

BST_5V

UG_5V

LX_5V

LG_5V

PR308

2.2_0402_5%

1 2

PU301

P PAD

VO2

VREG3

VBST2

DRVH2

LL2

DRVL2

ENTRIP2

3

4

5

6

VFB2

VREF

TONSEL

ENTRIP2

GND

VIN

SKIPSEL

EN0

15

16

14

13

VL

12

PC311

12

10U_0805_10V6K

B++

(4.5A,180mils ,Via NO.= 9)

+5VALW

(3A,120mils ,Via NO.= 6)

+3VALW

2007/05/29 2008/05/29

10U_0805_10V6K

PC312

0.1U_0603_25V7K

Compal Secret Data

Deciphered Date

PR504

10K_0402_5%@

PR318

1 2

0_0402_5%

B++

12

PC304

2200P_0402_50V7K

PC308

0.1U_0402_10V7K

1 2

+3VALW

12

VL

+3VLP

12

PC317

PC305

0.1U_0402_25V6

10U_1206_25V6M

UG1_5V

12

4.7_1206_5%

PR316

12

PC315

680P_0603_50V7K

R_EC_RSMRST# 22

PJP304

2 1

PAD-OPEN 2x2m

PJP301

2 1

PAD-OPEN 2x2m

+5VL

+3VL

Title

Size Document Number Rev

Date: Sheet of

12

578

PQ302

AO4466_SO8

3 6

241

PL303

PL303 10UH +-30% SIL1045RA-100PF 4.5A

10UH +-30% SIL1045RA-100PF 4.5A

1 2

578

3 6

241

PQ304

PQ304 AO4712_SO8

AO4712_SO8

1

+

2

+5VALWP

PC310

150U_D_6.3VM

OCP= 6.8A

Imax= 4.6A

Ipeak= 6.534A

F=245KHz

Rdsonmax= 15m

Compal Electronics, Inc.

3.3VALWP/5VALWP

Montevina Blade UMA LA4105P

37 46Thursday, April 15, 2010

1.0

A

B

C

D

E

A

1 1

PR401

0_0402_5%

SUSP#31,33

PR410

@PR410

@

10K_0402_5%

2 2

12

+1.05V_VCCP

1 2

12

PC401

1000P_0402_50V7K

PR405

0_0402_5%

@PC401

@

+5VALW

PR403

PR403 100_0603_1%

100_0603_1%

1 2

12

PC409

4.7U_0603_6.3V6M

+1.05V_VCCP

1 2

PR408

3.74K_0402_1%

PR404

PR404 255K_0402_1%

255K_0402_1%

1 2

12

2

3

4

5

6

PR409

9.31K_0402_1%

PU401

TON

VOUT

VDD

FB

PGOOD

1

EN/DEM

GND7PGND

B

1 2

PR402

2.2_0603_5%

14NC15

DH_1.05V

13

BOOT UGATE

PHASE

LGATE

RT8209BGQW_WQFN14_3P5X3P5

8

VDDP

LX_1.05V

12

11

CS

10

9

BST1_1.05VBST_1.05V

0.1U_0402_10V7K

+5VALW

12

4.7U_0805_10V6K

1 2

PC402

1 2

PR406

17.4K +-1% 0402

PC415

PR411

1 2

0_0402_5%

DL_1.05V

578

3 6

578

3 6

241

C

12

0.1U_0402_25V6

PQ401

PQ401 AO4466_SO8

AO4466_SO8

PQ402

FDS6690AS-G_SO8

HCB1608KF-121T30_0603

12

PC404

4.7U_0805_25V6-K

PL402

1 2

HCB1608KF-121T30_0603

PC405

2200P_0402_50V7K

1.05V_B+

12

PC403

PC414

4.7U_0805_25V6-K

1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%

12

PR407

4.7_1206_5%

PC412

PC412 220P_0603_50V8J

220P_0603_50V8J

1 2

PL401

1 2

1

+

2

D

B+

12

PC406

PC406 680P_0402_50V7K@

680P_0402_50V7K@

+1.05V_VCCP

PC408

330U_2.5V_M

3 3

PJP401

+1.05V_VCCP

4 4

A

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP402

PJP402

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP403

PJP403

1 2

PAD-OPEN 4x4m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

(6A,240mils ,Via NO.=12)

+VCCP

Compal Secret Data

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1.05V_VCCP

Montevina Blade UMA LA4105P

D

38 46Thursday, April 15, 2010

1.0

5

D D

4

3

2

1

PR521

SYSON9,31,33

C C

+5VALW

B B

+5VALW

4.7U_0603_6.3V6M

PR522

100_0603_1%

1 2

PC522

0_0402_5%

+1.5VP

12

PC524

1000P_0402_50V7K

1 2

PR520 0_0402_5%PR520 0_0402_5%

1 2

PR501

9.76K_0402_1%

9.31K_0402_1%

@PC524

@

PR523

PR523 255K_0402_1%

255K_0402_1%

PR502

1 2

12

PC511

0.1U_0402_10V7K

PR510

UG_1.5V

LX_1.5V

1 2

LG_1.5V

0.1U_0402_10V7K

1 2

14.7K +-1% 0402

PR515

+5VALW

12

PC523

4.7U_0805_10V6K

PR508

0_0402_5%

1 2

UG1_1.5V

12

PR516

4.7_1206_5%@

12

PC519

@PC519

@

680P_0603_50V7K

BST_1.5V

1 2

2.2_0603_5%

1

PU502

2

TON

EN/DEM

3

VOUT

4

VDD

5

FB

6

PGOOD

GND7PGND

+1.5V

12

PR503

10K_0402_5%@

2.2_0603_5%

14NC15

13

BOOT UGATE

12

PHASE

11

CS

10

VDDP

9

LGATE

RT8209BGQW_WQFN14_3P5X3P5

8

1.5VP_B+

578

3 6

241

1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%

578

3 6

241

PL502

HCB1608KF-121T30_0603

12

PC516

PC504

4.7U_0805_25V6-K

PQ501

PQ501 AO4466_SO8

AO4466_SO8

PL501

1 2

PQ503

AO4712_SO8

12

PC505

2200P_0402_50V7K

12

PC510

4.7U_0603_6.3V6M

OCP= 16.05A

Imax= 9.23A

B+

12

PC521

0.1U_0402_25V6

+1.5VP

1

+

PC508

2

330U_2.5V_M

Ipeak=13.188A

DDR3_SM_PWROK 9

F=315KHz

Rdsonmax= 5.6m

PJP501

1 2

PAD-OPEN 4x4m

PJP502

5

1 2

PAD-OPEN 4x4m

+1.5VP

A A

(8A,320mils ,Via NO.= 16)

+1.5V

Security Classification

2007/05/29 2008/05/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/29 2008/05/29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

1.5VP

Montevina Blade UMA LA4105P

39 46Thursday, April 15, 2010

1

1.0

5

D D

C C

PJP601

+0.75VSP

1 2

PAD-OPEN 3x3m

(2A,80mils ,Via NO.= 4)

+0.75VS

4

+1.5V

12

PC601

10U_0805_10V4Z

SYSON#33

SUSP33

1 2

@

PR602

0_0402_5%

SSM3K7002FU_SC70-3

1 2

PR604

0_0402_5%

12

PC606

PC606 .1U_0402_16V7K@

.1U_0402_16V7K@

PQ601

2

12

PC602

PR601

PR601 1K_0402_1%

1K_0402_1%

10U_0805_10V4Z@

12

PR603

13

D

1K_0402_1%

G

1K_0402_1%

S

3

PU601

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

6

5

NC

7

NC

8

NC

9

TP

12

PC603

PC603 1U_0603_16V6K

1U_0603_16V6K

+5VALW

2

1

+0.75VSP

12

PC604

PC605

PC605 10U_0805_6.3V6M

10U_0805_6.3V6M

.1U_0402_16V7K

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

0.75VP

Montevina Blade UMA LA4105P

1

40 46Thursday, April 15, 2010

1.0

5

VGATE17,22

CLK_ENABLE#17

D D

CPU_VREF

1 2

PR130

5.11K_0402_1%

1 2

CPU_CSP1

C C

B B

PR132 470_0402_1%PR132 470_0402_1%

CPU_CSN1

PR136 470_0402_1%PR136 470_0402_1%

CPU_CSN2

PR137 470_0402_1%PR137 470_0402_1%

CPU_CSP2

PR138 470_0402_1%PR138 470_0402_1%

12

PC102

100P_0402_50V8J

12

PC111

100P_0402_50V8J

12

1 2

PC98 68P_0402_50V8JPC98 68P_0402_50V8J

1 2

PC99 0.22U_0603_10V7KPC99 0.22U_0603_10V7K

1 2

PC104 33P_0402_50V8KPC104 33P_0402_50V8K

1 2

PC106 33P_0402_50V8KPC106 33P_0402_50V8K

1 2

PC108 33P_0402_50V8KPC108 33P_0402_50V8K

1 2

PC112 33P_0402_50V8KPC112 33P_0402_50V8K

12

PR140

0_0402_5%

PR140

0_0402_5%

VSSSENSE

1U_0402_6.3V6K

CPU_DROOP

CPU_VREF

CPU_CSP1-2

CPU_CSN1-1

CPU_CSN2-1

CPU_CSP2-2

CPU_GNDSNS

CPU_VSNS

12

PR141

0_0402_5%

PR141

0_0402_5%

7

VCCSENSE

1 2

PR121

PR121 0_0402_5%@

0_0402_5%@

PC103

CPU_THERM

PR143

PR143 20K_0402_1%

20K_0402_1%

7

1

2

3

4

5

6

7

8

9

10

4

+3VS

12

PR120

PR119

10K_0402_5%@

1.91K_0402_1%

+3VS +5VS

12

PR124

PR235

0_0402_5%

@

41

DROOP

VREF

GND

CSP1

CSN1

CSN2

CSP2

GNDSNS

VSNS

THERM

0_0402_5%

CPU_VREF

12

CPU_V5FILT

40

GND

PR125 0_0402_5%PR125 0_0402_5%

PR123 124K_0402_1%PR123 124K_0402_1%

CPU_OSRSEL

CPU_TRIPSEL

CPU_ISLEW

CPU_TONSEL

36

37

38

39

ISLEW

V5FILT

TONSEL

OSRSEL

PU11

TPS51620RHAR_QFN40_6X6

VR_TT#11DPRSTP#12PSI#13VID614VID515VID416VID317VID218VID119VID0

VID5

VID6

PSI#

CPU_DPRSTP#

12

1 2

PR150 0_0402_5%PR150 0 _0402_5%

PR149 0_0402_5%PR149 0 _0402_5%

PR151 0_0402_5%PR151 0 _0402_5%

H_PSI#

CPU_VID67CPU_VID57CPU_VID37CPU_VID4

H_DPRSTP#

3

9,22

31

DPRSLPVR

VR_ON

PMON

PQ32

3 5

241

3 5

241

PQ33

3 5

PQ36

S TR AON6716L 1N DFN

PQ32 S TR AON6410 1N DFN-8

S TR AON6410 1N DFN-8

241

12

@

1 2

PR122 0_0402_5%PR122 0_0402_5%

PR128 499_0402_1%PR128 499_0402_1%

PR127 0_0402_5%@PR127 0_0402_5%

PR126 0_0402_5%PR126 0_0402_5%

CPU_VR_ON

CPU_DPRSLPVR

CPU_CLK_EN#

31

32

33

34

35

VR_ON

TRIPSEL

CLK_EN#

PWRMON

DPRSLPVR

VID0

VID1

VID2

VID3

VID4

1 2

PR154 0_0402_5%PR154 0 _0402_5%

PR153 0_0402_5%PR153 0 _0402_5%

PR155 0_0402_5%PR155 0 _0402_5%

PR152 0_0402_5%PR152 0 _0402_5%

7

7,9,21

PR157 0_0402_5%PR157 0 _0402_5%

7

CPU_VID2

CPU_VID1

PGOOD DRVH1

DRVL1

DRVL2

VBST2

DRVH2

20

1 2

CPU_VID0

VBST

V5IN

PGND

PR158 0_0402_5%PR158 0 _0402_5%

LL1

LL2

7

UGATE_CPU1

30

BOOT_CPU1

29

PHASE_CPU1

28

LGATE_CPU1

27

26

1 2

PC107 10U_0603_6.3V6M

25

LGATE_CPU2

24

PHASE_CPU2

23

BOOT_CPU2

22

UGATE_CPU2

21

7

PR133

1 2

0_0603_5%

PR159

1 2

0_0603_5%

+5VS

PD17

PD17 1SS355_SOD323-2

1SS355_SOD323-2

1 2

BOOT_CPU1-1

1 2

PC100

0.22U_0603_10V7K

+5VS

BOOT_CPU2-1

1 2

PC113

0.22U_0603_10V7K

1 2

PD16

PD16 1SS355_SOD323-2

1SS355_SOD323-2

+5VS

3 5

241

PQ31

S TR AON6716L 1N DFN

3 5

241

PQ35

PC94

12

PR135

6.8_1206_5%

CPU1_SNB

12

PC101

PC101 680P_0603_50V7K

680P_0603_50V7K

12

PQ37

S TR AON6410 1N DFN-8

2

12

PC95

10U_1206_25V6M

12

PC109

10U_1206_25V6M

12

PR142

6.8_1206_5%

CPU2_SNB

12

PC114

PC114 680P_0603_50V7K

680P_0603_50V7K

+CPU_B+

1

12

PC110

PC24768U_25V_M_R0.44+PC24768U_25V_M_R0.44

12

PC96

2200P_0402_50V7K

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR129

17.8K_0402_1%

+CPU_B+

CPU_CSP1

10U_1206_25V6M

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR144

17.8K_0402_1%

CPU_CSP2

+

2

1 2

12

1 2

PR134

28.7K_0402_1%

1 2

12

1 2

PR148

28.7K_0402_1%

+

2

PL13

PR131

69.8K_0402_1%

1 2

CPU_SN-1

1 2

PC105

0.033U_0402_16V7K

PL14

PR145

69.8K_0402_1%

1 2

CPU_SN-2

1 2

PC115

0.033U_0402_16V7K

PL12

HCB4532KF-800T90_1812

1 2

PC248

68U_25V_M_R0.44

PH2

100K_0402_1%_NCP15WF104F03RC

CPU_CSN1

PH3

100K_0402_1%_NCP15WF104F03RC

CPU_CSN2

1

B+

+VCC_CORE

A A

Compal Electronics, Inc.

Title

+CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+CPU_CORE

Size Document Number Rev

Custom

Date: Sheet of

41 46Thursday, April 15, 2010

1

1.0

5

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power CircuitVersion Change List ( P. I. R. List ) for Power Circuit

Page#

Item phase

Page#Page#

ItemItem

Reason for change

Reason for changeReason for change

4

Description

DescriptionDescription

3

phase

phasephase

2

modifyItem

modifymodify

1

Rev.

Rev.modify

Rev.Rev.

1

D D

2

3

4

5

6

7

8

C C

9

10

11

12

13

14

15

16

B B

17

35

37

34

41

39

31

41

38

41

34/35

36

41

37 COST DOWN Change PQ304 DVT From SB000004J80 change to SB00000AJ00

38 COST DOWN Change PQ401/PQ402 DVT PQ401 From SB00000BO00 change to SB00000CG00

39 DVT

change charge IC for cost down change charge IC from TPS24740 to ISL6251

Due to ISL6251 can't support pre-charge

Add pre-charge and Vin detector function

DVT36

DVT

and Vin detector function

for common design

Change CPU OTP IC for Cost down

PH2,PH3 size from 0603 change to 0402 for cost down.

PC510 size from 0805 change to 0603 for Cost down

for battery can not be charging full issue (notes issue number: ACIC009)

change load line voltage

PC302 change to 1U; PC306 change to 4.7U

CPU OTP IC from LM358 change to G718

PH2,PH3 size from 0603 change to 0402

PC510 size from 0805 change to 0603

CHGVADJ signal from EC 108pin change to 72pin CHGVADJ signal from EC 108pin change to 72pin

change PR130 from 4.02K change to 5.11K

DVT

DVT PR130 from SD034402180 change to SD028511100

COST DOWN Delete CPU_core L-SIDE MOS PQ31 PQ35 DVT delete: PQ31 PQ35

COST DOWN Change PL402 from 1U to 1.8U

COST DOWN Change CPU_core L-side

DVT

DVT From SB00000GL00 change to SB00000HR00

COST DOWN Change PD1/PD2/PD3 DVT From SC11N414880 change to SC1000001Y80

COST DOWN Change PD13 DVT From SC1B751V010 change to SCS00000Z00

COST DOWN Change PL13/PL14 DVT From SH00000F000 change to SH000005680

COST DOWN Change PQ501/PQ503

delete: pu101 and Support Components. add: PU5 and Support Components.

add PU12

PC302 from 0.22U change to 1U PC306 from 10U change to 4.7U

delete: PU1 and Support Components

from SL210021F20 change to SL200000V00

from SE093475K80 change to SE107475M80

From SH000008V80 change to SH000008U80

PQ402 From SB000009F80 change to SB00000AJ00

PQ501 From SB00000BO00 change to SB00000CG00 PQ503 From SB000009F80 change to SB00000AJ00

18

34 COST DOWN

Remove PU2;Connect +3VLP to +CHGRTC

DVT Remove SA009200010

19

20

21

22

34 design change Add PQ1/PQ309 and support circuit DVT Add PQ1:SB906100210 PQ309:SB000009610

34 change PU3 support circuit

35 cost down delete VIN detector circuit DVT

35 change RTCVREF to 62521VREF and

support circuit

change from EN0_TRIP to MAINPWON

PR21 change from 499k to 511k PR25 change from 499k to 255k PR39 change from 191k to 150k

DVT

change from EN0_TRIP to mainpwon

use ISL6251 VIN detector function

PR21 change from SD034499380 to SD034511300 PR25 change from SD034499380 to SD034255300 PR39 change from SD034191380 to SD028150300

change RTCVREF to 62521VREF

23

A A

35,36 COST DOWN Change PQ5/PQ23/PQ24/PQ26 DVT From SB502060000 change to SB000009610

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Power Changed-List History-1

Montevina Blade UMA LA4105P

1.0

42 46Wednesday, April 14, 2010

1

1.0

A

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power CircuitVersion Change List ( P. I. R. List ) for Power Circuit

Page#

Item phase

Page#Page#

ItemItem

Reason for change

Reason for changeReason for change

B

Description

DescriptionDescription

C

phase

phasephase

D

modifyItem

modifymodify

E

Rev.

Rev.modify

Rev.Rev.

1 1

24

25

26

27

28

29

30

31

2 2

32

33

36

37

38

39

COST DOWN

for common design

COST DOWN

COST DOWN change +3/5VALW enable circuit

COST DOWN

change +1.05V_VCCP OCP setting change PR406 from 13.7K to 14.7K PR406 from SD034137200 to SD034147200

COST DOWN

change PQ15 to AO4407L DVT36

change PQ27 to AO4468L

change ISL6251 ACIN function

change PL303 to SH000002L80

change +3/5VALW enable circuit

change PQ402 to FDS6690AS

change PC408 from 220U to 330U

change PL501 from 1UH to 2.2UH

Change PC508 from Tantalum CAP to Aluminum

DVT

DVT PC408 from SGA20221150 to SF000002Z00

DVT PL501 from SH000008V80 to SH00000FD10

DVT

PQ15 from SB00000DL00 to SB944070010

change PQ27 from SB00000CG00 to SB000009510

change ISL6251 ACIN function

PL303 from SH162100M10 to SH000002L80

PQ402 from SB00000AJ00 to SB000004J10

PC508 from SGA00000W00 to SF000002Z00

CAP

34

35

36

37

38

39

3 3

39

41

change +1.5VP OCP setting

COST DOWN Change PQ32,PQ37 from TPCA8023 to TPCA8030 DVT PQ32,PQ37 from SB00000CK00 to SB00000HL00

42

43

44

COST DOWN cause CPU hang up issue

36 for 030 common design Change PR91, PR93, PR97

change PR515 from 8.87K to 14.7K

DVT PR515 from SD034887180 to SD034147200

PVTshortage issue Change PR406 from 14.7K to 17.4K PR406 from SD03414700 to SD03417400

PVTShortage issue Change PQ15 from AO4407L to S TR P1403 PQ15 from SB00000DL00 to SB00000DM00

ADD PQ31,PQ35 ADD PQ31,PQ35

PVT

Pre-MP

PR91,PR93,PR97 change to 150K,140K,18.2K

TPCA8030-H change to AON6410

40 41

For shortage issue Change CPU_CORE H/L side MOS Pre-MP

TPCA8036-H change to AON6716L

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Power Changed-List History-2

Montevina Blade UMA LA4105P

43 46Wednesday, April 14, 2010

E

1.0

5

4

3

2

1

Item (Reason for change)Fixed Issue PAGE Modify List Date

1

2 LCD can't display. 32

3 Follow Vendor's datasheet. 25

D D

4 Follow ID demand. 32

5

31Keyboard can't work.

Change R584/R599 pull up PWR from +3valw to +3VL

Add (R2406) Lid_sw# pull up to +3VL with 100K.

Change Lan chip pin15 to pull down with 10K.

Change Wireless/BT from 2 colore to single colore(Amber)

26To meet KBC PWR plane

Change KILL_SW# pull high PWR plane to +3VL

2009/12/17

2010/01/04

Phase

DVT

6 Follow ID. 31 Delete wow audio/video/dj on EC. 2010/01/04 DVT

7 Follow ME demand. 32 Change JP60 to 8pin. DVT2010/01/04

8 17 Delete R123 from BOM 2010/01/04 DVT

9

10

11 Follow LAN datasheet. 17/25

C C

Kill switch is HW part.

SYSON should be 3V.

26 Delete CONN@ from schematics. 2010/01/04 DVT

31 Change R213(8.2K) to CAP(C1415 1U). 2010/01/04 DVT

Delete R191 from Bom,and add R467 to pull up LAN_CLKREQ# with 10k.

2010/01/04 DVT

12 6 Change to 3pin FAN. 2010/01/04 DVT

13 Cost down. 28 Change to 2pin SPK, and change AMP to SA00003X300 2010/01/04 DVT

14 EC common design. 31 2010/01/04 DVT

15

Follow panel PWR sequence.

19 Delete C232 from BOM. 2010/01/08 DVT

add FAN_SPEED at EC pin28, and Kill switch change to pin26.

16 26 Add ESD D8 diode on Kill switch. DVT2010/01/11

17 Follow EC common design. 26/31 Change WL_OFF# to EC pin106 control. 2010/01/11 DVT

18 Follow EC common design. 29/31

19 Key part demand. 29/26

B B

20 32For debug.

21

22

Change WL/BT LED to be always light when WL/BT work .

follow PWR's suggestion.

31/32 Change WL_BT_LED# contral to EC pin86. 2010/01/14 DVT

31 Change VCTRL from EC Pin108 to 68 2010/01/14 DVT

Change BT_OFF to EC pin99 control.

Change to 8pin BT module.

Add PWR button SW on M/B.

2010/01/11 DVT

2010/01/13 DVT

23 Follow EC's request. 31 change EC pin108 as EC_SEL. 2010/01/18 DVT

24 Cost down. change C150/C135 to SF000002000. change C131/3200/94/98/77/115/458 to SF000001500. 2010/01/18 DVT

25

Follow PWR net name

31

change VTRL to CHGVADJ on EC pin68.

2010/01/19 DVT

26 Follow EC common design. 31 Change CHGVADJ from EC pin68 to pin72 2010/01/20 DVT

27 29/31

A A

Follow EC common design. 2010/01/20 DVT

28

It is convenient for EC debug.

5

26/31

4

Add R602/R603/Q14. change BT_OFF to BT_OFF#.

EC-TX and EC-RX should connect to WL connector(JP7) 49 pin and 51 pin.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

2010/01/20 DVT

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HW PIR 3

Montevina Blade UMA LA4105P

1

1.0

44 46Wednesday, April 14, 2010

1.0

5

4

3

2

1

Item (Reason for change)Fixed Issue PAGE Modify List Date Phase

31no use ADP_ID.1 delete location R592(10K).

2 31

3 31

D D

4 28

5 28

6 28 DVT

7 Cost down. 18

no use CIR_IN.

no use TP_BTN#.

Modify Gain to 10db.

delete location R720(10K). 2010/01/20

delete location R587(10K). 2010/01/20

Change C504 to 0.1U.

Change R436/R437 to 30K.

Change R427/R428 to 10K.

Change L2/L3/L4 to SM01000DS00. Change C228/C229/230 to SE07122AC80. Install C225/C226/C227 with SE07122AC80. Modify as KSWAA.

2010/01/20

2010/01/21

2010/01/22 DVT

DVT

8 Modify Gain to 10db. Change C504 back to 0.22U.28 DVT2010/01/23

Change R429 from 10K to 5K(SD00000HN80).28Modify Gain to 10db.9 2010/01/23 DVT

10 Cost down. 19/29 Change Q7/Q105 from SB923010020 to SB934130000, modify as KSWAA. 2010/01/23 DVT

11 Cost down. 28 Change C66/C1450 from SE000004880 to SE053106Z80, 2010/01/23 DVT

C C

12 Cost down. Delete R699,R700,R701,R702,R703,R443 (SD028000080)26/31 2010/01/23 DVT

13 Modify the lighteness of LED3. 32 Change R151 from 453ohm to 300ohm (SD028300000) 2010/01/25 DVT

14 28 Uninstall C1492/C1493 (SE071470J80) 2010/01/25 DVT

15 28 Add Location R1281/R1282 at SPK side.(SD013000080) 2010/01/26 DVT

16

Cost down and modify the lighteness of LED.

32 Change R146 from SD034453080 to SD028300000(300ohm) 2010/01/26 DVT

17 Modify the lighteness of LED1/D53. 32 Change R1098/R1101 fromSD028820080 to SD028220080 (220ohm) 2010/01/26 DVT

18

19 17 Delete Location CLRP1. 2010/01/28 DVT

B B

Follow WLAN+BT datasheet.

26 Connect JP7 Pin37/43 to GND. 2010/01/26 DVT

20 32 Add ESD diode D31@ at ON/OFFBTN&ON/OFFBTN_LED# 2010/01/28 DVT

21 29 Uninstall R603. 2010/01/28 DVT

22 18

Change NET C_RED/GRN/BLU to M_RED/GREEN/BLUE.

2010/01/28 DVT

23 26Follow EC common desing. Add R1094(SD028100380) to pull down EC_TX with 100kohm. 2010/01/28 DVT

24

25 Follow EC common design. 31

26 22

27 EMI demand. 18/19/32 install D31/C223/C224/C302/303. 2010/02/01 DVT

A A

Cost down, follow PWR's demand.

Follow EC's suggestion. 2010/02/01 DVT

8 Change C41/C42@/C43/C44 to SGA19331D10. 2010/01/29 DVT

uninstall R590.

2010/02/01 DVT

Add location R347, and uninstall R334.

28 19/28 Change Q7/C66 back to SB923010020/SE000004880. 2010/02/02 DVT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HW PIR 3

Montevina Blade UMA LA4105P

1

1.0

45 46Wednesday, April 14, 2010

1.0

5

4

3

2

1

Item (Reason for change)Fixed Issue PAGE Modify List Date Phase

2010/03/05

2

3

D D

4

5

6

7

8

Modify the lightness of LED2 32 Modify R120 from SD028220080(220ohm) to SD028100080(100ohm). 2010/03/15 PVT

Modify the lightness of LED2 32 Modify R146 from SD028300000(300ohm) to SD028120000(120ohm). 2010/03/15 PVT

Modify the lightness of LED1/D53 32 Modify R1098/R1101 from SD028220080(220ohm) to SD00000LK80(90.9ohm). 2010/03/15 PVT

Modify the lightness of LED3 32 Modify R151 from SD028300000(300ohm) to SD028150000(150ohm). 2010/03/15 PVT

SPK noise issue. 28 Modify R436/r437 from SD014300280(30Kohm) to SD014150280(15Kohm). 2010/03/15 PVT

9

10

11

C C

12

Add BT_OFF# pull high to +3VS.

Reserver ICH_susclk for EC's CLK IN.

13

14

15

16

Set E0 EC as main source. 31 Change EC P/N to SA00001J5A0(E0) 2010/03/31 Pre_MP

Change R249 to 4.99K that have correct description.

Can't disable BT for combo card. 26/29 Add location Q15(SB570020020), add location R155/R439(SD028000080), add location(SD028100280) 2010/04/01 Pre_MP

19 Reserve location C71 for BKOFF# 2010/03/05 PVT

31 Change R1131 from 22ohm SD028220A80 to 0ohm SD028000080 2010/03/05 PVT

28 Reserve C304 for +MIC1_VREFO 2010/03/15 PVTAvoid MIC noise issue.

26Can't disable BT for combo card.

22/31

31

Install R603(10K)-->SD028100280.29

Reserve R438 to connect BT_OFF# with JP7 pin5.

Delete T58 and reserver R592.

Install R1093 and uninstall R1091

2010/03/24 Pre_MP

2010/03/25 Pre_MP

2010/03/29 Pre_MPSet E0 EC as main source.

31 Change R249 from SD00000HN80 to SD014499180. 2010/03/31 Pre_MP

PVT19White screen issue.1 Install R245(10K)-->SD028100280.

17

18

19

B B

Reserver ICH_susclk for EC's CLK IN.

31

Reserver location R605 2010/04/08 Pre_MP

EMI Request. 25 Add C1409/C1410/C1411(SE070104Z80). 2010/04/08 Pre_MP

20

21

22

23

24

25

26

27

A A

28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HW PIR 3

Montevina Blade UMA LA4105P

1

0.3

46 46Wednesday, April 14, 2010

0.3

Compal LA-6121P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual