COMPAL LA-6101P Schematics

A

ZZZ1

JDCIN1

ZZZ2

PCB

DAZ@

1 1

11/18 Change PCB P/N from DA60000G300 to DA60000G200

JDCIN1

DCIN Cable

45@

11/03 Add DC-IN Cable P/N : DC301009N00

ZZZ1

LA-6101P

M/B

M/B DA2@

DA2@

ZZZ3

LS-6101P

FUN/B

FUN/B DA2@

DA2@

12/04 Change PJP1 to JDCIN1

ZZZ4

LS-6102P

FP/B

FP/B DA2@

DA2@

B

ZZZ6

ZZZ5

LS-6103P

LED/B

LED/B DA2@

DA2@

ZZZ6

LS-6104P

PWR/B

PWR/B DA2@

DA2@

C

D

E

02/26 Change LA-6101P P/N from DA60000G200 to DA60000G210

02/26 Add DAZ P/N and other small board P/N

02/26 Change DAZ P/N from DAZ0D9001001 to DAZ0D900101

Compal Confidential

2 2

NAU00 LA-6101P Schematics Document

Intel Arrandale Processor with DDRIII + Ibex Peak-M

SV M/B

3 3

2010-03-09

Rev : 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

NAU00 M/B LA-6101P Schematics

148Tuesday, March 09, 2010

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E

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1.0

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B

C

D

E

Compal Confidential

Model Name : NAU00 File Name : LA-6101P

1 1

Clock Generator

IDT: 9LRS3199AKLFT SILEGO: SLG8SP587

133/120/100/96/14.318MHZ to PCH

48MHZ to CardReader

Page 12

Fan Control

Page 37

Intel

Arrandale

SV

Processor

rPGA988A

Page 4,5,6,7,8,9

Memory Bus (DDRIII)

Dual Channel

1.5V DDRIII 800/1066/1333

6.4G/8.5G/10.6G

100M/133M/166M(CFD)

204 Pin DDRIII SO-DIMM x2

BANK 0, 1, 2, 3

Page 10,11

HDMI Conn.

Page 24

2 2

HDMI Level Shifter

ASmedia AM1442T

Page 24

100MHz

New Card

Port 3

Page 37

3 3

CRT Conn.

Page 23

LVDS Conn.

ABD PCIE Gen1 2.5GT/S

Mini Card

WLAN

LAN(GbE)

Atheros 8151

Port 2 Port 1

Page 32 Page 26

Page 22

LVDS

CRT

HDMI

PCI-Express X1

PortPortPort

FDI x8

100MHz

1GB/s x4

DMI x4

100MHz

2.7GT/s

Intel

Ibex Peak-M

PCH

FCBGA 1071Pin

Page 13,14,15,16,17,18,19,20, 21

LPC

33MHz

USB Conn.x3

Port 0,3 (USB) Port 1 (eSATA)

Page 31

USB

3.3V 48MHz

HD Audio

SATA

Gen1 1.5GT/S ,Gen2 3GT/S

SPI

BIOS ROM

4MB

Page 13

CardReader

Port 5

3.3V 24MHz

HDD

Port 0

Page 25 Page 32

Bluetooth Camera

Port 11

Port 2

FingerPrint

UPEK TCS5BB6A2Realtek RTS5138 Port 9

Page 28 Page 35 Page 22 Page 36

100MHz

3G Card

Port 13

Page 32

SSD

Port 1,5 Mini card slot

e-SATA Conn.

Port 4

Page 31

HDA Codec

Realtek ALC259

CPU XDP

Page 35

RTC Ckt.

Page 35

RJ-45

Page 27

ENE KB926E0

Page 33

Touch Pad Int.KBD

Page 35

Page 36

Small Board

Power/B

LS-6104P

Thinklight/B

LS-6103P

Int. Speaker Int. Digital MIC

Page 30 Page 30

Page 29

Phone Jack x 2

Power On/Off Ckt.

Page 34

4 4

DC/DC Interface Ckt.

Power Ckt.

Page 34

Page 38

G-Sensor

Page 25

A

EC I/O Buffer EC ROM

Page 33 Page 36

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

128kB

Issued Date

2009/10/10 2010/10/10

C

Function/B

LS-6101P

Compal Secret Data

Deciphered Date

FP/B

D

LS-6102P

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

NAU00 M/B LA-6101P Schematics

248Friday, February 26, 2010

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A

Voltage Rails

Power Plane Description

VIN

B+

+CPU_CORE

1 1

2 2

+0.75VS 0. 75V switched powe r rail for DDR terminator

+1.05VS

+1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF

+1.5V ON ON OFF

+1.5VS

+1.8VS 1.8V switched power rail

+3VALW 3.3V always on power rail

+3V

+3V_LAN

+3VS

+5VALW

+5VS

+5V 5V power rail for PCH

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only wit h AC power available, otherwise it is OFF.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

1.05V switched power rail for PCH

1.5V power ra il for DDRIII

1.5V switched power rail

3.3V power rail for PCH

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail

5V switched power rail

B

S1

S3 S5

N/A N/A N/A

ON

ON OFF OFF

ON

ON ON

ON

ON ON ON

ON

N/AN/AN/A

OFF

ON

OFF

ON ON*

ON

ON*

OFF

ON ON*

OFF

OFFON

ONON

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOW

LOWLOWLOW

LOW LOW LOW LOW

HIGHHIGHHIGH

HIGH

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

ON

OFF

ON

OFF

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

ON ON

ON

OFF

max

E

LOW

OFF

BOARD ID Table

External PCI Devices

Device IDSEL#

REQ#/GNT#

Interrupts

Board ID

0

*

1 2 3 4 5 6 7

PCB Revision

0.1

EC SM Bus1 address

3 3

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

Ibex SM Bus address

Device

Clock Generator (9LRS3199AKLFT, SLG8SP587)

DDR DIMM0

DDR DIMM2

ISL90727 ISL90728

4 4

A

Address

1101 0010b

1001 000Xb

1001 010Xb

0101 1100b 0111 1100b

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

C

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

NAU00 M/B LA-6101P Schematics

348Friday, February 26, 2010

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5

JCPU1A

DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3

DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2

H_FDI_FSYNC0<15> H_FDI_FSYNC1<15>

H_FDI_LSYNC0<15> H_FDI_LSYNC1<15>

H_FDI_INT<15>

DMI_PTX_HRX_P3

DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3

DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3

H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7

H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7

D D

C C

B B

A A

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

CONN@

DMI Intel(R) FDI

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

4

PEG_IRCOMP

EXP_RBIAS

R1

1 2

R2

1 2

49.9_0402_1%

750_0402_1%

DMI_PTX_HRX_N[0..3] <15> DMI_PTX_HRX_P[0..3] <15>

DMI_HTX_PRX_N[0..3] <15> DMI_HTX_PRX_P[0..3] <15>

H_FDI_TXN[0..7] <15> H_FDI_TXP[0..7] <15>

3

11/12 Delete R3(@),R4(@),R5(@),R6(@)

11/17 Delete R9,R10

CFG0 - PCI-Express Configuration Select

*1:Single PEG 0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

2

JCPU1E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_rPGA,R1P0

CONN@

(CFD Only) (CFD Only)

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD_TP_59 RSVD_TP_60

RESERVED

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

RSVD32 RSVD33

RSVD34 RSVD35

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

KEY RSVD62 RSVD63 RSVD64 RSVD65

VSS

1

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15

11/17 Delete R7,R8

C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

*:Default

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR (1/6) DMI,FDI,PEG

NAU00 M/B LA-6101P Schematics

1

of

448Tuesday, March 09, 2010

1.0

5

JCPU1B

H_COMP3

H_COMP2

H_COMP1

H_COMP0

@

PAD

T1

R19

1 2

0_0402_5%

R29

1 2

0_0402_5%

R32

R32 0_0402_5%

0_0402_5%

R34

R34 0_0402_5%

0_0402_5%

R37

R37 0_0402_5%

0_0402_5%

R40

1 2

0_0402_5%

1 2

T1

1 2

D D

H_PECI<18>

H_PROCHOT#<33,47>

H_THERMTRIP#<18>

H_PM_SYNC<15>

C C

H_CPUPWRGD<18>

PM_DRAM_PWRGD<15>

VCCP_POK<45>

R620 1K_0402_1%R620 1K_0402_1%

R621 560_0402_5%R621 560_0402_5%

SKTOCC#_R

H_CATERR#

H_PECI_R

H_PROCHOT#

H_THERMTRIP#_R

H_CPURST#

H_PM_SYNC_R

H_CPUPWRGD_1

H_CPUPWRGD_0

PM_DRAM_PWRGD_R

VCCP_POK_R

10/30 Add R620,R621 (Follow NIWE2)

PLT_RST#<17,33>

2009/2/4 #414044 DG Update Rev1.11

R42

1 2

1.5K_0402_1%

PLT_RST#_R

12

R43

R43 750_0402_1%

750_0402_1%

JCPU1B

AT23

AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

IC,AUB_CFD_rPGA,R1P0

CONN@

10/21 Delete R41 Delete Net : H_PWRGD_XDP,H_PWRGD_XDP_R

4

COMP3

COMP2

COMP1

COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

MISC THERMAL

DPLL_REF_SSCLK#

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY# PREQ#

TCK TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TDI

3

11/12 Delete R11,R12,R15,R16 (Layout Spacing)

CLK_CPU_BCLK

A16

CLK_CPU_BCLK#

B16

CLK_CPU_ITP_R

AR30 AT30

E16 D16

A18 A17

F6

AL1 AM1 AN1

AN15 AP15

AT28 AP27

AN28 AP28 AT27

AT29 AR27 AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

CLK_CPU_ITP#_R

CLK_CPU_DMI CLK_CPU_DMI#

CLK_CPU_DP_R CLK_CPU_DP#_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PM_EXTTS#0 PM_EXTTS#1_R

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO XDP_TDI_M XDP_TDO_M

XDP_DBR#_R

R572 0_0402_5%R572 0_0402_5% R573 0_0402_5%R573 0_0402_5%

R36 0_0402_5%@R36 0_0402_5%@

1 2

PAD @

T17

PAD @

T18

1 2 1 2

SM_DRAMRST# <10>

11/05 Delete R21(@)

R25 10K_0402_5%R25 10K_0402_5%

1 2

R27 10K_0402_5%R27 10K_0402_5%

1 2

R28 0_0402_5%R28 0_0402_5%

1 2

11/25 Change R36 from mount to @ (Follow NIWE2)

ESD Recommend

10/21 Delete Net : XDP_OBS[7:0]

2009/2/4 Delete dampling resistor for power noise and Layout space issue

2

CLK_CPU_BCLK <18> CLK_CPU_BCLK# <18>

10/21 Delete R13,R14, Add T17,T18

CLK_CPU_DMI <14> CLK_CPU_DMI# <14>

10/30 Delete Net : CLK_CPU_DP, CLK_CPU_DP# Delete R17,R18

+1.1VS_VTT

PM_EXTTS#0_1 <10,11>

XDP_DBRESET#

XDP_DBR#_R

XDP_DBRESET# <15>

C500 0.1U_0402_16V4Z@C500 0.1U_0402_16V4Z@

1 2

Processor CLK

Reference Input Clock

BCLK/BCLK#

PEG_CLK/ PEG_CLK#

DPLL_REF_SSCLK/ DPLL_REF_SSCLK#

10/28 Delete R31,R33(@),R38(@),R39 Delete Net : XDP_TDI_R,XDP_TDO_R

XDP_PRDY# XDP_TMS XDP_TDI XDP_PREQ# XDP_TCLK

XDP_TRST#

XDP_TDO_M

XDP_TDI_M

Input Frequency

133MHz

100MHz

120MHz

R20 51_0402_5%@R20 51_0402_5%@

1 2

R22 51_0402_5%@R22 51_0402_5%@

1 2

R23 51_0402_5%@R23 51_0402_5%@

1 2

R24 51_0402_5%@R24 51_0402_5%@

1 2

R26 51_0402_5%@R26 51_0402_5%@

1 2

R30 51_0402_5% R30 51_0402_5%

1 2

12

R35

R35 0_0402_5%

0_0402_5%

1

Associated PLL

Processor/Memory /Graphic

PCI Express/ DMI/FDI

Embedded Displayport

+1.1VS_VTT

+3VALW

5

2

P

B

4

Y

1

A

G

U1

3

NC7SZ08P5X_NL_SC70-5

Note: When implement S3 power reduction not to pop,R53,R44 pop U1,R45,R54

11/23 Change R44,R53 from mount to @ Change U1,R45,R54 from @ to mount

VCCP_POK

SSM3K7002FU_SC70-3

2

G

Q37

VCCP_POK

+5VALW

12

R574

R574 10K_0402_5%

10K_0402_5%

S3_0.75V_EN

13

D

S

12/04 Change Q37 from SB000008J00 to SB000009610 (Layout Spacing)

4

VCCP_POK <45>

S3_0.75V_EN <44>

H_CATERR# H_PROCHOT# H_CPURST#

H_COMP0 H_COMP1 H_COMP2 H_COMP3

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

11/16 Reserve C530,C531,C532 for avoiding switching noise 11/23 Change C530,C531,C532 from @ to mount

VCCP_POK

PM_DRAM_PWRGD_R

H_CPUPWRGD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R46 49.9_0402_1%R46 49.9_0402_1%

1 2

R47 68_0402_5%R47 68_0402_5%

1 2

R48 68_0402_5%@R48 68_0402_5%@

1 2

R49 49.9_0402_1%R49 49.9_0402_1%

1 2

R50 49.9_0402_1%R50 49.9_0402_1%

1 2

R51 20_0402_1%R51 20_0402_1%

1 2

R55 20_0402_1%R55 20_0402_1%

1 2

R58 100_0402_1%R58 100_0402_1%

1 2

R60 24.9_0402_1%R60 24.9_0402_1%

1 2

R61 130_0402_1%R61 130_0402_1%

1 2

C530 100P_0402_50V8JC530 100P_0402_50V8J

1 2

C531 100P_0402_50V8JC531 100P_0402_50V8J

1 2

C532 100P_0402_50V8JC532 100P_0402_50V8J

1 2

2009/10/10 2010/10/10

3

1.1K_0402_1%

3K_0402_1%

+1.5V_1

R44

@

R53

@

12

R45

1.5K_0402_1%

12

R54

750_0402_1%

5

B B

PM_DRAM_PWRGD_R

A A

+1.1VS_VTT

Compal Secret Data

Deciphered Date

10/21 Delete JP1,R52,R56,R57,R59,C1 Delete Net : H_CPUPWRGD,H_PWRGOOD_R, PBTN_OUT#_XDP,CLK_CPU_XDP,CLK_CPU_XDP#

XDP_DBRESET#

XDP_TDO

10/22 Change R62 from mount to @ 10/30 Change R62 from @ to mount (Follow NCQD0) 11/25 Change R62 from mount to @ (Follow NIWE2)

2

1 2

Title

Size Document Number Rev

B

Date: Sheet

R62

@ R62

@

1K_0402_5%

R63

R63 51_0402_5%

51_0402_5%

Compal Electronics, Inc.

PROCESSOR (2/6) CLK,JTAG

NAU00 M/B LA-6101P Schematics

+3VS

+1.1VS_VTT

1

Leakage Issue

548Tuesday, March 09, 2010

1.0

of

5

JCPU1C

C10

D10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ10

AL10

AK12

AK8

AK11

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

A10

B10

E10

F10

J10

AJ7 AJ6

AJ9

AL7

AL8

C7 A7

A8 D8

E6 F7 E9 B7 E7 C6

G8

K7

J8

G7

J7

L7 M6 M8

L9

L6

K8 N8 P9

U7

JCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

DDR_A_D[0..63]<10>

DDR_A_DM[0..7]<10>

DDR_A_DQS#[0..7]<10>

DDR_A_DQS[0..7]<10>

DDR_A_MA[0..15]<10>

DDR_A_D0 DDR_A_D1

D D

C C

B B

DDR_A_BS0<10> DDR_A_BS1<10> DDR_A_BS2<10>

DDR_A_CAS#<10> DDR_A_RAS#<10> DDR_A_WE#<10>

DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0

DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_A_MA14

DDR_A_MA15

DDR_A_CLK0 <10> DDR_A_CLK0# <10> DDR_A_CKE0 <10>

DDR_A_CLK1 <10> DDR_A_CLK1# <10> DDR_A_CKE1 <10>

DDR_A_CS0# <10> DDR_A_CS1# <10>

DDR_A_ODT0 <10> DDR_A_ODT1 <10>

3

JCPU1D

AM6 AN2

AM4 AM3

AN5

AN6 AN4 AN3

AN7

AR10

AT10

AF3 AG1

AK1 AG4 AG3

AH4 AK3 AK4

AK5 AK2

AP3

AT4

AT5 AT6

AP6 AP8 AT9 AT7 AP9

AB1

AC5

AC6

JCPU1D

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2

J6

J3 G1 G5

J2

J1

J5 K2

L3 M1 K5 K4 M4 N5

AJ3

AJ4

W5

R7

Y7

DDR_B_D[0..63]<11> DDR_B_DM[0..7]<11>

DDR_B_DQS#[0..7]<11>

DDR_B_DQS[0..7]<11>

DDR_B_MA[0..15]<11>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0<11> DDR_B_BS1<11> DDR_B_BS2<11>

DDR_B_CAS#<11> DDR_B_RAS#<11> DDR_B_WE#<11>

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

1

DDR_B_CLK0 <11> DDR_B_CLK0# <11> DDR_B_CKE0 <11>

DDR_B_CLK1 <11> DDR_B_CLK1# <11> DDR_B_CKE1 <11>

DDR_B_CS0# <11> DDR_B_CS1# <11>

DDR_B_ODT0 <11> DDR_B_ODT1 <11>

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

IC,AUB_CFD_rPGA,R1P0

CONN@

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

PROCESSOR (3/6) DDRIII

NAU00 M/B LA-6101P Schematics

1

of

648Tuesday, March 09, 2010

1.0

5

JCPU1F

+CPU_CORE

WW15 MOW

48A Continuous 18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

D D

C C

B B

A A

AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26

VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

CPU VIDS

SENSE LINES

Peak 21A

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

4

10U_0805_6.3V6M

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

VTT_SELECT

G15

VTT_SELECT = Low, 1.1V VTT_SELECT = High, 1.05V

AN35

VCCSENSE_CPU

AJ34

VSSSENSE_CPU

AJ35

B15

VSS_SENSE_VTT

A15

Note:CRB has the VTT_ SENSE connected through a "no-stuff" 0- series resistor and VSS_SENSE_VTT floating.Connec t VSS_SENSE_VTT to GND or can be left floating.

10U_0805_6.3V6M

1

C2

2

10U_0805_6.3V6M

1

+

C18

2

330U_D2_2.5VY_R9M

22U_0805_6.3V6M

1

C28

C29

2

22U_0805_6.3V6M

IMVP_IMON <47 >

R83 0_0402_5%R83 0_0402_5%

1 2

R84 0_0402_5%R84 0_0402_5%

1 2

R86 0_0402_5%@R86 0_0402_5%@

10U_0805_6.3V6M

1

C4

C3

2

10U_0805_6.3V6M

+1.1VS_VTT

330U_D2_2.5VY_R9M

1

+

C19

C20

@

2

330U_D2E_2VM_R6M

+1.1VS_VTT

1

2

VTT_SENSE <45>

1 2

1

2

10U_0805_6.3V6M

1

+

2

PSI# <47>

H_VID0 <47> H_VID1 <47> H_VID2 <47> H_VID3 <47> H_VID4 <47> H_VID5 <47> H_VID6 <47> PROC_DPRSLPVR <47>

VTT_SELECT <45>

VTT Rail

Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V

3

+1.1VS_VTT

10U_0805_6.3V6M

1

C5

C6

2

1

C7

C8

2

10U_0805_6.3V6M

11/25 Change C18,C19,C20 from SGA00002380 (6mohm) to SGA00002680 (9mohm) 11/25 Change C19 from mount to @

+CPU_CORE

10U_0805_6.3V6M

1

C9

2

11/30 Change C20 from SGA00002680 (9mohm) to SGA00002U00 (6mohm)

11/09 Change R64,R66 from mount to @ (PWR Recommend)

11/09 Change R65 ,R67 from @ to mount (PWR Recommend)

CSC (Current Sense Configuration)

11/09 H_VID[6:0] => 0100100

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

PROC_DPRSLPVR

PSI#

11/17 Reserve C534,C535 for avoiding switching noise 11/17 Change C534,C535 from @ to mount

VTT_SELECT

VTT_SENSE

R64 1K_0402_1%@R64 1K_0402_1%@

1 2

R65 1K_0402_1%R65 1K_0402_1%

1 2

R66 1K_0402_1%@R66 1K_0402_1%@

1 2

R67 1K_0402_1%R67 1K_0402_1%

1 2

R68 1K_0402_1%R68 1K_0402_1%

1 2

R69 1K_0402_1%@R69 1K_0402_1%@

1 2

R70 1K_0402_1%@R70 1K_0402_1%@

1 2

R71 1K_0402_1%R71 1K_0402_1%

1 2

R72 1K_0402_1%@R72 1K_0402_1%@

1 2

R73 1K_0402_1%R73 1K_0402_1%

1 2

R74 1K_0402_1%R74 1K_0402_1%

1 2

R75 1K_0402_1%@R75 1K_0402_1%@

1 2

R76 1K_0402_1%@R76 1K_0402_1%@

1 2

R77 1K_0402_1%R77 1K_0402_1%

1 2

R78 1K_0402_1%R78 1K_0402_1%

1 2

R79 1K_0402_1%@R79 1K_0402_1%@

1 2

R80 1K_0402_1%@R80 1K_0402_1%@

1 2

R81 1K_0402_1%R81 1K_0402_1%

1 2

C534 100P_0402_50V8JC534 100P_0402_50V8J

1 2

C535 100P_0402_50V8JC535 100P_0402_50V8J

1 2

+1.1VS_VTT

Please place C534,C535 close to PU701

11/09 Change C42~C47 from SGA00002U00 to SGA00001Q80 (PWR Recommend)

11/11 Correct C42~C47 footprint

+CPU_CORE

1 2

R82 100_0402_1%R82 100_0402_1%

VCCSENSE VSSSENSE

1 2

R85 100_0402_1%R85 100_0402_1%

+CPU_CORE

VCCSENSE <47> VSSSENSE <47>

C42

330U_X_2VM_R6M

11/25 Change R86 from mount to @ (Follow NIWE2)

2

10U_0805_6.3V6M

1

C10

2

10U_0805_6.3V6M

(Place these capacitors between inductor and socket on Bottom)

+CPU_CORE

10U_0805_6.3V6M

4 x 330uF(6m ohm@100kHz)

1

+

2

C44

330U_X_2VM_R6M

TOP side (under inductor)

10U_0805_6.3V6M

C11

10U_0805_6.3V6M

C21

1

2

1

2

1

2

1

2

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

22U_0805_6.3V6M

1

C34

2

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE

22U_0805_6.3V6M

1

C36

2

22U_0805_6.3V6M

1

C12

2

1

C22

2

10U_0805_6.3V6M

1

C30

2

22U_0805_6.3V6M

1

C37

2

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)

C13

10U_0805_6.3V6M

C23

1

C35

2

1

C38

2

1

2

1

2

SGA00001Q80

1

+

@

330U_X_2VM_R6M

2

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

1

+

C45

330U_X_2VM_R6M

2

C,uF

4X330uF 6m ohm/4

16X22uF

16X10uF 3m ohm/16

+

C46

ESR, mohm

3m ohm/12

10U_0805_6.3V6M

C14

C24

10U_0805_6.3V6M

22U_0805_6.3V6M

1

C31

2

22U_0805_6.3V6M

1

C39

2

1

330U_X_2VM_R6M

2

1

C15

2

10U_0805_6.3V6M

1

C25

2

1

C32

2

22U_0805_6.3V6M

1

C40

2

22U_0805_6.3V6M

1

+

C47

2

Stuffing Option

2X330uF

10U_0805_6.3V6M

1

C16

2

1

C26

2

10U_0805_6.3V6M

22U_0805_6.3V6M

1

C33

2

22U_0805_6.3V6M

1

C41

2

C43

330U_X_2VM_R6M

1

C17

2

1

C27

2

1

+

@

2

Security Classification

IC,AUB_CFD _rPGA,R1P0

CONN@

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR (4/6) PWR,Bypass

NAU00 M/B LA-6101P Schematics

748Tuesday, March 09, 2010

of

1

of

1.0

5

4

3

2

1

+GFX_CORE

22U_0805_6.3V6M

1

C53

C48

@

22U_0805_6.3V6M

1

+

C52

2

@

2

D D

330U_D2_2.5VY_R9M

22U_0805_6.3V6M

1

C54

C49

@

2

22U_0805_6.3V6M

1

+

C57

@

330U_D2_2.5VY_R9M

2

22U_0805_6.3V6M

1

C55

C50

2

22U_0805_6.3V6M

10U_0805_6.3V6M

1

C56

C51

2

10U_0805_6.3V6M

1

2

11/25 Change C52,C57 from SGA00002380 (6mohm) to SGA00002680 (9mohm)

C C

+1.1VS_VTT

1

2

1

2

1

C67

22U_0805_6.3V6M

2

1

C70

22U_0805_6.3V6M

2

C66

22U_0805_6.3V6M

+1.1VS_VTT

C69

22U_0805_6.3V6M

B B

22U_0805_6.3V6M

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R1P0

CONN@

15A

GRAPHICS

FDI PEG & DMI

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6

3A

POWER

0.6A

VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

DDR3 - 1.5V RAILS

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65

1.1V1.8V

VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

GFXVR_EN

AR25

GFXVR_DPRSLPVR_R

AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

1U_0402_6.3V4Z

C58

1U_0402_6.3V4Z

+1.1VS_VTT

1

2

+1.8VS_VCCSFR

C72

VCC_AXG_SENSE <46> VSS_AXG_SENSE <46>

11/23 Change R610 from SD028470180(4.7kohm) to SD028470080(470ohm) (Follow Intel Recommend)

GFXVR_VID_0 <46> GFXVR_VID_1 <46> GFXVR_VID_2 <46> GFXVR_VID_3 <46> GFXVR_VID_4 <46> GFXVR_VID_5 <46> GFXVR_VID_6 <46>

R87 0_0402_5%R87 0_0402_5%

1 2

1U_0402_6.3V4Z

1

C59

2

+1.1VS_VTT

C71

22U_0805_6.3V6M

1

C73

2

1U_0402_6.3V4Z

1

C60

C61

2

1U_0402_6.3V4Z

1

C68

10U_0805_6.3V6M

2

2.2U_0603_6.3V6K

1

C75

C74

2

4.7U_0603_6.3V6K

10/22 Reserve R609,R610 for GFXVR_EN,GFXVR_DPRSLPVR_R

11/02 Change R610 from @ to mount (Follow NIWE2)

1

C62

2

1U_0402_6.3V4Z

1

2

GFXVR_EN GFXVR_DPRSLPVR_R

GFXVR_EN <46>

PAD

T16

GFXVR_IMON <46>

22U_0805_6.3V6M

1

C63

C64

2

22U_0805_6.3V6M

1 2

1

C76

2

22U_0805_6.3V6M

R610 470_0402_5%R610 470_0402_5%

1 2

R609 10K_0402_5%@R609 10K_0402_5%@

1 2

@

1

+

C65

C65 330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

12/22 Change C65 from SGA20331E10 to SGA00002680

R88

R88 0_0805_5%

0_0805_5%

+1.8VS

+1.5V_1

A A

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR (5/6) PWR

NAU00 M/B LA-6101P Schematics

1

of

848Tuesday, March 09, 2010

1.0

5

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

VSS8

AR17

VSS9

AR15

VSS10

D D

C C

B B

AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2

AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8

AF4

AF2 AE35

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

K27

H35 H32 H28 H26 H24 H22 H18 H15 H13 H11

G34 G31 G20

F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11

D33 D30 D26

C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11

A29 A27 A23

4

JCPU1I

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178

H8

VSS179

H5

VSS180

H2

VSS181 VSS182 VSS183 VSS184

G9

VSS185

G6

VSS186

G3

VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201

E8

VSS202

E5

VSS203

E2

VSS204 VSS205 VSS206 VSS207

D9

VSS208

D6

VSS209

D3

VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226

B8

VSS227

B6

VSS228

B4

VSS229 VSS230 VSS231 VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

11/17 Delete T2,T3,T4,T5

AT35 AT1 AR34 B34 B2 B1 A35

3

Screw cap.

2

Please place C520~C529 close to H1,H10,H2,H20,H3,H4,H6,H7,H8,H9

12/15 Change C520(@),C528(@) from SE070104Z80 to SE042104K80

C524

@

0.1U_0402_16V4Z

1

C522

@

0.1U_0402_16V4Z

2

+3VS

1

2

11/10 Add C520~C529(@) (ESD Recommend)

11/13 Change C522 power from +3VS to +3VALW

11/17 Delete C521(@),C523(@)

+3VS

1

C525

@

0.1U_0402_16V4Z

2

1

C526

@

0.1U_0402_16V4Z

2

1

C527

@

0.1U_0402_16V4Z

2

12/15 Add C536~C540 (EMI Recommend)

12/15 Change C539,C540 from SE070104Z80 to SE042104K80

1

C536

0.1U_0402_16V4Z

2

+5VS

12/15 Add C541~C543 (EMI Recommend)

1

C541

0.1U_0402_16V4Z

2

1

C537

0.1U_0402_16V4Z

2

1

C542

0.1U_0402_16V4Z

2

1

C538

0.1U_0402_16V4Z

2

1

C543

0.1U_0402_16V4Z

2

1

11/17 Change the power of C520,C528 from +3VS to B+

B++3VALW

1

C520

@

0.1U_0603_25V7K

2

1

C529

@

0.1U_0402_16V4Z

2

B++3VS

1

C539

0.1U_0603_25V7K

2

1

C528

@

0.1U_0603_25V7K

2

1

C540

0.1U_0603_25V7K

2

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

5

IC,AUB_CFD_rPGA,R1P0

CONN@

4

1

C550

0.1U_0402_16V4Z

2

01/15 Add C544~C549 (EMI Recommend) 01/16 Add C550 (EMI Recommend)

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

1

C544

0.1U_0402_16V4Z

2

1

C545

0.1U_0603_25V7K

2

B++R_CRT_VCC B+ +5VS +USB_VCCA+3VS

1

C546

0.1U_0603_25V7K

2

Title

Size Document Number Rev

Custom

Date: Sheet

1

C547

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

PROCESSOR (6/6) VSS

NAU00 M/B LA-6101P Schematics

1

C548

0.1U_0402_16V4Z

2

1

C549

0.1U_0402_16V4Z

2

of

948Friday, February 26, 2010

1.0

5

M1 Circuit

+1.5V

12

R91

1K_0402_1%

12

D D

+V_DDR3_DIMM_REF

R89

1K_0402_1%

2009/04/13 For Arrandale ,it should be use M1 Circuit For Clarksfield ,it should be use M3 Circuit DG V1.52

DDR_A_DQS#[0..7]<6>

DDR_A_D[0..63]<6>

DDR_A_DM[0..7]<6>

DDR_A_DQS[0..7]<6>

DDR_A_MA[0..15]<6>

SM_DRAMRST#<5>

11/05 Change R94 from @ to mount (Follow NIWE2)

C C

Layout Note: Place near JDIMM1

Layout Note: Place these 4 Caps near Command

B B

+1.5V

10U_0805_6.3V6M

1

C82

C81

2

10U_0805_6.3V6M

Layout Note: Place near JDIMM1.203 & JDIMM1.204

+0.75VS

1U_0603_10V4Z

A A

1U_0603_10V4Z

2

C94

1

1U_0603_10V4Z

and Control signals of DIMMA

10U_0805_6.3V6M

1

C83

2

10U_0805_6.3V6M

2

C95

1

1U_0603_10V4Z

C84

2

1U_0603_10V4Z

2

C96

1

5

1

C85

2

10U_0805_6.3V6M

1

C97

2

10U_0805_6.3V6M

1

C86

2

C98

10U_0805_6.3V6M

1

2

0.1U_0402_16V4Z

1

C87

2

1

C88

2

0.1U_0402_16V4Z

1

C89

2

4

12

R94

100K_0402_1%

1

C90

2

4

3

M1 Circuit

R90 0_0402_5%R90 0_0402_5%

+V_DDR3_DIMM_REF

R92 0_0402_5%@R92 0_0402_5%@

1 2

SGD

3 1

Q9 BSH111_SOT23-3

2

RST_GATE<18>

10/22 Add C502 at RST_GATE (Intel 425302_Calpella_S3PowerReduction_WhitePaper_Rev1.0) 11/09 Change C502 from 0.047uF to 0.1uF

11/23 Change R92 from mount to @ Change Q9 from @ to mount

1

+

C91

@

220U_D2_4VM

2

RST_GATE

1

C502

0.1U_0402_16V4Z

2

1 2

+1.5V

0.1U_0402_16V4Z

12

R93

1K_0402_1%

DIMM_DRAMRST#

10/21 Change R93 from @ to mount

11/25 Change C91(@) from SGA20331E10 to SGA00000Y80

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VREF_DQA

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2

1

C77

2.2U_0603_6.3V4Z

1

C78

2.2U_0603_6.3V4Z

2

11/10 Change C78 from SE103225Z80 to SE049225Z80

DDR_A_CKE0<6>

DDR_A_BS2<6>

DDR_A_CLK0<6> DDR_A_CLK0#<6>

DDR_A_BS0<6>

DDR_A_WE#<6> DDR_A_CAS#<6>

DDR_A_CS1#<6>

+3VS

1

C92

2

2009/10/10 2010/08/25

DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_CKE0

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK0#

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDR_A_CS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R96 10K_0402_5%R96 10K_0402_5%

1 2

1

C93

0.1U_0402_16V4Z

2

Compal Secret Data

12

R97

10K_0402_5%

Deciphered Date

+1.5V

2

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F CONN@

CONN@

Copy NTUC0

2

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

1

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28

DIMM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDR_A_CKE1

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_CLK1 DDR_A_CLK1#

DDR_A_BS1 DDR_A_RAS#

DDR_A_CS0# DDR_A_ODT0

DDR_A_ODT1

DDR_VREF_CA_DIMMA

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK

DIMM_DRAMRST# <11>

DDR_A_CKE1 <6>

DDR_A_CLK1 <6> DDR_A_CLK1# <6>

DDR_A_BS1 <6> DDR_A_RAS# <6>

DDR_A_CS0# <6> DDR_A_ODT0 <6>

DDR_A_ODT1 <6>

1 2

R95 0_0402_5%R95 0_0402_5%

C79

2.2U_0603_6.3V4Z

PM_EXTTS#0_1 <5,11>

D_CK_SDATA <11,12>

+0.75VS

D_CK_SCLK <11,12>

DDR3 SO-DIMM A Standard Type H = 4.0mm

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

NAU00 M/B LA-6101P Schematics

1

+V_DDR3_DIMM_REF

1

2

10 48Tuesday, March 09, 2010

1

C80

0.1U_0402_16V4Z

2

of

1.0

5

4

3

2

1

+1.5V

DDR_B_DQS#[0..7]<6>

DDR_B_D[0..63]<6>

DDR_B_DM[0..7]<6>

DDR_B_DQS[0..7]<6>

D D

DDR_B_MA[0..15]<6>

M1 Circuit

R98 0_0402_5%R98 0_0402_5%

+V_DDR3_DIMM_REF_B

2009/04/13 For Arrandale ,it should be use M1 Circuit For Clarksfield ,it should be use M3 Circuit DG V1.52

11/10 Change C99 from SE103225Z80 to SE049225Z80

R606

1K_0402_1%

1

C110

2

0.1U_0402_16V4Z

+1.5V

12

+V_DDR3_DIMM_REF_B

12

R607

1K_0402_1%

0.1U_0402_16V4Z

1

C111

2

+V_DDR3_DIMM_REF_B

1

+

C113

C112

0.1U_0402_16V4Z

C113

220U_D2_4VM

2

11/25 Change C113 from SGA20331E10 to SGA00000Y80

C C

Layout Note: Place near JDIMM2

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

+1.5V

10U_0805_6.3V6M

1

B B

A A

C103

10U_0805_6.3V6M

1U_0603_10V4Z

1

C104

2

10U_0805_6.3V6M

Layout Note: Place near JDIMM2.203 & JDIMM2.204

+0.75VS

C114

2

C116

C115

2

1

1U_0603_10V4Z

C105

1U_0603_10V4Z

1

C106

2

10U_0805_6.3V6M

C117

2

1

1U_0603_10V4Z

10U_0805_6.3V6M

1

C107

2

C118

2

1

10U_0805_6.3V6M

1

2

0.1U_0402_16V4Z

1

C108

2

10U_0805_6.3V6M

C109

1 2

2.2U_0603_6.3V4Z

+3VS

2.2U_0603_6.3V4Z

1

C99

2

C119

1

C100

2

0.1U_0402_16V4Z

DDR_B_CKE0<6>

DDR_B_BS2<6>

DDR_B_CLK0<6> DDR_B_CLK0#<6>

DDR_B_BS0<6>

DDR_B_WE#<6> DDR_B_CAS#<6>

DDR_B_CS1#<6>

1

2

C120

0.1U_0402_16V4Z

VREF_DQB

DDR_B_D0 DDR_B_D1

DDR_B_DM0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_B_CKE0

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK0#

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_B_CS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

R100 10K_0402_5%R100 10K_0402_5%

1 2

R101 10K_0402_5%R101 10K_0402_5%

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F CONN@

CONN@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

Copy NTUC0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/08/25

Compal Secret Data

Deciphered Date

DM1

DM2

DM4

DM6

SDA

DQ4 DQ5

DQ6 DQ7

CK1

BA1

NC2

SCL

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

DIMM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_B_CKE1

74 76

DDR_B_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_B_BS1 DDR_B_RAS#

DDR_B_CS0# DDR_B_ODT0

DDR_B_ODT1

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK

DIMM_DRAMRST# <10>

DDR_B_CKE1 <6>

DDR_B_CLK1 <6> DDR_B_CLK1# <6>

DDR_B_BS1 <6> DDR_B_RAS# <6>

DDR_B_CS0# <6> DDR_B_ODT0 <6>

DDR_B_ODT1 <6>

R99 0_0402_5%R99 0_0402_5%

PM_EXTTS#0_1 <5,10>

+0.75VS

1 2

C101

2.2U_0603_6.3V4Z

D_CK_SDATA <10,12> D_CK_SCLK <10,12>

+V_DDR3_DIMM_REF_B

1

C102

0.1U_0402_16V4Z

2

DDR3 SO-DIMM B Standard Type

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

NAU00 M/B LA-6101P Schematics

1

of

11 48Tuesday, March 09, 2010

of

11 48Tuesday, March 09, 2010

of

11 48Tuesday, March 09, 2010

1.0

A

B

C

D

E

F

G

H

Layout note:

Place C122 close to L2 Place C123 close to U2.15 Place C124 close to U2.18

1 1

+1.1VS_VTT

L2 0_0603_5% L2 0_0603_5%

1 2

11/06 Change +1.05VS to +1.1VS_VTT

11/03 Delete C121(@)

+CLK_VDDSRC

C122

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

C124

C123

2

11/03 Change L2 from SM01000AX00 to 0ohm (Follow NIWE2)

2 2

11/03 Delete RP1,RP2,RP3,RP4

CLK_BUF_DREF_96M<14> CLK_BUF_DREF_96M#<14>

CLK_BUF_DREF_96M CLK_BUF_DREF_96M#

10/21 Change R542 from 0ohm to 33ohm (Vendor Recommend)

CLK_48M<28>

CLK_BUF_PCIE_SATA<14> CLK_BUF_PCIE_SATA#<14>

CLK_BUF_CPU_DMI<14> CLK_BUF_CPU_DMI#<14>

3 3

11/04 Reserve C510(@) for CLK_48M (RF Recommend)

C510 15P_0402_50V8J@C510 15P_0402_50V8J@

1 2

CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA#

CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI#

10/23 Change R107 from mount to @

11/03 Change R107 from @ to mount

+3VS

R107 10K_0402_5%R107 10K_0402_5%

1 2

IDT& Realtek Have Internal Pull-Down

R109 10K_0402_5%R109 10K_0402_5%

1 2

4 4

PIN 30

0

(Default)

1

A

CPU_0

133MHz

100MHz

H_STP_CPU#

REF_0/CPU_SEL

CPU_1

133MHz

100MHz

B

Layout note: Layout note:

Place C130 close to L1 Place C131 close to U2.5 Place C132 close to U2.29

L1 0_0603_5% L1 0_0603_5%

+3VS

1 2

11/03 Delete C129(@)

+CLK_VDD

0.1U_0402_16V4Z

1

C130

2

10U_0805_10V4Z

1

C131

2

0.1U_0402_16V4Z

11/03 Change L1 from SM01000AX00 to 0ohm (Follow NIWE2)

10/23 Change U2 Pin1,17,24 Net Name to +VDD_3V3_1V5

+CLK_VDDSRC

R542 33_0402_5%R542 33_0402_5%

1 2

SSM3K7002FU_SC70-3

PCH_SMBDATA<14,32,37>

9/10 Change symbol of Q31/Q32 to SC70-3

PCH_SMBCLK<14,32,37>

SSM3K7002FU_SC70-3

C

+VDD_3V3_1V5

+CLK_VDD

48M

H_STP_CPU#

Q11

Q12

+3VS

2

1 3

D

+3VS

2

1 3

D

G

Clock Generator

U2

1

VDD_USB_48

2

VSS_48M

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

USB_48

9

VSS_27M

10

SATA

11

SATA#

12

VSS_SRC

13

SRC_1

14

SRC_1#

15

VDD_SRC_IO

16

CPU_STOP#

33

TGND

SLG8SP587VTR_QFN32_5X5

SA00003HR00 11/03 Change U2 from SA00003MF 00 to SA00002XY00 11/23 Change U2 from SA00002XY00 to SA00003HR00

R108

4.7K_0402_5%

1 2

D_CK_SDATA

S

R110

4.7K_0402_5%

1 2

D_CK_SCLK

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

+3VS

1

C132

2

Type

Standard

Low Power

SSM3K7002FU_SC70-3

2009/10/10 2010/10/10

Layout note: Place C507 close to R103

+1.5VS

11/03 Delete L3,C126,C125(@)

10/23 Delete C127, C128, C501 on +CLK_1.5VDD

R102 R103

Mount@@

Mount

+CLK_VDD

32

SCL

31

SDA

REF_0/CPU_SEL

XTAL_OUT

CKPWRGD/PD#

VDD_CPU_IO

+3VS

D

Q10

S

30 29

VDD_REF

28

XTAL_IN

27 26

VSS_REF

25

24

VDD_CPU

23

CPU_0

22

CPU_0#

21

VSS_CPU

20

CPU_1

19

CPU_1#

18 17

VDD_SRC

Realtek Have Internal Pull-Down

R105

R105 10K_0402_5%

10K_0402_5%

1 2

CK505_PWRGD

13

2

G

9/10 Change symbol o f Q29 to SC70-3

Compal Secret Data

Deciphered Date

E

R103 0_0402_5%R103 0_0402_5%

1 2

+CLK_VDDSRC

D_CK_SCLK D_CK_SDATA REF_0/CPU_SEL

CLK_XTAL_IN CLK_XTAL_OUT

CK505_PWRGD

+VDD_3V3_1V5

R106

R106 0_0402_5%

0_0402_5%

@

1 2

CLK_EN# <47>

+CLK_VDD

12

R102

@

0_0402_5%

10U_0805_10V4Z

10/23 Add C1000 on +VDD_3V3_1V5 Change C133, C134, C135 from +CLK_VDD to +VDD_3V3_1V5 11/03 Change C507 from @ to mount

R104 33_0402_5%R104 33_0402_5%

1 2

VGATE <15,47>

F

14.318MHZ_16PF_7A14300083

Place C133 close to U2.1 Place C134 close to U2.17 Place C135 close to U2.24

+VDD_3V3_1V5

1

C507

2

0.1U_0402_16V4Z

CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK#

CLK_XTAL_IN

CLK_XTAL_OUT

1

C133

2

1

C509

10P_0402_50V8J

2

1

C134

2

0.1U_0402_16V4Z

22P_0402_50V8J

Y1

22P_0402_50V8J

1 2

C135

0.1U_0402_16V4Z

D_CK_SCLK <10,11> D_CK_SDATA <10,11> CLK_BUF_ICH_14M <14>

11/04 Reserve C509(@) for CLK_BUF_ICH_14M (RF Recommend)

01/15 Add C509 (10pF)

CLK_BUF_CPU_BCLK <14> CLK_BUF_CPU_BCLK# <14>

C136

9/23 Change C495 to 22pF

12

C137

12

update PCB footprint

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Clock Generator (CK505)

NAU00 M/B LA-6101P Schematics

G

1.0

of

12 48Tuesday, March 09, 2010

H

5

+RTCVCC

1 2

R111

R111 20K_0402_1%

20K_0402_1%

PCH_RTCRST#

RC Delay 18~25mS

18P_0402_50V8J

close to RAM door

1 2

J1

@J1

@

10K_0603_5%

C139

1U_0603_10V6K

D D

+RTCVCC

close to RAM door

HDA for AUDIO

C508 15P_0402_50V8J@C508 15P_0402_50V8J@

HDA_BITCLK_AUDIO<29>

HDA_SYNC_AUDIO<29>

HDA_RST#_AUDIO<29>

C C

HDA_SDOUT_AUDIO<29>

If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door.

1 2

R115

R115 20K_0402_1%

20K_0402_1%

1 2

J2

@J2

@

10K_0603_5%

C141

1U_0603_10V6K

1 2

11/04 Reserve C508(@) for BITCLK (RF Recommend)

1 2

R116 33_0402_5%R116 33_0402_5%

R117 33_0402_5%R117 33_0402_5%

R118 33_0402_5%R118 33_0402_5%

R119 33_0402_5%R119 33_0402_5%

32.768KHZ_12.5PF_Q13MC14610002

PCH_SRTCRST#

RC Delay 18~25mS

INTVRMEN - Integrated SUS 1.1V VRM Enable High - Enable Interna l VRs

1 2

HDA_BITCLK_PCH

HDA_SYNC_PCH

HDA_RST#_PCH

HDA_SDOUT_PCH

10/5 Change R223 to 330K ohm

ME_EN#<33>

11/10 Delete Q13,R120,R121 (Follow NIWE2)

GPIO33 can not pull down (manufacturing environments)

+3VS

R126

R126 10K_0402_5%

10K_0402_5%

@

B B

1 2

R127

R127 10K_0402_5%

10K_0402_5%

PCH Pin RefDes

R138

PCH_JTAG_TDO No Install

R139

R135

PCH_JTAG_TMS No Install

A A

PCH_JTAG_TDI

PCH_JTAG_TCK

R136

R143 No Install

R144

R150

R146

PCH_JTAG_RST#

R147

10/5 Change R287 to 10K ohm

PCH_SPKR

Have internal PD

SERIRQ PCH_GPIO21

PCH JTAG Pre-Production

ES2 MPES1

No Install

200ohm

100ohm

200ohm

100ohm100ohm

200ohm

100ohm100ohm

51ohm

20Kohm

10Kohm

5

51ohm 51ohm

20Kohm

10Kohm

PCH_SPI_CLK_1

PCH_SPI_CS0#

PCH_SPI_MISO_1 PCH_SPI_MISO

PCH JTAG Production

*

No Install

3

2

18P_0402_50V8J

+RTCVCC

R113 1M_0402_5%R113 1M_0402_5%

R114 330K_0402_5%R114 330K_0402_5%

R604 1K_0402_5%@R604 1K_0402_5%@

R603 10K_0402_5%@R603 10K_0402_5%@

+3VALW

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_RST#

11/05 Change R135,R136,R138,R139,R 143,R144,R146,R147 from mount to @ (Follow NIWE2) 11/10 Delete R134(@),R137(@),R142(@),R145(@)

4

C138

12

X1

OSC

NC

OSC

NC

C140

12

1 2

HDA_SDIN0<29>

1 2

R123 0_0402_5%R123 0_0402_5%

1 2

R124 15_0402_5%R124 15_0402_5%

1 2

PCH_RTCX1

4

1

10M_0402_5%

PCH_RTCX2

PCH_SPKR<29>

9/3 Remove R738

R128 15_0402_5%R128 15_0402_5%

1 2

R130 0_0402_5%R130 0_0402_5%

1 2

10/5 Change R734 to 0 ohm

R135 200_0402_5%@R135 200_0402_5%@

1 2

R136 100_0402_5%@R136 100_0402_5%@

1 2

R138 200_0402_5%@R138 200_0402_5%@

1 2

R139 100_0402_5%@R139 100_0402_5%@

1 2

R143 200_0402_5%@R143 200_0402_5%@

1 2

R144 100_0402_5%@R144 100_0402_5%@

1 2

R146 20K_0402_5%@R146 20K_0402_5%@

1 2

R147 10K_0402_5%@R147 10K_0402_5%@

1 2

4

12

R112

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK_PCH

HDA_SYNC_PCH

PCH_SPKR

HDA_RST#_PCH

HDA_SDOUT_PCH

ME_EN#

PCH_GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_RST#

PCH_SPI_CLK

PCH_SPI_CS0#_R

PCH_SPI_MOSIPCH_SPI_MOSI_1

3

12/17 Change U3 from SA00003N7B0 to SA00003N7A0

11/30 Change U3 from SA00003N720 to SA00003N7B0

PCH : SA00003N7A0

REV1.0

LPC

RTCIHDA

SATA

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI JTAG

11/06 Change +1.05VS to +1.1VS_VTT

+3VALW

B13 D13

C14

D17

A16

A14

A30

D29

C30

G30

E32

B29

H32

BA2

AV3

AY3

AY1

AV1

P1

F30

F32

J30

M3

K3

K1

J2

J4

U3A

RTCX1 RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO1 3

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TRST#

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

IBEXPEAK-M_FCBGA107

11/09 Delete R148(@) (Follow NIWE2)

PCH_SPI_MOSI

enable iTPM: SPI_MOSI High

PCH_JTAG_TCK

LPC_AD0

LDRQ0#

SERIRQ

D33

LPC_AD1

B33

LPC_AD2

C32

LPC_AD3

A32

LPC_FRAME#

C34

A34 F34

SERIRQ

AB9

SATA_DTX_C_PRX_N0

AK7

SATA_DTX_C_PRX_P0

AK6

SATA_PTX_DRX_N0

AK11

SATA_PTX_DRX_P0

AK9

SATA_DTX_C_PRX_N1

AH6

SATA_DTX_C_PRX_P1

AH5

SATA_PTX_DRX_N1

AH9

SATA_PTX_DRX_P1

AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

SATA_DTX_C_PRX_N4

AD9

SATA_DTX_C_PRX_P4

AD8

SATA_PTX_DRX_N4

AD6

SATA_PTX_DRX_P4

AD5

SATA_DTX_C_PRX_N5

AD3

SATA_DTX_C_PRX_P5

AD1

SATA_PTX_DRX_N5

AB3

SATA_PTX_DRX_P5

AB1

AF16

AF15

T3

Y9

PCH_GPIO19

V1

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA0RXN

SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA1RXP SATA1TXN SATA1TXP

SATA2RXN

SATA2RXP SATA2TXN SATA2TXP

SATA3RXN

SATA3RXP SATA3TXN SATA3TXP

SATA4RXN

SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

R149 1K_0402_5%@R149 1K_0402_5%@

1 2

R150 51_0402_5%R150 51_0402_5%

1 2

2/10 SATA2, SATA3 not support on HM55

SATA_COMP

PCH_SATALED#_R

R122 37.4_0402_1%R122 37.4_0402_1%

R125 10K_0402_5%R125 10K_0402_5%

+3VS

2

LPC_AD0 <33> LPC_AD1 <33> LPC_AD2 <33> LPC_AD3 <33>

LPC_FRAME# <33>

SERIRQ <33>

SATA_DTX_C_PRX_N0 <25> SATA_DTX_C_PRX_P0 <25>

SATA_PTX_DRX_N0 <25> SATA_PTX_DRX_P0 <25>

SATA_DTX_C_PRX_N1 <32> SATA_DTX_C_PRX_P1 <32>

SATA_PTX_DRX_N1 <32> SATA_PTX_DRX_P1 <32>

SATA_DTX_C_PRX_N4 <31> SATA_DTX_C_PRX_P4 <31>

SATA_PTX_DRX_N4 <31> SATA_PTX_DRX_P4 <31>

SATA_DTX_C_PRX_N5 <32> SATA_DTX_C_PRX_P5 <32>

SATA_PTX_DRX_N5 <32> SATA_PTX_DRX_P5 <32>

1 2

10K_0402_5%

11/23 Change R129,R131 from @ to mount Change R132,R133 from mount to @ (Follow NIWE2)

R140 3.3K_0402_5%R140 3.3K_0402_5%

1 2

R141 3.3K_0402_5%R141 3.3K_0402_5%

1 2

11/05 Change R150 from 4.7kohm to 51ohm (Follow NIWE2)

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

2

PCH_SATALED#_R

01/21 Add U34,R652(@)

+1.1VS_VTT

11/06 Change +1.05VS to +1.1VS_VTT

+3VS

R129 10K_0402_5%R129 10K_0402_5%

R131 10K_0402_5%R131 10K_0402_5%

12

R132

@

12

R133

@

10K_0402_5%

PCH_SPI_CS0# SPI_WP1# SPI_HOLD1#

Title

Size Document Number Rev

Custom

Date: Sheet

1

R652 0_0402_5%@R652 0_0402_5%@

1 2

+3VS

5

2

P

B

4

Y

1

A

G

U34

3

NC7SZ08P5X_NL_SC70-5

SATA for HDD

SATA for SSD

SATA for eSATA

SATA for SSD

+3VS

1 2

U4

1

CS#

3

WP#

7

HOLD#

4

GND

S IC FL 32M MX25L3205DM2I-12G SOP 8P

VCC

SCLK

8 6 5

SI

2

SO

SPI ROM Footprint 150mil

Compal Electronics, Inc.

PCH (1/9) SATA,HDA,SPI, LPC

NAU00 M/B LA-6101P Schematics

13 48Tuesday, March 09, 2010

1

PCH_SATALED# <36>

+3VS

PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1

of

1.0

5

PCIE_DTX_C_PRX_N1<26>

For PCIE LAN

For Wireless LAN

D D

For New Card

PCIE_DTX_C_PRX_P1<26>

PCIE_PTX_C_DRX_N1<26> PCIE_PTX_C_DRX_P1<26>

PCIE_DTX_C_PRX_N2<32> PCIE_DTX_C_PRX_P2<32>

PCIE_PTX_C_DRX_N2<32> PCIE_PTX_C_DRX_P2<32>

PCIE_DTX_C_PRX_N3<37> PCIE_DTX_C_PRX_P3<37>

PCIE_PTX_C_DRX_N3<37> PCIE_PTX_C_DRX_P3<37>

C142 .1U_0402_16V7KC142 .1U_0402_16V7K C143 .1U_0402_16V7KC143 .1U_0402_16V7K

12 12

C144 .1U_0402_16V7KC144 .1U_0402_16V7K

12

C145 .1U_0402_16V7KC145 .1U_0402_16V7K

12

C146 .1U_0402_16V7KC146 .1U_0402_16V7K

12

C147 .1U_0402_16V7KC147 .1U_0402_16V7K

12

2/10 PCIE7, PCIE8 not support on HM55

C C

R151 0_0402_5%R151 0_0402_5%

For PCIE LAN

CLK_PCIE_LAN#<26> CLK_PCIE_LAN<26>

11/05 Delete R153

1 2 1 2

1 2

5

CLK_PCIE_MINI1#<32> CLK_PCIE_MINI1<32>

CLK_PCIE_EXP#<37> CLK_PCIE_EXP<37>

+3VS

+3VALW

For Wireless LAN

For New Card

B B

MINI1_CLKREQ# EXP_CLKREQ#

A A

9/14 Change to +3VALW(Follow CRB1.1)

PCH_GPIO25

R168 10K_0402_5%R168 10K_0402_5% R169 10K_0402_5%R169 10K_0402_5%

R177 10K_0402_5%R177 10K_0402_5%

1 2

R152 0_0402_5%R152 0_0402_5%

1 2

LAN_CLKREQ#<26>

R154 0_0402_5%R154 0_0402_5%

1 2

R155 0_0402_5%R155 0_0402_5%

1 2

MINI1_CLKREQ#<32>

R156 0_0402_5%R156 0_0402_5%

1 2

R157 0_0402_5%R157 0_0402_5%

1 2

EXP_CLKREQ#<37>

9/14 Change power net from +3V to +3VALW

EC_LID_OUT# PCH_SMBCLK PCH_SMBDATA

PCH_GPIO60

PCH_SML1CLK PCH_SML1DAT

PCH_GPIO74

PCH_GPIO26 PCH_GPIO44 PCH_GPIO56 LAN_CLKREQ#

4

PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1

PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_DTX_C_PRX_N2 PCIE_DTX_C_PRX_P2

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_DTX_C_PRX_N3 PCIE_DTX_C_PRX_P3

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

LAN_CLKREQ#

CLK_PCIE_MINI1#_R CLK_PCIE_MINI1_R

MINI1_CLKREQ#

CLK_PCIE_EXP#_R CLK_PCIE_EXP_R

EXP_CLKREQ#

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

R170 10K_0402_5%R170 10K_0402_5%

1 2

R171 2.2K_0402_5%R171 2.2K_0402_5%

1 2

R172 2.2K_0402_5%R172 2.2K_0402_5%

1 2

R173 10K_0402_5%R173 10K_0402_5%

1 2

R174 2.2K_0402_5%R174 2.2K_0402_5%

1 2

R175 2.2K_0402_5%R175 2.2K_0402_5%

1 2

R176 10K_0402_5%R176 10K_0402_5%

1 2

R178 10K_0402_5%R178 10K_0402_5%

1 2

R179 10K_0402_5%R179 10K_0402_5%

1 2

R180 10K_0402_5%R180 10K_0402_5%

1 2

R181 10K_0402_5%R181 10K_0402_5%

1 2

4

3

U3B

BG30

BJ30 BF29

BH29

AW30

BA30 BC30 BD30

AU30

AT30 AU32 AV32

BA32 BB32 BD32 BE32

BF33 BH33 BG32

BJ32

BA34

AW34

BC34 BD34

AT34 AU34 AU36 AV36

BG34

BJ34 BG36

BJ36

AK48 AK47

P9

AM43 AM45

U4

AM47 AM48

N4

AH42 AH41

A8

AM51 AM53

M9

AJ50

AJ52

H6

AK53 AK51

P13

IBEXPEAK-M_FCBGA107

+3VALW

REV1.0

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_ N

CLKOUT_DP_P / CLKOUT_BCLK1_ P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N

CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

EC_LID_OUT#

B9

PCH_SMBCLK

H14

PCH_SMBDATA

C8

PCH_GPIO60

J14

PCH_SML0CLK

C6

PCH_SML0DAT

G8

PCH_GPIO74

M14

E10

G12

T13

T11

T9

PCH_SML1CLK

PCH_SML1DAT

R625 0_0402_5%R625 0_0402_5%

R626 0_0402_5%R626 0_0402_5%

11/05 Add R625,R626, delete Q14,Q15 (Follow NIWE2)

11/02 Change R597 to pull-up resister to +3VALW on PCH_GPIO47

PCH_GPIO47

H1

AD43 AD45

AN4 AN2

AT1 AT3

10/30 Delete Net : CLK_CPU_DP,CLK_CPU_DP#

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

XCLK_RCOMP

AF38

Project Port ID

PROJECT_ID2

T45

PROJECT_ID1

P43

PROJECT_ID0

T42

PROJECT_ID3

N50

R597 10K_0402_5%R597 10K_0402_5%

R158 90.9_0402_1%R158 90.9_0402_1%

9/14 Add R374/R239/R375/R376(Pro ject ID use)

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

2

EC_LID_OUT# <33>

PCH_SMBCLK <12,32,37>

PCH_SMBDATA <12,32,37>

1 2

CLK_CPU_DMI# <5> CLK_CPU_DMI <5>

CLK_BUF_CPU_DMI# <12> CLK_BUF_CPU_DMI <12>

CLK_BUF_CPU_BCLK# <12> CLK_BUF_CPU_BCLK <12>

CLK_BUF_DREF_96M# <12> CLK_BUF_DREF_96M <12>

CLK_BUF_PCIE_SATA# <12> CLK_BUF_PCIE_SATA <12>

CLK_BUF_ICH_14M <12>

CLK_PCI_FB <17>

EC_SMB_CK2

EC_SMB_DA2

11/06 Change +1.05VS to +1.1VS_VTT

1 2

R160 10K_0402_5%@R160 10K_0402_5%@

1 2 1 2

R162 10K_0402_5%@R162 10K_0402_5%@

1 2 1 2

R164 10K_0402_5%@R164 10K_0402_5%@

1 2

R165 10K_0402_5%R165 10K_0402_5%

1 2

R166 10K_0402_5%@R166 10K_0402_5%@

1 2 1 2

10K_0402_5%R161 10K_0402_5%R161

10K_0402_5%R163 10K_0402_5%R163

10K_0402_5%R167 10K_0402_5%R167

2

1

+3VALW

PCH_SML0CLK

PCH_SML0DAT

R622 2.2K_0402_5%R622 2.2K_0402_5%

1 2

R623 2.2K_0402_5%R623 2.2K_0402_5%

1 2

11/02 Add R621,R622 pull-up 2.2kohm to +3VALW (Follow NIWE2)

EC_SMB_CK2 <33>

EC_SMB_DA2 <33>

+3VALW

C148

C148 27P_0402_50V8J

27P_0402_50V8J

1 2

+3VS

+1.1VS_VTT

Title

Size Document Number Rev

Custom

Date: Sheet

12

R159

1M_0402_5%

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

NAU00 M/B LA-6101P Schematics

Y2

Y2 25MHZ_20PF_7A25000012

25MHZ_20PF_7A25000012

1 2

C149

C149 27P_0402_50V8J

27P_0402_50V8J

1

of

14 48Tuesday, March 09, 2010

1.0

5

DMI_HTX_PRX_N[0..3]<4>

DMI_HTX_PRX_P[0..3]<4>

DMI_PTX_HRX_N[0..3]<4>

DMI_PTX_HRX_P[0..3]<4>

DMI_HTX_PRX_N[0..3]

DMI_HTX_PRX_P[0..3]

DMI_PTX_HRX_N[0..3]

DMI_PTX_HRX_P[0..3]

4

3

2

1

D D

+3VS

R182 8.2K_0402_5%R182 8.2K_0402_5%

R183 10K_0402_5%R183 10K_0402_5%

10/30 Change R183 from mount to @ (Follow NCQD0) 11/25 Change R183 from @ to mount (Follow NIWE2)

+3VALW

R184 10K_0402_5%R184 10K_0402_5%

R186 8.2K_0402_5%R186 8.2K_0402_5%

C C

R187 10K_0402_5%R187 10K_0402_5%

R188 10K_0402_5%R188 10K_0402_5%

R189 10K_0402_5%

H_FDI_TXN[0..7]<4>

H_FDI_TXP[0..7]<4>

1 2

9/14 Change power net from +3V to +3VALW

1 2

@

1 2

PM_CLKRUN#

PCH_SYS_RESET#

SUS_PWR_ACK_R

PCH_GPIO72

RI#

PCH_PCIE_WAKE#

PM_SLP_LAN#

XDP_DBRESET#<5>

11/05 Add R627(@) (Follow NIWE2)

B B

SUS_PWR_ACK<33>

11/03 Change R193 from 100kohm to 10kohm (Follow Intel and NIWE2)

+3VALW

AC_PRESENT<33>

11/03 Delete D1, add R624

11/05 Delete the off page : EC_SWI# from PCH to EC, change net from EC_SWI# to RI# (Follow NIWE2)

SYS_PWROK

A A

5

H_FDI_TXN[0..7]

H_FDI_TXP[0..7]

+1.1VS_VTT

DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3

DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3

DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3

DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2

11/06 Change +1.05VS to +1.1VS_VTT

R185

49.9_0402_1%

1 2

DMI_PTX_HRX_P3

DMI_COMP

BC24

BJ22

AW20

BJ20

BD24 BG22 BA20 BG20

BE22

BF21 BD20 BE18

BD22 BH21 BC20 BD18

BH25

BF25

U3C

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

REV1.0

10/22 Change R188 from 1kohm to 10kohm (Follow checklist)

10/22 Reserve R612(@) between PCH_SYS_RESET# and XDP_DBRESET# Chanfe R183 from @ to mount 10/30 Change R612 from @ to mount (Follow NCQD0)

R612 0_0402_5%R612 0_0402_5%

SYS_PWROK VGATE

R190 0_0402_5%R190 0_0402_5% R191 0_0402_5%@R191 0_0402_5%@

SYS_PWROK

R627 0_0402_5%@R627 0_0402_5%@

R193 10K_0402_5%R193 10K_0402_5%

1 2

R624 0_0402_5%R624 0_0402_5%

1 2

PM_DRAM_PWRGD<5>

1 2

12

12 12

PBTN_OUT#<33>

11/09 Add R629(@)

R629 0_0402_5%@R629 0_0402_5%@

1 2

+3VS

5

U5

2

P

B

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

SYS_PWROK

EC_PWROK

LAN_RST#

No used Integrated LAN, connecting LAN_RST# to GND

1 2

R198 10K_0402_5%R198 10K_0402_5%

1 2

R199 10K_0402_5%R199 10K_0402_5%

1 2

R200 10K_0402_5%R200 10K_0402_5%

PCH_SYS_RESET#

SYS_PWROK_R

12

R192 0_0402_5%R192 0_0402_5%

LAN_RST#

PCH_RSMRST#

SUS_PWR_ACK_R

PBTN_OUT#

PCH_ACIN

PCH_GPIO72

RI#

EC_PWROK

VGATE

ME_PWROK

EC_PWROK <33>

VGATE <12,47>

4

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPI O30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA107

BA18

FDI_RXN0

BH17

FDI_RXN1

BD16

FDI_RXN2

BJ16

FDI_RXN3

BA16

FDI_RXN4

BE14

FDI_RXN5

BA14

FDI_RXN6

BC12

FDI_RXN7

BB18

FDI_RXP0

BF17

FDI_RXP1

BC16

FDI_RXP2

BG16

FDI_RXP3

AW16

FDI_RXP4

BD14

FDI_RXP5

BB14

FDI_RXP6

BD12

FDI_RXP7

BJ14

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

PCH_PCIE_WAKE#

PM_CLKRUN#

PCH_GPIO61

PCH_GPIO62

PM_SLP_M#

PM_SLP_DSW#

PM_SLP_LAN#

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7

H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7

@

PAD

@

PAD

PM_SLP_S5# <33>

PM_SLP_S4# <33>

PM_SLP_S3# <33>

@

PAD

@

PAD

H_PM_SYNC <5>

H_FDI_INT <4>

H_FDI_FSYNC0 <4>

H_FDI_FSYNC1 <4>

H_FDI_LSYNC0 <4>

H_FDI_LSYNC1 <4>

PCH_PCIE_WAKE# <26,32,37>

PM_CLKRUN# <33>

T6

T7

T8

T9

9/14 Change PN of D14B from SC6V99DW000 to SC6V99DW010

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

2

R194 0_0402_5%@R194 0_0402_5%@

PCH_RSMRST#

R195

R195 10K_0402_5%

10K_0402_5%

12

Title

Size Document Number Rev

Custom

Date: Sheet

12

Q16

Q16 MMBT3906_SOT23-3

MMBT3906_SOT23-3

123

C

E

B

1 2

R196 4.7K_0402_5%R196 4.7K_0402_5%

D2A

1

2

BAV99DW-7-F_SOT363~N

D2B

4

5

BAV99DW-7-F_SOT363~N

Compal Electronics, Inc.

PCH (3/9) DMI, FDI, PM

NAU00 M/B LA-6101P Schematics

EC_RSMRST# <33>

+3VALW

9/14 Change power net from +3V to +3VALW

6

11/05 Change D3B to D2B

3

12

R197

2.2K_0402_5%

1

1.0

of

15 48Tuesday, March 09, 2010

COMPAL LA-6101P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual