COMPAL LA-6101P Schematics

A

ZZZ1

JDCIN1

ZZZ2

PCB

DAZ@

1 1

11/18 Change PCB P/N from DA60000G300 to DA60000G200

JDCIN1

DCIN Cable

45@

11/03 Add DC-IN Cable P/N : DC301009N00

ZZZ1

LA-6101P

M/B

M/B DA2@

DA2@

ZZZ3

LS-6101P

FUN/B

FUN/B DA2@

DA2@

12/04 Change PJP1 to JDCIN1

ZZZ4

LS-6102P

FP/B

FP/B DA2@

DA2@

B

ZZZ6

ZZZ5

LS-6103P

LED/B

LED/B DA2@

DA2@

ZZZ6

LS-6104P

PWR/B

PWR/B DA2@

DA2@

C

D

E

02/26 Change LA-6101P P/N from DA60000G200 to DA60000G210

02/26 Add DAZ P/N and other small board P/N

02/26 Change DAZ P/N from DAZ0D9001001 to DAZ0D900101

Compal Confidential

2 2

NAU00 LA-6101P Schematics Document

Intel Arrandale Processor with DDRIII + Ibex Peak-M

SV M/B

3 3

2010-03-09

Rev : 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

NAU00 M/B LA-6101P Schematics

148Tuesday, March 09, 2010

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E

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1.0

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B

C

D

E

Compal Confidential

Model Name : NAU00 File Name : LA-6101P

1 1

Clock Generator

IDT: 9LRS3199AKLFT SILEGO: SLG8SP587

133/120/100/96/14.318MHZ to PCH

48MHZ to CardReader

Page 12

Fan Control

Page 37

Intel

Arrandale

SV

Processor

rPGA988A

Page 4,5,6,7,8,9

Memory Bus (DDRIII)

Dual Channel

1.5V DDRIII 800/1066/1333

6.4G/8.5G/10.6G

100M/133M/166M(CFD)

204 Pin DDRIII SO-DIMM x2

BANK 0, 1, 2, 3

Page 10,11

HDMI Conn.

Page 24

2 2

HDMI Level Shifter

ASmedia AM1442T

Page 24

100MHz

New Card

Port 3

Page 37

3 3

CRT Conn.

Page 23

LVDS Conn.

ABD PCIE Gen1 2.5GT/S

Mini Card

WLAN

LAN(GbE)

Atheros 8151

Port 2 Port 1

Page 32 Page 26

Page 22

LVDS

CRT

HDMI

PCI-Express X1

PortPortPort

FDI x8

100MHz

1GB/s x4

DMI x4

100MHz

2.7GT/s

Intel

Ibex Peak-M

PCH

FCBGA 1071Pin

Page 13,14,15,16,17,18,19,20, 21

LPC

33MHz

USB Conn.x3

Port 0,3 (USB) Port 1 (eSATA)

Page 31

USB

3.3V 48MHz

HD Audio

SATA

Gen1 1.5GT/S ,Gen2 3GT/S

SPI

BIOS ROM

4MB

Page 13

CardReader

Port 5

3.3V 24MHz

HDD

Port 0

Page 25 Page 32

Bluetooth Camera

Port 11

Port 2

FingerPrint

UPEK TCS5BB6A2Realtek RTS5138 Port 9

Page 28 Page 35 Page 22 Page 36

100MHz

3G Card

Port 13

Page 32

SSD

Port 1,5 Mini card slot

e-SATA Conn.

Port 4

Page 31

HDA Codec

Realtek ALC259

CPU XDP

Page 35

RTC Ckt.

Page 35

RJ-45

Page 27

ENE KB926E0

Page 33

Touch Pad Int.KBD

Page 35

Page 36

Small Board

Power/B

LS-6104P

Thinklight/B

LS-6103P

Int. Speaker Int. Digital MIC

Page 30 Page 30

Page 29

Phone Jack x 2

Power On/Off Ckt.

Page 34

4 4

DC/DC Interface Ckt.

Power Ckt.

Page 34

Page 38

G-Sensor

Page 25

A

EC I/O Buffer EC ROM

Page 33 Page 36

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

128kB

Issued Date

2009/10/10 2010/10/10

C

Function/B

LS-6101P

Compal Secret Data

Deciphered Date

FP/B

D

LS-6102P

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

NAU00 M/B LA-6101P Schematics

248Friday, February 26, 2010

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A

Voltage Rails

Power Plane Description

VIN

B+

+CPU_CORE

1 1

2 2

+0.75VS 0. 75V switched powe r rail for DDR terminator

+1.05VS

+1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF

+1.5V ON ON OFF

+1.5VS

+1.8VS 1.8V switched power rail

+3VALW 3.3V always on power rail

+3V

+3V_LAN

+3VS

+5VALW

+5VS

+5V 5V power rail for PCH

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only wit h AC power available, otherwise it is OFF.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

1.05V switched power rail for PCH

1.5V power ra il for DDRIII

1.5V switched power rail

3.3V power rail for PCH

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail

5V switched power rail

B

S1

S3 S5

N/A N/A N/A

ON

ON OFF OFF

ON

ON ON

ON

ON ON ON

ON

N/AN/AN/A

OFF

ON

OFF

ON ON*

ON

ON*

OFF

ON ON*

OFF

OFFON

ONON

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOW

LOWLOWLOW

LOW LOW LOW LOW

HIGHHIGHHIGH

HIGH

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

D

ON

OFF

ON

OFF

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

ON ON

ON

OFF

max

E

LOW

OFF

BOARD ID Table

External PCI Devices

Device IDSEL#

REQ#/GNT#

Interrupts

Board ID

0

*

1 2 3 4 5 6 7

PCB Revision

0.1

EC SM Bus1 address

3 3

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

Ibex SM Bus address

Device

Clock Generator (9LRS3199AKLFT, SLG8SP587)

DDR DIMM0

DDR DIMM2

ISL90727 ISL90728

4 4

A

Address

1101 0010b

1001 000Xb

1001 010Xb

0101 1100b 0111 1100b

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

C

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

NAU00 M/B LA-6101P Schematics

348Friday, February 26, 2010

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5

JCPU1A

DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3

DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2

H_FDI_FSYNC0<15> H_FDI_FSYNC1<15>

H_FDI_LSYNC0<15> H_FDI_LSYNC1<15>

H_FDI_INT<15>

DMI_PTX_HRX_P3

DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3

DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3

H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7

H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7

D D

C C

B B

A A

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

CONN@

DMI Intel(R) FDI

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

4

PEG_IRCOMP

EXP_RBIAS

R1

1 2

R2

1 2

49.9_0402_1%

750_0402_1%

DMI_PTX_HRX_N[0..3] <15> DMI_PTX_HRX_P[0..3] <15>

DMI_HTX_PRX_N[0..3] <15> DMI_HTX_PRX_P[0..3] <15>

H_FDI_TXN[0..7] <15> H_FDI_TXP[0..7] <15>

3

11/12 Delete R3(@),R4(@),R5(@),R6(@)

11/17 Delete R9,R10

CFG0 - PCI-Express Configuration Select

*1:Single PEG 0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

2

JCPU1E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_rPGA,R1P0

CONN@

(CFD Only) (CFD Only)

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD_TP_59 RSVD_TP_60

RESERVED

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

RSVD32 RSVD33

RSVD34 RSVD35

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

KEY RSVD62 RSVD63 RSVD64 RSVD65

VSS

1

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15

11/17 Delete R7,R8

C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

*:Default

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR (1/6) DMI,FDI,PEG

NAU00 M/B LA-6101P Schematics

1

of

448Tuesday, March 09, 2010

1.0

5

JCPU1B

H_COMP3

H_COMP2

H_COMP1

H_COMP0

@

PAD

T1

R19

1 2

0_0402_5%

R29

1 2

0_0402_5%

R32

R32 0_0402_5%

0_0402_5%

R34

R34 0_0402_5%

0_0402_5%

R37

R37 0_0402_5%

0_0402_5%

R40

1 2

0_0402_5%

1 2

T1

1 2

D D

H_PECI<18>

H_PROCHOT#<33,47>

H_THERMTRIP#<18>

H_PM_SYNC<15>

C C

H_CPUPWRGD<18>

PM_DRAM_PWRGD<15>

VCCP_POK<45>

R620 1K_0402_1%R620 1K_0402_1%

R621 560_0402_5%R621 560_0402_5%

SKTOCC#_R

H_CATERR#

H_PECI_R

H_PROCHOT#

H_THERMTRIP#_R

H_CPURST#

H_PM_SYNC_R

H_CPUPWRGD_1

H_CPUPWRGD_0

PM_DRAM_PWRGD_R

VCCP_POK_R

10/30 Add R620,R621 (Follow NIWE2)

PLT_RST#<17,33>

2009/2/4 #414044 DG Update Rev1.11

R42

1 2

1.5K_0402_1%

PLT_RST#_R

12

R43

R43 750_0402_1%

750_0402_1%

JCPU1B

AT23

AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

IC,AUB_CFD_rPGA,R1P0

CONN@

10/21 Delete R41 Delete Net : H_PWRGD_XDP,H_PWRGD_XDP_R

4

COMP3

COMP2

COMP1

COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

MISC THERMAL

DPLL_REF_SSCLK#

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY# PREQ#

TCK TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TDI

3

11/12 Delete R11,R12,R15,R16 (Layout Spacing)

CLK_CPU_BCLK

A16

CLK_CPU_BCLK#

B16

CLK_CPU_ITP_R

AR30 AT30

E16 D16

A18 A17

F6

AL1 AM1 AN1

AN15 AP15

AT28 AP27

AN28 AP28 AT27

AT29 AR27 AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

CLK_CPU_ITP#_R

CLK_CPU_DMI CLK_CPU_DMI#

CLK_CPU_DP_R CLK_CPU_DP#_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PM_EXTTS#0 PM_EXTTS#1_R

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO XDP_TDI_M XDP_TDO_M

XDP_DBR#_R

R572 0_0402_5%R572 0_0402_5% R573 0_0402_5%R573 0_0402_5%

R36 0_0402_5%@R36 0_0402_5%@

1 2

PAD @

T17

PAD @

T18

1 2 1 2

SM_DRAMRST# <10>

11/05 Delete R21(@)

R25 10K_0402_5%R25 10K_0402_5%

1 2

R27 10K_0402_5%R27 10K_0402_5%

1 2

R28 0_0402_5%R28 0_0402_5%

1 2

11/25 Change R36 from mount to @ (Follow NIWE2)

ESD Recommend

10/21 Delete Net : XDP_OBS[7:0]

2009/2/4 Delete dampling resistor for power noise and Layout space issue

2

CLK_CPU_BCLK <18> CLK_CPU_BCLK# <18>

10/21 Delete R13,R14, Add T17,T18

CLK_CPU_DMI <14> CLK_CPU_DMI# <14>

10/30 Delete Net : CLK_CPU_DP, CLK_CPU_DP# Delete R17,R18

+1.1VS_VTT

PM_EXTTS#0_1 <10,11>

XDP_DBRESET#

XDP_DBR#_R

XDP_DBRESET# <15>

C500 0.1U_0402_16V4Z@C500 0.1U_0402_16V4Z@

1 2

Processor CLK

Reference Input Clock

BCLK/BCLK#

PEG_CLK/ PEG_CLK#

DPLL_REF_SSCLK/ DPLL_REF_SSCLK#

10/28 Delete R31,R33(@),R38(@),R39 Delete Net : XDP_TDI_R,XDP_TDO_R

XDP_PRDY# XDP_TMS XDP_TDI XDP_PREQ# XDP_TCLK

XDP_TRST#

XDP_TDO_M

XDP_TDI_M

Input Frequency

133MHz

100MHz

120MHz

R20 51_0402_5%@R20 51_0402_5%@

1 2

R22 51_0402_5%@R22 51_0402_5%@

1 2

R23 51_0402_5%@R23 51_0402_5%@

1 2

R24 51_0402_5%@R24 51_0402_5%@

1 2

R26 51_0402_5%@R26 51_0402_5%@

1 2

R30 51_0402_5% R30 51_0402_5%

1 2

12

R35

R35 0_0402_5%

0_0402_5%

1

Associated PLL

Processor/Memory /Graphic

PCI Express/ DMI/FDI

Embedded Displayport

+1.1VS_VTT

+3VALW

5

2

P

B

4

Y

1

A

G

U1

3

NC7SZ08P5X_NL_SC70-5

Note: When implement S3 power reduction not to pop,R53,R44 pop U1,R45,R54

11/23 Change R44,R53 from mount to @ Change U1,R45,R54 from @ to mount

VCCP_POK

SSM3K7002FU_SC70-3

2

G

Q37

VCCP_POK

+5VALW

12

R574

R574 10K_0402_5%

10K_0402_5%

S3_0.75V_EN

13

D

S

12/04 Change Q37 from SB000008J00 to SB000009610 (Layout Spacing)

4

VCCP_POK <45>

S3_0.75V_EN <44>

H_CATERR# H_PROCHOT# H_CPURST#

H_COMP0 H_COMP1 H_COMP2 H_COMP3

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

11/16 Reserve C530,C531,C532 for avoiding switching noise 11/23 Change C530,C531,C532 from @ to mount

VCCP_POK

PM_DRAM_PWRGD_R

H_CPUPWRGD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R46 49.9_0402_1%R46 49.9_0402_1%

1 2

R47 68_0402_5%R47 68_0402_5%

1 2

R48 68_0402_5%@R48 68_0402_5%@

1 2

R49 49.9_0402_1%R49 49.9_0402_1%

1 2

R50 49.9_0402_1%R50 49.9_0402_1%

1 2

R51 20_0402_1%R51 20_0402_1%

1 2

R55 20_0402_1%R55 20_0402_1%

1 2

R58 100_0402_1%R58 100_0402_1%

1 2

R60 24.9_0402_1%R60 24.9_0402_1%

1 2

R61 130_0402_1%R61 130_0402_1%

1 2

C530 100P_0402_50V8JC530 100P_0402_50V8J

1 2

C531 100P_0402_50V8JC531 100P_0402_50V8J

1 2

C532 100P_0402_50V8JC532 100P_0402_50V8J

1 2

2009/10/10 2010/10/10

3

1.1K_0402_1%

3K_0402_1%

+1.5V_1

R44

@

R53

@

12

R45

1.5K_0402_1%

12

R54

750_0402_1%

5

B B

PM_DRAM_PWRGD_R

A A

+1.1VS_VTT

Compal Secret Data

Deciphered Date

10/21 Delete JP1,R52,R56,R57,R59,C1 Delete Net : H_CPUPWRGD,H_PWRGOOD_R, PBTN_OUT#_XDP,CLK_CPU_XDP,CLK_CPU_XDP#

XDP_DBRESET#

XDP_TDO

10/22 Change R62 from mount to @ 10/30 Change R62 from @ to mount (Follow NCQD0) 11/25 Change R62 from mount to @ (Follow NIWE2)

2

1 2

Title

Size Document Number Rev

B

Date: Sheet

R62

@ R62

@

1K_0402_5%

R63

R63 51_0402_5%

51_0402_5%

Compal Electronics, Inc.

PROCESSOR (2/6) CLK,JTAG

NAU00 M/B LA-6101P Schematics

+3VS

+1.1VS_VTT

1

Leakage Issue

548Tuesday, March 09, 2010

1.0

of

5

JCPU1C

C10

D10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ10

AL10

AK12

AK8

AK11

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

A10

B10

E10

F10

J10

AJ7 AJ6

AJ9

AL7

AL8

C7 A7

A8 D8

E6 F7 E9 B7 E7 C6

G8

K7

J8

G7

J7

L7 M6 M8

L9

L6

K8 N8 P9

U7

JCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

DDR_A_D[0..63]<10>

DDR_A_DM[0..7]<10>

DDR_A_DQS#[0..7]<10>

DDR_A_DQS[0..7]<10>

DDR_A_MA[0..15]<10>

DDR_A_D0 DDR_A_D1

D D

C C

B B

DDR_A_BS0<10> DDR_A_BS1<10> DDR_A_BS2<10>

DDR_A_CAS#<10> DDR_A_RAS#<10> DDR_A_WE#<10>

DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0

DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_A_MA14

DDR_A_MA15

DDR_A_CLK0 <10> DDR_A_CLK0# <10> DDR_A_CKE0 <10>

DDR_A_CLK1 <10> DDR_A_CLK1# <10> DDR_A_CKE1 <10>

DDR_A_CS0# <10> DDR_A_CS1# <10>

DDR_A_ODT0 <10> DDR_A_ODT1 <10>

3

JCPU1D

AM6 AN2

AM4 AM3

AN5

AN6 AN4 AN3

AN7

AR10

AT10

AF3 AG1

AK1 AG4 AG3

AH4 AK3 AK4

AK5 AK2

AP3

AT4

AT5 AT6

AP6 AP8 AT9 AT7 AP9

AB1

AC5

AC6

JCPU1D

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2

J6

J3 G1 G5

J2

J1

J5 K2

L3 M1 K5 K4 M4 N5

AJ3

AJ4

W5

R7

Y7

DDR_B_D[0..63]<11> DDR_B_DM[0..7]<11>

DDR_B_DQS#[0..7]<11>

DDR_B_DQS[0..7]<11>

DDR_B_MA[0..15]<11>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0<11> DDR_B_BS1<11> DDR_B_BS2<11>

DDR_B_CAS#<11> DDR_B_RAS#<11> DDR_B_WE#<11>

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

1

DDR_B_CLK0 <11> DDR_B_CLK0# <11> DDR_B_CKE0 <11>

DDR_B_CLK1 <11> DDR_B_CLK1# <11> DDR_B_CKE1 <11>

DDR_B_CS0# <11> DDR_B_CS1# <11>

DDR_B_ODT0 <11> DDR_B_ODT1 <11>

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

IC,AUB_CFD_rPGA,R1P0

CONN@

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

PROCESSOR (3/6) DDRIII

NAU00 M/B LA-6101P Schematics

1

of

648Tuesday, March 09, 2010

1.0

5

JCPU1F

+CPU_CORE

WW15 MOW

48A Continuous 18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

D D

C C

B B

A A

AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26

VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

CPU VIDS

SENSE LINES

Peak 21A

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

4

10U_0805_6.3V6M

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

VTT_SELECT

G15

VTT_SELECT = Low, 1.1V VTT_SELECT = High, 1.05V

AN35

VCCSENSE_CPU

AJ34

VSSSENSE_CPU

AJ35

B15

VSS_SENSE_VTT

A15

Note:CRB has the VTT_ SENSE connected through a "no-stuff" 0- series resistor and VSS_SENSE_VTT floating.Connec t VSS_SENSE_VTT to GND or can be left floating.

10U_0805_6.3V6M

1

C2

2

10U_0805_6.3V6M

1

+

C18

2

330U_D2_2.5VY_R9M

22U_0805_6.3V6M

1

C28

C29

2

22U_0805_6.3V6M

IMVP_IMON <47 >

R83 0_0402_5%R83 0_0402_5%

1 2

R84 0_0402_5%R84 0_0402_5%

1 2

R86 0_0402_5%@R86 0_0402_5%@

10U_0805_6.3V6M

1

C4

C3

2

10U_0805_6.3V6M

+1.1VS_VTT

330U_D2_2.5VY_R9M

1

+

C19

C20

@

2

330U_D2E_2VM_R6M

+1.1VS_VTT

1

2

VTT_SENSE <45>

1 2

1

2

10U_0805_6.3V6M

1

+

2

PSI# <47>

H_VID0 <47> H_VID1 <47> H_VID2 <47> H_VID3 <47> H_VID4 <47> H_VID5 <47> H_VID6 <47> PROC_DPRSLPVR <47>

VTT_SELECT <45>

VTT Rail

Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V

3

+1.1VS_VTT

10U_0805_6.3V6M

1

C5

C6

2

1

C7

C8

2

10U_0805_6.3V6M

11/25 Change C18,C19,C20 from SGA00002380 (6mohm) to SGA00002680 (9mohm) 11/25 Change C19 from mount to @

+CPU_CORE

10U_0805_6.3V6M

1

C9

2

11/30 Change C20 from SGA00002680 (9mohm) to SGA00002U00 (6mohm)

11/09 Change R64,R66 from mount to @ (PWR Recommend)

11/09 Change R65 ,R67 from @ to mount (PWR Recommend)

CSC (Current Sense Configuration)

11/09 H_VID[6:0] => 0100100

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

PROC_DPRSLPVR

PSI#

11/17 Reserve C534,C535 for avoiding switching noise 11/17 Change C534,C535 from @ to mount

VTT_SELECT

VTT_SENSE

R64 1K_0402_1%@R64 1K_0402_1%@

1 2

R65 1K_0402_1%R65 1K_0402_1%

1 2

R66 1K_0402_1%@R66 1K_0402_1%@

1 2

R67 1K_0402_1%R67 1K_0402_1%

1 2

R68 1K_0402_1%R68 1K_0402_1%

1 2

R69 1K_0402_1%@R69 1K_0402_1%@

1 2

R70 1K_0402_1%@R70 1K_0402_1%@

1 2

R71 1K_0402_1%R71 1K_0402_1%

1 2

R72 1K_0402_1%@R72 1K_0402_1%@

1 2

R73 1K_0402_1%R73 1K_0402_1%

1 2

R74 1K_0402_1%R74 1K_0402_1%

1 2

R75 1K_0402_1%@R75 1K_0402_1%@

1 2

R76 1K_0402_1%@R76 1K_0402_1%@

1 2

R77 1K_0402_1%R77 1K_0402_1%

1 2

R78 1K_0402_1%R78 1K_0402_1%

1 2

R79 1K_0402_1%@R79 1K_0402_1%@

1 2

R80 1K_0402_1%@R80 1K_0402_1%@

1 2

R81 1K_0402_1%R81 1K_0402_1%

1 2

C534 100P_0402_50V8JC534 100P_0402_50V8J

1 2

C535 100P_0402_50V8JC535 100P_0402_50V8J

1 2

+1.1VS_VTT

Please place C534,C535 close to PU701

11/09 Change C42~C47 from SGA00002U00 to SGA00001Q80 (PWR Recommend)

11/11 Correct C42~C47 footprint

+CPU_CORE

1 2

R82 100_0402_1%R82 100_0402_1%

VCCSENSE VSSSENSE

1 2

R85 100_0402_1%R85 100_0402_1%

+CPU_CORE

VCCSENSE <47> VSSSENSE <47>

C42

330U_X_2VM_R6M

11/25 Change R86 from mount to @ (Follow NIWE2)

2

10U_0805_6.3V6M

1

C10

2

10U_0805_6.3V6M

(Place these capacitors between inductor and socket on Bottom)

+CPU_CORE

10U_0805_6.3V6M

4 x 330uF(6m ohm@100kHz)

1

+

2

C44

330U_X_2VM_R6M

TOP side (under inductor)

10U_0805_6.3V6M

C11

10U_0805_6.3V6M

C21

1

2

1

2

1

2

1

2

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

22U_0805_6.3V6M

1

C34

2

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE

22U_0805_6.3V6M

1

C36

2

22U_0805_6.3V6M

1

C12

2

1

C22

2

10U_0805_6.3V6M

1

C30

2

22U_0805_6.3V6M

1

C37

2

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)

C13

10U_0805_6.3V6M

C23

1

C35

2

1

C38

2

1

2

1

2

SGA00001Q80

1

+

@

330U_X_2VM_R6M

2

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

1

+

C45

330U_X_2VM_R6M

2

C,uF

4X330uF 6m ohm/4

16X22uF

16X10uF 3m ohm/16

+

C46

ESR, mohm

3m ohm/12

10U_0805_6.3V6M

C14

C24

10U_0805_6.3V6M

22U_0805_6.3V6M

1

C31

2

22U_0805_6.3V6M

1

C39

2

1

330U_X_2VM_R6M

2

1

C15

2

10U_0805_6.3V6M

1

C25

2

1

C32

2

22U_0805_6.3V6M

1

C40

2

22U_0805_6.3V6M

1

+

C47

2

Stuffing Option

2X330uF

10U_0805_6.3V6M

1

C16

2

1

C26

2

10U_0805_6.3V6M

22U_0805_6.3V6M

1

C33

2

22U_0805_6.3V6M

1

C41

2

C43

330U_X_2VM_R6M

1

C17

2

1

C27

2

1

+

@

2

Security Classification

IC,AUB_CFD _rPGA,R1P0

CONN@

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR (4/6) PWR,Bypass

NAU00 M/B LA-6101P Schematics

748Tuesday, March 09, 2010

of

1

of

1.0

5

4

3

2

1

+GFX_CORE

22U_0805_6.3V6M

1

C53

C48

@

22U_0805_6.3V6M

1

+

C52

2

@

2

D D

330U_D2_2.5VY_R9M

22U_0805_6.3V6M

1

C54

C49

@

2

22U_0805_6.3V6M

1

+

C57

@

330U_D2_2.5VY_R9M

2

22U_0805_6.3V6M

1

C55

C50

2

22U_0805_6.3V6M

10U_0805_6.3V6M

1

C56

C51

2

10U_0805_6.3V6M

1

2

11/25 Change C52,C57 from SGA00002380 (6mohm) to SGA00002680 (9mohm)

C C

+1.1VS_VTT

1

2

1

2

1

C67

22U_0805_6.3V6M

2

1

C70

22U_0805_6.3V6M

2

C66

22U_0805_6.3V6M

+1.1VS_VTT

C69

22U_0805_6.3V6M

B B

22U_0805_6.3V6M

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R1P0

CONN@

15A

GRAPHICS

FDI PEG & DMI

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6

3A

POWER

0.6A

VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

DDR3 - 1.5V RAILS

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65

1.1V1.8V

VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

GFXVR_EN

AR25

GFXVR_DPRSLPVR_R

AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

1U_0402_6.3V4Z

C58

1U_0402_6.3V4Z

+1.1VS_VTT

1

2

+1.8VS_VCCSFR

C72

VCC_AXG_SENSE <46> VSS_AXG_SENSE <46>

11/23 Change R610 from SD028470180(4.7kohm) to SD028470080(470ohm) (Follow Intel Recommend)

GFXVR_VID_0 <46> GFXVR_VID_1 <46> GFXVR_VID_2 <46> GFXVR_VID_3 <46> GFXVR_VID_4 <46> GFXVR_VID_5 <46> GFXVR_VID_6 <46>

R87 0_0402_5%R87 0_0402_5%

1 2

1U_0402_6.3V4Z

1

C59

2

+1.1VS_VTT

C71

22U_0805_6.3V6M

1

C73

2

1U_0402_6.3V4Z

1

C60

C61

2

1U_0402_6.3V4Z

1

C68

10U_0805_6.3V6M

2

2.2U_0603_6.3V6K

1

C75

C74

2

4.7U_0603_6.3V6K

10/22 Reserve R609,R610 for GFXVR_EN,GFXVR_DPRSLPVR_R

11/02 Change R610 from @ to mount (Follow NIWE2)

1

C62

2

1U_0402_6.3V4Z

1

2

GFXVR_EN GFXVR_DPRSLPVR_R

GFXVR_EN <46>

PAD

T16

GFXVR_IMON <46>

22U_0805_6.3V6M

1

C63

C64

2

22U_0805_6.3V6M

1 2

1

C76

2

22U_0805_6.3V6M

R610 470_0402_5%R610 470_0402_5%

1 2

R609 10K_0402_5%@R609 10K_0402_5%@

1 2

@

1

+

C65

C65 330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

12/22 Change C65 from SGA20331E10 to SGA00002680

R88

R88 0_0805_5%

0_0805_5%

+1.8VS

+1.5V_1

A A

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR (5/6) PWR

NAU00 M/B LA-6101P Schematics

1

of

848Tuesday, March 09, 2010

1.0

5

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

VSS8

AR17

VSS9

AR15

VSS10

D D

C C

B B

AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2

AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8

AF4

AF2 AE35

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

K27

H35 H32 H28 H26 H24 H22 H18 H15 H13 H11

G34 G31 G20

F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11

D33 D30 D26

C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11

A29 A27 A23

4

JCPU1I

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178

H8

VSS179

H5

VSS180

H2

VSS181 VSS182 VSS183 VSS184

G9

VSS185

G6

VSS186

G3

VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201

E8

VSS202

E5

VSS203

E2

VSS204 VSS205 VSS206 VSS207

D9

VSS208

D6

VSS209

D3

VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226

B8

VSS227

B6

VSS228

B4

VSS229 VSS230 VSS231 VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

11/17 Delete T2,T3,T4,T5

AT35 AT1 AR34 B34 B2 B1 A35

3

Screw cap.

2

Please place C520~C529 close to H1,H10,H2,H20,H3,H4,H6,H7,H8,H9

12/15 Change C520(@),C528(@) from SE070104Z80 to SE042104K80

C524

@

0.1U_0402_16V4Z

1

C522

@

0.1U_0402_16V4Z

2

+3VS

1

2

11/10 Add C520~C529(@) (ESD Recommend)

11/13 Change C522 power from +3VS to +3VALW

11/17 Delete C521(@),C523(@)

+3VS

1

C525

@

0.1U_0402_16V4Z

2

1

C526

@

0.1U_0402_16V4Z

2

1

C527

@

0.1U_0402_16V4Z

2

12/15 Add C536~C540 (EMI Recommend)

12/15 Change C539,C540 from SE070104Z80 to SE042104K80

1

C536

0.1U_0402_16V4Z

2

+5VS

12/15 Add C541~C543 (EMI Recommend)

1

C541

0.1U_0402_16V4Z

2

1

C537

0.1U_0402_16V4Z

2

1

C542

0.1U_0402_16V4Z

2

1

C538

0.1U_0402_16V4Z

2

1

C543

0.1U_0402_16V4Z

2

1

11/17 Change the power of C520,C528 from +3VS to B+

B++3VALW

1

C520

@

0.1U_0603_25V7K

2

1

C529

@

0.1U_0402_16V4Z

2

B++3VS

1

C539

0.1U_0603_25V7K

2

1

C528

@

0.1U_0603_25V7K

2

1

C540

0.1U_0603_25V7K

2

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

5

IC,AUB_CFD_rPGA,R1P0

CONN@

4

1

C550

0.1U_0402_16V4Z

2

01/15 Add C544~C549 (EMI Recommend) 01/16 Add C550 (EMI Recommend)

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

1

C544

0.1U_0402_16V4Z

2

1

C545

0.1U_0603_25V7K

2

B++R_CRT_VCC B+ +5VS +USB_VCCA+3VS

1

C546

0.1U_0603_25V7K

2

Title

Size Document Number Rev

Custom

Date: Sheet

1

C547

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

PROCESSOR (6/6) VSS

NAU00 M/B LA-6101P Schematics

1

C548

0.1U_0402_16V4Z

2

1

C549

0.1U_0402_16V4Z

2

of

948Friday, February 26, 2010

1.0

5

M1 Circuit

+1.5V

12

R91

1K_0402_1%

12

D D

+V_DDR3_DIMM_REF

R89

1K_0402_1%

2009/04/13 For Arrandale ,it should be use M1 Circuit For Clarksfield ,it should be use M3 Circuit DG V1.52

DDR_A_DQS#[0..7]<6>

DDR_A_D[0..63]<6>

DDR_A_DM[0..7]<6>

DDR_A_DQS[0..7]<6>

DDR_A_MA[0..15]<6>

SM_DRAMRST#<5>

11/05 Change R94 from @ to mount (Follow NIWE2)

C C

Layout Note: Place near JDIMM1

Layout Note: Place these 4 Caps near Command

B B

+1.5V

10U_0805_6.3V6M

1

C82

C81

2

10U_0805_6.3V6M

Layout Note: Place near JDIMM1.203 & JDIMM1.204

+0.75VS

1U_0603_10V4Z

A A

1U_0603_10V4Z

2

C94

1

1U_0603_10V4Z

and Control signals of DIMMA

10U_0805_6.3V6M

1

C83

2

10U_0805_6.3V6M

2

C95

1

1U_0603_10V4Z

C84

2

1U_0603_10V4Z

2

C96

1

5

1

C85

2

10U_0805_6.3V6M

1

C97

2

10U_0805_6.3V6M

1

C86

2

C98

10U_0805_6.3V6M

1

2

0.1U_0402_16V4Z

1

C87

2

1

C88

2

0.1U_0402_16V4Z

1

C89

2

4

12

R94

100K_0402_1%

1

C90

2

4

3

M1 Circuit

R90 0_0402_5%R90 0_0402_5%

+V_DDR3_DIMM_REF

R92 0_0402_5%@R92 0_0402_5%@

1 2

SGD

3 1

Q9 BSH111_SOT23-3

2

RST_GATE<18>

10/22 Add C502 at RST_GATE (Intel 425302_Calpella_S3PowerReduction_WhitePaper_Rev1.0) 11/09 Change C502 from 0.047uF to 0.1uF

11/23 Change R92 from mount to @ Change Q9 from @ to mount

1

+

C91

@

220U_D2_4VM

2

RST_GATE

1

C502

0.1U_0402_16V4Z

2

1 2

+1.5V

0.1U_0402_16V4Z

12

R93

1K_0402_1%

DIMM_DRAMRST#

10/21 Change R93 from @ to mount

11/25 Change C91(@) from SGA20331E10 to SGA00000Y80

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VREF_DQA

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2

1

C77

2.2U_0603_6.3V4Z

1

C78

2.2U_0603_6.3V4Z

2

11/10 Change C78 from SE103225Z80 to SE049225Z80

DDR_A_CKE0<6>

DDR_A_BS2<6>

DDR_A_CLK0<6> DDR_A_CLK0#<6>

DDR_A_BS0<6>

DDR_A_WE#<6> DDR_A_CAS#<6>

DDR_A_CS1#<6>

+3VS

1

C92

2

2009/10/10 2010/08/25

DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_CKE0

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK0#

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDR_A_CS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R96 10K_0402_5%R96 10K_0402_5%

1 2

1

C93

0.1U_0402_16V4Z

2

Compal Secret Data

12

R97

10K_0402_5%

Deciphered Date

+1.5V

2

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F CONN@

CONN@

Copy NTUC0

2

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

1

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28

DIMM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDR_A_CKE1

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_CLK1 DDR_A_CLK1#

DDR_A_BS1 DDR_A_RAS#

DDR_A_CS0# DDR_A_ODT0

DDR_A_ODT1

DDR_VREF_CA_DIMMA

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK

DIMM_DRAMRST# <11>

DDR_A_CKE1 <6>

DDR_A_CLK1 <6> DDR_A_CLK1# <6>

DDR_A_BS1 <6> DDR_A_RAS# <6>

DDR_A_CS0# <6> DDR_A_ODT0 <6>

DDR_A_ODT1 <6>

1 2

R95 0_0402_5%R95 0_0402_5%

C79

2.2U_0603_6.3V4Z

PM_EXTTS#0_1 <5,11>

D_CK_SDATA <11,12>

+0.75VS

D_CK_SCLK <11,12>

DDR3 SO-DIMM A Standard Type H = 4.0mm

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

NAU00 M/B LA-6101P Schematics

1

+V_DDR3_DIMM_REF

1

2

10 48Tuesday, March 09, 2010

1

C80

0.1U_0402_16V4Z

2

of

1.0

5

4

3

2

1

+1.5V

DDR_B_DQS#[0..7]<6>

DDR_B_D[0..63]<6>

DDR_B_DM[0..7]<6>

DDR_B_DQS[0..7]<6>

D D

DDR_B_MA[0..15]<6>

M1 Circuit

R98 0_0402_5%R98 0_0402_5%

+V_DDR3_DIMM_REF_B

2009/04/13 For Arrandale ,it should be use M1 Circuit For Clarksfield ,it should be use M3 Circuit DG V1.52

11/10 Change C99 from SE103225Z80 to SE049225Z80

R606

1K_0402_1%

1

C110

2

0.1U_0402_16V4Z

+1.5V

12

+V_DDR3_DIMM_REF_B

12

R607

1K_0402_1%

0.1U_0402_16V4Z

1

C111

2

+V_DDR3_DIMM_REF_B

1

+

C113

C112

0.1U_0402_16V4Z

C113

220U_D2_4VM

2

11/25 Change C113 from SGA20331E10 to SGA00000Y80

C C

Layout Note: Place near JDIMM2

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

+1.5V

10U_0805_6.3V6M

1

B B

A A

C103

10U_0805_6.3V6M

1U_0603_10V4Z

1

C104

2

10U_0805_6.3V6M

Layout Note: Place near JDIMM2.203 & JDIMM2.204

+0.75VS

C114

2

C116

C115

2

1

1U_0603_10V4Z

C105

1U_0603_10V4Z

1

C106

2

10U_0805_6.3V6M

C117

2

1

1U_0603_10V4Z

10U_0805_6.3V6M

1

C107

2

C118

2

1

10U_0805_6.3V6M

1

2

0.1U_0402_16V4Z

1

C108

2

10U_0805_6.3V6M

C109

1 2

2.2U_0603_6.3V4Z

+3VS

2.2U_0603_6.3V4Z

1

C99

2

C119

1

C100

2

0.1U_0402_16V4Z

DDR_B_CKE0<6>

DDR_B_BS2<6>

DDR_B_CLK0<6> DDR_B_CLK0#<6>

DDR_B_BS0<6>

DDR_B_WE#<6> DDR_B_CAS#<6>

DDR_B_CS1#<6>

1

2

C120

0.1U_0402_16V4Z

VREF_DQB

DDR_B_D0 DDR_B_D1

DDR_B_DM0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_B_CKE0

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK0#

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_B_CS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

R100 10K_0402_5%R100 10K_0402_5%

1 2

R101 10K_0402_5%R101 10K_0402_5%

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F CONN@

CONN@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

Copy NTUC0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/08/25

Compal Secret Data

Deciphered Date

DM1

DM2

DM4

DM6

SDA

DQ4 DQ5

DQ6 DQ7

CK1

BA1

NC2

SCL

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

DIMM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_B_CKE1

74 76

DDR_B_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_B_BS1 DDR_B_RAS#

DDR_B_CS0# DDR_B_ODT0

DDR_B_ODT1

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK

DIMM_DRAMRST# <10>

DDR_B_CKE1 <6>

DDR_B_CLK1 <6> DDR_B_CLK1# <6>

DDR_B_BS1 <6> DDR_B_RAS# <6>

DDR_B_CS0# <6> DDR_B_ODT0 <6>

DDR_B_ODT1 <6>

R99 0_0402_5%R99 0_0402_5%

PM_EXTTS#0_1 <5,10>

+0.75VS

1 2

C101

2.2U_0603_6.3V4Z

D_CK_SDATA <10,12> D_CK_SCLK <10,12>

+V_DDR3_DIMM_REF_B

1

C102

0.1U_0402_16V4Z

2

DDR3 SO-DIMM B Standard Type

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

NAU00 M/B LA-6101P Schematics

1

of

11 48Tuesday, March 09, 2010

of

11 48Tuesday, March 09, 2010

of

11 48Tuesday, March 09, 2010

1.0

A

B

C

D

E

F

G

H

Layout note:

Place C122 close to L2 Place C123 close to U2.15 Place C124 close to U2.18

1 1

+1.1VS_VTT

L2 0_0603_5% L2 0_0603_5%

1 2

11/06 Change +1.05VS to +1.1VS_VTT

11/03 Delete C121(@)

+CLK_VDDSRC

C122

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

C124

C123

2

11/03 Change L2 from SM01000AX00 to 0ohm (Follow NIWE2)

2 2

11/03 Delete RP1,RP2,RP3,RP4

CLK_BUF_DREF_96M<14> CLK_BUF_DREF_96M#<14>

CLK_BUF_DREF_96M CLK_BUF_DREF_96M#

10/21 Change R542 from 0ohm to 33ohm (Vendor Recommend)

CLK_48M<28>

CLK_BUF_PCIE_SATA<14> CLK_BUF_PCIE_SATA#<14>

CLK_BUF_CPU_DMI<14> CLK_BUF_CPU_DMI#<14>

3 3

11/04 Reserve C510(@) for CLK_48M (RF Recommend)

C510 15P_0402_50V8J@C510 15P_0402_50V8J@

1 2

CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA#

CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI#

10/23 Change R107 from mount to @

11/03 Change R107 from @ to mount

+3VS

R107 10K_0402_5%R107 10K_0402_5%

1 2

IDT& Realtek Have Internal Pull-Down

R109 10K_0402_5%R109 10K_0402_5%

1 2

4 4

PIN 30

0

(Default)

1

A

CPU_0

133MHz

100MHz

H_STP_CPU#

REF_0/CPU_SEL

CPU_1

133MHz

100MHz

B

Layout note: Layout note:

Place C130 close to L1 Place C131 close to U2.5 Place C132 close to U2.29

L1 0_0603_5% L1 0_0603_5%

+3VS

1 2

11/03 Delete C129(@)

+CLK_VDD

0.1U_0402_16V4Z

1

C130

2

10U_0805_10V4Z

1

C131

2

0.1U_0402_16V4Z

11/03 Change L1 from SM01000AX00 to 0ohm (Follow NIWE2)

10/23 Change U2 Pin1,17,24 Net Name to +VDD_3V3_1V5

+CLK_VDDSRC

R542 33_0402_5%R542 33_0402_5%

1 2

SSM3K7002FU_SC70-3

PCH_SMBDATA<14,32,37>

9/10 Change symbol of Q31/Q32 to SC70-3

PCH_SMBCLK<14,32,37>

SSM3K7002FU_SC70-3

C

+VDD_3V3_1V5

+CLK_VDD

48M

H_STP_CPU#

Q11

Q12

+3VS

2

1 3

D

+3VS

2

1 3

D

G

Clock Generator

U2

1

VDD_USB_48

2

VSS_48M

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

USB_48

9

VSS_27M

10

SATA

11

SATA#

12

VSS_SRC

13

SRC_1

14

SRC_1#

15

VDD_SRC_IO

16

CPU_STOP#

33

TGND

SLG8SP587VTR_QFN32_5X5

SA00003HR00 11/03 Change U2 from SA00003MF 00 to SA00002XY00 11/23 Change U2 from SA00002XY00 to SA00003HR00

R108

4.7K_0402_5%

1 2

D_CK_SDATA

S

R110

4.7K_0402_5%

1 2

D_CK_SCLK

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

+3VS

1

C132

2

Type

Standard

Low Power

SSM3K7002FU_SC70-3

2009/10/10 2010/10/10

Layout note: Place C507 close to R103

+1.5VS

11/03 Delete L3,C126,C125(@)

10/23 Delete C127, C128, C501 on +CLK_1.5VDD

R102 R103

Mount@@

Mount

+CLK_VDD

32

SCL

31

SDA

REF_0/CPU_SEL

XTAL_OUT

CKPWRGD/PD#

VDD_CPU_IO

+3VS

D

Q10

S

30 29

VDD_REF

28

XTAL_IN

27 26

VSS_REF

25

24

VDD_CPU

23

CPU_0

22

CPU_0#

21

VSS_CPU

20

CPU_1

19

CPU_1#

18 17

VDD_SRC

Realtek Have Internal Pull-Down

R105

R105 10K_0402_5%

10K_0402_5%

1 2

CK505_PWRGD

13

2

G

9/10 Change symbol o f Q29 to SC70-3

Compal Secret Data

Deciphered Date

E

R103 0_0402_5%R103 0_0402_5%

1 2

+CLK_VDDSRC

D_CK_SCLK D_CK_SDATA REF_0/CPU_SEL

CLK_XTAL_IN CLK_XTAL_OUT

CK505_PWRGD

+VDD_3V3_1V5

R106

R106 0_0402_5%

0_0402_5%

@

1 2

CLK_EN# <47>

+CLK_VDD

12

R102

@

0_0402_5%

10U_0805_10V4Z

10/23 Add C1000 on +VDD_3V3_1V5 Change C133, C134, C135 from +CLK_VDD to +VDD_3V3_1V5 11/03 Change C507 from @ to mount

R104 33_0402_5%R104 33_0402_5%

1 2

VGATE <15,47>

F

14.318MHZ_16PF_7A14300083

Place C133 close to U2.1 Place C134 close to U2.17 Place C135 close to U2.24

+VDD_3V3_1V5

1

C507

2

0.1U_0402_16V4Z

CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK#

CLK_XTAL_IN

CLK_XTAL_OUT

1

C133

2

1

C509

10P_0402_50V8J

2

1

C134

2

0.1U_0402_16V4Z

22P_0402_50V8J

Y1

22P_0402_50V8J

1 2

C135

0.1U_0402_16V4Z

D_CK_SCLK <10,11> D_CK_SDATA <10,11> CLK_BUF_ICH_14M <14>

11/04 Reserve C509(@) for CLK_BUF_ICH_14M (RF Recommend)

01/15 Add C509 (10pF)

CLK_BUF_CPU_BCLK <14> CLK_BUF_CPU_BCLK# <14>

C136

9/23 Change C495 to 22pF

12

C137

12

update PCB footprint

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Clock Generator (CK505)

NAU00 M/B LA-6101P Schematics

G

1.0

of

12 48Tuesday, March 09, 2010

H

5

+RTCVCC

1 2

R111

R111 20K_0402_1%

20K_0402_1%

PCH_RTCRST#

RC Delay 18~25mS

18P_0402_50V8J

close to RAM door

1 2

J1

@J1

@

10K_0603_5%

C139

1U_0603_10V6K

D D

+RTCVCC

close to RAM door

HDA for AUDIO

C508 15P_0402_50V8J@C508 15P_0402_50V8J@

HDA_BITCLK_AUDIO<29>

HDA_SYNC_AUDIO<29>

HDA_RST#_AUDIO<29>

C C

HDA_SDOUT_AUDIO<29>

If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door.

1 2

R115

R115 20K_0402_1%

20K_0402_1%

1 2

J2

@J2

@

10K_0603_5%

C141

1U_0603_10V6K

1 2

11/04 Reserve C508(@) for BITCLK (RF Recommend)

1 2

R116 33_0402_5%R116 33_0402_5%

R117 33_0402_5%R117 33_0402_5%

R118 33_0402_5%R118 33_0402_5%

R119 33_0402_5%R119 33_0402_5%

32.768KHZ_12.5PF_Q13MC14610002

PCH_SRTCRST#

RC Delay 18~25mS

INTVRMEN - Integrated SUS 1.1V VRM Enable High - Enable Interna l VRs

1 2

HDA_BITCLK_PCH

HDA_SYNC_PCH

HDA_RST#_PCH

HDA_SDOUT_PCH

10/5 Change R223 to 330K ohm

ME_EN#<33>

11/10 Delete Q13,R120,R121 (Follow NIWE2)

GPIO33 can not pull down (manufacturing environments)

+3VS

R126

R126 10K_0402_5%

10K_0402_5%

@

B B

1 2

R127

R127 10K_0402_5%

10K_0402_5%

PCH Pin RefDes

R138

PCH_JTAG_TDO No Install

R139

R135

PCH_JTAG_TMS No Install

A A

PCH_JTAG_TDI

PCH_JTAG_TCK

R136

R143 No Install

R144

R150

R146

PCH_JTAG_RST#

R147

10/5 Change R287 to 10K ohm

PCH_SPKR

Have internal PD

SERIRQ PCH_GPIO21

PCH JTAG Pre-Production

ES2 MPES1

No Install

200ohm

100ohm

200ohm

100ohm100ohm

200ohm

100ohm100ohm

51ohm

20Kohm

10Kohm

5

51ohm 51ohm

20Kohm

10Kohm

PCH_SPI_CLK_1

PCH_SPI_CS0#

PCH_SPI_MISO_1 PCH_SPI_MISO

PCH JTAG Production

*

No Install

3

2

18P_0402_50V8J

+RTCVCC

R113 1M_0402_5%R113 1M_0402_5%

R114 330K_0402_5%R114 330K_0402_5%

R604 1K_0402_5%@R604 1K_0402_5%@

R603 10K_0402_5%@R603 10K_0402_5%@

+3VALW

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_RST#

11/05 Change R135,R136,R138,R139,R 143,R144,R146,R147 from mount to @ (Follow NIWE2) 11/10 Delete R134(@),R137(@),R142(@),R145(@)

4

C138

12

X1

OSC

NC

OSC

NC

C140

12

1 2

HDA_SDIN0<29>

1 2

R123 0_0402_5%R123 0_0402_5%

1 2

R124 15_0402_5%R124 15_0402_5%

1 2

PCH_RTCX1

4

1

10M_0402_5%

PCH_RTCX2

PCH_SPKR<29>

9/3 Remove R738

R128 15_0402_5%R128 15_0402_5%

1 2

R130 0_0402_5%R130 0_0402_5%

1 2

10/5 Change R734 to 0 ohm

R135 200_0402_5%@R135 200_0402_5%@

1 2

R136 100_0402_5%@R136 100_0402_5%@

1 2

R138 200_0402_5%@R138 200_0402_5%@

1 2

R139 100_0402_5%@R139 100_0402_5%@

1 2

R143 200_0402_5%@R143 200_0402_5%@

1 2

R144 100_0402_5%@R144 100_0402_5%@

1 2

R146 20K_0402_5%@R146 20K_0402_5%@

1 2

R147 10K_0402_5%@R147 10K_0402_5%@

1 2

4

12

R112

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK_PCH

HDA_SYNC_PCH

PCH_SPKR

HDA_RST#_PCH

HDA_SDOUT_PCH

ME_EN#

PCH_GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_RST#

PCH_SPI_CLK

PCH_SPI_CS0#_R

PCH_SPI_MOSIPCH_SPI_MOSI_1

3

12/17 Change U3 from SA00003N7B0 to SA00003N7A0

11/30 Change U3 from SA00003N720 to SA00003N7B0

PCH : SA00003N7A0

REV1.0

LPC

RTCIHDA

SATA

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI JTAG

11/06 Change +1.05VS to +1.1VS_VTT

+3VALW

B13 D13

C14

D17

A16

A14

A30

D29

C30

G30

E32

B29

H32

BA2

AV3

AY3

AY1

AV1

P1

F30

F32

J30

M3

K3

K1

J2

J4

U3A

RTCX1 RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO1 3

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TRST#

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

IBEXPEAK-M_FCBGA107

11/09 Delete R148(@) (Follow NIWE2)

PCH_SPI_MOSI

enable iTPM: SPI_MOSI High

PCH_JTAG_TCK

LPC_AD0

LDRQ0#

SERIRQ

D33

LPC_AD1

B33

LPC_AD2

C32

LPC_AD3

A32

LPC_FRAME#

C34

A34 F34

SERIRQ

AB9

SATA_DTX_C_PRX_N0

AK7

SATA_DTX_C_PRX_P0

AK6

SATA_PTX_DRX_N0

AK11

SATA_PTX_DRX_P0

AK9

SATA_DTX_C_PRX_N1

AH6

SATA_DTX_C_PRX_P1

AH5

SATA_PTX_DRX_N1

AH9

SATA_PTX_DRX_P1

AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

SATA_DTX_C_PRX_N4

AD9

SATA_DTX_C_PRX_P4

AD8

SATA_PTX_DRX_N4

AD6

SATA_PTX_DRX_P4

AD5

SATA_DTX_C_PRX_N5

AD3

SATA_DTX_C_PRX_P5

AD1

SATA_PTX_DRX_N5

AB3

SATA_PTX_DRX_P5

AB1

AF16

AF15

T3

Y9

PCH_GPIO19

V1

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA0RXN

SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA1RXP SATA1TXN SATA1TXP

SATA2RXN

SATA2RXP SATA2TXN SATA2TXP

SATA3RXN

SATA3RXP SATA3TXN SATA3TXP

SATA4RXN

SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

R149 1K_0402_5%@R149 1K_0402_5%@

1 2

R150 51_0402_5%R150 51_0402_5%

1 2

2/10 SATA2, SATA3 not support on HM55

SATA_COMP

PCH_SATALED#_R

R122 37.4_0402_1%R122 37.4_0402_1%

R125 10K_0402_5%R125 10K_0402_5%

+3VS

2

LPC_AD0 <33> LPC_AD1 <33> LPC_AD2 <33> LPC_AD3 <33>

LPC_FRAME# <33>

SERIRQ <33>

SATA_DTX_C_PRX_N0 <25> SATA_DTX_C_PRX_P0 <25>

SATA_PTX_DRX_N0 <25> SATA_PTX_DRX_P0 <25>

SATA_DTX_C_PRX_N1 <32> SATA_DTX_C_PRX_P1 <32>

SATA_PTX_DRX_N1 <32> SATA_PTX_DRX_P1 <32>

SATA_DTX_C_PRX_N4 <31> SATA_DTX_C_PRX_P4 <31>

SATA_PTX_DRX_N4 <31> SATA_PTX_DRX_P4 <31>

SATA_DTX_C_PRX_N5 <32> SATA_DTX_C_PRX_P5 <32>

SATA_PTX_DRX_N5 <32> SATA_PTX_DRX_P5 <32>

1 2

10K_0402_5%

11/23 Change R129,R131 from @ to mount Change R132,R133 from mount to @ (Follow NIWE2)

R140 3.3K_0402_5%R140 3.3K_0402_5%

1 2

R141 3.3K_0402_5%R141 3.3K_0402_5%

1 2

11/05 Change R150 from 4.7kohm to 51ohm (Follow NIWE2)

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

2

PCH_SATALED#_R

01/21 Add U34,R652(@)

+1.1VS_VTT

11/06 Change +1.05VS to +1.1VS_VTT

+3VS

R129 10K_0402_5%R129 10K_0402_5%

R131 10K_0402_5%R131 10K_0402_5%

12

R132

@

12

R133

@

10K_0402_5%

PCH_SPI_CS0# SPI_WP1# SPI_HOLD1#

Title

Size Document Number Rev

Custom

Date: Sheet

1

R652 0_0402_5%@R652 0_0402_5%@

1 2

+3VS

5

2

P

B

4

Y

1

A

G

U34

3

NC7SZ08P5X_NL_SC70-5

SATA for HDD

SATA for SSD

SATA for eSATA

SATA for SSD

+3VS

1 2

U4

1

CS#

3

WP#

7

HOLD#

4

GND

S IC FL 32M MX25L3205DM2I-12G SOP 8P

VCC

SCLK

8 6 5

SI

2

SO

SPI ROM Footprint 150mil

Compal Electronics, Inc.

PCH (1/9) SATA,HDA,SPI, LPC

NAU00 M/B LA-6101P Schematics

13 48Tuesday, March 09, 2010

1

PCH_SATALED# <36>

+3VS

PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1

of

1.0

5

PCIE_DTX_C_PRX_N1<26>

For PCIE LAN

For Wireless LAN

D D

For New Card

PCIE_DTX_C_PRX_P1<26>

PCIE_PTX_C_DRX_N1<26> PCIE_PTX_C_DRX_P1<26>

PCIE_DTX_C_PRX_N2<32> PCIE_DTX_C_PRX_P2<32>

PCIE_PTX_C_DRX_N2<32> PCIE_PTX_C_DRX_P2<32>

PCIE_DTX_C_PRX_N3<37> PCIE_DTX_C_PRX_P3<37>

PCIE_PTX_C_DRX_N3<37> PCIE_PTX_C_DRX_P3<37>

C142 .1U_0402_16V7KC142 .1U_0402_16V7K C143 .1U_0402_16V7KC143 .1U_0402_16V7K

12 12

C144 .1U_0402_16V7KC144 .1U_0402_16V7K

12

C145 .1U_0402_16V7KC145 .1U_0402_16V7K

12

C146 .1U_0402_16V7KC146 .1U_0402_16V7K

12

C147 .1U_0402_16V7KC147 .1U_0402_16V7K

12

2/10 PCIE7, PCIE8 not support on HM55

C C

R151 0_0402_5%R151 0_0402_5%

For PCIE LAN

CLK_PCIE_LAN#<26> CLK_PCIE_LAN<26>

11/05 Delete R153

1 2 1 2

1 2

5

CLK_PCIE_MINI1#<32> CLK_PCIE_MINI1<32>

CLK_PCIE_EXP#<37> CLK_PCIE_EXP<37>

+3VS

+3VALW

For Wireless LAN

For New Card

B B

MINI1_CLKREQ# EXP_CLKREQ#

A A

9/14 Change to +3VALW(Follow CRB1.1)

PCH_GPIO25

R168 10K_0402_5%R168 10K_0402_5% R169 10K_0402_5%R169 10K_0402_5%

R177 10K_0402_5%R177 10K_0402_5%

1 2

R152 0_0402_5%R152 0_0402_5%

1 2

LAN_CLKREQ#<26>

R154 0_0402_5%R154 0_0402_5%

1 2

R155 0_0402_5%R155 0_0402_5%

1 2

MINI1_CLKREQ#<32>

R156 0_0402_5%R156 0_0402_5%

1 2

R157 0_0402_5%R157 0_0402_5%

1 2

EXP_CLKREQ#<37>

9/14 Change power net from +3V to +3VALW

EC_LID_OUT# PCH_SMBCLK PCH_SMBDATA

PCH_GPIO60

PCH_SML1CLK PCH_SML1DAT

PCH_GPIO74

PCH_GPIO26 PCH_GPIO44 PCH_GPIO56 LAN_CLKREQ#

4

PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1

PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_DTX_C_PRX_N2 PCIE_DTX_C_PRX_P2

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_DTX_C_PRX_N3 PCIE_DTX_C_PRX_P3

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

LAN_CLKREQ#

CLK_PCIE_MINI1#_R CLK_PCIE_MINI1_R

MINI1_CLKREQ#

CLK_PCIE_EXP#_R CLK_PCIE_EXP_R

EXP_CLKREQ#

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

R170 10K_0402_5%R170 10K_0402_5%

1 2

R171 2.2K_0402_5%R171 2.2K_0402_5%

1 2

R172 2.2K_0402_5%R172 2.2K_0402_5%

1 2

R173 10K_0402_5%R173 10K_0402_5%

1 2

R174 2.2K_0402_5%R174 2.2K_0402_5%

1 2

R175 2.2K_0402_5%R175 2.2K_0402_5%

1 2

R176 10K_0402_5%R176 10K_0402_5%

1 2

R178 10K_0402_5%R178 10K_0402_5%

1 2

R179 10K_0402_5%R179 10K_0402_5%

1 2

R180 10K_0402_5%R180 10K_0402_5%

1 2

R181 10K_0402_5%R181 10K_0402_5%

1 2

4

3

U3B

BG30

BJ30 BF29

BH29

AW30

BA30 BC30 BD30

AU30

AT30 AU32 AV32

BA32 BB32 BD32 BE32

BF33 BH33 BG32

BJ32

BA34

AW34

BC34 BD34

AT34 AU34 AU36 AV36

BG34

BJ34 BG36

BJ36

AK48 AK47

P9

AM43 AM45

U4

AM47 AM48

N4

AH42 AH41

A8

AM51 AM53

M9

AJ50

AJ52

H6

AK53 AK51

P13

IBEXPEAK-M_FCBGA107

+3VALW

REV1.0

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_ N

CLKOUT_DP_P / CLKOUT_BCLK1_ P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N

CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

EC_LID_OUT#

B9

PCH_SMBCLK

H14

PCH_SMBDATA

C8

PCH_GPIO60

J14

PCH_SML0CLK

C6

PCH_SML0DAT

G8

PCH_GPIO74

M14

E10

G12

T13

T11

T9

PCH_SML1CLK

PCH_SML1DAT

R625 0_0402_5%R625 0_0402_5%

R626 0_0402_5%R626 0_0402_5%

11/05 Add R625,R626, delete Q14,Q15 (Follow NIWE2)

11/02 Change R597 to pull-up resister to +3VALW on PCH_GPIO47

PCH_GPIO47

H1

AD43 AD45

AN4 AN2

AT1 AT3

10/30 Delete Net : CLK_CPU_DP,CLK_CPU_DP#

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

XCLK_RCOMP

AF38

Project Port ID

PROJECT_ID2

T45

PROJECT_ID1

P43

PROJECT_ID0

T42

PROJECT_ID3

N50

R597 10K_0402_5%R597 10K_0402_5%

R158 90.9_0402_1%R158 90.9_0402_1%

9/14 Add R374/R239/R375/R376(Pro ject ID use)

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

2

EC_LID_OUT# <33>

PCH_SMBCLK <12,32,37>

PCH_SMBDATA <12,32,37>

1 2

CLK_CPU_DMI# <5> CLK_CPU_DMI <5>

CLK_BUF_CPU_DMI# <12> CLK_BUF_CPU_DMI <12>

CLK_BUF_CPU_BCLK# <12> CLK_BUF_CPU_BCLK <12>

CLK_BUF_DREF_96M# <12> CLK_BUF_DREF_96M <12>

CLK_BUF_PCIE_SATA# <12> CLK_BUF_PCIE_SATA <12>

CLK_BUF_ICH_14M <12>

CLK_PCI_FB <17>

EC_SMB_CK2

EC_SMB_DA2

11/06 Change +1.05VS to +1.1VS_VTT

1 2

R160 10K_0402_5%@R160 10K_0402_5%@

1 2 1 2

R162 10K_0402_5%@R162 10K_0402_5%@

1 2 1 2

R164 10K_0402_5%@R164 10K_0402_5%@

1 2

R165 10K_0402_5%R165 10K_0402_5%

1 2

R166 10K_0402_5%@R166 10K_0402_5%@

1 2 1 2

10K_0402_5%R161 10K_0402_5%R161

10K_0402_5%R163 10K_0402_5%R163

10K_0402_5%R167 10K_0402_5%R167

2

1

+3VALW

PCH_SML0CLK

PCH_SML0DAT

R622 2.2K_0402_5%R622 2.2K_0402_5%

1 2

R623 2.2K_0402_5%R623 2.2K_0402_5%

1 2

11/02 Add R621,R622 pull-up 2.2kohm to +3VALW (Follow NIWE2)

EC_SMB_CK2 <33>

EC_SMB_DA2 <33>

+3VALW

C148

C148 27P_0402_50V8J

27P_0402_50V8J

1 2

+3VS

+1.1VS_VTT

Title

Size Document Number Rev

Custom

Date: Sheet

12

R159

1M_0402_5%

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

NAU00 M/B LA-6101P Schematics

Y2

Y2 25MHZ_20PF_7A25000012

25MHZ_20PF_7A25000012

1 2

C149

C149 27P_0402_50V8J

27P_0402_50V8J

1

of

14 48Tuesday, March 09, 2010

1.0

5

DMI_HTX_PRX_N[0..3]<4>

DMI_HTX_PRX_P[0..3]<4>

DMI_PTX_HRX_N[0..3]<4>

DMI_PTX_HRX_P[0..3]<4>

DMI_HTX_PRX_N[0..3]

DMI_HTX_PRX_P[0..3]

DMI_PTX_HRX_N[0..3]

DMI_PTX_HRX_P[0..3]

4

3

2

1

D D

+3VS

R182 8.2K_0402_5%R182 8.2K_0402_5%

R183 10K_0402_5%R183 10K_0402_5%

10/30 Change R183 from mount to @ (Follow NCQD0) 11/25 Change R183 from @ to mount (Follow NIWE2)

+3VALW

R184 10K_0402_5%R184 10K_0402_5%

R186 8.2K_0402_5%R186 8.2K_0402_5%

C C

R187 10K_0402_5%R187 10K_0402_5%

R188 10K_0402_5%R188 10K_0402_5%

R189 10K_0402_5%

H_FDI_TXN[0..7]<4>

H_FDI_TXP[0..7]<4>

1 2

9/14 Change power net from +3V to +3VALW

1 2

@

1 2

PM_CLKRUN#

PCH_SYS_RESET#

SUS_PWR_ACK_R

PCH_GPIO72

RI#

PCH_PCIE_WAKE#

PM_SLP_LAN#

XDP_DBRESET#<5>

11/05 Add R627(@) (Follow NIWE2)

B B

SUS_PWR_ACK<33>

11/03 Change R193 from 100kohm to 10kohm (Follow Intel and NIWE2)

+3VALW

AC_PRESENT<33>

11/03 Delete D1, add R624

11/05 Delete the off page : EC_SWI# from PCH to EC, change net from EC_SWI# to RI# (Follow NIWE2)

SYS_PWROK

A A

5

H_FDI_TXN[0..7]

H_FDI_TXP[0..7]

+1.1VS_VTT

DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3

DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3

DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3

DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2

11/06 Change +1.05VS to +1.1VS_VTT

R185

49.9_0402_1%

1 2

DMI_PTX_HRX_P3

DMI_COMP

BC24

BJ22

AW20

BJ20

BD24 BG22 BA20 BG20

BE22

BF21 BD20 BE18

BD22 BH21 BC20 BD18

BH25

BF25

U3C

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

REV1.0

10/22 Change R188 from 1kohm to 10kohm (Follow checklist)

10/22 Reserve R612(@) between PCH_SYS_RESET# and XDP_DBRESET# Chanfe R183 from @ to mount 10/30 Change R612 from @ to mount (Follow NCQD0)

R612 0_0402_5%R612 0_0402_5%

SYS_PWROK VGATE

R190 0_0402_5%R190 0_0402_5% R191 0_0402_5%@R191 0_0402_5%@

SYS_PWROK

R627 0_0402_5%@R627 0_0402_5%@

R193 10K_0402_5%R193 10K_0402_5%

1 2

R624 0_0402_5%R624 0_0402_5%

1 2

PM_DRAM_PWRGD<5>

1 2

12

12 12

PBTN_OUT#<33>

11/09 Add R629(@)

R629 0_0402_5%@R629 0_0402_5%@

1 2

+3VS

5

U5

2

P

B

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

SYS_PWROK

EC_PWROK

LAN_RST#

No used Integrated LAN, connecting LAN_RST# to GND

1 2

R198 10K_0402_5%R198 10K_0402_5%

1 2

R199 10K_0402_5%R199 10K_0402_5%

1 2

R200 10K_0402_5%R200 10K_0402_5%

PCH_SYS_RESET#

SYS_PWROK_R

12

R192 0_0402_5%R192 0_0402_5%

LAN_RST#

PCH_RSMRST#

SUS_PWR_ACK_R

PBTN_OUT#

PCH_ACIN

PCH_GPIO72

RI#

EC_PWROK

VGATE

ME_PWROK

EC_PWROK <33>

VGATE <12,47>

4

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPI O30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA107

BA18

FDI_RXN0

BH17

FDI_RXN1

BD16

FDI_RXN2

BJ16

FDI_RXN3

BA16

FDI_RXN4

BE14

FDI_RXN5

BA14

FDI_RXN6

BC12

FDI_RXN7

BB18

FDI_RXP0

BF17

FDI_RXP1

BC16

FDI_RXP2

BG16

FDI_RXP3

AW16

FDI_RXP4

BD14

FDI_RXP5

BB14

FDI_RXP6

BD12

FDI_RXP7

BJ14

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

PCH_PCIE_WAKE#

PM_CLKRUN#

PCH_GPIO61

PCH_GPIO62

PM_SLP_M#

PM_SLP_DSW#

PM_SLP_LAN#

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7

H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7

@

PAD

@

PAD

PM_SLP_S5# <33>

PM_SLP_S4# <33>

PM_SLP_S3# <33>

@

PAD

@

PAD

H_PM_SYNC <5>

H_FDI_INT <4>

H_FDI_FSYNC0 <4>

H_FDI_FSYNC1 <4>

H_FDI_LSYNC0 <4>

H_FDI_LSYNC1 <4>

PCH_PCIE_WAKE# <26,32,37>

PM_CLKRUN# <33>

T6

T7

T8

T9

9/14 Change PN of D14B from SC6V99DW000 to SC6V99DW010

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

2

R194 0_0402_5%@R194 0_0402_5%@

PCH_RSMRST#

R195

R195 10K_0402_5%

10K_0402_5%

12

Title

Size Document Number Rev

Custom

Date: Sheet

12

Q16

Q16 MMBT3906_SOT23-3

MMBT3906_SOT23-3

123

C

E

B

1 2

R196 4.7K_0402_5%R196 4.7K_0402_5%

D2A

1

2

BAV99DW-7-F_SOT363~N

D2B

4

5

BAV99DW-7-F_SOT363~N

Compal Electronics, Inc.

PCH (3/9) DMI, FDI, PM

NAU00 M/B LA-6101P Schematics

EC_RSMRST# <33>

+3VALW

9/14 Change power net from +3V to +3VALW

6

11/05 Change D3B to D2B

3

12

R197

2.2K_0402_5%

1

1.0

of

15 48Tuesday, March 09, 2010

5

ENBKL<33>

D D

R202 100K_0402_5%R202 100K_0402_5%

1 2

ENBKL

IGPU_BKLT_EN

10/5 Change R163 to 2.37K oh m(Follow CRB & DG2.0)

+3VS

C229

PCH_CRT_B

PCH_CRT_G

PCH_CRT_R

LCTLA_CLK

LCTLB_DATA

PCH_CRT_CLK

PCH_CRT_DATA

1

C230

2

12P_0402_50V8J

1

C231

2

12P_0402_50V8J

R205 10K_0402_5%R205 10K_0402_5%

1 2

R206 10K_0402_5%R206 10K_0402_5%

C C

R209 150_0402_1%R209 150_0402_1%

R210 150_0402_1%R210 150_0402_1%

R211 150_0402_1%R211 150_0402_1%

B B

1 2

R207 2.2K_0402_5%R207 2.2K_0402_5%

1 2

R208 2.2K_0402_5%R208 2.2K_0402_5%

1 2

12P_0402_50V8J

10/29 Move C229,C230,C231 close to U3 (EMI Recommend)

4

R2130_0402_5% R2130_0402_5%

12

PCH_ENVDD<22>

DPST_PWM<22>

PCH_LCD_CLK<22> PCH_LCD_DATA<22>

11/09 Delete R203

PCH_TXCLK-<22> PCH_TXCLK+<22>

PCH_TXOUT0-<22> PCH_TXOUT1-<22> PCH_TXOUT2-<22>

PCH_TXOUT0+<22> PCH_TXOUT1+<22> PCH_TXOUT2+<22>

PCH_CRT_B<23> PCH_CRT_G<23> PCH_CRT_R<23>

PCH_CRT_CLK<23> PCH_CRT_DATA<23>

PCH_CRT_HSYNC<23> PCH_CRT_VSYNC<23>

R201

1 2

2.37K_0402_1%

3

U3D

IGPU_BKLT_EN

PCH_LCD_CLK PCH_LCD_DATA

LCTLA_CLK LCTLB_DATA

LVDS_IBG

PCH_TXCLKPCH_TXCLK+

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+

PCH_CRT_B PCH_CRT_G PCH_CRT_R

PCH_CRT_CLK PCH_CRT_DATA

CRT_IREF

12

R212

R212 1K_0402_0.5%

1K_0402_0.5%

2/3 Change to 1K_0402_0.5% from Intel Suggestion. (EDS 1.0 is incorrect)

U3D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M_FCBGA107

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

CRT

REV1.0

PCH_DPB_HPD

PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3

2

R204 100K_0402_5%R204 100K_0402_5%

1 2

C150 .1U_0402_16V7KC150 .1U_0402_16V7K

12

C151 .1U_0402_16V7KC151 .1U_0402_16V7K

12

C152 .1U_0402_16V7KC152 .1U_0402_16V7K

12

C153 .1U_0402_16V7KC153 .1U_0402_16V7K

12

C154 .1U_0402_16V7KC154 .1U_0402_16V7K

12

C155 .1U_0402_16V7KC155 .1U_0402_16V7K

12

C156 .1U_0402_16V7KC156 .1U_0402_16V7K

12

C157 .1U_0402_16V7KC157 .1U_0402_16V7K

12

1

SDVO_SCLK <24> SDVO_SDATA <24>

PCH_DPB_HPD <24>

PCH_TMDS_D2# <24> PCH_TMDS_D2 <24> PCH_TMDS_D1# <24> PCH_TMDS_D1 <24> PCH_TMDS_D0# <24> PCH_TMDS_D0 <24> PCH_TMDS_CK# <24> PCH_TMDS_CK <24>

HDMI D2

HDMI D1

HDMI D0

HDMI CLK

A A

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (4/9) LVDS, CRT, DPI

NAU00 M/B LA-6101P Schematics

1

of

16 48Tuesday, March 09, 2010

1.0

5

+3VS

R218 8.2K_0402_5%R218 8.2K_0402_5%

1 2

R214 8.2K_0402_5%R214 8.2K_0402_5%

1 2

R215 8.2K_0402_5%R215 8.2K_0402_5%

1 2

R220 8.2K_0402_5%R220 8.2K_0402_5%

1 2

D D

C C

B B

R222 8.2K_0402_5%R222 8.2K_0402_5%

1 2

R223 8.2K_0402_5%R223 8.2K_0402_5%

1 2

R216 8.2K_0402_5%R216 8.2K_0402_5%

1 2

R224 8.2K_0402_5%R224 8.2K_0402_5%

1 2

R217 8.2K_0402_5%R217 8.2K_0402_5%

1 2

R226 8.2K_0402_5%R226 8.2K_0402_5%

1 2

R227 8.2K_0402_5%R227 8.2K_0402_5%

1 2

R228 8.2K_0402_5%R228 8.2K_0402_5%

1 2

R229 8.2K_0402_5%R229 8.2K_0402_5%

1 2

R230 8.2K_0402_5%R230 8.2K_0402_5%

1 2

R231 8.2K_0402_5%R231 8.2K_0402_5%

1 2

R232 8.2K_0402_5%R232 8.2K_0402_5%

1 2

R233 8.2K_0402_5%R233 8.2K_0402_5%

1 2

R234 8.2K_0402_5%R234 8.2K_0402_5%

1 2

R235 8.2K_0402_5%R235 8.2K_0402_5%

1 2

R236 8.2K_0402_5%R236 8.2K_0402_5%

1 2

CLK_PCI_LPC<33> CLK_PCI_FB<14>

PCI_PIRQA# PCI_PIRQG# PCI_PIRQC# PCI_SERR#

PCI_PLOCK# PCI_PERR# PCI_PIRQE# PCI_STOP#

PCI_REQ0# PCI_PIRQB# PCI_PIRQF# PCI_REQ3#

PCI_ IRDY# PCI_PIRQD# PCI_REQ2# PCI_DEVSEL#

PCI_FRAME# PCI_REQ1# PCI_PIRQH# PCI_TRDY#

PAD

T14

PCI_PME#<33>

PLT_RST#<5,33>

R242 22_0402_5%R242 22_0402_5%

1 2

R243 22_0402_5%R243 22_0402_5%

1 2

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#

PCI_GNT0# PCI_GNT1#

@

PCI_GNT2# PCI_GNT3#

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

PCI_SERR# PCI_PERR#

PCI_ IRDY#

PCI_DEVSEL# PCI_FRAME#

PCI_PLOCK#

PCI_STOP# PCI_TRDY#

PCI_PME#

PLT_RST#

CLK_PCI_LPC_R CLK_PCI_FB_R

2008/1/6 2009MOW01 change to 22 ohm

Boot BIOS Strap

PCI_GNT#0 PCI_GNT#1 Boot BIOS Location

00

A A

01

10

11

*

A16 swap override Strap/Top-Block

Swap Override jumper

PCI_GNT#3

Low = A16 swap High = Default

5

LPC

Reserved (NAND)

PCI

SPI

Have internal PU

PCI_GNT0#

PCI_GNT1#

PCI_GNT3#

4

U3E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M_FCBGA107

R245 1K_0402_5%@R245 1K_0402_5%@

1 2

R248 1K_0402_5%@R248 1K_0402_5%@

1 2

R250 1K_0402_5%@R250 1K_0402_5%@

1 2

4

REV1.0

3

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

BD3 AY6

AU2

AV7

AY8 AY5

AV11 BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

B25

D25

N16 J16 F16 L16 E14 G16 F12 T15

9/4 NC

NV_ALE NV_CLE

9/4 NC

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB20_N5 USB20_P5

USB20_N0 <31> USB20_P0 <31> USB20_N1 <31> USB20_P1 <31> USB20_N2 <22> USB20_P2 <22> USB20_N3 <31> USB20_P3 <31>

USB20_N5 <28> USB20_P5 <28>

USB Conn.(HS) JUSB1

eSATA USB Conn.

CMOS Camera (LVDS)

USB Conn.(HS) JUSB2

CardReader

Note: USB6,USB7 not support on HM55

USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11

USB20_N13 USB20_P13

USB_BIAS

USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R

2009/10/10 2010/10/10

3

USB20_N8 <32> USB20_P8 <32> USB20_N9 <36> USB20_P9 <36> USB20_N10 <37> USB20_P10 <37> USB20_N11 <35> USB20_P11 <35>

USB20_N13 <32> USB20_P13 <32>

1 2

R237

22.6_0402_1%

Mini Card(WLAN)

Fingerprint

New Card

Bluetooth

Mini Card(3G)

11/09 Delete R238,R601

USB_OC#0 <31> USB_OC#1 <31>

Compal Secret Data

(For USB Port0) (For eSATA USB Port1) (For USB Port3)

Deciphered Date

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_ALE NV_CLE

NV_RCOMP

PCI

NV_RB#

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USB

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

NV_ALE

R219 1K_0402_5%@R219 1K_0402_5%@

NV_CLE

PLT_RST#

NC7SZ08P5X_NL_SC70-5

1 2

R221 1K_0402_5%@R221 1K_0402_5%@

1 2

R628 0_0402_5%R628 0_0402_5%

1 2

+3VS

U6

@U6

@

2

B

1

A

12/04 Change U6 from mount to @

EHCI 1

EHCI 2

USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R

2

R598 10K_0402_5%R598 10K_0402_5% R599 10K_0402_5%R599 10K_0402_5% R600 10K_0402_5%R600 10K_0402_5% R244 10K_0402_5%R244 10K_0402_5% R247 10K_0402_5%R247 10K_0402_5% R249 10K_0402_5%R249 10K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

1

+VCCQ_NAND

11/09 Add R628(@)

12/04 Change R628 from @ to

5

P

4

Y

G

3

mount

12

R225

R225 100K_0402_5%

100K_0402_5%

PLT_RST_BUF# <26,32,37>

Danbury Technology Enabled

NV_ALE

High = Enabled

Low = Disabled

DMI Termination Voltage

NV_CLE

OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2

NAU00 M/B LA-6101P Schematics

Set to Vss when LOW

Set to Vcc when HIGH

9/14 Change power net from +3V to +3VALW

12 12 12 12 12 12

Compal Electronics, Inc.

PCH (5/9) PCI, USB, VRAM

+3VALW

1

17 48Tuesday, March 09, 2010

1.0

of

5

4

3

2

1

+3VS

R277 10K_0402_5%R277 10K_0402_5% R251 10K_0402_5%R251 10K_0402_5% R252 10K_0402_5%R252 10K_0402_5% R253 10K_0402_5%R253 10K_0402_5%

D D

C C

R254 10K_0402_5%R254 10K_0402_5% R263 10K_0402_5%R263 10K_0402_5% R255 10K_0402_5%R255 10K_0402_5% R264 10K_0402_5%R264 10K_0402_5% R256 10K_0402_5%R256 10K_0402_5% R257 10K_0402_5%R257 10K_0402_5% R258 10K_0402_5%R258 10K_0402_5%

R260 10K_0402_5%R260 10K_0402_5% R261 10K_0402_5%@R261 10K_0402_5%@

+3VALW

11/25 Change R261,R266 from mount to @ (Follow NIWE2)

R262 10K_0402_5%R262 10K_0402_5%

R266 10K_0402_5%@R266 10K_0402_5%@

R267 1K_0402_5%R267 1K_0402_5%

R270 10K_0402_5%R270 10K_0402_5% R271 10K_0402_5%R271 10K_0402_5% R272 10K_0402_5%R272 10K_0402_5% R273 10K_0402_5%R273 10K_0402_5%

9/14 Change power net from +3V to +3VALW

1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2 1 2 1 2

12

11/09 Delete R274(@),R276(@)

R275 10K_0402_5%R275 10K_0402_5%

1 2

PCH_GPIO0 PCH_GPIO1 PCH_GPIO6 PCH_GPIO16

PCH_GPIO22 PCH_GPIO38 PCH_GPIO39 PCH_GPIO36 PCH_GPIO37 PCH_GPIO48 PCH_TEMP_ALERT#

PCH_GPIO34 EC_SCI#

PCH_GPIO57

EC_SMI#

PCH_GPIO15

PCH_GPIO28 CP_PE# RST_GATE PCH_GPIO45

PCH_GPIO35

EC_SCI#<33>

EC_SMI#<33>

CP_PE#<37>

@

PAD

T19

@

PAD

T13

RST_GATE<10>

PCH_TEMP_ALERT#<33>

Schematics check list 2.0

B B

PCH_GPIO0

PCH_GPIO1

PCH_GPIO6

EC_SCI#

EC_SMI#

CP_PE#

PCH_GPIO15

PCH_GPIO16

PCH_GPIO17

PCH_GPIO22

(Rev:1.0 GPIO24 Only)

PCH_GPIO27

PCH_GPIO28

PCH_GPIO34

PCH_GPIO35

PCH_GPIO36

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO45

RST_GATE

PCH_GPIO48

PCH_TEMP_ALERT#

PCH_GPIO57

U3F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

(GPIO8 Should not be Pull-Low)

K9

LAN_PHY_PWR_CTRL / G PIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_FCBGA107

GPIO

NCTF

RSVD

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

CLKOUT_BCLK0_N / CLKOUT_P CIE8N

CLKOUT_BCLK0_P / CLKOUT_ PCIE8P

CPU

REV1.0

CLKOUT_PCIE7P

A20GATE

PROCPWRGD

THRMTRIP#

INIT3_3V#

PECI

RCIN#

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

TP24

AH45 AH46

AF48 AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

AW22

BB22

AY45

AY46

AV43

AV45

AF13

M18

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

EC_GA20

EC_KBRST#

TP24_SST

EC_GA20 <33>

CLK_CPU_BCLK# <5>

CLK_CPU_BCLK <5>

H_PECI <5>

EC_KBRST# <33>

H_CPUPWRGD <5>

R268 56_0402_5%R268 56_0402_5%

WW46 Platform/Design Updates 2008/11/17 54.9 1% ->56 5%

@

PAD

T10

+3VS

EC_GA20

R265 10K_0402_5%R265 10K_0402_5%

EC_KBRST#

12

H_THERMTRIP#THRMTRIP_PCH#

12

R269 56_0402_5%R269 56_0402_5%

1 2

R259 10K_0402_5%R259 10K_0402_5%

1 2

H_THERMTRIP# <5>

+1.1VS_VTT

A A

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (6/9) GPIO, CPU, MISC

NAU00 M/B LA-6101P Schematics

1

of

18 48Tuesday, March 09, 2010

1.0

5

4

3

2

CRB 0.9 is 180 ohm @ 100MHz DG0.8 is 600 ohm FB (Page 290)

1

R649

1_0603_5%

+3VS

+1.8VS

11/06 Change +1.05VS to +1.1VS_VTT

D D

All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails

C C

B B

Intel suggest follow CRB 8/21

+1.1VS_VTT

10U_0805_10V4Z

C168

Top Side

11/06 Change +1.05VS to +1.1VS_VTT

Near AN20

1

2

1

C169

2

1U_0402_6.3V4Z

Follow Intel suggestion 8/21

1U_0402_6.3V4Z

C170

+1.1VS_VTT

10U_0805_10V4Z

1

C158

2

Near AB24 Top Side

11/09 Delete L6(@),C166(@)

1

2

1

C171

2

1U_0402_6.3V4Z

Near AN35

0.1U_0402_16V4Z

C175

11/09 Delete L7(@),C176(@)

U3G

1U_0402_6.3V4Z

C159

1U_0402_6.3V4Z

C172

12

+VCCVRM

+1.1VS_VTT

1

2

+1.1VS_VTT

1

2

+3VS

U3G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

42mA

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IBEXPEAK-M_FCBGA107

11/06 Change +1.05VS to +1.1VS_VTT

POWER

1524mA

3208mA

6mA

69mA

CRTLVDS

VCC CORE

HVCMOS

DMI

PCI E*

NAND / SPI

FDI

REV1.0

VCCADAC[1]

VCCADAC[2]

VSSA_DAC[1]

VSSA_DAC[2]

300mA

VCCALVDS

VSSA_LVDS

59mA

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCC3_3[2]

VCC3_3[3]

VCC3_3[4]

35mA

VCCVRM[2]

61mA

VCCDMI[1]

VCCDMI[2]

156mA

VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]

85mA

VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]

AE50

AE52

AF53

AF51

AH38

AH39

AP43 AP45 AT46 AT45

AB34

AB35

AD35

AT24

AT16

AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

+VCCADAC

1

C160

0.01U_0402_16V7K

2

11/09 Delete R278(@)

+VCCA_LVDS

+VCCTX_LVDS

C163

0.01U_0402_16V7K

1

C167

0.1U_0402_16V4Z

2

+VCCVRM

C173

C173 1U_0402_6.3V4Z

1U_0402_6.3V4Z

Near AP43

1

2

+3VS

Near AB34

R282 0_0402_5%R282 0_0402_5%

+VCC_DMI

1

2

Near AT16

1

C174

0.1U_0402_16V4Z

2

Near AK13

+3VS

1

C177

0.1U_0402_16V4Z

2

Near AM8

60mA

1

C161

0.1U_0402_16V4Z

2

Near AE50Near AB24

R279 0_0603_5%R279 0_0603_5%

11/09 Change R279 from 0_0805 to 0_0603

C165

1

22U_0805_6.3V6M

C164

0.01U_0402_16V7K

1 2

22U_0805_6.3V6M

2

R283 0_0402_5%R283 0_0402_5%

1 2

11/06 Delete R284(@)

R285 0_0402_5%R285 0_0402_5%

1 2

C162

22U_0805_6.3V6M

1 2

1

2

1

C551

@

22U_0805_6.3V6M

2

+3VS

L5

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

1 2

1

2

01/18 Change L4 (SM010005500) to R649 (SD013100B80) 01/18 Change C162 from 10uF to 22uF 01/19 Add C551(@)

12

Change R280,R281,R282 from 0805 to 0603 (Layout Request)

11/06 Change +1.05VS to +1.1VS_VTT

11/09 Delete R280(@),R281(@)

11/09 Change R282 from 0_0603 to 0_0402

+1.8VS

+1.1VS_VTT

11/09 Change R283 from 0_0805 to 0_0402

+1.8VS+VCCQ_NAND

11/09 Change R285 from 0_0805 to 0_0402

A A

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (7/9) PWR

NAU00 M/B LA-6101P Schematics

1

of

19 48Friday, February 26, 2010

1.0

5

11/09 Delete L8(@),C178(@),C179(@)

11/09 Delete R286(@),C190(@)

12

R287

D D

R287

0_0402_5%

11/06 Change +1.05VS to +1.1VS_VTT

+1.1VS_VTT

22U_0805_6.3V6M

1

C192

2

22U_0805_6.3V6M

All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails

1

C186

2

1U_0402_6.3V4Z

Near AD38 Near V39

1U_0402_6.3V4Z

Follow Intel suggestion

1

C193

2

C187

C187 22U_0805_6.3V6M

22U_0805_6.3V6M

Near V9

C C

11/06 Change +1.05VS to +1.1VS_VTT

1U_0402_6.3V4Z

Near AH35

B B

A A

9/14 Change power net from +3V to +3VALW

5

+1.1VS_VTT

1

C198

2

+1.1VS_VTT

C210

4.7U_0603_6.3V6K

+RTCVCC

1U_0402_6.3V4Z

1

C199

2

1U_0402_6.3V4Z

+3VALW

0.1U_0402_16V4Z

+3VS

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

C214

2

C211

C215

0.1U_0402_16V4Z

4

+PCH_VCCD6W

1

C183

0.1U_0402_16V4Z

2

1

C188

2

1U_0402_6.3V4Z

C194

0.1U_0402_16V4Z

1 2

+VCCVRM

+VCCADPLLA

+VCCADPLLB

Near AH23Near AF32

1

C200

C200 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1 2

C202

0.1U_0402_16V4Z

1 2

C205

0.1U_0402_16V4Z

1

C206

2

Near P18

1

C208

2

Near V15

1

C212

0.1U_0402_16V4Z

2

1

C216

0.1U_0402_16V4Z

2

4

Near Y20

1

2

+VCCRTCEXT

+VCCSST

Near V12

+VCCSUS

Near Y22

1

2

Near AT18

1

2

Near A12

3

POWER

U3J

AP51

VCCACLK[1]

AP53

VCCACLK[2]

344mA

AF23

VCCLAN[1]

AF24

VCCLAN[2]

Y20

DCPSUSBYP

1998mA

AD38

VCCME[1]

AD39

VCCME[2]

AD41

VCCME[3]

AF43

VCCME[4]

AF41

VCCME[5]

AF42

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

AU24

VCCVRM[3]

72mA

BB51

VCCADPLLA[1]

BB53

VCCADPLLA[2]

73mA

BD51

VCCADPLLB[1]

BD53

VCCADPLLB[2]

AH23

VCCIO[21]

AJ35

VCCIO[22]

AH35

VCCIO[23]

AF34

VCCIO[2]

AH34

VCCIO[3]

AF32

VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

> 1mA

AT18

V_CPU_IO[1]

AU18

V_CPU_IO[2]

2mA

A12

VCCRTC

IBEXPEAK-M_FCBGA107

POWER

REV1.0

52mA

VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8]

VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13]

USB

VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

163mA

VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]

VCCSUS3_3[28]

>1mA

V5REF_SUS

Clock and Miscellaneous

PCI/GPIO/LPC

SATA

PCI/GPIO/LPC

CPU

RTC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDA

VCC3_3[10]

VCC3_3[11]

VCC3_3[12]

VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1] VCCSATAPLL[2]

VCCVRM[4]

VCCSUSHDA

3

V24

VCCIO[5]

V26

VCCIO[6]

Y24

VCCIO[7]

Y26

VCCIO[8]

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23

V23

VCCIO[56]

F24

>1mA

K49

V5REF

357mA

J38

VCC3_3[8]

L38

VCC3_3[9]

M36

N36

P36

U35

AD13

32mA

AK3 AK1

AH22

VCCIO[9]

AT20

AH19

VCCIO[10]

AD20

VCCIO[11]

AF22

VCCIO[12]

AD19

VCCIO[13]

AF20

VCCIO[14]

AF19

VCCIO[15]

AH20

VCCIO[16]

AB19

VCCIO[17]

AB20

VCCIO[18]

AB22

VCCIO[19]

AD22

VCCIO[20]

AA34

VCCME[13]

Y34

VCCME[14]

Y35

VCCME[15]

AA35

VCCME[16]

6mA

L30

2009/10/10 2010/10/10

Near V24

Near A26

+1.1VS_VTT

+VCC5REFSUS

+VCC5REF

Near J38

11/09 Delete L11(@),C203(@),C204(@)

PCH_VCCME13 PCH_VCCME14 PCH_VCCME15 PCH_VCCME16

+VCCSUSHDA

Compal Secret Data

1

C189

C189 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

0.1U_0402_16V4Z

1

C180

2

+3VALW

21

D4

D4 RB751V-40_SOD323-2

RB751V-40_SOD323-2

9/14 Follow CRB1.1 Change to 10 ohm

1 2

C195

12

0.1U_0402_16V4Z

Near F24

Change to 1U for power sequence issue on ICH9

+3VS

1

C197

0.1U_0402_16V4Z

2

1 2

+1.1VS_VTT

11/06 Change +1.05VS to +1.1VS_VTT

+VCCVRM

+1.1VS_VTT

1

C207

C207 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

Near AB19

11/09 Change R292,R293,R294,R295 from 0_0603 to 0_0402

R292 0_0402_5%R292 0_0402_5% R293 0_0402_5%R293 0_0402_5% R294 0_0402_5%R294 0_0402_5% R295 0_0402_5%R295 0_0402_5%

R593 0_0402_5%R593 0_0402_5%

1 2

R594 0_0402_5%@R594 0_0402_5%@

1 2

C213 1U_0402_6.3V4ZC213 1U_0402_6.3V4Z

1 2

Deciphered Date

2

+1.1VS_VTT

9/14 Change power net from +3V to +3VALW

11/06 Change +1.05VS to +1.1VS_VTT

+1.1VS_VTT

+3VALW

1

C181

0.1U_0402_16V4Z

2

Near U23

12/27 Change D4,D5 from SC1H751H010 to SCS00000Z00

+3VS

21

12

R289

+5VALW

10_0402_5%

9/14 Follow CRB1.1 Change to 0.1uF

Near K49

+3VS

Near AD13

C201

0.1U_0402_16V4Z

11/06 Change +1.05VS to +1.1VS_VTT

+1.1VS_VTT

1 2 1 2 1 2 1 2

+3VALW +1.5V

11/09 Change R593,R594 from 0_0603 to 0_0402

Near L30

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

1

L9

1 2

10UH_LB2012T100MR_20%

10uH inductor, 120mA

C182

220U_B2_2.5VM_R35

L10

1 2

10UH_LB2012T100MR_20%

10uH inductor, 120mA

C184

220U_B2_2.5VM_R35

D5

D5 RB751V-40_SOD323-2

RB751V-40_SOD323-2

R290

10_0402_5%

1 2

C196

C196 1U_0402_6.3V6K

1U_0402_6.3V6K

Custom

10_0402_5%

Compal Electronics, Inc.

PCH (8/9) PWR

NAU00 M/B LA-6101P Schematics

Near BB51

1

+

C191

C191 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1

+

C185

C185 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

9/14 Follow CRB1.1 Change to 10 ohm

+5VS

1

2

1

2

Near BD51

20 48Friday, February 26, 2010

+VCCADPLLA

R288

12

0_0402_5%

@

+VCCADPLLB

of

1.0

5

U3I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

VSS[168]

B7

VSS[169]

D D

C C

B B

A A

BG12

VSS[170]

BB12

VSS[171]

BB16

VSS[172]

BB20

VSS[173]

BB24

VSS[174]

BB30

VSS[175]

BB34

VSS[176]

BB38

VSS[177]

BB42

VSS[178]

BB49

VSS[179]

BB5

VSS[180]

BC10

VSS[181]

BC14

VSS[182]

BC18

VSS[183]

BC2

VSS[184]

BC22

VSS[185]

BC32

VSS[186]

BC36

VSS[187]

BC40

VSS[188]

BC44

VSS[189]

BC52

VSS[190]

BH9

VSS[191]

BD48

VSS[192]

BD49

VSS[193]

BD5

VSS[194]

BE12

VSS[195]

BE16

VSS[196]

BE20

VSS[197]

BE24

VSS[198]

BE30

VSS[199]

BE34

VSS[200]

BE38

VSS[201]

BE42

VSS[202]

BE46

VSS[203]

BE48

VSS[204]

BE50

VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]

BF49

VSS[209]

BF51

VSS[210]

BG18

VSS[211]

BG24

VSS[212]

BG4

VSS[213]

BG50

VSS[214]

BH11

VSS[215]

BH15

VSS[216]

BH19

VSS[217]

BH23

VSS[218]

BH31

VSS[219]

BH35

VSS[220]

BH39

VSS[221]

BH43

VSS[222]

BH47

VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]

AF39

VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

IBEXPEAK-M_FCBGA107

REV1.0

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

9/14 Change PN of U60 from S A00002KV0L to SA00003NI20

5

4

U3H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBEXPEAK-M_FCBGA107

REV1.0

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

9/14 Change PN of U60 from S A00002KV0L to SA00003NI20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

3

Compal Secret Data

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (9/9) VSS & PCH XDP Port

NAU00 M/B LA-6101P Schematics

1

1.0

of

21 48Friday, February 26, 2010

1

5

+LCDVDD

R296

300_0603_5%

Q1A

D D

PCH_ENVDD

11/16 Reserve C533 for avoiding switching noise 11/23 Change C533 from @ to mount

Q1A

2N7002DW-T/R7_SOT363-6

PCH_ENVDD<16>

100K_0402_5%

C533 100P_0402_50V8JC533 100P_0402_50V8J

1 2

LCD POWER CIRCUIT

+3VALW

9/14 Change power net from +3V

12

61

2

12

R301

to +3VALW

12

R297

R297 100K_0402_5%

100K_0402_5%

LVDS_OE#

3

5

Q1B

4

2N7002DW-T/R7_SOT363-6

01/15 Change Q1 from SB00000AR00 to SB00000D900

03/05 Change Q1,Q2 from SB00000D900 to SB00000DH00 (MFG Recommend)

11/09 Change C218 from 0.047uf to 0.1uF Change R299 from 1kohm to 100kohm Change C219 from mount to @ (Follow KHLBX)

R299

12

100K_0402_5%

C218

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

+3VS

G

2

1

2

C219

@

4

W=60mils

1

C217

4.7U_0603_6.3V6K

2

S

Q18

Q18 AO3413_SOT23-3

AO3413_SOT23-3

D

1 3

+LCDVDD

W=60mils

12/05 Change Q18 from SB934130000 to SB923010020

1

C220

0.1U_0402_16V4Z

2

11/10 Change U7 from @ to mount

12/31 Change U7,R302 from mount to @ Change R298,R300 from @ to mount

NC7SZ14P5X_NL_SC70-5

01/07 Change Q18 from SB923010020 to SB934130000

DPST_PWM<16>

INVT_PW M<33>

11/09 Change U7,R298 from mount to @ Change R302 from @ to mount

3

+3VS

U7

1

5

@

P

NC

4

A2Y

G

3

1 2

R300 0_0402_5%R300 0_0402_5%

INVT_PW M INVTPWM

@

1 2

R302 0_0402_5%

INVTPWMDPST_PWM_1

1 2

R298 0_0402_5%R298 0_0402_5%

12

R303

R303 10K_0402_5%

10K_0402_5%

@

2

1

CH3

Vp

CH4

2

3

11/10 Delete R305

PCH_LCD_CLK

PCH_LCD_DATA

<EMI>D6

<EMI>

3

CH2

2

Vn

USB20_CMOS_P2

1

CH1

C221

680P_0402_50V7K

+INVPWR_B+

L12

FBMA-L11-201209-221LMA30T_0805

1

2

1

C224

C224 68P_0402_50V8J

68P_0402_50V8J

2

+3VS

1

2

3

W=60mils

C226

0.1U_0402_16V4Z

+5VALW

KB_LIGHT#

2

D7

@

PESD5V0U2BT 3P C/C SOT23 ESD

1

B+

12

INVTPWM

BKOFF#

11/09 Change D7 from mount to @

+LCDVDD

1

2

C222

10U_0805_10V4Z

C225 220P _0402_50V7K C225 220P _0402_50V7K

C227 220P _0402_50V7K C227 220P _0402_50V7K

W=60mils

1

C223

0.1U_0402_16V4Z

2

ESD PROTECT CLOSE TO JLVDS1

1 2

W=60mils

W=40mils

PCH_LCD_CLK<16> PCH_LCD_DATA<16> PCH_TXOUT0-<16> PCH_TXOUT0+<16>

PCH_TXOUT1-<16> PCH_TXOUT1+<16>

PCH_TXOUT2-<16> PCH_TXOUT2+<16>

PCH_TXCLK-<16> PCH_TXCLK+<16>

W=20mils

KB_LIGHT#<33>

W=60mils

USB20_N2<17> USB20_P2<17>

+INVPWR_B+

LCD/PANEL BD. Conn.

+LCDVDD

+3VS

R310 0_0603_5%R310 0_0603_5%

+5VS

R311 0_0402_5% R311 0_0402_5% R312 0_0402_5% R312 0_0402_5% R309 300_0402_5%R309 300_0402_5%

+5VALW

1 2 1 2 1 2

12

Copy NAV50 Conn.

PCH_LCD_CLK PCH_LCD_DATA PCH_TXOUT0PCH_TXOUT0+

PCH_TXOUT1PCH_TXOUT1+

PCH_TXOUT2PCH_TXOUT2+

PCH_TXCLKPCH_TXCLK+ +5V_CAM_LV USB20_CMOS_N2 USB20_CMOS_P2 +5VALW_LV

INVTPWM BKOFF#

JLVDS1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ACES_88341-3000B001

CONN@

11/09 Delete R304(@)

BKOFF#<33>

C C

9/1 Del D5/R22(BKOFF# not need to pull high)

+3VS

R307 2.2K_0402_5%R307 2.2K_0402_5%

1 2

R308 2.2K_0402_5%R308 2.2K_0402_5%

1 2

USB20_N2 USB20_CMOS_N2

1

USB20_P2 USB20_CMOS_P2

4

9/14 Add By Vivian(EMI suggest)

B B

A A

USB20_CMOS_N2

+3VS

BKOFF#

R306 10K_0402_5%R306 10K_0402_5%

1 2

L13

1

4

WCM2012F2S-900T04_0805

@

D6

6

5

4

CM1293-04SO_SOT23-6

@

11/09 Change JLVDS1 and pin definition

12/04 Change JLVDS1 and pin definition

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

LVDS Connector

NAU00 M/B LA-6101P Schematics

22 48Tuesday, March 09, 2010

of

1

of

1.0

A

B

C

D

E

10/29 Delete L14,L15,L16 (For layout spacing)

CRT Connector

1 1

PCH_CRT_R<16> PCH_CRT_G<16> PCH_CRT_B<16>

PCH_CRT_R

PCH_CRT_G

PCH_CRT_B

R313

150_0402_1%

2 2

PCH_CRT_HSYNC<16>

PCH_CRT_R PCH_CRT_G PCH_CRT_B

12

R314

150_0402_1%

C239 0.1U_0402_16V4ZC239 0.1U_0402_16V4Z

1 2

12

R315

150_0402_1%

PCH_CRT_HSYNC

PCH_CRT_VSYNC<16>

10/29 Delete D8,D9,D10 (For layout spacing)

+CRT_VCC

1

5

U8

P

4

OE#

A2Y

G

TC7SET125FUF SC70 5P BUFFER

3

C244 0.1U_0402_16V4ZC244 0.1U_0402_16V4Z

1 2

+CRT_VCC

PCH_CRT_VSYNC

1

C232

2

22P_0402_50V8J

R317 10K_0402_5%R317 10K_0402_5%

5

P

A2Y

G

3

12

R540 39_0402_5%R540 39_0402_5%

1 2

1

U9

CRT_VSYNC_R CRT_VSYNC_1

4

OE#

TC7SET125FUF SC70 5P BUFFER

L18 FCM2012CF-800T06_2PL18 FCM2012CF-800T06_2P

L19 FCM2012CF-800T06_2PL19 FCM2012CF-800T06_2P

L22 FCM2012CF-800T06_2PL22 FCM2012CF-800T06_2P

1

C234

C233

2

22P_0402_50V8J

CRT_HSYNC_1CRT_HSYNC_R

R541 39_0402_5%R541 39_0402_5%

1 2

15P_0402_50V8J

1

C235

2

15P_0402_50V8J

Change to 12pf for DIS

1 2

L23 BLM18A G121SN1D_2PL23 BLM18AG121SN1D_2P

1 2

L24 BLM18A G121SN1D_2PL24 BLM18AG121SN1D_2P

11/11 Correct L23,L24 footprint

C236

1

2

1

C237

C237 15P_0402_50V8J

15P_0402_50V8J

2

C240

10P_0402_50V8J

CRT_R_2

CRT_G_2

CRT_B_2

CRT_HSYNC_2

CRT_VSYNC_2

1

2

+5VS

1

C241

C241 10P_0402_50V8J

10P_0402_50V8J

2

11/03 Change U8,U9 from SA411250130 to SA00000RZ00

PCH DDC PU 2.2K on Page 17

3 3

PCH_CRT_DATA<16>

PCH_CRT_CLK<16>

PCH_CRT_DATA DSUB_12

PCH_CRT_CLK

9/10 Change from 2N7002E-T1-E3_SOT23-3 to 2N7002DW-T/R7_SOT363-6 Michael

+3VS

2

Q2A

61

2N7002DW-T/R7_SOT363-6

5

Q2B

3

4

2N7002DW-T/R7_SOT363-6

01/15 Change Q2 from SB00000AR00 to SB00000D900

03/05 Change Q1,Q2 from SB00000D900 to SB00000DH00 (MFG Recommend)

R538

2.2K_0402_5%

12

D11

2 1

RB491D_SC59-3

+CRT_VCC

12

R539

2.2K_0402_5%

DSUB_15

W=40mils

F1

1.1A_6V_SMD1812P110TF

0.1U_0402_16V4Z

1

C238

100P_0402_50V8J

2

1

2

C242

68P_0402_50V8J

C228

21

1

2

W=40mils

1

2

DSUB_12

DSUB_15

C243

C243 68P_0402_50V8J

68P_0402_50V8J

+CRT_VCC+R_CRT_VCC

Copy KAV60

JCRT1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

SUYIN_070546FR015S290ZR

CONN@

0909 Change JCRT1 symbol from KAVAA

11/10 Add C518,C519 (EMI Recommend)

+3VS

1

C518

680P_0402_50V7K

2

C519

680P_0402_50V7K

16

G

17

G

1

2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

NAU00 M/B LA-6101P Schematics

23 48Tuesday, March 09, 2010

of

E

of

1.0

5

+3VS

Copy NTUC0

HDMI_DETECT

D D

R322 0_0402_5%R322 0_0402_5%

7318C@

33K_0402_5%

R325

12

R318

4.7K_0402_5%

13

D

2

G

Q19

S

SSM3K7002FU_SC70-3

+3VS

12

R326

4.7K_0402_5%

12

@

R330

R330 0_0402_5%

0_0402_5%

+3VS

R331 4.7K_0402_5%7318C@R331 4.7K_0402_5%7318C @ R333 4.7K_0402_5%7318C@R333 4.7K_0402_5%7318C @

12/22 Change R338 from @ to 1442@

C C

01/20 Add R651 (Asmedia Recommend)

B B

A A

4

+3VS

12

@

R319

R319 0_0402_5%

0_0402_5%

12

@

R323

R323 0_0402_5%

0_0402_5%

1 2 1 2

4.7K_0402_5%

PCH_TMDS_D0<16> PCH_TMDS_D0#<16>

PCH_TMDS_D2<16> PCH_TMDS_D2#<16>

PCH_TMDS_D1<16> PCH_TMDS_D1#<16>

PCH_TMDS_CK<16> PCH_TMDS_CK#<16>

R338

1442@

HDMI_OE#

HDMICLK_R

HDMIDAT_R

HDMI_DETECT

@

R339

4.7K_0402_5%

1 2

12

25

28

29

30

32

34 35

48 47

45 44

42 41

39 38

R651

2.2K_0402_5%

U10

OE#

SCL_SINK

SDA_SINK

HPD_SINK

DDC_EN

CFG0 CFG1

IN_D4+ IN_D4-

IN_D3+ IN_D3-

IN_D2+ IN_D2-

IN_D1+ IN_D1-

PS8101QFN48G QFN 48P

8101@

11/09 Delete R350(@)

11/17 Change net name from +5VS to +5VS_HDMI

+5VS_HDMI

R351

HDMIDAT_R HDMICLK_R

R351

2.2K_0402_5%

1 2

R352

2.2K_0402_5%

1 2

+5VS

21

D12

D12 RB491D_SC59-3

RB491D_SC59-3

+5VS_HDMI_D

F21.1A_6VDC_FUSE F21.1A_6VDC_FUSE

2 1

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

3

1

C249

0.1U_0402_16V4Z

2

HDMI_DETECT +5VS_HDMI

10/23 Change R327 from 7318C@ from @ Change R332 from @ to 7318C@

+3VS

VCC VCC VCC VCC VCC VCC VCC VCC

PC1 PC0

REXT

HPD#

SDA

SCL

RT_EN#

OUT_D4+

OUT_D4-

OUT_D3+

OUT_D3-

OUT_D2+

OUT_D2-

OUT_D1+

OUT_D1-

GND GND GND GND GND GND GND GND GND GND

PAD

U10

ASM1442_QFN48_7X7

1442@

2 11 15 21 26 33 40 46

4 3

6

7

8

9

10

13 14

16 17

19 20

22 23

1 5 12 18 24 27 31 36 37 43 49

(Vendor Recommend)

1

C245

0.1U_0402_16V4Z

2

R327 4.7K_0402_5%@R327 4.7K_0402_5%@

1 2

R328 4.7K_0402_5%8101@R328 4.7K_0402_5%8101@

1 2

R332 4.7K_0402_5%1442@R332 4.7K_0402_5%1442@

1 2

R334 4.7K_0402_5%@R334 4.7K_0402_5%@

1 2

internal pull down

R335 430_0402_1%8101@R335 430_0402_1%8101@

1 2

PCH_DPB_HPD

HDMI_TX0+ HDMI_TX0-

HDMI_TX2+ HDMI_TX2-

HDMI_TX1+ HDMI_TX1-

HDMI_CLK+ HDMI_CLK-

U10

CH7318C

7318C@

11/17 Add F2 (Safety Recommend)

Copy KHLB0

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

TYCO_1775040-6

CONN@

GND GND GND GND

20 21 22 23

1

C246

0.1U_0402_16V4Z

2

PCH_DPB_HPD <16>

R340 4.7K_0402_5%@R340 4.7K_0402_5%@

1 2

12

R341

@

4.7K_0402_5%

2

1

10/22 Change R335(1442@) from 3.3kohm to 3.4kohm (Vendor Recommend)

R335

1.2K_0402_1%

7318C@

SDVO_SDATA <16>

SDVO_SCLK <16>

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

HDMI_CLK+_CONN

1

C247

0.1U_0402_16V4Z

2

+3VS

12

R335

3.4K_0402_1%

1442@

1

C248

C248 10U_0805_10V4Z

10U_0805_10V4Z

2

10/23 Delete R324(7318C@),R329(7318C@) for Calpella

12/22 Change R332 from 7318C@ to 1442@

12

R337

+3VS

R337

2.2K_0402_5%

SDVO_SDATA

SDVO_SCLK

HDMI_TX2+ HDMI_TX2HDMI_TX1+ HDMI_TX1HDMI_TX0+ HDMI_TX0HDMI_CLK+ HDMI_CLK-

R342 0_0402_5%1442@R342 0_0402_5%1442@ R343 0_0402_5%1442@R343 0_0402_5%1442@ R344 0_0402_5%1442@R344 0_0402_5%1442@ R345 0_0402_5%1442@R345 0_0402_5%1442@ R346 0_0402_5%1442@R346 0_0402_5%1442@ R347 0_0402_5%1442@R347 0_0402_5%1442@ R348 0_0402_5%1442@R348 0_0402_5%1442@ R349 0_0402_5%1442@R349 0_0402_5%1442@

R336

2.2K_0402_5%

06/25 Mirror L8,L9,L10,L11

HDMI_TX2+

HDMI_TX2-

HDMI_TX1+

HDMI_TX1-

HDMI_TX0+

HDMI_TX0-

HDMI_CLK+

HDMI_CLK-

L25

WCM-2012-900T_4P

7318C@

11/09 Delete R353

HDMI_DETECT

WCM-2012-900T_4P

1

4

L25

8101@L25

8101@

WCM-2012-900T_4P

1

4

L26

8101@L26

8101@

WCM-2012-900T_4P

1

4

L27

8101@L27

8101@

WCM-2012-900T_4P

1

4

L28

8101@L28

8101@

L26

WCM-2012-900T_4P

7318C@

HDMI_TX2+_CONN

2

HDMI_TX2-_CONN

3

HDMI_TX1+_CONN

2

HDMI_TX1-_CONN

3

HDMI_TX0+_CONN

2

HDMI_TX0-_CONN

3

HDMI_CLK+_CONN

2

HDMI_CLK-_CONN

3

L27

WCM-2012-900T_4P

7318C@

+5VS

3

@

1

D13

D13 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_CLK-_CONN

L28

WCM-2012-900T_4P

7318C@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/03/20

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

HDMI Level Shifter & Conn.

NAU00 M/B LA-6101P Schematics

24 48Tuesday, March 09, 2010

1

1.0

of

A

B

C

D

E

F

G

H

HDD

SATA HDD Conn.

Copy NIM00

JHDD1

1

SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0SATA_PTX_DRX_N0

SATA_DTX_PRX_N0 SATA_DTX_PRX_P0

+3VS

+5VS_HDD

C255

1U_0402_6.3V4Z

SATA_PTX_DRX_P0

SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0

10U_0805_10V4Z

1

C256

2

SATA_PTX_DRX_P0<13>

1 1

2 2

SATA_PTX_DRX_N0<13>

SATA_DTX_C_PRX_N0<13> SATA_DTX_C_PRX_P0<13>

+5VS_HDD

0.1U_0402_16V4Z

1

C254

2

1000P_0402_50V7K

1

2

C250 0.01U_0402_16V7KC250 0.01U_0402_16V7K C251 0.01U_0402_16V7KC251 0.01U_0402_16V7K

C252 0.01U_0402_16V7KC252 0.01U_0402_16V7K C253 0.01U_0402_16V7KC253 0.01U_0402_16V7K

+5VS

C257

1 2 1 2

R354 0_0805_5%R354 0_0805_5%

1 2

11/11 Correct Q20 footprint

+3VS

S

G-Sensor

Copy KIUE0

C258

GSENSOR@

0.1U_0402_16V4Z

1

2

C259

GSENSOR@

1U_0603_10V4Z

+3VS_GEN

1

C260

GSENSOR@

10U_0805_6.3V6M

2

R355

1 2

47_0402_5%

GSENSOR@

EC_GENPD<33>

01/07 Change Q20 from SB923010020 to SB934130000

+3VS_ITES_R

C261

1 2

0.1U_0402_16V4Z

GSENSOR@

Q20

GSENSOR@

Q20

GSENSOR@

AO3413_SOT23-3

D

1 3

G

2

12

R356

GSENSOR@

100K_0402_5%

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

DAS/DSS

19

GND

20

V12

21

V12

22

V12

SUYIN_127043FR022G196ZR

CONN@

1

C262

GSENSOR@

1U_0603_10V4Z

2

GND GND

23 24

11/11 Add GND net on JHDD1.23 and JHDD1.24

3 3

G_SELFTEST<33>

4 4

12

R357

@

10K_0402_5%

12

R360

GSENSOR@

100K_0402_5%

U13

2

ST

14

Vs

15

Vs

3

COM

5

COM

6

COM

7

COM

S IC LIS244ALTR LGA 16P G-SENSOR

GSENSOR@

Xout Yout

12 10

1

NC

4

NC

8

NC

9

NC

11

NC

13

NC

16

NC

GSENSOR@ 1 2 1 2

1 2

0.1U_0402_16V4Z

GSENSOR@

1

C263

@

2

GSENSOR@

0.1U_0402_16V4Z

C264

1

2

VOUTY

1

C265

GSENSOR@

0.1U_0402_16V4Z

2

X VOUTX

R358 0_0402_5%

Y

R359 0_0402_5%

Z VOUTZ

R361 0_0402_5%@R361 0_0402_5%@

VOUTX <33> VOUTY <33>

VOUTZ <33>

12/17 Change C258,C259,C260,R355,Q20,C261,R356,C262,R360,R358,R359,C264,C265,U13 from mount to GSENSOR@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2009/10/10 2010/10/10

E

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

F

Date: Sheet

Compal Electronics, Inc.

HDD Conn/G-Sensor

NAU00 M/B LA-6101P Schematics

G

25 48Tuesday, March 09, 2010

of

H

1.0

5

4

3

2

1

LAN Power Circuit & Refer NTUC0

+1.7_VDDCT

1 2

+3V_LAN

C271

EN_WOL# <33>

LAN_TEST_RST

LAN_XTALO LAN_XTALI

0.1U_0402_16V4Z

60mil

1000P_0402_50V7K

1

C272

2

LAN_CLKREQ#

4

1

C493

10U_0805_10V4Z

2

U14

29

TX_N

30

TX_P

36

RX_N

35

RX_P

32

REFCLK_N

33

REFCLK_P

2

PERST#

3

WAKE#

25

SMCLK

26

SMDATA

28

TEST_RST

27

TESTMODE

7

XTLO

8

XTLI

4

CLKREQ#

13

AVDDL

19

AVDDL

31

AVDDL

34

AVDDL

6

AVDDL_REG

41

GND

AR8151-AL1A_QFN40_5X5

Atheros

8151-AL1A

LED_0 LED_1 LED_2

TRXN0

TRXP0

TRXN1

TRXP1

TRXN2

TRXP2

TRXN3

TRXP3

RBIAS

VDD33

VDDCT

DVDDL

DVDDL_REG

AVDDH AVDDH

AVDDH_REG

R366

5.1K_0402_5%

1 2

LAN_ACTIVITY#

38

10/100_LINK_LED

39

LED2_CKR#

23

MIDI0-

12

MIDI0+

11

MIDI1-

15

MIDI1+

14

MIDI2-

18

MIDI2+

17

MIDI3-

21

MIDI3+

20

LAN_RBIAS

10

+3V_LAN

1

+1.7_LX

40

LX

+1.7_VDDCT

5

+1.1_DVDDL

24 37

16 22 9

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

C278 0.1U_0402_16V4Z

C280 1U_0402_6.3V4Z

C280 1U_0402_6.3V4Z C281 0.1U_0402_16V4Z

C281 0.1U_0402_16V4Z

+2.7_AVDDH

1

2

C289

C288

1U_0402_6.3V4Z

Layout note : C288&C289 Close to Pin9 C290 Close to Pin16 C291 Close to Pin22

Issued Date

3

+1.7_LX

1 2

1 2 1 2

Near Pin37

1

2

C290

0.1U_0402_16V4Z

no overclocking PD 5.1K

LAN_ACTIVITY# <27>

MIDI0- <27> MIDI0+ <27> MIDI1- <27> MIDI1+ <27> MIDI2- <27> MIDI2+ <27> MIDI3- <27> MIDI3+ <27>

R372

2.37K_0402_1%

1

2

C291

0.1U_0402_16V4Z

2009/10/10

+1.7_VDDCT

1

C279

0.1U_0402_16V4Z

2

Compal Secret Data

Deciphered Date

R362 0_0603_5%

1 2

@

+3VALW

D D

01/07 Change Q21 from SB923010020 to SB934130000

C C

PCIE_DTX_C_PRX_N1<14>

PCIE_DTX_C_PRX_P1<14>

PCIE_PTX_C_DRX_N1<14>

PCIE_PTX_C_DRX_P1<14>

CLK_PCIE_LAN#<14> CLK_PCIE_LAN<14>

PLT_RST_BUF#<17,32,37>

PCH_PCIE_WAKE#<15,32,37>

27P_0402_50V8J

PCH_PCIE_WAKE#_R<33>

1

2

C282

Layout note : C286&C287 Close to Pin6 C282 Close to Pin13 C283 Close to Pin19 C284 Close to Pin31 C285 Close to Pin34

Y3

1 2

25MHZ_20PF_7A25000012

1

C276

2

10/22 Change off-page direction of PCH_PCIE_WAKE# and PCH_PCIE_WAKE#_R

B B

A A

@

1U_0402_6.3V4Z

1

C270

C269

2

D

S

D

S

G

Q21

2

AO3413_SOT23-3

R363 10K_0402_5%R363 10K_0402_5%

2

C273

0.1U_0402_16V4Z

1

01/15 Change R362 from mount to @ Change Q21,R363,C273 from @ to mount

R369 0_0402_5%R369 0_0402_5% R370 0_0402_5%R370 0_0402_5%

PLT_RST_BUF#

R543 0_0402_5%R543 0_0402_5%

R374 4.7K_0402_5%

+3V_LAN +3V_LAN

R374 4.7K_0402_5%

10U_0805_10V4Z

13

1 2

C274 .1U_0402_16V7K

1 2

C275 .1U_0402_16V7K

1 2

12 12

1 2

12

@

2

0.1U_0402_16V4Z

Place Close to Pin 1 Refer CRB

PCIE_DTX_PRX_N1

PCIE_DTX_PRX_P1

CLK_PCIE_LAN#_C CLK_PCIE_LAN_C

PCH_PCIE_WAKE#_R

11/02 Change R374 from mount to @

LAN_CLKREQ#<14>

+1.1_AVDDL

1

2

C286

C287

1U_0402_6.3V4Z

5

0.1U_0402_16V4Z

1

C277

2

1

2

C283

0.1U_0402_16V4Z

LAN_XTALI

LAN_XTALO

27P_0402_50V8J

1

2

C284

C285

0.1U_0402_16V4Z

1

C266

1

C267

2

10U_0805_10V4Z

10/22 Remove R364

10/100_LINK_LED

LED2_CKR#

+3V_LAN

10/22 Change R376 from mount to @

11/02 Change R373 from mount to @

11/02 Delete Q3(@),R375(@),R377(@)

11/09 Delete R373(@),R376(@)

MIDI0+

MIDI0-

MIDI1+

MIDI1-

MIDI2+

MIDI2-

MIDI3+

MIDI3-

2010/10/10

2

0.1U_0402_16V4Z

R371 4.7K_0402_5%

L33 4.7UH_SIA4012-4R7M_20%L33 4.7UH_SIA4012-4R7M_20%

1

Layout note : C266,C267,C268&L33 Close to Pin40

C268

2

R365

1 2

0_0402_5%

@

1000P_0402_50V7K

1000_LINK_LED

12

Note: Place Close to LAN chip L33 DCR< 0.15 ohm Rate current of L33 > 1A

LAN_CLKREQ#

Place Close to LAN chip

49.9_0402_1%

R378

1 2

49.9_0402_1%

R379

1 2

49.9_0402_1%

R380

1 2

49.9_0402_1%

R381

1 2

49.9_0402_1%

R382

1 2

49.9_0402_1%

R383

1 2

49.9_0402_1%

R384

1 2

49.9_0402_1%

R385

1 2

Title

Size Document Number Rev

Custom

NAU00 M/B LA-6101P Schematics

Tuesday, March 09, 2010

Date: Sheet

+1.7_LX

+1.7_LX+1.7_VDDCT

2

1

3

D14

D14 CHP202UPT_SOT323-3

CHP202UPT_SOT323-3

C292 1000P_0402_50V7K

1 2

C293 0.1U_0402_16V4Z

1 2

C294 1000P_0402_50V7K

1 2

C295 0.1U_0402_16V4Z

1 2

C296 1000P_0402_50V7KC296 1000P_0402_50V7K

1 2

C297 0.1U_0402_16V4ZC 297 0.1U_0402_16V4Z

1 2

C298 1000P_0402_50V7KC298 1000P_0402_50V7K

1 2

C299 0.1U_0402_16V4ZC 299 0.1U_0402_16V4Z

1 2

Compal Electronics, Inc.

LAN AR8151

LAN_LINK# <27>

1

26 48

1.0

of

5

4

3

2

1

Copy NIMUA

+1.7_VDDCT

Layout note : C300 Close to R386

10/28 Swap transformer signal 10/28 Swap transformer signal

1

2

0.1U_0402_16V4Z

C303

MIDI3MIDI3+

MIDI2MIDI2+

MIDI1MIDI1+

MIDI0MIDI0+

1

C304

1000P_0402_50V7K

2

0.1U_0402_16V4Z

Place close to TCT pi n

MIDI3-<26>

C301

1000P_0402_50V7K

MIDI3+<26>

MIDI2-<26> MIDI2+<26>

MIDI1-<26> MIDI1+<26>

MIDI0-<26> MIDI0+<26>

1

C302

2

D D

near Pin1 near Pin4 near Pin7 near Pin10

C C

1 2

1

C306

C305

1000P_0402_50V7K

2

R386

R386 0_0603_5%

0_0603_5%

C300

C300 1U_0402_6.3V4Z

1U_0402_6.3V4Z

12

Close to R7

1

2

0.1U_0402_16V4Z

+1.7_VDDCT_R

1

C308

C307

1000P_0402_50V7K

2

TAIMAG: SP050004M00 BOTHHAND: NA

T11

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

350UH_IH-037-2

1

2

0.1U_0402_16V4Z

MCT1

MCT2

MCT3

MCT4

MX1+ MX1-

MX2+ MX2-

MX3+ MX3-

MX4+ MX4-

MCT3

24 23 22

MCT2

21 20 19

MCT1

18 17 16

MCT0

15 14 13

12

R387 75_0402_1%R387 75_0402_1%

12

R389 75_0402_1%

R388 75_0402_1%R388 75_0402_1%

12

R390 75_0402_1%

RJ45_GND

40mil

RJ45_MIDI3RJ45_MIDI3+

RJ45_MIDI2RJ45_MIDI2+

RJ45_MIDI1RJ45_MIDI1+

RJ45_MIDI0RJ45_MIDI0+

LAN_ACTIVITY#<26>

+3V_LAN

C309

12

470P_0402_50V7K

R391 510_0402_5% R391 510_0402_5%

R392 510_0402_5%R392 510_0402_5%

1 2

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

Copy NAV50

JLAN1

11

Yellow LED+

12

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

9

Green LED+

10

Green LED-

SANTA_130452-3

R394

0_0402_5%

1

C310

470P_0402_50V7K

2

SHLD1

DETECT PIN1

SHLD1

12

15

13

14

LAN_LINK# <26>

LANGND

1000P_1206_2KV7K

RJ45_GND

C311

1 2

C496

LANGND

1

2

0.1U_0402_16V4Z

C497

1

2

C494

10U_0805_10V4Z

1

40mil

1

C312

C495

2

0.1U_0402_16V4Z

470P_0402_50V7K

1

2

C498

10U_0805_10V4Z

1

470P_0402_50V7K

Follow CRB

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/10/10

Compal Secret Dat a

Deciphered Dat e

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

LAN Magnetic & RJ45

NAU00 M/B LA-6101P Schematics

1

27 48Tuesday, March 09, 2010

of

1.0

5

11/09 Delete RR1(@)

RR3 0_0603_5%RR3 0_0603_5%

+3VS

D D

40mil 40mil

C C

1 2

+3VS_CR

1

CR3

2

CR3

10U_0805_10V6K

2

CR2

0.1U_0402_16V4Z

Place CR2,CR3 close to U15 Pin4

USB20_N5<17> USB20_P5<17>

+VCC_3IN1

40mil +V18_CR : 20mil

0.1U_0402_16V4Z

1

CR4

2

4

CR_REFE must far away from 48MHz clock trace. Place CR1,RR2 close to U15 Pin1

11/04 Change CR1 from SE071101J1M to SE071101J80

CR1 100P_0402_50V8JCR1 100P_0402_50V8J

1 2

RR2 6.19K_0402_1%RR2 6.19K_0402_1%

2

CR5

1

1U_0402_6.3V6K

12

XD_RDY_SD_WP_MS_CLK_R

Place CR4,CR5 close to U15 Pin5,6

3

Pin1 and pin6 of U15 trace width = 20mil

CR_REFE

+VCC_3IN1 +V18_CR

XD_CD#

RR5

0_0402_5%

XD_RDY_SD_WP_MS_CLK

12

XD_RE#_MS_INS# XD_CE#_SD_D1 XD_CLE_SD_D0_MS_D7 XD_ALE_SD_D7_MS_D3

2

U15

1

REFE

2

DM

3

DP

4

3V3_IN

5

CARD_3V3

6

V18

7

XD_CD#

8

SP1

9

SP2

10

SP3

11

SP4

12

SP5

RTS5138-GR_QFN24_4X4

17

GPIO0

24

CLK_IN

23

XD_D7

22

SP14 SP13 SP12 SP11 SP10

SP9 SP8 SP7 SP6

EPAD

25

Ground pad must have 4 via

XD_D5_SD_D2_MS_D5

21

XD_D4_SD_D3_MS_D1

20

XD_D3_SD_D4_MS_D4

19 18

XD_D1_SD_D5_MS_D0

16

XD_D0_SD_CLK_MS_D2

15

XD_WP_SD_D6_MS_D6

14 13

11/09 Delete RR4

XD_D7

XD_D6_MS_BS

XD_D2_SD_CMD

XD_WE#_SD_CD#

RR6

1 2

0_0402_5%

no more than 2 via on all signal trace

Pin8 and Pin15 Keep trace routing lengths as short as possible, Avoid via and layer changes

1

CLK_48M

XD_D0_SD_CLK_MS_D2_R

Close to U15 pin24

CLK_48M

12

RR7

22_0402_5%

1

CR6

10P_0402_50V8J

2

CLK_48M <12>

20mil

+VCC_3IN1+VCC_3IN1

12/22 Mount RR7,CR6

7 in 1 Card Reader

Copy NCQF0

JCR1

22

XD_D0_SD_CLK_MS_D2 XD_D1_SD_D5_MS_D0 XD_D2_SD_CMD XD_D3_SD_D4_MS_D4 XD_D4_SD_D3_MS_D1 XD_D5_SD_D2_MS_D5

B B

A A

XD_D6_MS_BS XD_D7

XD_WE#_SD_CD# XD_WP_SD_D6_MS_D6 XD_ALE_SD_D7_MS_D3 XD_CD# XD_RDY_SD_WP_MS_CLK XD_RE#_MS_INS# XD_CE#_SD_D1 XD_CLE_SD_D0_MS_D7

12

RR10

@

100K_0402_5%

5

XD-VCC

30

XD10-D0

29

XD11-D1

28

XD12-D2

27

XD13-D3

26

XD14-D4

25

XD15-D5

24

XD16-D6

23

XD17-D7

33

XD07-WE

32

XD08-WP

34

XD06-ALE

39

XD01-CD

38

XD02-R/B

37

XD03-RE

36

XD04-CE

35

XD05-CLE

31

XD GND

40

XD GND

41

SD CD/WP GND

42

SD CD/WP GND

T-SOL_144-1300302600_NR

CONN@

1

CR11

0.1U_0402_16V4Z

2

MS4-DATA0 MS3-DATA1 MS5-DATA2 MS7-DATA3

SD4-VDD MS9-VCC

SD5-CLK SD7-DAT0 SD8-DAT1 SD9-DAT2 SD1-DAT3

SD2-CMD

SD-CD

SD-WP

SD6-VSS

SD3-VSS

MS8-SCLK

MS6-INS

MS2-BS

MS1-VSS

MS10-VSS

11 18

9 4 3 21 19 16 1 2

6 13

17 10 8 12 15 14 7 5 20

4

XD_D0_SD_CLK_MS_D2 XD_CLE_SD_D0_MS_D7 XD_CE#_SD_D1 XD_D5_SD_D2_MS_D5 XD_D4_SD_D3_MS_D1 XD_D2_SD_CMD XD_WE#_SD_CD#

XD_RDY_SD_WP_MS_CLK

XD_D1_SD_D5_MS_D0 XD_D4_SD_D3_MS_D1 XD_D0_SD_CLK_MS_D2 XD_ALE_SD_D7_MS_D3 XD_RE#_MS_INS# XD_D6_MS_BS

Security Classification

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

Issued Date

CR8

1

2

Close to JCR1

1

CR7

0.1U_0402_16V4Z

2

Compal Secret Data

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

EMI reserved Close to JCR1

XD_D0_SD_CLK_MS_D2_R

XD_RDY_SD_WP_MS_CLK_R

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

12

RR8

@

10_0402_5%

1

CR9

@

10P_0402_50V8J

2

Compal Electronics, Inc.

Card Reader/7-IN-1 Socket

NAU00 M/B LA-6101P Schematics

1

12

RR9

@

10_0402_5%

1

CR10

@

10P_0402_50V8J

2

of

28 48Tuesday, March 09, 2010

1.0

5

4

3

2

1

10/29 Follow NTUC0

C332

R414 47K_0402_5%R414 47K_0402_5%

BEEP#<33>

PCH_SPKR<13>

D D

10/29 Delete C333,C334,D15,Q22,R411,R412,R413 Change R414,R415 from 560ohm to 47kohm Change C332,C328 from 1uF to 0.1uF

C C

1 2

R415 47K_0402_5%R415 47K_0402_5%

1 2

R416

10K_0402_5%

12

1

C328

0.1U_0402_16V4Z

2

11/09 Change L35,L36,L50 from SM010015410 to SD013000080

11/10 Change R465,R466 from SE053475Z80 to SE107475M80 (Realtek Recommend)

MIC1_L_R<30> MIC1_R_R<30>

B B

A A

01/07 Change C351.2 from R422.2 to R422.1

1 2

C351 10P_0402_50V8J@C351 10P_0402_50V8J@

DMIC_CLK_R<30>

01/07 Add R648(@) to +HD_AVDD (Realtek Recommend)

HP_PLUG#<30>

MIC_PLUG#<30>

SENSE A

SENSE B

DGGLW

ImpedanceSense Pin

39.2K

20K

10K

5.1K

39.2K

20K

10K

5.1K

5

12

R427 39.2K_0402_1%

1 2

R428 20K _0402_1%

Codec Signals

PORT-A (PIN 32, 33)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

PORT-D (PIN 48)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)

PORT-G (PIN 20)

PORT-H (PIN 47)

SENSE_A

DMIC_DATA_R<30>

EC_MUTE#<33>

HDA_RST#_AUDIO<13>

MONO_IN

1 2

0.1U_0402_16V4Z

L35

1 2

+3VS

L50

@L50

@

1 2

+1.5VS

change to +3vs

+3VS

1 2

L36 0_0603_5%L36 0_0603_5%

C341

@

100P_0402_50V8J

C465 4.7U_0603_6.3V6KC465 4.7U_0603_6.3V6K

1 2

C466 4.7U_0603_6.3V6KC466 4.7U_0603_6.3V6K

1 2

02/26 Change R422 from SD028000080 to SM01000CY00

+HD_AVDD

R420 0_0402_5%R420 0_0402_5%

1 2

R422 FBMA-10-100505-301T 0402R422 FBMA-10-100505-301T 0402

R424 0_0402_5%R424 0_0402_5%

1 2

R648 10K_0402_5%@R648 10K_0402_5%@

1 2

C499 0.01U_0402_16V7K@C499 0.01U_0402_16V7K@

1 2

MONO_IN

10/30 Change C352 GND from AGND to GND

+MIC1_VREFO_L

0_0603_5%

10U_0805_10V4Z

1

C342

C343

2

HDA_RST#_AUDIO

1 2

C352 100P_0402_50V8J@C352 100P_0402_50V8J@

1 2

C353 2.2U_0402_6.3V6M

10mil

10U_0805_10V4Z

1

C337

2

20mil

1

2

0.1U_0402_16V4Z

MIC1_L MIC1_R HP_RIGHT

DMIC_DATA

DMIC_CLK

SENSE_A

change pin31 and pin28

4

+5VAMP

0.1U_0402_16V4Z

1

C329

2

1

C336

0.1U_0402_16V4Z

2

1

C340

0.1U_0402_16V4Z

2

40mil

1

2

1 2

DGGLWIRU(0,

1 2

L37

FBMA-L11-160808-800LMT_0603

11/11 Correct L37 footprint

+MIC1_VREFO_R

1

C354

12

10U_0805_10V4Z@

2

R432

20K_0402_1%

+1.5VS_3VS_HDIO

1

C338

2

0.1U_0402_16V4Z

+3VS_HD

U17

23

LINE1_L

24

LINE1_R

14

LINE2_L

15

LINE2_R

21

MIC1_L

22

MIC1_R

16

MIC2_L

17

MIC2_R

2

GPIO0/DMIC_D ATA

3

GPIO1/DMIC_C LK

4

PD#

11

RESET#

12

PCBEEP

13

SENSE A

18

SENSE B

36

CBP

35

CBN

31

MIC1_VREFO_L

43

PVSS2

42

PVSS1

49

DVSS2

7

DVSS1

ALC259-VB5-GR_QFN48_7X7

1

DVDD

L34

+5VS

+HD_AVDD

9

PVDD139PVDD2

DVDD_IO

46

AVDD125AVDD2

SPK_OUT_L+

SPK_OUT_L-

SPK_OUT_R+

SPK_OUT_R-

HP_OUT_L

HP_OUT_R

SYNC

BCLK

SDATA_OUT

SDATA_IN

EAPD

SPDIFO

MONO_OUT

MIC2_VREFO

MIC1_VREFO_R

LDO_CAP

VREF

JDREF

CPVEE

AVSS1 AVSS2

38

1 2

FBMA-L11-201209-221LMA30T_0805

W=40mil

1

C335

10U_0805_10V4Z

2

W=40mil

1

C339

10U_0805_10V4Z

2

100P_0402_50V8J

1

C344

@

40 41

45 44

32 33

10

6

5

8

47

48

20

29

30 28

27

19

34

26 37

1

C345

2

0.1U_0402_16V4Z

SPKL+ SPKL-

SPKR+ SPKR-

HP_LEFT

HDA_BITCLK_AUDIO_R

HDA_SDOUT_AUDIO_R

HDA_SDIN0_R

EAPD

11/05 Add net name : CODEC_LDO_CAP,+CODEC_VREF,+CODEC_JDREF,CODEC_CPVEE

CODEC_LDO_CAP

+CODEC_VREF

+CODEC_JDREF

CODEC_CPVEE

2

AGNDDGND

1

+5VS

0.1U_0402_16V4Z

1

C347

C346

2

10U_0805_10V4Z

SPKL+ <30> SPKL- <30>

SPKR+ <30> SPKR- <30>

HP_LEFT <30> HP_RIGHT <30>

R421 0_0402_5%R421 0_0402_5%

R423 0_0402_5%R423 0_0402_5%

R425 33_0402_5%

R426 0_0402_5%R426 0_0402_5%

10mil 10mil 10mil 10mil 10mil

C356

2.2U_0402_6.3V6M

10/21 Change U17 to SA00003QR00 Symbol

03/04 Change U17 from SA00003QR00 to SA00003QR10

11/02 Change R429,R430,R431,R433,R434,R605 from 0_0603 to 0_0402 (Layout Spacing)

11/17 Delete R429,R430

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

1

C330

0.1U_0402_16V4Z

2

+VDDA

12

HDA_SYNC_AUDIO <13>

HDA_BITCLK_AUDIO <13>

HDA_SDOUT_AUDIO <13>

HDA_SDIN0 <13>

EC_EAPD <33>

C492 10U _0805_10V4ZC492 10U_0805_10V4Z

1 2

1

C355

0.1U_0402_16V4Z

2

PLO

J3

2

112

JUMP_43X39

U16

@

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

'9718LW

HDA_BITCLK_AUDIO_R

0.1U_0402_16V4Z

5

PLO

4

+MIC1_VREFO_R +MIC1_VREFO_L

C349

+VDDA

1 2

R418 22_0402_5%

22_0402_5%

@

0.1U_0402_16V4Z

(output = 300 mA)

4.75V

C331

@

2.2U_0603_6.3V6K

1 2

@R418

@

C348

@C348

@

10P_0402_50V8J

C350

@

DGND To AGND Bypass

R431 0_0402_5%R431 0_0402_5%

1 2

R433 0_0402_5%R433 0_0402_5%

1 2

R434 0_0402_5%R434 0_0402_5%

1 2

R605 0_0402_5%R605 0_0402_5%

1 2

DGND AGND

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

HDA Codec ALC259Q-GR

NXXXX M/B LA-6101P Schematics

29 48Tuesday, March 09, 2010

1

1.0

of

5

11/11 Change R435~R438 from SM010012010 to SD013000080 11/10 Add C512~C517(@) for EMI (Follow Realtek CRB)

Please place R435~R438,C512~C517 close to U17

20mil

D D

20mil

4

R435 0_0603_5%R435 0_0603_5%

SPKL+

SPKL+<29>

SPKL-<29>

1 2

R436 0_0603_5%R436 0_0603_5%

SPKL-

1 2

1

C513

@

1U_0402_6.3V4Z

2

1

C514

@

1U_0402_6.3V4Z

2

SPK_L+

1

C512

@

1U_0402_6.3V4Z

2

SPK_L-

3

Int. Speaker Conn.

2

3

D33

PJDLC05C_SOT23-3

@

1

2

3

1

2

Copy KTV00

SPK_RSPK_R+ SPK_LSPK_L+

D34

D34 PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

@

JSPK1

1

2

3

G1

4

G2

ACES_88266-04001

1

Right

5

Left

6

11/18 Change the pin definition of JSPK1 (Audio Recommend) 11/18 Swap D33

SPKR-

R437 0_0603_5%R437 0_0603_5%

20mil

C C

SPKR-<29>

SPKR+<29>

1 2

R438 0_0603_5%R438 0_0603_5%

SPKR+

1 2

1

C516

@

1U_0402_6.3V4Z

2

1

C517

@

1U_0402_6.3V4Z

2

10/29 Change R441,R442 from 56ohm to 75ohm (Follow Realtek CRB)

HP_LEFT

HP_LEFT<29>

HP_RIGHT<29>

HP_RIGHT

1 2

R441 75_0402_1%R441 75_0402_1%

1 2

R442 75_0402_1%R442 75_0402_1%

11/11 Correct L38,L39,L40,L41 footprint

Copy KTV00

+3VS

DMIC_CLK_R<29> DMIC_DATA_R<29>

2

3

D17

PJDLC05C_SOT23-3

B B

PJDLC05C_SOT23-3

For ESD 12/22

D17

@

1

8mil

C361

22P_0402_50V8J

12

R619

@

1

@

2

0_0402_5%

C362

22P_0402_50V8J

@

1

@

2

JMIC1

1

2

3

G1

4

G2

ACES_88266-04001

CONN@

5 6

316&$

MIC1_L_R<29>

MIC1_R_R<29>

A A

1 2

R445 1K_0603_1%R445 1K_0603_1%

1 2

R446 1K_0603_1%R446 1K_0603_1%

SPK_R-

1

C515

@

1U_0402_6.3V4Z

2

SPK_R+

330P_0402_50V7K

1 2

PLO

7DNHRII'

L38 FBMA-L11-160808-700LMT_2PL38 FBMA-L11-160808-700LMT_2P

HPOUT_R_1

L39 FBMA-L11-160808-700LMT_2PL39 FBMA-L11-160808-700LMT_2P

10/29 Short D18,D19 (Follow Realtek CRB) 10/29 Change R443,R444 location

+MIC1_VREFO_L +MIC1_VREFO_R

PLO PLO

4.7K_0402_5%

MIC1_L_R_1

MIC1_R_R_1

R443

12

R444

4.7K_0402_5%

L41 FBMA-L11-160808-700LMT_2PL41 FBMA-L11-160808-700LMT_2P

1 2

L40 FBMA-L11-160808-700LMT_2PL40 FBMA-L11-160808-700LMT_2P

1 2

220P_0402_50V8J

C363

2

C358

C357

C358

330P_0402_50V7K

1

HPOUT_L_2HPOUT_L_1

HPOUT_R_2

2

3

1

HP_PLUG#<29>

D35

D35 PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

@

01/07 Change GND to GNDA

MIC1_L_R_2

MIC1_R_R_2

1

220P_0402_50V8J

2

C364

1

2

3

D20

D20 PJSOT05C_SOT23-3

PJSOT05C_SOT23-3

@

1

MIC_PLUG#<29>

11/11 Correct D20 footprint

Headphone Out

Copy NIUR1

JEHP1

1 2

3

4

5 6

SUYIN_010030FR006G109ZL

CONN@

MIC JACK

Copy NIUR1

JEMIC1

1 2

3

4

5 6

SUYIN_010030FR006G109ZL

CONN@

01/07 Change GND to GNDA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sh eet

2

Date: Sh eet

Compal Electronics, Inc.

Audio Jack/MIC Conn/SPK Conn

NXXXX M/B LA-6101P Schematics

1

of

30 48Tuesday, March 09, 2010

1.0

A

10/22 Add R614, change R590,R589 from 0ohm to 4.7kohm (Vendor Recommend)

eSATA

12/22 Change U32,C490,C491,C503~C506,R589,R590,R614 from mount to @

Copy NITU1

10/23 Add C503~C506

C503 0.01U_0402_25V7K@C503 0.01U_0402_25V7K@

1 1

SATA_PTX_DRX_P4<13> SATA_PTX_DRX_N4<13>

SATA_DTX_C_PRX_P4<13> SATA_DTX_C_PRX_N4<13>

1 2

C504 0.01U_0402_25V7K@C504 0.01U_0402_25V7K@

1 2

C505 0.01U_0402_25V7K@C505 0.01U_0402_25V7K@

1 2

C506 0.01U_0402_25V7K@C506 0.01U_0402_25V7K@

1 2

SATA_PTX_DRX_P4

SATA_PTX_DRX_N4

SATA_DTX_C_PRX_N4

SATA_DTX_C_PRX_P4

R585 0_0402_5%R585 0_0402_5%

R586 0_0402_5%R586 0_0402_5%

R587 0_0402_5%R587 0_0402_5%

R588 0_0402_5%R588 0_0402_5%

On opposite side of U32

2 2

SATA_PTX_DRX_P4_CR SATA_PTX_DRX_N4_CR

SATA_DTX_C_PRX_P4_CR SATA_DTX_C_PRX_N4_CR

12

TI:D0 D1

BBBAEN

XX0

001

11

0

11

0

1

11

B

+3VS

R614

1 2

SATA_PTX_DRX_P4_RR

SATA_PTX_DRX_N4_RR

SATA_DTX_C_PRX_N4_RR

SATA_DTX_C_PRX_P4_RR

10/23 Add R615~618

12/22 Change R585~R588,R615~R618 from @ to mount

4.7K_0402_5%

@R614

4.7K_0402_5%

@

U32

7

EN

1

RX_0P RX_0N2VCC

5

TX_1P

4

TX_1N

3

GND GND13TX_0N

17

GND

18

GND

19

GND

21

PAD

SN75LVCP412RTJR_QFN20_4X4

@

6

VCC

10

VCC

16

VCC

20

9

D0

8

D1

15

TX_0P

14

12

RX_1N

11

RX_1P

R615 0_0402_5%R615 0_0402_5%

R616 0_0402_5%R616 0_0402_5%

R617 0_0402_5%R617 0_0402_5%

R618 0_0402_5%R618 0_0402_5%

0.01U_0402_16V7K

1

C490

@

0.1U_0402_16V4Z

2

SATA_PTX_DRX_P4_R SATA_PTX_DRX_N4_R

SATA_DTX_C_PRX_N4_R SATA_DTX_C_PRX_P4_R

12

2

1

SATA_PTX_DRX_P4_R

SATA_PTX_DRX_N4_R

SATA_DTX_C_PRX_N4_R

SATA_DTX_C_PRX_P4_R

SN75LVCP412

CHANNEL 0

CHANNEL 1

Low-powerLow-power

0dB

0dB2.5dB pre-emphasis

2.5dB pre-emphasis0dB

2.5dB pre-emphasis2.5dB pre-emphasis

C491

@

1 2

(Default)

C

R590

@

4.7K_0402_5%

R591

@

0_0402_5%

R589

@

4.7K_0402_5%

1 2

R592

@

0_0402_5%

1 2

D

+3VALW

C365

12

1

+

2

+5VALW

USB_ON#

1

C367

4.7U_0603_6.3V6K

2

9/14 Change symbol o f U59 by Vivian

11/25 Change L42 from @ to mount Change R451,R448 from mount to @ (EMI Recommend)

12/22 Change L42 from mount to @ Change R451,R448 from @ to mount (EMI Recommend)

USB20_N1<17>

USB20_P1<17>

11/09 Change D22 from mount to @

USB20_N1

USB20_P1

SATA_PTX_DRX_P4_R SATA_PTX_DRX_N4_R

SATA_DTX_C_PRX_N4_R SATA_DTX_C_PRX_P4_R

U18

1 2

4

RT9715BGS_SO8

R448 0_0402_5%R448 0_0402_5%

1 2

L42

1

4

WCM2012F2S-900T04_0805

1 2

R451 0_0402_5%R451 0_0402_5%

+USB_VCCD

VOUT VOUT

FLG

8 7 6 5

GND VIN VIN3VOUT EN

12/27 Change C365 from SGA00002N80 to SGA00001E00

150U_B2_6.3VM_R45M

@L42

@

2

3

C369 0.01U_0402_25V7KC369 0.01U_0402_25V7K

12

C370 0.01U_0402_25V7KC370 0.01U_0402_25V7K

12

C371 0.01U_0402_25V7KC371 0.01U_0402_25V7K

12

C372 0.01U_0402_25V7KC372 0.01U_0402_25V7K

12

11/05 Delete USB20_N1_1,USB20_P1_1 on D21 (ESD Recommend)

10/5 Change Bom structu re to mount(D13)

+USB_VCCD

USB20_P0_1

D21

6

CH3

5

Vp

4

CH4

CM1293-04SO_SOT23-6

<ESD>@D21

<ESD>@

CH2

CH1

USB20_N0_1

3

2

Vn

1

E

9/14 Change power net from +3V to +3VALW

R447

100K_0402_5%

1 2

R449

R449 10K_0402_5%

10K_0402_5%

470P_0402_50V7K

SATA_PTX_C_DRX_P4 SATA_PTX_C_DRX_N4

SATA_DTX_PRX_N4 SATA_DTX_PRX_P4

+USB_VCCD

1

C366

2

USB20_N1_1 USB20_P1_1

1

C368

0.1U_0402_16V4Z

2

USB_OC#0 <17>

Copy NCQF0

JSATA1

USB

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

ESATA

7

A-

8

GND

9

B-

10

B+

11

GND

12

GND

13

GND

14

GND

15

GND

TYCO_1759576-1

CONN@

USB Port

+USB_VCCD

3 3

+5VALW

USB_ON#

1

C377

4.7U_0603_6.3V6K

2

USB_ON#<33>

4 4

10/6 Change Bom structu re to mount(D26)

11/09 Change D22 from mount to @

+USB_VCCA

USB20_P3_1

U19

1

GND

2

VIN VIN3VOUT

4

EN

RT9715BGS_SO8

9/14 Change symbol o f U64 by Vivian

D22

6

CH3

5

Vp

4

CH4

CM1293-04SO_SOT23-6

VOUT VOUT

FLG

+USB_VCCA

8 7 6 5

<ESD>@D22

<ESD>@

CH2

Vn

CH1

3

2

1

11/11 Swap USB20_P3_1 and USB20_N3_1

A

9/14 Change power net from +3V to +3VALW

+3VALW

12

R455

R455 100K_0402_5%

100K_0402_5%

1 2

R456

R456 10K_0402_5%

10K_0402_5%

USB20_N3_1

1

C378

0.1U_0402_16V4Z

2

B

150U_B2_6.3VM_R45M

12/27 Change C373,C375 from SGA00002N80 to SGA00001E00

USB_OC#1 <17>

+USB_VCCA

150U_B2_6.3VM_R45M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C375

C373

1

2

1

+

2

1

C374

+

C374

2

470P_0402_50V7K

1

C376

2

470P_0402_50V7K

2009/10/10 2010/10/10

C

USB20_N0<17>

USB20_P0<17>

USB20_N3<17>

USB20_P3<17>

Compal Secret Data

USB20_N0

USB20_P0

11/25 Change L43 from @ to mount Change R452,R453 from mount to @ (EMI Recommend)

USB20_N3

USB20_P3

11/12 Swap USB20_N3,USB20_P3,USB20_P3_1 and USB20_N3_1 on L44

11/25 Change L44 from @ to mount Change R454,R457 from mount to @ (EMI Recommend)

Deciphered Date

1 2

R452 0_0402_5%R452 0_0402_5%

L43

@L43

@

1

4

WCM2012F2S-900T04_0805

R453 0_0402_5%R453 0_0402_5%

1 2

2

3

11/06 Swap L43

12/22 Change L43 from mount to @ Change R452,R453 from @t to mount (EMI Recommend)

R454 0_0402_5%R454 0_0402_5%

1 2

L44

@L44

@

1

4

WCM2012F2S-900T04_0805

1 2

R457 0_0402_5%R457 0_0402_5%

2

3

12/22 Change L44 from mount to @ Change R454,R457 from @ to mount (EMI Recommend)

D

2

USB20_N0_1 USB20_P0_1

3

USB20_N3_1 USB20_P3_1

Title

Size Document Number Rev

Custom

NAU00 M/B LA-6101P Schematics

Date: Sheet

+USB_VCCD

Copy NAV50

JUSB1

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020133GB004M25MZL

CONN@

+USB_VCCA

Copy NAV50

JUSB2

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020133GB004M25MZL

CONN@

Compal Electronics, Inc.

USB / BT / eSATA

31 48Tuesday, March 09, 2010

E

1.0

of

5

4

3

2

1

WLAN

R460 0_0402_5%

10/22 Add Net : BT_ACTIVE and R613, Delete T13

11/10 Add R631(@)

D D

C C

PCH_PCIE_WAKE#<15,26,37>

BT_ACTIVE<35>

MINI1_CLKREQ#<14>

CLK_PCIE_MINI1#<14> CLK_PCIE_MINI1<14>

PCIE_DTX_C_PRX_N2<14> PCIE_DTX_C_PRX_P2<14>

PCIE_PTX_C_DRX_N2<14> PCIE_PTX_C_DRX_P2<14>

+3VS_WLAN

EC_TX_P80_DATA<33>

EC_RX_P80_CLK<33>

PCH_PCIE_WAKE# +3VS_WLAN

R631 0_0402_5%@R631 0_0402_5%@

1 2

R613 0_0402_5%@R613 0_0402_5%@

1 2

MINI1_CLKREQ#

CLK_PCIE_MINI1# CLK_PCIE_MINI1

PCIE_DTX_C_PRX_N2 PCIE_DTX_C_PRX_P2

PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2

EC_TX_P80_DATA EC_RX_P80_CLK

100K_0402_5%

R460 0_0402_5%

1 2

12

R634

Copy NTUC0

@

BT_ACTIVE_R_1 BT_ACTIVE_R

JWLAN1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

GND2

FOX_AS0B226-S40N-7F

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

11/14 Add +1.5VS

+1.5VS

WL_OFF# PLT_RST_BUF#

R632 0_0402_5%R632 0_0402_5% R633 0_0402_5%@R633 0_0402_5%@

PCH_SMBCLK PCH_SMBDATA

USB20_N8 USB20_P8

WW AN_LED#_RR WLAN_LED#_RR

WL_OFF# <33> PLT_RST_BUF# <17,26,37>

1 2 1 2

PCH_SMBCLK <12,14,37> PCH_SMBDATA <12,14,37>

USB20_N8 <17> USB20_P8 <17>

R646 0_0402_5%@R646 0_0402_5%@

1 2

R647 0_0402_5%R647 0_0402_5%

1 2

12/16 Add R646(@),R647

+3VS_WLAN

+3VS_WLAN +3VALW

11/10 Add R632,R633(@)

11/17 Add GND on JWLAN1.40

WLAN_LED# <35>

+3VS_WLAN

0.1U_0402_16V4Z

1

C379

2

4.7U_0805_10V4Z

R458 0_0603_5%R458 0_0603_5%

1 2

R459 0_0603_5%@R459 0_0603_5%@

1 2

10/22 Reserve pull-up resister R611(@) for WLAN_LED#

01/21 Change R611 from @ to mount Change R461 from mount to @

WLAN_LED#

1

C380

C381

2

0.1U_0402_16V4Z

+3VS +3VALW

(9~16mA)

12

R461

@

10K_0402_5%

+3VS+5VS

12

R611

10K_0402_5%

10/5 Add C13/C15/C16 by Vivian

11/10 Change net : EC_TX_P80_DATA from JWLAN1.17 to JWLAN1.49 Add R634

WWAN

+3VS_WW AN

R462 0_0603_5%R462 0_0603_5%

1 2

+3VS

12/15 Reserve R642(@)

12/16 Add R643(@)

R643 0_0402_5%@R643 0_0402_5%@

R642 10K_0402_5%@R642 10K_0402_5%@

1 2 1 2

1 2

B B

11/17 Swap SATA port5 signals

SATA_DTX_C_PRX_N5<13> SATA_DTX_C_PRX_P5<13>

SATA_DTX_C_PRX_P1<13> SATA_DTX_C_PRX_N1<13>

PCH_PCIE_WAKE#<15,26,37>

+3VS

SATA_PTX_DRX_P5<13> SATA_PTX_DRX_N5<13>

SATA_PTX_DRX_N1<13> SATA_PTX_DRX_P1<13>

C489 0.01U_0402_16V7KC489 0.01U_0402_16V7K C488 0.01U_0402_16V7KC488 0.01U_0402_16V7K

C487 0.01U_0402_16V7KC487 0.01U_0402_16V7K C486 0.01U_0402_16V7KC486 0.01U_0402_16V7K

C382 0.01U_0402_16V7KC382 0.01U_0402_16V7K C384 0.01U_0402_16V7KC384 0.01U_0402_16V7K

C385 0.01U_0402_16V7KC385 0.01U_0402_16V7K C386 0.01U_0402_16V7KC386 0.01U_0402_16V7K

PCH_PCIE_WAKE#_3G

SATA_PTX_C_DRX_P5 SATA_PTX_C_DRX_N5

SATA_DTX_PRX_N5 SATA_DTX_PRX_P5

SATA_DTX_PRX_P1 SATA_DTX_PRX_N1

SATA_PTX_C_DRX_N1 SATA_PTX_C_DRX_P1

+3VS_WW AN

11/17 Change SSD_DET# from JWWAN1.47 to JWWAN1.51

SSD_DET#<33>

R469 100K_0402_5%@R469 100K_0402_5%@

A A

+3VALW

+3VS

1 2

R545 100K_0402_5%@R545 100K_0402_5%@

1 2

Copy NTUC0

JWW AN1

1

3

5

7

9

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

FOX_AS0B226-S40N-7F

+3VS_WW AN

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

+1.5VS

+UIM_PWR

UIM_DATA

UIM_RST UIM_VPP

R463 0_0402_5%R463 0_0402_5%

PLT_RST_BUF#

R464 0_0402_5%R464 0_0402_5% R465 0_0402_5%@R465 0_0402_5%@

R644 0_0402_5%@R644 0_0402_5%@ R645 0_0402_5%@R645 0_0402_5%@

USB20_N13 USB20_P13

WW AN_LED#

R467 100K_0402_5%@R467 100K_0402_5%@ R468 100K_0402_5%R468 100K_0402_5%

12/15 Add PLT_RST_BUF# on JWWAN.22 12/16 Add R644(@),R645(@)

1 2

1 2 1 2

USB20_N13 <17> USB20_P13 <17>

1 2 1 2

WW AN_LED# <35>

WW AN_OFF# <33>

PLT_RST_BUF# <17,26,37>

+3VS_WW AN +3VALW

PCH_SMBCLK <12,14,37> PCH_SMBDATA <12,14,37>

+5VS +3VS

UIM_VPP UIM_DATA

10K_0402_5%

+UIM_PWR

Reserve for SIM card does not meet rise time and pull-up is needed.

10/28 Change Net from USB20_N9,USB20_P9 to USB20_N13,USB20_P13

01/22 Change R468 from @ to mount Change R467 from mount to @

Copy NTUC0

SIM Card Conn.

JSIM1

4

GND

5

VPP

6

I/O

7

DET

12

@

R466

TAITW_PMPAT6-06GLBS7N14N0 CONN@

+3VS_WW AN

0.1U_0402_16V4Z

1

C552

2

4.7U_0805_10V4Z

1

C553

2

0.1U_0402_16V4Z

VCC RST

CLK

GND GND

C554

+UIM_PWR

1 2 3

8 9

UIM_RSTUIM_CLK UIM_CLK

1U_0603_10V4Z

C383

1

2

01/19 Add C552,C553,C554 for +3VS_WWAN

Security Classification

2009/10/10 2010/10/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

WLAN/WWAN

NAU00 M/B LA-6101P Schematics

1

of

32 48Tuesday, March 09, 2010

1.0

12/05 Change L48,L49 from SM010016810 to SM010005500

L48

+3VALW +EC_AVCC

+3VALW

10/22 Change R561 from mount to @ Change R562 from @ to mount 11/10 Change R562 from mount to @

PCH_PCIE_WAKE#_R<26>

11/05 Change the power of R566,R567 from +5VALW to +3VALW (Follow NIWE2)

+3VALW

11/03 Change R568,R569 from 2.7kohm to 2.2kohm 11/05 Change R568,R569 from mount to @ (Follow NIWE2) 11/10 Delete R568(@),R569(@),C483(@),C484(@)

1 2

BLM18AG601SN1D_2P

0.1U_0402_16V4Z

L49

1 2

BLM18AG601SN1D_2P

EC_KBRST#<18>

11/10 Change R546 from @ to mount Change D31 from mount to @

C475 22P_0402_50V8J@C475 22P_0402_50V8J@

1 2

R550 47K_0402_5%R550 47K_0402_5%

0.1U_0402_16V4Z

For ENE issue

1 2

R557 47K_0402_5%R557 47K_0402_5%

1 2

R558 47K_0402_5%R558 47K_0402_5%

PCI_PME#<17>

1 2

R566 4.7K_0402_5%R566 4.7K_0402_5%

1 2

R567 4.7K_0402_5%R567 4.7K_0402_5%

2

C472

1

R546 0_0402_5%R546 0_0402_5%

1 2

2 1

CH751H-40PT_SOD323-2

12

2

C476

1

R561 0_0402_5%@R561 0_0402_5%@

R562 0_0402_5%@R562 0_0402_5%@

EC_SMB_CK1

EC_SMB_DA1

ECAGND

D31

@

PM_CLKRUN#<15>

KSO1

KSO2

1 2

1

C473

1000P_0402_50V7K

2

12

10_0402_5%@

R549

R635

11/10 Add R635(@)

KSO[0..15]<36>

KSI[0..7]<36>

+3VALW

R560

10K_0402_5%

1 2

3

OSC

NC

2

OSC

NC

X2

32.768KHZ_12.5PF_Q13MC14610002

01/11 Change X2 from SJ100003M00 to SJ132P7KW10 (Cost down)

0.1U_0402_16V4Z

C467

0.1U_0402_16V4Z

C467

0.1U_0402_16V4Z

1

2

EC_GA20<18>

SERIRQ<13> LPC_FRAME#<13>

LPC_AD3<13> LPC_AD2<13> LPC_AD1<13> LPC_AD0<13>

CLK_PCI_LPC<17>

PLT_RST#<5,17>

EC_SCI#<18>

1 2

0_0402_5%@

KSO[0..15]

KSI[0..7]

EC_SMB_CK1<41>

EC_SMB_DA1<41>

EC_SMB_CK2<14>

EC_SMB_DA2<14>

PM_SLP_S3#<15> PM_SLP_S5#<15>

EC_SMI#<18>

PCH_TEMP_ALERT#<18>

NOVO#<36>

USER_BTN#<36>

SUS_PWR_ACK<15>

INVT_PW M<22>

FAN_SPEED1<37>

WWAN_OFF#<32> EC_TX_P80_DATA<32> EC_RX_P80_CLK<32>

ON/OFF#<34> PWR_LED#<35,36> NUM_LED#<36>

EC_PME#

+3VALW

1 2

R564 100K _0402_1%R564 100K_0402_1%

1 2

R565 100K _0402_1%R565 100K_0402_1%

12

C482 15P_0402_50V8JC482 15P_0402_50V8J

4

1

12

C485 15P_0402_50V8JC485 15P_0402_50V8J

+3VALW

C474

1000P_0402_50V7K

C474

1000P_0402_50V7K

C470

0.1U_0402_16V4Z

C470

C468

1

2

PM_CLKRUN#_R

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

0.1U_0402_16V4Z

C469

0.1U_0402_16V4Z

C469

0.1U_0402_16V4Z

EC_GA20 KB_RST#_EC SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMPA LPC_AD0

EC_RST# EC_SCI#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

PM_SLP_S3# PM_SLP_S5# EC_SMI# PCH_TEMP_ALERT# NOVO# USER_BTN# SUS_PWR_ACK INVT_PW M FAN_SPEED1 WWAN_OFF# EC_TX_P80_DATA EC_RX_P80_CLK ON/OFF# PWR_LED# NUM_LED#

XCLKI XCLKO

1

2

10

12 13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

C471

1000P_0402_50V7K

C471

1000P_0402_50V7K

1

2

U30

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

LPC & MISC

LAD0

PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24

Int. K/B

KSO5/GPIO25

Matrix

KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47

6

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO0 8 LID_SW# /GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C EC_PME#/GP IO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LE D#/GPIO19 NUMLED#/GPIO1A

XCLK1 XCLK0

KB926QFA1_LQFP128

SM Bus

9

22

33

96

111

125

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GND

11

24

35

94

113

+EC_AVCC

67

AVCC

INVT_PW M/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B AD4/GPIO42

SELIO2#/AD5/GP IO43

DAC_BRIG/D A0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3 E

DA3/GPIO3F

PSCLK1/GPIO4 A PSDAT1/GPIO4B PSCLK2/GPIO4 C PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SEL IO#/GPIO50

BATT_CHGI_ LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK 32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

GPO

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPI

AGND

69

E0 Version

SPICS#

GPXO10 GPXO11

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

21 23 26 27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

KB926 SPI STRAP PIN

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

SA00001J5A0

ECAGND

MUTE_BTN#

USER_BTN#

12

@

R571

R571 20M_0603_5%

20M_0603_5%

11/02 Delete U31,Q36,R570

XCLKO

XCLKI

10/21 Change U30 from SA00001J580 to SA00001J5A0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

KILL_SW# BEEP# FAN_PWM ACOFF

BATT_OVP ADP_I VOUTX VOUTY BRD_IN

11/02 Delete net : KB_L#DA

BATT_SEL_EC IREF CHGVADJ

EC_MUTE# USB_ON# G_SELFTEST T/P_LOCK_LED# TP_CLK TP_DATA

EN_WOL# ME_EN# LID_SW#

EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL#

SSD_DET# EC_GENPD FSTCHG CHARGE_LED0# CAPS_LED# CHARGE_LED1# KB_LED# SYSON VR_ON ACIN

EC_RSMRST# EC_LID_OUT# EC_ON H_PROCHOT#_EC EC_PWROK BKOFF# WL_OFF# MUTE_BTN# BT_ON#

PM_SLP_S4# ENBKL EC_EAPD AC_PRESENT SUSP# PBTN_OUT# EC_PME#

C480

1

4.7U_0603_6.3V6M

2

Compal Secret Data

2009/10/10 2010/10/10

Compal Secret Data

KILL_SW# <35> BEEP# <29> FAN_PWM <37>

ACOFF <40,42>

BATT_TEMPA <41>

T15PAD@T15PAD

@

ADP_I <42> VOUTX <25> VOUTY <25>

BATT_SEL_EC <42> IREF <42> CHGVADJ <42>

R555 10K_0402_5%@R555 10K_0402_5%@

1 2

EC_MUTE# <29> USB_ON# <31> G_SELFTEST <25>

T/P_LOCK_LED# <35> TP_CLK <35> TP_DATA <35>

R608 10K_0402_5%@R608 10K_0402_5%@

1 2

R556 4.7K_0402_5%R556 4.7K_0402_5%

1 2

EN_WOL# <26> ME_EN# <13>

LID_SW# <35>

EC_SI_SPI_SO <36> EC_SO_SPI_SI <36> EC_SPICLK <36> EC_SPICS#/FSEL# <36>

SSD_DET# <32> EC_GENPD <25> FSTCHG <42> CHARGE_LED0# <35> CAPS_LED# <36> CHARGE_LED1# <35>

SYSON <37,38,44> VR_ON <47> ACIN <38,40>

EC_RSMRST# <15> EC_LID_OUT# <14> EC_ON <34>

EC_PWROK <15> BKOFF# <22> WL_OFF# <32> MUTE_BTN# <36> BT_ON# <35>

PM_SLP_S4# <15> ENBKL <16> EC_EAPD <29> AC_PRESENT <15> SUSP# <37,38,42,45> PBTN_OUT# <15>

11/10 Change ME_EN to ME_EN#

11/02 Change net from KB_LIGHT# to KB_LIGHT#_R

11/05 Change net from KB_LIGHT#_R to KB_LED# (EC Recommend)

R551 0_0402_5%R551 0_0402_5%

11/02 Delete R552

R636 0_0402_5%R636 0_0402_5%

1 2

11/05 Delete net : EC_SWI# on U30.103 (Follow NIWE2) 11/12 Add R636, net : H_PROCHOT#

11/10 Delete C481(@)

Deciphered Date

+3VALW

12

11/03 Add AC_PRESENT on U30.115

BRD_IN

R547 0_0402_5%@R547 0_0402_5%@

1 2

USB_ON#

R548 10K_0402_5%@R548 10K_0402_5%@

1 2

12/07 Change R548(@) connection from GND to +3VALW

TP_CLK

R553 4.7K_0402_5%R553 4.7K_0402_5%

1 2

R554 4.7K_0402_5%R554 4.7K_0402_5%

1 2

C477 100P_0402_50V8JC477 100P_0402_50V8J

1 2

C478 100P_0402_50V8JC478 100P_0402_50V8J

1 2

C479 100P_0402_50V8JC479 100P_0402_50V8J

KB926D3 : Pull-up KB926E0 : Pull-down

TP_DATA

BATT_OVP

BATT_TEMPA

ACIN

VOUTZ <25>

+3VALW

+5VS

10/21 Reserve R608(@) for EC strap pin

11/10 Change R556 from @ to mount

KB_LIGHT# <22>

H_PROCHOT# <5,47>

11/03 Delete U29

11/05 Delete D32(@), move to close to JBATT1 (ESD Recommend)

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

EC ENE-KB926

NAU00 M/B LA-6101P Schematics

33 48Tuesday, March 09, 2010

of

1.0

A

B

C

D

E

Power Button

1 1

ON/OFF switch

ON/OFFBTN#<36>

12/04 Delete SW1

2 2

EC_ON

EC_ON<33>

R490

10K_0402_5%

+3VALW

D24

2

1

DAN202UT106_SC70-3

3

2

G

1 2

R489

100K_0402_5%

1 2

51_ON#

13

D

Q24

Q24 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

ON/OFF# <33>

51_ON# <36,40>

9/10 Change symbol of Q48 to SC70-3

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Power OK/PBN/TP Lock/LED

NAU00 M/B LA-6101P Schematics

34 48Tuesday, March 09, 2010

of

E

of

1.0

5

4

3

2

1

Lid Switch

(Hall Effect Switch)

D D

C407

0.1U_0402_16V4Z

A3212ELHLT-T_SOT23W-3

KILL Switch

C C

LED

B B

R595 820_0402_5%R595 820_0402_5%

+5VS

R499 820_0402_5%R499 820_0402_5%

+5VS

R500 820_0402_5%R500 820_0402_5%

+5VALW

2

1

U22

1 2

+3VALW

2

OUTPUT

1

VDD

GND

12

R495

R495 47K_0402_5%

47K_0402_5%

LID_SW#

3

1

C411

C411 10P_0402_50V8J

10P_0402_50V8J

2

DAN217T146_SC59-3

2 1

LID_SW# <33>

9/1 Del D19 and change net name to LID_SW#

+3VALW

11/11 Correct D25 footprint

2

3

D25

<EMI>

@

1

KILL_SW#

5

3

SW2

11223

SW2

G14G2

1BS003-1210L_3P

LED5

HT-191NB_BLUE_0603

LED1

HT-191NB_BLUE_0603

LED2

HT-191NB_BLUE_0603

01/21 Change R650 from @ to mount Change R596 from mount to @

WLAN_LED#<32>

WWAN_LED#<32>

Blue

BT_LED#

Blue

WLAN_WWAN_LED#

Blue

PWR_LED#

+3VALW

Copy JHXXX

R498

100K_0402_5%

1 2

11/11 Correct SW2 footprint

11/11 Correct U33 footprint

WLAN_LED#

WWAN_LED#

KILL_SW# <33>

PWR_LED# <33,36>

BT

12/17 Change R491,C405,R494,C406,Q25,C410,Q26,R496 from mount to BT@

20mil

BT_ON#<33>

+3VALW

+3VS

R491 0_0603_5%BT@R491 0_0603_5%BT@

R492 0_0603_5%@R492 0_0603_5%@

C405

BT@

0.1U_0402_16V4Z

BT@

1 2

R494

R494 10K_0402_5%

10K_0402_5%

01/07 Change Q25 from SB923010020 to SB934130000

4.7U_0603_6.3V6K

11/10 Delete C408 11/10 Change C409 from mount to @

01/20 Add R650(@)

12

R650

10K_0402_5%

4

+5VS

12

13

D

2

G

S

R596

@

10K_0402_5%

Q38

Q38 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

13

2

G

WLAN_WWAN_LED#

D

S

Q39

Q39 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

+3VS

5

2

P

B

Y

1

A

G

U33

3

NC7SZ08P5X_NL_SC70-5

12

12/05 Change Q25 from SB934130000 to SB923010020 12/09 Add +3V_BT net name

+3V_BT

20mil

1

C406

BT@

1U_0603_10V4Z

S

Q25

BT@

D

AO3413_SOT23-3

1 3

1

2

C410

BT@

0.1U_0402_16V4Z

2

C409

G

@

+BT_VCC

20mil

SSM3K7002FU_SC70-3

BT_LED#

Q26

BT@

+5VS

D

S

12

13

R493

10K_0402_5%

BT_ACTIVE<32> USB20_P11<17> USB20_N11<17>

2

G

12

R496

BT@

10K_0402_5%

Copy NIWE2 Conn.

+BT_VCC

BT_ACTIVE USB20_P11 USB20_N11 BTON_LED

JBT1

1

2

3

4

5

7

5

G1

6

8

6

G2

ACES_87213-0600G

CONN@

RTC

11/10 Delete D26,C412,R497, Add R630,C511 (Follow NIWE2)

TP_CLK TP_DATA

+RTCBATT

+5VS

JTP1

4

3

2

6

2

6

1

5

1

5

ACES_85201-0405

CONN@

TP_CLK TP_DATA

2

3

D36

D36 PJSOT05C_SOT23-3

PJSOT05C_SOT23-3

@

1

11/11 Correct D36 footprint

+RTCVCC

2

1

Touch Pad

+5VS

1

C413

0.1U_0402_16V4Z

2

R630 100_0603_1%R630 100_0603_1%

1 2

C511

0.1U_0402_16V4Z

TP_CLK<33>

TP_DATA<33>

11/09 Change JTP1 pin definition (Follow rubber dome pin defintion)

A A

LED6

R501 300_0402_5%R501 300_0402_5%

+5VALW

1 2

R502 300_0402_5%R502 300_0402_5%

1 2

10/30 Add LED6, change LED3

5

2 1

LED6 HT-191UD_Amber_0603

HT-191UD_Amber_0603

LED3

HT-191NB_BLUE_0603

11/11 Correct LED6 footprint

Amber

CHARGE_LED1#

Blue

CHARGE_LED0#

4

CHARGE_LED1# <33>

CHARGE_LED0# <33>

+5VS

R503

1 2

4.3k_0402_5%

2 1

LED4

HT-191NB_BLUE_0603

R503

01/26 Change R503 from 820ohm to 4.3kohm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

2

T/P_LOCK_LED#

Title

Size Document Number Rev

Date: Sheet

T/P_LOCK_LED# <33>

Compal Electronics, Inc.

LID/RTC/BT/TP/KILL SW/LED

NAU00 M/B LA-6101P Schematics

1

1.0

of

35 48Tuesday, March 09, 2010

of

35 48Tuesday, March 09, 2010

of

35 48Tuesday, March 09, 2010

INT_KBD Conn.

KSI[0..7]

KSO[0..15]

KSI[0..7] <3 3>

KSO[0..15] <33>

FingerPrint/B Conn.

D27

+3VS

USB20_R_N9

D27

6

CH3

5

Vp

4

CH4

CM1293A-04SO SOT23-6

<EMI> @

12/22 Change D27 from FP@ to @

CH2

CH1

USB20_R_P9

3

2

Vn

1

Function/B Conn.

Copy KIUE0

JKB1

KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0

JKB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

G1

26

G2

ACES_85202-24051

CONN@

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

03/02 Add C555 (10uF) for FP power

12/17 Change D27,R504,R505 from mount to FP@

10/28 Change Net from USB20_N10,USB20_P10,USB20_R_P 10,USB20_R_N10 to USB20_N9,USB20_P9,USB20_R_P9,USB20_R_N9 11/11 Correct L47 footprint

USB20_P9<17> USB20_N9<17>

USB20_P9 USB20_N9

L47

@L47

@

4

1

WCM2012F2S-900T04_0805

R504 0_0402_5%FP@R504 0_0402_5%FP@

1 2

R505 0_0402_5%FP@R505 0_0402_5%FP@

1 2

3

2

USB20_R_P9 USB20_R_N9

10U_0805_10V4Z

+5VS

Copy IFT00

1 2 3 4

Copy IFT00

JFUN1

MUTE_BTN#<33> USER_BTN#<33>

MUTE_BTN# USER_BTN#

JFUN1

1

5

1

5

2

6

2

6

3

4

ACES_85201-0405

CONN@

+5VS

1

C555

2

JFP1

5

1

5

6

2

6 3 4

ACES_85201-0405

CONN@

KSO15

C414 100P_0402_50V8J@C414 100P_0402_50V8J@

KSO14

KSO13

KSO12

KSI0

KSO11

KSO10

KSI1

KSI2

KSO9

KSI3

KSO8

1 2

C416 100P_0402_50V8J@C416 100P_0402_50V8J@

1 2

C418 100P_0402_50V8J@C418 100P_0402_50V8J@

1 2

C420 100P_0402_50V8J@C420 100P_0402_50V8J@

1 2

C422 100P_0402_50V8J@C422 100P_0402_50V8J@

1 2

C424 100P_0402_50V8J@C424 100P_0402_50V8J@

1 2

C426 100P_0402_50V8J@C426 100P_0402_50V8J@

1 2

C428 100P_0402_50V8J@C428 100P_0402_50V8J@

1 2

C430 100P_0402_50V8J@C430 100P_0402_50V8J@

1 2

C432 100P_0402_50V8J@C432 100P_0402_50V8J@

1 2

C434 100P_0402_50V8J@C434 100P_0402_50V8J@

1 2

C436 100P_0402_50V8J@C436 100P_0402_50V8J@

1 2

EC SPI ROM

EC_SPICS#/FSEL#<33>

R507 4.7K_0402_5%R507 4.7K_0402_5%

+3VALW

R509 4.7K_0402_5%R509 4.7K_0402_5%

1 2 1 2

KSO7

C415 100P_0402_50V8J@C415 100P_0402_50V8J@

1 2

KSO6

C417 100P_0402_50V8J@C417 100P_0402_50V8J@

1 2

KSO5

C419 100P_0402_50V8J@C419 100P_0402_50V8J@

1 2

KSO4

C421 100P_0402_50V8J@C421 100P_0402_50V8J@

1 2

KSO3

C423 100P_0402_50V8J@C423 100P_0402_50V8J@

1 2

KSI4

C425 100P_0402_50V8J@C425 100P_0402_50V8J@

1 2

KSO2

C427 100P_0402_50V8J@C427 100P_0402_50V8J@

1 2

KSO1

C429 100P_0402_50V8J@C429 100P_0402_50V8J@

1 2

KSO0

C431 100P_0402_50V8J@C431 100P_0402_50V8J@

1 2

KSI5

C433 100P_0402_50V8J@C433 100P_0402_50V8J@

1 2

KSI6

C435 100P_0402_50V8J@C435 100P_0402_50V8J@

1 2

KSI7

C437 100P_0402_50V8J@C437 100P_0402_50V8J@

1 2

11/25 Change U23 from SA00002C100 to SA00003GK00

U23

EC_SPICS#/FSEL#

SPI_WP# SPI_HOLD#

150mils

U23

1

CE#

3 7 4

VDD

WP#

SCK HOLD# VSS

MX25L2005CMI-12G_SOP8

SA00003GK00

256kB

SI

SO

EC_SPICLK_R

8 6 5 2

11/04 Change Net from EC_SPICLK to EC_SPICLK_R on R512.2

Layout Note : Please place R508,R510,R512,C439 close to U30

EC_SPICLK_R EC_SO_SPI_SI_R EC_SI_SPI_SO_R

R512

20mils

R508 0_0402_5%R508 0_0402_5%

1 2

R510 0_0402_5%R510 0_0402_5%

1 2

R511 0_0402_5%R511 0_0402_5%

1 2

@R512

@

0_0402_5%

C4380.1U_0402_16V4Z C4380.1U_0402_16V4Z

12

@

C439

12

33P_0402_50V8K

11/10 Delete R506

EC_SPICLK EC_SO_SPI_SI EC_SI_SPI_SO

+3VALW

EC_SPICLK <33>

EC_SO_SPI_SI <33>

EC_SI_SPI_SO <33>

Power/B Conn.

Copy KSW01

JPWR1

1

2

ON/OFFBTN#

3

NOVO_BTN#

4

PWR_LED#

5

CAPS_LED#

6

NUM_LED#

7

PCH_SATALED#

8

9

10

11

GND

12

GND

ACES_85201-1005N

CONN@

+5VALW +5VS

ON/OFFBTN# <34>

PWR_LED# <33,35>

CAPS_LED# <33>

NUM_LED# <33>

PCH_SATALED# <13>

+3VALW

R544

R544 100K_0402_5%

100K_0402_5%

D30

NOVO#<33>

51_ON#<34,40>

NOVO#

51_ON#

1 2

D30

2

1

3

DAN202UT106_SC70-3

NOVO_BTN#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/10/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

BIOS/KBD/Fun_B/PWR_B/FP_B

NAU00 M/B LA-6101P Schematics

36 48Tuesday, March 09, 2010

of

1.0

New Card Power Switch

+3VS

0.1U_0402_16V4Z

PLT_RST_BUF#

SYSON

SUSP#

+1.5VS

CP_PE#

U24

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin

AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

G577NSR91U TQFN

1.5Vout

3.3Vout

OC#

PERST#

GND

NC

C442

0.1U_0402_16V4Z

12

C443

0.1U_0402_16V4Z

12

C444

+3VALW +3VALW_CARD1

PLT_RST_BUF#<17,26,32>

SYSON<33,38,44>

SUSP#<33,38,42,45>

+3VALW

11/09 Delete R602(@) Change net from CP_USB# to CP_PE# (Follow NIWE2)

R513 100K_0402_5%@R 513 100K_0402_5%@

12

(Internal Pull High to AUXIN) (Internal Pull High to AUXIN)

11/17 Add R637,R638

+1.5VS_CARD1_R

11 13

+3VS_CARD1_R

3 5

15

19

PERST1#

8

16

7

R637 0_0603_5%R637 0_0603_5%

1 2

R638 0_0603_5%R638 0_0603_5%

1 2

+1.5VS_CARD1

+3VS_CARD1

C440

0.1U_0402_16V4Z

C445

0.1U_0402_16V4Z

C447

0.1U_0402_16V4Z

+3VS_CARD1

1

2

+1.5VS_CARD1

1

2

+3VALW_CARD1

1

2

1

C441

@

4.7U_0805_10V4Z

2

1

C446

@

4.7U_0805_10V4Z

2

1

C448

@

4.7U_0805_10V4Z

2

New Card Socket

10/28 Change Net from USB20_N4,USB20_P4 to USB20_N10, USB20_P10

USB20_N10<17>

PCH_SMBCLK<12,14,32>

PCH_SMBDATA<12,14,32>

+1.5VS_CARD1

PCH_PCIE_WAKE#<15,26,32>

+3VALW_CARD1

+3VS_CARD1

EXP_CLKREQ#<14> CP_PE#<18> CLK_PCIE_EXP#<14> CLK_PCIE_EXP<14>

PCIE_DTX_C_PRX_N3<14> PCIE_DTX_C_PRX_P3<14>

PCIE_PTX_C_DRX_N3<14> PCIE_PTX_C_DRX_P3<14>

USB20_P10<17>

CP_PE#

PERST1#

EXP_CLKREQ# CP_PE#

Copy KIUE0

JEXP1

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

GND28GND

SANTA_130801-5_RT

CONN@

30 29

FAN1 Conn

1 2

+5VS

R515 0_0603_5%R515 0_0603_5%

9/1 Del U3/C11/C12/R8

+VCC_FAN1

11/10 Delete D28,D29,C449,C450

12/10 Change H17 from H_3P6X5P6 to H_3P6X4P6

11/14 Add H26 H_2P8

11/11 Change H12~H15 to H_3P3

H1

H2

H_2P8

@

1

+3VS

12

R514

R514 10K_0402_5%

10K_0402_5%

FAN_SPEED1<33>

11/10 Delete C451

FAN_PWM<33>

40mil

+VCC_FAN1

FAN_PWM

JFAN1

1

2

3

4

5

G5

6

G6

ACES_85205-04001

CONN@

Copy NIWE2

10/23 Change JFAN1 to NIWE2 FAN connector

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H17

H17 H_3P6X4P6

H_3P6X4P6

@

1

@

1

FD1

FD1 FIDUCIAL_C40M80

FIDUCIAL_C40M80

Compal Secret Data

2009/10/10 2010/10/10

Compal Secret Data

H3

H_2P8

@

1

H_3P3

H18

H18 H_3P6X5P6

H_3P6X5P6

@

1

@

1

FD2

FD2 FIDUCIAL_C40M80

FIDUCIAL_C40M80

Deciphered Date

H4

@

1

H12

@

1

H5

H_2P8

@

1

H13

H_3P3

@

1

H19

H19 H_4P1X3P1

H_4P1X3P1

1

@

1

FD3

FD3 FIDUCIAL_C40M80

FIDUCIAL_C40M80

H6

H_2P8

@

1

H7

H_2P8

@

1

H14

H_3P3

@

1

@

1

FD4

FD4 FIDUCIAL_C40M80

FIDUCIAL_C40M80

H8

H_2P8

@

1

H15

H_3P3

@

1

H20

H20 H_6P0

H_6P0

@

1

Date: Sheet

H_2P8

@

1

H16

H_3P6

@

1

H22

H21

H_3P8

@

1

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Compal Electronics, Inc.

NAU00 M/B LA-6101P Schematics

H_2P8

@

1

H26

H_2P8

@

1

H23

H24

H_3P8

@

1

FAN & Screw Hole

H24

H_3P8

@

1

H25

H11

H10

H9

H8

@

1.0

37 48Tuesday, March 09, 2010

1.0

of

A

B

C

D

E

+5VALW TO +5VS

R517

10K_0402_5%

SUSP

+5VALW

5VS_GATE

12

2

G

Q5

U25

8

S

D

7

S

D

6

S

D

5

G

D

SI4800BDY-T1-E3_SO8

SB548000310

R641

1 2

10K_0402_5%

13

D

S

12/07 Add R641 (10kohm)

11/10 Change R517 from 200kohm to 20kohm (Follow NIWE2)

12/17 Change R517

1 1

from 20kohm to 10kohm

B+

SSM3K7002FU_SC70-3

1 2 3 4

+5VS

1U_0603_10V4Z

5VS_GATE_1

1

C454

0.1U_0603_25V7K

2

+3VALW TO +3VS

+3VALW

U26

8

S

D

R522

7 6 5

12

2

G

Q7

S

D

S

D

G

D

SI4800BDY-T1-E3_SO8

SB548000310

3VS_GATE

13

D

S

11/10 Change R522 from 200kohm to 47kohm (Follow NIWE2)

2 2

B+

47K_0402_5%

SUSP

SSM3K7002FU_SC70-3

1 2 3 4

+3VS

1U_0603_10V4Z

1

C456

0.1U_0603_25V7K

2

+1.5V to +1.5VS

+1.5V

U27

8 7 6

R528

12

2

G

Q8

ACIN

R532

22_0603_5%

2

G

A

5

13

11/06 Delete R533,Q32

11/10 Change R528 from 510kohm to 100kohm (Follow NIWE2)

3 3

B+

100K_0402_5%

SUSP

SSM3K7002FU_SC70-3

ACIN<33,40>

4 4

SSM3K7002FU_SC70-3

11/23 Change R532 from SD013470080(470ohm) to SD000001R80(22ohm) (Follow Intel Rec ommend)

1 2

13

D

S

Q31

1

S

D

2

S

D

3

S

D

4

G

D

SI4800BDY-T1-E3_SO8

SB548000310

1.5VS_GATE

12

R529

D

@

510K_0402_5%

S

510K_0402_5%

13

D

2

G

S

1

C462

0.1U_0603_25V7K

2

@

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3 Q28

Q28

For EMI Require 1/21 Put near Right side of DIMM

0.1U_0402_16V4Z

@

SUSP

1

C453

2

SYSON<33,37,44>

@

1

C452

C455

2

R516

@

470_0603_5%

1 2

13

D

SUSP

2

G

Q40

S

SSM3K7002FU_SC70-3

12/04 Change Q5,Q6,Q7,Q8 from SB00000AR00 to SB000009610 Add Q40,Q41,Q42,Q43(SB000009610) 12/04 Change Q40,Q41,Q42,Q43,R516,R521,R527,R518 from mount to @

1

2

R521

@

470_0603_5%

1 2

13

D

2

G

Q42

S

SSM3K7002FU_SC70-3

12/18 Change U27 from SB000007O00 to SB548000310

Optional, if +1.5VS can combine with +1.5V_1

+1.5VS

1

C461

2

1U_0603_10V4Z

9/10 Change symbol of Q39 to SC70-3

R534

@

470_0603_5%

1 2

13

D

2

G

Q33

S

SSM3K7002FU_SC70-3

11/25 Change R534,R535,Q33,Q34 from mount to @

@

R527

@

470_0603_5%

1 2

13

D

G

Q43

S

SSM3K7002FU_SC70-3

1 2

13

D

S

11/17 Delete R526(@)

SUSP

2

@

R535

@

470_0603_5%

2

G

Q34

@

Q34

@

SSM3K7002FU_SC70-3

+1.5V+1.8VS+1.1VS_VTT+0.75VS

R536

R536 470_0603_5%

470_0603_5%

@

1 2

13

D

SSM3K7002FU_SC70-3

S

9/10 Change symbol of Q44/Q64/Q66 to SC70-3

B

SYSON#SUSPSUSPSUSP

2

G

Q35

@

9/10 Change symbol of Q37/Q38 to SC70-3

R518

@

100K_0402_5%

1 2

13

D

2

G

12

Q6

@

Q6

@

S

SSM3K7002FU_SC70-3

10K_0402_5%

SYSON#

SYSON

R523

11/09 Change R523 from 100kohm to 10kohm

11/10 Change R531 from 100kohm to 20kohm (Follow NIWE2)

11/25 Change R531 from 20kohm to 100kohm

B+

R531

1 2

33K_0402_5%

SSM3K7002FU_SC70-3

11/23 Change C457,C458,C459,C460,U28,R531,C464,Q30,C463,R530,Q29 from @ to mount (For Intel S3 Power Reduction.)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/10 2010/10/10

12/04 Add R639, Change R520 from mount to @

01/21 Change R520 from @ to mount Change R639 from mount to @

01/21 Change R520 from 100kohm to 10kohm

+1.5V

C457 0.1U_0402_16V4ZC457 0.1U_0402_16V4Z

C458 0.1U_0402_16V4ZC458 0.1U_0402_16V4Z

C459 0.1U_0402_16V4ZC459 0.1U_0402_16V4Z

C460 0.1U_0402_16V4ZC460 0.1U_0402_16V4Z

JUMP_43X118@

8 7 6 5

1.5V_1_GATE SUSP

SUSP

2

G

Q30

Compal Secret Data

+1.5V_1

1 2

J4

2

112

J5

2

112

U28

D D D D

SI4800BDY-T1-E3_SO8

SB548000310

R640

47K_0402_5%

13

D

S

12/18 Change U28 from SB000007O00 to SB548000310

1

S

2

S

3

S

4

1.5V_1_GATE_1

G

12

1

C464

0.1U_0603_25V7K

2

12/04 Add R640 12/05 Change R640 from 10kohm to 20kohm 12/15 Change R640 from 20kohm to 47kohm 12/15 Change R531 from 100kohm to 33kohm

Deciphered Date

For Calpella CPU S3 DRAM Power

(1.5V_CPU VDDQ)

250mil(6A)

1

C463

0.1U_0402_16V4Z

2

D

R530

220_0603_5%

11/23 Change R530 from SD013470080(470ohm) to SD013220080(220ohm)

1 2

13

D

2

G

Q29

S

SSM3K7002FU_SC70-3

+5VALW+5VALW RTCVREF

12

R520

R639

@

100K_0402_5%

SUSP<44>

SUSP#<33,37,42,45>

Title

Size Document Number Rev

B

Date: Sheet

SUSP

12

R525

10K_0402_5%

Compal Electronics, Inc.

NAU00 M/B LA-6101P Schematics

R520

10K_0402_5%

1 2

13

D

2

G

Q41

S

SSM3K7002FU_SC70-3

DC Interface

E

38 48Tuesday, March 09, 2010

of

1.0

A

B

COMPAL CONFIDENTIAL

C

D

E

MODEL NAME: PCB NAME: REVISION:

1 1

DATE:

AC MODE

BATT MODE

2 2

A1

VIN

BATT

B1

V

PU5

KBLA0 Power Sequence Block Diagram LA4811P

2008/12/04

SBPWR_EN

A3

B4

B5

+3VALW

A5

V

B7

2

V

2

V

A2

PU4

V

B+

V

B2

B+

V

PQ1

EC

EC_RSMRST#

VV

A5

A4

ON/OFF

B7

B6

V

PBTN_OUT#

V

B3

51ON#

EC_ON

SLP_S3# SLP_S4# SLP_S5#

SYSON

7 SYSON#

SUSP#,SUSP

2

4

PCH_RSMRST#

5

6

8

U28,+3V

V

Q5,+5V

3

PCH

VV

+1.5V

V

PU6

V

U20

+3V +5V

V

PM_DRAM_PWRGD

H_CPUPWRGD

PLT_RST#

8a

12

SYS_PWROK

VS_ON

13

V

14

V

15

V

H_VTTPWRGD

PU13 +1.1VS_VTT

CPU

(UMA)

8c

V

GFXVR_EN

V

PU12 MAX17028 Power Up

8b

V

11a

VGATE EC_PWROK

11b

U39

3 3

V

+5VS

U19

V

+3VS

U26

VV

VS_ON

(DIS)

VGA_ON

PU7

V V

+1.05VS

MXM

V

+1.5VS

PU8 +0.75V

VR_ON

4 4

A

B

9

PU11

V

+CPU_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

VGA_PWRGD

CLK_ENABLE#10

2009/10/10 2010/10/10

(DIS)

8c

GFX_CORE_PWRGD

U36

V

CK505

Compal Secret Data

Deciphered Date

(UMA)

8c

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Power Sequence Block Diagram

NAU00 M/B LA-6101P Schematics

39 48Friday, February 26, 2010

of

E

of

1.0

A

SINGA_2DW- 0268-B16@

SINGA_2DW- 0268-B16@ JDCIN1

JDCIN1

1 1

APDIN APDIN1

4

3

2

1

PF101

7A_24VDC_429007.W RML

21

PL101

SMB3025500YA_2P

1 2

12

100P_0402_50V8J

0.1U_0603_25V7K@

PC101

100P_0402_50V8J

PC103

PC102

1000P_0402_50V7K

Vin Detector Min. typ. Max.

B

ACIN

VIN

Precharge detector

Min. typ. Max. L-->H 14.991V 15.381V 15.782V H-->L 13.860V 14.247V 14.621V

12

PC104

0.1U_0603_25V7K@

12

100P_0402_50V8J

PC105

PC106

1000P_0402_50V7K

VIN

12

PD102

PD102 LL4148_LL34-2

LL4148_LL34-2

C

D

BATT ONLY

Precharge detector

Min. typ. Max. L-->H 7.196V 7.349V 7.505V H-->L 6.138V 6.214V 6.056V

PR102

PR102 1K_1206_5%

1K_1206_5%

1 2

PR103

PR103 1K_1206_5%

1K_1206_5%

1 2

PR104

PR104 1K_1206_5%

1K_1206_5%

1 2

PR105

100K_0402_1%

12

PQ102

TP0610K-T1-E3_SOT23-3

12

PR106

100K_0402_1%

13

2

L-->H 17.430V 17.901V 18.384V H-->L 16.976V 17.262V 17.728V

2

12

5

+

6

-

12

+RTCBATT

+CHGRTC

13

PQ103

DTC115EUA_SC70-3

PC110

0.01U_0402_25V7K

PC111

1000P_0402_50V7K

PQ105

SSM3K7002FU_SC70-3

PR101

PR101 1M_0402_1%

1M_0402_1%

1 2

VINDE-2

PD105

PR126

3

2

PR115

PR115 10K_0402_5%

10K_0402_5%

12

PR125

VS

+

-

12

8

P

O

G

PU102A

PU102A LM393DG_SO8

LM393DG_SO8

4

12

RTCVREF

51ON-2

1 2

12

PC107

0.01U_0402_25V7K

1

LLZ4V3B_LL34-2

3.3V

TP0610K-T1-E3_SOT23-3

PC114

0.22U_0603_25V7K

51ON-3

2 2

PC108

3 3

VIN

12

PR108

84.5K_0402_1%

PR111

PR111 22K_0402_1%

12

PR112

BATT+

51_ON#<34,36>

22K_0402_1%

1 2

20K_0402_1%

CHGRTCP

VINDE-3

12

PC109

0.1U_0402_16V7K

LL4148_LL34-2

PR124

200_0603_5%

1 2

100K_0402_1%

22K_0402_1%

1 2

VINDE-1

12

0.068U_0603_16V7K

RTCVREF

PU101

4 4

+CHGRTC

PR129

560_0603_5%

1 2

A

3.3V

12

APL5156-33DI-TRL_SOT89-3

3

VOUT

PC116

PC116 10U_0603_6.3V6M

10U_0603_6.3V6M

PU101

GND

2

VIN

1

CHGRTCINRTCVREF-1

PD101

PQ101

VIN

12

PR109

2 1

68_1206_5%

2

12

PR127

PR127 200_0603_5%

200_0603_5%

12

PC117

PC117 1U_0805_25V6K

1U_0805_25V6K

10K_0805_5%

PR120

13

PR110

PR110 10K_0402_1%

10K_0402_1%

1 2

PACIN

12

PR114

10K_0402_5%

VIN

PD104

LL4148_LL34-2

1 2

51ON-1

12

PC115

0.1U_0603_25V7K

B

12

PR121

PR121 68_1206_5%

68_1206_5%

ACOFF<33,42>

ACIN <33,38>

PR113

7

PU102B

LM393DG_SO8

PR113

2.2M_0402_5%

VS

8

P

O

G

4

PR122

PR122 10K_0402_5%

10K_0402_5%

PACIN <42>

VL

12

PR117

PD103

RB715F_SOT323-3

MAINPWON<41,43>

ACON<42>

2

3

100K_0402_1%

1

12

PC113

0.1U_0603_25V7K

RTCVREF

VS

PR128

JRTC1

-+

MAXEL_ML1220T10@

12

PR128

560_0603_5%

1 2

PD106

1 2

RB751V-40_SOD323-2

RTC Battery

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/01/06

Compal Secret Data

Deciphered Date

C

12

PR107

100K_0402_1%

13

2

12

PR118

PRG++

13

D

S

Size Document Number Rev

Date: Sheet

205K_0402_1%

2

G

Title

Custom

PQ104

DTC115EUA_SC70-3

PR123

PR123 47K_0402_5%

47K_0402_5%

13

PQ106

PQ106 DTC115EUA_SC70-3

DTC115EUA_SC70-3

Compal Electronics, Inc.

DCIN & DETECTOR

B+

12

PR116

499K_0402_1%

12

PC112

PR119

499K_0402_1%

0.01U_0402_25V7K

PACIN

12

2

D

+5VALW

40 48Tuesday, March 09, 2010

0.1

of

A

1 1

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 95 degree C Recovery at 56 degree C

JBATT1

VMB2

JBATT1

1

2

EC_SMCA

3

2 2

3 3

3

EC_SMDA

4

5

6

7

8

GND

9

GND

SUYIN_200082MR007G100ZR@

12

PR201

100_0402_1%

PR201

100_0402_1%

PR202

100_0402_1%

PR202

100_0402_1%

2

3

PD201

PJSOT24C_SOT23-3@

1

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

21

2

3

PD202

@

1

PESD5V0U2BT 3P C/C SOT23 ESD

1 2

PR208

6.49K_0402_1%

1 2

PR209

PR209 10K_0402_5%

10K_0402_5%

VMB

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 <33>

EC_SMB_DA1 <33>

+3VALW

BATT_TEMPA <33>

PL201

SMB3025500YA_2P

1 2

A/D

BATT+

12

PC202

0.01U_0402_25V7K

0.1U_0603_25V7K

PC203

VL

12

PU201

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

PR203

10K_0402_1%

8

7

6

5

1 2

PR207

47K_0402_1%@

1 2

12

PH202

PH202 100K_0402_1%_TSM0B104F4251RZ@

100K_0402_1%_TSM0B104F4251RZ@

12

PR204

PR204 20K_0402_1%

20K_0402_1%

PR206

8.87K_0402_1%

1 2

12

PH201

PH201 100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ

1 2

PR205

PR205 100K_0402_1%@

100K_0402_1%@

MAINPWON <40,43>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2010/01/062009/10/10

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN / OTP

41 48Tuesday, March 09, 2010

D

41 48Tuesday, March 09, 2010

0.1

of

5

PQ301

FDS6675BZ_SO8

DTA144EUA_SC70-3

13

2

PQ307

PACIN

PQ311

DTC115EUA_SC70-3

ACOFF

8 7

5

PQ304

2

1 3

PQ305

DTC115EUA_SC70-3

PR313

3K_0402_1%

1 2

2

4

VIN

D D

C C

12

PR301

47K_0402_5%

2

G

PACIN<40>

ACON<40>

ACOFF<33,40>

13

D

SSM3K7002FU_SC70-3

S

P2

1 2 36

12

PC301

PR303

200K_0402_1%

0.1U_0603_25V7K

12

PR309

150K_0402_1%

PQ310

13

D

SSM3K7002FU_SC70-3

2

G

S

13

IREF<33>

CHGVADJ=(Vcell-4)/0.10627

Vcell

4V

B B

4.2V

4.35V

CC=0.25A~3A

IREF=1.016*Icharge

IREF=0.254V~3.048V

VCHLIM need over 95mV

CHGVADJ

1.882V

3.2935V

P3

0V

UMA CP mode (55W) Vaclim=2.39*((2.26K//152K)/(2.26K//152K+21K//152K))=0.25739V Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) where Vaclim=0.25739V, Iinput=2.7692A

UMA CP mode (30W) Vaclim=2.39*((31.6K//152K)/(31.6K//152K+31.6K//152K))=1.195V Iinput=(1/0.05)((0.05*Vaclim)/2.39+0.05) where Vaclim=1.195V, Iinput=1.5A

PQ314 TP0610K-T1-E3_SOT23-3PQ314 TP0610K-T1-E3_SOT23-3

12

PR333

10_0603_5%

13

1 2

PQ302

FDS6675BZ_SO8

1 2 3 6

4

FSTCHG<33>

0.01U_0402_25V7K

ADP_I<33>

PR319

154K_0402_1%

PR322

100K_0402_1%

Connect to EC A/D Pin.

6251_DCIN

8 7

5

FSTCHG

PC313

1 2

12

4

P3

1 2

PC315

PC315 100P_0402_50V8J@

100P_0402_50V8J@

12

PC321

0.01U_0402_25V7K

CHGVADJ<33>

PR302

0.02_1206_1%

1

2

RB751V-40_SOD323-2

PD301

PR306

PC308

1 2

2.26K_0402_1%

15.4K_0402_1%

1 2

6251_VDD

12

1 2

PR316

PR316 100_0402_1%

100_0402_1%

PR321

PR321 21K_0402_1%

21K_0402_1%

1 2

PR324

PR325

31.6K_0402_1%

PR308

1 2

10K_0402_1%

1 2

0.1U_0402_16V7K

PC312 6800P_0402_25V7KPC312 6800P_0402_25V7K

1 2

PR314 6.81K_0402_1%PR314 6.81K_0402_1%

1 2

PC316

0.1U_0402_16V7K

6251_VREF

3

B+

PJ301

6251_DCIN

12

PC310

0.047U_0402_16V7K

PC314

0.1U_0402_16V7K

1 2

LX_CHG

DH_CHG

2.2_0402_5%

BST_CHG

6251_VDDP

DL_CHG

2

112

JUMP_43X118@

PC309

0.1U_0603_25V7K

12

20_0402_5%

1 2

PR311

20_0402_5%

12

PR312

PR312 20_0402_5%

20_0402_5%

1 2

2.2_0402_5%

PR320

1 2

12

PC323

4.7U_0805_6.3V6K

CSIN CSIP

PR310

PR315

0.1U_0603_25V7K

BST_CHGA

12

PD303

RB751V-40_SOD323-2

1 2

PR323

4.7_0402_5%

CELLS

12

2N7002KDW-2N _SOT363-6@

4

3

12

PC307

12

PR326

100K_0402_1%

12

1

2.2U_0603_6.3V6K

2

6251_EN CSON

3

CELLS

4

5

6

7

6251_VREF

8

9

10

11

12

PC302

@ PC302

@

470P_0603_50V8J

PU301

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

24

23

22

21

20

19

18

17

16

15

14

13

VDD

ACSET

EN

CELLS

ICOMP

VCOMP

ICM

VREF

CHLIM

ACLIM

VADJ

GND

ISL6251AHAZ-T_QSOP24

PR330

@PR330

@

0_0402_5%

PC317

6251_VDD

1 2

12

1 2

PC303

PC305

PC304

4.7U_0805_25V6-K

CSOP

6251_VDD 6251_VDD

PR327

PR327 100K_0402_1%

100K_0402_1%

1 2

61

2

PQ313A

2N7002KDW-2N _SOT363-6@

1 2

34

2

PC306

2200P_0402_50V7K

PR328

PR328 100K_0402_1%@

100K_0402_1%@

PQ313B

CHG_B+

PC324

1 2

@

2200P_0402_50V7K

DTC115EUA_SC70-3

3 5

241

3 5

241

5

PR331

PR331 0_0402_5%@

0_0402_5%@

PR305

10K_0402_1%

1 2 13

PQ306

PQ308

PL301

10UH_1164AY-100M=P3_4.7A_20%

SIS412DN-T1-GE3 _PAK1212-8

1 2

12

PR318

4.7_1206_5%

PQ312

4.7_1206_5%

12

PC322

SI7716ADN-T1-GE3 _PAK1212-8

680P_0603_50V7K

12

PQ303

FDS6675BZ_SO8

1 2 3 6

4

PR304

47K_0402_1%

1 2

1

PD302

PD302 RB715F_SOT323-3

RB715F_SOT323-3

2

CHGCHG

1

2

BATT_SEL_EC <33>

8 7

5

VIN

ACOFF

3

2

12

PC311

0.1U_0603_25V7K

PR317

0.02_1206_1%

4

3

1

PR307

200K_0402_1%

1 2

13

D

PACIN

2

G

S

PQ309

SSM3K7002FU_SC70-3

12

PC319

PC318

10U_1206_25V6M

VIN

BATT+

12

PC320

10U_1206_25V6M

PR335

100K_0402_1%

A A

5

PR337

2

100K_0402_1%

PQ315

DTC115EUA_SC70-3

12

13

FSTCHG

2

1

2

PD304

RB715F_SOT323-3

SUSP#

3

4

SUSP# <33,37,38,45>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2008/6/222009/10/10

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CHARGER

1

of

42 48Tuesday, March 09, 2010

of

42 48Tuesday, March 09, 2010

of

42 48Tuesday, March 09, 2010

0.1

5

4

3

2

1

ISL6237_B+

12

PC406

PC405

10U_1206_25V6M

2200P_0402_50V7K

PL402

4.7UH_PCMC063T-4R7MN_5.5A_20%

12

PR405

4.7_1206_5%

5V_SNB

12

680P_0603_50V7K

PC416

12

PJ402

2

112

JUMP_43X118@

PJ403

2

112

JUMP_43X118@

PC407

0.1U_0402_25V6

PR407

61.9K_0402_1%@

PR409

0_0402_5%

12

PC424

@

2200P_0402_50V7K

+5VALWP

1

+

PC415

PC415 150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M

2

1 2

12

@

0_0402_5%

12

PC423

2200P_0402_50V7K

100K_0402_1%

1 2

PR419

ISL6237_B+

PQ401

PQ401 SIS412DN-T1-GE3_PAK1212-8

SIS412DN-T1-GE3_PAK1212-8

3 5

241

3 5

241

PQ403

PQ403 SI7716ADN-T1-GE3_PAK1212-8

SI7716ADN-T1-GE3_PAK1212-8

PR412

PR414

1 2

200K_0402_1%

12

BST3A-1

PC413

0.1U_0603_25V7K

1 2

PC419

0.22U_0603_25V7K

1 2

VL

PR418

1 2

806K_0603_1%

12

PR401

0_0402_5%

1 2

PR403

2.2_0603_5%

2VREF_ISL6237

PR420

47K_0402_1%@

1 2

PC421

0.047U_0402_16V7K

0.1U_0603_25V7K

UG3

BST3A

12

SW3

LG3

FB3

VL

1 2

PC418

0.22U_0603_25V7K

EN_LDO

3/5V_EN1

3/5V_EN2

12

PC422

0.047U_0402_16V7K

@

PC408

PR417

PR417 0_0402_5%

0_0402_5%

1 2

2VREF_ISL6237

VL

1 2

PC409

1 2

3/5V_VIN

3/5V_VCC

3

6

PU401

33

VIN

TP

26

UGATE2

24

BOOT2

25

PHASE2

23

LGATE2

30

OUT2

32

FB2

1

REF

8

NC

20

SECFB

4

EN_LDO

14

EN1

27

EN2

PC420

VCC

TON

NC

2

5

3/5V_NC

12

3/5V_TON

12

PR421

PR421 0_0402_5%

0_0402_5%

1U_0603_10V6K

12

1U_0603_10V6K

PC410

7

19

PVCC

LDO

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

RT8206BGQW_Q FN32_5X5

21

4.7U_0805_6.3V6K

PC411

1U_0603_10V6K

1 2

HG5

BST5A

PR406

2.2_0603_5%

SW5

LG5

FB5

5V_SKIP

ILM1

ILIM2

BST5A-1

12

PC414

0.1U_0603_25V7K

PR410

PR410 0_0402_5%@

0_0402_5%@

1 2

PR411

PR411 0_0402_5%

0_0402_5%

PR413

PR413 0_0402_5%@

0_0402_5%@

PR415

PR415 301K_0402_1%

301K_0402_1%

PR416

PR416 301K_0402_1%

301K_0402_1%

1 2

12

2VREF_ISL6237

12

PQ402

PQ402 SIS412DN-T1-GE3_PAK1212-8

SIS412DN-T1-GE3_PAK1212-8

3 5

241

3 5

241

PQ404

PQ404 SI7716ADN-T1-GE3_PAK1212-8

SI7716ADN-T1-GE3_PAK1212-8

VL

+3VALWP +3VALW

+5VALWP +5VALW

2VREF_ISL6237

B+

PJ401

PJ401 JUMP_43X118@

JUMP_43X118@

2

112

D D

+3VALWP

PC412

150U_B2_6.3VM_R45M

C C

B B

PC412

12

PC402

PC401

330P_0402_50V7K

1

+

2

VS

PC402

0.1U_0402_25V6

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

PR404

0_0402_5%

PR404

0_0402_5%

1 2

PR408

10K_0402_1%

1 2

@

PD402

LLZ5V1B_LL34-2

12

PC403

PL401

4.7_1206_5%

680P_0603_50V7K

21

MAINPWON<40,41>

12

10U_1206_25V6M

PR402

PC417

PD401

1 2

RB751V-40_SOD323-2

EN_LDO-1

PD403

1 2

RB751V-40_SOD323-2

PC404

2200P_0402_50V7K

12

3V_SNB

12

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/01/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

3VALW/5VALW

Size Document Number Rev

Tuesday, March 09, 2010

Date: Sheet

2

Date: Sheet

43 48

1

0.1Custom

of

5

D D

SYSON<33,37,38>

+5VALW

C C

PR501

0_0402_5%

1 2

PR505

100_0603_1%

1 2

PC509

4.7U_0603_6.3V6K

4

12

PC501

0.1U_0402_16V7K

@

12

PC510

47P_0402_50V8J@

1 2

PR508

31.6K_0402_1%

1 2

PR509

30.1K_0402_1%

1.5V_TON

1.5V_EN

1.5V_V5FILT

1.5V_FB

3

578

PR502

240K_0402_1%

1 2

BST_1.5V BST_1.5V-1

1 2

PR503

2.2_0603_5%

14

1

PU501

2

TON

3

VOUT

4

VDD

5

FB

6

PGOOD

15

NC

BOOT

UGATE

EN/DEM

PHASE

VDDP

LGATE

GND7PGND

RT8209BGQW _WQFN14_3P5X3P5

8

UG_1.5V

13

1.5V_TRIP

12

SW_1.5V

11

CS

10

LG_1.5V

9

1 2

PR506

10K_0402_1%

1 2

PC506

0.1U_0603_25V7K

+5VALW

12

PC512

4.7U_0805_6.3V6K

5

4

2

PJ501

1.5V_IN

12

PQ501

3 6

241

SI4686DY-T1-E3_SO8

786

PQ502

123

SI4634DY-T1-E3_SO8

12

PC502

PC503

10U_1206_25V6M

PL501

1UH_PCMB103E-1R0MS_20A_20%

1 2

12

PR504

4.7_1206_5%

1.5V_SNB

12

PC513

680P_0603_50V7K

12

PC504

10U_1206_25V6M

0.1U_0402_25V6

+1.5VP +1.5V

PJ501

2

112

JUMP_43X79@

12

PC511

PC505

@

2200P_0402_50V7K

+1.5VP

220U_B2_2.5VM_R15M

12

PC508

10U_0603_6.3V6M

PJ504

2

112

JUMP_43X118@

1

+

PC507

2

1

B+

PJ506

2

112

JUMP_43X79@

PJ603

+1.8VSP +1.8VS

+1.5V

PC525

2

G

12

PC528

0.1U_0402_16V7K

1

PJ503

1

JUMP_43X79@

2

12

PR519

1K_0402_1%

13

D

PR522

1K_0402_1%

PQ505

S

SSM3K7002FU_SC70-3

0.75V_IN

12

0.75V_REF

12

PC527

0.1U_0402_16V7K

12

PU503

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

+0.75VSP

12

PC529

PC529 10U_0603_6.3V6M

10U_0603_6.3V6M

4

+3VS

6

5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC526

PC526 1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0805_6.3V6K

PR620

100K_0402_1%

LDO_1.8V_EN

SUSP<38>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

PC622

0.1U_0402_16V7K

3

PJ604

PJ604 JUMP_43X39@

JUMP_43X39@

12

PC618

2

G

1

2

12

PR619

1K_0402_1%

13

D

PR621

1.24K_0402_1%

S

PQ604

PQ604 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

Compal Secret Data

Deciphered Date

LDO_1.8V_IN

12

LDO_1.8V_REF

12

PC620

0.1U_0402_16V7K

12

PU602

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

+1.8VSP

12

PC621

PC621 10U_0603_6.3V6M

10U_0603_6.3V6M

2010/01/062009/10/10

2

6

5

NC

7

NC

8

NC

9

TP

+5VS

12

PC619

PC619 1U_0402_6.3V6K

1U_0402_6.3V6K

Title

Size Document Number Rev

Date: Sheet

B B

4.7U_0805_6.3V6K

@

PR520

@

0_0402_5%

S3_0.75V_EN<5>

SUSP<38>

A A

1 2

PR521

PR521 150K_0402_1%

150K_0402_1%

1 2

PD501

1SS355_SOD323-2

5

0.75V_EN

12

2

112

JUMP_43X39@

Compal Electronics, Inc.

1.5V/0.75V/1.8V

+0.75VS+0.75VSP

0.1

of

44 48Tuesday, March 09, 2010

of

44 48Tuesday, March 09, 2010

of

44 48Tuesday, March 09, 2010

1

5

PJ701

2

B+

JUMP_43X118@

D D

C C

B B

SUSP#<33,37,38,42>

VTT_B+

112

12

PC701

VTT_SELECT<7> VTT_SENSE <7>

12

PC703

PR706

0.1U_0402_25V6

12

PC704

2200P_0402_50V7K

@

35.7K_0402_1%

PC708

1 2

12

PC702

10U_1206_25V6M

0_0402_5%

1 2

H_VTTVID1= Low, 1.1V H_VTTVID1= High, 1.05V

2200P_0402_50V7K

PR713

VCCP_POK<5>

12

0.1U_0402_16V7K@

VTT_VCC

12

PC707

2.2U_0603_6.3V6K

PC710

VTT_EN-1

PC713

0_0402_5%

1 2

12

22P_0402_50V8J

4

PR703

PU701

3

VIN

4

VCC

5

EN

VTT_COMP

PC714

VFB=0.6V

+5VS

12

1.1VS_PGOOD

2

8

GND

PGOOD

ISL6268CAZ-T_SSOP16

COMP6FB7FSET

12

VTT_FB

PR710

22.1K_0402_1%

VTT_COMP-1

12

6800P_0402_25V7K

12

SW_VTT

UG_VTT

PR701

1K_0402_5%

1UG16

PHASE

9

VTT_FSET

12

PR711

PR716

1.96K_0402_1%

VTT_BOOT

15

BOOT

VO

10

12

42.2K_0402_1%

1 2

14

PVCC

13

LG

12

PGND

11

ISEN

PC712

0.01U_0402_25V7K

1 2

PR714

1.62K_0402_1%

PR702

2.2_0603_5%

+5VALW

12

PR704

PR704 0_0603_5%

0_0603_5%

1 2

VTT_PVCC

2.2U_0603_6.3V6K

LG_VTT

VTT_ISEN

VTT_BOOT-1

PR705

4.7_0603_5%

1 2

PC706

1 2

PR709

2.21K_0402_1%

VTT_FB-1

3

1 2

PC705

0.1U_0603_25V7K

VTT_VCC

Rds=2.3~3.2mȍ

2

5

PQ701

AON6410

4

123

PL701

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

12

AON6704

PQ702

AON6704

4

AON6704

4

123 5

AON6704

PQ703

VTT_SNB

12

123 5

PR707

4.7_1206_5%

PC711

PC711 680P_0603_50V7K

680P_0603_50V7K

PR712

PR712 10_0402_5%

10_0402_5%

1 2

PR715

PR715 0_0402_5%

0_0402_5%

12

1

+1.1V_VCCPP

1

+

2

PC709

330U_D2E_2VM_R6M

PJ702

2

+1.1V_VCCPP +1.1VS_VTT

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2010/01/06

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

112

JUMP_43X118@

PJ703

2

112

JUMP_43X118@

Compal Electronics, Inc.

+1.1VS_VTT

45 48Tuesday, March 09, 2010

1

0.1

of

5

4

3

2

1

change name

D D

GFXVR_EN

GFXVR_VID_1

PR814

PR803 0_0402_5% PR803 0_0402_5%

0_0402_5%

@

@ 1 2

1 2

GFX_EN

32

EN

1

PWRGD

2

IMON

3

CLKEN#

4

FBRTN

ADP3211AMNR2G_QFN32_5X5

5

FB

6

COMP

7

GPU

8

ILIM

IREF9RPM10RT11RAMP12LLINE13CSREF14CSFB15CSCOMP

GFX_IREF

GFX_RPM

PR821

80.6K_0402_1%

1 2

237K_0402_1%

GFX_RAMP-1

12

PC815

1000P_0402_50V7K

GFXVR_VID_0

PR804 0_0402_5% PR804 0_0402_5%

PR805 0_0402_5% PR805 0_0402_5%

1 2

GFX_VID0

GFX_VID1

GFX_VID2

VID031VID130VID229VID328VID427VID526VID6

PU801

GFX_RT

GFX_RAMP

PR822

12

1 2

340K_0402_1%

12

+3VS

12

PR801

12

GFX_IMON

GFX_FB

GFX_COMP

GFX_VCC

GFX_ILIM

1 2

GFX_CSCOMP

PR820

PR829

1K_0402_1%

10K_0402_1%

PR802

0_0402_5%

GFX_PWRGD

47P_0402_50V8J

GFX_COMP-1

12

PC809

1 2

PR818

20K_0402_1%

PR819

10.7K_0402_1%

GFXVR_PWRGD

+1.1VS_VTT

12

PR812

PR812 300K_0402_1%@

300K_0402_1%@

12

1 2

PC807

PR817

PC801

0.056U_0402_16V7K

GFX_IMON

12

PR813

6.98K_0402_1%

1 2

PC810

470P_0402_50V8J

GFXVR_IMON<8>

12

PC806

1000P_0402_50V7K

C C

1000P_0402_50V7K

220P_0402_50V7K

1 2

1K_0402_1%

Avoid high dV/dt

PR824

PR823

0_0402_5%

B B

PR830

100_0402_1%

1 2

PR824 0_0402_5%

0_0402_5%

1 2

PR831

PR831 100_0402_1%

100_0402_1%

1 2

<8>

+GFX_B+

Connect to input caps

+GFX_COREP

VSS_AXG_SENSE

VCC_AXG_SENSE

<8>

GFXVR_VID_3

GFXVR_VID_2

PR806 0_0402_5% PR806 0_0402_5%

1 2

GFX_VID3

GFX_CSCOMP

PR825

<8>

GFXVR_VID_5

GFXVR_VID_4

PR808 0_0402_5% PR808 0_0402_5%

PR809 0_0402_5% PR809 0_0402_5%

PR807 0_0402_5% PR807 0_0402_5%

1 2

GFX_VID4

GFX_VID5

GFX_CSFB

422K_0402_1%

12

PC816

PC816 1000P_0402_50V7K

1000P_0402_50V7K

<8>

1 2

GFX_VID6

25

16

GFX_CSCOMP

<8>

GFXVR_VID_6

PR810 0_0402_5% PR810 0_0402_5%

VCC

BST

DRVH

SW

PVCC

DRVL

PGND

AGND

12

<8>

PC813

PC813 1000P_0402_50V7K

1000P_0402_50V7K

<8>

+5VS

PR811

PR811 10_0603_1%

10_0603_1%

1 2

12

PC804

PC804 1U_0603_16V6K

1U_0603_16V6K

GFX_VCC

24

GFX_BOOST

1 2

23

GFX_DRVH

22

GFX_SW

21

20

GFX_DRVL

19

18

17

33

12

Shortest the net trace

PR815

2.2_0603_5%

GFX_BOOST-1

PC808

2.2U_0603_10V6K

PH801

1 2

220K_0402_5%_ERTJ0EV224J~D

PR826

71.5K_0402_1%

PC814

PC814 560P_0402_50V7K

560P_0402_50V7K

578

PC805

0.22U_0603_25V7K

1 2

3 6

241

+5VS

12

3 5

241

Place RTH1 close to inductor on the same layer

12

PR827

PR827 165K_0402_1%

165K_0402_1%

12

PR828

34K_0603_1%

PQ801

SI4686DY-T1-E3_SO8

PQ802

TPCA8028_PSO8

12

PC817

0.1U_0402_25V6

12

PR816

4.7_1206_5%

12

PC812

PC812 680P_0603_50V7K

680P_0603_50V7K

12

PC818

PC819

@ PC819

@

2200P_0402_50V7K

0.36UH_PCMC104T-R36MN1R 17_30A_20%

PL802

1

2

+GFX_B+

12

PC802

10U_1206_25V6M

4

3

+GFX_COREP

PL801

FBMA-L11-201209-121LMA50T_0805

10U_1206_25V6M

1 2

12

PC803

B+

+GFX_COREP

1

+

PC811

2

330U_D2_2.5VY_R9M

PJ801

2

112

JUMP_43X118@

PJ802

2

112

JUMP_43X118@

+GFX_CORE

LL=7m ohm OCP=26A VID:~1.25V Io(max)=22A

(15A,600mils ,Via NO.= 30)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/10 2010/01/06

Compal Secret Dat a

Deciphered Dat e

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

GFX_CORE

1

of

46 48Tuesday, March 09, 2010

of

46 48Tuesday, March 09, 2010

of

46 48Tuesday, March 09, 2010

0.1

8

H H

G G

+3VS

12

PR901

1.91K_0402_1%

PR914

0_0402_5%

PR920

4.99K_0402_1%

12

1 2

0_0402_5%

+1.1VS_VTT

12

1 2

CLK_EN#<12>

F F

IMVP_IMON<7>

PC910

1000P_0402_50V7K

E E

PR926

PR926 0_0402_5%

0_0402_5%

D D

Avoid high dV/dt

C C

B B

3212_CLK_EN#

12

VGATE<12,15>

PR916

@ PR916

@

0_0402_5%

12

PC901

0.082U_0402_16V7K

PC912 150P_0402_50V8JPC912 150P_0402_50V8J

1 2

PR922

1.65K_0402_1%

1 2

PR927

0_0402_5%

H_PROCHOT#<5,33>

+5VS

12

PR937

7.32K_0402_1%

12

PR940

@PR940

@

0_0402_5%

12

PH901

@PH901

@

100K +-1% NCP15WF104F03RC 0402

PR915

0_0402_5%

PC914

150P_0402_50V8J

1 2

PR930

0_0402_5%

@

PQ909

7

PROC_DPRSLPVR<7>

VR_ON<33>

+3VS

12

PR912

3K_0402_5%

12

IMVP_IMON

3212_CLK_EN#

3212_FBRTN

12P_0402_50V8J

3212_FB

PC913

12

PR923

39.2K_0402_1%

1 2

PR924 5.11K_0402_1% PR924 5.11K_0402_1%

+5VS

3212_VRTT

+3VS

TTSENSE

12

PR928

@PR928

@

499_0402_1%

12

13

D

3212_VRTT

2

G

S

2N7002W-T/R7_SOT323-3

Connect to input caps

TTSENSE

12

@

PC921

0.01U_0402_50V7K

Layout note: Close Phase 1 MOS

H_VID6<7>

H_VID5<7>

H_VID4<7>

H_VID3<7>

H_VID2<7>

H_VID1<7>

H_VID0<7>

12

PSI#<7>

PR913

0_0402_5%

1

2

3

4

5

6

7

8

9

10

11

12

49

80.6K_0402_1%

+CPU_B+

6

12

PR903 0_0402_5%PR903 0_0402_5%

PR904 0_0402_5%PR904 0_0402_5%

PU901

48

47

VID0

VID1

EN

PWRGD

IMON

CLKEN

FBRTN

FB

$'3015*B4)1B;

COMP

TRDET

VARFR

VRTT

TTSNS

GND

AGND

PR933

69.8K_0402_1%

1K_0402_1%

1000P_0402_50V7K

CSREF

IREF

13

12

PR939

PR934

RPM

14

12

PR905 0_0402_5%PR905 0_0402_5%

46

VID2

RT

15

12

PR935

PC922

1U_0603_16V6K

12

PR907 0_0402_5%PR907 0_0402_5%

PR906 0_0402_5%PR906 0_0402_5%

44

45

VID3

RAMP

17

16

12

162K_0402_1%

3212_CSCOMP

PR936

PR936 649K_0402_1%

649K_0402_1%

12

PC925

PR908 0_0402_5%PR908 0_0402_5%

VID4

LLINE

12

43

VID5

CSREF

18

12

PR909 0_0402_5%PR909 0_0402_5%

42

VID6

CSSUM

19

12

PR911 499_0402_1%PR911 499_0402_1%

PR910 0_0402_5%PR910 0_0402_5%

41

40

PSI

DPRSLP

CSCOMP

ILIM

20

21

12

3212_CSCOMP

PR938

1.91K_0402_1%

12

PC923

390P_0402_50V7K

PR943 127K_0603_1%PR943 127K_0603_1%

PR944 127K_0603_1%PR944 127K_0603_1%

39

38

PH0

PH1

PWM3

OD3

23

22

1 2

PC924

165K_0402_1%

1200P_0402_50V7K

12

+5VS

12

PR902

PR902 10_0603_5%

10_0603_5%

37

VCC

DRVH1

SWFB1

PVCC

DRVL1

PGND

DRVL2

SWFB2

DRVH2

SWFB3

24

PR942

1 2

5

12

BST1

SW1

SW2

BST2

PR941

3212_CS_PH1

3212_CS_PH2

PC902

1U_0603_16V6K

36

35

34

33

32

31

30

29

28

27

26

25

12

71.5K_0402_1%

PR917

2.2_0603_5%

12

3212_DRVH1

PR921

1 2

100_0402_1%

3212_DRVL1

3212_DRVL2

PR925

1 2

100_0402_1%

3212_DRVH2

Layout note: Boost Parts close

3212_SW2 3212_DRVH2

PR929

12

2.2_0603_5%

PH902

220K_0402_5%_ERTJ0EV224J~D

1 2

Layout note: Boost Parts close

PC908

0.1U_0603_25V7K

3212_SW1

3212_CS_PH1

12

PC911

4.7U_0603_6.3V6M

3212_CS_PH2

PC919

0.1U_0603_25V7K

4

12

+5VS

12

3212_SW1

3212_DRVL1

4

Close IC

3212_SW2

3212_DRVL2

4

Layout note: Close to PHASE 1 inductor on the same layer

3

PC903

5

PQ902

4

PQ902

TPCA8030-H_SOP-ADV8-5

123

PQ904

123 5

TPCA8028-H_SOP-ADVANCE8-5

5

PQ906

TPCA8030-H_SOP-ADV8-5

123

PQ908

123 5

@

TPCA8028-H_SOP-ADVANCE8-5

3212_DRVH1

PQ903

3212_DRVL1

123 5

@

TPCA8028-H_SOP-ADVANCE8-5

3212_DRVL2

PQ907

123 5

TPCA8028-H_SOP-ADVANCE8-5

12

PC904

0.1U_0603_25V7K

12

4.7_1206_5%

12

470P_0603_50V8J

+CPU_B+

12

PC916

0.1U_0603_25V7K

12

4.7_1206_5%

12

470P_0603_50V8J

2

12

PC926

2200P_0402_50V7K

@

PR918

PC909

12

PC917

2200P_0402_50V7K

PR931

PC920

+CPU_B+

12

PC906

PC905

10U_1206_25VAK

DCR=1.1mȍ ±7%

PL902

0.36UH_PCMC104T-R36MN1R 17_30A_20%

12

PC918

0.36UH_PCMC104T-R36MN1R 17_30A_20%

PL902

1

2

3212_CS_PH1

12

PC915

10U_1206_25VAK

DCR=1.1mȍ ±7%

PL903

1

2

3212_CS_PH2

4

3

1

PL901

FBMA-L18-453215-900LMA90T_1812

1

+

PC907

2

68U_25V_M_R0.36

4

3

12

PR919

PR919 10_0402_5%

10_0402_5%

CSREF

12

PR932

10_0402_5%

CSREF

12

B+

+CPU_CORE

VCCSENSE

VSSSENSE

VCCSENSE <7>

VSSSENSE <7>

Shortest the net trace

0603 package at least

OCP : 60A

A A

Layout note: Close CPU pin

8

7

6

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2009/10/10 2010/01/06

Compal Secret Dat a

Deciphered Dat e

3

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

CPU_CORE

of

47 48Tuesday, March 09, 2010

of

47 48Tuesday, March 09, 2010

of

47 48Tuesday, March 09, 2010

1

0.1

5

4

3

2

1

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IRU3:5

5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH,WHP



D D



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

$GG3535IRU*);B&25(VHQFH $GG3535IRU*);B&25(VHQFH

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C C

$GG3'3)RU(6' (97

5HPRYH9V-8033)RU+:UHTXHVWUHPRYH9V-803 (97

&KDQJH3&IURPX)WRX)

3  (97

3 +:UHTXHVW  (97

3

7KHUPDOWHDPUHTXHVWWRFKDQJH273WHPSFKDQJHIURPGHJUHHWRGHJUHH





 397



B B













A A



Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/10 2009/01/06

3

Compal Secret Data

Deciphered Date

2

20081022

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

NAU00 M/B LA-6101P Schematics

1

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48 48Tuesday, March 09, 2010

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COMPAL LA-6101P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual