Cirrus Logic EP7212 Datasheet

EP7212

FEATURES

n ARM720T processor

— ARM7TDMI CPU — 8 K-bytes of four-way set-associative cache — MMU with 64-entry TLB (transition look-aside buffer) —Write Buffer —Windows — Thumb code support enabled

Dynamically programmable clock speeds of

18, 36, 49, and 7 4 MHz at 2 .5 V

n Performance matching 100-MHz Intel

Pentium-based PC

n Ultra low power

— Designed for applications that require long battery life

while using standard AA/AAA batteries or rechargeable cells

— Typical Power Numbers

● 90 mW at 74 MHz in the Operating State

● 30 mW at 18MHz in the Operating St a te

● 10 mW in the Idle State (clock to the CPU stopped,

everything else running)

● <1 mW in the S t andb y State (realtime clock ‘on’,

everything else stopped)



CE enabled



EP7212

High-Performance, Low-Power

System-on-Chip with LCD

Controller and Digital Audio

Interface (DAI)

OVERVIEW

The EP7212 is design ed f or ul t ra- lo w-p ower appl ica tions such as organizers / PDAs, two-way pagers, smart cellular ph ones or any v ertical P DA device that features t he ad d ed capability o f d ig ital audio decom pression. The co re-logic functionality of the device is built around a n ARM720T processor with 8 K-bytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for suppor t of sophisti cated operat ing systems like Microsoft Wi ndo ws CE.

(cont.) (cont.)

Functional Block Diagram

13-MHZ INPUT

3.6864 MHZ

32.768 KHZ

NPOR, RUN,

RESET, WAKEUP

BATOK, EXTPWR PWRFL, BATCHG

EINT[1-3], FIQ,

MEDCHG

FLASHING LED DRIVE

PORTS A, B, D (8-BIT)

PORT E (3-BIT)

KEYBD DRIVERS (0-7)

BUZZER DRIVE

DC TO DC

ADCCLK, ADCIN,

ADCOUT, SMPCLK,

SSICLK, SSITXFR,

SSITXDA, SSIRXDA,

ADCCS

SSIRSFR

32.768-KHZ

OSCILLATOR

STATE CONTROL

POWER

MANAGEMENT

INTERRUPT

CONTROLLER

RTC

GPIO

PWM

SSI1 (ADC)

DAI

PLL

SSI2

CODEC

ARM720T

ARM7TDMI

CORE

CPU

8-KBYTE

CACHE

MMU

WRITE

BUFFER

TIMER

COUNTERS(2)

ON-CHIP

BOOT ROM

EPB BRIDGE

EPB BUS

INTERNAL DATA BUS

MEMORY CONTROLLER

CL-PS6700 INTF

EXPANSION CNTRL

DRAM CNTRL

INTERNAL ADDRESS BUS

LCD DMA

ICE-JTAG

LCD

CONTROLLER

ON-CHIP SRAM

38,400 BYTES

UART1

UART2

IrDA

D[0-31]

PB[0-1], NCS[4-5]

EXPCLK, WORD, NCS[0-3], EXPRDY, WRITE

MOE, MWE, RAS[0-1], CAS[0-3]

A[0-27],

DRA[0-12]

TEST AND DEVELOPMENT

LCD DRIVE

LED AND PHOTODIODE

ASYNC INTERFACE 1

ASYNC INTERFACE 2

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FEB 00

Low-Power System-on-Chip with LCD Controller and Digital Audio Interface

FEATURES (cont.)

n Advanced audio decoder / decompression

capability

— Allows for support of multiple audio decompression

algorithms

— Supports MPEG 1, 2, & 2.5 layer 3 audio decoding,

including ISO compliant MPEG 1 & 2 layer 3 support for

all standard sample rates and bit rates — Supports bit streams with adaptive bit rates — DAI (Digital Audio Interface) providing glueless interface

to low-power DACs, ADCs, and Codecs

LCD controller

— Interfaces directly to a single-scan panel monochrome

LCD — Panel width size is programmable from 32 to 1024 pixels

in 16-pixel increments — Video frame buffer size programmable up to

128 kbytes — Bits per pixel of 1, 2, or 4 bits

DRAM controller

— Supports both 16- and 32-bit-wide DRAMs — EDO support (Fast Page Mode support for 13MHz and

18 MHz operation only)

Memory controller

— Decodes up to 6 separate memory segment s of up to

256 Mbytes each — Each segment can be configured as 8, 16, or 32 bits

wide and supports page-mode access — Programmable access time for conventional ROM /

SRAM / FLASH memory — Supports Removable FLASH card interface — Enables connection to removable FLASH card for

addition of expansion FLASH memory modules

38,400 bytes ( 0 x9 600) of on -ch i p S RAM for f as t program execution and / or as a frame buffer

EP7212

n Synchronous serial interface

— ADC (SSI) Interface: Master mode only; SPI and

Microwire1

On-chip ROM; for manufacturing support

n 27-bits of general-purpose I/O

— Three 8-bit and one 3-bit GPIO port — Supports scanning keyboard matrix

Two UARTs (16550 type)

— Supports bit rates up to 115 .2 kbps — Contains two 16-byte FIFOs for TX and RX — UART1 supports modem control signals

SIR (up to 115.2 kbps) infrared encoder / decoder

— IrDA (Infrared Data Association) SIR protocol encoder /

decoder

n DC-to-DC converter interface (PWM)

— Provides two 96-kHz clock outputs with programmable

duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a DC to DC converter

Two timer counters

n 208-pin LQFP or new 256-ball PBGA packages n Evaluation kit available with BOM, schematics,

sample code, and design database

n Support for up to two ultra-low-power CL-PS6700

PC Card controllers

n Dedicated LED flasher pin from RTC n Full JTAG boundary scan and Embedded ICE

support

n Commercial operating temperature range



-compatible (128 kbps operation)



OVERVIEW (cont.)

The EP7212 also includes a 32-bit Y2K-compliant realtime clock and comp ar at or.

Power Management

The EP7212 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V–3.3 V. The device has three basic power states:

Operating — This state is the full performance

state. All the clocks and peripheral logic are enabled.

Idle — This state is the same as the Operating

St ate, exce pt th e CPU cl ock is halt ed wh ile w aiting for an event such as a key press.

2 DS474PP1

St andby — This state is equivalent to the computer

being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor.

Memory Interfaces

There are two main ex te r nal memo r y in te rfa ces . The first one i s the R OM / SRA M / FLASH- style int er-

face that has programm able wait-state timings and includes burst-mode capability, with eight chip selects decoding six 256-Mbyte sections of addressable space. For maximu m flexibility, each bank can be specified to be 8, 16, or 32 bits wide. This allows the use of 8-bit-w ide boot ROM options t o minimize ov er-

EP7212

Low-Power System-on-Chip with LCD Controller and Digital Audio Interface

OVERVIEW (cont.)

all system cost. The on-chip boot ROM can be used in product manuf acturing to se rially downlo ad system code into system FLASH memory. To further minimize system memory requirements and cost, the



ARM Thumb

instruction se t is suppo rted, provi ding for the use of high-speed 32-bit operations in 16-bit op-codes and yiel ding industr y-leading co de density.

The second is the programmable 16- or 32-bit-wide DRAM interface that allows direct conn ection of up to two banks of DRAM, eac h ba nk co ntaining up to 256 Mbytes. To assure the lowest possible power consumption, the EP721 2 sup ports self-refresh DRAMs, which are placed in a low-power state by the device when it enters the low-power Standby State. EDO and Fast Page DRAM are s upp or ted.

A DMA address generator is also provided that fetches video disp lay dat a for the LCD controller f rom main DRAM memory. The display frame buffer start address is programmable. In addition, the built-in LCD controller can utilize external or internal SRAM for memory, thus eliminating th e nee d for DR AMs.

Digital Audio Capability

The EP7212 uses its powerful 3 2-bit RISC p rocessing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor and the av ailabi lit y of e ff icien t C -compil ers and other softwar e development t ools, ensures th at a wide range of audio decompression algorithms can easily be ported to and run on the EP7212.

Serial Interfaces

The EP7212 include s two 16550-type UARTs for RS232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. The UARTs support bit rates up to 115.2 kbps. An IrDA SIR protocol encoder / decoder can be optionally switched in to the RX / TX si gnals to / from one of the UARTs to e nable these signals t o drive an infrared communication interface directly.

Digital Audio Interface (DAI)

The EP7212 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal power audio DACs and the Cry stal power ADC. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limi ter fu ncti ons .

Packaging

The EP7212 is availabl e in a 208-pi n LQFP p ac kag e and a 256-ball PBGA p a ckage.

System Design

As shown in system block diagram, simply adding desired memory and periphera ls to the highly integrated EP7212 completes a low-power system solution. All necessary interface logic is integrated on-chip.



CS43L41 / 42 / 43 low-



CS53L32 low-

3DS474PP1

EP7212

Low-Power System-on-Chip with LCD Controller and Digital Audio Interface

CRYSTAL CRYSTAL

PC CARD

SOCKET

EXTERNAL MEMORYMAPPED EXPANSION

ADDITIONAL I/O

CL-PS6700

PC CARD

CONTROLLER

× 16

DRAM

× 16

DRAM

× 16

FLASH

× 16

FLASH

BUFFERS

LATCHES

DRAM

× 16

FLASH

× 16

FLASH

AND

× 16

MOSCIN RTCIN CS[4]

PB0 EXPCLK

D[31:0] A[27:0]

MOE WRITE

RAS[1] RAS[0]

CAS[0] CAS[1]

CAS[2] CAS[3]

NCS[0] NCS[1]

CS[n] WORD

CS[2] CS[3]

DD[3:0]

COL[7:0]

PA[7:0]

PB[7:0]

PD[7:0]

PE[2:0]

PWRFL

BATOK EXTPWR BATCHG

EP7212

WAKEUP

DRIVE[1:0]

FB[1:0]

SSICLK

SSITXFR

SSITXDA SSIRXDA

LEDDRV

PHDIN

RxD1/2

TxD1/2

ADCCLK

ADCCS ADCOUT

ADCIN

SMPCLK

CL1 CL2

POR

RUN

DSR

CTS

DCD

A EP7212–Based System

LCD MODULE

KEYBOARD

POWER

SUPPLY UNIT

AND

COMPARATORS

DC-TO-DC

CONVERTERS

CODEC/SSI2/

DAI

IR LED AND

PHOTODIODE

2× RS-232

TRANSCEIVERS

ADC

DIGITIZER

INPUT

BATTERY

4 DS474PP1

EP7212

1. CONVENTIONS ...................................................................................................................... 11

1.1 Acronyms and Abbreviations ............................................................................................ 11

1.2 Units of Measurement ......................................................................................................12

1.3 General Conventions ........................................................................................................12

1.4 Pin Description Conventions ............................................................................................. 12

2. PIN INFORMATION ..... ....... ...... ....... ...... ....... ...... ....... ...... ...... ................................................. 13

2.1 208-Pin LQFP Pin Diagram .............................................................................................. 13

2.2 Pin Descriptions ................................................................................................................ 14

2.2.1 External Signal Functions ................................................................................... 14

2.2.2 SSI/Codec/DAI Pin Multiplexing ............................................................................. 18

2.2.3 Output Bi-Directional Pins .................................................................................... 18

3. FUNCTIONAL DESCRIPTION ............................................................................................... 19

3.1 CPU Core .......................................................................................................................... 20

3.2 State Control ..................................................................................................................... 21

3.2.1 Standby State .......................................................................................................... 21

3.2.1.1 UART in Standby State ............................................................................... 22

3.2.2 Idle State ................................................................................................................. 23

3.2.3 Keyboard Interrupt ................................................................................................... 23

3.3 Power-Up Sequence ......................................................................................................... 23

3.4 Resets ............................................................................................................................... 24

3.5 Clocks ............................................................................................................................... 25

3.5.1 On-Chip PLL ............................................................................................................ 25

3.5.1.1 Characteristics of the PLL Interface ............................................................ 25

3.5.2 External Clock Input (13 MHz) ................................................................................ 26

3.5.3 Dynamic Clock Switching When in the PLL Clocking Mode .................................... 26

3.6 Interrupt Controller ............................................................................................................ 27

3.6.1 Interrupt Latencies in Different States ..................................................................... 27

3.6.1.1 Operating State ........................................................................................... 27

3.6.1.2 Idle State ..................................................................................................... 29

3.6.1.3 Standby State .............................................................................................. 29

3.7 EP7212 Boot ROM .......................................................................................................... 29

3.8 Memory and I/O Expansion Interface ............................................................................... 30

3.9 DRAM Controller with EDO Support ................................................................................. 31

3.10 CL-PS6700 PC Card Controller Interface ....................................................................... 33

3.11 Endianness ..................................................................................................................... 36

3.12 Internal UARTs (Two) and SIR Encoder ......................................................................... 36

3.13 Serial Interfaces .............................................................................................................. 38

EP7212

Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product in formati on descri bes pro ducts whic h are in pr oductio n, but for whi ch fu ll chara cteri zatio n data i s not yet avail able. Advance product information describes products which are in devel opme nt and subject to development changes. Cirru s Logi c, I nc. has ma de best efforts to ensure that the infor mati on contained in this document is accurate and rel i abl e. However, the information is sub j ect t o chan ge wi t hout notice and is provided “AS IS” with out warranty of any kind (express or implied). No resp on s ibility is assumed by Cirrus Logic, Inc. fo r th e u s e of this information, nor for infringem ent s of patents or other rights of third parties. This doc ument is the property of Cirrus Lo gic, I nc. and i mplies no li cense under paten ts, copyr ights, tradem arks, or t rade secrets. No part of t his pu blic ation m ay be copie d reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written con sent of Cirrus Logic, Inc. Items from any Cirrus Logic websit e or disk may be printed for use by the user . However, no part of the printout or electronic files may be copied, reproduced, stored in a ret rieval system, or transmitted, i n any form or by any means (electronic, mech anical, photographi c, or otherwi se) without the prio written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consen of Cirrus Logic, Inc. T he names of produ cts of Cirrus L ogic, In c. or other ve ndor s and supp liers ap pear ing in this do cument may be t rademarks or service marks o their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com

DS474PP1 5

DS474PP1

EP7212

3.13.1 Codec Sound Interface ..........................................................................................39

3.13.2 Digital Audio Interface ............................................................................................ 40

3.13.2.1 DAI Operation ............................................................................................41

3.13.2.2 DAI Frame Format ..................................................................................... 41

3.13.2.3 DAI Signals ................................................................................................42

3.13.3 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface) ........... 42

3.13.4 Master / Slave SSI2 (Synchronous Serial Interface 2) ..........................................43

3.13.4.1 Read Back of Residual Data .....................................................................44

3.13.4.2 Support for Asymmetric Traffic .................................................................. 45

3.13.4.3 Continuous Data Transfer .........................................................................45

3.13.4.4 Discontinuous Clock .................................................................................. 45

3.13.4.5 Error Conditions ......................................................................................... 46

3.13.4.6 Clock Polarity ............................................................................................. 46

3.14 LCD Controller with Support for On-Chip Frame Buffer .................................................. 46

3.15 Timer Counters ...............................................................................................................47

3.15.1 Free Running Mode ...............................................................................................48

3.15.2 Prescale Mode ............................. ...... ....... ...... ...... ....................................... ....... ... 48

3.16 Real Time Clock .............................................................................................................. 49

3.16.1 Characteristics of the Real Time Clock Interface ...................................................49

3.17 Dedicated LED Flasher ................................................................................................... 49

3.18 Two PWM Interfaces .......................................................................................................49

3.19 Boundary Scan ................................................................................................................50

3.20 In-Circuit Emulation ......................................................................................................... 50

3.20.1 Introduction ..................................................... ...... ....... ...... ....... ...... .......................50

3.20.2 Functionality .................................................... ...... ....... ...... ....... ...... ....... ...... ....... ...51

3.21 Maximum EP7212-Based System ..................................................................................51

4. MEMORY MAP ...................................... ....... .......................................................................... 53

5. REGISTER DESCRIPTIONS .................................................................................................. 54

5.1 Internal Registers ..............................................................................................................54

5.1.1 PADR Port A Data Register .....................................................................................57

5.1.2 PBDR Port B Data Register .....................................................................................57

5.1.3 PDDR Port D Data Register ....................................................................................57

5.1.4 PADDR Port A Data Direction Register ...................................................................58

5.1.5 PBDDR Port B Data Direction Register ...................................................................58

5.1.6 PDDDR Port D Data Direction Register ...................................................................58

5.1.7 PEDR Port E Data Register .....................................................................................58

5.1.8 PEDDR Port E Data Direction Register ...................................................................58

5.2 SYSTEM Control Registers ...............................................................................................58

5.2.1 SYSCON1 The System Control Register 1 ............................................................. 58

5.2.2 SYSCON2 System Control Register 2 .....................................................................61

5.2.3 SYSCON3 System Control Register 3 .....................................................................63

5.2.4 SYSFLG1 — The System Status Flags Register .................................................... 64

5.2.5 SYSFLG2 System Status Register 2 .......................................................................66

5.3 Interrupt Registers .............................................................................................................67

5.3.1 INTSR1 Interrupt Status Register 1 .........................................................................67

5.3.2 INTMR1 Interrupt Mask Register 1 ..........................................................................68

5.3.3 INTSR2 Interrupt Status Register 2 .........................................................................69

5.3.4 INTMR2 Interrupt Mask Register 2 ..........................................................................69

5.3.5 INTSR3 Interrupt Status Register 3 .........................................................................70

5.3.6 INTMR3 Interrupt Mask Register 3 ..........................................................................70

5.4 Memory Configuration Registers .......................................................................................71

5.4.1 MEMCFG1 Memory Configuration Register 1 .........................................................71

5.4.2 MEMCFG2 Memory Configuration Register 2 .........................................................71

6 DS474PP1

EP7212

5.5 Timer / Counter Registers ................................................................................................. 74

5.5.1 TC1D Timer Counter 1 Data Register ..................................................................... 74

5.5.2 TC2D Timer Counter 2 Data Register ..................................................................... 74

5.5.3 RTCDR Real Time Clock Data Register ................................................................. 74

5.5.4 RTCMR Real Time Clock Match Register ............................................................... 74

5.6 LEDFLSH Register ...........................................................................................................75

5.7 PMPCON Pump Control Register ..................................................................................... 76

5.8 CODR — The CODEC Interface Data Register ................................................................ 77

5.9 UART Registers ................................................................................................................ 77

5.9.1 UARTDR1–2, UART1–2 Data Registers ................................................................. 77

5.9.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers ................................. 78

5.10 LCD Registers ................................................................................................................. 79

5.10.1 LCDCON — The LCD Control Register ................................................................ 79

5.10.2 PALLSW Least Signi fic an t Word — LCD Palette Register ................................... 80

5.10.3 PALMSW Most Significant Word — LCD Palette Register ................................... 81

5.10.4 FBADDR LCD Frame Buffer Start Address ........................................................... 81

5.11 SSI Register .................................................................................................................... 82

5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register .................................. 82

5.12 STFCLR Clear all ‘Start Up Reason’ flags location ........ ....... ....................................... ... 83

5.13 End Of Interrupt Locations .............................................................................................. 83

5.13.1 BLEOI Battery Low End of Interrupt ...................................................................... 83

5.13.2 MCEOI Media Changed End of Interrupt .............................................................. 83

5.13.3 TEOI Tick End of Interrupt Location ...................................................................... 83

5.13.4 TC1EOI TC1 End of Interrupt Location ................................................................. 83

5.13.5 TC2EOI TC2 End of Interrupt Location ................................................................. 84

5.13.6 RTCEOI RTC Match End of Interrupt ....... ...... ...... ....................................... ....... ... 84

5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt .................................. 84

5.13.8 COEOI Codec End of Interrupt Location ............................................................... 84

5.13.9 KBDEOI Keyboard End of Interrupt Location ........................................................ 84

5.13.10 SRXEOF End of Interrupt Location ..................................................................... 84

5.14 State Control Registers ...................................................................................................84

5.14.1 STDBY Enter the Standby State Location ............................................................. 84

5.14.2 HALT Enter the Idle State Location ....................................................................... 84

5.15 SS2 Registers ................................................................................................................. 85

5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ......................................... 85

5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte ............................... 85

5.16 DAI Register Definitions ..................................................................................................85

5.16.1 DAIR DAI Control Register ... ....... ...... ....... ...... ....................................... ...... ....... ... 86

5.16.1.1 DAI Enable (DAIEN) .................................................................................. 87

5.16.1.2 DAI Interrupt Generation ........................................................................... 87

5.16.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM) ................................. 87

5.16.1.4 Left Channel Receive FIFO Interrupt Mask (LARM) ................................. 87

5.16.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM) .............................. 87

5.16.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM) .............................. 88

5.16.1.7 Loopback Mode (LBM) .............................................................................. 88

5.16.2 DAI Data Registers .. ....... ...... ....... ...... ....... ...... ....................................... ...... ....... ... 89

5.16.2.1 DAIDR0 DAI Data Register 0 .......................... ...... ....... ............................. 89

5.16.2.2 DAIDR1 DAI Data Register 1 .......................... ...... ....... ............................. 90

5.16.2.3 DAIDR2 DAI Data Register 2 .......................... ...... ....... ............................. 91

5.16.3 DAISR DAI Status Register ................................................................................... 92

5.16.3.1 Right Channel Transmit FIFO Service Request Flag (RCTS) ................... 94

5.16.3.2 Right Channel Receive FIFO Service Request Flag (RCRS) ................... 94

5.16.3.3 Left Channel Transmit FIFO Service Request Flag (LCTS) ...................... 94

DS474PP1 7

EP7212

5.16.3.4 Left Channel Receive FIFO Service Request Flag (LCRS) ....................... 94

5.16.3.5 Right Channel Transmit FIFO Underrun Status (RCTU) ........................... 94

5.16.3.6 Right Channel Receive FIFO Overrun Status (RCRO) .............................94

5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU) ..............................95

5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO) ................................95

5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF) .................................95

5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE) ........................... 95

5.16.3.11 Left Channel Transmit FIFO Not Full Flag (LCNF) ..................................95

5.16.3.12 Left Channel Receive FIFO Not Empty Flag (LCNE) ..............................95

5.16.3.13 FIFO Operation Completed Flag (FIFO) ..................................................95

6. ELECTRICAL SPECIFICATIONS .......................................................................................... 96

6.1 Absolute Maximum Ratings ..............................................................................................96

6.2 Recommended Operating Conditions ..............................................................................96

6.3 DC Characteristics ............................................................................................................ 96

6.4 AC Characteristics ............................................................................................................98

6.5 I/O Buffer Characteristics ................................................................................................ 110

6.6 JTAG Boundary Scan Signal Ordering ........................................................................... 111

7. TEST MODES ........ ...... ....................................... ....... ...... ...... ....... ...... ....... ...... ....... ...... ........114

7.1 Oscillator and PLL Bypass Mode .................................................................................... 114

7.2 Oscillator and PLL Test Mode ......................................................................................... 114

7.3 Debug / ICE Test Mode .................................................................................................. 115

7.4 Hi-Z (System) Test Mode ...............................................................................................115

7.5 Software Selectable Test Functionality ..........................................................................115

8. PIN INFORMATION ..... ....... ...... ....... ...... ....... ...... ....... ...... ............................................. ........116

8.1 208-Pin LQFP Pin Diagram .............................................................................................116

8.2 208-Pin LQFP Numeric Pin Listing ................................................................................. 117

8.3 256-Pin PBGA Pin Diagram ............................................................................................120

8.4 256-Ball PBGA Ball Listing ..............................................................................................121

9. PACKAGE SPECIFICATIONS .............................................................................................125

9.1 208-Pin LQFP Package Outline Drawing .......................................................................125

9.2 EP7212 256-Ball PBGA (17

10. ORDERING INFORMATION ............................................................................................... 127

11. APPENDIX A: BOOT CODE ..............................................................................................128

12. INDEX ................................................................................................................................. 133

× 17 × 1.53-mm Body) Dimensions ...................................126

8 DS474PP1

LIST OF FIGURES

Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ............................................ 13

Figure 2. EP7212 Block Diagram..................................................................................................20

Figure 3. State Diagram................................................................................................................ 21

Figure 4. CLKEN Timing Entering the Standby State ................................................................... 26

Figure 5. CLKEN Timing Entering the Standby State ................................................................... 26

Figure 6. Codec Interrupt Timing .................................................................................................. 40

Figure 7. DAI Interface........................................................... ...... ....... .......................................... 41

Figure 8. EP7212 Rev C - Digital Audio Interface Timing – MSB / Left Justified format............... 42

Figure 9. SSI2 Port Directions in Slave and Master Mode............................................................ 44

Figure 10. Residual Byte Reading ................................................................................................45

Figure 11. Video Buffer Mapping .................................................................................................. 48

Figure 12. A Maximum EP7212 Based System............................................................................ 52

Figure 13. Consecutive Memory Read Cycles with Minimum Wait States ................................. 100

Figure 14. Sequential Page Mode Read Cycles with Minimum Wait States............................... 101

Figure 15. Consecutive Memory Write Cycles with Minimum Wait States.................................. 102

Figure 16. DRAM Read Cycles at 13 MHz and 18.432 MHz...................................................... 103

Figure 17. DRAM Read Cycles at 36 MHz.................................................................................. 104

Figure 18. DRAM Write Cycles at 13 MHz and 18 MHz ............................................................. 105

Figure 19. DRAM Write Cycles at 36 MHz.................................................................................. 106

Figure 20. Video Quad Word Read from DRAM at 13 MHz and 18 MHz ................................... 107

Figure 21. Quad Word Read from DRAM at 36 MHz.................................................................. 107

Figure 22. DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz............................... 108

Figure 23. DRAM CAS Before RAS Refresh Cycle at 36 MHz................................................... 109

Figure 24. LCD Controller Timings.............................................................................................. 109

Figure 25. SSI Interface for AD7811/2........................................................................................ 110

Figure 26. SSI2 Interface Timings...............................................................................................110

Figure 27. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ........................................ 116

Figure 28. 256-Ball Plastic Ball Grid Array Diagram................................................................... 120

EP7212

LIST OF TABLES

Table 1. Acronyms and Abbreviations .......................................................................................... 11

Table 2. Unit of Measurement....................................................................................................... 12

Table 3. Pin Description Conventions........................................................................................... 12

Table 4. External Signal Functions ............................................................................................... 14

Table 5. SSI/Codec/DAI Pin Multiplexing...................................................................................... 18

Table 6. Output Bi-Directional Pins............................................................................................... 18

Table 7. Peripheral Status in Different Power Management States.............................................. 22

Table 8. Exception Priority Handling............................................................................................. 27

Table 9. Interrupt Allocation in the First Interrupt Register............................................................ 28

Table 10. Interrupt Allocation in the Second Interrupt Register .................................................... 28

Table 11. Interrupt Allocation in the Third Interrupt Register ........................................................ 28

Table 12. External Interrupt Source Latencies.............................................................................. 30

Table 13. Chip Select Address Ranges After Boot From On-Chip Boot ROM.............................. 30

Table 14. Boot Options ................................................................................................................. 31

Table 15. Physical to DRAM Address Mapping............................................................................ 32

Table 16. DRAM Address Mapping When Connected to an External 32-Bit DRAM

Memory System ............................................................................................................... 33

Table 17. CL-PS6700 Memory Map.............................................................................................. 34

Table 18. Space Field Decoding................................................................................................... 34

DS474PP1 9

EP7212

Table 19. Effect of Endianness on Read Operations .................................................................... 37

Table 20. Effect of Endianness on Write Operations ....................................................................37

Table 21. Serial Interface Options.................................................................................................39

Table 22. Serial-Pin Assignments................................................................................................. 39

Table 23. ADC Interface Operation Frequencies ..........................................................................43

Table 24. Instructions Supported in JTAG Mode ..........................................................................50

Table 25. Device ID Register ........................................................................................................51

Table 26. EP7212 Memory Map in External Boot Mode............................................................... 53

Table 27. EP7212 Internal Registers (Little Endian Mode)........................................................... 55

Table 28. EP7212 Internal Registers (Big Endian Mode)..............................................................57

Table 29. SYSCON1 ..................................................................................................................... 59

Table 30. SYSCON2 ..................................................................................................................... 61

Table 31. SYSCON3 ..................................................................................................................... 63

Table 32. SYSFLG ........................................................................................................................ 64

Table 33. SYSFLG2 ...................................................................................................................... 66

Table 34. INTSR1.......................................................................................................................... 67

Table 35. INSTR2..........................................................................................................................69

Table 36. INTSR3.......................................................................................................................... 70

Table 37. Values of the Bus Width Field ....................................................................................... 72

Table 38. Values of the Wait State Field at 13 MHz and 18 MHz .................................................72

Table 39. Values of the Wait State Field at 36 MHz......................................................................72

Table 40. MEMCFG ......................................................................................................................73

Table 41. LED Flash Rates ...........................................................................................................75

Table 42. LED Duty Ratio..............................................................................................................75

Table 43. PMPCON.......................................................................................................................76

Table 44. Sense of PWM control lines .......................................................................................... 76

Table 45. UARTDR1-2 UART1-2 ..................................................................................................77

Table 46. UBRLCR1-2 UART1-2 ..................................................................................................78

Table 47. LCDCON ....................................................................................................................... 79

Table 48. Grayscale Value to Color Mapping................................................................................81

Table 49. SYNCIO.........................................................................................................................82

Table 50. DAI Control Register .....................................................................................................86

Table 51. DAI Data Register 0 ......................................................................................................89

Table 52. DAI Data Register 1 ......................................................................................................90

Table 53. DAI Data Register 2 ......................................................................................................91

Table 54. DAI Control, Data and Status Register Locations .........................................................92

Table 55. absolute Maximum Ratings...........................................................................................96

Table 56. Recommended Operating Conditions ...........................................................................96

Table 57. DC Characteristics ........................................................................................................96

Table 58. AC Timing Characteristics.............................................................................................98

Table 59. Timing Characteristics................................................................................................... 99

Table 60. I/O Buffer Output Characteristics ................................................................................111

Table 61. 208-Pin LQFP Numeric Pin Listing.............................................................................. 111

Table 62. EP7212 Hardware Test Modes...................................................................................114

Table 63. Oscillator and PLL Test Mode Signals ........................................................................ 115

Table 64. Software Selectable Test Functionality ....................................................................... 115

Table 65. 208-Pin LQFP Numeric Pin Listing.............................................................................. 117

Table 66. 256-Ball PBGA Ball Listing..........................................................................................121

10 DS474PP1

EP7212

1. CONVENTIONS

This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet.

1.1 Acronyms and Abbreviations

Table 1 lists abbreviations and acronyms used in

this data sheet.

Acronym/

Abbreviation

AC alternating current. A/D analog-to-digital. ADC analog-to-digital co nve r ter.

CMOS CODEC coder / decoder.

CPU central processing unit. D/A digital-to-analog. DC direct current. DMA direct-memory access. EPB embedded peripheral bus. FCS frame check sequence. FIFO first in / first out. GPIO general purpose I/O. ICT in circuit test. IR infrared. IrDA Infrared Data Association. JTAG Joint Test Action Group. LCD liquid crystal displa y. LED light-emitting diode. LQFP low profile quad flat pack. LSB least significant bit.

MIPS MMU memory management unit.

MSB most significant bit. PBGA plastic ball grid array. PCB printed circuit board. PDA personal digital assistant.

complementary metal oxide semiconductor.

millions of instructions per second.

Definition

Acronym/

Abbreviation

PIA peripheral inter face a dapt er. PLL phase locked loop. PSU power supply unit. p/u pull-up resistor. RAM random access memory.

RISC ROM read-only memory.

RTC Real Time Clock. SIR slow (9600–115.2 kb ps) infrared . SRAM static random access memory. SSI synchronous serial interface. TAP te st ac ces s port. TLB tran slati on loo ka side buffer.

UART

Table 1. Acronyms and Abbreviations (cont.)

reduced instruction set computer.

universal asynchro n ous receiver.

Definition

Table 1. Acronyms and Abbreviations

DS474PP1 11

EP7212

1.2 Units of Measurement

Symbol Unit of Measure

°C

Hz hertz (cycle per second) kbits/s kilobits per second kbyte kilobyte (1,024 bytes) kHz kilohertz

Ω kilohm

k Mbps megabits (1,048,576 bits) per second Mbyte megabyte (1,048,576 bytes) MHz megahertz (1,000 kilohertz)

µAmicroampere µFmicrofarad µWmicrowatt µs microsecond (1,000 nanoseconds)

mA milliampere mW milliwatt ms millisecond (1,000 microseconds) ns nanosecond Vvolt Wwatt

degree Celsius

a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, ‘11’ designates a binary number). Numbers not indicated by an ‘h’, 0x or quotation marks are decimal.

Registers are referred to by acronym, as listed in the tables on the previous page, with bits listed in brackets MSB-to-LSB separated by a colon (:) (for example, CODR[7:0]), or LSB-to-MSB separated by a hyphen (for example, CODR[0–2]).

The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘n/c’ indicates a pin that is a ‘no connect’.

1.4 Pin Description Conventions

Abbreviations used for signal directions are listed in Table 3.

Abbreviation Direction

I Input OOutput I/O Input or Output

Table 2. Unit of Measurement

1.3 General Conventions

Hexadecimal numbers are presented with all letters in uppercase and a lowercase ‘h’ appended or with

Table 3. Pin Description Conventions

12 DS474PP1

2. PIN INFORMATION

2.1 208-Pin LQFP Pin Diagram

EP7212

VDDOSC

MOSCIN

MOSCOUT

VSSOSC WAKEUP NPWRFL

A[6] D[6] A[5]

D[5] VDDIO VSSIO

A[4]

D[4]

A[3]

D[3]

A[2] VSSIO

D[2]

A[1]

D[1]

A[0]

D[0]

VSSCORE

VDDCORE

VSSIO VDDIO

CL[2] CL[1]

FRM

DD[3] DD[2]

VSSIO

DD[1]

DD[0] NRAS[1] NRAS[0] NCAS[3] NCAS[2]

VDDIO

VSSIO NCAS[1] NCAS[0]

NMWE

NMOE

VSSIO NCS[0] NCS[1] NCS[2] NCS[3] NCS[4]

/DRA[10]

/DRA[12]

/DRA[11]

NEXTPWR

BATOK

NPOR

NURESET

NMEDCHG/NBROM

156

155

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186

187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

D[7]

A[7]

D[8]

A[8]

D[9]

D[10]

A[10]

VSSIO

VDDIO

A[11]

D[12]

A[12]

D[13]

A[13]

D[14]

NBATCHG

VSSIO

154

153

152

151

150

149

148

147

146

D[11]

A[9]

145

144

143

140

139

138

137

141

142

A[14]

132

134

136

135

133

D[17]

D[15]

131

A[15]

130

A[17]

NTRST

A[16]

128

VSSIO

124

125

126

127

D[16]

129

EP7212

208-Pin LQFP

(Top View)

2345678910111213141516171819202122232425262728293031323334353637383940414243444546474849515052

VDDIO

D[18]

122

123

/DRA[8]

/DRA[9]

A[18

D[19]

A[19]

119

120

121

/DRA[6]

/DRA[4]

A[23]

110

/DRA[3]

D[24]

VSSIO

VDDIO

A[24]

HALFWORD

106

107

108

109

105

104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

D[25] A[25]/DRA[2 ] D[26] A[26]/DRA[1 ] D[27] A[27]/DRA[0 ] VSSIO D[28] D[29] D[30] D[31] BUZ COL[0] COL[1] TCLK VDDIO COL[2] COL[3] COL[4] COL[5] COL[6] COL[7] FB[0] VSSIO FB[1] SMPCLK ADCOUT ADCCLK DRIVE[0] DRIVE[1] VDDIO VSSIO VDDCORE VSSCORE NADCCS ADCIN SSIRXFR SSIRXDA SSITXDA SSITXFR VSSIO SSICLK PD[0]/LEDFL SH PD[1] PD[2] PD[3] TMS VDDIO PD[4] PD[5] PD[6] PD[7]

/DRA[7]

D[20]

A[20]

117

118

/DRA[5]

VSSIO

A[21]

D[22]

D[23]

A[22]

D[21]

111

112

113

114

115

116

TDI

PB[7]

PB[6]

PB[5]

PB[4]

VSSIO

VDDIO

NCS[5]

EXPCLK

TXD[2]

WORD

WRITE

VSSIO

RXD[2]

EXPRDY

PB[3]

RUN/CLKEN

TDO

PB[2]

PB[1]/PRDY[2]

PB[0]/PRDY[1]

VDDIO

PA[6]

PA[5]

PA[4]

PA[3]

PA[2]

PA[1]

PA[7]

PA[0]

TXD[1]

LEDDRV

CTS

DSR

DCD

VSSIO

PHDIN

RXD[1]

EINT[3]

NEINT[2]

NEINT[1]

NTEST[1]

NEXTFIQ

NTEST[0]

PE[2]/CLKSEL

PE[1]BOOTSEL[1]

PE[0]BOOTSEL[0]

N/C

RTCIN

VDDRTC

VSSRTC

RTCOUT

Notes: 1) For package specifications, please see 208--Pin LQFP Package Outline Drawing on page 125

2) N/C should not be grounded but left as no connects

Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

DS474PP1 13

EP7212

2.2 Pin Descriptions

Table 4 describes the function of all the external signals to the EP7212. Note that all output signals and all

I/O pins (when acting as outputs) are three stateable. This is to enable the Hi-Z test modes to be supported.

2.2.1 External Signal Functions

Function Signal

Signal Description

Name

Data bus D[0-31] I/O 32-bit system data bus for memory, DRAM, and I/O interface

A[0-14] O 15 bits of system byte address during memory and expansion cycles

Address bus

Memory

Interface

A[15-27]

DRA[0-12]

nRAS[0-1] O Row Address Select outputs to DRAM banks 0 to 1. nCAS[0-3] I/O Column Address Select outputs allowing for bytes 0 to 3 within a 32-bit word.

nMOE O Memory output enable

nMWE O Memory write enable nCS[0-3] O Chip select; active low, SRAM-like chip selects for expansion nCS[4-5] O Chip select; active low, CS for expansion or for CL-PS6700 select

EXPRDY I Expansion port ready; external expansion devices drive this low to extend the

WRITE O Write strobe, low during reads, high during writes from the EP7212

WORD/

HALFWORD

DRA[0-12] is multiplexed with A[15-27], offering additional power savings since the lightest loading is exp ect ed on the hig h or der ROM addres s lines . Whenever the EP7212 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to p reve nt perip herals that are powe red-d own from draining current. Also, the internal peripheral’s signals get set to their Reset State.

bus cycle. This is used to insert wait states for an external bus cycle.

O To do write accesses of dif ferent s izes W ord and Half -W ord must be externall y

decoded. The encoding of these signals is as follows:

Access Size Word Half-Word

Word 1 0

Half-Word * 1

Byte 0 0

The core will generate an address. When doing a read, the ARM core will select the appropriate byte channels. When doing a write, the correct bytes will have to be enabled depending on the above signals and the least significant bits of the address bus. The ARM architecture does no t sup port un ali gne d ac ces s es. For a read using x 32 memory, it is assumed tha t y ou w ill i gno re b it s 1 an d 0 of the address bus and perform a word rea d (or i n po wer c ritical systems decode the relevant bits depending on the size of the access). If an unaligned read takes place, the core will rotate the resulting data in the register. For more information on this behavior see the LDR instruction in the ARM7TDMI data sheet.

EXPCLK I/O Expansion clock rate is the same as the CP U cl ock fo r 13MHz and 18 MHz. It

runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is used as the clock input.

Table 4. External Signal Functions

14 DS474PP1

EP7212

Function Signal

Name

nMEDCHG/

nBROM

Interrupts

Power

Management

State Control

nEXTFIQ I External active low fast interrupt request input

EINT[3] I External active high interrupt request input

nEINT[1:2] I Two general purpose, active low interrupt inputs

nPWRFL

BATOK

nEXTPWR I External power sense; must be driven low if the system is powered by an

nBATCHG

nPOR I Power-on reset input. This signal is not deglitched. When active it completely

RUN/CLKEN I/O This pin is programmed to either output the RUN signal or the CLKEN signal.

WAKEUP

nURESET

Signal Description

I Media changed input; active low, deglitched. Used as a general purpose FIQ

interrupt during normal ope r ati on. It is also us ed on pow er up to co nfi gure the processor to either boot from the internal Boot ROM, or from external memory. When low, the chip will boot from the internal Boot ROM.

I Power fail input; active low, deglitched input to force system into the Standby

State

I Main battery OK in put; fallin g edge generat es a FIQ , a low level i n the Standby

State inhibits system start up; deglitched input

external source

I New battery sense; driven low if battery voltage falls below the "no-battery"

threshold; it is a deglitched input

resets the entire system, including all the RTC registers. Upon power-up, the signal must be held active low for a minimum of 100 µsec after V

tled. During normal operation, nPOR needs to be held low for at least one clock cycle of the selected clock speed (i.e., when running at 13 MHz, the pulse width of nPOR needs to be > 77 nsec).

Note that nURESET, RUN/CLKEN, TEST(0), TEST(1), PE(0), PE(1), PE(2), DRIVE(0), DRIVE(1), DD(0), DD(1), DD(2), and DD(3) are all latched on the rising edge of nPOR.

The CLKENSL bit is used to configure this pin. When RUN is selected, the pin will be high when the system is active or idle, low while in the Standby State. When CLKEN is selected, the pin will only be driven low when in the Standby State (For RUN, see Table 6).

Wake up is a deglitched input signal. It must also be held high for at least 125

µsec to guarantee its detection. Once detected it forces the

system into the Operating State from the Standby State. It is only active when the system is in the Standby State. This pin is ignored when the system is in the Idle or Operating State. It is used to wakeup the system after first power-up, or after software has forced the system into the Standby State. WAKEUP will be ignored for up to two seconds after nPOR goes HIGH. Therefore, the external WAKEUP logic must be designed to allow it to rise and stay HIGH for at least 125 usec, two seconds after nPOR goes HIGH.

I User reset input; active low deglitched input from user reset button.

This pin is also latched upon the rising edge of nPOR and read along with the input pins nTEST[0-1] to force the device into special test modes. nURESET does not reset the RTC.

has set-

Table 4. External Signal Functions (cont.)

DS474PP1 15

EP7212

Function Signal

DAI, Codec or

SSI2

Interface

(See Table 5 for

pin assignment and direction following multiplex-

ing)

ADC

Interface

(SSI1)

IrDA and

RS232

Interfaces

LCD

Keyboard & Buzzer drive LED Flasher

SSITXFR I/O DAI/Codec/SSI2 serial data output frame/synchronization pulse output SSITXDA O DAI/Codec/SSI2 serial data output

SSIRXDA I DAI/Codec/SSI 2 serial data input

SSIRXFR I/O SSI2 serial data i nput frame/synchronization pulse

ADCOUT O Seria l data output

SMPCLK O Sample clock output

RXD[1-2] I RS232 UART1 and 2 RX inputs

LEDFLSH

Signal Description

Name

SSICLK I/O DAI/Codec/SSI2 clock signal

DAI external clock input ADCCLK O Serial clock output nADCCS O Chip select for ADC interface

ADCIN I Serial data input

LEDDRV O Infrared LED drive output (UART1)

PHDIN I Photo diode input (UART1)

TXD[1-2] O RS232 UART1 and 2 TX outputs

DSR I RS232 DSR input DCD I RS232 DCD input CTS I RS232 CTS input

DD[0-3] I/O LCD serial display data; pins can be used on power up to read the ID of some

LCD modules (See Table 6).

CL[1] O LCD line clock CL[2] O LCD pixel clock

FRM O LCD frame synchronization pulse output

M O LCD AC bias drive

COL[0-7] O Keyboard column drives (SYSCON1)

BUZ O Buzzer drive output (SYSCON1)

PD[0]/

O LED flasher driver — multiplexed with Port D bit 0. This pin can provide up to

4 mA of drive current.

Table 4. External Signal Functions (cont.)

16 DS474PP1

EP7212

Function Signal

Signal Description

Name

PA[0:7] I/O Port A I/O (bit 6 for boot clock option, bit 7 for CL-PS6700 PRDY input); also

used as keyboard row inputs

General

Purpose I/O

PWM

Drives

Boundary

Scan

Test nTEST[0:1] I Test mode select inputs . Thes e pins are u sed in conju nct ion with t he pow er-on

Oscillators

No Connects N/C No connects should be left as no connects; do not connect to ground

PB[0]/PRDY1 PB[1]/PRDY2

PB[2:7]

PD[0:7] I/O Port D I/O

PE[0]/

BOOTSEL[0]

PE[1]/

BOOTSEL[1]

PE[2]/

CLKSEL

DRIVE[0:1] I/O PWM drive outputs. These pins are inputs on power up to determine w hat

FB[0:1] I PWM feedback inputs

TDI I JTAG data in TDO O JTAG data out TMS I JTAG mode select

TCLK I JTAG clock

nTRST I JTAG async reset

MOSCIN

MOSCOUT

RTCIN

RTCOUT

I/O Port B I/O. All eight Port B bits can be used as GPIOs.

When the PC CARD1 or 2 control bits in the SYSCON2 register are deasserted, PB[0] and PB[1] are available for GPIO. When asserted, these port bits are used as the PRDY signals for connected CL-PS6700 PC Card Host Adapter devices.

I/O Port E I/O (3 bits only). Can be used as general purpose I/O during normal

operation.

I/O During power-on reset, PE[0] and PE[1] are inputs and are latched by the ris-

ing edge of nPOR to s el ect the me mo ry wi d th tha t th e EP7212 will use to read from the boot code storage device (i.e., external 8-bit-wide FLASH bank).

I/O During power-on reset, PE[2] is latched by the rising edge of nPOR to select

the clock mode of operation (i.e., either the PLL or external 13 MHz clock mode).

polarity the output of the PWM should be when active. Otherwise, these pins are always an output (See Table 6).

latched state of nURESET to select between the various device test models.

Main 3.6864 MHz oscillator for 18.432 MHz–73.728 MHz PLL

Real Time Clock 32.768 kHz oscillator

Table 4. External Signal Functions (cont.)

1. All deglitched inputs are via the 16.384 kHz clock. Each deglitched signal must be held active for at least two clock periods. Therefore, the input signal must be active for at least ~125

µs to be detected cleanly.

The RTC crystal must be populated for the device to function properly.

DS474PP1 17

EP7212

2.2.2 SSI/Codec/DAI Pin Multiplexing

SSI2 Codec DAI Direction Strength

SSICLK PCMCLK SCLK I/O 1 SSITXFR PCMSYNC LRCK I/O 1 SSITXDA PCMOUT SDOUT Output 1

SSIRXDA PCMIN SDIN Input SSIRXFR p/u* MCLK I/O 1

* p/u = use an ~10 k pull-up

The selection between SSI2 and the codec is controlled by the state of the SERSEL bit in SYSCON2 (See SYSCON2 System Control Register 2). The choice between the SSI2, codec, and the DAI is controlled by the DAISEL bit in SYSCON3 (See SYSCON3 System Control Register 3).

Table 5. SSI/Codec/DAI Pin Mu lt iplexing

2.2.3 Output Bi-Directional Pins

RUN The RUN pin is looped back in to skew the address and data bus from each other. nCAS[3:0] The nCAS pins are looped back into the EP7212 to be used as the actual clock source for the data to be

latched internally.

Drive [0-1] Drive 0 and 1 are looped back in on power up to determine what polarity the output of the PWM should be

when active.

DD[3:0] DD[3:0] are looped back in on power up to enable the reading of the ID of some LCD modules.

NOTE: The above output p ins are implemen ted as b i-direction al pins to enable the output side of the pad to

be monitored and hence provide more accurate control of timing or duration.

Table 6. Output Bi-Directional Pin s

18 DS474PP1

EP7212

3. FUNCTIONAL DESCRIPTION

The EP7212 device is a single-chip embedded controller designed to be used in low-cost and ultralow-power applications. Operating at 74 MHz, the EP7212 delivers approximately 66 Dhrystone

2.1 MIPS of sustained performance (74 MIPS peak). This is approximately the same as a 100 MHz Pentium-based PC.

The EP7212 contains the following functional blocks:

• ARM720T processor which consists of the following functional sub-blocks:

- ARM7TDMI CPU core (which supports

the logic for the Thumb instruction set, core debug, enhanced multiplier, JTAG, and the Embedded ICE) running at a dynamically programmable clock speed of 18 MHz, 36 MHz, 49 MHz, or 74 MHz.

- Memory Management Unit (MMU) com-

patible with the ARM710 core (providing address translation and a 64-entry translation lookaside buffer) with added support for Windows CE.

- 8 kbytes of unified instruction and data

cache with a four-way set associative cache controller.

- Write buffer

• 38,400 bytes (0x9600) of on-chip SRAM that can be shared between the LCD controller and general application use.

• Memory interfaces for up to 6 independent 256 Mbyte expansion segments with progra mming wait states.

• 27 bits of general purpose I /O - multiplexed to provide additional functionality where necessary.

• Digital Audio Interface (DAI) for connection to CD-quality DACs and codecs.

• Interrupt controller

• Advanced system state control and power management.

• Two full-duplex 16550A compatible UARTs with 16-byte transmit and receive FIFOs.

• IrDA SIR protocol controller capable of speeds up to 115.2 kbps.

• Programmable 1-, 2-, or 4-bit-per-pixel LCD controller with 16-level grayscaler.

• Programmable frame buffer start address, allowing a system to be built using only internal SRAM for memory.

• On-chip boot ROM programmed with serial load boot sequence.

• Two 16-bit general purpose timer counters.

• A 32-bit Real Time Clock (RTC) and comparator.

• Dedicated LED flasher pin driven from the RTC with programmable duty ratio (multiplexed with a GPIO pin).

• Two synchronous serial interfaces for Microwire or SPI peripherals such as ADCs, one supporting both the master and slave mode and the other supporting only the master mode.

• Full JTAG boundary scan and Embedded ICE support.

• Two programmable pulse-width modulation interfaces.

• An interface to one or two Cirrus Logic CLPS6700 PC Card controller devices to support two PC Card slots.

• EDO DRAM support (Fast Page DRAM is only supported at 13 MHz and 18 MHz. It can interface up to two banks of DRAM. Each bank can be up to 256 Mbytes in size. The DRAM interface is programmable to be 16-bit or 32-bit wide.

DS474PP1 19

EP7212

• Oscillator and phase-locked loop (PLL) to generate the core clock speeds of 18.432 MHz,

36.864 MHz, 49.152 MHz, and 73.728 MHz from an external 3.6864 MHz cr ystal, with an alternative external clock input (used in 13 MHz mode).

• A low power 32.768 kHz oscillator.

The EP7212 design is optimized for low power dissipation and is fabricated on a fully static

0.25 micron CMOS process. It is available in a

256-ball PBGA or a 208-pin LQFP package.

Figure 2 shows a simplified block diagram of the

EP7212. All external memory and peripheral devices are connected to the 32-bit data bus using the external 28-bit address bus and control signals.

3.1 CPU Core

The ARM720T consists of an ARM7TDMI 32-bit RISC processor, a unified cache, and a memory management unit (MMU). The cache is four-way set associative with 8-kbytes organized as 512 lines of 4 words. The cache is directly connected to the ARM7TDMI, and therefore caches the virtual address from the CPU. When the cache misses, the MMU translates the virtual address into a physical address. A 64-entry translation lookaside buffer (TLB) is utilized to speed the address translation process and reduce bus traffic necessary to read the page table. The MMU saves power by only translating the cache misses.

See the ARM720T Data sheet for a complete description of the various logic blocks that make up the processor, as well as all internal registe r information.

13-MHZ INPUT

3.6864 MHZ

32.768 KHZ

NPOR, RUN,

RESET, WAKEUP

BATOK, EXTPWR PWRFL, BATCHG

EINT[1-3], FIQ,

MEDCHG

FLASHING LED DRIVE

PORTS A, B, D (8-B IT)

PORT E (3-BIT)

KEYBD DRIVERS (0–7)

BUZZER DRIVE

DC-TO-DC

ADCCLK, ADCIN,

ADCOUT, SMPCLK,

ADCCS

SSICLK, SSIT XFR,

SSITXDA, SSIRXDA,

SSIRSFR

PLL

32.768-KHZ

OSCILLATOR

STATE CONTROL

POWER

MANAGEMENT

INTERRUPT

CONTROLLER

RTC

GPIO

PWM

SSI1 (ADC)

DAI

SSI2

CODEC

ARM720T

ARM7TDMI CPU CORE

8-KBYTE

CACHE

MMU

WRITE

BUFFER

TIMER

COUNTERS (2)

ON-CHIP

BOOT ROM

EPB BRIDGE

EPB BUS

INTERNAL DATA BUS

MEMORY CONTROLLER

CL-PS6700

INTFC.

EXPANSION

CONTROL

DRAM CNTRL

INTERNAL ADDRESS BUS

LCD DMA

ICE-JTAG

LCD

CONTROLLER

ON-CHIP SRAM

38,400 BYTES

UART1

UART2

IrDA

D[0-31]

PB[0:1], NCS[4:5]

EXPCLK, WORD, NCS[0:3],

EXPRDY, WRITE MOE, MWE, NRAS[0-1], NCAS[0-3]

A[0-27],

DRA[0-12]

TEST AND

DEVELOPMENT

LCD DRIVE

LED AND

PHOTODIODE

ASYNC

INTERFACE 1

ASYNC

INTERFACE 2

Figure 2. EP7212 Block Diagram

20 DS474PP1

EP7212

Figure 3. State Diagram

Standby

Operating

Idle

Interrupt or rising wakeup

Write to standby location, power fail, or user reset

Write to halt location

nPOR, power fail, or user reset

3.2 State Control

The EP7212 supports the following Power Management States: Operating, Idle, and Standby (see

Figure 3). The normal program execution state is

the Operating State; this is a full performance state where all of the clocks and peripheral logic are enabled. The Idle State is the same as the Operating State with the exception of the CPU clock being halted, and an interrupt or wakeup will return it back to the Operating State. The Standby State has the lowest power consumption of the three states. By selecting this mode the main oscillator shuts down, leaving only the Real Time Clock and its associated logic powered. It is important when the EP7212 is in Standby that all power and ground pins remain connected to power and ground in order to have a proper system wake-up. The only state that Standby can transition to is the Operating State.

3.2.1 Standby State

The Standby State equates to the system being switched "off" (i.e., no display, and the main oscillator is shut down). When the 18.432–73.72 MHz mode is selected, the PLL will be shut down. In the 13 MHz mode, if the CLKENSL bit is set low, then the CLKEN signal will be forced low and can, if required, be used to disable an external oscillator.

In the Standby State, all the system memory and state is maintained and the system time is kept upto-date. The PLL/on-chip oscillator or external oscillator is disabled and the system is static, except for the low power watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher. The RUN signal is driven low, therefore this signal can be used externally in the system to power down other system modules.

Whenever the EP7212 is in the Standby State, the external address and data buses are forced low internally by the RUN signal. Thi s i s do ne to preve nt peripherals that are powered down from draining current. Also, the internal peripheral’s signals get set to their Reset State.

In the description below, the RUN/CLKEN pin can be used either for the RUN functionality, or the CLKEN functionality to allow an external oscillator to be disabled in the 13 MHz mode. Either RUN or CLKEN functionality can be selected according to the state of the CLKENSL bit in the SYSCON2 register. Table 7 on the following page shows peripheral status in various power management states.

When first powered, or reset by the nPOR (Power On Reset, active low) signal, the EP7212 is forced into the Standby State. This is known as a cold reset, and when leaving the Standby State after a cold reset, external wake up is the only way to wake up the device. When leaving the Standby State after non-cold reset conditions (i.e., the software has forced the device into the Standby State), the transition to the Operating State can be caused by a rising edge on the WAKEUP input signal or by an enabled interrupt. Normally, when entering the Standby State from the Operating State, the software will leave some interrupt sources enabled.

NOTE: The CPU cannot be awakened by the TINT,

WEINT, and BLINT interrupts when in the Standby State.

Typically, software writes to the Standby internal memory location to cause the transition from the

DS474PP1 21

EP7212

Address (W/B) Operating Idle Standby nPOR

RESET

DRAM Control On On SELFREF Off SELFREF

UARTs On On Off Reset Reset LCD FIFO On On Reset Reset Reset LCD On On Off Reset Reset ADC Interface On On Off Reset Reset SSI2 Interface On On Off Reset Reset DAI Interface On On Off Reset Reset Codec On On Off Reset Reset Timers On On Off Reset Reset RTC On On On On On LED Flasher On On On Reset Reset DC-to-DC On On Off Reset Reset CPU On Off Off Reset Reset Interrupt Control On On On Reset Reset PLL/CLKEN Signal On On Off Off Off

Table 7. Peripheral Status in Different Power Management States

nURESET

RESET

Operating State to the Standby State. Before entering the Standby State, if external I/O devices (such as the CL-PS6700s connected to nCS[4] or nCS[5]) are in use, the software must c heck to ensure that they are idle before issuing the write to the Standby State location.

Before entering the Standby State, the software must properly disable the DAI. Failing to do so will result in higher than expected power consumption in the Standby State, as well as unpredictable operation of the DAI. The DAI ca n be r e-enabled afte r transitioning back to the Operating State.

The system can also be forced into the Standby State by hardware if the nPWRFL or nURESET inputs are forced low. The only exit from the Standby State is to the Operating State.

The system will only transition to the Operating State from the Standby State under the following conditions: when the nPWRFL input pin is high when the nEXTPWR input pin is low or when the BATOK input pin is high. This prevents the system

from starting when the power supply is inadequate (i.e., the main batteries are low), corresponding to a low level on nPWRFL or BATOK.

From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock running, the EP7212 will be initialized into a state where it is ready to start and is waiting for the CPU to start receiving its clock. The CPU will still be held in reset at this point. After the first clock is applied, there will be a delay of about eight clock cycles before the CPU is enabled. This delay is to allow the clock to the CPU time to settle.

3.2.1.1 UART in Standby State

During the Standby State, the UARTs are disabled and cannot detect any activity (i.e., start bit) on the receiver. If this functionality is required then this can be accomplished in software by the following method:

1) Permanently connect the RX pin to one of the active low external interrupt pins.

22 DS474PP1

EP7212

2) Ensure that on entry to the Standby State, the chosen interrupt source is not masked, and the UART is enabled.

3) Send a preamble that consists of one start bit, 8 bits of zero, and one stop bit. This will cause the EP7212 to wake and execute the enabled interrupt vector.

The UART will automatically be re-enabled when the processor re-enters the Operating State, and the preamble will be received. Since the UART was not awake at the start of the pream ble, the timing of the sample point will be off-center during the preamble byte. However, the next byte transmitted will be correctly aligned. Thus, the actual first real byte to be received by the UART will get captured correctly.

3.2.2 Idle State

If in the Operating State, the I dle State can be en tered by writing to a special internal memory location (HALT) in the EP7212. If an interrupt occurs, the EP7212 will return immediately back to the Operating State and execute the next instruction. The WAKEUP signal can not be used to exit the Idle State. It is only used to exit the Standby State.

In the Idle State, the device functions just like it does when in the Operating State. However, the CPU clock is halted while it waits for an event such as a key press to generate an interrupt. The PLL (in

18.432–73.728 MHz mode) or the external

13 MHz clock source always remains active in the Idle State.

3.2.3 Keyboard Interrupt

For the case of the keyboard interrupt, the following options are available and are selectable according to bits 1 and 3 of the SYSCON2 register (refer to the SYSCON2 Register Description for details).

• If the KBWEN bit (SYSCON2 bit 3) is set low, then a keypress will cause a transition from a

power saving state only if the keyboard interrupt is non-masked (i.e., the interrupt mask register 2 (INTMR2 bit 0) is high).

• When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the interrupt mask register. This is called the “Keyboard Direct Wakeup’ mode. In this mode, the interrupt request may not get serviced. If the interrupt is masked (i.e., the interrupt mask register 2 (INTMR2 bit 0) is low), the processor simply starts re-executing code from where it left off before it entered the power saving state. If the interrupt is non-masked, then the processor will service the interrupt.

• When the KBD6 bit (SYSCON2 bit 1) is low, all 8 of Port A inputs are OR’ed together to produce the internal wakeup signal and keyboard interrupt request. This is the default reset state.

• When the KBD6 bit (SYSCON2 bit 1) is high, only the lowest 6 bits of Port A are OR’ed together to produce the internal wakeup signal and keyboard interrupt request. The two most significant bits of Port A are available as GPIO when this bit is set high.

In the case where KBWEN is low and the INTMR2 bit 0 is low, it will only be possible to wakeup the device by using the external WAKEUP pin or another enabled interrupt source. The keyboard interrupt capability allows an OS to use either a polled or interrupt-driven keyboard routine, or a combination of both.

NOTE: The keyboard interrup t is NOT deglit ch ed.

3.3 Power-Up Sequence

The EP7212 has a power-up sequence that should be followed for proper start up. If any of the below recommended timing sequences are violated, then it is possible that the part may not start-up properly. This could cause the device to get lost and not recover without a hard reset.

DS474PP1 23

EP7212

1). Upon power, the signal nPOR must be held active (LOW) for a minimum of 100us, after VDD has become settled.

2). After nPOR goes HIGH, the EP7212 will enter the Standby State (and only this state). In this state, the PLL is not enabled, and thus the CPU is not enabled either. The only method that can be used to allow the EP7212 to exit the Standby State into the Operating State is by the WAKEUP signal going active (HIGH).

NOTE: It is not a requirement to use the nURE SET

signal. If not us ed, the nURESET signal must be HIGH, and it must have gone HIGH prior to nPOR going HIGH. This is due to the fact that nURESET is latched into the device by the rising edge of nPOR. When nURESET is LOW on the rising ed ge of nPOR, it can force the device into one of its Test Mode states.

3). After nPOR goes HIGH, the WAKEUP signal cannot be detected as going HIGH, until after at least two seconds. After two seconds, the WAKEUP signal can become active, and it must be HIGH for at least 125us.

4). After the WAKEUP signal is detected internally, it first goes through a deglitching circuit. This is why is must be active for at least 125us. Then the PLL gets enabled. WAKEUP is ignored immediately after waking up the system. It also ignores it while in the Idle or Operating State. It can constantly toggle with no affect on the device. It will only be read again if nPOR goes low and then high again, or if software has forced the device back into the Standby State.

5). A maximum of 250 msec will pass before the CPU becomes enabled and starts to fetch the first instruction.

3.4 Resets

There are three asynchronous resets to the EP7212: nPOR, nPWRFL and nURESET. If any of these are active, a system reset is generated internally. This will reset all internal registers in the EP7212 except

the RTC data and match registers. These registers are only cleared by nPOR allowing the system time to be preserved through a user reset or power fail condition.

Any reset will also reset the CPU and cause it to start execution at the reset vector when the EP7212 returns to the Operating State.

Internal to the EP7212, three different signals are used to reset storage elements. These are nPOR, nSYSRES and nSTBY. nPOR is an external signal. nSTBY is equivalent to the external RUN signal.

nPOR (Power On Reset, active low) is the highest priority reset signal. When active (low), it will reset all storage elements in the EP7212. nPOR active forces nSYSRES and nSTBY active. nPOR will only be active after the EP7212 is first powered up and not during any other resets. nPOR active will clear all flags in the status register except for the cold reset flag (CLDFLG) bit (SYSFLG, bit 15), which is set.

nSYSRES (System Reset, active low) is generated internally to the EP7212 if nPOR, nPWRFL, or nURESET are active. It is the second highest priority reset signal, used to asynchronously reset most internal registers in the EP7212. nSYSRES active forces nSTBY and RUN low. nSYSRES is used to reset the EP7212 and force it into the Standby State with no co-operation from software. The CPU is also reset.

The nSTBY and RUN signals are high when the EP7212 is in the Operating or Idle States and low when in the Standby State. The main system clock is valid when nSTBY is high. The nSTBY signal will disable any peripheral block that is clocked from the master clock source (i.e., everything except for the RTC). In general, a system reset will clear all registers and nSTBY will disable all peripherals that require a main clock. The following peripherals are always disabled by a low level on nSTBY: two UARTs and IrDA SIR encoder, timer counters, telephony codec, and the two SSI inter-

24 DS474PP1

EP7212

faces. In addition, when in the Standby State, the LCD controller and PWM drive are also disabled.

When operating from an external 13 MHz oscillator which has become disabled in the Standby State by using the CLKEN (SYSCON, bit 13) signal (i.e., with CLKENSL = 0), the oscillator must be stable within 0.125 sec from the rising edge of the CLKEN signal.

3.5 Clocks

There are two clocking modes for the EP7212. Either an external clock input can be used or the onchip PLL. The clock source is selected by a strapping option on Port E, pin 2 (PE[2]). If PE[2] is high at the rising edge of nPOR (i.e., upon powerup), the external clock mode is selected. If PE[2] is low, then the on-chip PLL mode is selected. After power-up, PE[2] can be used as a GPIO.

The EP7212 device contains several separate sections of logic, each clocked according to its own clock frequency requirements. When the EP7212 is in external clock mode, the actual frequencies at the peripherals will be different than when in PLL mode. See each peripheral device section for more details. The section below describes the clocking for both the ARM720T and address/data bus.

3.5.1 On-Chip PLL

The ARM720T clock can be programmed to

18.432 MHz, 36.864 MHz, 49.152 MHz, or

73.728 MHz with the PLL running at twice the highest possible CPU clock frequency (147.456 MHz). The PLL uses an external

3.6864 MHz crystal. By chip default, the on-chip PLL is used and configured such that the ARM720T and address/data buses run at

18.432 MHz. When the clock frequency is selected to be

36 MHz, both the ARM720T and the address/data buses are clocked at 36 MHz. When the clock frequency is selected higher than 36 MHz, only the

ARM720T gets clocked at this higher speed. The address/data will be fixed at 36 MHz. The clock frequency used is selected by programming the CLKCTL[1:0] bits in the SYSCON3 register. The clock frequency selection does not effect the EPB (external peripheral bus). Therefore, all the peripheral clocks are fixed, regardless of the clock speed selected for the ARM720T.

NOTE: After modifying the CLKCTL[1:0] bits, the

next instruction should always be a ‘NOP’.

3.5.1.1 Characteristics of the PLL Interface

When connecting a crystal to the on-chip PLL interface pins (i.e. MOSCIN and MOSCOUT), the crystal and circuit should conform to the following requirements:

• The 3.6864 MHz frequency should be created by the crystals fundamental tone (i.e., it should be a fundamental mode crystal).

• A start-up resistor is not necessary, since one is provided internally.

• Start-up loading capacitors may be placed on each side of the external crystal and ground. Their value should be in the range of 10 pF. However, their values should be selected based upon the crystal specifications. The total sum of the capacitance of the traces between the EP7212’s clock pins, the capacitors, and the crystal leads should be subtracted from the crystal’s specifications when determining the values for the loading capacitors.

• The crystal should have a maximum 100 ppm frequency drift over the chip’s operating temperature range.

Alternatively, a digital clock source can be used to drive the MOSCIN pin of the EP7212. With this approach, the voltage levels of the clock source should match that of the VDD supply for the EP7212’s pads (i.e. the supply voltage level used to drive all of the non-VDD core pins on the EP7212).

DS474PP1 25

EP7212

The output clock pin (i.e., MOSCOUT) should be left floating.

3.5.2 External Clock Input (13 MHz)

An external 13 MHz crystal oscillator can be used to drive all of the EP7212. When selected the ARM720T and the address/data buses both get clocked at 13 MHz. The fixed clock sources to the various peripherals will have different frequencies than in the PLL mode. In this configuration, the PLL will not be used at all.

NOTE: When operating at 13 MHz, the

CLKCTL[1:0] bits should not be changed from their default value of ‘00’.

3.5.3 Dynamic Clock Switching When in the PLL Clocking Mode

The clock frequency used for the CPU and the buses is controlled by programming the CLKCTL[1:0] bits in the SYSCON3 register. When this occurs, the state controller switches from the current to the new clock frequency as soon as possible without causing a glitch on the clock signals. The glitchfree clock switching logic waits until the clock that is currently in use and the newly programmed clock source are both low, and then switches from the previous clock to the new clock without a glitch on the clocks.

EXPCLK

(internal)

RUN

CLKEN

Interrupt /

WAKEUP

13 MHz

CLKEN

Figure 4. CLKEN Timing Entering the Standby State

Figure 5. CLKEN Timing Entering the Standby State

26 DS474PP1

EP7212

3.6 Interrupt Controller

When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled.

Table 8 shows the priority order of all the excep-

tions.

Priority Exception

Highest Reset

. Data Abort .FIQ .IRQ .Prefetch Abort

Lowest Undefined Instruction,

Software Interrupt

Table 8. Exception Priority Handling

The EP7212 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources. Of these, seventeen are mapped to the IRQ input and five sources are mapped to the FIQ input. FIQs have a higher priority than IRQs. If two interrupts are received from within the same group (IRQ or FIQ), the order in which they are serviced must be resolved in software. The priorities are listed in

Table 9. All interrupts are level sensitive; that is,

they must conform to the following sequence.

1) The interrupting device (either external or internal) asserts the appropriate interrupt.

2) If the appropriate bit is set in the interrupt mask register, then either a FIQ or an IRQ will be asserted by the interrupt controller. (A description for each bit in this register can be found in INTSR1 Interrupt Status Register 1).

3) If interrupts are enabled the processor will jump to the appropriate address.

4) Interrupt dispatch software reads the interrupt

status register to establish the source(s) of the interrupt and calls the appropriate interrupt service routine(s).

5) Software in the interrupt service routine will clear the interrupt source by some action specific to the device requesting the interrupt (i.e., reading the UART RX register).

The interrupt service routine may then re-enable interrupts, and any other pending interrupts will be serviced in a similar way. Alternately, it may re turn to the interrupt dispatch code, which can check for any more pending interrupts and dispatch them accordingly. The “End of Interrupt” type interrupts are latched. All other interrupt sources (i.e., external interrupt source) must be held active until its respective service routine starts executing. See “End

Of Interrupt Locations” on page 83 for more de-

tails.

Table 9, Table 10, and Table 11 show the names

and allocation of interrupts in the EP7212.

3.6.1 Interrupt Latencies in Different

States

3.6.1.1 Operating State

The ARM720T processor checks for a low level on its FIQ and IRQ inputs at the end of each instruction. The interrupt latency is therefore directly related to the amount of time it takes to complete execution of the current instruction when the interrupt condition is detected. First, there is a one to two clock cycle synchronization penalty. For the case where the EP7212 is operating at 13 MHz with a 16-bit external memory system, and instruction sequence stored in one wait state FLASH memory, the worst-case interrupt latency is 251 clock cycles. This includes a dela y for cache line fills for instruction prefetches, and a data abort occurring at the end of the LDM instruction, and the LDM being non-quad word aligned. In addition, the worst-case interrupt latency assumes that LCD DMA cycles to support a panel size of 320 x

DS474PP1 27

EP7212

Interrupt Bit in INTMR1 and

INTSR1

FIQ 0 EXTFIQ External fast interrupt input (nEXTFIQ pin) FIQ 1 BLINT Battery low interrupt FIQ 2 WEINT Tick Watchdog expired interrupt

FIQ 3 MCINT Media changed interrupt IRQ 4 CSINT Codec sound interrupt IRQ 5 EINT1 External interrupt input 1 (nEINT[1] pin) IRQ 6 EINT2 External interrupt input 2 (nEINT[2] pin) IRQ 7 EINT3 External interrupt input 3 (EINT[3] pin) IRQ 8 TC1OI TC1 underflow interrupt IRQ 9 TC2OI TC2 underflow interrupt IRQ 10 RTCMI RTC compare match interrupt IRQ 11 TINT 64 Hz tick interrupt IRQ 12 UTXINT1 Internal UART1 transmit FIFO empty interrupt IRQ 13 URXINT1 Internal UART1 receive FIFO full interrupt IRQ 14 UMSINT Internal UART1 modem status changed interrupt IRQ 15 SSEOTI Synchronous serial interface 1 end of transfer interrupt

Table 9. Interrupt Allocation in the First Interrupt Register

Name Comment

Interrupt Bit in INTMR2 and

INTSR2

IRQ 0 KBDINT Key press interrupt IRQ 1 SS2RX Master / slave SSI 16 bytes received IRQ 2 SS2TX Master / slave SSI 16 bytes transmitted IRQ 12 UTXINT2 UART2 transmit FIFO empty interrupt IRQ 13 URXINT2 UART2 receive FIFO full interrupt

Table 10. Interrupt Allocation in the Second Interrupt Register

Interrupt Bit in INTMR3 and

INTSR3

FIQ 0 DAIINT DAI interface interrupt

Table 11. Interrupt Allocation in the Third Interrupt Register

Name Comment

28 DS474PP1

EP7212

240 at 4 bits-per-pixel, 60 Hz refresh rate, is in progress.

This would give a worst-case interrupt latency of about 19.3 µs for the ARM720T processor operating at 13 MHz in this system. For those interrupt inputs which have de-glitching, this figure is increased by the maximum time required to pass through the deglitcher, which is approximately 125 µs (2 cycle of the 16.384 kHz clock derived from the RTC oscillator). This would create an absolute worst-case latency of approximately 141 µs. If the ARM720T is run at 36 MHz or greater and/or 32 bit wide external memory, the 19.3 µs value will be reduced.

All the serial data transfer peripherals included in the EP7212 (except for the master-only SSI1) have local buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or less. This assumes that the design data rates do not exceed the data rates described in this specification. If the OS cannot meet this requirement, there will be a risk of data over/underflow occurring.

3.6.1.2 Idle State

When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately two clock cycles. However, there is still potentially up to 20 µsec latency as desc ribed in the first section above, unless the code is written to include at least two single cycle instructions immediately after the write to the IDLE register (in which case the latency drops to a few microseconds). This is important, as the Idle State can only be left because of a pending interrupt, which has to be synchronized by the processor before it can be serviced.

3.6.1.3 Standby State

In the Standby State, the latency will depend on whether the system clock is shut down and if the FASTWAKE bit in the SYSCON3 register is s et. If the system is configured to run from the internal PLL clock, then the PLL will always be shut down

when in the Standby State. In this case, if the FASTWAKE bit is cleared, then there will be a latency of between 0.125 sec to 0.25 sec. If the FASTWAKE bit is set, then there will be a latency of between 250 µsec to 500 µsec. If the system is running from the external clock (at 13 MHz), with the CLKENSL bit in SYSCON2 set to 0, then the latency will also be between 0.125 sec and 0.25 sec to allow an external oscillator to stabilize. In the case of a 13 MHz system where the clock is not disabled during the Standby State (CLKENSL = 1), then the latency will be the same as descri bed in the Idle State section above.

Whenever the EP7212 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripherals that are power-down from draining current. Also, the internal peripheral’s signals get set to their Reset State.

Table 12 summarizes the five external interrupt

sources and the effect they have on the processor interrupts.

3.7 EP7212 Boot ROM

The 128 bytes of on-chip Boot ROM contain an instruction sequence that initializes the device and then configures UART1 to receive 2048 bytes of serial data that will then be placed in the on-chip SRAM. Once the download is complete, execution jumps to the start of the on-chip SRAM. This would allow, for example, code to be downloaded to program system FLASH during a product’s manufacturing process. See Appendix A: Boot Code for details of the ROM Boot Code with com- ments to describe the stages of execution.

Selection of the Boot ROM option is determined by the state of the nMEDCHG pin during a power on reset. If nMEDCHG is high while nPOR is active, then the EP7212 will boot from an external memory device connected to CS[0] (normal boot mode).

DS474PP1 29

EP7212

Interrupt

nEXTFIQ Not deglitched; must be

nEINT1–2 Not deglitched Worst-case latency

EINT3 Not deglitched Worst-case latency

nMEDCHG Deglitched by 16 kHz

Input State Operating State

Worst-case latency active for 20 µs to be detected

clock; must be active for at least 125 µs to be detected

of 20 µsec

Worst-case latency

of 141 µsec

Table 12. External Interrupt Source Latencies

Latency

If nMEDCHG is low, then the boot will be from the on-chip ROM. Note that in both cases, following the de-assertion of power on reset, the EP7212 will be in the Standby State and requires a low-to-high transition on the external WAKEUP pin in order to actually start the boot sequence.

The effect of booting from the on-chip Boot ROM is to reverse the decoding for all chip selects internally. Table 13 shows this decoding. The control signal for the boot option is latched by nPOR, which means that the remapping of addresses and bus widths will continue to apply until nPOR is asserted again. After booting from the Boot ROM, the contents of the Boot ROM can be read back from address 0x00000000 onwards, and in normal state of operation the Boot ROM contents can be read back from address range 0x70000000.

3.8 Memory and I/O Expansion Interface

Six separate linear memory or expansion segments are decoded by the EP7212, two of which can be reserved for two PC Card cards, each interfacing to a separate single CL-PS6700 device. Each segment is 256 Mbytes in size. Two additional segments (i.e., in addition to these six) are dedicated to the on-chip SRAM and the on-chip ROM. The on-chip ROM space is fully decoded, and the SRAM space

Idle State

Latency

Worst-case 20 µsec: if only single cycle instructio ns, less than 1 µsec

As above As above

Worst-case 80 µsec: if only single cycle instructions, 125 µsec

0000.0000–0FFF.FFFF CS[7]

1000.0000–1FFF.FFFF CS[6]

2000.0000–2FFF.FFFF nCS[5]

3000.0000–3FFF.FFFF nCS[4]

4000.0000–4FFF.FFFF nCS[3]

5000.0000–5FFF.FFFF nCS[2]

6000.0000–6FFF.FFFF nCS[1]

7000.0000–7FFF.FFFF nCS[0]

Table 13. Chip Select Address Ranges After Boot From

Including PLL / osc. settling time, approx. 0.25 sec when FASTWAKE = 0, or approx. 500 µsec when FASTWAKE = 1, or = Idle State if in 13 MHz mode with CLKENSL set

As above (note difference if in 13 MHz mode with CLKENSL set)

Address Range Chip Select

Standby State Latency

(Internal only)

On-Chip Boot ROM

is fully decoded up to the maximum size of the video frame buffer programmed in the LCDCON register (128 kbytes). Beyond this address range the SRAM space is not fully decoded (i.e., any accesses beyond 128 kbyte range get wrapped around to within 128 kbyte range). Any of the six segments are configured to interface to a conventional SRAM-like interface, and can be individually programmed to be 8-, 16-, or 32-bits wide, to support page mode access, and to execute from 1 to 8 wait states for non-sequential accesses and 0 to 3 for burst mode accesses. The zero wait state sequential access feature is designed to support burst mode

30 DS474PP1

+ 106 hidden pages

Cirrus Logic EP7212 Datasheet

FEATURES

OVERVIEW

Functional Block Diagram

Power Management

Memory Interfaces

Digital Audio Capability

Serial Interfaces

Digital Audio Interface (DAI)

Packaging

System Design

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

1. CONVENTIONS

1.1 Acronyms and Abbreviations

1.2 Units of Measurement

1.4 Pin Description Conventions

Table 2. Unit of Measurement

1.3 General Conventions

Table 3. Pin Description Conventions

2. PIN INFORMATION

2.1 208-Pin LQFP Pin Diagram

Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

2.2 Pin Descriptions

2.2.1 External Signal Functions

2.2.2 SSI/Codec/DAI Pin Multiplexing

2.2.3 Output Bi-Directional Pins

Table 6. Output Bi-Directional Pin s

3. FUNCTIONAL DESCRIPTION

3.1 CPU Core

Figure 2. EP7212 Block Diagram

Figure 3. State Diagram

3.2 State Control

3.2.1 Standby State

Table 7. Peripheral Status in Different Power Management States

3.2.1.1 UART in Standby State

3.2.2 Idle State

3.2.3 Keyboard Interrupt

3.3 Power-Up Sequence

3.4 Resets

3.5 Clocks

3.5.1 On-Chip PLL

3.5.1.1 Characteristics of the PLL Interface

3.5.3 Dynamic Clock Switching When in the PLL Clocking Mode

Figure 4. CLKEN Timing Entering the Standby State

Figure 5. CLKEN Timing Entering the Standby State

3.6 Interrupt Controller

Table 8. Exception Priority Handling

3.6.1.1 Operating State

Table 9. Interrupt Allocation in the First Interrupt Register

3.6.1.2 Idle State

3.6.1.3 Standby State

3.7 EP7212 Boot ROM

3.8 Memory and I/O Expansion Interface