Cirrus Logic CS5378 User Manual

CS5378

Serial Interface

Decimation and Filtering Engine

Mod u lator Data Inte r fa c e

Test Bit Stream

Con tr o lle r

Reset, Synchronization

TBSD ATA

Time Break Controller

GPIO

General Purpose I/O

SCK

MOSI

VDDPAD

VDDPLL

VDDCORE

SYNC MSYNC

TIME B

GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1

GNDPAD

GNDCORE

GNDPLL

MDATA

MFLAG

GPIO0

GPIO6:PLL2

GPIO7:BOOT

DRDY

MISO

SS:EECS

RESET

CLK MCLK

PLL, Clock Generation

Low-power Single-channel Decimation Filter

Features

 Single-channel Digital Decimation Filter

 Multiple On-chip FIR and IIR Coefficient Sets  Programmable Coefficients for Custom Filters  Synchronous Operation

 Integrated PLL for Clock Generation

 1.024 MHz, 2.048 MHz, or 4.096 MHz Input  Standard Clock or Manchester Input

 Selectable Output Word Rate

 4000, 2000, 1000, 500, 333, 250 SPS  200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS

 Digital Gain and Offset Corrections  Test DAC Bit-stream Generator

 Digital Sine Wave Output

 Time Break Controller, General-purpose I/O  Microcontroller or EEPROM Configuration  Small-footprint, 28-pin SSOP Package  Low Power Consumption

 16 mW at 500 SPS OWR

 Flexible Power Supplies

 I/O Interface and PLL: 3.3 V or 5.0 V  Digital Logic Core: 2.5 V, 3.3 V or 5.0 V

Description

The CS5378 is a multi-function digital filter utilizing a lowpower signal processing architecture to achieve efficient filtering for a delta-sigma-type modulator. By combining the CS537 8 with a CS33 01A/02A di fferential a mplifier and a CS5373A modulator + test DAC, a synchronous high-resolution, self- testing, sin gle-channel m easurement system can be designed quickly and easily.

Digital filter coefficients for the CS5378 FIR and IIR filters are included on-chip for a simple setup, or they can be programmed for custom ap plications. Selectable digital filter decimation ratios produce output wor d rates from 4000 SPS to 1 SPS, resulting in measurement bandwidths ra nging fro m 16 00 Hz down to 400 mHz whe n using the on-chip coefficient sets.

The CS5378 includes integrated peripherals to simplify system d esign: a low- jitter PL L for standard clo ck or Manchester inpu ts, offset and gain co rrections, a test DAC bit stream generator, a tim e break controller, and eight general-purpose I/O pins.

ORDERING INFORMATION

See page 86.

http://www.cirrus.com

2&7 ‘10

DS639F3

TABLE OF CONTENTS

1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.1. Digital Filter Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.2. Integrated Peripheral Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.3. System Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.4. Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 12

Specified Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3. System Design with CS5378. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.2. Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.3. PLL and Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.4. Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.5. System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.6. Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.7. Data Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.8. Integrated peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.2. Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.3. Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5. Reset Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.2. Reset Self-Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.3. Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

6. PLL and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.2. PLL Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.3. Synchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.4. Master Clock Jitter and Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

7. Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.2. MSYNC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.3. Digital Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.4. Modulator Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.5. Test Bit Stream Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

8. Configuration By EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8.2. EEPROM Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8.3. EEPROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8.4. EEPROM Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8.5. Example EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9. Configuration By Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . 30

CS5378

DS639F3 2

9.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

9.2. Microcontroller Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

9.3. Microcontroller Serial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

9.4. Microcontroller Configuration Commands . . . . . . . . . . . . . . . . . . . . . . .33

9.5. Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . .35

10. Modulator Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.2. Modulator Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.3. Modulator Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.4. Modulator Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

10.5. Modulator Flag Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

11. Digital Filter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11.1. Filter Coefficient Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11.2. Filter Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12. SINC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1. SINC1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

12.2. SINC2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

12.3. SINC3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

12.4. SINC Filter Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

13. FIR Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

13.1. FIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

13.2. FIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

13.3. On-Chip FIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

13.4. Programmable FIR Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

13.5. FIR Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

14. IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

14.1. IIR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

14.2. IIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

14.3. IIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

14.4. IIR3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

14.5. On-Chip IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

14.6. Programmable IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

14.7. IIR Filter Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

15. Gain and Offset Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15.1. Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

15.2. Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

15.3. Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

16. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

16.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

16.2. Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

16.3. Serial Data Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

17. Test Bit Stream Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

17.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

17.2. TBS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

17.3. TBS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

17.4. TBS Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

17.5. TBS Sine Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

17.6. TBS Loopback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

CS5378

DS639F3 3

17.7. TBS Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

18. Time Break Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

18.1. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

18.2. Time Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

18.3. Time Break Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

19. General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

19.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

19.2. GPIO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

19.3. GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

19.4. GPIO Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

19.5. GPIO Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

20. Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

20.1. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

20.2. Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

21. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

22. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

24. Environmental, Manufacturing, & Handling Information. . . . . . . 86

25. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

CS5378

LIST OF FIGURES

Figure 1. CS5378 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Digital Filtering Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. FIR and IIR Coefficient Set Selection Word . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. MOSI Write Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. MISO Read Timing in SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. Serial Data Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing. . . . . . . . . . . . . . . . . . . . . 16

Figure 8. TBS Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. Single-Channel System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Reset Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Clock Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Synchronization Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14. EEPROM Configuration Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15. EEPROM Serial Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 16. 8 Kbyte EEPROM Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 17. Serial Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 18. Microcontroller Serial Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 19. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 20. Modulator Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 21. Digital Filter Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 22. FIR and IIR Coefficient Set Selection Word . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 23. SINC Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 24. SINC Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 25. FIR Filter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 26. FIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 27. FIR1 Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 28. FIR2 Linear Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DS639F3 4

Figure 29. FIR2 Minimum Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 30. IIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 31. IIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 32. Gain and Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 33. Serial Data Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 34. 32-bit Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 35. SD Port Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 36. Test Bit Stream Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 37. Time Break Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 38. GPIO Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 39. SPI Control Register SPICTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 40. SPI Command Register SPICMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 41. SPI Data Register SPIDAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 42. SPI Data Register SPIDAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 43. Hardware Configuration Register CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 44. GPIO Configuration Register GPCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 45. Filter Configuration Register FILTCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 46. Gain Correction Register GAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 47. Offset Correction Register OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 48. Time Break Counter Register TIMEBRK . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 49. Test Bit Stream Configuration Register TBSCFG. . . . . . . . . . . . . . . . . . . . . 78

Figure 50. Test Bit Stream Gain Register TBSGAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 51. User Defined System Register SYSTEM1 . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 52. Hardware Version ID Register VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 53. Self Test Result Register SELFTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 54. CS5378 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

CS5378

LIST OF TABLES

Table 1. Microcontroller and EEPROM Configuration Commands . . . . . . . . . . . . . . . . . 9

Table 2. TBS Configurations Using On-Chip Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. SPI and Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. PLL and BOOT Mode Reset Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. PLL Mode Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Maximum EEPROM Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7. EEPROM Boot Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8. Example EEPROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Microcontroller Boot Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 11. SINC Filter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 12. SINC1 and SINC2 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 13. SINC3 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 14. FIR Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 15. SINC + FIR Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 16. Minimum Phase Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 16. IIR Filter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 17. IIR Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 18. TBS Configurations Using On-chip Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

DS639F3 5

CS5378

Serial Interface

Decimation and Filtering Engine

Modulator D ata Interface

Test Bit Stream

Controller

Reset, Synchronization

TBSDATA

Time Break Controller

GPIO

General Purpose I/O

SCK

MOSI

VDDPAD

VDDPLL

VDDCORE

SYNC MSYNC

TIMEB

GPIO5:PLL1 GPIO4:PLL0 GPIO3 GPIO2 GPIO1

GNDPAD

GNDCORE

GNDPLL

MDATA

MFLAG

GPIO0

GPIO6:PLL2

GPIO7:BOOT

DRDY

MISO

SS:EECS

RESET

CLK MCLK

PLL, Clock Generation

Figure 1. CS5378 Block Diagram

1. GENERAL DESCRIPTION

The CS5378 is a single channel digital filter with integrated system peripherals. Figure 1 illustrates a simplified block diagram of the CS5378.

1.1 Digital Filter Features

• Single channel decimation filter for CS5373A ΔΣ modulator.

• Synchronous operation for simultaneous sampling in multi-sensor systems.

- Internal synchronization of digital filter

• Output word rates, including low bandwidth rates.

- Standard output rates: 4000, 2000, 1000,

- Low bandwidth rates: 200, 125, 100, 50,

phase to an external SYNC signal.

500, 333, 250 SPS.

40, 25, 20, 10, 5, 1 SPS.

• Flexible digital filter configuration. (See Figure

- Cascaded SINC, FIR, and IIR filters with selectable output stage.

- Linear and minimum phase FIR low-pass filter coefficients included.

- 3 Hz Butterworth IIR high-pass filter coefficients included.

- FIR and IIR coefficients programmable to create a custom filter response.

• Digital gain correction to normalize sensor gain.

• Digital offset correction and calibration.

- Offset correction to remove measurement

DS639F3 6

CS5378

Figure 2. Digital Filtering Stages

Sinc Filter

2 - 64000

FIR1

FIR2

IIR1 IIR2

Order

2nd Order

Output to High Speed Serial Interface

DC Offset

Corrections

Output Word Rate from 4000 SPS ~ 1 SPS

Gain &

Modulator

512 kHz

Input

DC offset.

- Calibration engine for automatic calculation of offset correction factor.

• Time break controller to record system timing information.

- Dedicated TB status bit in the output data

stream.

1.2 Integrated Peripheral Features

• Low jitter PLL to generate local clocks.

- 1.024 MHz, 2.048 MHz, 4.096 MHz standard clock or Manchester encoded input.

- Programmable output delay to match system group delay.

• 8 General Purpose I/O (GPIO) pins for local hardware control.

• Synchronous operation for simultaneous sampling in multi-sensor systems.

- MCLK / MSYNC output signals to syn-

chronize external components.

• High speed serial data output.

- Asynchronous operation to 4 MHz for di-

rect connection to system telemetry.

- Internal 8-deep data FIFO for flexible out-

put timing.

- Selectable 24-bit data only or 32-bit sta-

tus+data output.

• Digital test bit stream signal generator suitable for CS5373A ΔΣ test DAC.

- Sine wave output mode for testing total har-

monic distortion.

DS639F3 7

1.3 System Level Features

• Flexible configuration options.

- Configuration 'on-the-fly' via microcontroller or system telemetry.

- Fixed configuration via stand-alone boot EEPROM.

• Low power consumption.

- 16 mW at 500 SPS OWR.

- 100 μW standby mode.

• Flexible power supply configurations.

- Separate digital logic core, telemetry I/O, and PLL power supplies.

- Telemetry I/O and PLL interfaces operate

CS5378

from 3.3 V or 5 V.

- Digital logic core operates from 2.5 V,

3.3 V or 5 V.

• Small 28-pin SSOP package.

- Total footprint 8 mm x 10 mm plus three bypass capacitors.

1.4 Configuration Interface

• Configuration from microcontroller or standalone boot EEPROM.

- Microcontroller boot permits reconfigura-

tion during operation.

- EEPROM boot sets a fixed operational configuration.

• Configuration commands written through the serial interface. (See Table 1)

- Standardized microcontroller interface us-

ing SPI™ registers. (See Table 3)

- Commands write digital filter registers and

FIR / IIR filter coefficients.

- Digital filter registers set hardware config-

uration options.

DS639F3 8

Microcontroller Boot Configuration Commands

EEPROM Boot Configuration Commands

[DATA] indicates data word returned from digital filter. (DATA) indicates multiple words of this type are to be written.

Name CMD

24-bit

DAT1

24-bit

DAT2 24-bit

Description

NOP 000000 - - No Operation

WRITE DF REGISTER 000001 REG DATA Write Digital Filter Register

READ DF REGISTER 000002 REG

[DATA]

Read Digital Filter Register

WRITE FIR COEFFICIENTS 000003 NUM FIR1

(FIR COEF)

NUM FIR2

(FIR COEF)

Write Custom FIR Coefficients

WRITE IIR COEFFICIENTS 000004 a11

b11 a22 b21

b10 a21 b20 b22

Write Custom IIR Coefficients

WRITE ROM COEFFICIENTS 000005 COEF SEL - Use On-Chip Coefficients

NOP 000006 - - No Operation

NOP 000007 - - No Operation

FILTER START 000008 - - Start Digital Filter Operation

FILTER STOP 000009 - - Stop Digital Filter Operation

Name CMD

8-bit

DATA

24-bit

Description

NOP 00 - No Operation

WRITE DF REGISTER 01 REG

DATA

Write Digital Filter Register

WRITE FIR COEFFICIENTS 02 NUM FIR1

NUM FIR2

(FIR COEF)

Write Custom FIR Coefficients

WRITE IIR COEFFICIENTS 03 a11

b10 b11 a21 a22 b20 b21 b22

Write Custom IIR Coefficients

WRITE ROM COEFFICIENTS 04 COEF SEL Use On-Chip Coefficients

NOP 05 - No Operation

NOP 06 - No Operation

FILTER START 07 - Start Digital Filter Operation

Table 1. Microcontroller and EEPROM Configuration Commands

CS5378

DS639F3 9

CS5378

Bits 23:20 19:16 15:12 11:8 7:4 3:0

Selection 0000 0000 IIR2 IIR1 FIR2 FIR1

Figure 3. FIR and IIR Coefficient Set Selection Word

Bits 15:12 IIR2 Coefficients

0000 3 Hz @ 2000 SPS

0001 3 Hz @ 1000 SPS

0010 3 Hz @ 500 SPS

0011 3 Hz @ 333 SPS

0100 3 Hz @ 250 SPS

Bits 11:8 IIR1 Coefficients

0000 3 Hz @ 2000 SPS

0001 3 Hz @ 1000 SPS

0010 3 Hz @ 500 SPS

0011 3 Hz @ 333 SPS

0100 3 Hz @ 250 SPS

Bits 7:4 FIR2 Coefficients

0000 Linear Phase

0001 Minimum Phase

Bits 3:0 FIR1 Coefficients

0000 Linear Phase

0001 Minimum Phase

Test Bit Stream Characteristic Equation:

(Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz

Signal

Frequency

(TBSDATA)

Output

Rate

(TBSCLK)

Output Rate

Selection

(RATE)

Interpolation

Selection

(INTP)

10.00 Hz 256 kHz 0x4 0x18

10.00 Hz 512 kHz 0x5 0x31

25.00 Hz 256 kHz 0x4 0x09

25.00 Hz 512 kHz 0x5 0x13

31.25 Hz 256 kHz 0x4 0x07

31.25 Hz 512 kHz 0x5 0x0F

50.00 Hz 256 kHz 0x4 0x04

50.00 Hz 512 kHz 0x5 0x09

125.00 Hz 256 kHz 0x4 0x01

125.00 Hz 512 kHz 0x5 0x03

Table 2. TBS Configurations Using On-Chip Data

DS639F3 10

CS5378

SPI Registers

Digital Filter Registers

Name Addr. Type # Bits Description

SPICTRL 00 - 02 R/W 8, 8, 8 SPI Control

SPICMD 03 - 05 R/W 8, 8, 8 SPI Command

SPIDAT1 06 - 08 R/W 8, 8, 8 SPI Data 1

SPIDAT2 09 - 0B R/W 8, 8, 8 SPI Data 2

Name Addr. Type # Bits Description

CONFIG 00 R/W 24 Hardware Configuration

RESERVED 01-0D R/W 24 Reserved

GPCFG 0E R/W 24 GPIO[7:0] Direction, Pull-up Enable, and Data

RESERVED 0F-1F R/W 24 Reserved

FILTCFG 20 R/W 24 Digital Filter Configuration

GAIN 21 R/W 24 Gain Correction

RESERVED 22-24 R/W 24 Reserved

OFFSET 25 R/W 24 Offset Correction

RESERVED 26-28 R/W 24 Reserved

TIMEBRK 29 R/W 24 Time Break Delay

TBSCFG 2A R/W 24 Test Bit Stream Configuration

TBSGAIN 2B R/W 24 Test Bit Stream Gain

SYSTEM1 2C R/W 24 User Defined System Register 1

SYSTEM2 2D R/W 24 User Defined System Register 2

VERSION 2E R/W 24 Hardware Version ID

SELFTEST 2F R/W 24 Self-Test Result Code

Table 3. SPI and Digital Filter Registers

Table 4. PLL and BOOT Mode Reset Configurations

PLL[2:0] Mode Selection on Reset

111 32.768 MHz clock input (PLL bypass).

110 1.024 MHz clock input.

101 2.048 MHz clock input.

100 4.096 MHz clock input.

011 32.768 MHz clock input (PLL bypass).

010 1.024 MHz Manchester input.

001 2.048 MHz Manchester input.

000 4.096 MHz Manchester input.

Configuration Note:

States of the PLL[2:0] and BOOT pins are latched immediately after reset to select modes.

These pins have a weak (~100 kΩ) pull-up resistor enabled by default. An external 10 kΩ pull-down is required to set a low condition.

BOOT Mode Selection on Reset

1 EEPROM boot

0 Microcontroller boot

DS639F3 11

CS5378

2. CHARACTERISTICS AND SPECIFICATIONS

• Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions.

• Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.

• GND, GND1, GND2 = 0 V, all voltages with respect to 0 V.

SPECIFIED OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit

Logic Core Power Supply VDDCORE 2.375 2.5 5.25 V

PLL Power Supply VDDPLL 3.135 3.3 5.25 V

I/O Power Supply VDDPAD 3.135 3.3 5.25 V

Ambient Operating Temperature Industrial (-IQ) T

-40 - 85 °C

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Power Supplies Logic Core

Input Current, Any Pin Except Supplies (Note 1) I

Input Current, Power Supplies (Note 1) I

Output Current (Note 1) I

Power Dissipation P

Digital Input Voltages V

Ambient Operating Temperature (Power Applied) T

Storage Temperature Range T

1. Transient currents up to 100 mA will not cause SCR latch-up.

PLL

I/O

VDDCORE

VDDPLL VDDPAD

OUT

IND

STG

-0.3

-±10mA

-±50mA

-±25mA

-500mW

-0.3 VDD+0.3 V

-40 85 °C

-65 150 °C

6.0

V V V

DS639F3 12

THERMAL CHARACTERISTICS

2.6 V

0.7 V

fallin

risein

4.6 V

0.4 V

riseout

fallout

0.90 * VDD

0.10 * VDD

0.90 * VDD

0.10 * VDD

Parameter Symbol Min Typ Max Unit

Allowable Junction Temperature T

Junction to Ambient Thermal Impedance (4-Layer PCB) Θ

Ambient Operating Temperature (Power Applied) T

DIGITAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

High-Level Input Drive Voltage V

Low-Level Input Drive Voltage V

High-Level Output Drive Voltage I

Low-Level Output Drive Voltage I

Rise Times, Digital Inputs t

Fall Times, Digital Inputs t

Rise Times, Digital Outputs t

Fall Times, Digital Outputs t

Input Leakage Current (Note 2) I

3-State Leakage Current I

Digital Input Capacitance C

Digital Output Pin Capacitance C

= -40 µA V

out

= +40 µA V

out

RISE

FALL

RISE

FALL

OUT

--135°C

-50 °C / W

-40 - +85 °C

0.6 * VDD - VDD V

0.0 - 0.8 V

VDD - 0.3 - VDD V

0.0 - 0.3 V

--100ns

-± 1± 10µA

--± 10µA

-9-pF

CS5378

Notes: 2. Maximum leakage for pins with pull-up resistors (RESET, SS:EECS, GPIO, MOSI, SCK) is ±250 μA.

POWER CONSUMPTION

Parameter Symbol Min Typ Max Unit

Operational Power Consumption

1.024 MHz Digital Filter Clock PWR

2.048 MHz Digital Filter Clock PWR

4.096 MHz Digital Filter Clock PWR

8.192 MHz Digital Filter Clock PWR

Standby Power Consumption

32 kHz Digital Filter Clock, Filter Stopped PWR

-12-mW

-14-mW

-16-mW

-24-mW

- 100 - µW

DS639F3 13

SWITCHING CHARACTERISTICS

Figure 4. MOSI Write Timing in SPI Slave Mode

SSI

MOSI

SCLK

MSB MSB - 1

LSB

SCK

SS:EECS

Figure 5. MISO Read Timing in SPI Slave Mode

MISO

SCLK

MSB MSB - 1 LSB

SSI

SS:EECS

SCK

Serial Configuration Interface Timing (External Master)

CS5378

Parameter Symbol Min Typ Max Unit

MOSI Write Timing

SS:EECS

Data Set-up Time Prior to SCK Rising t

Data Hold Time After SCK Rising t

SCK High Time t

SCK Low Time t

SCK Falling Prior to SS:EECS

Enable to Valid Latch Clock t

Disable t

60 - - ns

120 - - ns

60 - - ns

MISO Read Timing

SCK Falling to New Data Bit t

SCK High Time t

SCK Low Time t

SS:EECS

DS639F3 14

Rising to MISO Hi-Z t

- - 60 ns

120 - - ns

--150ns

SWITCHING CHARACTERISTICS

Figure 6. Serial Data Read Timing

MISO

SCK

DRDY

Serial Data Interface Timing

CS5378

Parameter Symbol Min Typ Max Unit

DRDY

Falling Edge to SCK Rising t

SCK Falling to New Data Bit t

SCK High Time t

SCK Low Time t

Final SCK Falling to DRDY

Rising t

60 - - ns

--120ns

120 - - ns

60 - - ns

DS639F3 15

SWITCHING CHARACTERISTICS

MSYNC

MCLK

MDATA

Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing

msd

msh

Data1 Data2

SYNC

MCLK

2.048 MHz 1.024 MHz

msd

= T

MCLK

/ 4 t

msd

= 122 ns t

msd

= 244 ns

msh

= T

MCLK

msh

= 488 ns t

msh

= 976 ns

Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge.

CLK, SYNC, MCLK, MSYNC, and MDATA

CS5378

Master Clock Frequency (Note 3) CLK 32 32.768 33 MHz

Master Clock Duty Cycle DTY 40 - 60 %

Master Clock Rise Time t

Master Clock Fall Time t

Master Clock Jitter JTR - - 300 ps

Synchronization after SYNC rising (Note 4) SYNC -2 - 2 μs

MSYNC Setup Time to MCLK rising t

MCLK rising to Valid MDATA t

MSYNC falling to MCLK rising t

Notes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock when enabled.

4. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals.

DS639F3 16

Parameter Symbol Min Typ Max Unit

- - 20 ns

20 - - ns

- - 75 ns

20 - - ns

RISE

FALL

mss

mdv

msf

SWITCHING CHARACTERISTICS

Figure 8. TBS Output Data Timing

TBSDATA

MCLK

Note: Example timing shown for a 256 kHz output rate and no programmable delays.

Test Bit Stream (TBS)

CS5378

Parameter Symbol Min Typ Max Unit

TBS Data Output Timing

TBS Data Bit Rate - 256 - kbps

TBS Data Rising to MCLK Rising Setup Time t

MCLK Rising to TBS Data Falling Hold Time (Note 5) t

5. TBSDATA can be delayed from 0 to 63 full bit periods. The timing diagram shows no TBSDATA delay.

60 - - ns

DS639F3 17

CS5378

ΔΣ

Modulator

Test DAC

Digital Filter

AMP

Differential

Sensor

M U X

μController

Configuration

EEPROM

System

Telemetry

CS3301A CS3302A

CS5378

CS5373A

Figure 9. Single-Channel System Block Diagram

3. SYSTEM DESIGN WITH CS5378

Figure 9 illustrates a simplified block diagram of the CS5378 in a single channel measurement system.

A differential sensor is connected through the CS3301A/02A differential amplifiers to the CS5373A ΔΣ modulator, where analog to digital conversion occurs. The modulator’s 1-bit output connects to the CS5378 MDATA input, where the oversampled ΔΣ data is decimated and filtered to 24-bit output samples at a programmed output rate. These output samples are buffered into an 8-deep data FIFO and then passed to the system telemetry.

System self tests are performed by connecting the CS5378 test bit stream (TBS) generator to the CS5373A test DAC. Analog tests drive differential signals from the CS5373A test DAC into the multiplexed inputs of the CS3301A/02A amplifiers or directly to the differential sensor. Digital loopback tests internally connect the TBS digital output directly to the CS5378 modulator input.

3.1 Power Supplies

The system shown in Figure 9 typically operates from a ±2.5 V analog power supply and a 3.3 V digital power supply. The CS5378 logic core can be powered from 2.5 V to minimize power consumption, if required.

3.2 Reset Control

System reset is required only for the CS5378 device, and is a standard active low signal that can be generated by a power supply monitor or microcontroller. Other system devices default to a powerdown state when the CS5378 is reset.

3.3 PLL and Clock Generation

A PLL is included on the CS5378 to generate an internal 32.768 MHz master clock from a

1.024 MHz, 2.048 MHz, or 4.096 MHz standard clock or Manchester encoded input. Clock inputs for other system devices are driven by clock outputs from the CS5378.

DS639F3 18

CS5378

3.4 Synchronization

Digital filter phase and analog sample timing of the ΔΣ modulator connected to the CS5378 are synchronized by a rising edge on the SYNC pin. If a synchronization signal is received identically by all CS5378 devices in a measurement network, synchronous sampling across the network is guaranteed.

3.5 System Configuration

Through the serial configuration interface, filter coefficients and digital filter register settings can either be programmed by a microcontroller or automatically loaded from an external EEPROM after reset. System configuration is only required for the CS5378 device, as other devices are configured via the CS5378 General Purpose I/O pins.

Two registers in the digital filter, SYSTEM1 and SYSTEM2 (0x2C, 0x2D), are provided for user defined system information. These are general purpose registers that will hold any 24-bit data values written to them.

3.6 Digital Filter Operation

3.7 Data Collection

Data is collected from the CS5378 through the serial data interface. When data is available, serial transactions are automatically initiated to transfer 24-bit data or 32-bit status+data from the output FIFO to the system telemetry. The output FIFO has eight data locations to permit latency in data collection.

3.8 Integrated peripherals

Test Bit Stream (TBS)

A digital signal generator built into the CS5378 produces a 1-bit ΔΣ sine wave. This digital test bit stream is connected to the CS5373A test DAC to create high quality analog test signals or internally looped back to the CS5378 MDATA input to test the digital filter and data collection circuitry.

Time Break

Timing information is recorded during data collection by strobing the TIMEB pin. A dedicated flag in the sample status bits, TB, is set high to indicate during which measurement the timing event occurred.

After analog to digital conversion occurs in the modulator, the oversampled 1-bit ΔΣ data is read into the CS5378 through the MDATA pin. The digital filter then processes data through the enabled filter stages, decimating it to 24-bit words at a programmed output word rate. The final 24-bit samples are concatenated with 8-bit status words and placed into an output FIFO.

DS639F3 19

General Purpose I/O (GPIO)

Eight general purpose pins are available on the CS5378 for system control. Each pin can be set as input or output, high or low, with an internal pullup enabled or disabled. The CS3301A/02A and CS5373A devices in Figure 9 are configured by simple pin settings controlled through the CS5378 GPIO pins.

4. POWER SUPPLIES

821

12 17

14 15

VDDPAD

GNDPAD

GNDCORE

VDDCORE

Figure 10. Power Supply Block Diagram

GNDPLL

VDDPLL

CS5378

The CS5378 has three sets of power supply inputs. One set supplies power to the I/O pins of the device (VDDPAD), another supplies power to the logic core (VDDCORE) and the third supplies power to the PLL (VDDPLL). The I/O pin power supplies determine the maximum input and output voltages when interfacing to peripherals, the logic core power supply largely determines the power consumption of the CS5378 and the PLL power supply powers the internal PLL circuitry.

4.1 Pin Descriptions

VDDPAD, GNDPAD - Pins 9, 10

Sets the interface voltage to a microcontroller, system telemetry, modulator, and test DAC. VDDPAD can be driven with voltages from 3.3 V to 5V.

VDDPLL, GNDPLL - Pins 15, 16

Sets the operational voltage of the internal CS5378 PLL circuitry. Can be driven with voltages from

3.3 V to 5 V.

DS639F3 20

VDDCORE, GNDCORE - Pins 21, 22

Sets the operational voltage of the CS5378 logic core. VDDCORE can be driven with voltages from

2.5 V to 5 V. A 2.5 V supply will minimize total power consumption.

4.2 Bypass Capacitors

Each power supply pin should be bypassed with parallel 1 μF and 0.01 μF caps, or by a single

0.1 μF cap, placed as close as possible to the CS5378. Bypass capacitors should be ceramic (X7R, C0G), tantalum, or other good quality dielectric type.

4.3 Power Consumption

Power consumption of the CS5378 depends primarily on the power supply voltage of the logic core (VDDCORE) and the programmed digital filter clock rate. Digital filter clock rates are selected based on the required output word rate as explained in “Digital Filter Initialization” on page 38.

5. RESET CONTROL

RESET

Self-Tests

SELFTEST

BOOT

EEPROM

Boot

μController

Boot

Figure 11. Reset Control Block Diagram

BOOT Reset Mode

1 EEPROM boot

0 Microcontroller boot

Self-Test

Type

Pass

Code

Fail

Code

Program ROM 0x00000A 0x00000F

Data ROM 0x0000A0 0x0000F0

Program RAM 0x000A00 0x000F00

Data RAM 0x00A000 0x00F000

Execution Unit 0x0A0000 0x0F0000

CS5378

The CS5378 reset signal is active low. When released, a series of self-tests are performed and the device either actively boots from an external EEPROM or enters an idle state waiting for microcontroller configuration.

5.1 Pin Descriptions

RESET

Reset input, active low.

- Pin 18

GPIO7:BOOT - Pin 28

Boot mode select, latched immediately following reset. Weak (~100 kΩ) internal pull-up defaults high, external 10 kΩ pull-down required to set low.

combined into the SELFTEST register (0x2F), with 0x0AAAAA indicating all passed. Self-tests require 60 ms to complete.

5.3 Boot Configurations

The logic state of the BOOT pin after reset determines if the CS5378 actively reads configuration information from EEPROM or enters an idle state waiting for a microcontroller to write configuration commands.

EEPROM Boot

When the BOOT pin is high after reset, the CS5378 actively reads data from an external serial EEPROM and then begins operation in the specified configuration. Configuration commands and data are encoded in the EEPROM as specified in the ‘Configuration By EEPROM’ section of this data sheet, starting on page 25.

5.2 Reset Self-Tests

After RESET is released but before booting, a series of digital filter self-tests are run. Results are

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Microcontroller Boot

When the BOOT pin is low after reset, the CS5378 enters an idle state waiting for a microcontroller to write configuration commands and initialize filter operation. Configuration commands and data are written as specified in the ‘Configuration By Microcontroller’ section of this data sheet, starting on page 30.

6. PLL AND CLOCK GENERATION

PLL

CLK

DSPCFG Register

MCLK

Internal Clocks

Figure 12. Clock Generation Block Diagram

Clock Divider

Generator

and MCLK

Output

PLL[2:0]

32.768 MHz

PLL[2:0] PLL Mode

111 32.768 MHz clock input (PLL bypass).

110 1.024 MHz clock input.

101 2.048 MHz clock input.

100 4.096 MHz clock input.

011 32.768 MHz clock input (PLL bypass).

010 1.024 MHz Manchester input.

001 2.048 MHz Manchester input.

000 4.096 MHz Manchester input.

Table 5. PLL Mode Selections

CS5378

The CS5378 requires a 32.768 MHz master clock, which can be supplied directly or from an internal phase locked loop. This master clock is used to generate an internal digital filter clock and an external modulator clock.

The internal PLL will lock to standard clock or Manchester encoded input signals. The input type and input frequency are selected by the reset state of the PLL mode select pins.

6.1 Pin Descriptions

CLK - Pin 17

Clock or PLL input, standard clock or Manchester.

GPIO[4:6]:PLL[0:2] - Pins 5, 6, 7

PLL mode select, latched immediately after reset. Weak (~100 kΩ) internal pull-ups default high, external 10 kΩ pull-downs required to set low.

A weak internal pull-up resistor (~100 kΩ) will hold the PLL mode select pins high by default. To force the pin low on reset, an external 10 kΩ pulldown resistor should be connected. Once the pin state is latched following reset, the GPIO[4:6] pins function without affecting PLL operation.

6.3 Synchronous Clocking

To guarantee synchronous measurements throughout a sensor network, a system clock should be distributed to arrive at all nodes in phase. The distributed system clock can either be the full

32.768 MHz master clock, or the CS5378 PLL can create a synchronous 32.768 MHz clock from a slower clock. To ensure the generated clock remains synchronous with the network, the CS5378 PLL uses a phase/frequency detector architecture.

6.2 PLL Mode Select

The CS5378 PLL operational mode and frequency are selected immediately after reset based on the state of the PLL[0:2] pins. On the rising edge of the reset signal, the digital high or low state of the PLL[0:2] pins is latched and used to program the clock input type and frequency.

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CS5378

6.4 Master Clock Jitter and Skew

Care must be taken to minimize jitter and skew on the distributed system clock as both parameters affect measurement performance.

Jitter on the input clock causes jitter in the generated modulator clock, resulting in sample timing errors and increased noise.

Skew between input clocks from node to node creates a sample timing offset, resulting in systematic measurement errors in a reconstructed signal.

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7. SYNCHRONIZATION

Figure 13. Synchronization Block Diagram

SYNC

MSYNC

Digital

Filter

Generator

MSYNC

0 1

MSEN

TSYNC

Test Bit

Stream

Output

CS5378

The CS5378 has a dedicated SYNC input that aligns the internal digital filter phase and generates an external signal for synchronizing modulator analog sampling. By providing simultaneous rising edges to the SYNC pins of multiple CS5378 devices, synchronous sampling across a network can be guaranteed.

7.1 Pin Description

SYNC - Pin 19

Synchronization input, rising edge triggered.

7.2 MSYNC Generation

The SYNC signal rising edge is used to generate a retimed synchronization signal, MSYNC. The MSYNC signal reinitializes internal digital filter phase and is driven onto the MSYNC output pin to phase align modulator analog sampling.

The MSEN bit in the digital filter CONFIG register (0x00) enables MSYNC generation. See “Modulator Interface” on page 36 for more information about MSYNC.

7.3 Digital Filter Synchronization

The internal MSYNC signal resets the digital filter state machine to establish a known digital filter

phase. Filter convolutions restart, and the next output word is available one full sample period later.

Repetitive synchronization is supported when SYNC events occur at exactly the selected output rate. In this case, re-synchronization will occur at the start of a convolution cycle when the digital filter state machine is already reset.

7.4 Modulator Synchronization

The external MSYNC signal phase aligns modulator analog sampling when connected to the CS5373A MSYNC input. This ensures synchronous analog sampling relative to MCLK.

Repetitive synchronization of the modulators is supported when SYNC events occur at exactly the selected output rate. In this case, re-synchronization always occurs at the start of analog sampling.

7.5 Test Bit Stream Synchronization

When the test bit stream generator is enabled, an MSYNC signal can reset the internal data pointer. This restarts the test bit stream from the first data point to establish a known output signal phase.

The TSYNC bit in the digital filter TBSCFG register (0x2A) enables synchronization of the test bit stream by MSYNC. When TSYNC is disabled, the test bit stream phase is not affected by MSYNC.

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8. CONFIGURATION BY EEPROM

SS:EECS

SCK

MISO

MOSI

CS5378 AT25640

SCK

GND

WP VCC HOLD

387

Figure 14. EEPROM Configuration Block Diagram

CS5378

After reset, the CS5378 reads the state of the GPIO7:BOOT pin to determine a source for configuration commands. If BOOT is high, the CS5378 initiates serial transactions to read configuration information from an external EEPROM.

8.1 Pin Descriptions

Pins required for EEPROM boot are listed here, other serial pins are inactive.

SCK - Pin 24

Serial clock output, nominally 1.024 MHz.

MISO - Pin 25

Serial data input pin. Valid on rising edge of SCK, transition on falling edge.

MOSI - Pin 26

Serial data output pin. Valid on rising edge of SCK, transition on falling edge.

SS:EECS - Pin 27

EEPROM chip select output, active low.

8.2 EEPROM Hardware Interface

When booting from EEPROM the CS5378 actively performs serial transactions, as shown in Figure 15,

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to read configuration commands and data. 8-bit SPI opcodes and 16-bit addresses are combined to read back 8-bit configuration commands and 24-bit configuration data.

System design should include a connection to the configuration EEPROM for in-circuit reprogramming. The CS5378 serial pins tri-state when inactive to support external connections to the serial bus.

8.3 EEPROM Organization

The boot EEPROM holds the 8-bit commands and 24-bit data required to initialize the CS5378 into an operational state. Configuration information starts at memory location 0x10, with addresses 0x00 to 0x0F free for use as manufacturing header information.

The first serial transaction reads a 1-byte command from memory location 0x10 and then, depending on the command type, reads multiple 3-byte data words to complete the command. Command and data reads continue until the ‘Filter Start’ command is recognized.

SCK

MOSI

SS:EECS

MSB LSB

MISO

612345

MSB LSB612345

18276543

Cycle

MOSI

MISO

0x03 ADDR

DATA1 DATA3DATA2

SS:EECS

READ

1 BYTE / 3 BYTE

ADDR

CMD

ADDR

DATA

2 BYTE

Figure 15. EEPROM Serial Read Transactions

Serial Read from EEPROM

Instruction Opcode Address Definition

Read 0x03 ADDR[15:0] Read data beginning at the address given in ADDR.

CS5378

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CS5378

Figure 16. 8 Kbyte EEPROM Memory Organization

0000h

1FFFh

EEPROM Manufacturing Information

EEPROM Command and Data Values

Mfg Header

8-bit Command

0010h

N x 24-bit Data

8-bit Command N x 24-bit Data

. . .

Table 6. Maximum EEPROM Configuration

Memory Requirement Bytes

Digital Filter Registers (12) 84 FIR Coefficients (255+255) 1537 IIR Coefficients (3+5) 25 ‘Filter Start’ Command 1

Total Bytes 1647

Write DF Register - 0x01

This EEPROM command writes a data value to the specified digital filter register. Digital filter registers control hardware peripherals and filtering functions. See “Digital Filter Registers” on page 71 for the bit definitions of the digital filter registers.

Sample Command:

Write digital filter register 0x00 with data value 0x060431. Then write 0x20 with data 0x000240.

01 00 00 00 06 04 31 01 00 00 20 00 02 40

Write FIR Coefficients - 0x02

The maximum number of bytes that will be written for a single configuration is less than 2 KByte (16 Kbit), including command overhead:

Supported serial configuration EEPROMs are SPI mode 0 (0,0) compatible, 16-bit addresses, 8bit data, larger than 2 KByte (16 KBit). ATMEL AT25640, AT25128, or similar serial EEPROMs are recommended.

8.4 EEPROM Configuration Commands

A summary of available EEPROM commands is shown in Table 7.

This EEPROM command writes custom coefficients for the FIR1 and FIR2 filters. The first two data words set the number of FIR1 and FIR2 coefficients to be written. The remaining data words are the concatenated FIR1 and FIR2 coefficients.

A maximum of 255 coefficients can be written for each FIR filter, though the available digital filter computation cycles will limit their practical size. See “FIR Filter” on page 44 for more information about FIR filter coefficients.

Sample Command:

Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D.

02 00 00 02 00 00 02 00 02 2E 00 07 71 FF FF B9 FF FE 8D

Write IIR Coefficients - 0x03

This EEPROM command writes custom coefficients for the two stage IIR filter. The IIR architecture and number of coefficients is fixed, so eight data words containing coefficient values always immediately follow the command byte. The IIR coefficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. See “IIR Filter” on page 52 for more information about IIR filter coefficients.

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