Digital Gain and Offset Corrections
Test DAC Bit-stream Generator
Digital Sine Wave Output
Time Break Controller, General-purpose I/O
Microcontroller or EEPROM Configuration
Small-footprint, 28-pin SSOP Package
Low Power Consumption
16 mW at 500 SPS OWR
Flexible Power Supplies
I/O Interface and PLL: 3.3 V or 5.0 V
Digital Logic Core: 2.5 V, 3.3 V or 5.0 V
I
Description
The CS5378 is a multi-function digital filter utilizing a lowpower signal processing architecture to achieve efficient
filtering for a delta-sigma-type modulator. By combining
the CS537 8 with a CS33 01A/02A di fferential a mplifier
and a CS5373A modulator + test DAC, a synchronous
high-resolution, self- testing, sin gle-channel m easurement system can be designed quickly and easily.
Digital filter coefficients for the CS5378 FIR and IIR filters
are included on-chip for a simple setup, or they can be
programmed for custom ap plications. Selectable digital
filter decimation ratios produce output wor d rates from
4000 SPS to 1 SPS, resulting in measurement bandwidths ra nging fro m 16 00 Hz down to 400 mHz whe n
using the on-chip coefficient sets.
The CS5378 includes integrated peripherals to simplify
system d esign: a low- jitter PL L for standard clo ck or
Manchester inpu ts, offset and gain co rrections, a test
DAC bit stream generator, a tim e break controller, and
eight general-purpose I/O pins.
Note: Example timing shown for a 256 kHz output rate and no programmable delays.
Test Bit Stream (TBS)
CS5378
ParameterSymbol Min TypMaxUnit
TBS Data Output Timing
TBS Data Bit Rate-256-kbps
TBS Data Rising to MCLK Rising Setup Timet
MCLK Rising to TBS Data Falling Hold Time(Note 5)t
5. TBSDATA can be delayed from 0 to 63 full bit periods. The timing diagram shows no TBSDATA delay.
1
2
60--ns
60--ns
DS639F317
CS5378
ΔΣ
Modulator
Test
DAC
Digital Filter
AMP
Differential
Sensor
M
U
X
μController
or
Configuration
EEPROM
System
Telemetry
CS3301A
CS3302A
CS5378
CS5373A
Figure 9. Single-Channel System Block Diagram
3. SYSTEM DESIGN WITH CS5378
Figure 9 illustrates a simplified block diagram of
the CS5378 in a single channel measurement system.
A differential sensor is connected through the
CS3301A/02A differential amplifiers to the
CS5373A ΔΣ modulator, where analog to digital
conversion occurs. The modulator’s 1-bit output
connects to the CS5378 MDATA input, where the
oversampled ΔΣ data is decimated and filtered to
24-bit output samples at a programmed output rate.
These output samples are buffered into an 8-deep
data FIFO and then passed to the system telemetry.
System self tests are performed by connecting the
CS5378 test bit stream (TBS) generator to the
CS5373A test DAC. Analog tests drive differential
signals from the CS5373A test DAC into the multiplexed inputs of the CS3301A/02A amplifiers or
directly to the differential sensor. Digital loopback
tests internally connect the TBS digital output directly to the CS5378 modulator input.
3.1Power Supplies
The system shown in Figure 9 typically operates
from a ±2.5 V analog power supply and a 3.3 V
digital power supply. The CS5378 logic core can
be powered from 2.5 V to minimize power consumption, if required.
3.2Reset Control
System reset is required only for the CS5378 device, and is a standard active low signal that can be
generated by a power supply monitor or microcontroller. Other system devices default to a powerdown state when the CS5378 is reset.
3.3PLL and Clock Generation
A PLL is included on the CS5378 to generate an internal 32.768 MHz master clock from a
1.024 MHz, 2.048 MHz, or 4.096 MHz standard
clock or Manchester encoded input. Clock inputs
for other system devices are driven by clock outputs from the CS5378.
DS639F318
CS5378
3.4Synchronization
Digital filter phase and analog sample timing of the
ΔΣ modulator connected to the CS5378 are synchronized by a rising edge on the SYNC pin. If a
synchronization signal is received identically by all
CS5378 devices in a measurement network, synchronous sampling across the network is guaranteed.
3.5System Configuration
Through the serial configuration interface, filter
coefficients and digital filter register settings can
either be programmed by a microcontroller or automatically loaded from an external EEPROM after
reset. System configuration is only required for the
CS5378 device, as other devices are configured via
the CS5378 General Purpose I/O pins.
Two registers in the digital filter, SYSTEM1 and
SYSTEM2 (0x2C, 0x2D), are provided for user defined system information. These are general purpose registers that will hold any 24-bit data values
written to them.
3.6Digital Filter Operation
3.7Data Collection
Data is collected from the CS5378 through the serial data interface. When data is available, serial
transactions are automatically initiated to transfer
24-bit data or 32-bit status+data from the output
FIFO to the system telemetry. The output FIFO has
eight data locations to permit latency in data collection.
3.8Integrated peripherals
Test Bit Stream (TBS)
A digital signal generator built into the CS5378
produces a 1-bit ΔΣ sine wave. This digital test bit
stream is connected to the CS5373A test DAC to
create high quality analog test signals or internally
looped back to the CS5378 MDATA input to test
the digital filter and data collection circuitry.
Time Break
Timing information is recorded during data collection by strobing the TIMEB pin. A dedicated flag
in the sample status bits, TB, is set high to indicate
during which measurement the timing event occurred.
After analog to digital conversion occurs in the
modulator, the oversampled 1-bit ΔΣ data is read
into the CS5378 through the MDATA pin. The digital filter then processes data through the enabled
filter stages, decimating it to 24-bit words at a programmed output word rate. The final 24-bit samples are concatenated with 8-bit status words and
placed into an output FIFO.
DS639F319
General Purpose I/O (GPIO)
Eight general purpose pins are available on the
CS5378 for system control. Each pin can be set as
input or output, high or low, with an internal pullup enabled or disabled. The CS3301A/02A and
CS5373A devices in Figure 9 are configured by
simple pin settings controlled through the CS5378
GPIO pins.
4. POWER SUPPLIES
1
2
3
4
5
6
7
821
22
23
24
25
26
27
28
9
10
11
1217
18
19
20
13
1415
16
VDDPAD
GNDPAD
GNDCORE
VDDCORE
Figure 10. Power Supply Block Diagram
GNDPLL
VDDPLL
CS5378
The CS5378 has three sets of power supply inputs.
One set supplies power to the I/O pins of the device
(VDDPAD), another supplies power to the logic
core (VDDCORE) and the third supplies power to
the PLL (VDDPLL). The I/O pin power supplies
determine the maximum input and output voltages
when interfacing to peripherals, the logic core power supply largely determines the power consumption of the CS5378 and the PLL power supply
powers the internal PLL circuitry.
4.1Pin Descriptions
VDDPAD, GNDPAD - Pins 9, 10
Sets the interface voltage to a microcontroller, system telemetry, modulator, and test DAC. VDDPAD can be driven with voltages from 3.3 V to
5V.
VDDPLL, GNDPLL - Pins 15, 16
Sets the operational voltage of the internal CS5378
PLL circuitry. Can be driven with voltages from
3.3 V to 5 V.
DS639F320
VDDCORE, GNDCORE - Pins 21, 22
Sets the operational voltage of the CS5378 logic
core. VDDCORE can be driven with voltages from
2.5 V to 5 V. A 2.5 V supply will minimize total
power consumption.
4.2Bypass Capacitors
Each power supply pin should be bypassed with
parallel 1 μF and 0.01 μF caps, or by a single
0.1 μF cap, placed as close as possible to the
CS5378. Bypass capacitors should be ceramic
(X7R, C0G), tantalum, or other good quality dielectric type.
4.3Power Consumption
Power consumption of the CS5378 depends primarily on the power supply voltage of the logic
core (VDDCORE) and the programmed digital filter clock rate. Digital filter clock rates are selected
based on the required output word rate as explained
in “Digital Filter Initialization” on page 38.
5. RESET CONTROL
RESET
Self-Tests
SELFTEST
Register
BOOT
Pin
EEPROM
Boot
μController
Boot
1
0
Figure 11. Reset Control Block Diagram
BOOTReset Mode
1EEPROM boot
0Microcontroller boot
Self-Test
Type
Pass
Code
Fail
Code
Program ROM0x00000A0x00000F
Data ROM0x0000A00x0000F0
Program RAM0x000A000x000F00
Data RAM0x00A0000x00F000
Execution Unit0x0A00000x0F0000
CS5378
The CS5378 reset signal is active low. When released, a series of self-tests are performed and the
device either actively boots from an external EEPROM or enters an idle state waiting for microcontroller configuration.
5.1Pin Descriptions
RESET
Reset input, active low.
- Pin 18
GPIO7:BOOT - Pin 28
Boot mode select, latched immediately following
reset. Weak (~100 kΩ) internal pull-up defaults
high, external 10 kΩ pull-down required to set low.
combined into the SELFTEST register (0x2F),
with 0x0AAAAA indicating all passed. Self-tests
require 60 ms to complete.
5.3Boot Configurations
The logic state of the BOOT pin after reset determines if the CS5378 actively reads configuration
information from EEPROM or enters an idle state
waiting for a microcontroller to write configuration
commands.
EEPROM Boot
When the BOOT pin is high after reset, the CS5378
actively reads data from an external serial EEPROM and then begins operation in the specified
configuration. Configuration commands and data
are encoded in the EEPROM as specified in the
‘Configuration By EEPROM’ section of this data
sheet, starting on page 25.
5.2Reset Self-Tests
After RESET is released but before booting, a series of digital filter self-tests are run. Results are
DS639F321
Microcontroller Boot
When the BOOT pin is low after reset, the CS5378
enters an idle state waiting for a microcontroller to
write configuration commands and initialize filter
operation. Configuration commands and data are
written as specified in the ‘Configuration By Microcontroller’ section of this data sheet, starting on
page 30.
6. PLL AND CLOCK GENERATION
PLL
CLK
DSPCFG Register
MCLK
Internal
Clocks
Figure 12. Clock Generation Block Diagram
Clock Divider
Generator
and MCLK
Output
PLL[2:0]
32.768
MHz
PLL[2:0]PLL Mode
11132.768 MHz clock input (PLL bypass).
1101.024 MHz clock input.
1012.048 MHz clock input.
1004.096 MHz clock input.
01132.768 MHz clock input (PLL bypass).
0101.024 MHz Manchester input.
0012.048 MHz Manchester input.
0004.096 MHz Manchester input.
Table 5. PLL Mode Selections
CS5378
The CS5378 requires a 32.768 MHz master clock,
which can be supplied directly or from an internal
phase locked loop. This master clock is used to
generate an internal digital filter clock and an external modulator clock.
The internal PLL will lock to standard clock or
Manchester encoded input signals. The input type
and input frequency are selected by the reset state
of the PLL mode select pins.
6.1Pin Descriptions
CLK - Pin 17
Clock or PLL input, standard clock or Manchester.
GPIO[4:6]:PLL[0:2] - Pins 5, 6, 7
PLL mode select, latched immediately after reset.
Weak (~100 kΩ) internal pull-ups default high, external 10 kΩ pull-downs required to set low.
A weak internal pull-up resistor (~100 kΩ) will
hold the PLL mode select pins high by default. To
force the pin low on reset, an external 10 kΩ pulldown resistor should be connected. Once the pin
state is latched following reset, the GPIO[4:6] pins
function without affecting PLL operation.
6.3Synchronous Clocking
To guarantee synchronous measurements throughout a sensor network, a system clock should be distributed to arrive at all nodes in phase. The
distributed system clock can either be the full
32.768 MHz master clock, or the CS5378 PLL can
create a synchronous 32.768 MHz clock from a
slower clock. To ensure the generated clock remains synchronous with the network, the CS5378
PLL uses a phase/frequency detector architecture.
6.2PLL Mode Select
The CS5378 PLL operational mode and frequency
are selected immediately after reset based on the
state of the PLL[0:2] pins. On the rising edge of the
reset signal, the digital high or low state of the
PLL[0:2] pins is latched and used to program the
clock input type and frequency.
DS639F322
CS5378
6.4Master Clock Jitter and Skew
Care must be taken to minimize jitter and skew on
the distributed system clock as both parameters affect measurement performance.
Jitter on the input clock causes jitter in the generated modulator clock, resulting in sample timing errors and increased noise.
Skew between input clocks from node to node creates a sample timing offset, resulting in systematic
measurement errors in a reconstructed signal.
DS639F323
7. SYNCHRONIZATION
Figure 13. Synchronization Block Diagram
SYNC
MSYNC
Digital
Filter
Generator
MSYNC
0
1
MSEN
0
1
TSYNC
Test Bit
Stream
Output
CS5378
The CS5378 has a dedicated SYNC input that
aligns the internal digital filter phase and generates
an external signal for synchronizing modulator analog sampling. By providing simultaneous rising
edges to the SYNC pins of multiple CS5378 devices, synchronous sampling across a network can be
guaranteed.
7.1Pin Description
SYNC - Pin 19
Synchronization input, rising edge triggered.
7.2MSYNC Generation
The SYNC signal rising edge is used to generate a
retimed synchronization signal, MSYNC. The
MSYNC signal reinitializes internal digital filter
phase and is driven onto the MSYNC output pin to
phase align modulator analog sampling.
The MSEN bit in the digital filter CONFIG register
(0x00) enables MSYNC generation. See “Modulator Interface” on page 36 for more information
about MSYNC.
7.3Digital Filter Synchronization
The internal MSYNC signal resets the digital filter
state machine to establish a known digital filter
phase. Filter convolutions restart, and the next output word is available one full sample period later.
Repetitive synchronization is supported when
SYNC events occur at exactly the selected output
rate. In this case, re-synchronization will occur at
the start of a convolution cycle when the digital filter state machine is already reset.
7.4 Modulator Synchronization
The external MSYNC signal phase aligns modulator analog sampling when connected to the
CS5373A MSYNC input. This ensures synchronous analog sampling relative to MCLK.
Repetitive synchronization of the modulators is
supported when SYNC events occur at exactly the
selected output rate. In this case, re-synchronization always occurs at the start of analog sampling.
7.5Test Bit Stream Synchronization
When the test bit stream generator is enabled, an
MSYNC signal can reset the internal data pointer.
This restarts the test bit stream from the first data
point to establish a known output signal phase.
The TSYNC bit in the digital filter TBSCFG register (0x2A) enables synchronization of the test bit
stream by MSYNC. When TSYNC is disabled, the
test bit stream phase is not affected by MSYNC.
DS639F324
8. CONFIGURATION BY EEPROM
SS:EECS
SCK
MISO
MOSI
CS5378AT25640
CS
SCK
SI
SO
27
24
25
26
1
6
2
5
VD
GND
WP VCC HOLD
387
4
Figure 14. EEPROM Configuration Block Diagram
CS5378
After reset, the CS5378 reads the state of the
GPIO7:BOOT pin to determine a source for configuration commands. If BOOT is high, the
CS5378 initiates serial transactions to read configuration information from an external EEPROM.
8.1Pin Descriptions
Pins required for EEPROM boot are listed here,
other serial pins are inactive.
SCK - Pin 24
Serial clock output, nominally 1.024 MHz.
MISO - Pin 25
Serial data input pin. Valid on rising edge of SCK,
transition on falling edge.
MOSI - Pin 26
Serial data output pin. Valid on rising edge of
SCK, transition on falling edge.
SS:EECS - Pin 27
EEPROM chip select output, active low.
8.2EEPROM Hardware Interface
When booting from EEPROM the CS5378 actively
performs serial transactions, as shown in Figure 15,
DS639F325
to read configuration commands and data. 8-bit
SPI opcodes and 16-bit addresses are combined to
read back 8-bit configuration commands and 24-bit
configuration data.
System design should include a connection to the
configuration EEPROM for in-circuit reprogramming. The CS5378 serial pins tri-state when inactive to support external connections to the serial
bus.
8.3EEPROM Organization
The boot EEPROM holds the 8-bit commands and
24-bit data required to initialize the CS5378 into an
operational state. Configuration information starts
at memory location 0x10, with addresses 0x00 to
0x0F free for use as manufacturing header information.
The first serial transaction reads a 1-byte command
from memory location 0x10 and then, depending
on the command type, reads multiple 3-byte data
words to complete the command. Command and
data reads continue until the ‘Filter Start’ command
is recognized.
SCK
MOSI
SS:EECS
MSBLSB
MISO
X
612345
MSBLSB612345
18276543
Cycle
MOSI
MISO
0x03ADDR
DATA1DATA3DATA2
SS:EECS
READ
1 BYTE / 3 BYTE
ADDR
CMD
ADDR
DATA
2 BYTE
Figure 15. EEPROM Serial Read Transactions
Serial Read from EEPROM
InstructionOpcodeAddressDefinition
Read0x03ADDR[15:0]Read data beginning at the address given in ADDR.
CS5378
DS639F326
CS5378
Figure 16. 8 Kbyte EEPROM Memory Organization
0000h
1FFFh
EEPROM
Manufacturing
Information
EEPROM
Command and
Data Values
Mfg Header
8-bit Command
0010h
N x 24-bit Data
8-bit Command
N x 24-bit Data
. . .
Table 6. Maximum EEPROM Configuration
Memory RequirementBytes
Digital Filter Registers (12)84
FIR Coefficients (255+255)1537
IIR Coefficients (3+5)25
‘Filter Start’ Command1
Total Bytes1647
Write DF Register - 0x01
This EEPROM command writes a data value to the
specified digital filter register. Digital filter registers control hardware peripherals and filtering
functions. See “Digital Filter Registers” on page 71
for the bit definitions of the digital filter registers.
Sample Command:
Write digital filter register 0x00 with data value
0x060431. Then write 0x20 with data 0x000240.
01 00 00 00 06 04 31
01 00 00 20 00 02 40
Write FIR Coefficients - 0x02
The maximum number of bytes that will be written
for a single configuration is less than 2 KByte
(16 Kbit), including command overhead:
Supported serial configuration EEPROMs are
SPI mode 0 (0,0) compatible, 16-bit addresses, 8bit data, larger than 2 KByte (16 KBit). ATMEL
AT25640, AT25128, or similar serial EEPROMs
are recommended.
8.4EEPROM Configuration Commands
A summary of available EEPROM commands is
shown in Table 7.
This EEPROM command writes custom coefficients for the FIR1 and FIR2 filters. The first two
data words set the number of FIR1 and FIR2 coefficients to be written. The remaining data words are
the concatenated FIR1 and FIR2 coefficients.
A maximum of 255 coefficients can be written for
each FIR filter, though the available digital filter
computation cycles will limit their practical size.
See “FIR Filter” on page 44 for more information
about FIR filter coefficients.
Sample Command:
Write FIR1 coefficients 0x00022E, 0x000771 then
FIR2 coefficients 0xFFFFB9, 0xFFFE8D.
02 00 00 02 00 00 02
00 02 2E 00 07 71 FF FF B9 FF FE 8D
Write IIR Coefficients - 0x03
This EEPROM command writes custom coefficients for the two stage IIR filter. The IIR architecture and number of coefficients is fixed, so eight
data words containing coefficient values always
immediately follow the command byte. The IIR coefficient write order is: a11, b10, b11, a21, a22,
b20, b21, and b22. See “IIR Filter” on page 52 for
more information about IIR filter coefficients.
DS639F327
CS5378
Table 7. EEPROM Boot Configuration Commands
(DATA) indicates multiple words of this type are to be written.
NameCMD
8-bit
DATA
24-bit
Description
NOP00-No Operation
WRITE DF REGISTER01REG
DATA
Write Digital Filter Register
WRITE FIR COEFFICIENTS02NUM FIR1
NUM FIR2
(FIR COEF)
Write Custom FIR Coefficients
WRITE IIR COEFFICIENTS03a11
b10
b11
a21
a22
b20
b21
b22
Write Custom IIR Coefficients
WRITE ROM COEFFICIENTS04COEF SELUse On-Chip Coefficients
03
84 BC 9D 7D A1 B1 82 5E 4F 83 69 4F
3C AD 5F 3E 51 04 83 5D F8 3E 51 04
Write ROM Coefficients - 0x04
This EEPROM command selects the on-chip coefficients for the FIR1, FIR2, IIR 1st order, and IIR
2nd order filters for use by the digital filter. One
data word is required to select which internal coefficient sets to use. See “Filter Coefficient Selection” on page 38 for information about selecting
on-chip FIR and IIR coefficient sets.
Sample Command:
Select IIR1 and IIR2 3 Hz @ 500 SPS low-cut coefficients, with FIR1 and FIR2 linear phase highcut coefficients. Data word 0x002200.
04 00 22 00
Filter Start - 0x07
This EEPROM command initializes and starts the
digital filter. Measurement data becomes available
one full sample period after this command is issued. No data words are required for this EEPROM command.
Sample Command:
07
DS639F328
8.5Example EEPROM Configuration
Table 8. Example EEPROM File
AddrDataDescription
0000Mfg header
0100
0200
0300
0400
0500
0600
0700
0800
0900
0A00
0B00
0C00
0D00
0E00
0F00
1004Write ROM Coefficients
1100
1222
1300
1401Write CONFIG Register
1500
1600
1700
1806
1904
1A31
1B01Write FILTCFG Register
1C00
1D00
1E20
1F00
AddrDataDescription
2102
2240
2301Write TBSCFG Register
2400
2500
262A
2707
2840
2940
2A01Write TBSGAIN Register
2B00
2C00
2D2B
2E04
2FB0
3000
3107Filter Start
Table 8 shows an example EEPROM file for a minimal CS5378 configuration.
CS5378
DS639F329
9. CONFIGURATION BY MICROCONTROLLER
SCK
MISO
MOSI
Pin Logic
SPI™
Figure 17. Serial Interface Block Diagram
Command
SS:EECS
Registers
Digital Filter
Interpreter
Serial
CS5378
After reset, the CS5378 reads the state of the
GPIO7:BOOT pin to determine a source for configuration commands. If BOOT is low, the CS5378
receives configuration commands from a microcontroller.
9.1Pin Descriptions
Pins required for microcontroller boot are listed
here, other serial pins are inactive.
SS:EECS - Pin 27
Slave select input pin, active low. Serial chip select
input from a microcontroller.
MOSI - Pin 26
Serial data input pin. Valid on rising edge of SCK,
transition on falling edge.
MISO - Pin 25
Serial data output pin. Valid on rising edge of
SCK, transition on falling edge. Open drain output
requiring a 10 kΩ pull-up resistor.
9.2Microcontroller Hardware Interface
When booting from a microcontroller the CS5378
receives configuration commands and configuration data through serial transactions, as shown in
Figure 18. 8-bit SPI opcodes and 8-bit addresses
are combined to read and write 24-bit configuration
commands and data.
Microcontroller serial transactions require toggling
the SS:EECS pin as the CS5378 chip select and
writing a serial clock to the SCK input. Serial data
is input to the CS5378 on the MOSI pin, and output
on the MISO pin.
9.3Microcontroller Serial Transactions
Microcontroller configuration commands are written to the digital filter through SPI registers. A 24bit command and two 24-bit data words can be
written to the SPI registers in any single serial
transaction. Some commands require additional
data words through additional serial transactions to
complete.
SCK - Pin 24
Serial clock input pin. Serial clock input from microcontroller, maximum 4.096 MHz.
9.3.1SPI opcodes
A microcontroller communicates with the CS5378
serial port using standard 8-bit SPI opcodes and an
8-bit address. The standard SPI ‘Read’ and ‘Write’
opcodes are listed in Figure 18.
DS639F330
SCK
MOSI
Figure 18. Microcontroller Serial Transactions
SS:EECS
MSBLSB
MISO
X
612345
MSBLSB612345
18276543
Cycle
MISO0x02ADDRData1
MOSI
MISO
MOSI
Microcontroller Write to SPI Registers
Microcontroller Read from SPI Registers
DataNData2
SS:EECS
SS:EECS
0x03ADDR
Data1DataNData2
InstructionOpcodeAddressDefinition
Write0x02ADDR[7:0]Write SPI registers beginning at the address in ADDR.
Read0x03ADDR[7:0]Read SPI registers beginning at the address in ADDR.
CS5378
DS639F331
CS5378
NameAddr.Type# BitsDescription
SPICTRL00 - 02R/W8, 8, 8SPI Control
SPICMD03 - 05R/W8, 8, 8SPI Command
SPIDAT106 - 08R/W8, 8, 8SPI Data 1
SPIDAT209 - 0BR/W8, 8, 8SPI Data 2
Figure 19. SPI Registers
9.3.2SPI registers
The SPI registers are shown in Figure 19 and are
24-bit registers mapped into an 8-bit register space
as high, mid, and low bytes. See “SPI Registers” on
page 66 for the bit definitions of the SPI registers.
9.3.3Serial transactions
A serial transaction to the SPI registers starts with
an SPI opcode, followed by an address, and then
some number of data bytes written or read starting
at that address.
Typical serial write transactions require sending
groups of 5, 8, or 11 total bytes to the SPICMD or
SPIDAT1 registers:
5-byte write to SPICMD
02 03 12 34 56
5-byte write to SPIDAT1
02 06 12 34 56
MOSI: 03 01 00
MISO: xx xx 12
5-byte read of SPIDAT1
MOSI: 03 06 00 00 00
MISO: xx xx 12 34 56
9.3.4Multiple serial transactions
Some configuration commands require multiple serial transactions to complete. There must be a
small delay between transactions for the CS5378 to
process the incoming data. Two methods can be
used to ensure the CS5378 is ready to receive the
next configuration command.
1) Delay a fixed 1 ms period to guarantee enough
time for the command to be completed.
2) Verify the status of the E2DREQ bit by reading
the SPICTRL register. When low, the CS5378 is
ready for the next command.
8-byte write to SPICMD, SPIDAT1
02 03 12 34 56 AB CD EF
8-byte write to SPIDAT1, SPIDAT2
02 06 12 34 56 AB CD EF
11-byte write to SPICMD, SPIDAT1, SPIDAT2
02 03 12 34 56 AB CD EF 65 43 21
Typical serial read transactions require groups of 3
or 5 bytes, split between writing into MOSI and
reading from MISO.
3-byte read of mid-byte of SPICTRL
9.3.5Polling E2DREQ
One transaction type that can always be performed
no matter the delay from the previous configuration
command is reading E2DREQ in the mid-byte of
the SPICTRL register. A 3-byte read transaction.
MOSI: 03 01 00
MISO: xx xx 01 <- E2DREQ bit high
MISO: xx xx 00 <- E2DREQ bit low
The E2DREQ bit reads high while a serial transac-
tion is being processed. When low, the digital filter
is ready to receive a new serial transaction.
DS639F332
CS5378
[DATA] indicates data word returned from digital filter.
(DATA) indicates multiple words of this type are to be written.
NameCMD
24-bit
DAT1
24-bit
DAT2
24-bit
Description
NOP000000--No Operation
WRITE DF REGISTER000001REGDATAWrite Digital Filter Register
READ DF REGISTER000002REG
[DATA]
-
-
Read Digital Filter Register
WRITE FIR COEFFICIENTS000003NUM FIR1
(FIR COEF)
NUM FIR2
(FIR COEF)
Write Custom FIR Coefficients
WRITE IIR COEFFICIENTS000004a11
b11
a22
b21
b10
a21
b20
b22
Write Custom IIR Coefficients
WRITE ROM COEFFICIENTS000005COEF SEL-Use On-Chip Coefficients
NOP000006--No Operation
NOP000007--No Operation
FILTER START000008--Start Digital Filter Operation
A summary of available microcontroller configuration commands is listed in Table 9.
Write DF Register - 0x01
This configuration command writes a specified
digital filter register. Digital filter registers control
hardware peripherals and filtering functions. See
“Digital Filter Registers” on page 71 for the bit definitions of the digital filter registers.
Sample Command:
Write digital filter register 0x00 with data value
0x060431. Then write 0x20 with data 0x000240.
02 03 00 00 01 00 00 00 06 04 31
Delay 1 ms or poll E2DREQ
02 03 00 00 01 00 00 20 00 02 40
Delay 1 ms or poll E2DREQ
Read DF Register - 0x02
This command reads a specified digital filter register. The register value is requested in the first serial
transaction, with the register value copied to
SPIDAT1 and read in a subsequent serial transaction.
Sample Command:
Read digital filter registers 0x00 and 0x20.
02 03 00 00 02 00 00 00
Delay 1 ms or poll E2DREQ
MOSI: 03 06 00 00 00
MISO: xx xx 06 04 31
02 03 00 00 02 00 00 20
Delay 1 ms or poll E2DREQ
MOSI: 03 06 00 00 00
MISO: xx xx 00 02 40
DS639F333
CS5378
Write FIR Coefficients - 0x03
This command writes custom coefficients for the
FIR1 and FIR2 filters. The first two data words set
the number of FIR1 and FIR2 coefficients to be
written. The remaining data words are the concatenated FIR1 and FIR2 coefficients.
A maximum of 255 coefficients can be written for
each FIR filter, though the available digital filter
computation cycles will limit their practical size.
See “FIR Filter” on page 44 for more information
about FIR filter coefficients.
Sample Command:
Write FIR1 coefficients 0x00022E, 0x000771 then
FIR2 coefficients 0xFFFFB9, 0xFFFE8D.
02 03 00 00 03 00 00 02 00 00 02
Delay 1 ms or poll E2DREQ
02 06 00 02 2E 00 07 71
Delay 1 ms or poll E2DREQ
02 06 FF FF B9 FF FE 8D
Delay 1 ms or poll E2DREQ
Write IIR Coefficients - 0x04
This command writes custom coefficients for the
two stage IIR filter. The IIR architecture and number of coefficients is fixed, so eight coefficient values immediately follow this command. The IIR
coefficient write order is: a11, b10, b11, a21, a22,
b20, b21, and b22. See “IIR Filter” on page 52 for
more information about IIR filter coefficients.
02 06 3C AD 5F 3E 51 04
Delay 1 ms or poll E2DREQ
02 06 83 5D F8 3E 51 04
Delay 1 ms or poll E2DREQ
Write ROM Coefficients - 0x05
This configuration command selects the on-chip
coefficients for FIR1, FIR2, IIR 1st order, and IIR
2nd order filters for use by the digital filter. One
data word is required to select which internal coefficient sets to use. See “Filter Coefficient Selection” on page 38 for information about selecting
on-chip FIR and IIR coefficient sets.
Sample Command:
Select IIR1 and IIR2 3 Hz @ 500 SPS low-cut coefficients, with FIR1 and FIR2 linear phase highcut coefficients. Data word 0x002200.
02 03 00 00 05 00 22 00
Delay 1 ms or poll E2DREQ
Filter Start - 0x08
This command initializes and starts the digital filter. Measurement data becomes available one full
sample period after this command is issued. No
data words are required for this command.
Sample Command:
02 03 00 00 08
Delay 1 ms or poll E2DREQ
Filter Stop - 0x09
This command disables the digital filter. Measurement data output stops immediately after this command is issued. No data words are required for this
command.
02 03 00 00 04 84 BC 9D 7D A1 B1
Delay 1 ms or poll E2DREQ
02 06 82 5E 4F 83 69 4F
Delay 1 ms or poll E2DREQ
Table 10 shows an example microcontroller transactions for a minimal CS5378 configuration.
CS5378
DS639F335
CS5378
Figure 20. Modulator Data Interface
FIR
IIR
Filters
Filter
Output to High Speed Serial Interface
DC Offset
Correction
Output Rate 4000 SPS ~ 1 SPS
& Gain
MDATA
MFLAG
MDI Input
512 kHz
MCLK /
Generate
MSYNC
CLK
SYNC
MSYNC
SINC
Filter
MCLK
10.MODULATOR INTERFACE
The CS5378 performs digital filtering for a ΔΣ type
modulator. Signals from the ΔΣ modulators are
connected through the modulator data interface
(MDI).
10.1 Pin Descriptions
MCLK - Pin 11
Modulator clock output. Nominally 2.048 MHz or
1.024 MHz.
MSYNC - Pin 12
Modulator synchronization signal output. Generated from the SYNC input.
MDATA - Pin 13
Modulator data input, nominally 512 kbit/s.
MFLAG - Pin 14
10.2 Modulator Clock Generation
The MCLK output is a low-jitter, low-skew modulator clock generated from the 32.768 MHz master
clock.
MCLK typically operates at 2.048 MHz unless analog low-power modes require a 1.024 MHz modulator clock.
The MCLK rate is selected and the MCLK output
is enabled by bits in the digital filter CONFIG register (0x00). By default MCLK is disabled and
driven low.
10.3 Modulator Synchronization
The MSYNC output signal follows an input to the
SYNC pin. MSYNC phase aligns the modulator
sampling instant to guarantee synchronous analog
sampling across a measurement network.
Modulator flag input. Driven high when the modulator is unstable due to an analog over-range condition.
DS639F336
MSYNC is enabled by a bit in the CONFIG register
(0x00). By default SYNC inputs do not cause an
MSYNC output.
CS5378
10.4 Modulator Data Input
The MDATA input expects 1-bit ΔΣ data at a
512 kHz or 256 kHz rate. The input rate is selected
by a bit in the CONFIG register (0x00). By default,
MDATA is expected at 512 kHz.
The MDATA input one’s density is designed for
full scale positive at 86% and full scale negative at
14%, with absolute maximum over-range capability to 93% and 7%. These raw ΔΣ inputs are decimated and filtered by the digital filter to create 24bit samples at the output rate.
10.5 Modulator Flag Input
A high MFLAG input signal indicates the ΔΣ modulator has become unstable due to an analog overrange input signal. Once the over-range signal is
reduced, the modulator recovers stability and the
MFLAG signal is cleared.
The MFLAG input is mapped to a status bit in the
serial data output stream, and is associated with
each sample when written. See “Serial Data Interface” on page 58 for more information on the
MFLAG error bit in the serial data status byte.
DS639F337
CS5378
Figure 21. Digital Filter Stages
SINC Filter
2 - 64000
FIR1
4
FIR2
2
IIR1IIR2
1st Order
2nd Order
Output to High Speed Serial Data Interface
DC Offset
Correction
Output Rate 4000 SPS ~ 1 SPS
& Gain
Modulator
512 kHz
Input
11.DIGITAL FILTER INITIALIZATION
The CS5378 digital filter consists of three multistage sections: a three stage SINC filter, a two stage
FIR filter, and a two stage IIR filter.
To initialize the digital filter, FIR and IIR coefficient sets are selected using configuration commands and the FILTCFG register (0x20) is written
to select the output filter stage, the output word
rate, and the number of enabled channels. The digital filter clock rate is then selected by writing the
CONFIG register (0x00).
11.1 Filter Coefficient Selection
Selection of SINC filter coefficients is not required
as they are selected automatically based on the programmed output word rate.
Digital filter FIR and IIR coefficients are selected
using the ‘Write FIR Coefficients’ and ‘Write IIR
Coefficients’, or the ‘Write ROM Coefficients’
configuration commands. When writing the FIR
and IIR coefficients from ROM, a data word selects
an on-chip coefficient set for each filter stage. Figure 22 shows the format of the coefficient selection
word, and the available coefficient sets for each selection.
Characteristics of the on-chip digital filter coefficients are discussed in the ‘SINC Filter’, ‘FIR Filter’, and ‘IIR Filter’ sections of this data sheet.
11.2 Filter Configuration Options
Digital filter parameters are selected by bits in the
FILTCFG register (0x20), and the digital filter
clock rate is selected by bits in the CONFIG register (0x00).
11.2.1 Output Filter Stage
The digital filter can output data following any
stage in the filter chain. The output filter stage is
selected by the FSEL bits in the FILTCFG register.
Taking data from the SINC or FIR1 filter stages reduces the overall decimation of the filter chain and
increases the output rate, as discussed in the next
section. Taking data from FIR2, IIR1, IIR2, or IIR3
results in data at the selected rate.
DS639F338
11.2.2 Output Word Rate
Bits23:2019:1615:1211:87:43:0
Selection00000000IIR2IIR1FIR2FIR1
Figure 22. FIR and IIR Coefficient Set Selection Word
Bits 15:12IIR2 Coefficients
00003 Hz @ 2000 SPS
00013 Hz @ 1000 SPS
00103Hz @ 500SPS
00113Hz @ 333SPS
01003Hz @ 250SPS
Bits 11:8IIR1 Coefficients
00003 Hz @ 2000 SPS
00013 Hz @ 1000 SPS
00103 Hz @ 500 SPS
00113 Hz @ 333 SPS
01003 Hz @ 250 SPS
Bits 7:4FIR2 Coefficients
0000Linear Phase
0001Minimum Phase
Bits 3:0FIR1 Coefficients
0000Linear Phase
0001Minimum Phase
CS5378
The CS5378 digital filter supports output word rates (OWRs) between 4000 SPS and 1 SPS. The output
word rate is selected by the DEC bits in the FILTCFG register.
When taking data directly from the SINC filter, the decimation of the FIR1 and FIR2 stages is bypassed
and the actual output word rate is multiplied by a factor of eight compared with the register selection. When
taking data directly from FIR1, the decimation of the FIR2 stage is bypassed and the actual output word
rate is multiplied by a factor of two. Data taken from the FIR2, IIR1, IIR2, or IIR3 filtering stages is output
at the selected rate.
11.2.3 Digital Filter Clock
The digital filter clock rate is programmable between 8.192 MHz and 32 kHz by bits in the CONFIG register.
Computation Cycles
The minimum digital filter clock rate for a configuration depends on the computation cycles required to
complete digital filter convolutions at the selected output word rate. All configurations work for a maximum digital filter clock, but lower clock rates consume less power.
Standby Mode
The CS5378 can be placed in a low-power standby mode by sending the ‘Filter Stop’ configuration command and programming the digital filter clock to 32 kHz. In this mode the digital filter idles, consuming
minimal power until re-enabled by later configuration commands.
DS639F339
CS5378
sinc1
8
5th order
4th order
Figure 23. SINC Filter Block Diagram
1-bit
24-bit
Δ−Σ
2
stage1
sinc2
4th order
2
stage2
sinc2
5th order
2
stage3
sinc2
6th order
2
stage4
sinc2
4th order
5
stage1
sinc3
4th order
5
stage2
sinc3
4th order
5
stage3
sinc3
5th order
2
stage5
sinc3
6th order
3
stage6
sinc3
6th order
2
stage7
sinc3
Output
Input
5th order
5
stage4
sinc3
12.SINC FILTER
The SINC filter primary purpose is to attenuate outof-band noise components from the ΔΣ modulators. While doing so, they decimate 1-bit ΔΣ data
into lower frequency 24-bit data suitable for the
FIR and IIR filters.
The SINC filter has three cascaded sections,
SINC1, SINC2, and SINC3, which are each made
up of the smaller stages shown in Figure 23.
The selected output word rate in the FILTCFG register automatically determines the coefficients and
decimation ratios selected for the SINC filters.
12.1 SINC1 Filter
The first section is SINC1, a single stage 5th order
fixed decimate by 8 SINC filter. This SINC filter
decimates the incoming 1-bit ΔΣ bit stream from
the modulators down to a 64 kHz rate.
12.2 SINC2 Filter
The second section is SINC2, a multi-stage, variable order, variable decimation SINC filter. Depending on the selected output word rate in the
FILTCFG register, different cascaded SINC2 stages are enabled, as shown in Table 11.
12.3 SINC3 Filter
The last section is SINC3, a flexible multi-stage
variable order, variable decimation SINC filter.
Depending on the selected output word rate in the
FILTCFG register, different SINC3 stages are enabled, as shown in Table 11.
12.4 SINC Filter Synchronization
The SINC filter is synchronized to the external system by the MSYNC signal, which is generated
from the SYNC input. The MSYNC signal sets a
reference time (time 0) for all filter operations, and
the SINC filter is restarted to phase align with this
reference time.
FIR1 Filter - decimate by 4FIR2 Filter - decimate by 2
Figure 25. FIR Filter Block Diagram
13.FIR FILTER
The finite impulse response (FIR) filter block consists of two cascaded stages, FIR1 and FIR2. It compensates for SINC filter droop and creates a low-pass corner to block aliased components of the input signal.
On-chip linear phase or minimum phase coefficients can be selected using a configuration command, or
the coefficients can be programmed for a custom filter response.
13.1 FIR1 Filter
The FIR1 filter stage has a decimate by four architecture. It compensates for SINC filter droop and flattens
the magnitude response of the pass band.
The on-chip linear and minimum phase coefficient sets are 48-tap, with a maximum 255 programmable
coefficients. All coefficients are normalized to 24-bit two’s complement full scale, 0x7FFFFF.
The characteristic equation for FIR1 is a convolution of the input values, X(n), and the filter coefficients,
h(k), to produce an output value, Y.
Y = [h(k)*X(n-k)] + [h(k+1)*X(n-(k+1))] + ...
13.2 FIR2 Filter
The FIR2 filter stage has a decimate by two architecture. It creates a low-pass brick wall filter to block
aliased components of the input signal.
The on-chip linear and minimum phase coefficient sets are 126-tap, with a maximum 255 programmable
coefficients. All coefficients are normalized to 24-bit two’s complement full scale, 0x7FFFFF.
The characteristic equation for FIR2 is a convolution of the input values, X(n), and the filter coefficients,
h(k), to produce an output value, Y.
Y = [h(k)*X(n-k)] + [h(k+1)*X(n-(k+1))] + ...
DS639F344
CS5378
13.3 On-Chip FIR Coeffic ients
Two sets of on-chip coefficients, linear phase and
minimum phase, are available for FIR1 and FIR2.
Performance of the on-chip coefficient sets is very
good, with excellent ripple and stop band characteristics as described in Figure 26 and Table 14.
Which on-chip coefficient set to use is selected by
a data word following the ‘Write ROM Coefficients’ configuration command. See “Filter Coefficient Selection” on page 38 for information about
selecting on-chip coefficient sets.
13.4 Programmable FIR Coefficients
A maximum of 255 + 255 coefficients can be programmed into FIR1 and FIR2 to create a custom
filter response. The total number of coefficients for
the FIR filter is fundamentally limited by the available computation cycles in the digital filter, which
itself is determined by the digital filter clock rate.
scale, 0x7FFFFF, and scale all other coefficients
accordingly. To maintain maximum internal dynamic range, the CS5378 FIR filter performs double precision calculations with an automatic gain
correction to scale the final output.
Custom FIR coefficients are uploaded using the
‘Write FIR Coefficients’ configuration command.
See “EEPROM Configuration Commands” on
page 27 or “Microcontroller Configuration Commands” on page 33 for information about writing
custom FIR coefficients.
13.5 FIR Filter Synchronization
The FIR1 and FIR2 filters are synchronized to the
external system by the MSYNC signal, which is
generated from the SYNC input. The MSYNC signal sets a reference time (time 0) for all filter operations, and the FIR filters are restarted to phase
align with this reference time.
Custom filter sets should normalize the maximum
coefficient value to 24-bit two’s complement full
DS639F345
CS5378
FIR1 – Single stage, fixed decimate by 4
Coefficient set 0: linear phase decimate by 4, 48 coefficients
Coefficient set 1: minimum phase decimate by 4, 48 coefficients
SINC droop compensation filter
FIR2 – Single stage, fixed decimate by 2
Coefficient set 0: linear phase decimate by 2, 126 coefficients
Coefficient set 1: minimum phase decimate by 2, 126 coefficients
Brick wall low-pass filter, flat to 40% f
s
Combined SINC + FIR digital filter specifications
Passband ripple less than +/- 0.01 dB below 40% f
s
Transition band -3 dB frequency at 42.89% f
s
Stopband attenuation greater than 130 dB above 50% f
FIR1 (Coefficient set 0)
Low pass, SINC compensation
Linear phase decimate by 4
48 coefficients
h
0
= 558 h24 = 8388607
h
1
= 1905 h25 = 7042723
h
2
= 3834 h26 = 4768946
h
3
= 5118 h27 = 2266428
h
4
= 365 h28 = 189436
h
5
= -14518 h29 = -1053303
h
6
= -39787 h30 = -1392827
h
7
= -67365 h31 = -1084130
h
8
= -69909 h32 = -496361
h
9
= -19450 h33 = 39864
h
10
= 97434 h34 = 332367
h
11
= 258881 h35 = 375562
h
12
= 375562 h36 = 258881
h
13
= 332367 h37 = 97434
h
14
= 39864 h38 = -19450
h
15
= -496361 h39 = -69909
h
16
= -1084130 h40 = -67365
h
17
= -1392827 h41 = -39787
h
18
= -1053303 h42 = -14518
h
19
= 189436 h43 = 365
h
20
= 2266428 h44 = 5118
h
21
= 4768946 h45 = 3834
h
22
= 7042723 h46 = 1905
h
23
= 8388607 h47 = 558
FIR1 (Coefficient set 1)
Low pass, SINC compensation
Minimum phase decimate by 4
48 coefficients
h
0
= 3337 h24 = 555919
h
1
= 22258 h25 = -165441
h
2
= 88284 h26 = -581479
h
3
= 266742 h27 = -617500
h
4
= 655747 h28 = -388985
h
5
= 1371455 h29 = -99112
h
6
= 2502684 h30 = 114761
h
7
= 4031988 h31 = 186557
h
8
= 5783129 h32 = 141374
h
9
= 7396359 h33 = 58582
h
10
= 8388607 h34 = -12664
h
11
= 8325707 h35 = -42821
h
12
= 6988887 h36 = -35055
h
13
= 4531706 h37 = -16792
h
14
= 1507479 h38 = 367
h
15
= -1319126 h39 = 7929
h
16
= -3207750 h40 = 5926
h
17
= -3736028 h41 = 2892
h
18
= -2980701 h42 = 23
h
19
= -1421498 h43 = -1164
h
20
= 237307 h44 = -538
h
21
= 1373654 h45 = -238
h
22
= 1711919 h46 = 18
h
23
= 1322371 h47 = 113
Figure 27. FIR1 Coefficients
DS639F349
CS5378
Filter Type Filter Coefficients
(normalized 24-bit)
FIR2 (Coefficient set 0)
Low pass, passband to 40% f
s
Linear phase decimate by 2
126 coefficients
h0 = -71 h63 = 8388607
h
1
= -371 h64 = 3875315
h
2
= -870 h65 = -766230
h
3
= -986 h66 = -1854336
h
4
= 34 h67 = -137179
h
5
= 1786 h68 = 1113788
h
6
= 2291 h69 = 454990
h
7
= 291 h70 = -642475
h
8
= -2036 h71 = -553873
h
9
= -943 h72 = 298975
h
10
= 2985 h73 = 533334
h
11
= 3784 h74 = -49958
h
12
= -1458 h75 = -443272
h
13
= -5808 h76 = -116005
h
14
= -1007 h77 = 318763
h
15
= 7756 h78 = 208018
h
16
= 5935 h79 = -187141
h
17
= -7135 h80 = -238025
h
18
= -11691 h81 = 68863
h
19
= 3531 h82 = 221211
h
20
= 17500 h83 = 22850
h
21
= 4388 h84 = -174452
h
22
= -20661 h85 = -81993
h
23
= -15960 h86 = 114154
h
24
= 18930 h87 = 109009
h
25
= 29808 h88 = -54172
h
26
= -9795 h89 = -109189
h
27
= -42573 h90 = 4436
h
28
= -7745 h91 = 90744
h
29
= 49994 h92 = 29702
h
30
= 33021 h93 = -62651
h
31
= -47092 h94 = -47092
h
32
= -62651 h95 = 33021
h
33
= 29702 h96 = 49994
h
34
= 90744 h97 = -7745
h
35
= 4436 h98 = -42573
h
36
= -109189 h99 = -9795
h
37
= -54172 h
100
= 29808
h
38
= 109009 h
101
= 18930
h
39
= 114154 h
102
= -15960
h
40
= -81993 h
103
= -20661
h
41
= -174452 h
104
= 4388
h
42
= 22850 h
105
= 17500
h
43
= 221211 h
106
= 3531
h
44
= 68863 h
107
= -11691
h
45
= -238025 h
108
= -7135
h
46
= -187141 h
109
= 5935
h
47
= 208018 h
110
= 7756
h
48
= 318763 h
111
= -1007
h
49
= -116005 h
112
= -5808
h
50
= -443272 h
113
= -1458
h
51
= -49958 h
114
= 3784
h
52
= 533334 h
115
= 2985
h
53
= 298975 h
116
= -943
h
54
= -553873 h
117
= -2036
h
55
= -642475 h
118
= 291
h
56
= 454990 h
119
= 2291
h
57
= 1113788 h
120
= 1786
h
58
= -137179 h
121
= 34
h
59
= -1854336 h
122
= -986
h
60
= -766230 h
123
= -870
h
61
= 3875315 h
124
= -371
h
62
= 8388607 h
125
= -71
Figure 28. FIR2 Linear Phase Coefficients
DS639F350
CS5378
Filter Type Filter Coefficients
(normalized 24-bit)
FIR2 (Coefficient set 1)
Low pass, passband to 40% f
s
Minimum phase decimate by 2
126 coefficients
h0 = 4019 h63 = 67863
h
1
= 43275 h64 = -190800
h
2
= 235427 h65 = -128546
h
3
= 848528 h66 = 114197
h
4
= 2240207 h67 = 147750
h
5
= 4525758 h68 = -46352
h
6
= 7077833 h69 = -143269
h
7
= 8388607 h70 = -13290
h
8
= 6885673 h71 = 114721
h
9
= 2483461 h72 = 51933
h
10
= -2538963 h73 = -75952
h
11
= -4800543 h74 = -68746
h
12
= -2761696 h75 = 38171
h
13
= 1426109 h76 = 68492
h
14
= 3624338 h77 = -7856
h
15
= 1820814 h78 = -57526
h
16
= -1695825 h79 = -12540
h
17
= -2885148 h80 = 41717
h
18
= -605252 h81 = 23334
h
19
= 2135021 h82 = -25516
h
20
= 1974197 h83 = -26409
h
21
= -630111 h84 = 11717
h
22
= -2168177 h85 = 24246
h
23
= -750147 h86 = -1620
h
24
= 1516192 h87 = -19248
h
25
= 1550127 h88 = -4610
h
26
= -508445 h89 = 13356
h
27
= -1686937 h90 = 7526
h
28
= -437822 h91 = -7887
h
29
= 1308705 h92 = -8016
h
30
= 1069556 h93 = 3559
h
31
= -657282 h94 = 7023
h
32
= -1301014 h95 = -598
h
33
= -30654 h96 = -5350
h
34
= 1173754 h97 = -1097
h
35
= 579643 h98 = 3579
h
36
= -803111 h99 = 1806
h
37
= -895851 h
100
= -2058
h
38
= 328399 h
101
= -1859
h
39
= 962522 h
102
= 936
h
40
= 124678 h
103
= 1558
h
41
= -820948 h
104
= -224
h
42
= -466657 h
105
= -1129
h
43
= 545674 h
106
= -152
h
44
= 652827 h
107
= 718
h
45
= -220448 h
108
= 290
h
46
= -680495 h
109
= -395
h
47
= -80886 h
110
= -290
h
48
= 578844 h
111
= 178
h
49
= 306445 h
112
= 227
h
50
= -395302 h
113
= -53
h
51
= -431004 h
114
= -151
h
52
= 181900 h
115
= -5
h
53
= 454403 h
116
= 86
h
54
= 15856 h
117
= 23
h
55
= -395525 h
118
= -42
h
56
= -166123 h
119
= -22
h
57
= 284099 h
120
= 17
h
58
= 253485 h
121
= 14
h
59
= -152407 h
122
= -5
h
60
= -277888 h
123
= -7
h
61
= 28526 h
124
= 1
h
62
= 250843 h
125
= 3
Figure 29. FIR2 Minimum Phase Coefficients
DS639F351
CS5378
CS5378
Z
-1
Z
-1
Z
-1
-a
11
b
11
b
10
-a
21
-a
22
b
21
b
22
b
20
Figure 30. IIR Filter Block Diagram
1st Order IIR1
2nd Order IIR2
3rd Order IIR3 implemented by
running both IIR1 and IIR2 stages
14.IIR FILTER
The infinite impulse response (IIR) filter block
consists of two cascaded stages, IIR1 and IIR2. It
creates a high-pass corner to block very low-frequency and DC components of the input signal.
On-chip IIR1 and IIR2 coefficients can be selected
using a configuration command, or the coefficients
can be programmed for a custom filter response.
14.1 IIR Architecture
The architecture of the IIR filter is automatically
determined when the output filter stage is selected
in the FILTCFG register. Selecting the 1st order
IIR1 filter bypasses the 2nd order stage, while selecting the 2nd order IIR2 filter bypasses the 1st order stage. Selection of the 3rd order IIR3 filter
enables both the 1st and 2nd order stages.
14.2 IIR1 Filter
The 1st order IIR filter stage is a direct form filter
with three coefficients: a11, b10, and b11. Coefficients of a 1st order IIR are inherently normalized
to one, and should be scaled to 24-bit two’s complement full scale, 0x7FFFFF.
The characteristic equations for the 1st order IIR
include an input value, X, an output value, Y, and
two intermediate values, W1 and W2, separated by
a delay element (z
-1
).
W2 = W1
W1 = X + (-a11 * W2)
Y = (W1 * b10) + (W2 * b11)
14.3 IIR2 Filter
The 2nd order IIR filter stage is a direct form filter
with five coefficients: a21, a22, b20, b21, and b22.
Coefficients of a 2nd order IIR are inherently normalized to two, and should be scaled to 24-bit
two’s complement full scale, 0x7FFFFF. Normalization effectively divides the 2nd order coefficients in half relative to the input, and requires
modification of the characteristic equations.
The characteristic equations for the 2nd order IIR
include an input value, X, an output value, Y, and
three intermediate values, W3, W4, and W5, each
separated by a delay element (z-1). The following
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CS5378
characteristic equations model the operation of the
2nd order IIR filter with unnormalized coefficients.
cients to perform the 2nd order IIR filter calculation, which changes the algorithm slightly. The
following characteristic equations model the operation of the 2nd order IIR filter when using normalized coefficients.
The 3rd order IIR filter is implemented by running
both the 1st order and 2nd order IIR filter stages. It
can be modeled by cascading the characteristic
equations of the 1st order and 2nd order IIR stages.
14.5 On-Chip IIR Coeffic ients
Five sets of on-chip coefficients are available for
IIR1 and IIR2, each providing a 3 Hz high-pass
Butterworth response at different output word
rates. Characteristics of the on-chip coefficient sets
are described in Figure 31 and Table 16.
Which on-chip coefficient set to use is selected by
a data word following the ‘Write ROM Coefficients’ configuration command. See “Filter Coefficient Selection” on page 38 for information about
selecting on-chip coefficient sets.
14.6 Programmable IIR Coefficients
A maximum of 3 + 5 coefficients can be programmed into IIR1 and IIR2 to create a custom filter response. Custom filter sets should normalize
the coefficients to 24-bit two’s complement full
scale, 0x7FFFFF. To maintain maximum internal
dynamic range, the CS5378 IIR filter performs
double precision calculations with an automatic
gain correction to scale the final output.
Custom IIR coefficients are uploaded using the
‘Write IIR Coefficients’ configuration command.
See “EEPROM Configuration Commands” on
page 27 or “Microcontroller Configuration Commands” on page 33 for information about writing
custom IIR coefficients.
14.7 IIR Filter Synchronization
The IIR filter is not synchronized to the external
system directly, only indirectly through the synchronization of the SINC and FIR filters. Because
IIR filters have ‘infinite’ memory, a discontinuity
in the input data stream from a synchronization
event can require significant time to settle out. The
exact settling time depends on the size of the discontinuity and the filter coefficient characteristics.
The CS5378 digital filter can apply gain and offset
corrections to the measurement data. Also, an offset calibration algorithm can automatically calculate the offset correction value.
A gain correction value is written to the GAIN registers (0x21), while an offset correction value is
written to the OFFSET register (0x25). Gain and
offset corrections are enabled by the USEGR and
USEOR bits in the FILTCFG register (0x20).
When enabled, the offset calibration algorithm will
automatically calculate an offset correction value
and write it into the OFFSET register. Offset calibration is enabled by writing the EXP and ORCAL
bits in FILTCFG.
15.1 Gain Correction
Gain correction in the CS5378 normalizes sensor
gain in multi-sensor networks. It requires an externally calculated correction value to be written into
the GAIN register (0x21).
A gain correction value is 24-bit two’s complement
with unity gain defined as full scale, 0x7FFFFF.
Gain correction always scales to a fractional value,
and can never gain the digital filter data greater
than one.
Output Value = Data * (GAIN / 0x7FFFFF)
Unity Gain: GAIN = 0x7FFFFF
50% Gain: GAIN = 0x3FFFFF
Zero Gain: GAIN = 0x000000
Once the GAIN register is written, the USEGR bit
in the FILTCFG register enables gain correction.
15.2 Offset Correction
Offset correction in the CS5378 cancels the DC
bias of a measurement channel by subtracting the
value in the OFFSET register (0x25) from the digital filter output data word.
An offset correction value is 24-bit two’s complement with a maximum positive value of 0x7FFFFF,
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CS5378
and a maximum negative value of 0x800000. If applying an offset correction causes the final result to
exceed a 24-bit two’s complement maximum, the
output data will saturate to that maximum value.
Output Data = Input Data - Offset Correction
Max Positive Output Value = 0x7FFFFF
Max Negative Output Value = 0x800000
Once the OFFSET register is written, the USEOR
bit in the FILTCFG register enables offset correction.
15.3 Offset Calibration
An offset calibration algorithm in the CS5378 can
automatically calculate an offset correction value.
When using the offset calibration algorithm, background noise data should be used as the input signal
for calculating the offset of the measurement channel.
The offset calibration algorithm is an exponential
averaging function that places increased weight on
more recent digital filter data. The exponential
weighting factor is set by the EXP bits in the
FILTCFG register, with larger exponent values
producing a smoother averaging function that requires a longer settling time, and smaller values
producing a noisier averaging function that requires a shorter settling time. Typical exponential
values range from 0x05 to 0x0F, depending on the
available settling time.
The characteristic equations of the offset calibration algorithm include an input value, X, an output
value, Y, a summation value, YSUM, a sample index, n, and an exponential value, EXP.
Once the EXP bits are written, the ORCAL bit in
the FILTCFG register is set to enable offset calibration. When enabled, an updated offset correction
value is automatically written to the OFFSET register. When the offset calibration algorithm is fully
settled, the ORCAL bit should be cleared to maintain the final value in the OFFSET register.
DS639F357
16.SERIAL DATA INTERFACE
CS5378
Figure 33. Serial Data Interface Block Diagram
System Telemetry
MISO
DRDY
SCK
Data Ready
Data In
Clock Out
Data
Status
02331
--
MFLAG
----
W
3129302827262524
Figure 34. 32-bit Serial Data Format
TB
--
--
0 - Modulator Ok
1 - Modulator Error
0 - No Time Break
1 - Time Break
0 - FIFO Ok
1 - FIFO Overflow
CS5378
Once digital filtering is complete, each 24-bit output sample is combined with an 8-bit status byte.
These data words are written to an 8-deep FIFO
buffer and then transmitted to the communications
channel through a high speed serial data interface.
16.1 Pin Descriptions
DRDY
Data ready output signal, active low. Open drain
output requiring an external pull-up resistor.
- Pin 23
SCK - Pin 24
Serial clock input.
MISO - Pin 25
Serial data output.
16.2 Serial Data Format
Serial data transactions transfer either 24-bit data
words or 32-bit status+data words, depending on
the STAT bit in the CONFIG register. When transmitting status information, each 8-bit status byte
has an MFLAG bit, a time break bit, and a FIFO
overflow bit encoded as shown in Figure 34.
MFLAG Bit - MFLAG
The MFLAG bit is set in the status byte when an
signal is received on the MFLAG pin. When re-
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CS5378
DRDY
SCK
MISO
Figure 35. SD Port Transaction
MSBLSB
ceived, the MFLAG bit is set in the next output
word. See “Modulator Interface” on page 36 for
more information about MFLAG.
Time Break Bit - TB
The time break bit marks a timing reference based
on a rising edge into the TIMEB pin. After a programmed delay, the TB bit in the status byte is set
for one output sample. The TIMEBRK digital filter register (0x29) programs the sample delay for
the TB bit output. See “Time Break Controller” on
page 63 for more information about time break.
FIFO Overflow Bit - W
The FIFO overflow bit indicates an error condition
in the serial data FIFO, and is set if new digital filter data overwrites a FIFO location containing data
which has not yet been sent.
The W bit is sticky, meaning it persists indefinitely
once set. Clearing the W bit requires sending the
‘Filter Stop’ and ‘Filter Start’ configuration commands to reinitialize the data FIFO.
Conversion Data Word
The lower 24-bits of the serial data word is the conversion sample for the specified channel. Conversion data is 24-bit two’s complement format.
16.3 Serial Data Transactions
The CS5378 automatically initiates serial data
transactions whenever data becomes available in
the output FIFO by driving the DRDY
Once a serial data transaction is initiated, serial
clocks received into SCK cause data to be output to
MISO, as shown in Figure 35. When all available
data is read from the serial data FIFO, DRDY
leased.
pin low.
is re-
DS639F359
17.TEST BIT STREAM GENERATOR
Digital ΔΣ Modulator
24-bit
1-bit
TBSDATA
Digital Filter
TBSGAIN Register
24-bit
Figure 36. Test Bit Stream Generator Block Diagram
Data Bus
CS5378
The CS5378 test bit stream (TBS) generator creates
sine wave ΔΣ bit stream data to drive an external
test DAC. The TBS digital output can also be internally connected to the MDATA inputs for loopback testing of the digital filter.
17.1 Pin Descriptions
TBSDATA - Pin 8
Test bit stream 1-bit ΔΣ data output.
MCLK - Pin 11
Test bit stream clock output.
17.2 TBS Architecture
The test bit stream generator consists of a data interpolator and a digital ΔΣ modulator. It receives
periodic 24-bit data from the digital filter to create
a 1-bit ΔΣ data output on the TBSDATA pin.
The TBS input data from the digital filter is scaled
by the TBSGAIN register (0x2B). Maximum stable amplitude is 0x04FFFF, with 0x04B000 approximately full scale for the CS5373A test DAC.
The full scale 1-bit ΔΣ output from the TBS generator is defined as 25% minimum and 75% maximum one’s density.
17.3 TBS Configuration
Configuration options for the TBS generator are set
through the TBSCFG register (0x2A). Gain scaling of the TBS generator output is set by the TBSGAIN register (0x2B).
Interpolation Factor - INTP[7:0]
Selects how many times the interpolator uses a data
point when generating the output bit stream. Interpolation is zero based and represents one greater
than the programmed register value.
Output Rate - RATE[2:0]
Selects the TBSDATA output rate.
Synchronization - TSYNC
Enables synchronization of the TBS output phase
to the MSYNC signal.
Loopback - LOOP
Enables digital loopback from the TBS output to
the MDATA inputs.
Programs full period delays for TBSDATA, up to a
maximum of 63 bits.
17.5 TBS Sine Wave Output
The TBS generator uses data from digital filter
memory to create a sine wave test signal that can
drive a test DAC. Sine wave frequency and output
Gain - TBSGAIN[23:0]
Scales the amplitude of the sine wave output. Maximum 0x04FFFF, nominal 0x04B000.
17.4 TBS Data Source
An on-chip 24-bit 1024 point digital sine wave is
stored on the CS5378 which will produce the test
signal frequencies listed in Table 18. Additional
discrete test frequencies and output rates can be
programmed by varying the interpolation factor
data rate are calculated as shown by the characteristic equation of Table 18.
The sine wave maximum ΔΣ one’s density output
from the TBS generator is set by the TBSGAIN
register. TBSGAIN can be programmed up to a
maximum of 0x04FFFF, with the TBS generator
unstable for higher amplitudes. For the CS5373A
test DAC, a gain value of 0x04B000 produces an
approximately full scale sine wave output (5 V
differential).
and output rate.
pp
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CS5378
17.6 TBS Loopback Testing
Included as part of the CS5378 test bit stream generator is a feedback path to the digital filter MDATA input. This loopback mode provides a fully
digital signal path to test the TBS generator, digital
filter, and data collection interface. Digital loopback testing expects 512 kHz ΔΣ data into the
MDATA input.
A mismatch of the TBS generator full scale output
and the MDATA full scale input results in an amplitude mismatch when testing in loopback mode.
The TBS generator outputs a 75% maximum one’s
density, while the MDATA inputs expect an 86%
maximum one’s density from a ΔΣ modulator, re-
sulting in a measured full scale error of approximately -3.6 dB.
17.7 TBS Synchronization
When the TSYNC bit is set in the TBSCFG register, the MSYNC signal resets the sine wave data
pointer and phase aligns the TBS signal output.
Once the digital filter is settled, all CS5378 devices
receiving the SYNC signal will have identical TBS
signal phase. See “Synchronization” on page 24
for more information about the SYNC and
MSYNC signals.
If TSYNC is clear, MSYNC has no effect on the
TBS data pointer and no change in the TBS output
phase will occur during synchronization.
DS639F362
18.TIME BREAK CONTROLLER
TIMEB
in Serial Data
Status Byte
Delay Counter
TIMEBRK
TB Flag
Figure 37. Time Break Block Diagram
CS5378
A time break signal is used to mark timing events
that occur during measurement. An external signal
sets a flag in the status byte of an output sample to
mark when the external event occurred.
A rising edge input to the TIMEB pin causes the
TB timing reference flag to be set in the serial data
status byte. When set, the TB flag appears for only
one output sample in the status byte. The TB flag
output can be delayed by programming a sample
delay value into the TIMEBRK digital filter register.
18.1 Pin Description
TIMEB - Pin 20
Time break input pin, rising edge triggered.
18.2 Time Break Operation
An externally generated timing reference signal applied to the TIMEB pin initiates an internal sample
counter. After a number of output samples have
passed, programmed in the TIMEBRK digital filter
register (0x29), the TB flag is set in the status byte
of the serial data output word. The TB flag is automatically cleared for subsequent data words, and
appears for only one output sample.
18.3 Time Break Delay
The TIMEBRK register (0x29) sets a sample delay
between a received rising edge on the TIMEB pin
and writing the TB flag into the serial data status
byte.
The programmable sample counter can compensate
for group delay through the digital filters. When the
proper group delay value is programmed into the
TIMEBRK register, the TB flag will be set in the
status byte of the measurement sample taken when
the timing reference signal was received.
18.3.1 Step Input and Group Delay
A simple method to empirically measure the step
response and group delay of a CS5378 measurement channel is to use the time break signal as both
a timing reference input and an analog step input.
When a rising edge is received on the TIMEB pin
with no delay programmed into the TIMEBRK register, the TB flag is set in the next serial data status
byte. The same rising edge can act as a step input
to the analog channel, propagating through the digital filter to appear as a rising edge in the measurement data. By comparing the timing of the TB
status flag output and the rising edge in the measurement data, the measurement channel group delay can be determined.
DS639F363
19.GENERAL PURPOSE I/O
Figure 38. GPIO Block Diagram
GPIO
GP_DIR
GP_DATA
GP_PULL
Pull Up
Logic
R
CS5378
The General Purpose I/O (GPIO) block provides 8
general purpose pins to interface with external
hardware.
19.1 Pin Descriptions
GPIO[3:0] - Pins 4 - 1
Standard GPIO pins.
GPIO[6:4]:PLL[2:0] - Pins 7 - 5
Standard GPIO pins also used to select the PLL
mode after reset. Internal pull-ups default high,
10 kΩ external pull-downs required to set low.
GPIO7:BOOT - Pin 28
Standard GPIO pin also used to select boot mode
after reset. Internal pull-up defaults high, 10 kΩ external pull-down required to set low.
19.2 GPIO Architecture
Each GPIO pin can be configured as input or output, high or low, with a weak (~100 kΩ) internal
pull-up resistor enabled or disabled. Figure 38
shows the structure of a bi-directional GPIO pin.
19.3 GPIO Registers
GPIO pin settings are programmed in the GPCFG
register. GP_DIR bits set the input/output mode,
GP_PULL bits enable/disable the internal pull-up
resistor, and GP_DATA bits set the output data value. After reset, GPIO pins default as inputs with
pull-up resistors enabled.
19.4 GPIO Input Mode
When reading a value from the GP_DATA bits, the
returned data reports the current state of the pins. If
a pin is externally driven high it reads a logical 1, if
externally driven low it reads a logical 0. When a
GPIO pin is used as an input, the pull-up resistor
should be disabled to save power if it isn’t required.
19.5 GPIO Output Mode
When a GPIO pin is programmed as an output with
a data value of 0, the pin is driven low and the internal pull-up resistor is automatically disabled.
When programmed as an output with a data value
of 1, the pin is driven high and the pull-up resistor
is inconsequential.
Any GPIO pin can be used as an open-drain output
by setting the data value to 0, enabling the pull-up,
and using the GP_DIR direction bits to control the
pin value. This open-drain output configuration
uses the internal pull-up resistor to hold the pin
high when GP_DIR is set as an input, and drives the
pin low when GP_DIR is set as an output.
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CS5378
19.5.1 GPIO Reads in Output Mode
When reading GPIO pins the GP_DATA register
value always reports the current state of the pins, so
a value written in output mode does not necessarily
read back the same value. If a pin in output mode is
written as a logical 1, the CS5378 attempts to drive
the pin high. If an external device forces the pin
low, the read value reflects the pin state and returns
a logical 0. Similarly, if an output pin is written as
a logical 0 but forced high externally, the read value reflects the pin state and returns a logical 1. In
both cases the CS5378 is in contention with the external device resulting in increased power consumption.
DS639F365
20.REGISTER SUMMARY
20.1 SPI Registers
The CS5378 SPI registers interface the serial port to the digital filter.
NameAddr.Type# BitsDescription
SPICTRLH00R/W8SPI Control Register, High Byte
SPICTRLM01R/W8SPI Control Register, Middle Byte
SPICTRLL02R/W8SPI Control Register, Low Byte
SPICMDH03R/W8SPI Command, High Byte
SPICMDM04R /W8SPI Command, Middle Byte
SPICMDL05R/W8SPI Command, Low Byte
SPIDAT1H06R/W8SPI Data 1, High Byte
SPIDAT1M07R/W8SPI Data 1, Middle Byte
SPIDAT1L08R/W8SPI Data 1, Low Byte
SPIDAT2H09R/W8SPI Data 2, High Byte
SPIDAT2M0AR/W8SPI Data 2, Middle Byte
SPIDAT2L0BR/W8SPI Data 2, Low Byte
The CS5378 digital filter registers control hardware peripherals and filtering functions.
NameAddr.Type# BitsDescription
CONFIG00R/W24Hardware Configuration
RESERVED01-0DR/W24Reserved
GPCFG0ER/W24GPIO[7:0] Direction, Pull-Up Enable, and Data
RESERVED0F-1FR/W24Reserved
FILTCFG20R/W24Digital Filter Configuration
GAIN21R/W24Gain Correction
RESERVED22-24R/W24Reserved
OFFSET25R/W24Offset Correction
RESERVED26-28R/W24Reserved
TIMEBRK29R/W24Time Break Delay
TBSCFG2AR/W24Test Bit Stream Configuration
TBSGAIN2BR/W24Test Bit Stream Gain
SYSTEM12CR/W24User Defined System Register 1
SYSTEM22DR/W24User Defined System Register 2
VERSION2ER/W24Hardware Version ID
SELFTEST2FR/W24Self-Test Result Code
CS5378
DS639F371
20.2.1CONFIG : 0x00
(MSB)2322212019181716
----------DFS2DFS1DFS0
R/WR/WR/WR/WR/WR/WR/WR/W
00000101
15141312111098
----------MCKFS2MCKFS1MCKFS0
R/WR/WR/WR/WR/WR/WR/WR/W
00000100
7654321(LSB)0
STAT----MCKENMDIFS--BOOTMSEN
R/WR/WR/WR/WR/WR/WRR/W
00000001
Figure 43. Hardware Configuration Register CONFIG
Bit definitions:
23:19 - -reserved15:11 --reserved7:6STATSerial Data Status Byte
24.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model NumberPeak Reflow TempMSL Rating*Max Floor Life
CS5378-ISZ (Lead Free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
260 °C37 Days
CS5378
DS639F386
25.REVISION HISTORY
RevisionDateChanges
PP1FEB 2004Initial “Preliminary Product” release.
F1OCT 2005Added lead-free device ordering information. Added MSL data.
F2SEP 2008Rev B. Update Single-S part numbers. Remove TBS impulse mode.
OCT 2010Removed lead-containing device
F3
ordering information.
CS5378
DS639F387
CS5378
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. I F THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND AL L LIABILITY, INCLUDING
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
DS639F388
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