VA+ = +5 V; VA- = 0 V;VD = +3.3 V to +5 V
VA+ = +2.5 V;VA- = -2.5 V;VD = +3.3 V
Fully Differential
pp
∆Σ
Modulators
Description
The CS5371 and CS5372 are one- and two-channel,
high dynamic range, fourth-order ∆Σ modulators intended for geophysical and sonar applications. Used in
combination with the CS5376A or CS5378 digital filters,
a unique high-resolution A/D measurement system
results.
The CS5371 and CS5372 have high dynamic range
(127 dB @ 215 Hz bandwidth) and low total harmonic
distortion (typically -118 dB THD), with very low power
consumption per channel. In normal mode
(LPWR=0, MCLK=2.048MHz), power consumption is
25 mW per channel, and in low-power mode
(LPWR=1, MCLK=1.024MHz), power consumption is
15 mW per channel. Each modulator can be independently powered down to 1 mW per channel, and by
halting the input clock, they will enter a micropower state
using only 10 µW per channel.
The modulators generate an oversampled serial bit
stream at 512 kbits per second when operated from a
clock frequency of 2.048 MHz. They are available in a
small 24-pin SSOP package, providing exceptional performance in a very small footprint.
Channel to Channel Gain Variation (Note 3)CGV-1-%
Full-scale Drift(Notes 3 and 4)TC
Offset(Note 3)V
FS
ZSE
-5-ppm/C
-1-mV
Offset after Calibration(Note 5)-±1-µV
Offset Calibration Range(Note 6)-100-%F.S.
Offset Drift(Notes 3 and 4)TC
ZSE
-1-µV/C
Notes: 1. Dynamic Range defined as 20 log [ (RMS full scale) / (RMS idle noise) ]
2. Tested with full-scale input signal of 31.25 Hz; OWR = 1000 SPS; OFST = 1.
3. Specification is for the parameter over the specified temperature range for the CS5371/72 devices only
and does not include the effects of external components.
4. Specifications are guaranteed by design and/or characterization.
5. The offset after calibration specification applies to the effective offset voltage for a full-scale input to the
CS5371/72 modulator, but is measured from the output digital codes from the digital filter.
6. The CS5371/72 offset calibration is performed digitally and includes the full-scale range.
DS255F33
CS5371 CS5372
ANALOG CHARACTERISTICS (Continued)
ParameterSymbol Min TypMaxUnit
Specified Temperature RangeT
Input Characteristics
Input Signal Frequencies(Note 7)BWDC-1720Hz
Input Voltage Range(Note 8)VIN--5V
Input Over-range Voltage Tolerance(Note 8)I
Input Signal plus Common Mode(VA-)
Common Mode Rejection RatioCMRR-90-dB
Channel Crosstalk (CS5372 only)CXT--120-dB
Voltage Reference Input
VREF(VREF+) - (VREF-)-2.5-V
VREF Current--120µA
Power Supplies
DC Power Supply Currents(Note 9 and 10)
LPWR = 0; MCLK = 2.048 MHzAnalog
Digital
LPWR = 1; MCLK = 1.024 MHzAnalog
Digital
Power Down Modes
CS5371PWDN = 1
PWDN = 1, MCLK = 0
A
OVR
VA
VD
VA
VD
P
D
-40-+85C
5--%F.S.
-(VA+)
+ 0.7V
-
-
-
-
-
-
5.0
0.2
3.0
0.2
1
10
- 1.7V
7.0
0.3
4.5
0.3
-
-
mA
mA
mA
mA
mW
µW
p-p
V
CS5372PWDN1 or PWDN2 = 1
PWDN1 = PWDN2 = 1
PWDN1 = PWDN2 = 1, MCLK = 0
Power Supply Rejection(Note 11)PSRR-90-dB
Notes: 7. The upper bandwidth limit is determined by the digital filter. A simple single pole anti-alias filter with a -
3 dB frequency at (MCLK / 256) should be placed in front of each channel.
8. The input voltage range is for the configuration depicted in Figure 3, the System Connection Diagram,
and applies to signal frequencies from DC to the stop-band frequency selected in the digital filter.
9. Per channel. All outputs unloaded. All digital inputs forced to VD or GND respectively.
10. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the
oversampled signal bandwidth by a factor of 2.
11. Tested with a 50 Hz 100 mVpp sine wave applied separately to each supply.
-
-
-
25
1
10
-
-
-
mW
mW
µW
4DS255F3
CS5371 CS5372
DIGITAL CHARACTERISTICS Notes:T
= 25 C; VA+ = 5V or 2.5V ±5%; VA- = 0V or -2.5V ±5%;
A
VD = 5V or 3.3V ± 5%; DGND = 0V; All voltages with respect to DGND.
ParameterSymbol Min TypMaxUnit
High-level Input VoltageV
Low-level Input VoltageV
High-level Output VoltageI
Low-level Output VoltageI
= -5.0 mAV
out
= 5.0 mAV
out
Input Leakage CurrentI
3-state Leakage CurrentI
Digital Output Pin CapacitanceC
IH
IL
OH
OL
in
OZ
out
0.6 * VD-VDV
0.0-0.8V
(VD) - 1.0--V
--0.4V
-±1±10µA
--±10µA
-9-pF
ABSOLUTE MAXIMUM RATINGS Notes:DGND = 0 V
ParameterSymbol Min TypMaxUnit
DC Power Supplies (Notes 12 and 13) Positive Digital
Positive Analog
Negative Analog
Input Current, Any Pin Except Supplies(Note 14 and 15)I
Input Current, Supplies(Note 15)I
Output CurrentI
Power Dissipation(Note 16)PDN--500mW
Analog Input VoltageAll Analog PinsV
Digital Input VoltageAll Digital PinsV
Ambient Operating TemperatureT
Storage TemperatureT
VD
VA+
VA-
IN
IN
OUT
INA
IND
A
stg
-0.3
-0.3
-3.3
-
-
-
+6.0
+6.0
+0.3
--±10mA
--±50mA
--±25mA
(VA-) - 0.5-(VA+) + 0.5V
-0.5-(VD) + 0.5V
-40-85°C
-65-150°C
V
V
V
Notes: 12. VA+ and VA- must satisfy {(VA+) - (VA-)} < +6.8 V.
13. VD and VA- must satisfy {(VD) - (VA-)} < +7.6 V.
14. Includes continuous over-voltage conditions at the analog input (AIN) pins.
15. Transient current of up to 100 mA can be safely tolerated without SCR latch-up.
16. Total power dissipation, including all input and output currents.
DS255F35
CS5371 CS5372
SWITCHING CHARACTERISTICS Notes:T
= 0V or -2.5V ± 5%; VD = +5V or +3.3V ± 5%; Digital Inputs: Logic 0 = 0V, Logic 1 = VD; C
= -40 C to +85 C; VA+ = +5V or +2.5V ± 5%; VA-
A
=50pF
L
ParameterSymbol Min TypMaxUnit
MCLK Frequency(Note 17)f
c
0.12.0482.2MHz
MCLK Duty Cycle40-60%
MCLK Jitter (In-band or aliased in-band)--300ps
MCLK Jitter (Out-of-band)--1ns
Rise Times:Any Digital Input(Note 18)
Any Digital Output
Fall Times:Any Digital Input(Note 18)
Any Digital Output
MSYNC Setup Time to MCLK falling(Note 19)t
MSYNC Hold Time after MCLK fallingt
MCLK rising to Valid MFLAGt
MCLK rising to Valid MDATAt
t
risein
t
riseout
t
fallin
t
fallout
mss
msh
mfh
mdv
-
-
-
-
50
50
-
50
100
-
50
100
20--ns
20--ns
-3565ns
-6090ns
Notes: 17. If MCLK is removed, the CS5372 enters a micro power state.
18. Excludes MCLK input, MCLK should be driven with a signal having rise/fall times of 25 ns or faster.
19. MSYNC latched on MCLK falling edge, data output on next MCLK rising edge.
ns
ns
ns
ns
MCLK
t
mss
MSYNC
MDATA
MFLAG
t
risein
t
t
fallin
mdv
0.9 * VD
0.1 * VD
Figure 1. Rise and Fall Times
t
msh
VALID DATA
t
riseout
t
mdv
t
mfh
VALID DATA
t
fallout
0.9 * VD
0.1 * VD
Figure 2. CS5372 Interface Timing
6DS255F3
CS5371 CS5372
2. GENERAL DESCRIPTION.
The CS5371 and CS5372 are one- and two- channel fourth-order ∆Σ modulators, optimized for extremely high-resolution measurement of signals
between DC and 1600 Hz. They are designed to
be used with the CS5376A and CS5378 low-power
digital filters. Figure 3 on page 8 shows a fourchannel system connection diagram for two
CS5372 and one CS5376A.
High Performance
The CS5371/72 modulators have exceptional performance characteristics. Modulator dynamic
range (SNR) is 127 dB over a 215 Hz bandwidth
(2 ms sampling), with total harmonic distortion
(THD) of -118 dB.
Low Power Consumption
The CS5371/72 modulators have very low power
consumption. Power consumption is only 25 mW
per channel in normal mode (LPWR=0,
MCLK=2.048 MHz), and 15 mW per channel in low
power mode (LPWR=1, MCLK=1.024 MHz).
An independently selectable power-down mode
(PWDN=1) can be used to disable a modulator and
reduces its power consumption to 1 mW. If MCLK
is then halted (MCLK=0), the modulator enters a
micropower state using only 10
µW per channel.
Small Package Size
The CS5371/72 modulators are available in a very
small 24-pin SSOP package approximately
8 mm x 8 mm in size. The CS5372 has two modulator channels per package to increase board layout density even further.
Multi-channel System Support
Combining the CS5371 and CS5372 modulators
with a digital filter permits multiple system configurations:
1 Channel - CS5371, CS5378
2 Channel - CS5372, CS5376A
3 Channel - CS5371, CS5372, CS5376A
4 Channel - CS5372, CS5372, CS5376A
Differential Analog Signal Inputs
The CS5371/72 modulators have fully differential
analog inputs capable of measuring signals up to
5.0 V peak-to-peak when using a 2.5 V voltage reference. The inputs will tolerate a 5% over-range
voltage and continue operating at full specification.
Digital Filter Interface
The CS5371/72 modulators are designed to operate with the CS5376A and CS5378 digital filters.
The digital filter generates the modulator clock and
synchronization signal inputs (MCLK and
MSYNC), while receiving the modulator data and
over-range flag outputs (MDATA and MFLAG).
The modulators produce an oversampled ∆Σ serial
bit stream at 512 kbits per second when operated
from a 2.048 MHz modulator clock.
Multiple Power Supply Configurations
The CS5371/72 modulators support flexible power
supply configurations. They can run from single or
dual supplies in the following configurations: