Cirrus Logic CS5372 User Manual

CS5371 CS5372
Low-power, High-performance

Features & Description

127 dB SNR @ 215 Hz BW (2 ms Output)124 dB SNR @ 430 Hz BW (1 ms Output)
z Low Total Harmonic Distortion
-118 dB THD Typical, -112 dB THD Maximum
z Low Power Consumption
Normal Mode: 25 mW per ChannelLow-power Mode: 15 mW per Channel
z Small Footprint, 24-pin SSOP Package z Single- or Multi-channel System Support
1-channel System: CS53712-channel System: CS53723-channel System: CS5371 + CS53724-channel System: CS5372 + CS5372
z Single or Dual Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD = +3.3 V to +5 VVA+ = +2.5 V;VA- = -2.5 V;VD = +3.3 V
Fully Differential
pp
∆Σ
Modulators
Description
The CS5371 and CS5372 are one- and two-channel, high dynamic range, fourth-order ∆Σ modulators intend­ed for geophysical and sonar applications. Used in combination with the CS5376A or CS5378 digital filters, a unique high-resolution A/D measurement system results.
The CS5371 and CS5372 have high dynamic range (127 dB @ 215 Hz bandwidth) and low total harmonic distortion (typically -118 dB THD), with very low power consumption per channel. In normal mode (LPWR=0, MCLK=2.048MHz), power consumption is 25 mW per channel, and in low-power mode (LPWR=1, MCLK=1.024MHz), power consumption is 15 mW per channel. Each modulator can be indepen­dently powered down to 1 mW per channel, and by halting the input clock, they will enter a micropower state using only 10 µW per channel.
The modulators generate an oversampled serial bit stream at 512 kbits per second when operated from a clock frequency of 2.048 MHz. They are available in a small 24-pin SSOP package, providing exceptional per­formance in a very small footprint.
ORDERING INFORMATION
See page 21.
VA+
INF+ INR+
INR­INF-
VREF+
VREF-
4TH ORDER
∆−Σ
MODULATOR
CS5371
VA-
http://www.cirrus.com
PWDN
OFST LPWR DGND
VD
MFLAG
MDATA
CLOCK
GENERATOR
Copyright © Cirrus Logic, Inc. 2005
MCLK MSYNC
(All Rights Reserved)
INF1+ INR1+
INR1­INF1-
VREF+
VREF-
INF2+ INR2+
INR2­INF2-
VA+
VA-
4TH ORDER
∆−Σ
MODULATOR
4TH ORDER
∆−Σ
MODULATOR
PWDN1
PWDN2
OFST LPWR DGND
VD
CLOCK
GENERATOR
CS5372
MFLAG1
MDATA1
MCLK MSYNC
MFLAG2
MDATA2
OCT ‘05
DS255F3
TABLE OF CONTENTS
1. CHARACTERISTICS & SPECIFICATIONS ................................................... 3
ANALOG CHARACTERISTICS .................................................................. 3
DIGITAL CHARACTERISTICS ................................................................... 5
ABSOLUTE MAXIMUM RATINGS ............................................................. 5
SWITCHING CHARACTERISTICS ............................................................ 6
2. GENERAL DESCRIPTION. ........................................................................... 7
3. MODULATOR PERFORMANCE ................................................................... 9
3.1. Full-scale Signal Performance ........................................................... 9
3.2. Noise Performance ............................................................................ 9
4. SIGNAL INPUTS ........................................................................................... 9
4.1. Differential Inputs - INR+/-, INF+/- ..................................................... 9
4.2. Anti-alias Filters ............................................................................... 10
4.3. Input Impedance .............................................................................. 10
4.4. Maximum Signal Levels ................................................................... 10
5. INPUT OFFSET ........................................................................................... 10
5.1. Offset Enable - OFST ...................................................................... 11
5.2. Offset Drift........................................................................................ 11
6. VOLTAGE REFERENCE INPUTS .............................................................. 11
6.1. Voltage Reference Configurations ................................................... 12
6.2. VREF Input Impedance.................................................................... 12
6.3. Gain Accuracy.................................................................................. 12
6.4. Gain Drift.......................................................................................... 12
7. DIGITAL FILTER INTERFACE ................................................................... 12
7.1. Modulator Clock - MCLK.................................................................. 13
7.2. Modulator Data - MDATA................................................................. 13
7.3. Modulator Sync - MSYNC................................................................ 13
7.4. Modulator Flag - MFLAG ................................................................. 13
8. POWER MODES ......................................................................................... 14
8.1. Normal Power Mode ........................................................................ 14
8.2. Low Power Mode - LPWR................................................................ 14
8.3. Power Down Mode - PWDN ............................................................ 14
8.4. Micro-power Mode ........................................................................... 14
9. POWER SUPPLY ........................................................................................ 14
9.1. Power Supply Configurations........................................................... 14
9.2. Power Supply Bypassing ................................................................. 14
9.3. SCR Latch-up Considerations ......................................................... 15
9.4. DC-DC Converter Considerations.................................................... 15
9.5. Power Supply Rejection................................................................... 15
10. PIN DESCRIPTION - CS5371 ..................................................................... 16
11. PIN DESCRIPTION - CS5372 ..................................................................... 18
12. PACKAGE DIMENSIONS ............................................................................ 20
13. ORDERING INFORMATION ....................................................................... 21
14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION.. 21
15. REVISION HISTORY ................................................................................... 21
CS5371 CS5372
2 DS255F3

1. CHARACTERISTICS & SPECIFICATIONS

CS5371 CS5372

ANALOG CHARACTERISTICS Notes:T

= -40 C to +85 C; VA+ = 5V or 2.5V ± 5%; VA - = 0V or
A
-2.5V ± 5%; VD = 5V or 3.3V ± 5%; DGND = 0V; MCLK = 2.048 MHz; [(VREF+) - (VREF-)] = 2.5V; Devices are connected as shown in Figure 3, the System Connection Diagram.
CS5371-BS / CS5372-BS
Parameter Symbol
Specified Temperature Range T
A
-40 - +85 C
UnitMin Typ Max
Dynamic Performance
Dynamic Range (Note 1) LPWR = 0 0 Hz to 1720 Hz MCLK = 2.048 MHz 0 Hz to 860 Hz
0 Hz to 430 Hz
0 Hz to 215 Hz 0 Hz to 107.5 Hz 0 Hz to 53.75 Hz
0 Hz to 26.875 Hz
Dynamic Range (Note 1) LPWR = 1 0 Hz to 1720 Hz MCLK = 1.024 MHz 0 Hz to 860 Hz
0 Hz to 430 Hz
0 Hz to 215 Hz 0 Hz to 107.5 Hz 0 Hz to 53.75 Hz
0 Hz to 26.875 Hz
Total Harmonic Distortion (Note 2)
SNR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SNR
LP
-
-
121
-
-
-
-
-
-
118
-
-
-
-
109 121 124 127 130 133 136
106 118 121 124 127 130 133
THD - -118 -112 dB
dB dB dB dB dB dB dB
dB dB dB dB dB dB dB
LPWR = 0; MCLK = 2.048 MHz Total Harmonic Distortion (Note 2)
THD
LP
--114-108dB
LPWR = 1; MCLK = 1.024 MHz
DC Accuracy
Channel to Channel Gain Variation (Note 3) CGV - 1 - % Full-scale Drift (Notes 3 and 4) TC Offset (Note 3) V
FS
ZSE
-5-ppm/C
-1-mV Offset after Calibration (Note 5) - ±1 - µV Offset Calibration Range (Note 6) - 100 - %F.S. Offset Drift (Notes 3 and 4) TC
ZSE
-1-µV/C
Notes: 1. Dynamic Range defined as 20 log [ (RMS full scale) / (RMS idle noise) ]
2. Tested with full-scale input signal of 31.25 Hz; OWR = 1000 SPS; OFST = 1.
3. Specification is for the parameter over the specified temperature range for the CS5371/72 devices only and does not include the effects of external components.
4. Specifications are guaranteed by design and/or characterization.
5. The offset after calibration specification applies to the effective offset voltage for a full-scale input to the CS5371/72 modulator, but is measured from the output digital codes from the digital filter.
6. The CS5371/72 offset calibration is performed digitally and includes the full-scale range.
DS255F3 3
CS5371 CS5372
ANALOG CHARACTERISTICS (Continued)
Parameter Symbol Min Typ Max Unit
Specified Temperature Range T
Input Characteristics
Input Signal Frequencies (Note 7) BW DC - 1720 Hz
Input Voltage Range (Note 8) VIN - - 5 V
Input Over-range Voltage Tolerance (Note 8) I
Input Signal plus Common Mode (VA-)
Common Mode Rejection Ratio CMRR - 90 - dB
Channel Crosstalk (CS5372 only) CXT - -120 - dB
Voltage Reference Input
VREF (VREF+) - (VREF-) - 2.5 - V
VREF Current - - 120 µA
Power Supplies
DC Power Supply Currents (Note 9 and 10) LPWR = 0; MCLK = 2.048 MHz Analog
Digital
LPWR = 1; MCLK = 1.024 MHz Analog
Digital
Power Down Modes CS5371 PWDN = 1
PWDN = 1, MCLK = 0
A
OVR
VA
VD
VA
VD
P
D
-40 - +85 C
5--%F.S.
-(VA+)
+ 0.7V
-
-
-
-
-
-
5.0
0.2
3.0
0.2
1
10
- 1.7V
7.0
0.3
4.5
0.3
-
-
mA mA mA mA
mW
µW
p-p
V
CS5372 PWDN1 or PWDN2 = 1
PWDN1 = PWDN2 = 1
PWDN1 = PWDN2 = 1, MCLK = 0
Power Supply Rejection (Note 11) PSRR - 90 - dB
Notes: 7. The upper bandwidth limit is determined by the digital filter. A simple single pole anti-alias filter with a -
3 dB frequency at (MCLK / 256) should be placed in front of each channel.
8. The input voltage range is for the configuration depicted in Figure 3, the System Connection Diagram, and applies to signal frequencies from DC to the stop-band frequency selected in the digital filter.
9. Per channel. All outputs unloaded. All digital inputs forced to VD or GND respectively.
10. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the oversampled signal bandwidth by a factor of 2.
11. Tested with a 50 Hz 100 mVpp sine wave applied separately to each supply.
-
-
-
25
1
10
-
-
-
mW mW
µW
4 DS255F3
CS5371 CS5372

DIGITAL CHARACTERISTICS Notes:T

= 25 C; VA+ = 5V or 2.5V ±5%; VA- = 0V or -2.5V ±5%;
A
VD = 5V or 3.3V ± 5%; DGND = 0V; All voltages with respect to DGND.
Parameter Symbol Min Typ Max Unit
High-level Input Voltage V
Low-level Input Voltage V
High-level Output Voltage I
Low-level Output Voltage I
= -5.0 mA V
out
= 5.0 mA V
out
Input Leakage Current I
3-state Leakage Current I
Digital Output Pin Capacitance C
IH
IL
OH
OL
in
OZ
out
0.6 * VD - VD V
0.0 - 0.8 V
(VD) - 1.0 - - V
--0.4V
1±10µA
--±10µA
-9-pF

ABSOLUTE MAXIMUM RATINGS Notes:DGND = 0 V

Parameter Symbol Min Typ Max Unit
DC Power Supplies (Notes 12 and 13) Positive Digital
Positive Analog
Negative Analog
Input Current, Any Pin Except Supplies (Note 14 and 15) I
Input Current, Supplies (Note 15) I
Output Current I
Power Dissipation (Note 16) PDN - - 500 mW
Analog Input Voltage All Analog Pins V
Digital Input Voltage All Digital Pins V
Ambient Operating Temperature T
Storage Temperature T
VD
VA+
VA-
IN
IN
OUT
INA
IND
A
stg
-0.3
-0.3
-3.3
-
-
-
+6.0 +6.0 +0.3
--±10mA
--±50mA
--±25mA
(VA-) - 0.5 - (VA+) + 0.5 V
-0.5 - (VD) + 0.5 V
-40 - 85 °C
-65 - 150 °C
V V V
Notes: 12. VA+ and VA- must satisfy {(VA+) - (VA-)} < +6.8 V.
13. VD and VA- must satisfy {(VD) - (VA-)} < +7.6 V.
14. Includes continuous over-voltage conditions at the analog input (AIN) pins.
15. Transient current of up to 100 mA can be safely tolerated without SCR latch-up.
16. Total power dissipation, including all input and output currents.
DS255F3 5
CS5371 CS5372

SWITCHING CHARACTERISTICS Notes:T

= 0V or -2.5V ± 5%; VD = +5V or +3.3V ± 5%; Digital Inputs: Logic 0 = 0V, Logic 1 = VD; C
= -40 C to +85 C; VA+ = +5V or +2.5V ± 5%; VA-
A
=50pF
L
Parameter Symbol Min Typ Max Unit
MCLK Frequency (Note 17) f
c
0.1 2.048 2.2 MHz
MCLK Duty Cycle 40 - 60 %
MCLK Jitter (In-band or aliased in-band) - - 300 ps
MCLK Jitter (Out-of-band) - - 1 ns
Rise Times: Any Digital Input (Note 18)
Any Digital Output
Fall Times: Any Digital Input (Note 18)
Any Digital Output
MSYNC Setup Time to MCLK falling (Note 19) t
MSYNC Hold Time after MCLK falling t
MCLK rising to Valid MFLAG t
MCLK rising to Valid MDATA t
t
risein
t
riseout
t
fallin
t
fallout
mss
msh
mfh
mdv
-
-
-
-
50
50
-
50
100
-
50
100
20 - - ns
20 - - ns
-3565ns
-6090ns
Notes: 17. If MCLK is removed, the CS5372 enters a micro power state.
18. Excludes MCLK input, MCLK should be driven with a signal having rise/fall times of 25 ns or faster.
19. MSYNC latched on MCLK falling edge, data output on next MCLK rising edge.
ns ns
ns ns
MCLK
t
mss
MSYNC
MDATA
MFLAG
t
risein
t
t
fallin
mdv
0.9 * VD
0.1 * VD
Figure 1. Rise and Fall Times
t
msh
VALID DATA
t
riseout
t
mdv
t
mfh
VALID DATA
t
fallout
0.9 * VD
0.1 * VD
Figure 2. CS5372 Interface Timing
6 DS255F3
CS5371 CS5372

2. GENERAL DESCRIPTION.

The CS5371 and CS5372 are one- and two- chan­nel fourth-order ∆Σ modulators, optimized for ex­tremely high-resolution measurement of signals between DC and 1600 Hz. They are designed to be used with the CS5376A and CS5378 low-power digital filters. Figure 3 on page 8 shows a four­channel system connection diagram for two CS5372 and one CS5376A.
High Performance
The CS5371/72 modulators have exceptional per­formance characteristics. Modulator dynamic range (SNR) is 127 dB over a 215 Hz bandwidth (2 ms sampling), with total harmonic distortion (THD) of -118 dB.
Low Power Consumption
The CS5371/72 modulators have very low power consumption. Power consumption is only 25 mW per channel in normal mode (LPWR=0, MCLK=2.048 MHz), and 15 mW per channel in low power mode (LPWR=1, MCLK=1.024 MHz).
An independently selectable power-down mode (PWDN=1) can be used to disable a modulator and reduces its power consumption to 1 mW. If MCLK is then halted (MCLK=0), the modulator enters a micropower state using only 10
µW per channel.
Small Package Size
The CS5371/72 modulators are available in a very small 24-pin SSOP package approximately 8 mm x 8 mm in size. The CS5372 has two mod­ulator channels per package to increase board lay­out density even further.
Multi-channel System Support
Combining the CS5371 and CS5372 modulators with a digital filter permits multiple system configu­rations:
1 Channel - CS5371, CS5378
2 Channel - CS5372, CS5376A
3 Channel - CS5371, CS5372, CS5376A
4 Channel - CS5372, CS5372, CS5376A
Differential Analog Signal Inputs
The CS5371/72 modulators have fully differential analog inputs capable of measuring signals up to
5.0 V peak-to-peak when using a 2.5 V voltage ref­erence. The inputs will tolerate a 5% over-range voltage and continue operating at full specification.
Digital Filter Interface
The CS5371/72 modulators are designed to oper­ate with the CS5376A and CS5378 digital filters. The digital filter generates the modulator clock and synchronization signal inputs (MCLK and MSYNC), while receiving the modulator data and over-range flag outputs (MDATA and MFLAG). The modulators produce an oversampled ∆Σ serial bit stream at 512 kbits per second when operated from a 2.048 MHz modulator clock.
Multiple Power Supply Configurations
The CS5371/72 modulators support flexible power supply configurations. They can run from single or dual supplies in the following configurations:
VA+ = +5V; VA- = 0V; VD = +3.3V to +5VVA+ = +2.5V; VA- = -2.5V; VD = +3.3V
DS255F3 7
Loading...
+ 15 hidden pages