How it Works
Cirrus Logic
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CS5366
User Manual
42 pgs737.74 Kb0
Table of contents
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Cirrus Logic CS5366 User Manual

Features
Digital
Audio
Voltage
Reference
Level
Translator
Level
Translator
Internal
Oscillator
VD
3.3 - 5V
Control Interface
I2C, SPI
or Pins
Configuration
Registers
VA 5V
VLC
1.8 - 5V
VLS
1.8 - 5V
6 Differential
Analog Inputs
Device Control
Decimation
Filter
High Pass
Filter
Multi-bit
 ADC
Serial
Audio Out
PCM or
TDM
CS5366
114 dB, 192 kHz, 6-Channel A/D Converter
Advanced Multi-bit Delta-Sigma Architecture
24-Bit Conversion
114 dB Dynamic Range
Supports Audio Sample Rates up to 216 kHz
Selectable Audio Interface Formats
– Left-Justified, I²S, TDM
– 6-Channel TDM Interface Formats
Low Latency Digital Filter
Less than 535 mW Power Consumption
On-Chip Oscillator Driver
Operation as System Clock Master or Slave
Auto-Detect Speed in Slave Mode
Differential Analog Architecture
Separate 1.8 V to 5 V Logic Supplies for
Control and Serial Ports
High-Pass Filter for DC Offset Calibration
Overflow Detection
Footprint Compatible with the 8-Channel
CS5368
Additional Control Port Features
Supports I²C or SPI™ Control Interface per
specifications on page 17 and page 18
Individual Channel HPF Disable
Overflow Detection for Individual Channels
Mute Control for Individual Channels
Independent Power-Down Control per Channel
Pair
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2014
(All Rights Reserved)
JUL '14
DS626F5
CS5366
Description
The CS5366 is a complete 6-channel analog-to-digital converter for digital audio systems. It performs sampling, an­alog-to-digital conversion, and anti-alias filtering, generating 24-bit values for all 6-channel inputs in serial form at sample rates up to 216 kHz per channel.
The CS5366 uses a 5th-order, multi-bit delta sigma modulator followed by low latency digital filtering and decima­tion, which removes the need for an external anti-aliasing filter. The ADC uses a differential input architecture which provides excellent noise rejection.
Dedicated level translators for the Serial Port and Control Port allow seamless interfacing between the CS5366 and other devices operating over a wide range of logic levels. In addition, an on-chip oscillator driver provides clocking flexibility and simplifies design.
The CS5366 is the industry’s first audio A/D to support a high-speed TDM interface which provides a serial output of 6 channels of audio data with sample rates up to 216 kHz within a single data stream. It further reduces layout complexity and relieves input/output constraints in digital signal processors.
The CS5366 is available in a 48-pin LQFP package in both Commercial (-40°C to 85°C) and Automotive grades (-40°C to +105°C). The CDB5366 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering Information” on page 41 for complete ordering information.
The CS5366 is ideal for high-end and pro-audio systems requiring unrivaled sound quality, transparent conversion, wide dynamic range and negligible distortion, such as A/V receivers, digital mixing consoles, multi-channel record­ers, outboard converters, digital effect processors, and automotive audio systems.
2 DS626F5
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 6
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 9
3. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 10
RECOMMENDED OPERATING CONDITIONS ................................................................................. 10
ABSOLUTE RATINGS ....................................................................................................................... 10
SYSTEM CLOCKING ......................................................................................................................... 10
DC POWER ........................................................................................................................................ 11
LOGIC LEVELS ................................................................................................................................. 11
PSRR, VQ AND FILT+ CHARACTERISTICS .................................................................................... 11
ANALOG CHARACTERISTICS (COMMERCIAL) .............................................................................. 12
ANALOG PERFORMANCE (AUTOMOTIVE) ..................................................................................... 13
DIGITAL FILTER CHARACTERISTICS ............................................................................................. 14
OVERFLOW TIMEOUT ...................................................................................................................... 14
SERIAL AUDIO INTERFACE - I²S/LJ TIMING ................................................................................... 15
SERIAL AUDIO INTERFACE - TDM TIMING ..................................................................................... 16
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING ................................................... 17
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING .................................................. 18
4. APPLICATIONS ................................................................................................................................... 19
4.1 Power ............................................................................................................................................. 19
4.2 Control Port Mode and Stand-Alone Operation .............................................................................. 19
4.2.1 Stand-Alone Mode ................................................................................................................. 19
4.2.2 Control Port Mode ................................................................................................................. 19
4.3 Master Clock Source ...................................................................................................................... 20
4.3.1 On-Chip Crystal Oscillator Driver .......................................................................................... 20
4.3.2 Externally Generated Master Clock ....................................................................................... 20
4.4 Master and Slave Operation ........................................................................................................... 21
4.4.1 Synchronization of Multiple Devices ......................................................................................21
4.5 Serial Audio Interface (SAI) Format ................................................................................................ 22
4.5.1 I²S and LJ Format .................................................................................................................. 22
4.5.2 TDM Format .......................................................................................................................... 23
4.5.3 Configuring Serial Audio Interface Format ............................................................................ 23
4.6 Speed Modes ................................................................................................................................. 23
4.6.1 Sample Rate Ranges ............................................................................................................ 23
4.6.2 Using M1 and M0 to Set Sampling Parameters .................................................................... 23
4.6.3 Master Mode Clock Dividers ................................................................................................. 24
4.6.4 Slave Mode Audio Clocking With Auto-Detect ...................................................................... 24
4.7 Master and Slave Clock Frequencies ............................................................................................. 25
4.8 Reset .............................................................................................................................................. 27
4.8.1 Power-Down Mode ................................................................................................................ 27
4.9 Overflow Detection ......................................................................................................................... 27
4.9.1 Overflow in Stand-Alone Mode .............................................................................................. 27
4.9.2 Overflow in Control Port Mode .............................................................................................. 27
4.10 Analog Connections ..................................................................................................................... 28
4.11 Optimizing Performance in TDM Mode ........................................................................................29
4.12 DC Offset Control ......................................................................................................................... 29
4.13 Control Port Operation .................................................................................................................. 30
4.13.1 SPI Mode ............................................................................................................................. 30
4.13.2 I²C Mode .............................................................................................................................. 31
5. REGISTER MAP ................................................................................................................................... 32
5.1 Register Quick Reference ............................................................................................................. 32
5.2 00h (REVI) Chip ID Code & Revision Register ............................................................................... 32
CS5366
DS626F5 3
5.3 01h (GCTL) Global Mode Control Register ...................................................................................32
5.4 02h (OVFL) Overflow Status Register ........................................................................................... 33
5.5 03h (OVFM) Overflow Mask Register ............................................................................................ 33
5.6 04h (HPF) High-Pass Filter Register ............................................................................................. 34
5.7 05h Reserved ................................................................................................................................ 34
5.8 06h (PDN) Power Down Register .................................................................................................. 34
5.9 07h Reserved ................................................................................................................................ 34
5.10 08h (MUTE) Mute Control Register .............................................................................................. 34
5.11 09h Reserved .............................................................................................................................. 35
5.12 0Ah (SDEN) SDOUT Enable Control Register ............................................................................ 35
6. FILTER PLOTS ..................................................................................................................................... 36
7. PARAMETER DEFINITIONS ................................................................................................................ 39
8. PACKAGE DIMENSIONS ................................................................................................................... 40
THERMAL CHARACTERISTICS .......................................................................................................40
9. ORDERING INFORMATION ................................................................................................................ 41
10. REVISION HISTORY ......................................................................................................................... 41
LIST OF FIGURES
Figure 1. CS5366 Pinout ............................................................................................................................. 6
Figure 2. Typical Connection Diagram ........................................................................................................ 9
Figure 3. I²S/LJ Timing .............................................................................................................................. 15
Figure 4. TDM Timing ............................................................................................................................... 16
Figure 5. I²C Timing .................................................................................................................................. 17
Figure 6. SPI Timing ................................................................................................................................. 18
Figure 7. Crystal Oscillator Topology ........................................................................................................ 20
Figure 8. Master/Slave Clock Flow ........................................................................................................... 21
Figure 9. Master and Slave Clocking for a Multi-Channel Application ...................................................... 21
Figure 10. I²S Format ................................................................................................................................ 22
Figure 11. LJ Format ................................................................................................................................. 22
Figure 12. TDM Format ............................................................................................................................. 23
Figure 13. Master Mode Clock Dividers .................................................................................................... 24
Figure 14. Slave Mode Auto-Detect Speed ............................................................................................... 24
Figure 15. Recommended Analog Input Buffer ......................................................................................... 28
Figure 16. SPI Format ............................................................................................................................... 30
Figure 17. I²C Write Format ...................................................................................................................... 31
Figure 18. I²C Read Format ...................................................................................................................... 31
Figure 19. SSM Passband ........................................................................................................................ 36
Figure 20. DSM Passband ........................................................................................................................ 36
Figure 21. QSM Passband ........................................................................................................................ 36
Figure 22. SSM Stopband ......................................................................................................................... 37
Figure 23. DSM Stopband ......................................................................................................................... 37
Figure 24. QSM Stopband ........................................................................................................................ 37
Figure 25. SSM -1 dB Cutoff ..................................................................................................................... 38
Figure 26. DSM -1 dB Cutoff .................................................................................................................... 38
Figure 27. QSM -1 dB Cutoff ..................................................................................................................... 38
CS5366
4 DS626F5
LIST OF TABLES
Table 1. Power Supply Pin Definitions ...................................................................................................... 19
Table 2. DIF1 and DIF0 Pin Settings ........................................................................................................ 23
Table 3. M1 and M0 Settings .................................................................................................................... 23
Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S ..................................................................... 25
Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S ..................................................................... 25
Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S ................................................................... 25
Table 7. Frequencies for 48 kHz Sample Rate using TDM ....................................................................... 25
Table 8. Frequencies for 48 kHz Sample Rate using TDM ....................................................................... 25
Table 9. Frequencies for 96 kHz Sample Rate using TDM ....................................................................... 26
Table 10. Frequencies for 96 kHz Sample Rate using TDM ..................................................................... 26
Table 11. Frequencies for 192 kHz Sample Rate using TDM ................................................................... 26
Table 12. Frequencies for 192 kHz Sample Rate using TDM ................................................................... 26
CS5366
DS626F5 5

1. PIN DESCRIPTION

DIF1/AD1/CDIN
REF_GND
AIN3+
SDOUT1/TDM
VLS
TSTO
SDOUT3/TDM
GND
SDOUT2
M0/SDA/CDOUT
AIN5-
AIN1+
AIN5+
AIN6-
AIN6+
AIN3-
GND
GND
GND
GND
VD
XTI
GND
VLC
DIF0/AD0/CS
AIN1-
M1/SCL/CCLK
LRCK/FS
SCLK
MCLK
XTO
OVFL
CLKMODE
MDIV
RST
6
2
4
8
10
1
3
5
7
9
11
12
13 14 15 16 17 18 19 20 21 22 23 24
31
35
33
29
27
36
34
32
30
28
26 25
48 47 46 45 44 43 42 41 40 39 38 37
CS5366
FILT+
AIN2-
VA
GND
GND
AIN2+
GND
VA
AIN4+
AIN4-
VQ
VX
GND
CS5366

Figure 1. CS5366 Pinout

6 DS626F5
Pin Name Pin # Pin Description
AIN2+, AIN2­AIN4+, AIN4­AIN3+, AIN3­AIN6+, AIN6­AIN5+, AIN5­AIN1+, AIN1-
GND
VA 4, 9 Analog Power (Input) - Positive power supply for the analog section
REF_GND 5
FILT+ 6 Positive Voltage Reference (Output) - Reference voltage for internal sampling circuits.
VQ 7 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
VX 20
XTI
XTO
MCLK 23
LRCK/FS 24
SCLK 25
TSTO 26 Test Out (Output) - Must be left unconnected.
SDOUT2 27 Serial Audio Data (
VLS 28 Serial Audio Interface Power - Positive power for the serial audio interface.
SDOUT1/TDM 30 Serial Audio Data (Output) - Channels 1,2, TDM.
SDOUT3/TDM
VD 33 Digital Power (Input) - Positive power supply for the digital section.
VLC 35 Control Port Interface Power - Positive power for the control port interface.
OVFL
RST
Stand-Alone Mode
CLKMODE 34
DIF1 DIF0
M1 M0
MDIV 42
1,2 11,12 13,14 43,44 45,46 47,48
10,15 16,17 18,19 29,32
Differential Analog (Inputs) - Audio signals are presented differently to the delta sigma modula- tors via the AIN+/- pins.
3,8
Ground (Input) - Ground reference. Must be connected to analog ground.
Reference Ground (Input) - For the internal sampling circuits. Must be connected to analog
ground.
Crystal Oscillator Power (Input) - Also powers control logic to enable or disable oscillator cir- cuits.
2122Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which may be
used to generate MCLK.
System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buffered MCLK Source (Output). When the oscillator function is not used, this pin acts as an input for the system master clock. In this case, the XTI and XTO pins must be tied low.
Serial Audio Channel Clock (Input/Output) In I²S mode Serial Audio Channel Select. When low, the odd channels are selected. In LJ mode Serial Audio Channel Select. When high, the odd channels are selected. In TDM Mode a frame sync signal. When high, it marks the beginning of a new frame of serial audio samples. In Slave Mode, this pin acts as an input pin.
Main timing clock for the Serial Audio Interface (Input/Output) - During Master Mode, this pin acts as an output, and during Slave Mode it acts as an input pin.
Output) - Channels 3,4
31 Serial Audio Data (Output) - Channels 5,6, TDM is complementary TDM data.
36 Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
41 Reset (Input) - The device enters a low power mode when low.
CLKMODE (Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the core device circuitry.
37
DIF1, DIF0 (Input) - Sets the serial audio interface format.
38
39
Mode Selection (Input) - Determines the operational mode of the device.
40
MCLK Divider (Input) - Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the core device circuitry.
CS5366
DS626F5 7
Control Port Mode
CLKMODE 34
AD1/CDIN 37
AD0/CS 38
SCL/CCLK 39
SDA/CDOUT 40
MDIV 42
CS5366
CLKMODE (Input) - This pin is ignored in Control Port Mode and the same functionality
is obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND when using the part in Control Port Mode.
I²C Format, AD1 (Input) - Forms the device address input AD[1]. SPI Format, CDIN (Input) - Becomes the input data pin.
I²C Format, AD0 (Input) - Forms the device address input AD[0]. SPI Format, CS
I²C Format, SCL (Input) - Serial clock for the serial control port. An external pull-up
resistor is required for I²C control port operation.
SPI Format, CCLK (Input) - Serial clock for the serial control port.
I²C Format SDA (Input/Output) - Acts as an input/output data pin. An external pull-up
resistor is required for I²C control port operation.
SPI Format CDOUT (Output) - Acts as an output only data pin.
MCLK Divider (Input) - This pin is ignored in Control Port Mode and the same function-
ality is obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND when using the part in Control Port Mode.
(Input) - Acts as the active low chip select input.
8 DS626F5

2. TYPICAL CONNECTION DIAGRAM

FILT+
D
+
VA V
+5V
5.1
1 F
+
SDOUT2
DIF0/AD0/CS
Power Down
and Mode
Settings
0.01
F
MODE0/SDA/CDOUT
MODE1/SCL/CCLK
REF_GND
VLC
F
AIN
+1
AIN
-
1
Channel 1 Analog
Input Buffer
AIN
+2
AIN
-
2
Channel 2 Analog
Input Buffer
AIN +3
AIN
-
3
Channel 3 Analog
Input Buffer
AIN +4
AIN
-
4
Channel 4 Analog
Input Buffer
AIN +5
AIN
-
5
Channel 5 Analog
Input Buffer
AIN
+6
AIN
-
6
Channel 6 Analog
Input Buffer
0.1 F
VQ
GND
220F
0.1 F
+
1F
GND
DIF1/AD1/CDIN
RST
OVFL
0.01
0.01F
+5V to 3.3V
1 F
+
A/D CONVERTER
CS5366
SDOUT1/TDM
SDOUT3/TDM
SCLK
MCLK
Timing Logic
and Clock
Audio Data
Processor
MDIV
CLKMODE
RESERVED
4,9
39
36 37 38 41
42
34
30
27
31
26
24
25
23
LRCK/FS
+5V to 1.8V
33
6
5
7
8
47
48
1
2
13
14
11
12
45
46
43
44
3, 8, 10, 15, 16,
17, 18, 19, 29, 32
35
40
VLS
F
0.01
+5V to 1.8V
28
XTI
XTO
21
22
+5V
VX
20
Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD.
CS5366
For analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low-cost single-ended-to-differen­tial solution is provided on the Customer Evaluation Board.

Figure 2. Typical Connection Diagram

DS626F5 9
CS5366

3. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V, all voltages with respect to 0 V.
Parameter Symbol Min Typ Max Unit
DC Power Supplies: Positive Analog
Positive Crystal
Positive Digital
Positive Serial Logic
Positive Control Logic
Ambient Operating Temperature (-CQZ)
(-DQZ)
VA VX VD
VLS
VLC
T
AC
T
AA
4.75
4.75
3.14
1.71
1.71
-40
-40
1
5.0
5.0
3.3
3.3
3.3
5.25 V
-
-
85
105
°C
1. TDM Quad-Speed Mode specified to operate correctly at VLS 3.14 V.

ABSOLUTE RATINGS

Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Transient currents up to ±100 mA on the analog input pins will not cause SCR latch-up.
Parameter Symbol Min Typ Max Units
DC Power Supplies: Positive Analog
Positive Crystal
Positive Digital
Positive Serial Logic
Positive Control Logic
Input Current I
Analog Input Voltage V
Digital Input Voltage V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
VA VX
VD VLS VLC
in
IN
IND
A
stg
-0.3 - +6.0 V
-10
-0.3
-50 +125
-65 +150
-
10 mA
VA+ 0.3
VL+0.3
C
V

SYSTEM CLOCKING

Parameter Symbol Min Typ Max Unit
Input Master Clock Frequency MCLK 0.512 55.05 MHz
Input Master Clock Duty Cycle t
clkhl
10 DS626F5
40 60 %

DC POWER

MCLK = 12.288 MHz; Master Mode. GND = 0 V.
Parameter Symbol Min Typ Max Unit
Power Supply Current VA = 5 V (Normal Operation) VX = 5 V
VD = 5 V
VD = 3.3 V
VLS, VLC = 5 V
VLS, VLC = 3.3 V
Power Supply Current VA = 5 V (Power-Down) (Note 1) VLS, VLC,VD = 5 V
Power Consumption (Normal Operation) All Supplies = 5 V
VA = 5 V, VD = VLS = VLC = 3.3 V
(Power-Down) (Note 1)
CS5366
I
A
I
X
I
D
I
D
I
L
I
L
I
A
I
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
76
4 60 37
6
3
50
500
730 532
2.75
84
8 66 40
8
5
-
-
830 609
-
mA mA mA mA mA mA
AA
mW mW mW mW
1. Power-Down is defined as RST
= LOW with all clocks and data lines held static at a valid logic level.

LOGIC LEVELS

Parameter Symbol Min Typ Max Units
High-Level Input Voltage %VLS/VLC V
Low-Level Input Voltage %VLS/VLC V
High-Level Output Voltage at 100 A load %VLS/VLC V
Low-Level Output Voltage at -100 A load %VLS/VLC V
SDA Low-Level Output Voltage at -2 mA load %VLC V
Current Sink
OVFL
Input Leakage Current logic pins only I
IH
IL
OH
OL
OL
in
70 - - %
--30%
85 - - %
--15%
--TBD%
-4 mA
-10 - 10 A

PSRR, VQ AND FILT+ CHARACTERISTICS

MCLK = 12.288 MHz; Master Mode. Valid with the recommended capacitor values on FILT+ and VQ as shown in the “Typical Connection Diagram”.
Parameter Symbol Min Typ Max Unit
Power Supply Rejection Ratio at (1 kHz) PSRR - 65 - dB
V
Nominal Voltage
Q
Output Impedance Maximum allowable DC current source/sink
Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink
-
-
VA/ 2
25 10
VA
4.4 10
V
-
-
k A
V k A
DS626F5 11
CS5366

ANALOG CHARACTERISTICS (COMMERCIAL)

Test Conditions (unless otherwise specified). VA = 5 V, VD = VLS = VLC 3.3 V, and TA = 25° C. Full-scale input sine wave. Measurement Bandwidth is 10 Hz to 20 kHz.
Parameter Symbol Min Typ Max Unit
Single-Speed Mode Fs = 48 kHz
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB
-60 dB
Double-Speed Mode Fs = 96 kHz
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB
-60 dB
40 kHz bandwidth -1dB
Quad-Speed Mode Fs = 192 kHz
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB
-60 dB
40 kHz bandwidth -1dB
THD+N -
THD+N -
THD+N -
Dynamic Performance for All Modes
Interchannel Isolation - 110 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error -5 - 5 %
Gain Drift -
Offset Error HPF enabled
HPF disabled
Analog Input Characteristics
Full-scale Differential Input Voltage 1.07*VA 1.13*VA 1.19*VA Vpp
Input Impedance (Differential) - 250 - k
Common Mode Rejection Ratio CMRR - 82 - dB
108 105
108 105
-
108 105
-
0
-
114
111
-105
-91
-51
114
111
108
-105
-91
-51
-102
114
111
108
-105
-91
-51
-102
-
-
-99
-
-45
-dB
-99
-
-45
-
-dB
-99
-
-45
-
dB
dB
dB
dB
100 - ppm/°C
-
-
-
100
LSB
12 DS626F5
CS5366

ANALOG PERFORMANCE (AUTOMOTIVE)

Test Conditions (unless otherwise specified). VA = 5.25 to 4.75 V, VD = 5.25 to 3.14 V, VLS = VLC = 5.25 to 1.71 V and T
Single-Speed Mode Fs = 48 kHz
Dynamic Range A-weighted
Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB
Double-Speed Mode Fs = 96 kHz
Dynamic Range A-weighted
Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB
Quad-Speed Mode Fs = 192 kHz
Dynamic Range A-weighted
Total Harmonic Distortion + Noise -1 dB referred to typical full scale -20 dB
Dynamic Performance for All Modes
Interchannel Isolation - 110 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error -7 - 7 %
Gain Drift -
Offset Error HPF enabled
Analog Input Characteristics
Full-scale Input Voltage 1.02*VA 1.13*VA 1.24*VA Vpp
Input Impedance (Differential) 250 - k
Common Mode Rejection Ratio CMRR - 82 - dB
= -40° to +85° C. Full-scale input sine wave. Measurement Bandwidth is 10 Hz to 20 kHz.
A
Parameter Symbol Min Typ Max Unit
unweighted
-60 dB
unweighted
40 kHz bandwidth unweighted
-60 dB
40 kHz bandwidth -1 dB
unweighted
40 kHz bandwidth unweighted
-60 dB
40 kHz bandwidth -1 dB
106 103
THD+N -
106 103
-
THD+N -
106 103
-
THD+N -
114 111
-105
-91
-51
114 111 108
-105
-91
-51
-102
114 111 108
-105
-91
-51
-102
100 - ppm/°C
HPF disabled
0
-
-
-
-dB
-97
-
-45
-dB
-97
-
-45
-
-dB
-97
-
-45
-
-
100
dB
dB
dB
LSB
DS626F5 13
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